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7733f6c3 PL |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Cadence USBSS DRD Driver - gadget side. | |
4 | * | |
5 | * Copyright (C) 2018-2019 Cadence Design Systems. | |
6 | * Copyright (C) 2017-2018 NXP | |
7 | * | |
8 | * Authors: Pawel Jez <pjez@cadence.com>, | |
9 | * Pawel Laszczak <pawell@cadence.com> | |
10 | * Peter Chen <peter.chen@nxp.com> | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Work around 1: | |
15 | * At some situations, the controller may get stale data address in TRB | |
16 | * at below sequences: | |
17 | * 1. Controller read TRB includes data address | |
18 | * 2. Software updates TRBs includes data address and Cycle bit | |
19 | * 3. Controller read TRB which includes Cycle bit | |
20 | * 4. DMA run with stale data address | |
21 | * | |
22 | * To fix this problem, driver needs to make the first TRB in TD as invalid. | |
23 | * After preparing all TRBs driver needs to check the position of DMA and | |
24 | * if the DMA point to the first just added TRB and doorbell is 1, | |
25 | * then driver must defer making this TRB as valid. This TRB will be make | |
26 | * as valid during adding next TRB only if DMA is stopped or at TRBERR | |
27 | * interrupt. | |
28 | * | |
29 | * Issue has been fixed in DEV_VER_V3 version of controller. | |
30 | * | |
6bbf87a1 PL |
31 | * Work around 2: |
32 | * Controller for OUT endpoints has shared on-chip buffers for all incoming | |
33 | * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA | |
34 | * in correct order. If the first packet in the buffer will not be handled, | |
35 | * then the following packets directed for other endpoints and functions | |
36 | * will be blocked. | |
37 | * Additionally the packets directed to one endpoint can block entire on-chip | |
38 | * buffers. In this case transfer to other endpoints also will blocked. | |
39 | * | |
40 | * To resolve this issue after raising the descriptor missing interrupt | |
41 | * driver prepares internal usb_request object and use it to arm DMA transfer. | |
42 | * | |
43 | * The problematic situation was observed in case when endpoint has been enabled | |
44 | * but no usb_request were queued. Driver try detects such endpoints and will | |
45 | * use this workaround only for these endpoint. | |
46 | * | |
47 | * Driver use limited number of buffer. This number can be set by macro | |
48 | * CDNS3_WA2_NUM_BUFFERS. | |
49 | * | |
50 | * Such blocking situation was observed on ACM gadget. For this function | |
51 | * host send OUT data packet but ACM function is not prepared for this packet. | |
52 | * It's cause that buffer placed in on chip memory block transfer to other | |
53 | * endpoints. | |
54 | * | |
55 | * Issue has been fixed in DEV_VER_V2 version of controller. | |
56 | * | |
7733f6c3 PL |
57 | */ |
58 | ||
59 | #include <linux/dma-mapping.h> | |
60 | #include <linux/usb/gadget.h> | |
61 | #include <linux/module.h> | |
62 | #include <linux/iopoll.h> | |
63 | ||
64 | #include "core.h" | |
65 | #include "gadget-export.h" | |
66 | #include "gadget.h" | |
67 | #include "trace.h" | |
68 | #include "drd.h" | |
69 | ||
70 | static int __cdns3_gadget_ep_queue(struct usb_ep *ep, | |
71 | struct usb_request *request, | |
72 | gfp_t gfp_flags); | |
73 | ||
54c4c69f JP |
74 | static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, |
75 | struct usb_request *request); | |
76 | ||
77 | static int cdns3_ep_run_stream_transfer(struct cdns3_endpoint *priv_ep, | |
78 | struct usb_request *request); | |
79 | ||
80 | /** | |
81 | * cdns3_clear_register_bit - clear bit in given register. | |
82 | * @ptr: address of device controller register to be read and changed | |
83 | * @mask: bits requested to clar | |
84 | */ | |
e9010320 | 85 | static void cdns3_clear_register_bit(void __iomem *ptr, u32 mask) |
54c4c69f JP |
86 | { |
87 | mask = readl(ptr) & ~mask; | |
88 | writel(mask, ptr); | |
89 | } | |
90 | ||
7733f6c3 PL |
91 | /** |
92 | * cdns3_set_register_bit - set bit in given register. | |
93 | * @ptr: address of device controller register to be read and changed | |
94 | * @mask: bits requested to set | |
95 | */ | |
96 | void cdns3_set_register_bit(void __iomem *ptr, u32 mask) | |
97 | { | |
98 | mask = readl(ptr) | mask; | |
99 | writel(mask, ptr); | |
100 | } | |
101 | ||
102 | /** | |
103 | * cdns3_ep_addr_to_index - Macro converts endpoint address to | |
104 | * index of endpoint object in cdns3_device.eps[] container | |
105 | * @ep_addr: endpoint address for which endpoint object is required | |
106 | * | |
107 | */ | |
108 | u8 cdns3_ep_addr_to_index(u8 ep_addr) | |
109 | { | |
110 | return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0)); | |
111 | } | |
112 | ||
113 | static int cdns3_get_dma_pos(struct cdns3_device *priv_dev, | |
114 | struct cdns3_endpoint *priv_ep) | |
115 | { | |
116 | int dma_index; | |
117 | ||
118 | dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma; | |
119 | ||
120 | return dma_index / TRB_SIZE; | |
121 | } | |
122 | ||
123 | /** | |
124 | * cdns3_next_request - returns next request from list | |
125 | * @list: list containing requests | |
126 | * | |
127 | * Returns request or NULL if no requests in list | |
128 | */ | |
129 | struct usb_request *cdns3_next_request(struct list_head *list) | |
130 | { | |
131 | return list_first_entry_or_null(list, struct usb_request, list); | |
132 | } | |
133 | ||
134 | /** | |
135 | * cdns3_next_align_buf - returns next buffer from list | |
136 | * @list: list containing buffers | |
137 | * | |
138 | * Returns buffer or NULL if no buffers in list | |
139 | */ | |
e9010320 | 140 | static struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list) |
7733f6c3 PL |
141 | { |
142 | return list_first_entry_or_null(list, struct cdns3_aligned_buf, list); | |
143 | } | |
144 | ||
6bbf87a1 PL |
145 | /** |
146 | * cdns3_next_priv_request - returns next request from list | |
147 | * @list: list containing requests | |
148 | * | |
149 | * Returns request or NULL if no requests in list | |
150 | */ | |
e9010320 | 151 | static struct cdns3_request *cdns3_next_priv_request(struct list_head *list) |
6bbf87a1 PL |
152 | { |
153 | return list_first_entry_or_null(list, struct cdns3_request, list); | |
154 | } | |
155 | ||
7733f6c3 PL |
156 | /** |
157 | * select_ep - selects endpoint | |
158 | * @priv_dev: extended gadget object | |
159 | * @ep: endpoint address | |
160 | */ | |
161 | void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep) | |
162 | { | |
163 | if (priv_dev->selected_ep == ep) | |
164 | return; | |
165 | ||
166 | priv_dev->selected_ep = ep; | |
167 | writel(ep, &priv_dev->regs->ep_sel); | |
168 | } | |
169 | ||
54c4c69f JP |
170 | /** |
171 | * cdns3_get_tdl - gets current tdl for selected endpoint. | |
172 | * @priv_dev: extended gadget object | |
173 | * | |
174 | * Before calling this function the appropriate endpoint must | |
175 | * be selected by means of cdns3_select_ep function. | |
176 | */ | |
177 | static int cdns3_get_tdl(struct cdns3_device *priv_dev) | |
178 | { | |
179 | if (priv_dev->dev_ver < DEV_VER_V3) | |
180 | return EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd)); | |
181 | else | |
182 | return readl(&priv_dev->regs->ep_tdl); | |
183 | } | |
184 | ||
7733f6c3 PL |
185 | dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, |
186 | struct cdns3_trb *trb) | |
187 | { | |
188 | u32 offset = (char *)trb - (char *)priv_ep->trb_pool; | |
189 | ||
190 | return priv_ep->trb_pool_dma + offset; | |
191 | } | |
192 | ||
e9010320 | 193 | static int cdns3_ring_size(struct cdns3_endpoint *priv_ep) |
7733f6c3 PL |
194 | { |
195 | switch (priv_ep->type) { | |
196 | case USB_ENDPOINT_XFER_ISOC: | |
197 | return TRB_ISO_RING_SIZE; | |
198 | case USB_ENDPOINT_XFER_CONTROL: | |
199 | return TRB_CTRL_RING_SIZE; | |
200 | default: | |
54c4c69f JP |
201 | if (priv_ep->use_streams) |
202 | return TRB_STREAM_RING_SIZE; | |
203 | else | |
204 | return TRB_RING_SIZE; | |
205 | } | |
206 | } | |
207 | ||
208 | static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep) | |
209 | { | |
210 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
211 | ||
212 | if (priv_ep->trb_pool) { | |
213 | dma_free_coherent(priv_dev->sysdev, | |
214 | cdns3_ring_size(priv_ep), | |
215 | priv_ep->trb_pool, priv_ep->trb_pool_dma); | |
216 | priv_ep->trb_pool = NULL; | |
7733f6c3 PL |
217 | } |
218 | } | |
219 | ||
220 | /** | |
221 | * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint | |
222 | * @priv_ep: endpoint object | |
223 | * | |
224 | * Function will return 0 on success or -ENOMEM on allocation error | |
225 | */ | |
226 | int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep) | |
227 | { | |
228 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
229 | int ring_size = cdns3_ring_size(priv_ep); | |
54c4c69f | 230 | int num_trbs = ring_size / TRB_SIZE; |
7733f6c3 PL |
231 | struct cdns3_trb *link_trb; |
232 | ||
54c4c69f JP |
233 | if (priv_ep->trb_pool && priv_ep->alloc_ring_size < ring_size) |
234 | cdns3_free_trb_pool(priv_ep); | |
235 | ||
7733f6c3 PL |
236 | if (!priv_ep->trb_pool) { |
237 | priv_ep->trb_pool = dma_alloc_coherent(priv_dev->sysdev, | |
238 | ring_size, | |
239 | &priv_ep->trb_pool_dma, | |
240 | GFP_DMA32 | GFP_ATOMIC); | |
241 | if (!priv_ep->trb_pool) | |
242 | return -ENOMEM; | |
54c4c69f JP |
243 | |
244 | priv_ep->alloc_ring_size = ring_size; | |
7733f6c3 PL |
245 | } |
246 | ||
95f5acfc PC |
247 | memset(priv_ep->trb_pool, 0, ring_size); |
248 | ||
54c4c69f JP |
249 | priv_ep->num_trbs = num_trbs; |
250 | ||
7733f6c3 PL |
251 | if (!priv_ep->num) |
252 | return 0; | |
253 | ||
54c4c69f | 254 | /* Initialize the last TRB as Link TRB */ |
7733f6c3 | 255 | link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1)); |
7733f6c3 | 256 | |
54c4c69f JP |
257 | if (priv_ep->use_streams) { |
258 | /* | |
259 | * For stream capable endpoints driver use single correct TRB. | |
260 | * The last trb has zeroed cycle bit | |
261 | */ | |
262 | link_trb->control = 0; | |
263 | } else { | |
8dafb3c0 PC |
264 | link_trb->buffer = cpu_to_le32(TRB_BUFFER(priv_ep->trb_pool_dma)); |
265 | link_trb->control = cpu_to_le32(TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE); | |
7733f6c3 | 266 | } |
54c4c69f | 267 | return 0; |
7733f6c3 PL |
268 | } |
269 | ||
270 | /** | |
271 | * cdns3_ep_stall_flush - Stalls and flushes selected endpoint | |
272 | * @priv_ep: endpoint object | |
273 | * | |
274 | * Endpoint must be selected before call to this function | |
275 | */ | |
276 | static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep) | |
277 | { | |
278 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
279 | int val; | |
280 | ||
281 | trace_cdns3_halt(priv_ep, 1, 1); | |
282 | ||
283 | writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL, | |
284 | &priv_dev->regs->ep_cmd); | |
285 | ||
286 | /* wait for DFLUSH cleared */ | |
287 | readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, | |
288 | !(val & EP_CMD_DFLUSH), 1, 1000); | |
289 | priv_ep->flags |= EP_STALLED; | |
290 | priv_ep->flags &= ~EP_STALL_PENDING; | |
291 | } | |
292 | ||
293 | /** | |
294 | * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller. | |
295 | * @priv_dev: extended gadget object | |
296 | */ | |
297 | void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev) | |
298 | { | |
299 | writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf); | |
300 | ||
301 | cdns3_allow_enable_l1(priv_dev, 0); | |
302 | priv_dev->hw_configured_flag = 0; | |
303 | priv_dev->onchip_used_size = 0; | |
304 | priv_dev->out_mem_is_allocated = 0; | |
305 | priv_dev->wait_for_setup = 0; | |
54c4c69f | 306 | priv_dev->using_streams = 0; |
7733f6c3 PL |
307 | } |
308 | ||
309 | /** | |
310 | * cdns3_ep_inc_trb - increment a trb index. | |
311 | * @index: Pointer to the TRB index to increment. | |
312 | * @cs: Cycle state | |
313 | * @trb_in_seg: number of TRBs in segment | |
314 | * | |
315 | * The index should never point to the link TRB. After incrementing, | |
316 | * if it is point to the link TRB, wrap around to the beginning and revert | |
317 | * cycle state bit The | |
318 | * link TRB is always at the last TRB entry. | |
319 | */ | |
320 | static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg) | |
321 | { | |
322 | (*index)++; | |
323 | if (*index == (trb_in_seg - 1)) { | |
324 | *index = 0; | |
325 | *cs ^= 1; | |
326 | } | |
327 | } | |
328 | ||
329 | /** | |
330 | * cdns3_ep_inc_enq - increment endpoint's enqueue pointer | |
331 | * @priv_ep: The endpoint whose enqueue pointer we're incrementing | |
332 | */ | |
333 | static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep) | |
334 | { | |
335 | priv_ep->free_trbs--; | |
336 | cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs); | |
337 | } | |
338 | ||
339 | /** | |
340 | * cdns3_ep_inc_deq - increment endpoint's dequeue pointer | |
341 | * @priv_ep: The endpoint whose dequeue pointer we're incrementing | |
342 | */ | |
343 | static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep) | |
344 | { | |
345 | priv_ep->free_trbs++; | |
346 | cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs); | |
347 | } | |
348 | ||
e9010320 | 349 | static void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req) |
7733f6c3 PL |
350 | { |
351 | struct cdns3_endpoint *priv_ep = priv_req->priv_ep; | |
352 | int current_trb = priv_req->start_trb; | |
353 | ||
354 | while (current_trb != priv_req->end_trb) { | |
355 | cdns3_ep_inc_deq(priv_ep); | |
356 | current_trb = priv_ep->dequeue; | |
357 | } | |
358 | ||
359 | cdns3_ep_inc_deq(priv_ep); | |
360 | } | |
361 | ||
362 | /** | |
363 | * cdns3_allow_enable_l1 - enable/disable permits to transition to L1. | |
364 | * @priv_dev: Extended gadget object | |
365 | * @enable: Enable/disable permit to transition to L1. | |
366 | * | |
367 | * If bit USB_CONF_L1EN is set and device receive Extended Token packet, | |
368 | * then controller answer with ACK handshake. | |
369 | * If bit USB_CONF_L1DS is set and device receive Extended Token packet, | |
370 | * then controller answer with NYET handshake. | |
371 | */ | |
372 | void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable) | |
373 | { | |
374 | if (enable) | |
375 | writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf); | |
376 | else | |
377 | writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf); | |
378 | } | |
379 | ||
380 | enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev) | |
381 | { | |
382 | u32 reg; | |
383 | ||
384 | reg = readl(&priv_dev->regs->usb_sts); | |
385 | ||
386 | if (DEV_SUPERSPEED(reg)) | |
387 | return USB_SPEED_SUPER; | |
388 | else if (DEV_HIGHSPEED(reg)) | |
389 | return USB_SPEED_HIGH; | |
390 | else if (DEV_FULLSPEED(reg)) | |
391 | return USB_SPEED_FULL; | |
392 | else if (DEV_LOWSPEED(reg)) | |
393 | return USB_SPEED_LOW; | |
394 | return USB_SPEED_UNKNOWN; | |
395 | } | |
396 | ||
397 | /** | |
398 | * cdns3_start_all_request - add to ring all request not started | |
399 | * @priv_dev: Extended gadget object | |
400 | * @priv_ep: The endpoint for whom request will be started. | |
401 | * | |
402 | * Returns return ENOMEM if transfer ring i not enough TRBs to start | |
403 | * all requests. | |
404 | */ | |
405 | static int cdns3_start_all_request(struct cdns3_device *priv_dev, | |
406 | struct cdns3_endpoint *priv_ep) | |
407 | { | |
7733f6c3 PL |
408 | struct usb_request *request; |
409 | int ret = 0; | |
54c4c69f JP |
410 | u8 pending_empty = list_empty(&priv_ep->pending_req_list); |
411 | ||
412 | /* | |
413 | * If the last pending transfer is INTERNAL | |
414 | * OR streams are enabled for this endpoint | |
415 | * do NOT start new transfer till the last one is pending | |
416 | */ | |
417 | if (!pending_empty) { | |
418 | struct cdns3_request *priv_req; | |
419 | ||
420 | request = cdns3_next_request(&priv_ep->pending_req_list); | |
421 | priv_req = to_cdns3_request(request); | |
422 | if ((priv_req->flags & REQUEST_INTERNAL) || | |
423 | (priv_ep->flags & EP_TDLCHK_EN) || | |
424 | priv_ep->use_streams) { | |
b3a5ce87 | 425 | dev_dbg(priv_dev->dev, "Blocking external request\n"); |
54c4c69f JP |
426 | return ret; |
427 | } | |
428 | } | |
7733f6c3 PL |
429 | |
430 | while (!list_empty(&priv_ep->deferred_req_list)) { | |
431 | request = cdns3_next_request(&priv_ep->deferred_req_list); | |
7733f6c3 | 432 | |
54c4c69f JP |
433 | if (!priv_ep->use_streams) { |
434 | ret = cdns3_ep_run_transfer(priv_ep, request); | |
435 | } else { | |
436 | priv_ep->stream_sg_idx = 0; | |
437 | ret = cdns3_ep_run_stream_transfer(priv_ep, request); | |
438 | } | |
7733f6c3 PL |
439 | if (ret) |
440 | return ret; | |
441 | ||
442 | list_del(&request->list); | |
443 | list_add_tail(&request->list, | |
444 | &priv_ep->pending_req_list); | |
54c4c69f JP |
445 | if (request->stream_id != 0 || (priv_ep->flags & EP_TDLCHK_EN)) |
446 | break; | |
7733f6c3 PL |
447 | } |
448 | ||
449 | priv_ep->flags &= ~EP_RING_FULL; | |
450 | return ret; | |
451 | } | |
452 | ||
6bbf87a1 PL |
453 | /* |
454 | * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set | |
455 | * driver try to detect whether endpoint need additional internal | |
456 | * buffer for unblocking on-chip FIFO buffer. This flag will be cleared | |
457 | * if before first DESCMISS interrupt the DMA will be armed. | |
458 | */ | |
54c4c69f | 459 | #define cdns3_wa2_enable_detection(priv_dev, priv_ep, reg) do { \ |
6bbf87a1 PL |
460 | if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \ |
461 | priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \ | |
462 | (reg) |= EP_STS_EN_DESCMISEN; \ | |
463 | } } while (0) | |
464 | ||
465 | /** | |
466 | * cdns3_wa2_descmiss_copy_data copy data from internal requests to | |
467 | * request queued by class driver. | |
468 | * @priv_ep: extended endpoint object | |
469 | * @request: request object | |
470 | */ | |
471 | static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep, | |
472 | struct usb_request *request) | |
473 | { | |
474 | struct usb_request *descmiss_req; | |
475 | struct cdns3_request *descmiss_priv_req; | |
476 | ||
477 | while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { | |
478 | int chunk_end; | |
479 | int length; | |
480 | ||
481 | descmiss_priv_req = | |
482 | cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); | |
483 | descmiss_req = &descmiss_priv_req->request; | |
484 | ||
485 | /* driver can't touch pending request */ | |
486 | if (descmiss_priv_req->flags & REQUEST_PENDING) | |
487 | break; | |
488 | ||
489 | chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH; | |
490 | length = request->actual + descmiss_req->actual; | |
491 | ||
492 | request->status = descmiss_req->status; | |
493 | ||
494 | if (length <= request->length) { | |
495 | memcpy(&((u8 *)request->buf)[request->actual], | |
496 | descmiss_req->buf, | |
497 | descmiss_req->actual); | |
498 | request->actual = length; | |
499 | } else { | |
500 | /* It should never occures */ | |
501 | request->status = -ENOMEM; | |
502 | } | |
503 | ||
504 | list_del_init(&descmiss_priv_req->list); | |
505 | ||
506 | kfree(descmiss_req->buf); | |
507 | cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req); | |
508 | --priv_ep->wa2_counter; | |
509 | ||
510 | if (!chunk_end) | |
511 | break; | |
512 | } | |
513 | } | |
514 | ||
e9010320 | 515 | static struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev, |
e2e77a94 | 516 | struct cdns3_endpoint *priv_ep, |
517 | struct cdns3_request *priv_req) | |
6bbf87a1 PL |
518 | { |
519 | if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN && | |
520 | priv_req->flags & REQUEST_INTERNAL) { | |
521 | struct usb_request *req; | |
522 | ||
523 | req = cdns3_next_request(&priv_ep->deferred_req_list); | |
524 | ||
525 | priv_ep->descmis_req = NULL; | |
526 | ||
527 | if (!req) | |
528 | return NULL; | |
529 | ||
54c4c69f JP |
530 | /* unmap the gadget request before copying data */ |
531 | usb_gadget_unmap_request_by_dev(priv_dev->sysdev, req, | |
532 | priv_ep->dir); | |
533 | ||
6bbf87a1 PL |
534 | cdns3_wa2_descmiss_copy_data(priv_ep, req); |
535 | if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) && | |
536 | req->length != req->actual) { | |
537 | /* wait for next part of transfer */ | |
54c4c69f JP |
538 | /* re-map the gadget request buffer*/ |
539 | usb_gadget_map_request_by_dev(priv_dev->sysdev, req, | |
540 | usb_endpoint_dir_in(priv_ep->endpoint.desc)); | |
6bbf87a1 PL |
541 | return NULL; |
542 | } | |
543 | ||
544 | if (req->status == -EINPROGRESS) | |
545 | req->status = 0; | |
546 | ||
547 | list_del_init(&req->list); | |
548 | cdns3_start_all_request(priv_dev, priv_ep); | |
549 | return req; | |
550 | } | |
551 | ||
552 | return &priv_req->request; | |
553 | } | |
554 | ||
e9010320 | 555 | static int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev, |
e2e77a94 | 556 | struct cdns3_endpoint *priv_ep, |
557 | struct cdns3_request *priv_req) | |
6bbf87a1 PL |
558 | { |
559 | int deferred = 0; | |
560 | ||
561 | /* | |
562 | * If transfer was queued before DESCMISS appear than we | |
563 | * can disable handling of DESCMISS interrupt. Driver assumes that it | |
564 | * can disable special treatment for this endpoint. | |
565 | */ | |
566 | if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) { | |
567 | u32 reg; | |
568 | ||
569 | cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir); | |
570 | priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET; | |
571 | reg = readl(&priv_dev->regs->ep_sts_en); | |
572 | reg &= ~EP_STS_EN_DESCMISEN; | |
573 | trace_cdns3_wa2(priv_ep, "workaround disabled\n"); | |
574 | writel(reg, &priv_dev->regs->ep_sts_en); | |
575 | } | |
576 | ||
577 | if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) { | |
578 | u8 pending_empty = list_empty(&priv_ep->pending_req_list); | |
579 | u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list); | |
580 | ||
581 | /* | |
582 | * DESCMISS transfer has been finished, so data will be | |
583 | * directly copied from internal allocated usb_request | |
584 | * objects. | |
585 | */ | |
586 | if (pending_empty && !descmiss_empty && | |
587 | !(priv_req->flags & REQUEST_INTERNAL)) { | |
588 | cdns3_wa2_descmiss_copy_data(priv_ep, | |
589 | &priv_req->request); | |
590 | ||
591 | trace_cdns3_wa2(priv_ep, "get internal stored data"); | |
592 | ||
593 | list_add_tail(&priv_req->request.list, | |
594 | &priv_ep->pending_req_list); | |
595 | cdns3_gadget_giveback(priv_ep, priv_req, | |
596 | priv_req->request.status); | |
597 | ||
598 | /* | |
599 | * Intentionally driver returns positive value as | |
600 | * correct value. It informs that transfer has | |
601 | * been finished. | |
602 | */ | |
603 | return EINPROGRESS; | |
604 | } | |
605 | ||
606 | /* | |
607 | * Driver will wait for completion DESCMISS transfer, | |
608 | * before starts new, not DESCMISS transfer. | |
609 | */ | |
610 | if (!pending_empty && !descmiss_empty) { | |
611 | trace_cdns3_wa2(priv_ep, "wait for pending transfer\n"); | |
612 | deferred = 1; | |
613 | } | |
614 | ||
615 | if (priv_req->flags & REQUEST_INTERNAL) | |
616 | list_add_tail(&priv_req->list, | |
617 | &priv_ep->wa2_descmiss_req_list); | |
618 | } | |
619 | ||
620 | return deferred; | |
621 | } | |
622 | ||
623 | static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep) | |
624 | { | |
625 | struct cdns3_request *priv_req; | |
626 | ||
627 | while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { | |
628 | u8 chain; | |
629 | ||
630 | priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); | |
631 | chain = !!(priv_req->flags & REQUEST_INTERNAL_CH); | |
632 | ||
633 | trace_cdns3_wa2(priv_ep, "removes eldest request"); | |
634 | ||
635 | kfree(priv_req->request.buf); | |
636 | cdns3_gadget_ep_free_request(&priv_ep->endpoint, | |
637 | &priv_req->request); | |
638 | list_del_init(&priv_req->list); | |
639 | --priv_ep->wa2_counter; | |
640 | ||
641 | if (!chain) | |
642 | break; | |
643 | } | |
644 | } | |
645 | ||
646 | /** | |
647 | * cdns3_wa2_descmissing_packet - handles descriptor missing event. | |
4a35aa6d | 648 | * @priv_ep: extended gadget object |
6bbf87a1 PL |
649 | * |
650 | * This function is used only for WA2. For more information see Work around 2 | |
651 | * description. | |
652 | */ | |
653 | static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep) | |
654 | { | |
655 | struct cdns3_request *priv_req; | |
656 | struct usb_request *request; | |
54c4c69f JP |
657 | u8 pending_empty = list_empty(&priv_ep->pending_req_list); |
658 | ||
659 | /* check for pending transfer */ | |
660 | if (!pending_empty) { | |
661 | trace_cdns3_wa2(priv_ep, "Ignoring Descriptor missing IRQ\n"); | |
662 | return; | |
663 | } | |
6bbf87a1 PL |
664 | |
665 | if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) { | |
666 | priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET; | |
667 | priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN; | |
668 | } | |
669 | ||
670 | trace_cdns3_wa2(priv_ep, "Description Missing detected\n"); | |
671 | ||
54c4c69f JP |
672 | if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS) { |
673 | trace_cdns3_wa2(priv_ep, "WA2 overflow\n"); | |
6bbf87a1 | 674 | cdns3_wa2_remove_old_request(priv_ep); |
54c4c69f | 675 | } |
6bbf87a1 PL |
676 | |
677 | request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint, | |
678 | GFP_ATOMIC); | |
679 | if (!request) | |
680 | goto err; | |
681 | ||
682 | priv_req = to_cdns3_request(request); | |
683 | priv_req->flags |= REQUEST_INTERNAL; | |
684 | ||
685 | /* if this field is still assigned it indicate that transfer related | |
686 | * with this request has not been finished yet. Driver in this | |
687 | * case simply allocate next request and assign flag REQUEST_INTERNAL_CH | |
688 | * flag to previous one. It will indicate that current request is | |
689 | * part of the previous one. | |
690 | */ | |
691 | if (priv_ep->descmis_req) | |
692 | priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH; | |
693 | ||
694 | priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE, | |
695 | GFP_ATOMIC); | |
696 | priv_ep->wa2_counter++; | |
697 | ||
698 | if (!priv_req->request.buf) { | |
699 | cdns3_gadget_ep_free_request(&priv_ep->endpoint, request); | |
700 | goto err; | |
701 | } | |
702 | ||
703 | priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE; | |
704 | priv_ep->descmis_req = priv_req; | |
705 | ||
706 | __cdns3_gadget_ep_queue(&priv_ep->endpoint, | |
707 | &priv_ep->descmis_req->request, | |
708 | GFP_ATOMIC); | |
709 | ||
710 | return; | |
711 | ||
712 | err: | |
713 | dev_err(priv_ep->cdns3_dev->dev, | |
714 | "Failed: No sufficient memory for DESCMIS\n"); | |
715 | } | |
716 | ||
54c4c69f JP |
717 | static void cdns3_wa2_reset_tdl(struct cdns3_device *priv_dev) |
718 | { | |
719 | u16 tdl = EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd)); | |
720 | ||
721 | if (tdl) { | |
722 | u16 reset_val = EP_CMD_TDL_MAX + 1 - tdl; | |
723 | ||
724 | writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL, | |
725 | &priv_dev->regs->ep_cmd); | |
726 | } | |
727 | } | |
728 | ||
729 | static void cdns3_wa2_check_outq_status(struct cdns3_device *priv_dev) | |
730 | { | |
731 | u32 ep_sts_reg; | |
732 | ||
733 | /* select EP0-out */ | |
734 | cdns3_select_ep(priv_dev, 0); | |
735 | ||
736 | ep_sts_reg = readl(&priv_dev->regs->ep_sts); | |
737 | ||
738 | if (EP_STS_OUTQ_VAL(ep_sts_reg)) { | |
739 | u32 outq_ep_num = EP_STS_OUTQ_NO(ep_sts_reg); | |
740 | struct cdns3_endpoint *outq_ep = priv_dev->eps[outq_ep_num]; | |
741 | ||
742 | if ((outq_ep->flags & EP_ENABLED) && !(outq_ep->use_streams) && | |
743 | outq_ep->type != USB_ENDPOINT_XFER_ISOC && outq_ep_num) { | |
744 | u8 pending_empty = list_empty(&outq_ep->pending_req_list); | |
745 | ||
746 | if ((outq_ep->flags & EP_QUIRK_EXTRA_BUF_DET) || | |
747 | (outq_ep->flags & EP_QUIRK_EXTRA_BUF_EN) || | |
748 | !pending_empty) { | |
749 | } else { | |
750 | u32 ep_sts_en_reg; | |
751 | u32 ep_cmd_reg; | |
752 | ||
753 | cdns3_select_ep(priv_dev, outq_ep->num | | |
754 | outq_ep->dir); | |
755 | ep_sts_en_reg = readl(&priv_dev->regs->ep_sts_en); | |
756 | ep_cmd_reg = readl(&priv_dev->regs->ep_cmd); | |
757 | ||
758 | outq_ep->flags |= EP_TDLCHK_EN; | |
759 | cdns3_set_register_bit(&priv_dev->regs->ep_cfg, | |
760 | EP_CFG_TDL_CHK); | |
761 | ||
762 | cdns3_wa2_enable_detection(priv_dev, outq_ep, | |
763 | ep_sts_en_reg); | |
764 | writel(ep_sts_en_reg, | |
765 | &priv_dev->regs->ep_sts_en); | |
766 | /* reset tdl value to zero */ | |
767 | cdns3_wa2_reset_tdl(priv_dev); | |
768 | /* | |
769 | * Memory barrier - Reset tdl before ringing the | |
770 | * doorbell. | |
771 | */ | |
772 | wmb(); | |
773 | if (EP_CMD_DRDY & ep_cmd_reg) { | |
774 | trace_cdns3_wa2(outq_ep, "Enabling WA2 skipping doorbell\n"); | |
775 | ||
776 | } else { | |
777 | trace_cdns3_wa2(outq_ep, "Enabling WA2 ringing doorbell\n"); | |
778 | /* | |
779 | * ring doorbell to generate DESCMIS irq | |
780 | */ | |
781 | writel(EP_CMD_DRDY, | |
782 | &priv_dev->regs->ep_cmd); | |
783 | } | |
784 | } | |
785 | } | |
786 | } | |
787 | } | |
788 | ||
7733f6c3 PL |
789 | /** |
790 | * cdns3_gadget_giveback - call struct usb_request's ->complete callback | |
791 | * @priv_ep: The endpoint to whom the request belongs to | |
792 | * @priv_req: The request we're giving back | |
793 | * @status: completion code for the request | |
794 | * | |
795 | * Must be called with controller's lock held and interrupts disabled. This | |
796 | * function will unmap @req and call its ->complete() callback to notify upper | |
797 | * layers that it has completed. | |
798 | */ | |
799 | void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, | |
800 | struct cdns3_request *priv_req, | |
801 | int status) | |
802 | { | |
803 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
804 | struct usb_request *request = &priv_req->request; | |
805 | ||
806 | list_del_init(&request->list); | |
807 | ||
808 | if (request->status == -EINPROGRESS) | |
809 | request->status = status; | |
810 | ||
811 | usb_gadget_unmap_request_by_dev(priv_dev->sysdev, request, | |
812 | priv_ep->dir); | |
813 | ||
814 | if ((priv_req->flags & REQUEST_UNALIGNED) && | |
815 | priv_ep->dir == USB_DIR_OUT && !request->status) | |
816 | memcpy(request->buf, priv_req->aligned_buf->buf, | |
817 | request->length); | |
818 | ||
819 | priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED); | |
820 | trace_cdns3_gadget_giveback(priv_req); | |
821 | ||
6bbf87a1 PL |
822 | if (priv_dev->dev_ver < DEV_VER_V2) { |
823 | request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep, | |
824 | priv_req); | |
825 | if (!request) | |
826 | return; | |
827 | } | |
828 | ||
7733f6c3 PL |
829 | if (request->complete) { |
830 | spin_unlock(&priv_dev->lock); | |
831 | usb_gadget_giveback_request(&priv_ep->endpoint, | |
832 | request); | |
833 | spin_lock(&priv_dev->lock); | |
834 | } | |
835 | ||
836 | if (request->buf == priv_dev->zlp_buf) | |
837 | cdns3_gadget_ep_free_request(&priv_ep->endpoint, request); | |
838 | } | |
839 | ||
e9010320 | 840 | static void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep) |
7733f6c3 PL |
841 | { |
842 | /* Work around for stale data address in TRB*/ | |
843 | if (priv_ep->wa1_set) { | |
844 | trace_cdns3_wa1(priv_ep, "restore cycle bit"); | |
845 | ||
846 | priv_ep->wa1_set = 0; | |
847 | priv_ep->wa1_trb_index = 0xFFFF; | |
848 | if (priv_ep->wa1_cycle_bit) { | |
849 | priv_ep->wa1_trb->control = | |
8dafb3c0 | 850 | priv_ep->wa1_trb->control | cpu_to_le32(0x1); |
7733f6c3 PL |
851 | } else { |
852 | priv_ep->wa1_trb->control = | |
8dafb3c0 | 853 | priv_ep->wa1_trb->control & cpu_to_le32(~0x1); |
7733f6c3 PL |
854 | } |
855 | } | |
856 | } | |
857 | ||
858 | static void cdns3_free_aligned_request_buf(struct work_struct *work) | |
859 | { | |
860 | struct cdns3_device *priv_dev = container_of(work, struct cdns3_device, | |
861 | aligned_buf_wq); | |
862 | struct cdns3_aligned_buf *buf, *tmp; | |
863 | unsigned long flags; | |
864 | ||
865 | spin_lock_irqsave(&priv_dev->lock, flags); | |
866 | ||
867 | list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) { | |
868 | if (!buf->in_use) { | |
869 | list_del(&buf->list); | |
870 | ||
871 | /* | |
872 | * Re-enable interrupts to free DMA capable memory. | |
873 | * Driver can't free this memory with disabled | |
874 | * interrupts. | |
875 | */ | |
876 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
877 | dma_free_coherent(priv_dev->sysdev, buf->size, | |
878 | buf->buf, buf->dma); | |
879 | kfree(buf); | |
880 | spin_lock_irqsave(&priv_dev->lock, flags); | |
881 | } | |
882 | } | |
883 | ||
884 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
885 | } | |
886 | ||
887 | static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req) | |
888 | { | |
889 | struct cdns3_endpoint *priv_ep = priv_req->priv_ep; | |
890 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
891 | struct cdns3_aligned_buf *buf; | |
892 | ||
893 | /* check if buffer is aligned to 8. */ | |
894 | if (!((uintptr_t)priv_req->request.buf & 0x7)) | |
895 | return 0; | |
896 | ||
897 | buf = priv_req->aligned_buf; | |
898 | ||
899 | if (!buf || priv_req->request.length > buf->size) { | |
900 | buf = kzalloc(sizeof(*buf), GFP_ATOMIC); | |
901 | if (!buf) | |
902 | return -ENOMEM; | |
903 | ||
904 | buf->size = priv_req->request.length; | |
905 | ||
906 | buf->buf = dma_alloc_coherent(priv_dev->sysdev, | |
907 | buf->size, | |
908 | &buf->dma, | |
909 | GFP_ATOMIC); | |
910 | if (!buf->buf) { | |
911 | kfree(buf); | |
912 | return -ENOMEM; | |
913 | } | |
914 | ||
915 | if (priv_req->aligned_buf) { | |
916 | trace_cdns3_free_aligned_request(priv_req); | |
917 | priv_req->aligned_buf->in_use = 0; | |
918 | queue_work(system_freezable_wq, | |
919 | &priv_dev->aligned_buf_wq); | |
920 | } | |
921 | ||
922 | buf->in_use = 1; | |
923 | priv_req->aligned_buf = buf; | |
924 | ||
925 | list_add_tail(&buf->list, | |
926 | &priv_dev->aligned_buf_list); | |
927 | } | |
928 | ||
929 | if (priv_ep->dir == USB_DIR_IN) { | |
930 | memcpy(buf->buf, priv_req->request.buf, | |
931 | priv_req->request.length); | |
932 | } | |
933 | ||
934 | priv_req->flags |= REQUEST_UNALIGNED; | |
935 | trace_cdns3_prepare_aligned_request(priv_req); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep, | |
941 | struct cdns3_trb *trb) | |
942 | { | |
943 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
944 | ||
945 | if (!priv_ep->wa1_set) { | |
946 | u32 doorbell; | |
947 | ||
948 | doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); | |
949 | ||
950 | if (doorbell) { | |
951 | priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0; | |
952 | priv_ep->wa1_set = 1; | |
953 | priv_ep->wa1_trb = trb; | |
954 | priv_ep->wa1_trb_index = priv_ep->enqueue; | |
955 | trace_cdns3_wa1(priv_ep, "set guard"); | |
956 | return 0; | |
957 | } | |
958 | } | |
959 | return 1; | |
960 | } | |
961 | ||
962 | static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev, | |
963 | struct cdns3_endpoint *priv_ep) | |
964 | { | |
965 | int dma_index; | |
966 | u32 doorbell; | |
967 | ||
968 | doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); | |
969 | dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); | |
970 | ||
971 | if (!doorbell || dma_index != priv_ep->wa1_trb_index) | |
972 | cdns3_wa1_restore_cycle_bit(priv_ep); | |
973 | } | |
974 | ||
54c4c69f JP |
975 | static int cdns3_ep_run_stream_transfer(struct cdns3_endpoint *priv_ep, |
976 | struct usb_request *request) | |
977 | { | |
978 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
979 | struct cdns3_request *priv_req; | |
980 | struct cdns3_trb *trb; | |
981 | dma_addr_t trb_dma; | |
982 | int address; | |
983 | u32 control; | |
984 | u32 length; | |
985 | u32 tdl; | |
986 | unsigned int sg_idx = priv_ep->stream_sg_idx; | |
987 | ||
988 | priv_req = to_cdns3_request(request); | |
989 | address = priv_ep->endpoint.desc->bEndpointAddress; | |
990 | ||
991 | priv_ep->flags |= EP_PENDING_REQUEST; | |
992 | ||
993 | /* must allocate buffer aligned to 8 */ | |
994 | if (priv_req->flags & REQUEST_UNALIGNED) | |
995 | trb_dma = priv_req->aligned_buf->dma; | |
996 | else | |
997 | trb_dma = request->dma; | |
998 | ||
999 | /* For stream capable endpoints driver use only single TD. */ | |
1000 | trb = priv_ep->trb_pool + priv_ep->enqueue; | |
1001 | priv_req->start_trb = priv_ep->enqueue; | |
1002 | priv_req->end_trb = priv_req->start_trb; | |
1003 | priv_req->trb = trb; | |
1004 | ||
1005 | cdns3_select_ep(priv_ep->cdns3_dev, address); | |
1006 | ||
1007 | control = TRB_TYPE(TRB_NORMAL) | TRB_CYCLE | | |
1008 | TRB_STREAM_ID(priv_req->request.stream_id) | TRB_ISP; | |
1009 | ||
1010 | if (!request->num_sgs) { | |
8dafb3c0 | 1011 | trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma)); |
54c4c69f JP |
1012 | length = request->length; |
1013 | } else { | |
8dafb3c0 | 1014 | trb->buffer = cpu_to_le32(TRB_BUFFER(request->sg[sg_idx].dma_address)); |
54c4c69f JP |
1015 | length = request->sg[sg_idx].length; |
1016 | } | |
1017 | ||
1018 | tdl = DIV_ROUND_UP(length, priv_ep->endpoint.maxpacket); | |
1019 | ||
8dafb3c0 | 1020 | trb->length = cpu_to_le32(TRB_BURST_LEN(16) | TRB_LEN(length)); |
54c4c69f JP |
1021 | |
1022 | /* | |
1023 | * For DEV_VER_V2 controller version we have enabled | |
1024 | * USB_CONF2_EN_TDL_TRB in DMULT configuration. | |
1025 | * This enables TDL calculation based on TRB, hence setting TDL in TRB. | |
1026 | */ | |
1027 | if (priv_dev->dev_ver >= DEV_VER_V2) { | |
1028 | if (priv_dev->gadget.speed == USB_SPEED_SUPER) | |
8dafb3c0 | 1029 | trb->length |= cpu_to_le32(TRB_TDL_SS_SIZE(tdl)); |
54c4c69f JP |
1030 | } |
1031 | priv_req->flags |= REQUEST_PENDING; | |
1032 | ||
8dafb3c0 | 1033 | trb->control = cpu_to_le32(control); |
54c4c69f JP |
1034 | |
1035 | trace_cdns3_prepare_trb(priv_ep, priv_req->trb); | |
1036 | ||
1037 | /* | |
1038 | * Memory barrier - Cycle Bit must be set before trb->length and | |
1039 | * trb->buffer fields. | |
1040 | */ | |
1041 | wmb(); | |
1042 | ||
1043 | /* always first element */ | |
1044 | writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), | |
1045 | &priv_dev->regs->ep_traddr); | |
1046 | ||
1047 | if (!(priv_ep->flags & EP_STALLED)) { | |
1048 | trace_cdns3_ring(priv_ep); | |
1049 | /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/ | |
1050 | writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts); | |
1051 | ||
1052 | priv_ep->prime_flag = false; | |
1053 | ||
1054 | /* | |
1055 | * Controller version DEV_VER_V2 tdl calculation | |
1056 | * is based on TRB | |
1057 | */ | |
1058 | ||
1059 | if (priv_dev->dev_ver < DEV_VER_V2) | |
1060 | writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL, | |
1061 | &priv_dev->regs->ep_cmd); | |
1062 | else if (priv_dev->dev_ver > DEV_VER_V2) | |
1063 | writel(tdl, &priv_dev->regs->ep_tdl); | |
1064 | ||
1065 | priv_ep->last_stream_id = priv_req->request.stream_id; | |
1066 | writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); | |
1067 | writel(EP_CMD_ERDY_SID(priv_req->request.stream_id) | | |
1068 | EP_CMD_ERDY, &priv_dev->regs->ep_cmd); | |
1069 | ||
1070 | trace_cdns3_doorbell_epx(priv_ep->name, | |
1071 | readl(&priv_dev->regs->ep_traddr)); | |
1072 | } | |
1073 | ||
1074 | /* WORKAROUND for transition to L0 */ | |
1075 | __cdns3_gadget_wakeup(priv_dev); | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
7733f6c3 PL |
1080 | /** |
1081 | * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware | |
1082 | * @priv_ep: endpoint object | |
4a35aa6d | 1083 | * @request: request object |
7733f6c3 PL |
1084 | * |
1085 | * Returns zero on success or negative value on failure | |
1086 | */ | |
54c4c69f JP |
1087 | static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, |
1088 | struct usb_request *request) | |
7733f6c3 PL |
1089 | { |
1090 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1091 | struct cdns3_request *priv_req; | |
1092 | struct cdns3_trb *trb; | |
1093 | dma_addr_t trb_dma; | |
1094 | u32 togle_pcs = 1; | |
1095 | int sg_iter = 0; | |
1096 | int num_trb; | |
1097 | int address; | |
1098 | u32 control; | |
1099 | int pcs; | |
54c4c69f | 1100 | u16 total_tdl = 0; |
7733f6c3 PL |
1101 | |
1102 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1103 | num_trb = priv_ep->interval; | |
1104 | else | |
1105 | num_trb = request->num_sgs ? request->num_sgs : 1; | |
1106 | ||
1107 | if (num_trb > priv_ep->free_trbs) { | |
1108 | priv_ep->flags |= EP_RING_FULL; | |
1109 | return -ENOBUFS; | |
1110 | } | |
1111 | ||
1112 | priv_req = to_cdns3_request(request); | |
1113 | address = priv_ep->endpoint.desc->bEndpointAddress; | |
1114 | ||
1115 | priv_ep->flags |= EP_PENDING_REQUEST; | |
1116 | ||
1117 | /* must allocate buffer aligned to 8 */ | |
1118 | if (priv_req->flags & REQUEST_UNALIGNED) | |
1119 | trb_dma = priv_req->aligned_buf->dma; | |
1120 | else | |
1121 | trb_dma = request->dma; | |
1122 | ||
1123 | trb = priv_ep->trb_pool + priv_ep->enqueue; | |
1124 | priv_req->start_trb = priv_ep->enqueue; | |
1125 | priv_req->trb = trb; | |
1126 | ||
1127 | cdns3_select_ep(priv_ep->cdns3_dev, address); | |
1128 | ||
1129 | /* prepare ring */ | |
1130 | if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) { | |
1131 | struct cdns3_trb *link_trb; | |
1132 | int doorbell, dma_index; | |
1133 | u32 ch_bit = 0; | |
1134 | ||
1135 | doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); | |
1136 | dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); | |
1137 | ||
1138 | /* Driver can't update LINK TRB if it is current processed. */ | |
1139 | if (doorbell && dma_index == priv_ep->num_trbs - 1) { | |
1140 | priv_ep->flags |= EP_DEFERRED_DRDY; | |
1141 | return -ENOBUFS; | |
1142 | } | |
1143 | ||
1144 | /*updating C bt in Link TRB before starting DMA*/ | |
1145 | link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1); | |
1146 | /* | |
1147 | * For TRs size equal 2 enabling TRB_CHAIN for epXin causes | |
1148 | * that DMA stuck at the LINK TRB. | |
1149 | * On the other hand, removing TRB_CHAIN for longer TRs for | |
1150 | * epXout cause that DMA stuck after handling LINK TRB. | |
1151 | * To eliminate this strange behavioral driver set TRB_CHAIN | |
1152 | * bit only for TR size > 2. | |
1153 | */ | |
1154 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC || | |
1155 | TRBS_PER_SEGMENT > 2) | |
1156 | ch_bit = TRB_CHAIN; | |
1157 | ||
8dafb3c0 PC |
1158 | link_trb->control = cpu_to_le32(((priv_ep->pcs) ? TRB_CYCLE : 0) | |
1159 | TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit); | |
7733f6c3 PL |
1160 | } |
1161 | ||
1162 | if (priv_dev->dev_ver <= DEV_VER_V2) | |
1163 | togle_pcs = cdns3_wa1_update_guard(priv_ep, trb); | |
1164 | ||
1165 | /* set incorrect Cycle Bit for first trb*/ | |
1166 | control = priv_ep->pcs ? 0 : TRB_CYCLE; | |
1167 | ||
1168 | do { | |
1169 | u32 length; | |
1170 | u16 td_size = 0; | |
1171 | ||
1172 | /* fill TRB */ | |
1173 | control |= TRB_TYPE(TRB_NORMAL); | |
8dafb3c0 PC |
1174 | trb->buffer = cpu_to_le32(TRB_BUFFER(request->num_sgs == 0 |
1175 | ? trb_dma : request->sg[sg_iter].dma_address)); | |
7733f6c3 PL |
1176 | |
1177 | if (likely(!request->num_sgs)) | |
1178 | length = request->length; | |
1179 | else | |
1180 | length = request->sg[sg_iter].length; | |
1181 | ||
1182 | if (likely(priv_dev->dev_ver >= DEV_VER_V2)) | |
1183 | td_size = DIV_ROUND_UP(length, | |
1184 | priv_ep->endpoint.maxpacket); | |
54c4c69f JP |
1185 | else if (priv_ep->flags & EP_TDLCHK_EN) |
1186 | total_tdl += DIV_ROUND_UP(length, | |
1187 | priv_ep->endpoint.maxpacket); | |
7733f6c3 | 1188 | |
8dafb3c0 PC |
1189 | trb->length = cpu_to_le32(TRB_BURST_LEN(priv_ep->trb_burst_size) | |
1190 | TRB_LEN(length)); | |
7733f6c3 | 1191 | if (priv_dev->gadget.speed == USB_SPEED_SUPER) |
8dafb3c0 | 1192 | trb->length |= cpu_to_le32(TRB_TDL_SS_SIZE(td_size)); |
7733f6c3 PL |
1193 | else |
1194 | control |= TRB_TDL_HS_SIZE(td_size); | |
1195 | ||
1196 | pcs = priv_ep->pcs ? TRB_CYCLE : 0; | |
1197 | ||
1198 | /* | |
1199 | * first trb should be prepared as last to avoid processing | |
1200 | * transfer to early | |
1201 | */ | |
1202 | if (sg_iter != 0) | |
1203 | control |= pcs; | |
1204 | ||
1205 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) { | |
1206 | control |= TRB_IOC | TRB_ISP; | |
1207 | } else { | |
1208 | /* for last element in TD or in SG list */ | |
1209 | if (sg_iter == (num_trb - 1) && sg_iter != 0) | |
1210 | control |= pcs | TRB_IOC | TRB_ISP; | |
1211 | } | |
1212 | ||
1213 | if (sg_iter) | |
8dafb3c0 | 1214 | trb->control = cpu_to_le32(control); |
7733f6c3 | 1215 | else |
8dafb3c0 | 1216 | priv_req->trb->control = cpu_to_le32(control); |
7733f6c3 PL |
1217 | |
1218 | control = 0; | |
1219 | ++sg_iter; | |
1220 | priv_req->end_trb = priv_ep->enqueue; | |
1221 | cdns3_ep_inc_enq(priv_ep); | |
1222 | trb = priv_ep->trb_pool + priv_ep->enqueue; | |
1223 | } while (sg_iter < num_trb); | |
1224 | ||
1225 | trb = priv_req->trb; | |
1226 | ||
1227 | priv_req->flags |= REQUEST_PENDING; | |
1228 | ||
1229 | if (sg_iter == 1) | |
8dafb3c0 | 1230 | trb->control |= cpu_to_le32(TRB_IOC | TRB_ISP); |
7733f6c3 | 1231 | |
54c4c69f JP |
1232 | if (priv_dev->dev_ver < DEV_VER_V2 && |
1233 | (priv_ep->flags & EP_TDLCHK_EN)) { | |
1234 | u16 tdl = total_tdl; | |
1235 | u16 old_tdl = EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd)); | |
1236 | ||
1237 | if (tdl > EP_CMD_TDL_MAX) { | |
1238 | tdl = EP_CMD_TDL_MAX; | |
1239 | priv_ep->pending_tdl = total_tdl - EP_CMD_TDL_MAX; | |
1240 | } | |
1241 | ||
1242 | if (old_tdl < tdl) { | |
1243 | tdl -= old_tdl; | |
1244 | writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL, | |
1245 | &priv_dev->regs->ep_cmd); | |
1246 | } | |
1247 | } | |
1248 | ||
7733f6c3 PL |
1249 | /* |
1250 | * Memory barrier - cycle bit must be set before other filds in trb. | |
1251 | */ | |
1252 | wmb(); | |
1253 | ||
1254 | /* give the TD to the consumer*/ | |
1255 | if (togle_pcs) | |
8dafb3c0 | 1256 | trb->control = trb->control ^ cpu_to_le32(1); |
7733f6c3 PL |
1257 | |
1258 | if (priv_dev->dev_ver <= DEV_VER_V2) | |
1259 | cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep); | |
1260 | ||
1261 | trace_cdns3_prepare_trb(priv_ep, priv_req->trb); | |
1262 | ||
1263 | /* | |
1264 | * Memory barrier - Cycle Bit must be set before trb->length and | |
1265 | * trb->buffer fields. | |
1266 | */ | |
1267 | wmb(); | |
1268 | ||
1269 | /* | |
1270 | * For DMULT mode we can set address to transfer ring only once after | |
1271 | * enabling endpoint. | |
1272 | */ | |
1273 | if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) { | |
1274 | /* | |
1275 | * Until SW is not ready to handle the OUT transfer the ISO OUT | |
1276 | * Endpoint should be disabled (EP_CFG.ENABLE = 0). | |
1277 | * EP_CFG_ENABLE must be set before updating ep_traddr. | |
1278 | */ | |
1279 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir && | |
1280 | !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) { | |
1281 | priv_ep->flags |= EP_QUIRK_ISO_OUT_EN; | |
1282 | cdns3_set_register_bit(&priv_dev->regs->ep_cfg, | |
1283 | EP_CFG_ENABLE); | |
1284 | } | |
1285 | ||
1286 | writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma + | |
1287 | priv_req->start_trb * TRB_SIZE), | |
1288 | &priv_dev->regs->ep_traddr); | |
1289 | ||
1290 | priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR; | |
1291 | } | |
1292 | ||
1293 | if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) { | |
1294 | trace_cdns3_ring(priv_ep); | |
1295 | /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/ | |
1296 | writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts); | |
1297 | writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); | |
1298 | trace_cdns3_doorbell_epx(priv_ep->name, | |
1299 | readl(&priv_dev->regs->ep_traddr)); | |
1300 | } | |
1301 | ||
1302 | /* WORKAROUND for transition to L0 */ | |
1303 | __cdns3_gadget_wakeup(priv_dev); | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | void cdns3_set_hw_configuration(struct cdns3_device *priv_dev) | |
1309 | { | |
1310 | struct cdns3_endpoint *priv_ep; | |
1311 | struct usb_ep *ep; | |
7733f6c3 PL |
1312 | |
1313 | if (priv_dev->hw_configured_flag) | |
1314 | return; | |
1315 | ||
1316 | writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf); | |
7733f6c3 PL |
1317 | |
1318 | cdns3_set_register_bit(&priv_dev->regs->usb_conf, | |
1319 | USB_CONF_U1EN | USB_CONF_U2EN); | |
1320 | ||
7733f6c3 PL |
1321 | priv_dev->hw_configured_flag = 1; |
1322 | ||
1323 | list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { | |
1324 | if (ep->enabled) { | |
1325 | priv_ep = ep_to_cdns3_ep(ep); | |
1326 | cdns3_start_all_request(priv_dev, priv_ep); | |
1327 | } | |
1328 | } | |
f4cfe5ce PC |
1329 | |
1330 | cdns3_allow_enable_l1(priv_dev, 1); | |
7733f6c3 PL |
1331 | } |
1332 | ||
1333 | /** | |
1334 | * cdns3_request_handled - check whether request has been handled by DMA | |
1335 | * | |
1336 | * @priv_ep: extended endpoint object. | |
1337 | * @priv_req: request object for checking | |
1338 | * | |
1339 | * Endpoint must be selected before invoking this function. | |
1340 | * | |
1341 | * Returns false if request has not been handled by DMA, else returns true. | |
1342 | * | |
1343 | * SR - start ring | |
1344 | * ER - end ring | |
1345 | * DQ = priv_ep->dequeue - dequeue position | |
1346 | * EQ = priv_ep->enqueue - enqueue position | |
1347 | * ST = priv_req->start_trb - index of first TRB in transfer ring | |
1348 | * ET = priv_req->end_trb - index of last TRB in transfer ring | |
1349 | * CI = current_index - index of processed TRB by DMA. | |
1350 | * | |
1351 | * As first step, function checks if cycle bit for priv_req->start_trb is | |
1352 | * correct. | |
1353 | * | |
1354 | * some rules: | |
1355 | * 1. priv_ep->dequeue never exceed current_index. | |
1356 | * 2 priv_ep->enqueue never exceed priv_ep->dequeue | |
1357 | * 3. exception: priv_ep->enqueue == priv_ep->dequeue | |
1358 | * and priv_ep->free_trbs is zero. | |
1359 | * This case indicate that TR is full. | |
1360 | * | |
1361 | * Then We can split recognition into two parts: | |
1362 | * Case 1 - priv_ep->dequeue < current_index | |
1363 | * SR ... EQ ... DQ ... CI ... ER | |
1364 | * SR ... DQ ... CI ... EQ ... ER | |
1365 | * | |
1366 | * Request has been handled by DMA if ST and ET is between DQ and CI. | |
1367 | * | |
1368 | * Case 2 - priv_ep->dequeue > current_index | |
1369 | * This situation take place when CI go through the LINK TRB at the end of | |
1370 | * transfer ring. | |
1371 | * SR ... CI ... EQ ... DQ ... ER | |
1372 | * | |
1373 | * Request has been handled by DMA if ET is less then CI or | |
1374 | * ET is greater or equal DQ. | |
1375 | */ | |
1376 | static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep, | |
1377 | struct cdns3_request *priv_req) | |
1378 | { | |
1379 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1f9f5a81 | 1380 | struct cdns3_trb *trb; |
7733f6c3 PL |
1381 | int current_index = 0; |
1382 | int handled = 0; | |
1383 | int doorbell; | |
1384 | ||
1385 | current_index = cdns3_get_dma_pos(priv_dev, priv_ep); | |
1386 | doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); | |
1387 | ||
1388 | trb = &priv_ep->trb_pool[priv_req->start_trb]; | |
1389 | ||
8dafb3c0 | 1390 | if ((le32_to_cpu(trb->control) & TRB_CYCLE) != priv_ep->ccs) |
7733f6c3 PL |
1391 | goto finish; |
1392 | ||
1393 | if (doorbell == 1 && current_index == priv_ep->dequeue) | |
1394 | goto finish; | |
1395 | ||
1396 | /* The corner case for TRBS_PER_SEGMENT equal 2). */ | |
1397 | if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { | |
1398 | handled = 1; | |
1399 | goto finish; | |
1400 | } | |
1401 | ||
1402 | if (priv_ep->enqueue == priv_ep->dequeue && | |
1403 | priv_ep->free_trbs == 0) { | |
1404 | handled = 1; | |
1405 | } else if (priv_ep->dequeue < current_index) { | |
1406 | if ((current_index == (priv_ep->num_trbs - 1)) && | |
1407 | !priv_ep->dequeue) | |
1408 | goto finish; | |
1409 | ||
1410 | if (priv_req->end_trb >= priv_ep->dequeue && | |
1411 | priv_req->end_trb < current_index) | |
1412 | handled = 1; | |
1413 | } else if (priv_ep->dequeue > current_index) { | |
1414 | if (priv_req->end_trb < current_index || | |
1415 | priv_req->end_trb >= priv_ep->dequeue) | |
1416 | handled = 1; | |
1417 | } | |
1418 | ||
1419 | finish: | |
1420 | trace_cdns3_request_handled(priv_req, current_index, handled); | |
1421 | ||
1422 | return handled; | |
1423 | } | |
1424 | ||
1425 | static void cdns3_transfer_completed(struct cdns3_device *priv_dev, | |
1426 | struct cdns3_endpoint *priv_ep) | |
1427 | { | |
1428 | struct cdns3_request *priv_req; | |
1429 | struct usb_request *request; | |
1430 | struct cdns3_trb *trb; | |
1431 | ||
1432 | while (!list_empty(&priv_ep->pending_req_list)) { | |
1433 | request = cdns3_next_request(&priv_ep->pending_req_list); | |
1434 | priv_req = to_cdns3_request(request); | |
1435 | ||
f616c3bd PL |
1436 | trb = priv_ep->trb_pool + priv_ep->dequeue; |
1437 | ||
1438 | /* Request was dequeued and TRB was changed to TRB_LINK. */ | |
8dafb3c0 | 1439 | if (TRB_FIELD_TO_TYPE(le32_to_cpu(trb->control)) == TRB_LINK) { |
f616c3bd PL |
1440 | trace_cdns3_complete_trb(priv_ep, trb); |
1441 | cdns3_move_deq_to_next_trb(priv_req); | |
1442 | } | |
1443 | ||
54c4c69f JP |
1444 | if (!request->stream_id) { |
1445 | /* Re-select endpoint. It could be changed by other CPU | |
1446 | * during handling usb_gadget_giveback_request. | |
1447 | */ | |
1448 | cdns3_select_ep(priv_dev, priv_ep->endpoint.address); | |
7733f6c3 | 1449 | |
54c4c69f JP |
1450 | if (!cdns3_request_handled(priv_ep, priv_req)) |
1451 | goto prepare_next_td; | |
7733f6c3 | 1452 | |
54c4c69f JP |
1453 | trb = priv_ep->trb_pool + priv_ep->dequeue; |
1454 | trace_cdns3_complete_trb(priv_ep, trb); | |
1455 | ||
1456 | if (trb != priv_req->trb) | |
1457 | dev_warn(priv_dev->dev, | |
1458 | "request_trb=0x%p, queue_trb=0x%p\n", | |
1459 | priv_req->trb, trb); | |
7733f6c3 | 1460 | |
54c4c69f JP |
1461 | request->actual = TRB_LEN(le32_to_cpu(trb->length)); |
1462 | cdns3_move_deq_to_next_trb(priv_req); | |
1463 | cdns3_gadget_giveback(priv_ep, priv_req, 0); | |
7733f6c3 | 1464 | |
54c4c69f JP |
1465 | if (priv_ep->type != USB_ENDPOINT_XFER_ISOC && |
1466 | TRBS_PER_SEGMENT == 2) | |
1467 | break; | |
1468 | } else { | |
1469 | /* Re-select endpoint. It could be changed by other CPU | |
1470 | * during handling usb_gadget_giveback_request. | |
1471 | */ | |
1472 | cdns3_select_ep(priv_dev, priv_ep->endpoint.address); | |
1473 | ||
1474 | trb = priv_ep->trb_pool; | |
1475 | trace_cdns3_complete_trb(priv_ep, trb); | |
7733f6c3 | 1476 | |
54c4c69f JP |
1477 | if (trb != priv_req->trb) |
1478 | dev_warn(priv_dev->dev, | |
1479 | "request_trb=0x%p, queue_trb=0x%p\n", | |
1480 | priv_req->trb, trb); | |
1481 | ||
1482 | request->actual += TRB_LEN(le32_to_cpu(trb->length)); | |
1483 | ||
1484 | if (!request->num_sgs || | |
1485 | (request->num_sgs == (priv_ep->stream_sg_idx + 1))) { | |
1486 | priv_ep->stream_sg_idx = 0; | |
1487 | cdns3_gadget_giveback(priv_ep, priv_req, 0); | |
1488 | } else { | |
1489 | priv_ep->stream_sg_idx++; | |
1490 | cdns3_ep_run_stream_transfer(priv_ep, request); | |
1491 | } | |
7733f6c3 | 1492 | break; |
54c4c69f | 1493 | } |
7733f6c3 PL |
1494 | } |
1495 | priv_ep->flags &= ~EP_PENDING_REQUEST; | |
1496 | ||
1497 | prepare_next_td: | |
1498 | if (!(priv_ep->flags & EP_STALLED) && | |
1499 | !(priv_ep->flags & EP_STALL_PENDING)) | |
1500 | cdns3_start_all_request(priv_dev, priv_ep); | |
1501 | } | |
1502 | ||
1503 | void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm) | |
1504 | { | |
1505 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1506 | ||
1507 | cdns3_wa1_restore_cycle_bit(priv_ep); | |
1508 | ||
1509 | if (rearm) { | |
1510 | trace_cdns3_ring(priv_ep); | |
1511 | ||
1512 | /* Cycle Bit must be updated before arming DMA. */ | |
1513 | wmb(); | |
1514 | writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); | |
1515 | ||
1516 | __cdns3_gadget_wakeup(priv_dev); | |
1517 | ||
1518 | trace_cdns3_doorbell_epx(priv_ep->name, | |
1519 | readl(&priv_dev->regs->ep_traddr)); | |
1520 | } | |
1521 | } | |
1522 | ||
54c4c69f JP |
1523 | static void cdns3_reprogram_tdl(struct cdns3_endpoint *priv_ep) |
1524 | { | |
1525 | u16 tdl = priv_ep->pending_tdl; | |
1526 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1527 | ||
1528 | if (tdl > EP_CMD_TDL_MAX) { | |
1529 | tdl = EP_CMD_TDL_MAX; | |
1530 | priv_ep->pending_tdl -= EP_CMD_TDL_MAX; | |
1531 | } else { | |
1532 | priv_ep->pending_tdl = 0; | |
1533 | } | |
1534 | ||
1535 | writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL, &priv_dev->regs->ep_cmd); | |
1536 | } | |
1537 | ||
7733f6c3 PL |
1538 | /** |
1539 | * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint | |
1540 | * @priv_ep: endpoint object | |
1541 | * | |
1542 | * Returns 0 | |
1543 | */ | |
1544 | static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep) | |
1545 | { | |
1546 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1547 | u32 ep_sts_reg; | |
54c4c69f JP |
1548 | struct usb_request *deferred_request; |
1549 | struct usb_request *pending_request; | |
1550 | u32 tdl = 0; | |
7733f6c3 PL |
1551 | |
1552 | cdns3_select_ep(priv_dev, priv_ep->endpoint.address); | |
1553 | ||
1554 | trace_cdns3_epx_irq(priv_dev, priv_ep); | |
1555 | ||
1556 | ep_sts_reg = readl(&priv_dev->regs->ep_sts); | |
1557 | writel(ep_sts_reg, &priv_dev->regs->ep_sts); | |
1558 | ||
54c4c69f JP |
1559 | if ((ep_sts_reg & EP_STS_PRIME) && priv_ep->use_streams) { |
1560 | bool dbusy = !!(ep_sts_reg & EP_STS_DBUSY); | |
1561 | ||
1562 | tdl = cdns3_get_tdl(priv_dev); | |
1563 | ||
1564 | /* | |
1565 | * Continue the previous transfer: | |
1566 | * There is some racing between ERDY and PRIME. The device send | |
1567 | * ERDY and almost in the same time Host send PRIME. It cause | |
1568 | * that host ignore the ERDY packet and driver has to send it | |
1569 | * again. | |
1570 | */ | |
8dafb3c0 | 1571 | if (tdl && (dbusy || !EP_STS_BUFFEMPTY(ep_sts_reg) || |
54c4c69f JP |
1572 | EP_STS_HOSTPP(ep_sts_reg))) { |
1573 | writel(EP_CMD_ERDY | | |
1574 | EP_CMD_ERDY_SID(priv_ep->last_stream_id), | |
1575 | &priv_dev->regs->ep_cmd); | |
1576 | ep_sts_reg &= ~(EP_STS_MD_EXIT | EP_STS_IOC); | |
1577 | } else { | |
1578 | priv_ep->prime_flag = true; | |
1579 | ||
1580 | pending_request = cdns3_next_request(&priv_ep->pending_req_list); | |
1581 | deferred_request = cdns3_next_request(&priv_ep->deferred_req_list); | |
1582 | ||
1583 | if (deferred_request && !pending_request) { | |
1584 | cdns3_start_all_request(priv_dev, priv_ep); | |
1585 | } | |
1586 | } | |
1587 | } | |
1588 | ||
7733f6c3 PL |
1589 | if (ep_sts_reg & EP_STS_TRBERR) { |
1590 | if (priv_ep->flags & EP_STALL_PENDING && | |
1591 | !(ep_sts_reg & EP_STS_DESCMIS && | |
1592 | priv_dev->dev_ver < DEV_VER_V2)) { | |
1593 | cdns3_ep_stall_flush(priv_ep); | |
1594 | } | |
1595 | ||
1596 | /* | |
1597 | * For isochronous transfer driver completes request on | |
1598 | * IOC or on TRBERR. IOC appears only when device receive | |
1599 | * OUT data packet. If host disable stream or lost some packet | |
1600 | * then the only way to finish all queued transfer is to do it | |
1601 | * on TRBERR event. | |
1602 | */ | |
1603 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && | |
1604 | !priv_ep->wa1_set) { | |
1605 | if (!priv_ep->dir) { | |
1606 | u32 ep_cfg = readl(&priv_dev->regs->ep_cfg); | |
1607 | ||
1608 | ep_cfg &= ~EP_CFG_ENABLE; | |
1609 | writel(ep_cfg, &priv_dev->regs->ep_cfg); | |
1610 | priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN; | |
1611 | } | |
1612 | cdns3_transfer_completed(priv_dev, priv_ep); | |
1613 | } else if (!(priv_ep->flags & EP_STALLED) && | |
1614 | !(priv_ep->flags & EP_STALL_PENDING)) { | |
1615 | if (priv_ep->flags & EP_DEFERRED_DRDY) { | |
1616 | priv_ep->flags &= ~EP_DEFERRED_DRDY; | |
1617 | cdns3_start_all_request(priv_dev, priv_ep); | |
1618 | } else { | |
1619 | cdns3_rearm_transfer(priv_ep, | |
1620 | priv_ep->wa1_set); | |
1621 | } | |
1622 | } | |
1623 | } | |
1624 | ||
54c4c69f JP |
1625 | if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP) || |
1626 | (ep_sts_reg & EP_STS_IOT)) { | |
6bbf87a1 PL |
1627 | if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) { |
1628 | if (ep_sts_reg & EP_STS_ISP) | |
1629 | priv_ep->flags |= EP_QUIRK_END_TRANSFER; | |
1630 | else | |
1631 | priv_ep->flags &= ~EP_QUIRK_END_TRANSFER; | |
1632 | } | |
1633 | ||
54c4c69f JP |
1634 | if (!priv_ep->use_streams) { |
1635 | if ((ep_sts_reg & EP_STS_IOC) || | |
1636 | (ep_sts_reg & EP_STS_ISP)) { | |
1637 | cdns3_transfer_completed(priv_dev, priv_ep); | |
1638 | } else if ((priv_ep->flags & EP_TDLCHK_EN) & | |
1639 | priv_ep->pending_tdl) { | |
1640 | /* handle IOT with pending tdl */ | |
1641 | cdns3_reprogram_tdl(priv_ep); | |
1642 | } | |
1643 | } else if (priv_ep->dir == USB_DIR_OUT) { | |
1644 | priv_ep->ep_sts_pending |= ep_sts_reg; | |
1645 | } else if (ep_sts_reg & EP_STS_IOT) { | |
1646 | cdns3_transfer_completed(priv_dev, priv_ep); | |
1647 | } | |
1648 | } | |
1649 | ||
1650 | /* | |
1651 | * MD_EXIT interrupt sets when stream capable endpoint exits | |
1652 | * from MOVE DATA state of Bulk IN/OUT stream protocol state machine | |
1653 | */ | |
1654 | if (priv_ep->dir == USB_DIR_OUT && (ep_sts_reg & EP_STS_MD_EXIT) && | |
1655 | (priv_ep->ep_sts_pending & EP_STS_IOT) && priv_ep->use_streams) { | |
1656 | priv_ep->ep_sts_pending = 0; | |
7733f6c3 | 1657 | cdns3_transfer_completed(priv_dev, priv_ep); |
6bbf87a1 PL |
1658 | } |
1659 | ||
1660 | /* | |
1661 | * WA2: this condition should only be meet when | |
1662 | * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or | |
1663 | * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN. | |
54c4c69f | 1664 | * In other cases this interrupt will be disabled. |
6bbf87a1 PL |
1665 | */ |
1666 | if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 && | |
1667 | !(priv_ep->flags & EP_STALLED)) | |
1668 | cdns3_wa2_descmissing_packet(priv_ep); | |
7733f6c3 PL |
1669 | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev) | |
1674 | { | |
1675 | if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) { | |
1676 | spin_unlock(&priv_dev->lock); | |
1677 | priv_dev->gadget_driver->disconnect(&priv_dev->gadget); | |
1678 | spin_lock(&priv_dev->lock); | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | /** | |
1683 | * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device | |
1684 | * @priv_dev: extended gadget object | |
1685 | * @usb_ists: bitmap representation of device's reported interrupts | |
1686 | * (usb_ists register value) | |
1687 | */ | |
1688 | static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev, | |
1689 | u32 usb_ists) | |
1690 | { | |
1691 | int speed = 0; | |
1692 | ||
1693 | trace_cdns3_usb_irq(priv_dev, usb_ists); | |
1694 | if (usb_ists & USB_ISTS_L1ENTI) { | |
1695 | /* | |
1696 | * WORKAROUND: CDNS3 controller has issue with hardware resuming | |
1697 | * from L1. To fix it, if any DMA transfer is pending driver | |
1698 | * must starts driving resume signal immediately. | |
1699 | */ | |
1700 | if (readl(&priv_dev->regs->drbl)) | |
1701 | __cdns3_gadget_wakeup(priv_dev); | |
1702 | } | |
1703 | ||
1704 | /* Connection detected */ | |
1705 | if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) { | |
1706 | speed = cdns3_get_speed(priv_dev); | |
1707 | priv_dev->gadget.speed = speed; | |
1708 | usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED); | |
1709 | cdns3_ep0_config(priv_dev); | |
1710 | } | |
1711 | ||
1712 | /* Disconnection detected */ | |
1713 | if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) { | |
1714 | cdns3_disconnect_gadget(priv_dev); | |
1715 | priv_dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1716 | usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED); | |
1717 | cdns3_hw_reset_eps_config(priv_dev); | |
1718 | } | |
1719 | ||
1720 | if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) { | |
1721 | if (priv_dev->gadget_driver && | |
1722 | priv_dev->gadget_driver->suspend) { | |
1723 | spin_unlock(&priv_dev->lock); | |
1724 | priv_dev->gadget_driver->suspend(&priv_dev->gadget); | |
1725 | spin_lock(&priv_dev->lock); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) { | |
1730 | if (priv_dev->gadget_driver && | |
1731 | priv_dev->gadget_driver->resume) { | |
1732 | spin_unlock(&priv_dev->lock); | |
1733 | priv_dev->gadget_driver->resume(&priv_dev->gadget); | |
1734 | spin_lock(&priv_dev->lock); | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | /* reset*/ | |
1739 | if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) { | |
1740 | if (priv_dev->gadget_driver) { | |
1741 | spin_unlock(&priv_dev->lock); | |
1742 | usb_gadget_udc_reset(&priv_dev->gadget, | |
1743 | priv_dev->gadget_driver); | |
1744 | spin_lock(&priv_dev->lock); | |
1745 | ||
1746 | /*read again to check the actual speed*/ | |
1747 | speed = cdns3_get_speed(priv_dev); | |
1748 | priv_dev->gadget.speed = speed; | |
1749 | cdns3_hw_reset_eps_config(priv_dev); | |
1750 | cdns3_ep0_config(priv_dev); | |
1751 | } | |
1752 | } | |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * cdns3_device_irq_handler- interrupt handler for device part of controller | |
1757 | * | |
1758 | * @irq: irq number for cdns3 core device | |
1759 | * @data: structure of cdns3 | |
1760 | * | |
1761 | * Returns IRQ_HANDLED or IRQ_NONE | |
1762 | */ | |
1763 | static irqreturn_t cdns3_device_irq_handler(int irq, void *data) | |
1764 | { | |
af58e1fc | 1765 | struct cdns3_device *priv_dev = data; |
b1234e3b | 1766 | struct cdns3 *cdns = dev_get_drvdata(priv_dev->dev); |
7733f6c3 PL |
1767 | irqreturn_t ret = IRQ_NONE; |
1768 | u32 reg; | |
1769 | ||
b1234e3b PC |
1770 | if (cdns->in_lpm) |
1771 | return ret; | |
1772 | ||
7733f6c3 PL |
1773 | /* check USB device interrupt */ |
1774 | reg = readl(&priv_dev->regs->usb_ists); | |
1775 | if (reg) { | |
1776 | /* After masking interrupts the new interrupts won't be | |
1777 | * reported in usb_ists/ep_ists. In order to not lose some | |
1778 | * of them driver disables only detected interrupts. | |
1779 | * They will be enabled ASAP after clearing source of | |
1780 | * interrupt. This an unusual behavior only applies to | |
1781 | * usb_ists register. | |
1782 | */ | |
1783 | reg = ~reg & readl(&priv_dev->regs->usb_ien); | |
1784 | /* mask deferred interrupt. */ | |
1785 | writel(reg, &priv_dev->regs->usb_ien); | |
1786 | ret = IRQ_WAKE_THREAD; | |
1787 | } | |
1788 | ||
1789 | /* check endpoint interrupt */ | |
1790 | reg = readl(&priv_dev->regs->ep_ists); | |
1791 | if (reg) { | |
1792 | writel(0, &priv_dev->regs->ep_ien); | |
1793 | ret = IRQ_WAKE_THREAD; | |
1794 | } | |
1795 | ||
1796 | return ret; | |
1797 | } | |
1798 | ||
1799 | /** | |
1800 | * cdns3_device_thread_irq_handler- interrupt handler for device part | |
1801 | * of controller | |
1802 | * | |
1803 | * @irq: irq number for cdns3 core device | |
1804 | * @data: structure of cdns3 | |
1805 | * | |
1806 | * Returns IRQ_HANDLED or IRQ_NONE | |
1807 | */ | |
1808 | static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data) | |
1809 | { | |
af58e1fc | 1810 | struct cdns3_device *priv_dev = data; |
7733f6c3 PL |
1811 | irqreturn_t ret = IRQ_NONE; |
1812 | unsigned long flags; | |
06825ca0 | 1813 | unsigned int bit; |
8685c46d | 1814 | unsigned long reg; |
7733f6c3 | 1815 | |
7733f6c3 PL |
1816 | spin_lock_irqsave(&priv_dev->lock, flags); |
1817 | ||
1818 | reg = readl(&priv_dev->regs->usb_ists); | |
1819 | if (reg) { | |
1820 | writel(reg, &priv_dev->regs->usb_ists); | |
1821 | writel(USB_IEN_INIT, &priv_dev->regs->usb_ien); | |
1822 | cdns3_check_usb_interrupt_proceed(priv_dev, reg); | |
1823 | ret = IRQ_HANDLED; | |
1824 | } | |
1825 | ||
1826 | reg = readl(&priv_dev->regs->ep_ists); | |
1827 | ||
1828 | /* handle default endpoint OUT */ | |
1829 | if (reg & EP_ISTS_EP_OUT0) { | |
1830 | cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT); | |
1831 | ret = IRQ_HANDLED; | |
1832 | } | |
1833 | ||
1834 | /* handle default endpoint IN */ | |
1835 | if (reg & EP_ISTS_EP_IN0) { | |
1836 | cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN); | |
1837 | ret = IRQ_HANDLED; | |
1838 | } | |
1839 | ||
1840 | /* check if interrupt from non default endpoint, if no exit */ | |
1841 | reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0); | |
1842 | if (!reg) | |
1843 | goto irqend; | |
1844 | ||
8685c46d | 1845 | for_each_set_bit(bit, ®, |
7733f6c3 PL |
1846 | sizeof(u32) * BITS_PER_BYTE) { |
1847 | cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]); | |
1848 | ret = IRQ_HANDLED; | |
1849 | } | |
1850 | ||
54c4c69f JP |
1851 | if (priv_dev->dev_ver < DEV_VER_V2 && priv_dev->using_streams) |
1852 | cdns3_wa2_check_outq_status(priv_dev); | |
1853 | ||
7733f6c3 PL |
1854 | irqend: |
1855 | writel(~0, &priv_dev->regs->ep_ien); | |
1856 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
1857 | ||
1858 | return ret; | |
1859 | } | |
1860 | ||
1861 | /** | |
1862 | * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP | |
1863 | * | |
1864 | * The real reservation will occur during write to EP_CFG register, | |
1865 | * this function is used to check if the 'size' reservation is allowed. | |
1866 | * | |
1867 | * @priv_dev: extended gadget object | |
1868 | * @size: the size (KB) for EP would like to allocate | |
1869 | * @is_in: endpoint direction | |
1870 | * | |
1871 | * Return 0 if the required size can met or negative value on failure | |
1872 | */ | |
1873 | static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev, | |
1874 | int size, int is_in) | |
1875 | { | |
1876 | int remained; | |
1877 | ||
1878 | /* 2KB are reserved for EP0*/ | |
1879 | remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2; | |
1880 | ||
1881 | if (is_in) { | |
1882 | if (remained < size) | |
1883 | return -EPERM; | |
1884 | ||
1885 | priv_dev->onchip_used_size += size; | |
1886 | } else { | |
1887 | int required; | |
1888 | ||
1889 | /** | |
1890 | * ALL OUT EPs are shared the same chunk onchip memory, so | |
1891 | * driver checks if it already has assigned enough buffers | |
1892 | */ | |
1893 | if (priv_dev->out_mem_is_allocated >= size) | |
1894 | return 0; | |
1895 | ||
1896 | required = size - priv_dev->out_mem_is_allocated; | |
1897 | ||
1898 | if (required > remained) | |
1899 | return -EPERM; | |
1900 | ||
1901 | priv_dev->out_mem_is_allocated += required; | |
1902 | priv_dev->onchip_used_size += required; | |
1903 | } | |
1904 | ||
1905 | return 0; | |
1906 | } | |
1907 | ||
e9010320 | 1908 | static void cdns3_stream_ep_reconfig(struct cdns3_device *priv_dev, |
e2e77a94 | 1909 | struct cdns3_endpoint *priv_ep) |
54c4c69f JP |
1910 | { |
1911 | if (!priv_ep->use_streams || priv_dev->gadget.speed < USB_SPEED_SUPER) | |
1912 | return; | |
1913 | ||
1914 | if (priv_dev->dev_ver >= DEV_VER_V3) { | |
1915 | u32 mask = BIT(priv_ep->num + (priv_ep->dir ? 16 : 0)); | |
1916 | ||
1917 | /* | |
1918 | * Stream capable endpoints are handled by using ep_tdl | |
1919 | * register. Other endpoints use TDL from TRB feature. | |
1920 | */ | |
1921 | cdns3_clear_register_bit(&priv_dev->regs->tdl_from_trb, mask); | |
1922 | } | |
1923 | ||
1924 | /* Enable Stream Bit TDL chk and SID chk */ | |
1925 | cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_STREAM_EN | | |
1926 | EP_CFG_TDL_CHK | EP_CFG_SID_CHK); | |
1927 | } | |
1928 | ||
e9010320 | 1929 | static void cdns3_configure_dmult(struct cdns3_device *priv_dev, |
e2e77a94 | 1930 | struct cdns3_endpoint *priv_ep) |
7733f6c3 PL |
1931 | { |
1932 | struct cdns3_usb_regs __iomem *regs = priv_dev->regs; | |
1933 | ||
1934 | /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */ | |
1935 | if (priv_dev->dev_ver <= DEV_VER_V2) | |
1936 | writel(USB_CONF_DMULT, ®s->usb_conf); | |
1937 | ||
1938 | if (priv_dev->dev_ver == DEV_VER_V2) | |
1939 | writel(USB_CONF2_EN_TDL_TRB, ®s->usb_conf2); | |
1940 | ||
1941 | if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) { | |
1942 | u32 mask; | |
1943 | ||
1944 | if (priv_ep->dir) | |
1945 | mask = BIT(priv_ep->num + 16); | |
1946 | else | |
1947 | mask = BIT(priv_ep->num); | |
1948 | ||
1949 | if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) { | |
1950 | cdns3_set_register_bit(®s->tdl_from_trb, mask); | |
1951 | cdns3_set_register_bit(®s->tdl_beh, mask); | |
1952 | cdns3_set_register_bit(®s->tdl_beh2, mask); | |
1953 | cdns3_set_register_bit(®s->dma_adv_td, mask); | |
1954 | } | |
1955 | ||
1956 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) | |
1957 | cdns3_set_register_bit(®s->tdl_from_trb, mask); | |
1958 | ||
1959 | cdns3_set_register_bit(®s->dtrans, mask); | |
1960 | } | |
1961 | } | |
1962 | ||
1963 | /** | |
1964 | * cdns3_ep_config Configure hardware endpoint | |
1965 | * @priv_ep: extended endpoint object | |
1966 | */ | |
1967 | void cdns3_ep_config(struct cdns3_endpoint *priv_ep) | |
1968 | { | |
1969 | bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC); | |
1970 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
1971 | u32 bEndpointAddress = priv_ep->num | priv_ep->dir; | |
1972 | u32 max_packet_size = 0; | |
1973 | u8 maxburst = 0; | |
1974 | u32 ep_cfg = 0; | |
1975 | u8 buffering; | |
1976 | u8 mult = 0; | |
1977 | int ret; | |
1978 | ||
1979 | buffering = CDNS3_EP_BUF_SIZE - 1; | |
1980 | ||
1981 | cdns3_configure_dmult(priv_dev, priv_ep); | |
1982 | ||
1983 | switch (priv_ep->type) { | |
1984 | case USB_ENDPOINT_XFER_INT: | |
1985 | ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT); | |
1986 | ||
1987 | if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || | |
1988 | priv_dev->dev_ver > DEV_VER_V2) | |
1989 | ep_cfg |= EP_CFG_TDL_CHK; | |
1990 | break; | |
1991 | case USB_ENDPOINT_XFER_BULK: | |
1992 | ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK); | |
1993 | ||
1994 | if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || | |
1995 | priv_dev->dev_ver > DEV_VER_V2) | |
1996 | ep_cfg |= EP_CFG_TDL_CHK; | |
1997 | break; | |
1998 | default: | |
1999 | ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC); | |
2000 | mult = CDNS3_EP_ISO_HS_MULT - 1; | |
2001 | buffering = mult + 1; | |
2002 | } | |
2003 | ||
2004 | switch (priv_dev->gadget.speed) { | |
2005 | case USB_SPEED_FULL: | |
2006 | max_packet_size = is_iso_ep ? 1023 : 64; | |
2007 | break; | |
2008 | case USB_SPEED_HIGH: | |
2009 | max_packet_size = is_iso_ep ? 1024 : 512; | |
2010 | break; | |
2011 | case USB_SPEED_SUPER: | |
2012 | /* It's limitation that driver assumes in driver. */ | |
2013 | mult = 0; | |
2014 | max_packet_size = 1024; | |
2015 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) { | |
2016 | maxburst = CDNS3_EP_ISO_SS_BURST - 1; | |
2017 | buffering = (mult + 1) * | |
2018 | (maxburst + 1); | |
2019 | ||
2020 | if (priv_ep->interval > 1) | |
2021 | buffering++; | |
2022 | } else { | |
2023 | maxburst = CDNS3_EP_BUF_SIZE - 1; | |
2024 | } | |
2025 | break; | |
2026 | default: | |
2027 | /* all other speed are not supported */ | |
2028 | return; | |
2029 | } | |
2030 | ||
2031 | if (max_packet_size == 1024) | |
2032 | priv_ep->trb_burst_size = 128; | |
2033 | else if (max_packet_size >= 512) | |
2034 | priv_ep->trb_burst_size = 64; | |
2035 | else | |
2036 | priv_ep->trb_burst_size = 16; | |
2037 | ||
2038 | ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1, | |
2039 | !!priv_ep->dir); | |
2040 | if (ret) { | |
2041 | dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n"); | |
2042 | return; | |
2043 | } | |
2044 | ||
2045 | ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) | | |
2046 | EP_CFG_MULT(mult) | | |
2047 | EP_CFG_BUFFERING(buffering) | | |
2048 | EP_CFG_MAXBURST(maxburst); | |
2049 | ||
2050 | cdns3_select_ep(priv_dev, bEndpointAddress); | |
2051 | writel(ep_cfg, &priv_dev->regs->ep_cfg); | |
2052 | ||
2053 | dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n", | |
2054 | priv_ep->name, ep_cfg); | |
2055 | } | |
2056 | ||
2057 | /* Find correct direction for HW endpoint according to description */ | |
2058 | static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc, | |
2059 | struct cdns3_endpoint *priv_ep) | |
2060 | { | |
2061 | return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) || | |
2062 | (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc)); | |
2063 | } | |
2064 | ||
2065 | static struct | |
2066 | cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev, | |
2067 | struct usb_endpoint_descriptor *desc) | |
2068 | { | |
2069 | struct usb_ep *ep; | |
2070 | struct cdns3_endpoint *priv_ep; | |
2071 | ||
2072 | list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { | |
2073 | unsigned long num; | |
2074 | int ret; | |
2075 | /* ep name pattern likes epXin or epXout */ | |
2076 | char c[2] = {ep->name[2], '\0'}; | |
2077 | ||
2078 | ret = kstrtoul(c, 10, &num); | |
2079 | if (ret) | |
2080 | return ERR_PTR(ret); | |
2081 | ||
2082 | priv_ep = ep_to_cdns3_ep(ep); | |
2083 | if (cdns3_ep_dir_is_correct(desc, priv_ep)) { | |
2084 | if (!(priv_ep->flags & EP_CLAIMED)) { | |
2085 | priv_ep->num = num; | |
2086 | return priv_ep; | |
2087 | } | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | return ERR_PTR(-ENOENT); | |
2092 | } | |
2093 | ||
2094 | /* | |
2095 | * Cadence IP has one limitation that all endpoints must be configured | |
2096 | * (Type & MaxPacketSize) before setting configuration through hardware | |
2097 | * register, it means we can't change endpoints configuration after | |
2098 | * set_configuration. | |
2099 | * | |
2100 | * This function set EP_CLAIMED flag which is added when the gadget driver | |
2101 | * uses usb_ep_autoconfig to configure specific endpoint; | |
2102 | * When the udc driver receives set_configurion request, | |
2103 | * it goes through all claimed endpoints, and configure all endpoints | |
2104 | * accordingly. | |
2105 | * | |
2106 | * At usb_ep_ops.enable/disable, we only enable and disable endpoint through | |
2107 | * ep_cfg register which can be changed after set_configuration, and do | |
2108 | * some software operation accordingly. | |
2109 | */ | |
2110 | static struct | |
2111 | usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget, | |
2112 | struct usb_endpoint_descriptor *desc, | |
2113 | struct usb_ss_ep_comp_descriptor *comp_desc) | |
2114 | { | |
2115 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2116 | struct cdns3_endpoint *priv_ep; | |
2117 | unsigned long flags; | |
2118 | ||
2119 | priv_ep = cdns3_find_available_ep(priv_dev, desc); | |
2120 | if (IS_ERR(priv_ep)) { | |
2121 | dev_err(priv_dev->dev, "no available ep\n"); | |
2122 | return NULL; | |
2123 | } | |
2124 | ||
2125 | dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name); | |
2126 | ||
2127 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2128 | priv_ep->endpoint.desc = desc; | |
2129 | priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT; | |
2130 | priv_ep->type = usb_endpoint_type(desc); | |
2131 | priv_ep->flags |= EP_CLAIMED; | |
2132 | priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; | |
2133 | ||
2134 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2135 | return &priv_ep->endpoint; | |
2136 | } | |
2137 | ||
2138 | /** | |
2139 | * cdns3_gadget_ep_alloc_request Allocates request | |
2140 | * @ep: endpoint object associated with request | |
2141 | * @gfp_flags: gfp flags | |
2142 | * | |
2143 | * Returns allocated request address, NULL on allocation error | |
2144 | */ | |
2145 | struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, | |
2146 | gfp_t gfp_flags) | |
2147 | { | |
2148 | struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); | |
2149 | struct cdns3_request *priv_req; | |
2150 | ||
2151 | priv_req = kzalloc(sizeof(*priv_req), gfp_flags); | |
2152 | if (!priv_req) | |
2153 | return NULL; | |
2154 | ||
2155 | priv_req->priv_ep = priv_ep; | |
2156 | ||
2157 | trace_cdns3_alloc_request(priv_req); | |
2158 | return &priv_req->request; | |
2159 | } | |
2160 | ||
2161 | /** | |
2162 | * cdns3_gadget_ep_free_request Free memory occupied by request | |
2163 | * @ep: endpoint object associated with request | |
2164 | * @request: request to free memory | |
2165 | */ | |
2166 | void cdns3_gadget_ep_free_request(struct usb_ep *ep, | |
2167 | struct usb_request *request) | |
2168 | { | |
2169 | struct cdns3_request *priv_req = to_cdns3_request(request); | |
2170 | ||
2171 | if (priv_req->aligned_buf) | |
2172 | priv_req->aligned_buf->in_use = 0; | |
2173 | ||
2174 | trace_cdns3_free_request(priv_req); | |
2175 | kfree(priv_req); | |
2176 | } | |
2177 | ||
2178 | /** | |
2179 | * cdns3_gadget_ep_enable Enable endpoint | |
2180 | * @ep: endpoint object | |
2181 | * @desc: endpoint descriptor | |
2182 | * | |
2183 | * Returns 0 on success, error code elsewhere | |
2184 | */ | |
2185 | static int cdns3_gadget_ep_enable(struct usb_ep *ep, | |
2186 | const struct usb_endpoint_descriptor *desc) | |
2187 | { | |
2188 | struct cdns3_endpoint *priv_ep; | |
2189 | struct cdns3_device *priv_dev; | |
54c4c69f | 2190 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
7733f6c3 PL |
2191 | u32 reg = EP_STS_EN_TRBERREN; |
2192 | u32 bEndpointAddress; | |
2193 | unsigned long flags; | |
2194 | int enable = 1; | |
2195 | int ret; | |
2196 | int val; | |
2197 | ||
2198 | priv_ep = ep_to_cdns3_ep(ep); | |
2199 | priv_dev = priv_ep->cdns3_dev; | |
54c4c69f | 2200 | comp_desc = priv_ep->endpoint.comp_desc; |
7733f6c3 PL |
2201 | |
2202 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
2203 | dev_dbg(priv_dev->dev, "usbss: invalid parameters\n"); | |
2204 | return -EINVAL; | |
2205 | } | |
2206 | ||
2207 | if (!desc->wMaxPacketSize) { | |
2208 | dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n"); | |
2209 | return -EINVAL; | |
2210 | } | |
2211 | ||
2212 | if (dev_WARN_ONCE(priv_dev->dev, priv_ep->flags & EP_ENABLED, | |
2213 | "%s is already enabled\n", priv_ep->name)) | |
2214 | return 0; | |
2215 | ||
2216 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2217 | ||
2218 | priv_ep->endpoint.desc = desc; | |
2219 | priv_ep->type = usb_endpoint_type(desc); | |
2220 | priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; | |
2221 | ||
2222 | if (priv_ep->interval > ISO_MAX_INTERVAL && | |
2223 | priv_ep->type == USB_ENDPOINT_XFER_ISOC) { | |
2224 | dev_err(priv_dev->dev, "Driver is limited to %d period\n", | |
2225 | ISO_MAX_INTERVAL); | |
2226 | ||
2227 | ret = -EINVAL; | |
2228 | goto exit; | |
2229 | } | |
2230 | ||
54c4c69f JP |
2231 | bEndpointAddress = priv_ep->num | priv_ep->dir; |
2232 | cdns3_select_ep(priv_dev, bEndpointAddress); | |
2233 | ||
2234 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { | |
2235 | /* | |
2236 | * Enable stream support (SS mode) related interrupts | |
2237 | * in EP_STS_EN Register | |
2238 | */ | |
2239 | if (priv_dev->gadget.speed >= USB_SPEED_SUPER) { | |
2240 | reg |= EP_STS_EN_IOTEN | EP_STS_EN_PRIMEEEN | | |
2241 | EP_STS_EN_SIDERREN | EP_STS_EN_MD_EXITEN | | |
2242 | EP_STS_EN_STREAMREN; | |
2243 | priv_ep->use_streams = true; | |
2244 | cdns3_stream_ep_reconfig(priv_dev, priv_ep); | |
2245 | priv_dev->using_streams |= true; | |
2246 | } | |
2247 | } | |
2248 | ||
7733f6c3 PL |
2249 | ret = cdns3_allocate_trb_pool(priv_ep); |
2250 | ||
2251 | if (ret) | |
2252 | goto exit; | |
2253 | ||
2254 | bEndpointAddress = priv_ep->num | priv_ep->dir; | |
2255 | cdns3_select_ep(priv_dev, bEndpointAddress); | |
2256 | ||
2257 | trace_cdns3_gadget_ep_enable(priv_ep); | |
2258 | ||
2259 | writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); | |
2260 | ||
2261 | ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, | |
2262 | !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), | |
2263 | 1, 1000); | |
2264 | ||
2265 | if (unlikely(ret)) { | |
2266 | cdns3_free_trb_pool(priv_ep); | |
2267 | ret = -EINVAL; | |
2268 | goto exit; | |
2269 | } | |
2270 | ||
2271 | /* enable interrupt for selected endpoint */ | |
2272 | cdns3_set_register_bit(&priv_dev->regs->ep_ien, | |
2273 | BIT(cdns3_ep_addr_to_index(bEndpointAddress))); | |
2274 | ||
6bbf87a1 PL |
2275 | if (priv_dev->dev_ver < DEV_VER_V2) |
2276 | cdns3_wa2_enable_detection(priv_dev, priv_ep, reg); | |
2277 | ||
7733f6c3 PL |
2278 | writel(reg, &priv_dev->regs->ep_sts_en); |
2279 | ||
2280 | /* | |
2281 | * For some versions of controller at some point during ISO OUT traffic | |
2282 | * DMA reads Transfer Ring for the EP which has never got doorbell. | |
2283 | * This issue was detected only on simulation, but to avoid this issue | |
2284 | * driver add protection against it. To fix it driver enable ISO OUT | |
2285 | * endpoint before setting DRBL. This special treatment of ISO OUT | |
2286 | * endpoints are recommended by controller specification. | |
2287 | */ | |
2288 | if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) | |
2289 | enable = 0; | |
2290 | ||
2291 | if (enable) | |
2292 | cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE); | |
2293 | ||
2294 | ep->desc = desc; | |
2295 | priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING | | |
6bbf87a1 | 2296 | EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN); |
7733f6c3 PL |
2297 | priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR; |
2298 | priv_ep->wa1_set = 0; | |
2299 | priv_ep->enqueue = 0; | |
2300 | priv_ep->dequeue = 0; | |
2301 | reg = readl(&priv_dev->regs->ep_sts); | |
2302 | priv_ep->pcs = !!EP_STS_CCS(reg); | |
2303 | priv_ep->ccs = !!EP_STS_CCS(reg); | |
2304 | /* one TRB is reserved for link TRB used in DMULT mode*/ | |
2305 | priv_ep->free_trbs = priv_ep->num_trbs - 1; | |
2306 | exit: | |
2307 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2308 | ||
2309 | return ret; | |
2310 | } | |
2311 | ||
2312 | /** | |
2313 | * cdns3_gadget_ep_disable Disable endpoint | |
2314 | * @ep: endpoint object | |
2315 | * | |
2316 | * Returns 0 on success, error code elsewhere | |
2317 | */ | |
2318 | static int cdns3_gadget_ep_disable(struct usb_ep *ep) | |
2319 | { | |
2320 | struct cdns3_endpoint *priv_ep; | |
6bbf87a1 | 2321 | struct cdns3_request *priv_req; |
7733f6c3 PL |
2322 | struct cdns3_device *priv_dev; |
2323 | struct usb_request *request; | |
2324 | unsigned long flags; | |
2325 | int ret = 0; | |
2326 | u32 ep_cfg; | |
2327 | int val; | |
2328 | ||
2329 | if (!ep) { | |
2330 | pr_err("usbss: invalid parameters\n"); | |
2331 | return -EINVAL; | |
2332 | } | |
2333 | ||
2334 | priv_ep = ep_to_cdns3_ep(ep); | |
2335 | priv_dev = priv_ep->cdns3_dev; | |
2336 | ||
2337 | if (dev_WARN_ONCE(priv_dev->dev, !(priv_ep->flags & EP_ENABLED), | |
2338 | "%s is already disabled\n", priv_ep->name)) | |
2339 | return 0; | |
2340 | ||
2341 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2342 | ||
2343 | trace_cdns3_gadget_ep_disable(priv_ep); | |
2344 | ||
2345 | cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); | |
2346 | ||
2347 | ep_cfg = readl(&priv_dev->regs->ep_cfg); | |
2348 | ep_cfg &= ~EP_CFG_ENABLE; | |
2349 | writel(ep_cfg, &priv_dev->regs->ep_cfg); | |
2350 | ||
2351 | /** | |
2352 | * Driver needs some time before resetting endpoint. | |
2353 | * It need waits for clearing DBUSY bit or for timeout expired. | |
2354 | * 10us is enough time for controller to stop transfer. | |
2355 | */ | |
2356 | readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val, | |
2357 | !(val & EP_STS_DBUSY), 1, 10); | |
2358 | writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); | |
2359 | ||
2360 | readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, | |
2361 | !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), | |
2362 | 1, 1000); | |
2363 | if (unlikely(ret)) | |
2364 | dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n", | |
2365 | priv_ep->name); | |
2366 | ||
2367 | while (!list_empty(&priv_ep->pending_req_list)) { | |
2368 | request = cdns3_next_request(&priv_ep->pending_req_list); | |
2369 | ||
2370 | cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), | |
2371 | -ESHUTDOWN); | |
2372 | } | |
2373 | ||
6bbf87a1 PL |
2374 | while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { |
2375 | priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); | |
2376 | ||
2377 | kfree(priv_req->request.buf); | |
2378 | cdns3_gadget_ep_free_request(&priv_ep->endpoint, | |
2379 | &priv_req->request); | |
2380 | list_del_init(&priv_req->list); | |
2381 | --priv_ep->wa2_counter; | |
2382 | } | |
2383 | ||
7733f6c3 PL |
2384 | while (!list_empty(&priv_ep->deferred_req_list)) { |
2385 | request = cdns3_next_request(&priv_ep->deferred_req_list); | |
2386 | ||
2387 | cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), | |
2388 | -ESHUTDOWN); | |
2389 | } | |
2390 | ||
6bbf87a1 PL |
2391 | priv_ep->descmis_req = NULL; |
2392 | ||
7733f6c3 PL |
2393 | ep->desc = NULL; |
2394 | priv_ep->flags &= ~EP_ENABLED; | |
54c4c69f | 2395 | priv_ep->use_streams = false; |
7733f6c3 PL |
2396 | |
2397 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2398 | ||
2399 | return ret; | |
2400 | } | |
2401 | ||
2402 | /** | |
2403 | * cdns3_gadget_ep_queue Transfer data on endpoint | |
2404 | * @ep: endpoint object | |
2405 | * @request: request object | |
2406 | * @gfp_flags: gfp flags | |
2407 | * | |
2408 | * Returns 0 on success, error code elsewhere | |
2409 | */ | |
2410 | static int __cdns3_gadget_ep_queue(struct usb_ep *ep, | |
2411 | struct usb_request *request, | |
2412 | gfp_t gfp_flags) | |
2413 | { | |
2414 | struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); | |
2415 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
2416 | struct cdns3_request *priv_req; | |
2417 | int ret = 0; | |
2418 | ||
2419 | request->actual = 0; | |
2420 | request->status = -EINPROGRESS; | |
2421 | priv_req = to_cdns3_request(request); | |
2422 | trace_cdns3_ep_queue(priv_req); | |
2423 | ||
6bbf87a1 PL |
2424 | if (priv_dev->dev_ver < DEV_VER_V2) { |
2425 | ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep, | |
2426 | priv_req); | |
2427 | ||
2428 | if (ret == EINPROGRESS) | |
2429 | return 0; | |
2430 | } | |
2431 | ||
7733f6c3 PL |
2432 | ret = cdns3_prepare_aligned_request_buf(priv_req); |
2433 | if (ret < 0) | |
2434 | return ret; | |
2435 | ||
2436 | ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request, | |
2437 | usb_endpoint_dir_in(ep->desc)); | |
2438 | if (ret) | |
2439 | return ret; | |
2440 | ||
2441 | list_add_tail(&request->list, &priv_ep->deferred_req_list); | |
2442 | ||
2443 | /* | |
54c4c69f JP |
2444 | * For stream capable endpoint if prime irq flag is set then only start |
2445 | * request. | |
7733f6c3 PL |
2446 | * If hardware endpoint configuration has not been set yet then |
2447 | * just queue request in deferred list. Transfer will be started in | |
2448 | * cdns3_set_hw_configuration. | |
2449 | */ | |
54c4c69f JP |
2450 | if (!request->stream_id) { |
2451 | if (priv_dev->hw_configured_flag && | |
2452 | !(priv_ep->flags & EP_STALLED) && | |
2453 | !(priv_ep->flags & EP_STALL_PENDING)) | |
2454 | cdns3_start_all_request(priv_dev, priv_ep); | |
2455 | } else { | |
2456 | if (priv_dev->hw_configured_flag && priv_ep->prime_flag) | |
2457 | cdns3_start_all_request(priv_dev, priv_ep); | |
2458 | } | |
7733f6c3 PL |
2459 | |
2460 | return 0; | |
2461 | } | |
2462 | ||
2463 | static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
2464 | gfp_t gfp_flags) | |
2465 | { | |
2466 | struct usb_request *zlp_request; | |
2467 | struct cdns3_endpoint *priv_ep; | |
2468 | struct cdns3_device *priv_dev; | |
2469 | unsigned long flags; | |
2470 | int ret; | |
2471 | ||
2472 | if (!request || !ep) | |
2473 | return -EINVAL; | |
2474 | ||
2475 | priv_ep = ep_to_cdns3_ep(ep); | |
2476 | priv_dev = priv_ep->cdns3_dev; | |
2477 | ||
2478 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2479 | ||
2480 | ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags); | |
2481 | ||
2482 | if (ret == 0 && request->zero && request->length && | |
2483 | (request->length % ep->maxpacket == 0)) { | |
2484 | struct cdns3_request *priv_req; | |
2485 | ||
2486 | zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC); | |
2487 | zlp_request->buf = priv_dev->zlp_buf; | |
2488 | zlp_request->length = 0; | |
2489 | ||
2490 | priv_req = to_cdns3_request(zlp_request); | |
2491 | priv_req->flags |= REQUEST_ZLP; | |
2492 | ||
2493 | dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n", | |
2494 | priv_ep->name); | |
2495 | ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags); | |
2496 | } | |
2497 | ||
2498 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2499 | return ret; | |
2500 | } | |
2501 | ||
2502 | /** | |
2503 | * cdns3_gadget_ep_dequeue Remove request from transfer queue | |
2504 | * @ep: endpoint object associated with request | |
2505 | * @request: request object | |
2506 | * | |
2507 | * Returns 0 on success, error code elsewhere | |
2508 | */ | |
2509 | int cdns3_gadget_ep_dequeue(struct usb_ep *ep, | |
2510 | struct usb_request *request) | |
2511 | { | |
2512 | struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); | |
2513 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
2514 | struct usb_request *req, *req_temp; | |
2515 | struct cdns3_request *priv_req; | |
2516 | struct cdns3_trb *link_trb; | |
f616c3bd | 2517 | u8 req_on_hw_ring = 0; |
7733f6c3 PL |
2518 | unsigned long flags; |
2519 | int ret = 0; | |
2520 | ||
2521 | if (!ep || !request || !ep->desc) | |
2522 | return -EINVAL; | |
2523 | ||
2524 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2525 | ||
2526 | priv_req = to_cdns3_request(request); | |
2527 | ||
2528 | trace_cdns3_ep_dequeue(priv_req); | |
2529 | ||
2530 | cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); | |
2531 | ||
2532 | list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list, | |
2533 | list) { | |
f616c3bd PL |
2534 | if (request == req) { |
2535 | req_on_hw_ring = 1; | |
7733f6c3 | 2536 | goto found; |
f616c3bd | 2537 | } |
7733f6c3 PL |
2538 | } |
2539 | ||
2540 | list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list, | |
2541 | list) { | |
2542 | if (request == req) | |
2543 | goto found; | |
2544 | } | |
2545 | ||
2546 | goto not_found; | |
2547 | ||
2548 | found: | |
7733f6c3 | 2549 | link_trb = priv_req->trb; |
7733f6c3 | 2550 | |
f616c3bd | 2551 | /* Update ring only if removed request is on pending_req_list list */ |
95cd7dc4 | 2552 | if (req_on_hw_ring && link_trb) { |
8dafb3c0 PC |
2553 | link_trb->buffer = cpu_to_le32(TRB_BUFFER(priv_ep->trb_pool_dma + |
2554 | ((priv_req->end_trb + 1) * TRB_SIZE))); | |
2555 | link_trb->control = cpu_to_le32((le32_to_cpu(link_trb->control) & TRB_CYCLE) | | |
2556 | TRB_TYPE(TRB_LINK) | TRB_CHAIN); | |
f616c3bd PL |
2557 | |
2558 | if (priv_ep->wa1_trb == priv_req->trb) | |
2559 | cdns3_wa1_restore_cycle_bit(priv_ep); | |
7733f6c3 PL |
2560 | } |
2561 | ||
f616c3bd PL |
2562 | cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET); |
2563 | ||
7733f6c3 PL |
2564 | not_found: |
2565 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2566 | return ret; | |
2567 | } | |
2568 | ||
2569 | /** | |
2570 | * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint | |
2571 | * Should be called after acquiring spin_lock and selecting ep | |
4a35aa6d | 2572 | * @priv_ep: endpoint object to set stall on. |
7733f6c3 PL |
2573 | */ |
2574 | void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep) | |
2575 | { | |
2576 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
2577 | ||
2578 | trace_cdns3_halt(priv_ep, 1, 0); | |
2579 | ||
2580 | if (!(priv_ep->flags & EP_STALLED)) { | |
2581 | u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts); | |
2582 | ||
2583 | if (!(ep_sts_reg & EP_STS_DBUSY)) | |
2584 | cdns3_ep_stall_flush(priv_ep); | |
2585 | else | |
2586 | priv_ep->flags |= EP_STALL_PENDING; | |
2587 | } | |
2588 | } | |
2589 | ||
2590 | /** | |
2591 | * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint | |
2592 | * Should be called after acquiring spin_lock and selecting ep | |
4a35aa6d | 2593 | * @priv_ep: endpoint object to clear stall on |
7733f6c3 PL |
2594 | */ |
2595 | int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep) | |
2596 | { | |
2597 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
2598 | struct usb_request *request; | |
4bf2dd65 PC |
2599 | struct cdns3_request *priv_req; |
2600 | struct cdns3_trb *trb = NULL; | |
04db1d20 | 2601 | int ret; |
7733f6c3 PL |
2602 | int val; |
2603 | ||
2604 | trace_cdns3_halt(priv_ep, 0, 0); | |
2605 | ||
4bf2dd65 PC |
2606 | request = cdns3_next_request(&priv_ep->pending_req_list); |
2607 | if (request) { | |
2608 | priv_req = to_cdns3_request(request); | |
2609 | trb = priv_req->trb; | |
2610 | if (trb) | |
8dafb3c0 | 2611 | trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE); |
4bf2dd65 PC |
2612 | } |
2613 | ||
7733f6c3 PL |
2614 | writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd); |
2615 | ||
2616 | /* wait for EPRST cleared */ | |
04db1d20 CIK |
2617 | ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, |
2618 | !(val & EP_CMD_EPRST), 1, 100); | |
7733f6c3 PL |
2619 | if (ret) |
2620 | return -EINVAL; | |
2621 | ||
2622 | priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING); | |
2623 | ||
4bf2dd65 PC |
2624 | if (request) { |
2625 | if (trb) | |
8dafb3c0 PC |
2626 | trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE); |
2627 | ||
7733f6c3 | 2628 | cdns3_rearm_transfer(priv_ep, 1); |
4bf2dd65 | 2629 | } |
7733f6c3 PL |
2630 | |
2631 | cdns3_start_all_request(priv_dev, priv_ep); | |
2632 | return ret; | |
2633 | } | |
2634 | ||
2635 | /** | |
2636 | * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint | |
2637 | * @ep: endpoint object to set/clear stall on | |
2638 | * @value: 1 for set stall, 0 for clear stall | |
2639 | * | |
2640 | * Returns 0 on success, error code elsewhere | |
2641 | */ | |
2642 | int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
2643 | { | |
2644 | struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); | |
2645 | struct cdns3_device *priv_dev = priv_ep->cdns3_dev; | |
2646 | unsigned long flags; | |
2647 | int ret = 0; | |
2648 | ||
2649 | if (!(priv_ep->flags & EP_ENABLED)) | |
2650 | return -EPERM; | |
2651 | ||
2652 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2653 | ||
2654 | cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); | |
2655 | ||
2656 | if (!value) { | |
2657 | priv_ep->flags &= ~EP_WEDGE; | |
2658 | ret = __cdns3_gadget_ep_clear_halt(priv_ep); | |
2659 | } else { | |
2660 | __cdns3_gadget_ep_set_halt(priv_ep); | |
2661 | } | |
2662 | ||
2663 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2664 | ||
2665 | return ret; | |
2666 | } | |
2667 | ||
2668 | extern const struct usb_ep_ops cdns3_gadget_ep0_ops; | |
2669 | ||
2670 | static const struct usb_ep_ops cdns3_gadget_ep_ops = { | |
2671 | .enable = cdns3_gadget_ep_enable, | |
2672 | .disable = cdns3_gadget_ep_disable, | |
2673 | .alloc_request = cdns3_gadget_ep_alloc_request, | |
2674 | .free_request = cdns3_gadget_ep_free_request, | |
2675 | .queue = cdns3_gadget_ep_queue, | |
2676 | .dequeue = cdns3_gadget_ep_dequeue, | |
2677 | .set_halt = cdns3_gadget_ep_set_halt, | |
2678 | .set_wedge = cdns3_gadget_ep_set_wedge, | |
2679 | }; | |
2680 | ||
2681 | /** | |
2682 | * cdns3_gadget_get_frame Returns number of actual ITP frame | |
2683 | * @gadget: gadget object | |
2684 | * | |
2685 | * Returns number of actual ITP frame | |
2686 | */ | |
2687 | static int cdns3_gadget_get_frame(struct usb_gadget *gadget) | |
2688 | { | |
2689 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2690 | ||
2691 | return readl(&priv_dev->regs->usb_itpn); | |
2692 | } | |
2693 | ||
2694 | int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev) | |
2695 | { | |
2696 | enum usb_device_speed speed; | |
2697 | ||
2698 | speed = cdns3_get_speed(priv_dev); | |
2699 | ||
2700 | if (speed >= USB_SPEED_SUPER) | |
2701 | return 0; | |
2702 | ||
2703 | /* Start driving resume signaling to indicate remote wakeup. */ | |
2704 | writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf); | |
2705 | ||
2706 | return 0; | |
2707 | } | |
2708 | ||
2709 | static int cdns3_gadget_wakeup(struct usb_gadget *gadget) | |
2710 | { | |
2711 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2712 | unsigned long flags; | |
2713 | int ret = 0; | |
2714 | ||
2715 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2716 | ret = __cdns3_gadget_wakeup(priv_dev); | |
2717 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2718 | return ret; | |
2719 | } | |
2720 | ||
2721 | static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget, | |
2722 | int is_selfpowered) | |
2723 | { | |
2724 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2725 | unsigned long flags; | |
2726 | ||
2727 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2728 | priv_dev->is_selfpowered = !!is_selfpowered; | |
2729 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2730 | return 0; | |
2731 | } | |
2732 | ||
2733 | static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
2734 | { | |
2735 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2736 | ||
0eeda059 | 2737 | if (is_on) { |
7733f6c3 | 2738 | writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf); |
0eeda059 PC |
2739 | } else { |
2740 | writel(~0, &priv_dev->regs->ep_ists); | |
2741 | writel(~0, &priv_dev->regs->usb_ists); | |
7733f6c3 | 2742 | writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); |
0eeda059 | 2743 | } |
7733f6c3 PL |
2744 | |
2745 | return 0; | |
2746 | } | |
2747 | ||
2748 | static void cdns3_gadget_config(struct cdns3_device *priv_dev) | |
2749 | { | |
2750 | struct cdns3_usb_regs __iomem *regs = priv_dev->regs; | |
2751 | u32 reg; | |
2752 | ||
2753 | cdns3_ep0_config(priv_dev); | |
2754 | ||
2755 | /* enable interrupts for endpoint 0 (in and out) */ | |
2756 | writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, ®s->ep_ien); | |
2757 | ||
2758 | /* | |
2759 | * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1 | |
2760 | * revision of controller. | |
2761 | */ | |
2762 | if (priv_dev->dev_ver == DEV_VER_TI_V1) { | |
2763 | reg = readl(®s->dbg_link1); | |
2764 | ||
2765 | reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK; | |
2766 | reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) | | |
2767 | DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET; | |
2768 | writel(reg, ®s->dbg_link1); | |
2769 | } | |
2770 | ||
2771 | /* | |
2772 | * By default some platforms has set protected access to memory. | |
2773 | * This cause problem with cache, so driver restore non-secure | |
2774 | * access to memory. | |
2775 | */ | |
2776 | reg = readl(®s->dma_axi_ctrl); | |
2777 | reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) | | |
2778 | DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE); | |
2779 | writel(reg, ®s->dma_axi_ctrl); | |
2780 | ||
2781 | /* enable generic interrupt*/ | |
2782 | writel(USB_IEN_INIT, ®s->usb_ien); | |
2783 | writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf); | |
b5148d94 PC |
2784 | /* keep Fast Access bit */ |
2785 | writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr); | |
7733f6c3 PL |
2786 | |
2787 | cdns3_configure_dmult(priv_dev, NULL); | |
7733f6c3 PL |
2788 | } |
2789 | ||
2790 | /** | |
2791 | * cdns3_gadget_udc_start Gadget start | |
2792 | * @gadget: gadget object | |
2793 | * @driver: driver which operates on this gadget | |
2794 | * | |
2795 | * Returns 0 on success, error code elsewhere | |
2796 | */ | |
2797 | static int cdns3_gadget_udc_start(struct usb_gadget *gadget, | |
2798 | struct usb_gadget_driver *driver) | |
2799 | { | |
2800 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2801 | unsigned long flags; | |
94e259f8 | 2802 | enum usb_device_speed max_speed = driver->max_speed; |
7733f6c3 PL |
2803 | |
2804 | spin_lock_irqsave(&priv_dev->lock, flags); | |
2805 | priv_dev->gadget_driver = driver; | |
94e259f8 RQ |
2806 | |
2807 | /* limit speed if necessary */ | |
2808 | max_speed = min(driver->max_speed, gadget->max_speed); | |
2809 | ||
2810 | switch (max_speed) { | |
2811 | case USB_SPEED_FULL: | |
2812 | writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf); | |
2813 | writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf); | |
2814 | break; | |
2815 | case USB_SPEED_HIGH: | |
2816 | writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf); | |
2817 | break; | |
2818 | case USB_SPEED_SUPER: | |
2819 | break; | |
2820 | default: | |
2821 | dev_err(priv_dev->dev, | |
2822 | "invalid maximum_speed parameter %d\n", | |
2823 | max_speed); | |
0d9b6d49 | 2824 | fallthrough; |
94e259f8 RQ |
2825 | case USB_SPEED_UNKNOWN: |
2826 | /* default to superspeed */ | |
2827 | max_speed = USB_SPEED_SUPER; | |
2828 | break; | |
2829 | } | |
2830 | ||
7733f6c3 PL |
2831 | cdns3_gadget_config(priv_dev); |
2832 | spin_unlock_irqrestore(&priv_dev->lock, flags); | |
2833 | return 0; | |
2834 | } | |
2835 | ||
2836 | /** | |
2837 | * cdns3_gadget_udc_stop Stops gadget | |
2838 | * @gadget: gadget object | |
2839 | * | |
2840 | * Returns 0 | |
2841 | */ | |
2842 | static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) | |
2843 | { | |
2844 | struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); | |
2845 | struct cdns3_endpoint *priv_ep; | |
2846 | u32 bEndpointAddress; | |
2847 | struct usb_ep *ep; | |
7733f6c3 PL |
2848 | int val; |
2849 | ||
2850 | priv_dev->gadget_driver = NULL; | |
2851 | ||
2852 | priv_dev->onchip_used_size = 0; | |
2853 | priv_dev->out_mem_is_allocated = 0; | |
2854 | priv_dev->gadget.speed = USB_SPEED_UNKNOWN; | |
2855 | ||
2856 | list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { | |
2857 | priv_ep = ep_to_cdns3_ep(ep); | |
2858 | bEndpointAddress = priv_ep->num | priv_ep->dir; | |
2859 | cdns3_select_ep(priv_dev, bEndpointAddress); | |
2860 | writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); | |
2861 | readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, | |
2862 | !(val & EP_CMD_EPRST), 1, 100); | |
f5c8d290 SP |
2863 | |
2864 | priv_ep->flags &= ~EP_CLAIMED; | |
7733f6c3 PL |
2865 | } |
2866 | ||
2867 | /* disable interrupt for device */ | |
2868 | writel(0, &priv_dev->regs->usb_ien); | |
b5148d94 | 2869 | writel(0, &priv_dev->regs->usb_pwr); |
7733f6c3 PL |
2870 | writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); |
2871 | ||
8e1a2009 | 2872 | return 0; |
7733f6c3 PL |
2873 | } |
2874 | ||
2875 | static const struct usb_gadget_ops cdns3_gadget_ops = { | |
2876 | .get_frame = cdns3_gadget_get_frame, | |
2877 | .wakeup = cdns3_gadget_wakeup, | |
2878 | .set_selfpowered = cdns3_gadget_set_selfpowered, | |
2879 | .pullup = cdns3_gadget_pullup, | |
2880 | .udc_start = cdns3_gadget_udc_start, | |
2881 | .udc_stop = cdns3_gadget_udc_stop, | |
2882 | .match_ep = cdns3_gadget_match_ep, | |
2883 | }; | |
2884 | ||
2885 | static void cdns3_free_all_eps(struct cdns3_device *priv_dev) | |
2886 | { | |
2887 | int i; | |
2888 | ||
2889 | /* ep0 OUT point to ep0 IN. */ | |
2890 | priv_dev->eps[16] = NULL; | |
2891 | ||
2892 | for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) | |
2893 | if (priv_dev->eps[i]) { | |
2894 | cdns3_free_trb_pool(priv_dev->eps[i]); | |
2895 | devm_kfree(priv_dev->dev, priv_dev->eps[i]); | |
2896 | } | |
2897 | } | |
2898 | ||
2899 | /** | |
2900 | * cdns3_init_eps Initializes software endpoints of gadget | |
4a35aa6d | 2901 | * @priv_dev: extended gadget object |
7733f6c3 PL |
2902 | * |
2903 | * Returns 0 on success, error code elsewhere | |
2904 | */ | |
2905 | static int cdns3_init_eps(struct cdns3_device *priv_dev) | |
2906 | { | |
2907 | u32 ep_enabled_reg, iso_ep_reg; | |
2908 | struct cdns3_endpoint *priv_ep; | |
2909 | int ep_dir, ep_number; | |
2910 | u32 ep_mask; | |
2911 | int ret = 0; | |
2912 | int i; | |
2913 | ||
2914 | /* Read it from USB_CAP3 to USB_CAP5 */ | |
2915 | ep_enabled_reg = readl(&priv_dev->regs->usb_cap3); | |
2916 | iso_ep_reg = readl(&priv_dev->regs->usb_cap4); | |
2917 | ||
2918 | dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n"); | |
2919 | ||
2920 | for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) { | |
2921 | ep_dir = i >> 4; /* i div 16 */ | |
2922 | ep_number = i & 0xF; /* i % 16 */ | |
2923 | ep_mask = BIT(i); | |
2924 | ||
2925 | if (!(ep_enabled_reg & ep_mask)) | |
2926 | continue; | |
2927 | ||
2928 | if (ep_dir && !ep_number) { | |
2929 | priv_dev->eps[i] = priv_dev->eps[0]; | |
2930 | continue; | |
2931 | } | |
2932 | ||
2933 | priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep), | |
2934 | GFP_KERNEL); | |
4d2233ec | 2935 | if (!priv_ep) |
7733f6c3 | 2936 | goto err; |
7733f6c3 PL |
2937 | |
2938 | /* set parent of endpoint object */ | |
2939 | priv_ep->cdns3_dev = priv_dev; | |
2940 | priv_dev->eps[i] = priv_ep; | |
2941 | priv_ep->num = ep_number; | |
2942 | priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT; | |
2943 | ||
2944 | if (!ep_number) { | |
2945 | ret = cdns3_init_ep0(priv_dev, priv_ep); | |
2946 | if (ret) { | |
2947 | dev_err(priv_dev->dev, "Failed to init ep0\n"); | |
2948 | goto err; | |
2949 | } | |
2950 | } else { | |
2951 | snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s", | |
2952 | ep_number, !!ep_dir ? "in" : "out"); | |
2953 | priv_ep->endpoint.name = priv_ep->name; | |
2954 | ||
2955 | usb_ep_set_maxpacket_limit(&priv_ep->endpoint, | |
2956 | CDNS3_EP_MAX_PACKET_LIMIT); | |
2957 | priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS; | |
2958 | priv_ep->endpoint.ops = &cdns3_gadget_ep_ops; | |
2959 | if (ep_dir) | |
2960 | priv_ep->endpoint.caps.dir_in = 1; | |
2961 | else | |
2962 | priv_ep->endpoint.caps.dir_out = 1; | |
2963 | ||
2964 | if (iso_ep_reg & ep_mask) | |
2965 | priv_ep->endpoint.caps.type_iso = 1; | |
2966 | ||
2967 | priv_ep->endpoint.caps.type_bulk = 1; | |
2968 | priv_ep->endpoint.caps.type_int = 1; | |
2969 | ||
2970 | list_add_tail(&priv_ep->endpoint.ep_list, | |
2971 | &priv_dev->gadget.ep_list); | |
2972 | } | |
2973 | ||
2974 | priv_ep->flags = 0; | |
2975 | ||
eed6ed6e | 2976 | dev_dbg(priv_dev->dev, "Initialized %s support: %s %s\n", |
7733f6c3 PL |
2977 | priv_ep->name, |
2978 | priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "", | |
2979 | priv_ep->endpoint.caps.type_iso ? "ISO" : ""); | |
2980 | ||
2981 | INIT_LIST_HEAD(&priv_ep->pending_req_list); | |
2982 | INIT_LIST_HEAD(&priv_ep->deferred_req_list); | |
6bbf87a1 | 2983 | INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list); |
7733f6c3 PL |
2984 | } |
2985 | ||
2986 | return 0; | |
2987 | err: | |
2988 | cdns3_free_all_eps(priv_dev); | |
2989 | return -ENOMEM; | |
2990 | } | |
2991 | ||
2992 | void cdns3_gadget_exit(struct cdns3 *cdns) | |
2993 | { | |
2994 | struct cdns3_device *priv_dev; | |
2995 | ||
2996 | priv_dev = cdns->gadget_dev; | |
2997 | ||
7733f6c3 PL |
2998 | |
2999 | pm_runtime_mark_last_busy(cdns->dev); | |
3000 | pm_runtime_put_autosuspend(cdns->dev); | |
3001 | ||
3002 | usb_del_gadget_udc(&priv_dev->gadget); | |
98df91f8 | 3003 | devm_free_irq(cdns->dev, cdns->dev_irq, priv_dev); |
7733f6c3 PL |
3004 | |
3005 | cdns3_free_all_eps(priv_dev); | |
3006 | ||
3007 | while (!list_empty(&priv_dev->aligned_buf_list)) { | |
3008 | struct cdns3_aligned_buf *buf; | |
3009 | ||
3010 | buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list); | |
3011 | dma_free_coherent(priv_dev->sysdev, buf->size, | |
3012 | buf->buf, | |
3013 | buf->dma); | |
3014 | ||
3015 | list_del(&buf->list); | |
3016 | kfree(buf); | |
3017 | } | |
3018 | ||
3019 | dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf, | |
3020 | priv_dev->setup_dma); | |
3021 | ||
3022 | kfree(priv_dev->zlp_buf); | |
3023 | kfree(priv_dev); | |
3024 | cdns->gadget_dev = NULL; | |
b2aeb6da | 3025 | cdns3_drd_gadget_off(cdns); |
7733f6c3 PL |
3026 | } |
3027 | ||
3028 | static int cdns3_gadget_start(struct cdns3 *cdns) | |
3029 | { | |
3030 | struct cdns3_device *priv_dev; | |
3031 | u32 max_speed; | |
3032 | int ret; | |
3033 | ||
3034 | priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL); | |
3035 | if (!priv_dev) | |
3036 | return -ENOMEM; | |
3037 | ||
3038 | cdns->gadget_dev = priv_dev; | |
3039 | priv_dev->sysdev = cdns->dev; | |
3040 | priv_dev->dev = cdns->dev; | |
3041 | priv_dev->regs = cdns->dev_regs; | |
3042 | ||
3043 | device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size", | |
3044 | &priv_dev->onchip_buffers); | |
3045 | ||
3046 | if (priv_dev->onchip_buffers <= 0) { | |
3047 | u32 reg = readl(&priv_dev->regs->usb_cap2); | |
3048 | ||
3049 | priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg); | |
3050 | } | |
3051 | ||
3052 | if (!priv_dev->onchip_buffers) | |
3053 | priv_dev->onchip_buffers = 256; | |
3054 | ||
3055 | max_speed = usb_get_maximum_speed(cdns->dev); | |
3056 | ||
3057 | /* Check the maximum_speed parameter */ | |
3058 | switch (max_speed) { | |
3059 | case USB_SPEED_FULL: | |
7733f6c3 | 3060 | case USB_SPEED_HIGH: |
7733f6c3 PL |
3061 | case USB_SPEED_SUPER: |
3062 | break; | |
3063 | default: | |
3064 | dev_err(cdns->dev, "invalid maximum_speed parameter %d\n", | |
3065 | max_speed); | |
0d9b6d49 | 3066 | fallthrough; |
7733f6c3 PL |
3067 | case USB_SPEED_UNKNOWN: |
3068 | /* default to superspeed */ | |
3069 | max_speed = USB_SPEED_SUPER; | |
3070 | break; | |
3071 | } | |
3072 | ||
3073 | /* fill gadget fields */ | |
3074 | priv_dev->gadget.max_speed = max_speed; | |
3075 | priv_dev->gadget.speed = USB_SPEED_UNKNOWN; | |
3076 | priv_dev->gadget.ops = &cdns3_gadget_ops; | |
3077 | priv_dev->gadget.name = "usb-ss-gadget"; | |
3078 | priv_dev->gadget.sg_supported = 1; | |
3079 | priv_dev->gadget.quirk_avoids_skb_reserve = 1; | |
77f30ff4 | 3080 | priv_dev->gadget.irq = cdns->dev_irq; |
7733f6c3 PL |
3081 | |
3082 | spin_lock_init(&priv_dev->lock); | |
3083 | INIT_WORK(&priv_dev->pending_status_wq, | |
3084 | cdns3_pending_setup_status_handler); | |
3085 | ||
3086 | INIT_WORK(&priv_dev->aligned_buf_wq, | |
3087 | cdns3_free_aligned_request_buf); | |
3088 | ||
3089 | /* initialize endpoint container */ | |
3090 | INIT_LIST_HEAD(&priv_dev->gadget.ep_list); | |
3091 | INIT_LIST_HEAD(&priv_dev->aligned_buf_list); | |
3092 | ||
3093 | ret = cdns3_init_eps(priv_dev); | |
3094 | if (ret) { | |
3095 | dev_err(priv_dev->dev, "Failed to create endpoints\n"); | |
3096 | goto err1; | |
3097 | } | |
3098 | ||
3099 | /* allocate memory for setup packet buffer */ | |
3100 | priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8, | |
3101 | &priv_dev->setup_dma, GFP_DMA); | |
3102 | if (!priv_dev->setup_buf) { | |
3103 | ret = -ENOMEM; | |
3104 | goto err2; | |
3105 | } | |
3106 | ||
3107 | priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6); | |
3108 | ||
3109 | dev_dbg(priv_dev->dev, "Device Controller version: %08x\n", | |
3110 | readl(&priv_dev->regs->usb_cap6)); | |
3111 | dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n", | |
3112 | readl(&priv_dev->regs->usb_cap1)); | |
5d04111d | 3113 | dev_dbg(priv_dev->dev, "On-Chip memory configuration: %08x\n", |
7733f6c3 PL |
3114 | readl(&priv_dev->regs->usb_cap2)); |
3115 | ||
3116 | priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver); | |
3117 | ||
3118 | priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL); | |
3119 | if (!priv_dev->zlp_buf) { | |
3120 | ret = -ENOMEM; | |
3121 | goto err3; | |
3122 | } | |
3123 | ||
3124 | /* add USB gadget device */ | |
3125 | ret = usb_add_gadget_udc(priv_dev->dev, &priv_dev->gadget); | |
3126 | if (ret < 0) { | |
3127 | dev_err(priv_dev->dev, | |
3128 | "Failed to register USB device controller\n"); | |
3129 | goto err4; | |
3130 | } | |
3131 | ||
3132 | return 0; | |
3133 | err4: | |
3134 | kfree(priv_dev->zlp_buf); | |
3135 | err3: | |
3136 | dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf, | |
3137 | priv_dev->setup_dma); | |
3138 | err2: | |
3139 | cdns3_free_all_eps(priv_dev); | |
3140 | err1: | |
3141 | cdns->gadget_dev = NULL; | |
3142 | return ret; | |
3143 | } | |
3144 | ||
3145 | static int __cdns3_gadget_init(struct cdns3 *cdns) | |
3146 | { | |
7733f6c3 PL |
3147 | int ret = 0; |
3148 | ||
eb21a74a PL |
3149 | /* Ensure 32-bit DMA Mask in case we switched back from Host mode */ |
3150 | ret = dma_set_mask_and_coherent(cdns->dev, DMA_BIT_MASK(32)); | |
3151 | if (ret) { | |
3152 | dev_err(cdns->dev, "Failed to set dma mask: %d\n", ret); | |
3153 | return ret; | |
3154 | } | |
3155 | ||
b2aeb6da | 3156 | cdns3_drd_gadget_on(cdns); |
7733f6c3 PL |
3157 | pm_runtime_get_sync(cdns->dev); |
3158 | ||
3159 | ret = cdns3_gadget_start(cdns); | |
3160 | if (ret) | |
3161 | return ret; | |
3162 | ||
7733f6c3 PL |
3163 | /* |
3164 | * Because interrupt line can be shared with other components in | |
3165 | * driver it can't use IRQF_ONESHOT flag here. | |
3166 | */ | |
3167 | ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq, | |
3168 | cdns3_device_irq_handler, | |
3169 | cdns3_device_thread_irq_handler, | |
af58e1fc PC |
3170 | IRQF_SHARED, dev_name(cdns->dev), |
3171 | cdns->gadget_dev); | |
7733f6c3 PL |
3172 | |
3173 | if (ret) | |
3174 | goto err0; | |
3175 | ||
3176 | return 0; | |
3177 | err0: | |
3178 | cdns3_gadget_exit(cdns); | |
3179 | return ret; | |
3180 | } | |
3181 | ||
3182 | static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup) | |
3183 | { | |
3184 | struct cdns3_device *priv_dev = cdns->gadget_dev; | |
3185 | ||
3186 | cdns3_disconnect_gadget(priv_dev); | |
3187 | ||
3188 | priv_dev->gadget.speed = USB_SPEED_UNKNOWN; | |
3189 | usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED); | |
3190 | cdns3_hw_reset_eps_config(priv_dev); | |
3191 | ||
3192 | /* disable interrupt for device */ | |
3193 | writel(0, &priv_dev->regs->usb_ien); | |
3194 | ||
7733f6c3 PL |
3195 | return 0; |
3196 | } | |
3197 | ||
3198 | static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated) | |
3199 | { | |
3200 | struct cdns3_device *priv_dev = cdns->gadget_dev; | |
3201 | ||
3202 | if (!priv_dev->gadget_driver) | |
3203 | return 0; | |
3204 | ||
3205 | cdns3_gadget_config(priv_dev); | |
3206 | ||
3207 | return 0; | |
3208 | } | |
3209 | ||
3210 | /** | |
3211 | * cdns3_gadget_init - initialize device structure | |
3212 | * | |
4a35aa6d | 3213 | * @cdns: cdns3 instance |
7733f6c3 PL |
3214 | * |
3215 | * This function initializes the gadget. | |
3216 | */ | |
3217 | int cdns3_gadget_init(struct cdns3 *cdns) | |
3218 | { | |
3219 | struct cdns3_role_driver *rdrv; | |
3220 | ||
3221 | rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); | |
3222 | if (!rdrv) | |
3223 | return -ENOMEM; | |
3224 | ||
3225 | rdrv->start = __cdns3_gadget_init; | |
3226 | rdrv->stop = cdns3_gadget_exit; | |
3227 | rdrv->suspend = cdns3_gadget_suspend; | |
3228 | rdrv->resume = cdns3_gadget_resume; | |
3229 | rdrv->state = CDNS3_ROLE_STATE_INACTIVE; | |
3230 | rdrv->name = "gadget"; | |
3231 | cdns->roles[USB_ROLE_DEVICE] = rdrv; | |
3232 | ||
3233 | return 0; | |
3234 | } |