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e443b333 AS |
1 | /* |
2 | * bits.h - register bits of the ChipIdea USB IP core | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H | |
14 | #define __DRIVERS_USB_CHIPIDEA_BITS_H | |
15 | ||
758fc986 AS |
16 | #include <linux/usb/ehci_def.h> |
17 | ||
cb271f3c PC |
18 | /* |
19 | * ID | |
20 | * For 1.x revision, bit24 - bit31 are reserved | |
21 | * For 2.x revision, bit25 - bit28 are 0x2 | |
22 | */ | |
23 | #define TAG (0x1F << 16) | |
24 | #define REVISION (0xF << 21) | |
25 | #define VERSION (0xF << 25) | |
26 | #define CIVERSION (0x7 << 29) | |
27 | ||
65668718 PC |
28 | /* SBUSCFG */ |
29 | #define AHBBRST_MASK 0x7 | |
30 | ||
e443b333 AS |
31 | /* HCCPARAMS */ |
32 | #define HCCPARAMS_LEN BIT(17) | |
33 | ||
34 | /* DCCPARAMS */ | |
35 | #define DCCPARAMS_DEN (0x1F << 0) | |
36 | #define DCCPARAMS_DC BIT(7) | |
eb70e5ab | 37 | #define DCCPARAMS_HC BIT(8) |
e443b333 AS |
38 | |
39 | /* TESTMODE */ | |
40 | #define TESTMODE_FORCE BIT(0) | |
41 | ||
42 | /* USBCMD */ | |
43 | #define USBCMD_RS BIT(0) | |
44 | #define USBCMD_RST BIT(1) | |
45 | #define USBCMD_SUTW BIT(13) | |
46 | #define USBCMD_ATDTW BIT(14) | |
47 | ||
48 | /* USBSTS & USBINTR */ | |
49 | #define USBi_UI BIT(0) | |
50 | #define USBi_UEI BIT(1) | |
51 | #define USBi_PCI BIT(2) | |
52 | #define USBi_URI BIT(6) | |
53 | #define USBi_SLI BIT(8) | |
54 | ||
55 | /* DEVICEADDR */ | |
56 | #define DEVICEADDR_USBADRA BIT(24) | |
57 | #define DEVICEADDR_USBADR (0x7FUL << 25) | |
58 | ||
28362673 PC |
59 | /* TTCTRL */ |
60 | #define TTCTRL_TTHA_MASK (0x7fUL << 24) | |
61 | /* Set non-zero value for internal TT Hub address representation */ | |
62 | #define TTCTRL_TTHA (0x7fUL << 24) | |
63 | ||
e443b333 | 64 | /* PORTSC */ |
826cfe75 LJ |
65 | #define PORTSC_CCS BIT(0) |
66 | #define PORTSC_CSC BIT(1) | |
67 | #define PORTSC_PEC BIT(3) | |
68 | #define PORTSC_OCC BIT(5) | |
e443b333 AS |
69 | #define PORTSC_FPR BIT(6) |
70 | #define PORTSC_SUSP BIT(7) | |
71 | #define PORTSC_HSP BIT(9) | |
826cfe75 | 72 | #define PORTSC_PP BIT(12) |
e443b333 | 73 | #define PORTSC_PTC (0x0FUL << 16) |
961ea496 | 74 | #define PORTSC_WKCN BIT(20) |
864cf949 | 75 | #define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23)) |
40dcd0e8 | 76 | /* PTS and PTW for non lpm version only */ |
4f6743d5 | 77 | #define PORTSC_PFSC BIT(24) |
40dcd0e8 | 78 | #define PORTSC_PTS(d) \ |
dec23dca | 79 | (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0)) |
40dcd0e8 MG |
80 | #define PORTSC_PTW BIT(28) |
81 | #define PORTSC_STS BIT(29) | |
e443b333 | 82 | |
826cfe75 LJ |
83 | #define PORTSC_W1C_BITS \ |
84 | (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC) | |
85 | ||
e443b333 | 86 | /* DEVLC */ |
4f6743d5 | 87 | #define DEVLC_PFSC BIT(23) |
e443b333 | 88 | #define DEVLC_PSPD (0x03UL << 25) |
40dcd0e8 MG |
89 | #define DEVLC_PSPD_HS (0x02UL << 25) |
90 | #define DEVLC_PTW BIT(27) | |
91 | #define DEVLC_STS BIT(28) | |
dec23dca | 92 | #define DEVLC_PTS(d) (u32)(((d) & 0x7) << 29) |
40dcd0e8 MG |
93 | |
94 | /* Encoding for DEVLC_PTS and PORTSC_PTS */ | |
95 | #define PTS_UTMI 0 | |
96 | #define PTS_ULPI 2 | |
97 | #define PTS_SERIAL 3 | |
98 | #define PTS_HSIC 4 | |
e443b333 | 99 | |
5f36e231 AS |
100 | /* OTGSC */ |
101 | #define OTGSC_IDPU BIT(5) | |
826cfe75 | 102 | #define OTGSC_HADP BIT(6) |
e287b67b | 103 | #define OTGSC_HABA BIT(7) |
5f36e231 AS |
104 | #define OTGSC_ID BIT(8) |
105 | #define OTGSC_AVV BIT(9) | |
106 | #define OTGSC_ASV BIT(10) | |
107 | #define OTGSC_BSV BIT(11) | |
108 | #define OTGSC_BSE BIT(12) | |
109 | #define OTGSC_IDIS BIT(16) | |
110 | #define OTGSC_AVVIS BIT(17) | |
111 | #define OTGSC_ASVIS BIT(18) | |
112 | #define OTGSC_BSVIS BIT(19) | |
113 | #define OTGSC_BSEIS BIT(20) | |
c10b4f03 PC |
114 | #define OTGSC_1MSIS BIT(21) |
115 | #define OTGSC_DPIS BIT(22) | |
5f36e231 AS |
116 | #define OTGSC_IDIE BIT(24) |
117 | #define OTGSC_AVVIE BIT(25) | |
118 | #define OTGSC_ASVIE BIT(26) | |
119 | #define OTGSC_BSVIE BIT(27) | |
120 | #define OTGSC_BSEIE BIT(28) | |
c10b4f03 PC |
121 | #define OTGSC_1MSIE BIT(29) |
122 | #define OTGSC_DPIE BIT(30) | |
123 | #define OTGSC_INT_EN_BITS (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \ | |
124 | | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \ | |
125 | | OTGSC_DPIE) | |
126 | #define OTGSC_INT_STATUS_BITS (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \ | |
127 | | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \ | |
128 | | OTGSC_DPIS) | |
5f36e231 | 129 | |
e443b333 AS |
130 | /* USBMODE */ |
131 | #define USBMODE_CM (0x03UL << 0) | |
758fc986 | 132 | #define USBMODE_CM_DC (0x02UL << 0) |
e443b333 | 133 | #define USBMODE_SLOM BIT(3) |
758fc986 | 134 | #define USBMODE_CI_SDIS BIT(4) |
e443b333 AS |
135 | |
136 | /* ENDPTCTRL */ | |
137 | #define ENDPTCTRL_RXS BIT(0) | |
138 | #define ENDPTCTRL_RXT (0x03UL << 2) | |
139 | #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ | |
140 | #define ENDPTCTRL_RXE BIT(7) | |
141 | #define ENDPTCTRL_TXS BIT(16) | |
142 | #define ENDPTCTRL_TXT (0x03UL << 18) | |
143 | #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ | |
144 | #define ENDPTCTRL_TXE BIT(23) | |
145 | ||
146 | #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */ |