[mirror_ubuntu-artful-kernel.git] / drivers / usb / chipidea / ci_hdrc_msm.c

/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/usb/chipidea.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/io.h>
#include <linux/reset-controller.h>
#include <linux/extcon.h>
#include <linux/of.h>

#include "ci.h"

#define HS_PHY_AHB_MODE			0x0098

#define HS_PHY_GENCONFIG		0x009c
#define HS_PHY_TXFIFO_IDLE_FORCE_DIS	BIT(4)

#define HS_PHY_GENCONFIG_2		0x00a0
#define HS_PHY_SESS_VLD_CTRL_EN		BIT(7)
#define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX	BIT(19)

#define HSPHY_SESS_VLD_CTRL		BIT(25)

/* Vendor base starts at 0x200 beyond CI base */
#define HS_PHY_CTRL			0x0040
#define HS_PHY_SEC_CTRL			0x0078
#define HS_PHY_DIG_CLAMP_N		BIT(16)
#define HS_PHY_POR_ASSERT		BIT(0)

struct ci_hdrc_msm {
	struct platform_device *ci;
	struct clk *core_clk;
	struct clk *iface_clk;
	struct clk *fs_clk;
	struct ci_hdrc_platform_data pdata;
	struct reset_controller_dev rcdev;
	bool secondary_phy;
	bool hsic;
	void __iomem *base;
};

static int
ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
{
	struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
	void __iomem *addr = ci_msm->base;
	u32 val;

	if (id)
		addr += HS_PHY_SEC_CTRL;
	else
		addr += HS_PHY_CTRL;

	val = readl_relaxed(addr);
	val |= HS_PHY_POR_ASSERT;
	writel(val, addr);
	/*
	 * wait for minimum 10 microseconds as suggested by manual.
	 * Use a slightly larger value since the exact value didn't
	 * work 100% of the time.
	 */
	udelay(12);
	val &= ~HS_PHY_POR_ASSERT;
	writel(val, addr);

	return 0;
}

static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
	.reset = ci_hdrc_msm_por_reset,
};

static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
{
	struct device *dev = ci->dev->parent;
	struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
	int ret;

	switch (event) {
	case CI_HDRC_CONTROLLER_RESET_EVENT:
		dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");

		hw_phymode_configure(ci);
		if (msm_ci->secondary_phy) {
			u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
			val |= HS_PHY_DIG_CLAMP_N;
			writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
		}

		ret = phy_init(ci->phy);
		if (ret)
			return ret;

		ret = phy_power_on(ci->phy);
		if (ret) {
			phy_exit(ci->phy);
			return ret;
		}

		/* use AHB transactor, allow posted data writes */
		hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);

		/* workaround for rx buffer collision issue */
		hw_write_id_reg(ci, HS_PHY_GENCONFIG,
				HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);

		if (!msm_ci->hsic)
			hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
					HS_PHY_ULPI_TX_PKT_EN_CLR_FIX, 0);

		if (!IS_ERR(ci->platdata->vbus_extcon.edev)) {
			hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
					HS_PHY_SESS_VLD_CTRL_EN,
					HS_PHY_SESS_VLD_CTRL_EN);
			hw_write(ci, OP_USBCMD, HSPHY_SESS_VLD_CTRL,
				 HSPHY_SESS_VLD_CTRL);

		}
		break;
	case CI_HDRC_CONTROLLER_STOPPED_EVENT:
		dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
		phy_power_off(ci->phy);
		phy_exit(ci->phy);
		break;
	default:
		dev_dbg(dev, "unknown ci_hdrc event\n");
		break;
	}

	return 0;
}

static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
			       struct platform_device *pdev)
{
	struct regmap *regmap;
	struct device *dev = &pdev->dev;
	struct of_phandle_args args;
	u32 val;
	int ret;

	ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0,
					       &args);
	if (ret)
		return 0;

	regmap = syscon_node_to_regmap(args.np);
	of_node_put(args.np);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	ret = regmap_write(regmap, args.args[0], args.args[1]);
	if (ret)
		return ret;

	ci->secondary_phy = !!args.args[1];
	if (ci->secondary_phy) {
		val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL);
		val |= HS_PHY_DIG_CLAMP_N;
		writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL);
	}

	return 0;
}

static int ci_hdrc_msm_probe(struct platform_device *pdev)
{
	struct ci_hdrc_msm *ci;
	struct platform_device *plat_ci;
	struct clk *clk;
	struct reset_control *reset;
	struct resource *res;
	int ret;
	struct device_node *ulpi_node, *phy_node;

	dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");

	ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL);
	if (!ci)
		return -ENOMEM;
	platform_set_drvdata(pdev, ci);

	ci->pdata.name = "ci_hdrc_msm";
	ci->pdata.capoffset = DEF_CAPOFFSET;
	ci->pdata.flags	= CI_HDRC_REGS_SHARED | CI_HDRC_DISABLE_STREAMING |
			  CI_HDRC_OVERRIDE_AHB_BURST |
			  CI_HDRC_OVERRIDE_PHY_CONTROL;
	ci->pdata.notify_event = ci_hdrc_msm_notify_event;

	reset = devm_reset_control_get(&pdev->dev, "core");
	if (IS_ERR(reset))
		return PTR_ERR(reset);

	ci->core_clk = clk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ci->iface_clk = clk = devm_clk_get(&pdev->dev, "iface");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ci->fs_clk = clk = devm_clk_get(&pdev->dev, "fs");
	if (IS_ERR(clk)) {
		if (PTR_ERR(clk) == -EPROBE_DEFER)
			return -EPROBE_DEFER;
		ci->fs_clk = NULL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	ci->base = devm_ioremap_resource(&pdev->dev, res);
	if (!ci->base)
		return -ENOMEM;

	ci->rcdev.owner = THIS_MODULE;
	ci->rcdev.ops = &ci_hdrc_msm_reset_ops;
	ci->rcdev.of_node = pdev->dev.of_node;
	ci->rcdev.nr_resets = 2;
	ret = reset_controller_register(&ci->rcdev);
	if (ret)
		return ret;

	ret = clk_prepare_enable(ci->fs_clk);
	if (ret)
		goto err_fs;

	reset_control_assert(reset);
	usleep_range(10000, 12000);
	reset_control_deassert(reset);

	clk_disable_unprepare(ci->fs_clk);

	ret = clk_prepare_enable(ci->core_clk);
	if (ret)
		goto err_fs;

	ret = clk_prepare_enable(ci->iface_clk);
	if (ret)
		goto err_iface;

	ret = ci_hdrc_msm_mux_phy(ci, pdev);
	if (ret)
		goto err_mux;

	ulpi_node = of_find_node_by_name(pdev->dev.of_node, "ulpi");
	if (ulpi_node) {
		phy_node = of_get_next_available_child(ulpi_node, NULL);
		ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy");
		of_node_put(phy_node);
	}
	of_node_put(ulpi_node);

	plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource,
				     pdev->num_resources, &ci->pdata);
	if (IS_ERR(plat_ci)) {
		dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
		ret = PTR_ERR(plat_ci);
		goto err_mux;
	}

	ci->ci = plat_ci;

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_no_callbacks(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	return 0;

err_mux:
	clk_disable_unprepare(ci->iface_clk);
err_iface:
	clk_disable_unprepare(ci->core_clk);
err_fs:
	reset_controller_unregister(&ci->rcdev);
	return ret;
}

static int ci_hdrc_msm_remove(struct platform_device *pdev)
{
	struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	ci_hdrc_remove_device(ci->ci);
	clk_disable_unprepare(ci->iface_clk);
	clk_disable_unprepare(ci->core_clk);
	reset_controller_unregister(&ci->rcdev);

	return 0;
}

static const struct of_device_id msm_ci_dt_match[] = {
	{ .compatible = "qcom,ci-hdrc", },
	{ }
};
MODULE_DEVICE_TABLE(of, msm_ci_dt_match);

static struct platform_driver ci_hdrc_msm_driver = {
	.probe = ci_hdrc_msm_probe,
	.remove = ci_hdrc_msm_remove,
	.driver = {
		.name = "msm_hsusb",
		.of_match_table = msm_ci_dt_match,
	},
};

module_platform_driver(ci_hdrc_msm_driver);

MODULE_ALIAS("platform:msm_hsusb");
MODULE_ALIAS("platform:ci13xxx_msm");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
33f82f38 PK	1	/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
33f82f38 PK	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/platform_device.h>
2d0cdcc5	10	#include <linux/pm_runtime.h>
e443b333	11	#include <linux/usb/chipidea.h>
e9f15a71 SB	12	#include <linux/clk.h>
e9f15a71 SB	13	#include <linux/reset.h>
2fc305be SB	14	#include <linux/mfd/syscon.h>
	15	#include <linux/regmap.h>
	16	#include <linux/io.h>
1b8fc5a5	17	#include <linux/reset-controller.h>
47654a16 SB	18	#include <linux/extcon.h>
47654a16 SB	19	#include <linux/of.h>
33f82f38	20
e443b333	21	#include "ci.h"
33f82f38	22
ee33f6e7	23	#define HS_PHY_AHB_MODE 0x0098
33f82f38	24
47654a16 SB	25	#define HS_PHY_GENCONFIG 0x009c
	26	#define HS_PHY_TXFIFO_IDLE_FORCE_DIS BIT(4)
	27
	28	#define HS_PHY_GENCONFIG_2 0x00a0
	29	#define HS_PHY_SESS_VLD_CTRL_EN BIT(7)
	30	#define HS_PHY_ULPI_TX_PKT_EN_CLR_FIX BIT(19)
	31
	32	#define HSPHY_SESS_VLD_CTRL BIT(25)
	33
2fc305be	34	/* Vendor base starts at 0x200 beyond CI base */
1b8fc5a5	35	#define HS_PHY_CTRL 0x0040
2fc305be SB	36	#define HS_PHY_SEC_CTRL 0x0078
2fc305be SB	37	#define HS_PHY_DIG_CLAMP_N BIT(16)
1b8fc5a5	38	#define HS_PHY_POR_ASSERT BIT(0)
2fc305be	39
e9f15a71 SB	40	struct ci_hdrc_msm {
	41	struct platform_device *ci;
	42	struct clk *core_clk;
	43	struct clk *iface_clk;
	44	struct clk *fs_clk;
26f8e3a8	45	struct ci_hdrc_platform_data pdata;
1b8fc5a5	46	struct reset_controller_dev rcdev;
2fc305be	47	bool secondary_phy;
47654a16	48	bool hsic;
2fc305be	49	void __iomem *base;
e9f15a71 SB	50	};
e9f15a71 SB	51
1b8fc5a5 SB	52	static int
	53	ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id)
	54	{
	55	struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev);
	56	void __iomem *addr = ci_msm->base;
	57	u32 val;
	58
	59	if (id)
	60	addr += HS_PHY_SEC_CTRL;
	61	else
	62	addr += HS_PHY_CTRL;
	63
	64	val = readl_relaxed(addr);
	65	val \|= HS_PHY_POR_ASSERT;
	66	writel(val, addr);
	67	/*
	68	* wait for minimum 10 microseconds as suggested by manual.
	69	* Use a slightly larger value since the exact value didn't
	70	* work 100% of the time.
	71	*/
	72	udelay(12);
	73	val &= ~HS_PHY_POR_ASSERT;
	74	writel(val, addr);
	75
	76	return 0;
	77	}
	78
	79	static const struct reset_control_ops ci_hdrc_msm_reset_ops = {
	80	.reset = ci_hdrc_msm_por_reset,
	81	};
	82
11893dae	83	static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
33f82f38	84	{
2fc305be SB	85	struct device *dev = ci->dev->parent;
2fc305be SB	86	struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev);
11893dae	87	int ret;
33f82f38 PK	88
33f82f38 PK	89	switch (event) {
8e22978c AS	90	case CI_HDRC_CONTROLLER_RESET_EVENT:
8e22978c AS	91	dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
11893dae SB	92
11893dae SB	93	hw_phymode_configure(ci);
2fc305be SB	94	if (msm_ci->secondary_phy) {
	95	u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL);
	96	val \|= HS_PHY_DIG_CLAMP_N;
	97	writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL);
	98	}
	99
11893dae SB	100	ret = phy_init(ci->phy);
	101	if (ret)
	102	return ret;
	103
	104	ret = phy_power_on(ci->phy);
	105	if (ret) {
	106	phy_exit(ci->phy);
	107	return ret;
	108	}
	109
5ce7d27d	110	/* use AHB transactor, allow posted data writes */
ee33f6e7	111	hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8);
47654a16 SB	112
	113	/* workaround for rx buffer collision issue */
	114	hw_write_id_reg(ci, HS_PHY_GENCONFIG,
	115	HS_PHY_TXFIFO_IDLE_FORCE_DIS, 0);
	116
	117	if (!msm_ci->hsic)
	118	hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
	119	HS_PHY_ULPI_TX_PKT_EN_CLR_FIX, 0);
	120
	121	if (!IS_ERR(ci->platdata->vbus_extcon.edev)) {
	122	hw_write_id_reg(ci, HS_PHY_GENCONFIG_2,
	123	HS_PHY_SESS_VLD_CTRL_EN,
	124	HS_PHY_SESS_VLD_CTRL_EN);
	125	hw_write(ci, OP_USBCMD, HSPHY_SESS_VLD_CTRL,
	126	HSPHY_SESS_VLD_CTRL);
	127
	128	}
33f82f38	129	break;
8e22978c AS	130	case CI_HDRC_CONTROLLER_STOPPED_EVENT:
8e22978c AS	131	dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
11893dae SB	132	phy_power_off(ci->phy);
11893dae SB	133	phy_exit(ci->phy);
33f82f38 PK	134	break;
33f82f38 PK	135	default:
8e22978c	136	dev_dbg(dev, "unknown ci_hdrc event\n");
33f82f38 PK	137	break;
33f82f38 PK	138	}
11893dae SB	139
11893dae SB	140	return 0;
33f82f38 PK	141	}
33f82f38 PK	142
2fc305be SB	143	static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci,
	144	struct platform_device *pdev)
	145	{
	146	struct regmap *regmap;
	147	struct device *dev = &pdev->dev;
	148	struct of_phandle_args args;
	149	u32 val;
	150	int ret;
	151
	152	ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0,
	153	&args);
	154	if (ret)
	155	return 0;
	156
	157	regmap = syscon_node_to_regmap(args.np);
	158	of_node_put(args.np);
	159	if (IS_ERR(regmap))
	160	return PTR_ERR(regmap);
	161
	162	ret = regmap_write(regmap, args.args[0], args.args[1]);
	163	if (ret)
	164	return ret;
	165
	166	ci->secondary_phy = !!args.args[1];
	167	if (ci->secondary_phy) {
	168	val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL);
	169	val \|= HS_PHY_DIG_CLAMP_N;
	170	writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL);
	171	}
	172
	173	return 0;
	174	}
	175
8e22978c	176	static int ci_hdrc_msm_probe(struct platform_device *pdev)
33f82f38	177	{
e9f15a71	178	struct ci_hdrc_msm *ci;
62bb84ed	179	struct platform_device *plat_ci;
e9f15a71 SB	180	struct clk *clk;
e9f15a71 SB	181	struct reset_control *reset;
2fc305be	182	struct resource *res;
e9f15a71	183	int ret;
47654a16	184	struct device_node ulpi_node, phy_node;
33f82f38	185
8e22978c	186	dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");
33f82f38	187
e9f15a71 SB	188	ci = devm_kzalloc(&pdev->dev, sizeof(*ci), GFP_KERNEL);
	189	if (!ci)
	190	return -ENOMEM;
	191	platform_set_drvdata(pdev, ci);
	192
26f8e3a8 SB	193	ci->pdata.name = "ci_hdrc_msm";
	194	ci->pdata.capoffset = DEF_CAPOFFSET;
	195	ci->pdata.flags = CI_HDRC_REGS_SHARED \| CI_HDRC_DISABLE_STREAMING \|
11893dae SB	196	CI_HDRC_OVERRIDE_AHB_BURST \|
11893dae SB	197	CI_HDRC_OVERRIDE_PHY_CONTROL;
26f8e3a8	198	ci->pdata.notify_event = ci_hdrc_msm_notify_event;
2629b101	199
e9f15a71 SB	200	reset = devm_reset_control_get(&pdev->dev, "core");
	201	if (IS_ERR(reset))
	202	return PTR_ERR(reset);
	203
	204	ci->core_clk = clk = devm_clk_get(&pdev->dev, "core");
	205	if (IS_ERR(clk))
	206	return PTR_ERR(clk);
	207
	208	ci->iface_clk = clk = devm_clk_get(&pdev->dev, "iface");
	209	if (IS_ERR(clk))
	210	return PTR_ERR(clk);
	211
	212	ci->fs_clk = clk = devm_clk_get(&pdev->dev, "fs");
	213	if (IS_ERR(clk)) {
	214	if (PTR_ERR(clk) == -EPROBE_DEFER)
	215	return -EPROBE_DEFER;
	216	ci->fs_clk = NULL;
	217	}
	218
2fc305be SB	219	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	220	ci->base = devm_ioremap_resource(&pdev->dev, res);
	221	if (!ci->base)
	222	return -ENOMEM;
	223
1b8fc5a5 SB	224	ci->rcdev.owner = THIS_MODULE;
	225	ci->rcdev.ops = &ci_hdrc_msm_reset_ops;
	226	ci->rcdev.of_node = pdev->dev.of_node;
	227	ci->rcdev.nr_resets = 2;
	228	ret = reset_controller_register(&ci->rcdev);
e9f15a71 SB	229	if (ret)
	230	return ret;
	231
1b8fc5a5 SB	232	ret = clk_prepare_enable(ci->fs_clk);
	233	if (ret)
	234	goto err_fs;
	235
e9f15a71 SB	236	reset_control_assert(reset);
	237	usleep_range(10000, 12000);
	238	reset_control_deassert(reset);
	239
	240	clk_disable_unprepare(ci->fs_clk);
	241
	242	ret = clk_prepare_enable(ci->core_clk);
	243	if (ret)
1b8fc5a5	244	goto err_fs;
e9f15a71 SB	245
	246	ret = clk_prepare_enable(ci->iface_clk);
	247	if (ret)
	248	goto err_iface;
	249
2fc305be SB	250	ret = ci_hdrc_msm_mux_phy(ci, pdev);
	251	if (ret)
	252	goto err_mux;
	253
47654a16 SB	254	ulpi_node = of_find_node_by_name(pdev->dev.of_node, "ulpi");
	255	if (ulpi_node) {
	256	phy_node = of_get_next_available_child(ulpi_node, NULL);
	257	ci->hsic = of_device_is_compatible(phy_node, "qcom,usb-hsic-phy");
	258	of_node_put(phy_node);
	259	}
	260	of_node_put(ulpi_node);
	261
26f8e3a8 SB	262	plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource,
26f8e3a8 SB	263	pdev->num_resources, &ci->pdata);
cbc6dc2a	264	if (IS_ERR(plat_ci)) {
8e22978c	265	dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
e9f15a71 SB	266	ret = PTR_ERR(plat_ci);
e9f15a71 SB	267	goto err_mux;
33f82f38 PK	268	}
33f82f38 PK	269
e9f15a71	270	ci->ci = plat_ci;
6bf83594	271
2c8ea46d	272	pm_runtime_set_active(&pdev->dev);
2d0cdcc5 PK	273	pm_runtime_no_callbacks(&pdev->dev);
	274	pm_runtime_enable(&pdev->dev);
	275
33f82f38	276	return 0;
e9f15a71 SB	277
	278	err_mux:
	279	clk_disable_unprepare(ci->iface_clk);
	280	err_iface:
	281	clk_disable_unprepare(ci->core_clk);
1b8fc5a5 SB	282	err_fs:
1b8fc5a5 SB	283	reset_controller_unregister(&ci->rcdev);
e9f15a71	284	return ret;
33f82f38 PK	285	}
33f82f38 PK	286
8e22978c	287	static int ci_hdrc_msm_remove(struct platform_device *pdev)
6bf83594	288	{
e9f15a71	289	struct ci_hdrc_msm *ci = platform_get_drvdata(pdev);
6bf83594 FB	290
6bf83594 FB	291	pm_runtime_disable(&pdev->dev);
e9f15a71 SB	292	ci_hdrc_remove_device(ci->ci);
	293	clk_disable_unprepare(ci->iface_clk);
	294	clk_disable_unprepare(ci->core_clk);
1b8fc5a5	295	reset_controller_unregister(&ci->rcdev);
6bf83594 FB	296
	297	return 0;
	298	}
	299
2629b101 II	300	static const struct of_device_id msm_ci_dt_match[] = {
	301	{ .compatible = "qcom,ci-hdrc", },
	302	{ }
	303	};
	304	MODULE_DEVICE_TABLE(of, msm_ci_dt_match);
	305
8e22978c AS	306	static struct platform_driver ci_hdrc_msm_driver = {
	307	.probe = ci_hdrc_msm_probe,
	308	.remove = ci_hdrc_msm_remove,
2629b101 II	309	.driver = {
	310	.name = "msm_hsusb",
	311	.of_match_table = msm_ci_dt_match,
	312	},
33f82f38 PK	313	};
33f82f38 PK	314
8e22978c	315	module_platform_driver(ci_hdrc_msm_driver);
4703d2e9	316
6bf83594	317	MODULE_ALIAS("platform:msm_hsusb");
8e22978c	318	MODULE_ALIAS("platform:ci13xxx_msm");
4703d2e9	319	MODULE_LICENSE("GPL v2");