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Commit | Line | Data |
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e443b333 AS |
1 | /* |
2 | * core.c - ChipIdea USB IP core family device controller | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Description: ChipIdea USB IP core family device controller | |
15 | * | |
16 | * This driver is composed of several blocks: | |
17 | * - HW: hardware interface | |
18 | * - DBG: debug facilities (optional) | |
19 | * - UTIL: utilities | |
20 | * - ISR: interrupts handling | |
21 | * - ENDPT: endpoint operations (Gadget API) | |
22 | * - GADGET: gadget operations (Gadget API) | |
23 | * - BUS: bus glue code, bus abstraction layer | |
24 | * | |
25 | * Compile Options | |
58ce8499 | 26 | * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities |
e443b333 AS |
27 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
28 | * if defined mass storage compliance succeeds but with warnings | |
29 | * => case 4: Hi > Dn | |
30 | * => case 5: Hi > Di | |
31 | * => case 8: Hi <> Do | |
32 | * if undefined usbtest 13 fails | |
33 | * - TRACE: enable function tracing (depends on DEBUG) | |
34 | * | |
35 | * Main Features | |
36 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
37 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
38 | * - Normal & LPM support | |
39 | * | |
40 | * USBTEST Report | |
41 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
42 | * - Not Supported: 15 & 16 (ISO) | |
43 | * | |
44 | * TODO List | |
e443b333 AS |
45 | * - Suspend & Remote Wakeup |
46 | */ | |
47 | #include <linux/delay.h> | |
48 | #include <linux/device.h> | |
e443b333 | 49 | #include <linux/dma-mapping.h> |
e443b333 AS |
50 | #include <linux/platform_device.h> |
51 | #include <linux/module.h> | |
fe6e125e | 52 | #include <linux/idr.h> |
e443b333 AS |
53 | #include <linux/interrupt.h> |
54 | #include <linux/io.h> | |
e443b333 AS |
55 | #include <linux/kernel.h> |
56 | #include <linux/slab.h> | |
57 | #include <linux/pm_runtime.h> | |
58 | #include <linux/usb/ch9.h> | |
59 | #include <linux/usb/gadget.h> | |
60 | #include <linux/usb/otg.h> | |
61 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 62 | #include <linux/usb/of.h> |
4f6743d5 | 63 | #include <linux/of.h> |
40dcd0e8 | 64 | #include <linux/phy.h> |
1542d9c3 | 65 | #include <linux/regulator/consumer.h> |
e443b333 AS |
66 | |
67 | #include "ci.h" | |
68 | #include "udc.h" | |
69 | #include "bits.h" | |
eb70e5ab | 70 | #include "host.h" |
e443b333 | 71 | #include "debug.h" |
c10b4f03 | 72 | #include "otg.h" |
4dcf720c | 73 | #include "otg_fsm.h" |
e443b333 | 74 | |
5f36e231 | 75 | /* Controller register map */ |
987e7bc3 MKB |
76 | static const u8 ci_regs_nolpm[] = { |
77 | [CAP_CAPLENGTH] = 0x00U, | |
78 | [CAP_HCCPARAMS] = 0x08U, | |
79 | [CAP_DCCPARAMS] = 0x24U, | |
80 | [CAP_TESTMODE] = 0x38U, | |
81 | [OP_USBCMD] = 0x00U, | |
82 | [OP_USBSTS] = 0x04U, | |
83 | [OP_USBINTR] = 0x08U, | |
84 | [OP_DEVICEADDR] = 0x14U, | |
85 | [OP_ENDPTLISTADDR] = 0x18U, | |
86 | [OP_PORTSC] = 0x44U, | |
87 | [OP_DEVLC] = 0x84U, | |
88 | [OP_OTGSC] = 0x64U, | |
89 | [OP_USBMODE] = 0x68U, | |
90 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
91 | [OP_ENDPTPRIME] = 0x70U, | |
92 | [OP_ENDPTFLUSH] = 0x74U, | |
93 | [OP_ENDPTSTAT] = 0x78U, | |
94 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
95 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
96 | }; |
97 | ||
987e7bc3 MKB |
98 | static const u8 ci_regs_lpm[] = { |
99 | [CAP_CAPLENGTH] = 0x00U, | |
100 | [CAP_HCCPARAMS] = 0x08U, | |
101 | [CAP_DCCPARAMS] = 0x24U, | |
102 | [CAP_TESTMODE] = 0xFCU, | |
103 | [OP_USBCMD] = 0x00U, | |
104 | [OP_USBSTS] = 0x04U, | |
105 | [OP_USBINTR] = 0x08U, | |
106 | [OP_DEVICEADDR] = 0x14U, | |
107 | [OP_ENDPTLISTADDR] = 0x18U, | |
108 | [OP_PORTSC] = 0x44U, | |
109 | [OP_DEVLC] = 0x84U, | |
110 | [OP_OTGSC] = 0xC4U, | |
111 | [OP_USBMODE] = 0xC8U, | |
112 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
113 | [OP_ENDPTPRIME] = 0xDCU, | |
114 | [OP_ENDPTFLUSH] = 0xE0U, | |
115 | [OP_ENDPTSTAT] = 0xE4U, | |
116 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
117 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
118 | }; |
119 | ||
8e22978c | 120 | static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
121 | { |
122 | int i; | |
123 | ||
e443b333 | 124 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
125 | ci->hw_bank.regmap[i] = |
126 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
127 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
128 | ||
129 | for (; i <= OP_LAST; i++) | |
5f36e231 | 130 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
131 | 4 * (i - OP_ENDPTCTRL) + |
132 | (is_lpm | |
133 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
134 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
36304b06 LJ |
139 | /** |
140 | * hw_read_intr_enable: returns interrupt enable register | |
141 | * | |
19353881 PC |
142 | * @ci: the controller |
143 | * | |
36304b06 LJ |
144 | * This function returns register data |
145 | */ | |
146 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
147 | { | |
148 | return hw_read(ci, OP_USBINTR, ~0); | |
149 | } | |
150 | ||
151 | /** | |
152 | * hw_read_intr_status: returns interrupt status register | |
153 | * | |
19353881 PC |
154 | * @ci: the controller |
155 | * | |
36304b06 LJ |
156 | * This function returns register data |
157 | */ | |
158 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
159 | { | |
160 | return hw_read(ci, OP_USBSTS, ~0); | |
161 | } | |
162 | ||
e443b333 AS |
163 | /** |
164 | * hw_port_test_set: writes port test mode (execute without interruption) | |
165 | * @mode: new value | |
166 | * | |
167 | * This function returns an error code | |
168 | */ | |
8e22978c | 169 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
170 | { |
171 | const u8 TEST_MODE_MAX = 7; | |
172 | ||
173 | if (mode > TEST_MODE_MAX) | |
174 | return -EINVAL; | |
175 | ||
727b4ddb | 176 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
177 | return 0; |
178 | } | |
179 | ||
180 | /** | |
181 | * hw_port_test_get: reads port test mode value | |
182 | * | |
19353881 PC |
183 | * @ci: the controller |
184 | * | |
e443b333 AS |
185 | * This function returns port test mode value |
186 | */ | |
8e22978c | 187 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 188 | { |
727b4ddb | 189 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
190 | } |
191 | ||
864cf949 PC |
192 | /* The PHY enters/leaves low power mode */ |
193 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
194 | { | |
195 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
196 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
197 | ||
198 | if (enable && !lpm) { | |
199 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), | |
200 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
201 | } else if (!enable && lpm) { | |
202 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), | |
203 | 0); | |
204 | /* | |
90893b90 | 205 | * the PHY needs some time (less |
864cf949 PC |
206 | * than 1ms) to leave low power mode. |
207 | */ | |
90893b90 | 208 | usleep_range(1000, 1100); |
864cf949 PC |
209 | } |
210 | } | |
211 | ||
8e22978c | 212 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
213 | { |
214 | u32 reg; | |
215 | ||
216 | /* bank is a module variable */ | |
5f36e231 | 217 | ci->hw_bank.abs = base; |
e443b333 | 218 | |
5f36e231 | 219 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 220 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 221 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 222 | |
5f36e231 AS |
223 | hw_alloc_regmap(ci, false); |
224 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 225 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 226 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
227 | if (reg) |
228 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
229 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
230 | ci->hw_bank.size += OP_LAST; | |
231 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 232 | |
5f36e231 | 233 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 234 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 235 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 236 | |
09c94e62 | 237 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
238 | return -ENODEV; |
239 | ||
864cf949 PC |
240 | ci_hdrc_enter_lpm(ci, false); |
241 | ||
c344b518 PC |
242 | /* Disable all interrupts bits */ |
243 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
244 | ||
245 | /* Clear all interrupts status bits*/ | |
246 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
247 | ||
5f36e231 AS |
248 | dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", |
249 | ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
250 | |
251 | /* setup lock mode ? */ | |
252 | ||
253 | /* ENDPTSETUPSTAT is '0' by default */ | |
254 | ||
255 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
8e22978c | 260 | static void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 261 | { |
3b5d3e68 | 262 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
263 | |
264 | switch (ci->platdata->phy_mode) { | |
265 | case USBPHY_INTERFACE_MODE_UTMI: | |
266 | portsc = PORTSC_PTS(PTS_UTMI); | |
267 | lpm = DEVLC_PTS(PTS_UTMI); | |
268 | break; | |
269 | case USBPHY_INTERFACE_MODE_UTMIW: | |
270 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
271 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
272 | break; | |
273 | case USBPHY_INTERFACE_MODE_ULPI: | |
274 | portsc = PORTSC_PTS(PTS_ULPI); | |
275 | lpm = DEVLC_PTS(PTS_ULPI); | |
276 | break; | |
277 | case USBPHY_INTERFACE_MODE_SERIAL: | |
278 | portsc = PORTSC_PTS(PTS_SERIAL); | |
279 | lpm = DEVLC_PTS(PTS_SERIAL); | |
280 | sts = 1; | |
281 | break; | |
282 | case USBPHY_INTERFACE_MODE_HSIC: | |
283 | portsc = PORTSC_PTS(PTS_HSIC); | |
284 | lpm = DEVLC_PTS(PTS_HSIC); | |
285 | break; | |
286 | default: | |
287 | return; | |
288 | } | |
289 | ||
290 | if (ci->hw_bank.lpm) { | |
291 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
292 | if (sts) |
293 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
294 | } else { |
295 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
296 | if (sts) |
297 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
298 | } |
299 | } | |
300 | ||
d03cccff PC |
301 | /** |
302 | * ci_usb_phy_init: initialize phy according to different phy type | |
303 | * @ci: the controller | |
19353881 | 304 | * |
d03cccff PC |
305 | * This function returns an error code if usb_phy_init has failed |
306 | */ | |
307 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
308 | { | |
309 | int ret; | |
310 | ||
311 | switch (ci->platdata->phy_mode) { | |
312 | case USBPHY_INTERFACE_MODE_UTMI: | |
313 | case USBPHY_INTERFACE_MODE_UTMIW: | |
314 | case USBPHY_INTERFACE_MODE_HSIC: | |
315 | ret = usb_phy_init(ci->transceiver); | |
316 | if (ret) | |
317 | return ret; | |
318 | hw_phymode_configure(ci); | |
319 | break; | |
320 | case USBPHY_INTERFACE_MODE_ULPI: | |
321 | case USBPHY_INTERFACE_MODE_SERIAL: | |
322 | hw_phymode_configure(ci); | |
323 | ret = usb_phy_init(ci->transceiver); | |
324 | if (ret) | |
325 | return ret; | |
326 | break; | |
327 | default: | |
328 | ret = usb_phy_init(ci->transceiver); | |
329 | } | |
330 | ||
331 | return ret; | |
332 | } | |
333 | ||
e443b333 AS |
334 | /** |
335 | * hw_device_reset: resets chip (execute without interruption) | |
336 | * @ci: the controller | |
337 | * | |
338 | * This function returns an error code | |
339 | */ | |
8e22978c | 340 | int hw_device_reset(struct ci_hdrc *ci, u32 mode) |
e443b333 AS |
341 | { |
342 | /* should flush & stop before reset */ | |
343 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
344 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
345 | ||
346 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
347 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) | |
348 | udelay(10); /* not RTOS friendly */ | |
349 | ||
77c4400f RZ |
350 | if (ci->platdata->notify_event) |
351 | ci->platdata->notify_event(ci, | |
8e22978c | 352 | CI_HDRC_CONTROLLER_RESET_EVENT); |
e443b333 | 353 | |
8e22978c | 354 | if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) |
758fc986 | 355 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); |
e443b333 | 356 | |
4f6743d5 MG |
357 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { |
358 | if (ci->hw_bank.lpm) | |
359 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
360 | else | |
361 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
362 | } | |
363 | ||
e443b333 AS |
364 | /* USBMODE should be configured step by step */ |
365 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
eb70e5ab | 366 | hw_write(ci, OP_USBMODE, USBMODE_CM, mode); |
e443b333 AS |
367 | /* HW >= 2.3 */ |
368 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
369 | ||
eb70e5ab AS |
370 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { |
371 | pr_err("cannot enter in %s mode", ci_role(ci)->name); | |
e443b333 AS |
372 | pr_err("lpm = %i", ci->hw_bank.lpm); |
373 | return -ENODEV; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
22fa8445 PC |
379 | /** |
380 | * hw_wait_reg: wait the register value | |
381 | * | |
382 | * Sometimes, it needs to wait register value before going on. | |
383 | * Eg, when switch to device mode, the vbus value should be lower | |
384 | * than OTGSC_BSV before connects to host. | |
385 | * | |
386 | * @ci: the controller | |
387 | * @reg: register index | |
388 | * @mask: mast bit | |
389 | * @value: the bit value to wait | |
390 | * @timeout_ms: timeout in millisecond | |
391 | * | |
392 | * This function returns an error code if timeout | |
393 | */ | |
394 | int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, | |
395 | u32 value, unsigned int timeout_ms) | |
396 | { | |
397 | unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); | |
398 | ||
399 | while (hw_read(ci, reg, mask) != value) { | |
400 | if (time_after(jiffies, elapse)) { | |
401 | dev_err(ci->dev, "timeout waiting for %08x in %d\n", | |
402 | mask, reg); | |
403 | return -ETIMEDOUT; | |
404 | } | |
405 | msleep(20); | |
406 | } | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
5f36e231 AS |
411 | static irqreturn_t ci_irq(int irq, void *data) |
412 | { | |
8e22978c | 413 | struct ci_hdrc *ci = data; |
5f36e231 | 414 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 415 | u32 otgsc = 0; |
5f36e231 | 416 | |
4dcf720c | 417 | if (ci->is_otg) { |
0c33bf78 | 418 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
419 | if (ci_otg_is_fsm_mode(ci)) { |
420 | ret = ci_otg_fsm_irq(ci); | |
421 | if (ret == IRQ_HANDLED) | |
422 | return ret; | |
423 | } | |
424 | } | |
5f36e231 | 425 | |
a107f8c5 PC |
426 | /* |
427 | * Handle id change interrupt, it indicates device/host function | |
428 | * switch. | |
429 | */ | |
430 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
431 | ci->id_event = true; | |
0c33bf78 LJ |
432 | /* Clear ID change irq status */ |
433 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 434 | ci_otg_queue_work(ci); |
a107f8c5 PC |
435 | return IRQ_HANDLED; |
436 | } | |
b183c19f | 437 | |
a107f8c5 PC |
438 | /* |
439 | * Handle vbus change interrupt, it indicates device connection | |
440 | * and disconnection events. | |
441 | */ | |
442 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
443 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
444 | /* Clear BSV irq */ |
445 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 446 | ci_otg_queue_work(ci); |
a107f8c5 | 447 | return IRQ_HANDLED; |
5f36e231 AS |
448 | } |
449 | ||
a107f8c5 PC |
450 | /* Handle device/host interrupt */ |
451 | if (ci->role != CI_ROLE_END) | |
452 | ret = ci_role(ci)->irq(ci); | |
453 | ||
b183c19f | 454 | return ret; |
5f36e231 AS |
455 | } |
456 | ||
1542d9c3 PC |
457 | static int ci_get_platdata(struct device *dev, |
458 | struct ci_hdrc_platform_data *platdata) | |
459 | { | |
c22600c3 PC |
460 | if (!platdata->phy_mode) |
461 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
462 | ||
463 | if (!platdata->dr_mode) | |
464 | platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); | |
465 | ||
466 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
467 | platdata->dr_mode = USB_DR_MODE_OTG; | |
468 | ||
c2ec3a73 PC |
469 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
470 | /* Get the vbus regulator */ | |
471 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
472 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
473 | return -EPROBE_DEFER; | |
474 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
475 | /* no vbus regualator is needed */ | |
476 | platdata->reg_vbus = NULL; | |
477 | } else if (IS_ERR(platdata->reg_vbus)) { | |
478 | dev_err(dev, "Getting regulator error: %ld\n", | |
479 | PTR_ERR(platdata->reg_vbus)); | |
480 | return PTR_ERR(platdata->reg_vbus); | |
481 | } | |
f6a9ff07 PC |
482 | /* Get TPL support */ |
483 | if (!platdata->tpl_support) | |
484 | platdata->tpl_support = | |
485 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
486 | } |
487 | ||
4f6743d5 MG |
488 | if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) |
489 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; | |
490 | ||
1542d9c3 PC |
491 | return 0; |
492 | } | |
493 | ||
fe6e125e RZ |
494 | static DEFINE_IDA(ci_ida); |
495 | ||
8e22978c | 496 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 497 | struct resource *res, int nres, |
8e22978c | 498 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
499 | { |
500 | struct platform_device *pdev; | |
fe6e125e | 501 | int id, ret; |
cbc6dc2a | 502 | |
1542d9c3 PC |
503 | ret = ci_get_platdata(dev, platdata); |
504 | if (ret) | |
505 | return ERR_PTR(ret); | |
506 | ||
fe6e125e RZ |
507 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
508 | if (id < 0) | |
509 | return ERR_PTR(id); | |
510 | ||
511 | pdev = platform_device_alloc("ci_hdrc", id); | |
512 | if (!pdev) { | |
513 | ret = -ENOMEM; | |
514 | goto put_id; | |
515 | } | |
cbc6dc2a RZ |
516 | |
517 | pdev->dev.parent = dev; | |
518 | pdev->dev.dma_mask = dev->dma_mask; | |
519 | pdev->dev.dma_parms = dev->dma_parms; | |
520 | dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); | |
521 | ||
522 | ret = platform_device_add_resources(pdev, res, nres); | |
523 | if (ret) | |
524 | goto err; | |
525 | ||
526 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
527 | if (ret) | |
528 | goto err; | |
529 | ||
530 | ret = platform_device_add(pdev); | |
531 | if (ret) | |
532 | goto err; | |
533 | ||
534 | return pdev; | |
535 | ||
536 | err: | |
537 | platform_device_put(pdev); | |
fe6e125e RZ |
538 | put_id: |
539 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
540 | return ERR_PTR(ret); |
541 | } | |
8e22978c | 542 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 543 | |
8e22978c | 544 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 545 | { |
98c35534 | 546 | int id = pdev->id; |
cbc6dc2a | 547 | platform_device_unregister(pdev); |
98c35534 | 548 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 549 | } |
8e22978c | 550 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 551 | |
3f124d23 PC |
552 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
553 | { | |
554 | ci_hdrc_gadget_destroy(ci); | |
555 | ci_hdrc_host_destroy(ci); | |
cbec6bd5 PC |
556 | if (ci->is_otg) |
557 | ci_hdrc_otg_destroy(ci); | |
3f124d23 PC |
558 | } |
559 | ||
577b232f PC |
560 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
561 | { | |
562 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
563 | ci->is_otg = false; | |
564 | else | |
565 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
566 | DCCPARAMS_DC | DCCPARAMS_HC) | |
567 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
90893b90 | 568 | if (ci->is_otg) |
577b232f PC |
569 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
570 | } | |
571 | ||
41ac7b3a | 572 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
573 | { |
574 | struct device *dev = &pdev->dev; | |
8e22978c | 575 | struct ci_hdrc *ci; |
e443b333 AS |
576 | struct resource *res; |
577 | void __iomem *base; | |
578 | int ret; | |
691962d1 | 579 | enum usb_dr_mode dr_mode; |
e443b333 | 580 | |
fad56745 | 581 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
582 | dev_err(dev, "platform data missing\n"); |
583 | return -ENODEV; | |
584 | } | |
585 | ||
586 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
587 | base = devm_ioremap_resource(dev, res); |
588 | if (IS_ERR(base)) | |
589 | return PTR_ERR(base); | |
e443b333 | 590 | |
5f36e231 AS |
591 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
592 | if (!ci) { | |
593 | dev_err(dev, "can't allocate device\n"); | |
594 | return -ENOMEM; | |
595 | } | |
596 | ||
597 | ci->dev = dev; | |
fad56745 | 598 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
599 | ci->imx28_write_fix = !!(ci->platdata->flags & |
600 | CI_HDRC_IMX28_WRITE_FIX); | |
5f36e231 AS |
601 | |
602 | ret = hw_device_init(ci, base); | |
603 | if (ret < 0) { | |
604 | dev_err(dev, "can't initialize hardware\n"); | |
605 | return -ENODEV; | |
606 | } | |
e443b333 | 607 | |
c859aa65 PC |
608 | if (ci->platdata->phy) |
609 | ci->transceiver = ci->platdata->phy; | |
610 | else | |
611 | ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
612 | ||
613 | if (IS_ERR(ci->transceiver)) { | |
614 | ret = PTR_ERR(ci->transceiver); | |
615 | /* | |
616 | * if -ENXIO is returned, it means PHY layer wasn't | |
617 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
618 | * in that case, since no PHY driver will ever probe. | |
619 | */ | |
620 | if (ret == -ENXIO) | |
621 | return ret; | |
622 | ||
623 | dev_err(dev, "no usb2 phy configured\n"); | |
624 | return -EPROBE_DEFER; | |
625 | } | |
626 | ||
d03cccff | 627 | ret = ci_usb_phy_init(ci); |
74475ede PC |
628 | if (ret) { |
629 | dev_err(dev, "unable to init phy: %d\n", ret); | |
630 | return ret; | |
90893b90 PC |
631 | } else { |
632 | /* | |
633 | * The delay to sync PHY's status, the maximum delay is | |
634 | * 2ms since the otgsc uses 1ms timer to debounce the | |
635 | * PHY's input | |
636 | */ | |
637 | usleep_range(2000, 2500); | |
74475ede PC |
638 | } |
639 | ||
eb70e5ab AS |
640 | ci->hw_bank.phys = res->start; |
641 | ||
5f36e231 AS |
642 | ci->irq = platform_get_irq(pdev, 0); |
643 | if (ci->irq < 0) { | |
e443b333 | 644 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 645 | ret = ci->irq; |
c859aa65 | 646 | goto deinit_phy; |
5f36e231 AS |
647 | } |
648 | ||
577b232f PC |
649 | ci_get_otg_capable(ci); |
650 | ||
691962d1 | 651 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 652 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
653 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
654 | ret = ci_hdrc_host_init(ci); | |
655 | if (ret) | |
656 | dev_info(dev, "doesn't support host\n"); | |
657 | } | |
eb70e5ab | 658 | |
691962d1 SH |
659 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
660 | ret = ci_hdrc_gadget_init(ci); | |
661 | if (ret) | |
662 | dev_info(dev, "doesn't support gadget\n"); | |
663 | } | |
5f36e231 AS |
664 | |
665 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
666 | dev_err(dev, "no supported roles\n"); | |
74475ede | 667 | ret = -ENODEV; |
c859aa65 | 668 | goto deinit_phy; |
cbec6bd5 PC |
669 | } |
670 | ||
27c62c2d | 671 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
90893b90 PC |
672 | /* Disable and clear all OTG irq */ |
673 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
674 | OTGSC_INT_STATUS_BITS); | |
cbec6bd5 PC |
675 | ret = ci_hdrc_otg_init(ci); |
676 | if (ret) { | |
677 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
678 | goto stop; | |
679 | } | |
5f36e231 AS |
680 | } |
681 | ||
682 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 683 | if (ci->is_otg) { |
577b232f | 684 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
685 | /* Enable ID change irq */ |
686 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
687 | } else { |
688 | /* | |
689 | * If the controller is not OTG capable, but support | |
690 | * role switch, the defalt role is gadget, and the | |
691 | * user can switch it through debugfs. | |
692 | */ | |
693 | ci->role = CI_ROLE_GADGET; | |
694 | } | |
5f36e231 AS |
695 | } else { |
696 | ci->role = ci->roles[CI_ROLE_HOST] | |
697 | ? CI_ROLE_HOST | |
698 | : CI_ROLE_GADGET; | |
699 | } | |
700 | ||
5a1e1456 PC |
701 | /* only update vbus status for peripheral */ |
702 | if (ci->role == CI_ROLE_GADGET) | |
703 | ci_handle_vbus_change(ci); | |
704 | ||
4dcf720c LJ |
705 | if (!ci_otg_is_fsm_mode(ci)) { |
706 | ret = ci_role_start(ci, ci->role); | |
707 | if (ret) { | |
708 | dev_err(dev, "can't start %s role\n", | |
709 | ci_role(ci)->name); | |
710 | goto stop; | |
711 | } | |
e443b333 AS |
712 | } |
713 | ||
5f36e231 | 714 | platform_set_drvdata(pdev, ci); |
77c4400f | 715 | ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, |
5f36e231 AS |
716 | ci); |
717 | if (ret) | |
718 | goto stop; | |
e443b333 | 719 | |
4dcf720c LJ |
720 | if (ci_otg_is_fsm_mode(ci)) |
721 | ci_hdrc_otg_fsm_start(ci); | |
722 | ||
adf0f735 AS |
723 | ret = dbg_create_files(ci); |
724 | if (!ret) | |
725 | return 0; | |
5f36e231 | 726 | |
adf0f735 | 727 | free_irq(ci->irq, ci); |
5f36e231 | 728 | stop: |
3f124d23 | 729 | ci_role_destroy(ci); |
c859aa65 PC |
730 | deinit_phy: |
731 | usb_phy_shutdown(ci->transceiver); | |
e443b333 AS |
732 | |
733 | return ret; | |
734 | } | |
735 | ||
fb4e98ab | 736 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 737 | { |
8e22978c | 738 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 739 | |
adf0f735 | 740 | dbg_remove_files(ci); |
5f36e231 | 741 | free_irq(ci->irq, ci); |
3f124d23 | 742 | ci_role_destroy(ci); |
864cf949 | 743 | ci_hdrc_enter_lpm(ci, true); |
c859aa65 | 744 | usb_phy_shutdown(ci->transceiver); |
e443b333 AS |
745 | |
746 | return 0; | |
747 | } | |
748 | ||
5f36e231 AS |
749 | static struct platform_driver ci_hdrc_driver = { |
750 | .probe = ci_hdrc_probe, | |
7690417d | 751 | .remove = ci_hdrc_remove, |
e443b333 | 752 | .driver = { |
5f36e231 | 753 | .name = "ci_hdrc", |
7cf2f861 | 754 | .owner = THIS_MODULE, |
e443b333 AS |
755 | }, |
756 | }; | |
757 | ||
5f36e231 | 758 | module_platform_driver(ci_hdrc_driver); |
e443b333 | 759 | |
5f36e231 | 760 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
761 | MODULE_LICENSE("GPL v2"); |
762 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 763 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |