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57677be5 LJ |
1 | /* |
2 | * otg_fsm.c - ChipIdea USB IP core OTG FSM driver | |
3 | * | |
4 | * Copyright (C) 2014 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Author: Jun Li | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file mainly handles OTG fsm, it includes OTG fsm operations | |
15 | * for HNP and SRP. | |
4dcf720c LJ |
16 | * |
17 | * TODO List | |
18 | * - ADP | |
19 | * - OTG test device | |
57677be5 LJ |
20 | */ |
21 | ||
22 | #include <linux/usb/otg.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | #include <linux/usb/hcd.h> | |
25 | #include <linux/usb/chipidea.h> | |
826cfe75 | 26 | #include <linux/regulator/consumer.h> |
57677be5 LJ |
27 | |
28 | #include "ci.h" | |
29 | #include "bits.h" | |
30 | #include "otg.h" | |
31 | #include "otg_fsm.h" | |
32 | ||
15f75def LJ |
33 | /* Add for otg: interact with user space app */ |
34 | static ssize_t | |
35 | get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
36 | { | |
37 | char *next; | |
38 | unsigned size, t; | |
39 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
40 | ||
41 | next = buf; | |
42 | size = PAGE_SIZE; | |
43 | t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req); | |
44 | size -= t; | |
45 | next += t; | |
46 | ||
47 | return PAGE_SIZE - size; | |
48 | } | |
49 | ||
50 | static ssize_t | |
51 | set_a_bus_req(struct device *dev, struct device_attribute *attr, | |
52 | const char *buf, size_t count) | |
53 | { | |
54 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
55 | ||
56 | if (count > 2) | |
57 | return -1; | |
58 | ||
59 | mutex_lock(&ci->fsm.lock); | |
60 | if (buf[0] == '0') { | |
61 | ci->fsm.a_bus_req = 0; | |
62 | } else if (buf[0] == '1') { | |
63 | /* If a_bus_drop is TRUE, a_bus_req can't be set */ | |
64 | if (ci->fsm.a_bus_drop) { | |
65 | mutex_unlock(&ci->fsm.lock); | |
66 | return count; | |
67 | } | |
68 | ci->fsm.a_bus_req = 1; | |
2dfb46be LJ |
69 | if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) { |
70 | ci->gadget.host_request_flag = 1; | |
71 | mutex_unlock(&ci->fsm.lock); | |
72 | return count; | |
73 | } | |
15f75def LJ |
74 | } |
75 | ||
be6b0c1b | 76 | ci_otg_queue_work(ci); |
15f75def LJ |
77 | mutex_unlock(&ci->fsm.lock); |
78 | ||
79 | return count; | |
80 | } | |
81 | static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req); | |
82 | ||
83 | static ssize_t | |
84 | get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf) | |
85 | { | |
86 | char *next; | |
87 | unsigned size, t; | |
88 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
89 | ||
90 | next = buf; | |
91 | size = PAGE_SIZE; | |
92 | t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop); | |
93 | size -= t; | |
94 | next += t; | |
95 | ||
96 | return PAGE_SIZE - size; | |
97 | } | |
98 | ||
99 | static ssize_t | |
100 | set_a_bus_drop(struct device *dev, struct device_attribute *attr, | |
101 | const char *buf, size_t count) | |
102 | { | |
103 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
104 | ||
105 | if (count > 2) | |
106 | return -1; | |
107 | ||
108 | mutex_lock(&ci->fsm.lock); | |
109 | if (buf[0] == '0') { | |
110 | ci->fsm.a_bus_drop = 0; | |
111 | } else if (buf[0] == '1') { | |
112 | ci->fsm.a_bus_drop = 1; | |
113 | ci->fsm.a_bus_req = 0; | |
114 | } | |
115 | ||
be6b0c1b | 116 | ci_otg_queue_work(ci); |
15f75def LJ |
117 | mutex_unlock(&ci->fsm.lock); |
118 | ||
119 | return count; | |
120 | } | |
121 | static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop, | |
122 | set_a_bus_drop); | |
123 | ||
124 | static ssize_t | |
125 | get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf) | |
126 | { | |
127 | char *next; | |
128 | unsigned size, t; | |
129 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
130 | ||
131 | next = buf; | |
132 | size = PAGE_SIZE; | |
133 | t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req); | |
134 | size -= t; | |
135 | next += t; | |
136 | ||
137 | return PAGE_SIZE - size; | |
138 | } | |
139 | ||
140 | static ssize_t | |
141 | set_b_bus_req(struct device *dev, struct device_attribute *attr, | |
142 | const char *buf, size_t count) | |
143 | { | |
144 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
145 | ||
146 | if (count > 2) | |
147 | return -1; | |
148 | ||
149 | mutex_lock(&ci->fsm.lock); | |
150 | if (buf[0] == '0') | |
151 | ci->fsm.b_bus_req = 0; | |
2dfb46be | 152 | else if (buf[0] == '1') { |
15f75def | 153 | ci->fsm.b_bus_req = 1; |
2dfb46be LJ |
154 | if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) { |
155 | ci->gadget.host_request_flag = 1; | |
156 | mutex_unlock(&ci->fsm.lock); | |
157 | return count; | |
158 | } | |
159 | } | |
15f75def | 160 | |
be6b0c1b | 161 | ci_otg_queue_work(ci); |
15f75def LJ |
162 | mutex_unlock(&ci->fsm.lock); |
163 | ||
164 | return count; | |
165 | } | |
166 | static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req); | |
167 | ||
168 | static ssize_t | |
169 | set_a_clr_err(struct device *dev, struct device_attribute *attr, | |
170 | const char *buf, size_t count) | |
171 | { | |
172 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
173 | ||
174 | if (count > 2) | |
175 | return -1; | |
176 | ||
177 | mutex_lock(&ci->fsm.lock); | |
178 | if (buf[0] == '1') | |
179 | ci->fsm.a_clr_err = 1; | |
180 | ||
be6b0c1b | 181 | ci_otg_queue_work(ci); |
15f75def LJ |
182 | mutex_unlock(&ci->fsm.lock); |
183 | ||
184 | return count; | |
185 | } | |
186 | static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err); | |
187 | ||
188 | static struct attribute *inputs_attrs[] = { | |
189 | &dev_attr_a_bus_req.attr, | |
190 | &dev_attr_a_bus_drop.attr, | |
191 | &dev_attr_b_bus_req.attr, | |
192 | &dev_attr_a_clr_err.attr, | |
193 | NULL, | |
194 | }; | |
195 | ||
196 | static struct attribute_group inputs_attr_group = { | |
197 | .name = "inputs", | |
198 | .attrs = inputs_attrs, | |
199 | }; | |
200 | ||
3a316ec4 LJ |
201 | /* |
202 | * Keep this list in the same order as timers indexed | |
203 | * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h | |
204 | */ | |
205 | static unsigned otg_timer_ms[] = { | |
206 | TA_WAIT_VRISE, | |
207 | TA_WAIT_VFALL, | |
208 | TA_WAIT_BCON, | |
209 | TA_AIDL_BDIS, | |
210 | TB_ASE0_BRST, | |
211 | TA_BIDL_ADIS, | |
4a757547 | 212 | TB_AIDL_BDIS, |
3a316ec4 LJ |
213 | TB_SE0_SRP, |
214 | TB_SRP_FAIL, | |
215 | 0, | |
216 | TB_DATA_PLS, | |
217 | TB_SSEND_SRP, | |
218 | }; | |
219 | ||
826cfe75 LJ |
220 | /* |
221 | * Add timer to active timer list | |
222 | */ | |
2f8a467a | 223 | static void ci_otg_add_timer(struct ci_hdrc *ci, enum otg_fsm_timer t) |
826cfe75 | 224 | { |
3a316ec4 | 225 | unsigned long flags, timer_sec, timer_nsec; |
826cfe75 | 226 | |
2f8a467a | 227 | if (t >= NUM_OTG_FSM_TIMERS) |
826cfe75 LJ |
228 | return; |
229 | ||
3a316ec4 LJ |
230 | spin_lock_irqsave(&ci->lock, flags); |
231 | timer_sec = otg_timer_ms[t] / MSEC_PER_SEC; | |
232 | timer_nsec = (otg_timer_ms[t] % MSEC_PER_SEC) * NSEC_PER_MSEC; | |
233 | ci->hr_timeouts[t] = ktime_add(ktime_get(), | |
234 | ktime_set(timer_sec, timer_nsec)); | |
235 | ci->enabled_otg_timer_bits |= (1 << t); | |
236 | if ((ci->next_otg_timer == NUM_OTG_FSM_TIMERS) || | |
237 | (ci->hr_timeouts[ci->next_otg_timer].tv64 > | |
238 | ci->hr_timeouts[t].tv64)) { | |
239 | ci->next_otg_timer = t; | |
240 | hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, | |
241 | ci->hr_timeouts[t], NSEC_PER_MSEC, | |
242 | HRTIMER_MODE_ABS); | |
243 | } | |
244 | spin_unlock_irqrestore(&ci->lock, flags); | |
826cfe75 LJ |
245 | } |
246 | ||
247 | /* | |
248 | * Remove timer from active timer list | |
249 | */ | |
2f8a467a | 250 | static void ci_otg_del_timer(struct ci_hdrc *ci, enum otg_fsm_timer t) |
826cfe75 | 251 | { |
3a316ec4 LJ |
252 | unsigned long flags, enabled_timer_bits; |
253 | enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS; | |
826cfe75 | 254 | |
3a316ec4 LJ |
255 | if ((t >= NUM_OTG_FSM_TIMERS) || |
256 | !(ci->enabled_otg_timer_bits & (1 << t))) | |
826cfe75 LJ |
257 | return; |
258 | ||
3a316ec4 LJ |
259 | spin_lock_irqsave(&ci->lock, flags); |
260 | ci->enabled_otg_timer_bits &= ~(1 << t); | |
261 | if (ci->next_otg_timer == t) { | |
262 | if (ci->enabled_otg_timer_bits == 0) { | |
263 | /* No enabled timers after delete it */ | |
264 | hrtimer_cancel(&ci->otg_fsm_hrtimer); | |
265 | ci->next_otg_timer = NUM_OTG_FSM_TIMERS; | |
266 | } else { | |
267 | /* Find the next timer */ | |
268 | enabled_timer_bits = ci->enabled_otg_timer_bits; | |
269 | for_each_set_bit(cur_timer, &enabled_timer_bits, | |
270 | NUM_OTG_FSM_TIMERS) { | |
271 | if ((next_timer == NUM_OTG_FSM_TIMERS) || | |
272 | (ci->hr_timeouts[next_timer].tv64 < | |
273 | ci->hr_timeouts[cur_timer].tv64)) | |
274 | next_timer = cur_timer; | |
275 | } | |
4dcf720c LJ |
276 | } |
277 | } | |
3a316ec4 LJ |
278 | if (next_timer != NUM_OTG_FSM_TIMERS) { |
279 | ci->next_otg_timer = next_timer; | |
280 | hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, | |
281 | ci->hr_timeouts[next_timer], NSEC_PER_MSEC, | |
282 | HRTIMER_MODE_ABS); | |
961ea496 | 283 | } |
3a316ec4 | 284 | spin_unlock_irqrestore(&ci->lock, flags); |
4dcf720c LJ |
285 | } |
286 | ||
3a316ec4 LJ |
287 | /* OTG FSM timer handlers */ |
288 | static int a_wait_vrise_tmout(struct ci_hdrc *ci) | |
e287b67b | 289 | { |
3a316ec4 LJ |
290 | ci->fsm.a_wait_vrise_tmout = 1; |
291 | return 0; | |
e287b67b LJ |
292 | } |
293 | ||
3a316ec4 | 294 | static int a_wait_vfall_tmout(struct ci_hdrc *ci) |
e287b67b | 295 | { |
3a316ec4 LJ |
296 | ci->fsm.a_wait_vfall_tmout = 1; |
297 | return 0; | |
e287b67b LJ |
298 | } |
299 | ||
3a316ec4 | 300 | static int a_wait_bcon_tmout(struct ci_hdrc *ci) |
e287b67b | 301 | { |
3a316ec4 LJ |
302 | ci->fsm.a_wait_bcon_tmout = 1; |
303 | return 0; | |
304 | } | |
e287b67b | 305 | |
3a316ec4 LJ |
306 | static int a_aidl_bdis_tmout(struct ci_hdrc *ci) |
307 | { | |
308 | ci->fsm.a_aidl_bdis_tmout = 1; | |
309 | return 0; | |
e287b67b LJ |
310 | } |
311 | ||
3a316ec4 | 312 | static int b_ase0_brst_tmout(struct ci_hdrc *ci) |
e287b67b | 313 | { |
3a316ec4 LJ |
314 | ci->fsm.b_ase0_brst_tmout = 1; |
315 | return 0; | |
316 | } | |
e287b67b | 317 | |
3a316ec4 LJ |
318 | static int a_bidl_adis_tmout(struct ci_hdrc *ci) |
319 | { | |
320 | ci->fsm.a_bidl_adis_tmout = 1; | |
321 | return 0; | |
322 | } | |
e287b67b | 323 | |
4a757547 LJ |
324 | static int b_aidl_bdis_tmout(struct ci_hdrc *ci) |
325 | { | |
326 | ci->fsm.a_bus_suspend = 1; | |
327 | return 0; | |
328 | } | |
329 | ||
3a316ec4 LJ |
330 | static int b_se0_srp_tmout(struct ci_hdrc *ci) |
331 | { | |
332 | ci->fsm.b_se0_srp = 1; | |
333 | return 0; | |
e287b67b LJ |
334 | } |
335 | ||
3a316ec4 | 336 | static int b_srp_fail_tmout(struct ci_hdrc *ci) |
e287b67b | 337 | { |
3a316ec4 LJ |
338 | ci->fsm.b_srp_done = 1; |
339 | return 1; | |
340 | } | |
e287b67b | 341 | |
3a316ec4 LJ |
342 | static int b_data_pls_tmout(struct ci_hdrc *ci) |
343 | { | |
e287b67b LJ |
344 | ci->fsm.b_srp_done = 1; |
345 | ci->fsm.b_bus_req = 0; | |
346 | if (ci->fsm.power_up) | |
347 | ci->fsm.power_up = 0; | |
e287b67b | 348 | hw_write_otgsc(ci, OTGSC_HABA, 0); |
3a316ec4 LJ |
349 | pm_runtime_put(ci->dev); |
350 | return 0; | |
351 | } | |
e287b67b | 352 | |
3a316ec4 LJ |
353 | static int b_ssend_srp_tmout(struct ci_hdrc *ci) |
354 | { | |
355 | ci->fsm.b_ssend_srp = 1; | |
356 | /* only vbus fall below B_sess_vld in b_idle state */ | |
357 | if (ci->fsm.otg->state == OTG_STATE_B_IDLE) | |
358 | return 0; | |
359 | else | |
360 | return 1; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Keep this list in the same order as timers indexed | |
365 | * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h | |
366 | */ | |
367 | static int (*otg_timer_handlers[])(struct ci_hdrc *) = { | |
368 | a_wait_vrise_tmout, /* A_WAIT_VRISE */ | |
369 | a_wait_vfall_tmout, /* A_WAIT_VFALL */ | |
370 | a_wait_bcon_tmout, /* A_WAIT_BCON */ | |
371 | a_aidl_bdis_tmout, /* A_AIDL_BDIS */ | |
372 | b_ase0_brst_tmout, /* B_ASE0_BRST */ | |
373 | a_bidl_adis_tmout, /* A_BIDL_ADIS */ | |
4a757547 | 374 | b_aidl_bdis_tmout, /* B_AIDL_BDIS */ |
3a316ec4 LJ |
375 | b_se0_srp_tmout, /* B_SE0_SRP */ |
376 | b_srp_fail_tmout, /* B_SRP_FAIL */ | |
377 | NULL, /* A_WAIT_ENUM */ | |
378 | b_data_pls_tmout, /* B_DATA_PLS */ | |
379 | b_ssend_srp_tmout, /* B_SSEND_SRP */ | |
380 | }; | |
381 | ||
382 | /* | |
383 | * Enable the next nearest enabled timer if have | |
384 | */ | |
385 | static enum hrtimer_restart ci_otg_hrtimer_func(struct hrtimer *t) | |
386 | { | |
387 | struct ci_hdrc *ci = container_of(t, struct ci_hdrc, otg_fsm_hrtimer); | |
388 | ktime_t now, *timeout; | |
389 | unsigned long enabled_timer_bits; | |
390 | unsigned long flags; | |
391 | enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS; | |
392 | int ret = -EINVAL; | |
393 | ||
394 | spin_lock_irqsave(&ci->lock, flags); | |
395 | enabled_timer_bits = ci->enabled_otg_timer_bits; | |
396 | ci->next_otg_timer = NUM_OTG_FSM_TIMERS; | |
397 | ||
398 | now = ktime_get(); | |
399 | for_each_set_bit(cur_timer, &enabled_timer_bits, NUM_OTG_FSM_TIMERS) { | |
400 | if (now.tv64 >= ci->hr_timeouts[cur_timer].tv64) { | |
401 | ci->enabled_otg_timer_bits &= ~(1 << cur_timer); | |
402 | if (otg_timer_handlers[cur_timer]) | |
403 | ret = otg_timer_handlers[cur_timer](ci); | |
404 | } else { | |
405 | if ((next_timer == NUM_OTG_FSM_TIMERS) || | |
406 | (ci->hr_timeouts[cur_timer].tv64 < | |
407 | ci->hr_timeouts[next_timer].tv64)) | |
408 | next_timer = cur_timer; | |
409 | } | |
410 | } | |
411 | /* Enable the next nearest timer */ | |
412 | if (next_timer < NUM_OTG_FSM_TIMERS) { | |
413 | timeout = &ci->hr_timeouts[next_timer]; | |
414 | hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, *timeout, | |
415 | NSEC_PER_MSEC, HRTIMER_MODE_ABS); | |
416 | ci->next_otg_timer = next_timer; | |
417 | } | |
418 | spin_unlock_irqrestore(&ci->lock, flags); | |
419 | ||
420 | if (!ret) | |
421 | ci_otg_queue_work(ci); | |
422 | ||
423 | return HRTIMER_NORESTART; | |
e287b67b LJ |
424 | } |
425 | ||
426 | /* Initialize timers */ | |
427 | static int ci_otg_init_timers(struct ci_hdrc *ci) | |
428 | { | |
3a316ec4 LJ |
429 | hrtimer_init(&ci->otg_fsm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); |
430 | ci->otg_fsm_hrtimer.function = ci_otg_hrtimer_func; | |
e287b67b | 431 | |
e287b67b LJ |
432 | return 0; |
433 | } | |
434 | ||
826cfe75 LJ |
435 | /* -------------------------------------------------------------*/ |
436 | /* Operations that will be called from OTG Finite State Machine */ | |
437 | /* -------------------------------------------------------------*/ | |
438 | static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) | |
439 | { | |
440 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
441 | ||
442 | if (t < NUM_OTG_FSM_TIMERS) | |
443 | ci_otg_add_timer(ci, t); | |
444 | return; | |
445 | } | |
446 | ||
447 | static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) | |
448 | { | |
449 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
450 | ||
451 | if (t < NUM_OTG_FSM_TIMERS) | |
452 | ci_otg_del_timer(ci, t); | |
453 | return; | |
454 | } | |
455 | ||
456 | /* | |
457 | * A-device drive vbus: turn on vbus regulator and enable port power | |
458 | * Data pulse irq should be disabled while vbus is on. | |
459 | */ | |
460 | static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on) | |
461 | { | |
462 | int ret; | |
463 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
464 | ||
465 | if (on) { | |
466 | /* Enable power power */ | |
467 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
468 | PORTSC_PP); | |
469 | if (ci->platdata->reg_vbus) { | |
470 | ret = regulator_enable(ci->platdata->reg_vbus); | |
471 | if (ret) { | |
472 | dev_err(ci->dev, | |
473 | "Failed to enable vbus regulator, ret=%d\n", | |
474 | ret); | |
475 | return; | |
476 | } | |
477 | } | |
478 | /* Disable data pulse irq */ | |
479 | hw_write_otgsc(ci, OTGSC_DPIE, 0); | |
480 | ||
481 | fsm->a_srp_det = 0; | |
482 | fsm->power_up = 0; | |
483 | } else { | |
484 | if (ci->platdata->reg_vbus) | |
485 | regulator_disable(ci->platdata->reg_vbus); | |
486 | ||
487 | fsm->a_bus_drop = 1; | |
488 | fsm->a_bus_req = 0; | |
489 | } | |
490 | } | |
491 | ||
492 | /* | |
493 | * Control data line by Run Stop bit. | |
494 | */ | |
495 | static void ci_otg_loc_conn(struct otg_fsm *fsm, int on) | |
496 | { | |
497 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
498 | ||
499 | if (on) | |
500 | hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS); | |
501 | else | |
502 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
503 | } | |
504 | ||
505 | /* | |
506 | * Generate SOF by host. | |
826cfe75 LJ |
507 | * In host mode, controller will automatically send SOF. |
508 | * Suspend will block the data on the port. | |
8c100e74 LJ |
509 | * |
510 | * This is controlled through usbcore by usb autosuspend, | |
511 | * so the usb device class driver need support autosuspend, | |
512 | * otherwise the bus suspend will not happen. | |
826cfe75 LJ |
513 | */ |
514 | static void ci_otg_loc_sof(struct otg_fsm *fsm, int on) | |
515 | { | |
8c100e74 | 516 | struct usb_device *udev; |
826cfe75 | 517 | |
8c100e74 LJ |
518 | if (!fsm->otg->host) |
519 | return; | |
520 | ||
521 | udev = usb_hub_find_child(fsm->otg->host->root_hub, 1); | |
522 | if (!udev) | |
523 | return; | |
524 | ||
525 | if (on) { | |
526 | usb_disable_autosuspend(udev); | |
527 | } else { | |
528 | pm_runtime_set_autosuspend_delay(&udev->dev, 0); | |
529 | usb_enable_autosuspend(udev); | |
530 | } | |
826cfe75 LJ |
531 | } |
532 | ||
533 | /* | |
534 | * Start SRP pulsing by data-line pulsing, | |
535 | * no v-bus pulsing followed | |
536 | */ | |
537 | static void ci_otg_start_pulse(struct otg_fsm *fsm) | |
538 | { | |
539 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
540 | ||
541 | /* Hardware Assistant Data pulse */ | |
542 | hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP); | |
543 | ||
3a316ec4 | 544 | pm_runtime_get(ci->dev); |
826cfe75 LJ |
545 | ci_otg_add_timer(ci, B_DATA_PLS); |
546 | } | |
547 | ||
548 | static int ci_otg_start_host(struct otg_fsm *fsm, int on) | |
549 | { | |
550 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
551 | ||
826cfe75 LJ |
552 | if (on) { |
553 | ci_role_stop(ci); | |
554 | ci_role_start(ci, CI_ROLE_HOST); | |
555 | } else { | |
556 | ci_role_stop(ci); | |
826cfe75 LJ |
557 | ci_role_start(ci, CI_ROLE_GADGET); |
558 | } | |
826cfe75 LJ |
559 | return 0; |
560 | } | |
561 | ||
562 | static int ci_otg_start_gadget(struct otg_fsm *fsm, int on) | |
563 | { | |
564 | struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm); | |
565 | ||
826cfe75 LJ |
566 | if (on) |
567 | usb_gadget_vbus_connect(&ci->gadget); | |
568 | else | |
569 | usb_gadget_vbus_disconnect(&ci->gadget); | |
826cfe75 LJ |
570 | |
571 | return 0; | |
572 | } | |
573 | ||
574 | static struct otg_fsm_ops ci_otg_ops = { | |
575 | .drv_vbus = ci_otg_drv_vbus, | |
576 | .loc_conn = ci_otg_loc_conn, | |
577 | .loc_sof = ci_otg_loc_sof, | |
578 | .start_pulse = ci_otg_start_pulse, | |
579 | .add_timer = ci_otg_fsm_add_timer, | |
580 | .del_timer = ci_otg_fsm_del_timer, | |
581 | .start_host = ci_otg_start_host, | |
582 | .start_gadget = ci_otg_start_gadget, | |
583 | }; | |
584 | ||
4dcf720c LJ |
585 | int ci_otg_fsm_work(struct ci_hdrc *ci) |
586 | { | |
587 | /* | |
588 | * Don't do fsm transition for B device | |
589 | * when there is no gadget class driver | |
590 | */ | |
591 | if (ci->fsm.id && !(ci->driver) && | |
e47d9254 | 592 | ci->fsm.otg->state < OTG_STATE_A_IDLE) |
4dcf720c LJ |
593 | return 0; |
594 | ||
961ea496 | 595 | pm_runtime_get_sync(ci->dev); |
4dcf720c | 596 | if (otg_statemachine(&ci->fsm)) { |
e47d9254 | 597 | if (ci->fsm.otg->state == OTG_STATE_A_IDLE) { |
4dcf720c LJ |
598 | /* |
599 | * Further state change for cases: | |
600 | * a_idle to b_idle; or | |
601 | * a_idle to a_wait_vrise due to ID change(1->0), so | |
602 | * B-dev becomes A-dev can try to start new session | |
603 | * consequently; or | |
604 | * a_idle to a_wait_vrise when power up | |
605 | */ | |
606 | if ((ci->fsm.id) || (ci->id_event) || | |
3a316ec4 | 607 | (ci->fsm.power_up)) { |
be6b0c1b | 608 | ci_otg_queue_work(ci); |
3a316ec4 LJ |
609 | } else { |
610 | /* Enable data pulse irq */ | |
611 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | | |
612 | PORTSC_PP, 0); | |
613 | hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS); | |
614 | hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE); | |
615 | } | |
4dcf720c LJ |
616 | if (ci->id_event) |
617 | ci->id_event = false; | |
e47d9254 | 618 | } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) { |
4dcf720c LJ |
619 | if (ci->fsm.b_sess_vld) { |
620 | ci->fsm.power_up = 0; | |
621 | /* | |
622 | * Further transite to b_periphearl state | |
623 | * when register gadget driver with vbus on | |
624 | */ | |
be6b0c1b | 625 | ci_otg_queue_work(ci); |
4dcf720c | 626 | } |
961ea496 LJ |
627 | } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) { |
628 | pm_runtime_mark_last_busy(ci->dev); | |
629 | pm_runtime_put_autosuspend(ci->dev); | |
630 | return 0; | |
4dcf720c LJ |
631 | } |
632 | } | |
961ea496 | 633 | pm_runtime_put_sync(ci->dev); |
4dcf720c LJ |
634 | return 0; |
635 | } | |
636 | ||
637 | /* | |
638 | * Update fsm variables in each state if catching expected interrupts, | |
639 | * called by otg fsm isr. | |
640 | */ | |
641 | static void ci_otg_fsm_event(struct ci_hdrc *ci) | |
642 | { | |
643 | u32 intr_sts, otg_bsess_vld, port_conn; | |
644 | struct otg_fsm *fsm = &ci->fsm; | |
645 | ||
646 | intr_sts = hw_read_intr_status(ci); | |
647 | otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV); | |
648 | port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS); | |
649 | ||
e47d9254 | 650 | switch (ci->fsm.otg->state) { |
4dcf720c LJ |
651 | case OTG_STATE_A_WAIT_BCON: |
652 | if (port_conn) { | |
653 | fsm->b_conn = 1; | |
654 | fsm->a_bus_req = 1; | |
be6b0c1b | 655 | ci_otg_queue_work(ci); |
4dcf720c LJ |
656 | } |
657 | break; | |
658 | case OTG_STATE_B_IDLE: | |
659 | if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) { | |
660 | fsm->b_sess_vld = 1; | |
be6b0c1b | 661 | ci_otg_queue_work(ci); |
4dcf720c LJ |
662 | } |
663 | break; | |
664 | case OTG_STATE_B_PERIPHERAL: | |
665 | if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) { | |
4a757547 | 666 | ci_otg_add_timer(ci, B_AIDL_BDIS); |
4dcf720c | 667 | } else if (intr_sts & USBi_PCI) { |
4a757547 | 668 | ci_otg_del_timer(ci, B_AIDL_BDIS); |
4dcf720c LJ |
669 | if (fsm->a_bus_suspend == 1) |
670 | fsm->a_bus_suspend = 0; | |
671 | } | |
672 | break; | |
673 | case OTG_STATE_B_HOST: | |
674 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
675 | fsm->a_conn = 0; | |
676 | fsm->b_bus_req = 0; | |
be6b0c1b | 677 | ci_otg_queue_work(ci); |
4dcf720c LJ |
678 | } |
679 | break; | |
680 | case OTG_STATE_A_PERIPHERAL: | |
681 | if (intr_sts & USBi_SLI) { | |
682 | fsm->b_bus_suspend = 1; | |
683 | /* | |
684 | * Init a timer to know how long this suspend | |
6629467b | 685 | * will continue, if time out, indicates B no longer |
4dcf720c LJ |
686 | * wants to be host role |
687 | */ | |
688 | ci_otg_add_timer(ci, A_BIDL_ADIS); | |
689 | } | |
690 | ||
691 | if (intr_sts & USBi_URI) | |
692 | ci_otg_del_timer(ci, A_BIDL_ADIS); | |
693 | ||
694 | if (intr_sts & USBi_PCI) { | |
695 | if (fsm->b_bus_suspend == 1) { | |
696 | ci_otg_del_timer(ci, A_BIDL_ADIS); | |
697 | fsm->b_bus_suspend = 0; | |
698 | } | |
699 | } | |
700 | break; | |
701 | case OTG_STATE_A_SUSPEND: | |
702 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
703 | fsm->b_conn = 0; | |
704 | ||
705 | /* if gadget driver is binded */ | |
706 | if (ci->driver) { | |
707 | /* A device to be peripheral mode */ | |
708 | ci->gadget.is_a_peripheral = 1; | |
709 | } | |
be6b0c1b | 710 | ci_otg_queue_work(ci); |
4dcf720c LJ |
711 | } |
712 | break; | |
713 | case OTG_STATE_A_HOST: | |
714 | if ((intr_sts & USBi_PCI) && !port_conn) { | |
715 | fsm->b_conn = 0; | |
be6b0c1b | 716 | ci_otg_queue_work(ci); |
4dcf720c LJ |
717 | } |
718 | break; | |
719 | case OTG_STATE_B_WAIT_ACON: | |
720 | if ((intr_sts & USBi_PCI) && port_conn) { | |
721 | fsm->a_conn = 1; | |
be6b0c1b | 722 | ci_otg_queue_work(ci); |
4dcf720c LJ |
723 | } |
724 | break; | |
725 | default: | |
726 | break; | |
727 | } | |
728 | } | |
729 | ||
730 | /* | |
731 | * ci_otg_irq - otg fsm related irq handling | |
732 | * and also update otg fsm variable by monitoring usb host and udc | |
733 | * state change interrupts. | |
734 | * @ci: ci_hdrc | |
735 | */ | |
736 | irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci) | |
737 | { | |
738 | irqreturn_t retval = IRQ_NONE; | |
739 | u32 otgsc, otg_int_src = 0; | |
740 | struct otg_fsm *fsm = &ci->fsm; | |
741 | ||
742 | otgsc = hw_read_otgsc(ci, ~0); | |
743 | otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8); | |
744 | fsm->id = (otgsc & OTGSC_ID) ? 1 : 0; | |
745 | ||
746 | if (otg_int_src) { | |
3a316ec4 | 747 | if (otg_int_src & OTGSC_DPIS) { |
4dcf720c LJ |
748 | hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS); |
749 | fsm->a_srp_det = 1; | |
750 | fsm->a_bus_drop = 0; | |
751 | } else if (otg_int_src & OTGSC_IDIS) { | |
752 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
753 | if (fsm->id == 0) { | |
754 | fsm->a_bus_drop = 0; | |
755 | fsm->a_bus_req = 1; | |
756 | ci->id_event = true; | |
757 | } | |
758 | } else if (otg_int_src & OTGSC_BSVIS) { | |
759 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
760 | if (otgsc & OTGSC_BSV) { | |
761 | fsm->b_sess_vld = 1; | |
762 | ci_otg_del_timer(ci, B_SSEND_SRP); | |
763 | ci_otg_del_timer(ci, B_SRP_FAIL); | |
764 | fsm->b_ssend_srp = 0; | |
765 | } else { | |
766 | fsm->b_sess_vld = 0; | |
767 | if (fsm->id) | |
768 | ci_otg_add_timer(ci, B_SSEND_SRP); | |
769 | } | |
770 | } else if (otg_int_src & OTGSC_AVVIS) { | |
771 | hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS); | |
772 | if (otgsc & OTGSC_AVV) { | |
773 | fsm->a_vbus_vld = 1; | |
774 | } else { | |
775 | fsm->a_vbus_vld = 0; | |
776 | fsm->b_conn = 0; | |
777 | } | |
778 | } | |
be6b0c1b | 779 | ci_otg_queue_work(ci); |
4dcf720c LJ |
780 | return IRQ_HANDLED; |
781 | } | |
782 | ||
783 | ci_otg_fsm_event(ci); | |
784 | ||
785 | return retval; | |
786 | } | |
787 | ||
788 | void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci) | |
789 | { | |
be6b0c1b | 790 | ci_otg_queue_work(ci); |
4dcf720c LJ |
791 | } |
792 | ||
57677be5 LJ |
793 | int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci) |
794 | { | |
e287b67b | 795 | int retval = 0; |
57677be5 | 796 | |
1e5e2d3d AT |
797 | if (ci->phy) |
798 | ci->otg.phy = ci->phy; | |
799 | else | |
800 | ci->otg.usb_phy = ci->usb_phy; | |
57677be5 | 801 | |
ef44cb42 AT |
802 | ci->otg.gadget = &ci->gadget; |
803 | ci->fsm.otg = &ci->otg; | |
57677be5 LJ |
804 | ci->fsm.power_up = 1; |
805 | ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0; | |
e47d9254 | 806 | ci->fsm.otg->state = OTG_STATE_UNDEFINED; |
826cfe75 | 807 | ci->fsm.ops = &ci_otg_ops; |
75d2f754 LJ |
808 | ci->gadget.hnp_polling_support = 1; |
809 | ci->fsm.host_req_flag = devm_kzalloc(ci->dev, 1, GFP_KERNEL); | |
810 | if (!ci->fsm.host_req_flag) | |
811 | return -ENOMEM; | |
57677be5 LJ |
812 | |
813 | mutex_init(&ci->fsm.lock); | |
814 | ||
e287b67b LJ |
815 | retval = ci_otg_init_timers(ci); |
816 | if (retval) { | |
817 | dev_err(ci->dev, "Couldn't init OTG timers\n"); | |
818 | return retval; | |
819 | } | |
3a316ec4 LJ |
820 | ci->enabled_otg_timer_bits = 0; |
821 | ci->next_otg_timer = NUM_OTG_FSM_TIMERS; | |
e287b67b | 822 | |
15f75def LJ |
823 | retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group); |
824 | if (retval < 0) { | |
825 | dev_dbg(ci->dev, | |
826 | "Can't register sysfs attr group: %d\n", retval); | |
827 | return retval; | |
828 | } | |
829 | ||
57677be5 LJ |
830 | /* Enable A vbus valid irq */ |
831 | hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE); | |
832 | ||
833 | if (ci->fsm.id) { | |
834 | ci->fsm.b_ssend_srp = | |
835 | hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1; | |
836 | ci->fsm.b_sess_vld = | |
837 | hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0; | |
838 | /* Enable BSV irq */ | |
839 | hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE); | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
15f75def LJ |
844 | |
845 | void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci) | |
846 | { | |
847 | sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group); | |
848 | } |