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usb: chipidea: brush up structure definitions
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aa69a809 1/*
e443b333 2 * udc.h - ChipIdea UDC driver
aa69a809
DL
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
36825a2d 13#include <linux/delay.h>
aa69a809
DL
14#include <linux/device.h>
15#include <linux/dmapool.h>
16#include <linux/dma-mapping.h>
17#include <linux/init.h>
62bb84ed
AS
18#include <linux/platform_device.h>
19#include <linux/module.h>
aa69a809 20#include <linux/interrupt.h>
aa69a809
DL
21#include <linux/io.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
5a0e3ad6 24#include <linux/slab.h>
c036019e 25#include <linux/pm_runtime.h>
aa69a809
DL
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
f01ef574 28#include <linux/usb/otg.h>
e443b333 29#include <linux/usb/chipidea.h>
aa69a809 30
e443b333
AS
31#include "ci.h"
32#include "udc.h"
33#include "bits.h"
34#include "debug.h"
954aad8c 35
aa69a809
DL
36/* control endpoint description */
37static const struct usb_endpoint_descriptor
ca9cfea0 38ctrl_endpt_out_desc = {
aa69a809
DL
39 .bLength = USB_DT_ENDPOINT_SIZE,
40 .bDescriptorType = USB_DT_ENDPOINT,
41
ca9cfea0
PK
42 .bEndpointAddress = USB_DIR_OUT,
43 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
44 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
45};
46
47static const struct usb_endpoint_descriptor
48ctrl_endpt_in_desc = {
49 .bLength = USB_DT_ENDPOINT_SIZE,
50 .bDescriptorType = USB_DT_ENDPOINT,
51
52 .bEndpointAddress = USB_DIR_IN,
aa69a809
DL
53 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
54 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
55};
56
aa69a809
DL
57/**
58 * hw_ep_bit: calculates the bit number
59 * @num: endpoint number
60 * @dir: endpoint direction
61 *
62 * This function returns bit number
63 */
64static inline int hw_ep_bit(int num, int dir)
65{
66 return num + (dir ? 16 : 0);
67}
68
e443b333 69static inline int ep_to_bit(struct ci13xxx *udc, int n)
dd39c358 70{
d3595d13 71 int fill = 16 - udc->hw_ep_max / 2;
dd39c358 72
d3595d13 73 if (n >= udc->hw_ep_max / 2)
dd39c358
MKB
74 n += fill;
75
76 return n;
77}
78
aa69a809
DL
79/**
80 * hw_device_state: enables/disables interrupts & starts/stops device (execute
81 * without interruption)
82 * @dma: 0 => disable, !0 => enable and set dma engine
83 *
84 * This function returns an error code
85 */
d3595d13 86static int hw_device_state(struct ci13xxx *udc, u32 dma)
aa69a809
DL
87{
88 if (dma) {
262c1632 89 hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
aa69a809 90 /* interrupt, error, port change, reset, sleep/suspend */
262c1632 91 hw_write(udc, OP_USBINTR, ~0,
aa69a809 92 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
262c1632 93 hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
aa69a809 94 } else {
262c1632
AS
95 hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
96 hw_write(udc, OP_USBINTR, ~0, 0);
aa69a809
DL
97 }
98 return 0;
99}
100
101/**
102 * hw_ep_flush: flush endpoint fifo (execute without interruption)
103 * @num: endpoint number
104 * @dir: endpoint direction
105 *
106 * This function returns an error code
107 */
d3595d13 108static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
aa69a809
DL
109{
110 int n = hw_ep_bit(num, dir);
111
112 do {
113 /* flush any pending transfer */
262c1632
AS
114 hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
115 while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
aa69a809 116 cpu_relax();
262c1632 117 } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
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118
119 return 0;
120}
121
122/**
123 * hw_ep_disable: disables endpoint (execute without interruption)
124 * @num: endpoint number
125 * @dir: endpoint direction
126 *
127 * This function returns an error code
128 */
d3595d13 129static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
aa69a809 130{
d3595d13 131 hw_ep_flush(udc, num, dir);
262c1632 132 hw_write(udc, OP_ENDPTCTRL + num,
d3595d13 133 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
aa69a809
DL
134 return 0;
135}
136
137/**
138 * hw_ep_enable: enables endpoint (execute without interruption)
139 * @num: endpoint number
140 * @dir: endpoint direction
141 * @type: endpoint type
142 *
143 * This function returns an error code
144 */
d3595d13 145static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
aa69a809
DL
146{
147 u32 mask, data;
148
149 if (dir) {
150 mask = ENDPTCTRL_TXT; /* type */
151 data = type << ffs_nr(mask);
152
153 mask |= ENDPTCTRL_TXS; /* unstall */
154 mask |= ENDPTCTRL_TXR; /* reset data toggle */
155 data |= ENDPTCTRL_TXR;
156 mask |= ENDPTCTRL_TXE; /* enable */
157 data |= ENDPTCTRL_TXE;
158 } else {
159 mask = ENDPTCTRL_RXT; /* type */
160 data = type << ffs_nr(mask);
161
162 mask |= ENDPTCTRL_RXS; /* unstall */
163 mask |= ENDPTCTRL_RXR; /* reset data toggle */
164 data |= ENDPTCTRL_RXR;
165 mask |= ENDPTCTRL_RXE; /* enable */
166 data |= ENDPTCTRL_RXE;
167 }
262c1632 168 hw_write(udc, OP_ENDPTCTRL + num, mask, data);
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DL
169 return 0;
170}
171
172/**
173 * hw_ep_get_halt: return endpoint halt status
174 * @num: endpoint number
175 * @dir: endpoint direction
176 *
177 * This function returns 1 if endpoint halted
178 */
d3595d13 179static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
aa69a809
DL
180{
181 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
182
262c1632 183 return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
aa69a809
DL
184}
185
aa69a809
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186/**
187 * hw_test_and_clear_setup_status: test & clear setup status (execute without
188 * interruption)
dd39c358 189 * @n: endpoint number
aa69a809
DL
190 *
191 * This function returns setup status
192 */
d3595d13 193static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
aa69a809 194{
d3595d13 195 n = ep_to_bit(udc, n);
262c1632 196 return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
aa69a809
DL
197}
198
199/**
200 * hw_ep_prime: primes endpoint (execute without interruption)
201 * @num: endpoint number
202 * @dir: endpoint direction
203 * @is_ctrl: true if control endpoint
204 *
205 * This function returns an error code
206 */
d3595d13 207static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
aa69a809
DL
208{
209 int n = hw_ep_bit(num, dir);
210
262c1632 211 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
aa69a809
DL
212 return -EAGAIN;
213
262c1632 214 hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
aa69a809 215
262c1632 216 while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
aa69a809 217 cpu_relax();
262c1632 218 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
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DL
219 return -EAGAIN;
220
221 /* status shoult be tested according with manual but it doesn't work */
222 return 0;
223}
224
225/**
226 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
227 * without interruption)
228 * @num: endpoint number
229 * @dir: endpoint direction
230 * @value: true => stall, false => unstall
231 *
232 * This function returns an error code
233 */
d3595d13 234static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
aa69a809
DL
235{
236 if (value != 0 && value != 1)
237 return -EINVAL;
238
239 do {
262c1632 240 enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
aa69a809
DL
241 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
242 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
243
244 /* data toggle - reserved for EP0 but it's in ESS */
262c1632
AS
245 hw_write(udc, reg, mask_xs|mask_xr,
246 value ? mask_xs : mask_xr);
d3595d13 247 } while (value != hw_ep_get_halt(udc, num, dir));
aa69a809
DL
248
249 return 0;
250}
251
aa69a809
DL
252/**
253 * hw_is_port_high_speed: test if port is high speed
254 *
255 * This function returns true if high speed port
256 */
d3595d13 257static int hw_port_is_high_speed(struct ci13xxx *udc)
aa69a809 258{
262c1632
AS
259 return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
260 hw_read(udc, OP_PORTSC, PORTSC_HSP);
aa69a809
DL
261}
262
aa69a809
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263/**
264 * hw_read_intr_enable: returns interrupt enable register
265 *
266 * This function returns register data
267 */
d3595d13 268static u32 hw_read_intr_enable(struct ci13xxx *udc)
aa69a809 269{
262c1632 270 return hw_read(udc, OP_USBINTR, ~0);
aa69a809
DL
271}
272
273/**
274 * hw_read_intr_status: returns interrupt status register
275 *
276 * This function returns register data
277 */
d3595d13 278static u32 hw_read_intr_status(struct ci13xxx *udc)
aa69a809 279{
262c1632 280 return hw_read(udc, OP_USBSTS, ~0);
aa69a809
DL
281}
282
aa69a809
DL
283/**
284 * hw_test_and_clear_complete: test & clear complete status (execute without
285 * interruption)
dd39c358 286 * @n: endpoint number
aa69a809
DL
287 *
288 * This function returns complete status
289 */
d3595d13 290static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
aa69a809 291{
d3595d13 292 n = ep_to_bit(udc, n);
262c1632 293 return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
aa69a809
DL
294}
295
296/**
297 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
298 * without interruption)
299 *
300 * This function returns active interrutps
301 */
d3595d13 302static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
aa69a809 303{
d3595d13 304 u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
aa69a809 305
262c1632 306 hw_write(udc, OP_USBSTS, ~0, reg);
aa69a809
DL
307 return reg;
308}
309
310/**
311 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
312 * interruption)
313 *
314 * This function returns guard value
315 */
d3595d13 316static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
aa69a809 317{
262c1632 318 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
aa69a809
DL
319}
320
321/**
322 * hw_test_and_set_setup_guard: test & set setup guard (execute without
323 * interruption)
324 *
325 * This function returns guard value
326 */
d3595d13 327static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
aa69a809 328{
262c1632 329 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
aa69a809
DL
330}
331
332/**
333 * hw_usb_set_address: configures USB address (execute without interruption)
334 * @value: new USB address
335 *
ef15e549
AS
336 * This function explicitly sets the address, without the "USBADRA" (advance)
337 * feature, which is not supported by older versions of the controller.
aa69a809 338 */
ef15e549 339static void hw_usb_set_address(struct ci13xxx *udc, u8 value)
aa69a809 340{
ef15e549
AS
341 hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR,
342 value << ffs_nr(DEVICEADDR_USBADR));
aa69a809
DL
343}
344
345/**
346 * hw_usb_reset: restart device after a bus reset (execute without
347 * interruption)
348 *
349 * This function returns an error code
350 */
d3595d13 351static int hw_usb_reset(struct ci13xxx *udc)
aa69a809 352{
d3595d13 353 hw_usb_set_address(udc, 0);
aa69a809
DL
354
355 /* ESS flushes only at end?!? */
262c1632 356 hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
aa69a809
DL
357
358 /* clear setup token semaphores */
262c1632 359 hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
aa69a809
DL
360
361 /* clear complete status */
262c1632 362 hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
aa69a809
DL
363
364 /* wait until all bits cleared */
262c1632 365 while (hw_read(udc, OP_ENDPTPRIME, ~0))
aa69a809
DL
366 udelay(10); /* not RTOS friendly */
367
368 /* reset all endpoints ? */
369
370 /* reset internal status and wait for further instructions
371 no need to verify the port reset status (ESS does it) */
372
373 return 0;
374}
375
aa69a809
DL
376/******************************************************************************
377 * UTIL block
378 *****************************************************************************/
379/**
380 * _usb_addr: calculates endpoint address from direction & number
381 * @ep: endpoint
382 */
383static inline u8 _usb_addr(struct ci13xxx_ep *ep)
384{
385 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
386}
387
388/**
389 * _hardware_queue: configures a request at hardware level
390 * @gadget: gadget
391 * @mEp: endpoint
392 *
393 * This function returns an error code
394 */
395static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
396{
d3595d13 397 struct ci13xxx *udc = mEp->udc;
aa69a809 398 unsigned i;
0e6ca199
PK
399 int ret = 0;
400 unsigned length = mReq->req.length;
aa69a809 401
aa69a809
DL
402 /* don't queue twice */
403 if (mReq->req.status == -EALREADY)
404 return -EALREADY;
405
aa69a809 406 mReq->req.status = -EALREADY;
954aad8c 407 if (length && mReq->req.dma == DMA_ADDR_INVALID) {
aa69a809
DL
408 mReq->req.dma = \
409 dma_map_single(mEp->device, mReq->req.buf,
0e6ca199
PK
410 length, mEp->dir ? DMA_TO_DEVICE :
411 DMA_FROM_DEVICE);
aa69a809
DL
412 if (mReq->req.dma == 0)
413 return -ENOMEM;
414
415 mReq->map = 1;
416 }
417
0e6ca199
PK
418 if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
419 mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
420 &mReq->zdma);
421 if (mReq->zptr == NULL) {
422 if (mReq->map) {
423 dma_unmap_single(mEp->device, mReq->req.dma,
424 length, mEp->dir ? DMA_TO_DEVICE :
425 DMA_FROM_DEVICE);
954aad8c 426 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK
427 mReq->map = 0;
428 }
429 return -ENOMEM;
430 }
431 memset(mReq->zptr, 0, sizeof(*mReq->zptr));
432 mReq->zptr->next = TD_TERMINATE;
433 mReq->zptr->token = TD_STATUS_ACTIVE;
434 if (!mReq->req.no_interrupt)
435 mReq->zptr->token |= TD_IOC;
436 }
aa69a809
DL
437 /*
438 * TD configuration
439 * TODO - handle requests which spawns into several TDs
440 */
441 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
0e6ca199 442 mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
aa69a809 443 mReq->ptr->token &= TD_TOTAL_BYTES;
aa69a809 444 mReq->ptr->token |= TD_STATUS_ACTIVE;
0e6ca199
PK
445 if (mReq->zptr) {
446 mReq->ptr->next = mReq->zdma;
447 } else {
448 mReq->ptr->next = TD_TERMINATE;
449 if (!mReq->req.no_interrupt)
450 mReq->ptr->token |= TD_IOC;
451 }
aa69a809
DL
452 mReq->ptr->page[0] = mReq->req.dma;
453 for (i = 1; i < 5; i++)
454 mReq->ptr->page[i] =
0a313c4d 455 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
aa69a809 456
0e6ca199
PK
457 if (!list_empty(&mEp->qh.queue)) {
458 struct ci13xxx_req *mReqPrev;
459 int n = hw_ep_bit(mEp->num, mEp->dir);
460 int tmp_stat;
461
462 mReqPrev = list_entry(mEp->qh.queue.prev,
463 struct ci13xxx_req, queue);
464 if (mReqPrev->zptr)
465 mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
466 else
467 mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
468 wmb();
262c1632 469 if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
0e6ca199
PK
470 goto done;
471 do {
262c1632
AS
472 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
473 tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
474 } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
475 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
0e6ca199
PK
476 if (tmp_stat)
477 goto done;
478 }
479
480 /* QH configuration */
ca9cfea0
PK
481 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
482 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
0e6ca199 483 mEp->qh.ptr->cap |= QH_ZLT;
aa69a809
DL
484
485 wmb(); /* synchronize before ep prime */
486
d3595d13 487 ret = hw_ep_prime(udc, mEp->num, mEp->dir,
aa69a809 488 mEp->type == USB_ENDPOINT_XFER_CONTROL);
0e6ca199
PK
489done:
490 return ret;
aa69a809
DL
491}
492
493/**
494 * _hardware_dequeue: handles a request at hardware level
495 * @gadget: gadget
496 * @mEp: endpoint
497 *
498 * This function returns an error code
499 */
500static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
501{
aa69a809
DL
502 if (mReq->req.status != -EALREADY)
503 return -EINVAL;
504
0e6ca199
PK
505 if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
506 return -EBUSY;
507
508 if (mReq->zptr) {
509 if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
510 return -EBUSY;
511 dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
512 mReq->zptr = NULL;
513 }
aa69a809
DL
514
515 mReq->req.status = 0;
516
517 if (mReq->map) {
518 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
519 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 520 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL
521 mReq->map = 0;
522 }
523
524 mReq->req.status = mReq->ptr->token & TD_STATUS;
0e6ca199 525 if ((TD_STATUS_HALTED & mReq->req.status) != 0)
aa69a809
DL
526 mReq->req.status = -1;
527 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
528 mReq->req.status = -1;
529 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
530 mReq->req.status = -1;
531
532 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
533 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
534 mReq->req.actual = mReq->req.length - mReq->req.actual;
535 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
536
537 return mReq->req.actual;
538}
539
540/**
541 * _ep_nuke: dequeues all endpoint requests
542 * @mEp: endpoint
543 *
544 * This function returns an error code
545 * Caller must hold lock
546 */
547static int _ep_nuke(struct ci13xxx_ep *mEp)
548__releases(mEp->lock)
549__acquires(mEp->lock)
550{
aa69a809
DL
551 if (mEp == NULL)
552 return -EINVAL;
553
d3595d13 554 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809 555
ca9cfea0 556 while (!list_empty(&mEp->qh.queue)) {
aa69a809
DL
557
558 /* pop oldest request */
559 struct ci13xxx_req *mReq = \
ca9cfea0 560 list_entry(mEp->qh.queue.next,
aa69a809
DL
561 struct ci13xxx_req, queue);
562 list_del_init(&mReq->queue);
563 mReq->req.status = -ESHUTDOWN;
564
7c25a826 565 if (mReq->req.complete != NULL) {
aa69a809
DL
566 spin_unlock(mEp->lock);
567 mReq->req.complete(&mEp->ep, &mReq->req);
568 spin_lock(mEp->lock);
569 }
570 }
571 return 0;
572}
573
574/**
575 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
576 * @gadget: gadget
577 *
578 * This function returns an error code
aa69a809
DL
579 */
580static int _gadget_stop_activity(struct usb_gadget *gadget)
aa69a809
DL
581{
582 struct usb_ep *ep;
583 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
e2b61c1d 584 unsigned long flags;
aa69a809 585
aa69a809
DL
586 if (gadget == NULL)
587 return -EINVAL;
588
d3595d13 589 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK
590 udc->gadget.speed = USB_SPEED_UNKNOWN;
591 udc->remote_wakeup = 0;
592 udc->suspended = 0;
d3595d13 593 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d 594
aa69a809
DL
595 /* flush all endpoints */
596 gadget_for_each_ep(ep, gadget) {
597 usb_ep_fifo_flush(ep);
598 }
d36ade60
AS
599 usb_ep_fifo_flush(&udc->ep0out->ep);
600 usb_ep_fifo_flush(&udc->ep0in->ep);
aa69a809 601
1f339d84
AS
602 if (udc->driver)
603 udc->driver->disconnect(gadget);
aa69a809
DL
604
605 /* make sure to disable all endpoints */
606 gadget_for_each_ep(ep, gadget) {
607 usb_ep_disable(ep);
608 }
aa69a809 609
ca9cfea0 610 if (udc->status != NULL) {
d36ade60 611 usb_ep_free_request(&udc->ep0in->ep, udc->status);
ca9cfea0 612 udc->status = NULL;
aa69a809
DL
613 }
614
aa69a809
DL
615 return 0;
616}
617
618/******************************************************************************
619 * ISR block
620 *****************************************************************************/
621/**
622 * isr_reset_handler: USB reset interrupt handler
623 * @udc: UDC device
624 *
625 * This function resets USB engine after a bus reset occurred
626 */
627static void isr_reset_handler(struct ci13xxx *udc)
628__releases(udc->lock)
629__acquires(udc->lock)
630{
aa69a809
DL
631 int retval;
632
aa69a809
DL
633 dbg_event(0xFF, "BUS RST", 0);
634
d3595d13 635 spin_unlock(&udc->lock);
aa69a809
DL
636 retval = _gadget_stop_activity(&udc->gadget);
637 if (retval)
638 goto done;
639
d3595d13 640 retval = hw_usb_reset(udc);
aa69a809
DL
641 if (retval)
642 goto done;
643
d36ade60 644 udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
ac1aa6a2
A
645 if (udc->status == NULL)
646 retval = -ENOMEM;
ca9cfea0 647
d3595d13 648 spin_lock(&udc->lock);
aa69a809
DL
649
650 done:
651 if (retval)
0f089094 652 dev_err(udc->dev, "error: %i\n", retval);
aa69a809
DL
653}
654
655/**
656 * isr_get_status_complete: get_status request complete function
657 * @ep: endpoint
658 * @req: request handled
659 *
660 * Caller must release lock
661 */
662static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
663{
0f089094 664 if (ep == NULL || req == NULL)
aa69a809 665 return;
aa69a809
DL
666
667 kfree(req->buf);
668 usb_ep_free_request(ep, req);
669}
670
671/**
672 * isr_get_status_response: get_status request response
ca9cfea0 673 * @udc: udc struct
aa69a809
DL
674 * @setup: setup request packet
675 *
676 * This function returns an error code
677 */
ca9cfea0 678static int isr_get_status_response(struct ci13xxx *udc,
aa69a809
DL
679 struct usb_ctrlrequest *setup)
680__releases(mEp->lock)
681__acquires(mEp->lock)
682{
d36ade60 683 struct ci13xxx_ep *mEp = udc->ep0in;
aa69a809
DL
684 struct usb_request *req = NULL;
685 gfp_t gfp_flags = GFP_ATOMIC;
686 int dir, num, retval;
687
aa69a809
DL
688 if (mEp == NULL || setup == NULL)
689 return -EINVAL;
690
691 spin_unlock(mEp->lock);
692 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
693 spin_lock(mEp->lock);
694 if (req == NULL)
695 return -ENOMEM;
696
697 req->complete = isr_get_status_complete;
698 req->length = 2;
699 req->buf = kzalloc(req->length, gfp_flags);
700 if (req->buf == NULL) {
701 retval = -ENOMEM;
702 goto err_free_req;
703 }
704
705 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
e2b61c1d 706 /* Assume that device is bus powered for now. */
1f339d84 707 *(u16 *)req->buf = udc->remote_wakeup << 1;
aa69a809
DL
708 retval = 0;
709 } else if ((setup->bRequestType & USB_RECIP_MASK) \
710 == USB_RECIP_ENDPOINT) {
711 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
712 TX : RX;
713 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
d3595d13 714 *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
aa69a809
DL
715 }
716 /* else do nothing; reserved for future use */
717
718 spin_unlock(mEp->lock);
719 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
720 spin_lock(mEp->lock);
721 if (retval)
722 goto err_free_buf;
723
724 return 0;
725
726 err_free_buf:
727 kfree(req->buf);
728 err_free_req:
729 spin_unlock(mEp->lock);
730 usb_ep_free_request(&mEp->ep, req);
731 spin_lock(mEp->lock);
732 return retval;
733}
734
541cace8
PK
735/**
736 * isr_setup_status_complete: setup_status request complete function
737 * @ep: endpoint
738 * @req: request handled
739 *
740 * Caller must release lock. Put the port in test mode if test mode
741 * feature is selected.
742 */
743static void
744isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
745{
746 struct ci13xxx *udc = req->context;
747 unsigned long flags;
748
ef15e549
AS
749 if (udc->setaddr) {
750 hw_usb_set_address(udc, udc->address);
751 udc->setaddr = false;
752 }
753
d3595d13 754 spin_lock_irqsave(&udc->lock, flags);
541cace8 755 if (udc->test_mode)
d3595d13
AS
756 hw_port_test_set(udc, udc->test_mode);
757 spin_unlock_irqrestore(&udc->lock, flags);
541cace8
PK
758}
759
aa69a809
DL
760/**
761 * isr_setup_status_phase: queues the status phase of a setup transation
ca9cfea0 762 * @udc: udc struct
aa69a809
DL
763 *
764 * This function returns an error code
765 */
ca9cfea0 766static int isr_setup_status_phase(struct ci13xxx *udc)
aa69a809
DL
767__releases(mEp->lock)
768__acquires(mEp->lock)
769{
770 int retval;
ca9cfea0 771 struct ci13xxx_ep *mEp;
aa69a809 772
d36ade60 773 mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
541cace8
PK
774 udc->status->context = udc;
775 udc->status->complete = isr_setup_status_complete;
aa69a809
DL
776
777 spin_unlock(mEp->lock);
ca9cfea0 778 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
aa69a809
DL
779 spin_lock(mEp->lock);
780
781 return retval;
782}
783
784/**
785 * isr_tr_complete_low: transaction complete low level handler
786 * @mEp: endpoint
787 *
788 * This function returns an error code
789 * Caller must hold lock
790 */
791static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
792__releases(mEp->lock)
793__acquires(mEp->lock)
794{
0e6ca199 795 struct ci13xxx_req *mReq, *mReqTemp;
76cd9cfb 796 struct ci13xxx_ep *mEpTemp = mEp;
986b11b8 797 int uninitialized_var(retval);
aa69a809 798
ca9cfea0 799 if (list_empty(&mEp->qh.queue))
aa69a809
DL
800 return -EINVAL;
801
0e6ca199
PK
802 list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
803 queue) {
804 retval = _hardware_dequeue(mEp, mReq);
805 if (retval < 0)
806 break;
807 list_del_init(&mReq->queue);
808 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
809 if (mReq->req.complete != NULL) {
810 spin_unlock(mEp->lock);
76cd9cfb
PK
811 if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
812 mReq->req.length)
1f339d84 813 mEpTemp = mEp->udc->ep0in;
76cd9cfb 814 mReq->req.complete(&mEpTemp->ep, &mReq->req);
0e6ca199
PK
815 spin_lock(mEp->lock);
816 }
d9bb9c18
AL
817 }
818
ef907482 819 if (retval == -EBUSY)
0e6ca199
PK
820 retval = 0;
821 if (retval < 0)
822 dbg_event(_usb_addr(mEp), "DONE", retval);
aa69a809 823
aa69a809
DL
824 return retval;
825}
826
827/**
828 * isr_tr_complete_handler: transaction complete interrupt handler
829 * @udc: UDC descriptor
830 *
831 * This function handles traffic events
832 */
833static void isr_tr_complete_handler(struct ci13xxx *udc)
834__releases(udc->lock)
835__acquires(udc->lock)
836{
837 unsigned i;
541cace8 838 u8 tmode = 0;
aa69a809 839
d3595d13 840 for (i = 0; i < udc->hw_ep_max; i++) {
aa69a809 841 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
4c5212b7 842 int type, num, dir, err = -EINVAL;
aa69a809
DL
843 struct usb_ctrlrequest req;
844
31fb6014 845 if (mEp->ep.desc == NULL)
aa69a809
DL
846 continue; /* not configured */
847
d3595d13 848 if (hw_test_and_clear_complete(udc, i)) {
aa69a809
DL
849 err = isr_tr_complete_low(mEp);
850 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
851 if (err > 0) /* needs status phase */
ca9cfea0 852 err = isr_setup_status_phase(udc);
aa69a809
DL
853 if (err < 0) {
854 dbg_event(_usb_addr(mEp),
855 "ERROR", err);
d3595d13 856 spin_unlock(&udc->lock);
aa69a809 857 if (usb_ep_set_halt(&mEp->ep))
0f089094 858 dev_err(udc->dev,
0917ba84 859 "error: ep_set_halt\n");
d3595d13 860 spin_lock(&udc->lock);
aa69a809
DL
861 }
862 }
863 }
864
865 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
d3595d13 866 !hw_test_and_clear_setup_status(udc, i))
aa69a809
DL
867 continue;
868
869 if (i != 0) {
0f089094 870 dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
aa69a809
DL
871 continue;
872 }
873
ca9cfea0
PK
874 /*
875 * Flush data and handshake transactions of previous
876 * setup packet.
877 */
d36ade60
AS
878 _ep_nuke(udc->ep0out);
879 _ep_nuke(udc->ep0in);
ca9cfea0 880
aa69a809
DL
881 /* read_setup_packet */
882 do {
d3595d13 883 hw_test_and_set_setup_guard(udc);
ca9cfea0 884 memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
d3595d13 885 } while (!hw_test_and_clear_setup_guard(udc));
aa69a809
DL
886
887 type = req.bRequestType;
888
ca9cfea0 889 udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
aa69a809
DL
890
891 dbg_setup(_usb_addr(mEp), &req);
892
893 switch (req.bRequest) {
894 case USB_REQ_CLEAR_FEATURE:
e2b61c1d
PK
895 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
896 le16_to_cpu(req.wValue) ==
897 USB_ENDPOINT_HALT) {
898 if (req.wLength != 0)
899 break;
900 num = le16_to_cpu(req.wIndex);
4c5212b7 901 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 902 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 903 if (dir) /* TX */
d3595d13 904 num += udc->hw_ep_max/2;
e2b61c1d 905 if (!udc->ci13xxx_ep[num].wedge) {
d3595d13 906 spin_unlock(&udc->lock);
e2b61c1d
PK
907 err = usb_ep_clear_halt(
908 &udc->ci13xxx_ep[num].ep);
d3595d13 909 spin_lock(&udc->lock);
e2b61c1d
PK
910 if (err)
911 break;
912 }
913 err = isr_setup_status_phase(udc);
914 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
915 le16_to_cpu(req.wValue) ==
916 USB_DEVICE_REMOTE_WAKEUP) {
917 if (req.wLength != 0)
aa69a809 918 break;
e2b61c1d
PK
919 udc->remote_wakeup = 0;
920 err = isr_setup_status_phase(udc);
921 } else {
922 goto delegate;
aa69a809 923 }
aa69a809
DL
924 break;
925 case USB_REQ_GET_STATUS:
926 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
927 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
928 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
929 goto delegate;
930 if (le16_to_cpu(req.wLength) != 2 ||
931 le16_to_cpu(req.wValue) != 0)
932 break;
ca9cfea0 933 err = isr_get_status_response(udc, &req);
aa69a809
DL
934 break;
935 case USB_REQ_SET_ADDRESS:
936 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
937 goto delegate;
938 if (le16_to_cpu(req.wLength) != 0 ||
939 le16_to_cpu(req.wIndex) != 0)
940 break;
ef15e549
AS
941 udc->address = (u8)le16_to_cpu(req.wValue);
942 udc->setaddr = true;
ca9cfea0 943 err = isr_setup_status_phase(udc);
aa69a809
DL
944 break;
945 case USB_REQ_SET_FEATURE:
e2b61c1d
PK
946 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
947 le16_to_cpu(req.wValue) ==
948 USB_ENDPOINT_HALT) {
949 if (req.wLength != 0)
950 break;
951 num = le16_to_cpu(req.wIndex);
4c5212b7 952 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 953 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 954 if (dir) /* TX */
d3595d13 955 num += udc->hw_ep_max/2;
aa69a809 956
d3595d13 957 spin_unlock(&udc->lock);
e2b61c1d 958 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
d3595d13 959 spin_lock(&udc->lock);
e2b61c1d 960 if (!err)
541cace8
PK
961 isr_setup_status_phase(udc);
962 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
e2b61c1d
PK
963 if (req.wLength != 0)
964 break;
541cace8
PK
965 switch (le16_to_cpu(req.wValue)) {
966 case USB_DEVICE_REMOTE_WAKEUP:
967 udc->remote_wakeup = 1;
968 err = isr_setup_status_phase(udc);
969 break;
970 case USB_DEVICE_TEST_MODE:
971 tmode = le16_to_cpu(req.wIndex) >> 8;
972 switch (tmode) {
973 case TEST_J:
974 case TEST_K:
975 case TEST_SE0_NAK:
976 case TEST_PACKET:
977 case TEST_FORCE_EN:
978 udc->test_mode = tmode;
979 err = isr_setup_status_phase(
980 udc);
981 break;
982 default:
983 break;
984 }
985 default:
986 goto delegate;
987 }
e2b61c1d
PK
988 } else {
989 goto delegate;
990 }
aa69a809
DL
991 break;
992 default:
993delegate:
994 if (req.wLength == 0) /* no data phase */
ca9cfea0 995 udc->ep0_dir = TX;
aa69a809 996
d3595d13 997 spin_unlock(&udc->lock);
aa69a809 998 err = udc->driver->setup(&udc->gadget, &req);
d3595d13 999 spin_lock(&udc->lock);
aa69a809
DL
1000 break;
1001 }
1002
1003 if (err < 0) {
1004 dbg_event(_usb_addr(mEp), "ERROR", err);
1005
d3595d13 1006 spin_unlock(&udc->lock);
aa69a809 1007 if (usb_ep_set_halt(&mEp->ep))
0f089094 1008 dev_err(udc->dev, "error: ep_set_halt\n");
d3595d13 1009 spin_lock(&udc->lock);
aa69a809
DL
1010 }
1011 }
1012}
1013
1014/******************************************************************************
1015 * ENDPT block
1016 *****************************************************************************/
1017/**
1018 * ep_enable: configure endpoint, making it usable
1019 *
1020 * Check usb_ep_enable() at "usb_gadget.h" for details
1021 */
1022static int ep_enable(struct usb_ep *ep,
1023 const struct usb_endpoint_descriptor *desc)
1024{
1025 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
ca9cfea0 1026 int retval = 0;
aa69a809
DL
1027 unsigned long flags;
1028
aa69a809
DL
1029 if (ep == NULL || desc == NULL)
1030 return -EINVAL;
1031
1032 spin_lock_irqsave(mEp->lock, flags);
1033
1034 /* only internal SW should enable ctrl endpts */
1035
31fb6014 1036 mEp->ep.desc = desc;
aa69a809 1037
ca9cfea0 1038 if (!list_empty(&mEp->qh.queue))
0f089094 1039 dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
aa69a809 1040
15739bb5
MK
1041 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
1042 mEp->num = usb_endpoint_num(desc);
1043 mEp->type = usb_endpoint_type(desc);
aa69a809 1044
29cc8897 1045 mEp->ep.maxpacket = usb_endpoint_maxp(desc);
aa69a809 1046
ca9cfea0 1047 dbg_event(_usb_addr(mEp), "ENABLE", 0);
aa69a809 1048
ca9cfea0 1049 mEp->qh.ptr->cap = 0;
aa69a809 1050
ca9cfea0
PK
1051 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1052 mEp->qh.ptr->cap |= QH_IOS;
1053 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
1054 mEp->qh.ptr->cap &= ~QH_MULT;
1055 else
1056 mEp->qh.ptr->cap &= ~QH_ZLT;
aa69a809 1057
ca9cfea0
PK
1058 mEp->qh.ptr->cap |=
1059 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
1060 mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
aa69a809 1061
ac1aa6a2
A
1062 /*
1063 * Enable endpoints in the HW other than ep0 as ep0
1064 * is always enabled
1065 */
1066 if (mEp->num)
d3595d13 1067 retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
aa69a809
DL
1068
1069 spin_unlock_irqrestore(mEp->lock, flags);
1070 return retval;
1071}
1072
1073/**
1074 * ep_disable: endpoint is no longer usable
1075 *
1076 * Check usb_ep_disable() at "usb_gadget.h" for details
1077 */
1078static int ep_disable(struct usb_ep *ep)
1079{
1080 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1081 int direction, retval = 0;
1082 unsigned long flags;
1083
aa69a809
DL
1084 if (ep == NULL)
1085 return -EINVAL;
31fb6014 1086 else if (mEp->ep.desc == NULL)
aa69a809
DL
1087 return -EBUSY;
1088
1089 spin_lock_irqsave(mEp->lock, flags);
1090
1091 /* only internal SW should disable ctrl endpts */
1092
1093 direction = mEp->dir;
1094 do {
1095 dbg_event(_usb_addr(mEp), "DISABLE", 0);
1096
1097 retval |= _ep_nuke(mEp);
d3595d13 1098 retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1099
1100 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1101 mEp->dir = (mEp->dir == TX) ? RX : TX;
1102
1103 } while (mEp->dir != direction);
1104
f9c56cdd 1105 mEp->ep.desc = NULL;
aa69a809
DL
1106
1107 spin_unlock_irqrestore(mEp->lock, flags);
1108 return retval;
1109}
1110
1111/**
1112 * ep_alloc_request: allocate a request object to use with this endpoint
1113 *
1114 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
1115 */
1116static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1117{
1118 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1119 struct ci13xxx_req *mReq = NULL;
aa69a809 1120
0f089094 1121 if (ep == NULL)
aa69a809 1122 return NULL;
aa69a809 1123
aa69a809
DL
1124 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
1125 if (mReq != NULL) {
1126 INIT_LIST_HEAD(&mReq->queue);
954aad8c 1127 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL
1128
1129 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
1130 &mReq->dma);
1131 if (mReq->ptr == NULL) {
1132 kfree(mReq);
1133 mReq = NULL;
1134 }
1135 }
1136
1137 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
1138
aa69a809
DL
1139 return (mReq == NULL) ? NULL : &mReq->req;
1140}
1141
1142/**
1143 * ep_free_request: frees a request object
1144 *
1145 * Check usb_ep_free_request() at "usb_gadget.h" for details
1146 */
1147static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
1148{
1149 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1150 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1151 unsigned long flags;
1152
aa69a809 1153 if (ep == NULL || req == NULL) {
aa69a809
DL
1154 return;
1155 } else if (!list_empty(&mReq->queue)) {
0f089094 1156 dev_err(mEp->udc->dev, "freeing queued request\n");
aa69a809
DL
1157 return;
1158 }
1159
1160 spin_lock_irqsave(mEp->lock, flags);
1161
1162 if (mReq->ptr)
1163 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
1164 kfree(mReq);
1165
1166 dbg_event(_usb_addr(mEp), "FREE", 0);
1167
1168 spin_unlock_irqrestore(mEp->lock, flags);
1169}
1170
1171/**
1172 * ep_queue: queues (submits) an I/O request to an endpoint
1173 *
1174 * Check usb_ep_queue()* at usb_gadget.h" for details
1175 */
1176static int ep_queue(struct usb_ep *ep, struct usb_request *req,
1177 gfp_t __maybe_unused gfp_flags)
1178{
1179 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1180 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1f339d84 1181 struct ci13xxx *udc = mEp->udc;
aa69a809
DL
1182 int retval = 0;
1183 unsigned long flags;
1184
31fb6014 1185 if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1186 return -EINVAL;
1187
1188 spin_lock_irqsave(mEp->lock, flags);
1189
76cd9cfb
PK
1190 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1191 if (req->length)
1f339d84
AS
1192 mEp = (udc->ep0_dir == RX) ?
1193 udc->ep0out : udc->ep0in;
76cd9cfb
PK
1194 if (!list_empty(&mEp->qh.queue)) {
1195 _ep_nuke(mEp);
1196 retval = -EOVERFLOW;
0f089094
AS
1197 dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
1198 _usb_addr(mEp));
76cd9cfb 1199 }
aa69a809
DL
1200 }
1201
1202 /* first nuke then test link, e.g. previous status has not sent */
1203 if (!list_empty(&mReq->queue)) {
1204 retval = -EBUSY;
0f089094 1205 dev_err(mEp->udc->dev, "request already in queue\n");
aa69a809
DL
1206 goto done;
1207 }
1208
1155a7b8
AS
1209 if (req->length > 4 * CI13XXX_PAGE_SIZE) {
1210 req->length = 4 * CI13XXX_PAGE_SIZE;
aa69a809 1211 retval = -EMSGSIZE;
0f089094 1212 dev_warn(mEp->udc->dev, "request length truncated\n");
aa69a809
DL
1213 }
1214
1215 dbg_queue(_usb_addr(mEp), req, retval);
1216
1217 /* push request */
1218 mReq->req.status = -EINPROGRESS;
1219 mReq->req.actual = 0;
aa69a809 1220
0e6ca199 1221 retval = _hardware_enqueue(mEp, mReq);
d9bb9c18
AL
1222
1223 if (retval == -EALREADY) {
aa69a809
DL
1224 dbg_event(_usb_addr(mEp), "QUEUE", retval);
1225 retval = 0;
1226 }
0e6ca199
PK
1227 if (!retval)
1228 list_add_tail(&mReq->queue, &mEp->qh.queue);
aa69a809
DL
1229
1230 done:
1231 spin_unlock_irqrestore(mEp->lock, flags);
1232 return retval;
1233}
1234
1235/**
1236 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
1237 *
1238 * Check usb_ep_dequeue() at "usb_gadget.h" for details
1239 */
1240static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
1241{
1242 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1243 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1244 unsigned long flags;
1245
0e6ca199 1246 if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
31fb6014 1247 mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
0e6ca199 1248 list_empty(&mEp->qh.queue))
aa69a809
DL
1249 return -EINVAL;
1250
1251 spin_lock_irqsave(mEp->lock, flags);
1252
1253 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
1254
d3595d13 1255 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1256
1257 /* pop request */
1258 list_del_init(&mReq->queue);
0e6ca199
PK
1259 if (mReq->map) {
1260 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1261 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 1262 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK
1263 mReq->map = 0;
1264 }
aa69a809
DL
1265 req->status = -ECONNRESET;
1266
7c25a826 1267 if (mReq->req.complete != NULL) {
aa69a809
DL
1268 spin_unlock(mEp->lock);
1269 mReq->req.complete(&mEp->ep, &mReq->req);
1270 spin_lock(mEp->lock);
1271 }
1272
1273 spin_unlock_irqrestore(mEp->lock, flags);
1274 return 0;
1275}
1276
1277/**
1278 * ep_set_halt: sets the endpoint halt feature
1279 *
1280 * Check usb_ep_set_halt() at "usb_gadget.h" for details
1281 */
1282static int ep_set_halt(struct usb_ep *ep, int value)
1283{
1284 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1285 int direction, retval = 0;
1286 unsigned long flags;
1287
31fb6014 1288 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1289 return -EINVAL;
1290
1291 spin_lock_irqsave(mEp->lock, flags);
1292
1293#ifndef STALL_IN
1294 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
1295 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
ca9cfea0 1296 !list_empty(&mEp->qh.queue)) {
aa69a809
DL
1297 spin_unlock_irqrestore(mEp->lock, flags);
1298 return -EAGAIN;
1299 }
1300#endif
1301
1302 direction = mEp->dir;
1303 do {
1304 dbg_event(_usb_addr(mEp), "HALT", value);
d3595d13 1305 retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
aa69a809
DL
1306
1307 if (!value)
1308 mEp->wedge = 0;
1309
1310 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1311 mEp->dir = (mEp->dir == TX) ? RX : TX;
1312
1313 } while (mEp->dir != direction);
1314
1315 spin_unlock_irqrestore(mEp->lock, flags);
1316 return retval;
1317}
1318
1319/**
1320 * ep_set_wedge: sets the halt feature and ignores clear requests
1321 *
1322 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
1323 */
1324static int ep_set_wedge(struct usb_ep *ep)
1325{
1326 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1327 unsigned long flags;
1328
31fb6014 1329 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1330 return -EINVAL;
1331
1332 spin_lock_irqsave(mEp->lock, flags);
1333
1334 dbg_event(_usb_addr(mEp), "WEDGE", 0);
1335 mEp->wedge = 1;
1336
1337 spin_unlock_irqrestore(mEp->lock, flags);
1338
1339 return usb_ep_set_halt(ep);
1340}
1341
1342/**
1343 * ep_fifo_flush: flushes contents of a fifo
1344 *
1345 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
1346 */
1347static void ep_fifo_flush(struct usb_ep *ep)
1348{
1349 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1350 unsigned long flags;
1351
aa69a809 1352 if (ep == NULL) {
0f089094 1353 dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
aa69a809
DL
1354 return;
1355 }
1356
1357 spin_lock_irqsave(mEp->lock, flags);
1358
1359 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
d3595d13 1360 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1361
1362 spin_unlock_irqrestore(mEp->lock, flags);
1363}
1364
1365/**
1366 * Endpoint-specific part of the API to the USB controller hardware
1367 * Check "usb_gadget.h" for details
1368 */
1369static const struct usb_ep_ops usb_ep_ops = {
1370 .enable = ep_enable,
1371 .disable = ep_disable,
1372 .alloc_request = ep_alloc_request,
1373 .free_request = ep_free_request,
1374 .queue = ep_queue,
1375 .dequeue = ep_dequeue,
1376 .set_halt = ep_set_halt,
1377 .set_wedge = ep_set_wedge,
1378 .fifo_flush = ep_fifo_flush,
1379};
1380
1381/******************************************************************************
1382 * GADGET block
1383 *****************************************************************************/
f01ef574
PK
1384static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
1385{
1386 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1387 unsigned long flags;
1388 int gadget_ready = 0;
1389
1390 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
1391 return -EOPNOTSUPP;
1392
d3595d13 1393 spin_lock_irqsave(&udc->lock, flags);
f01ef574
PK
1394 udc->vbus_active = is_active;
1395 if (udc->driver)
1396 gadget_ready = 1;
d3595d13 1397 spin_unlock_irqrestore(&udc->lock, flags);
f01ef574
PK
1398
1399 if (gadget_ready) {
1400 if (is_active) {
c036019e 1401 pm_runtime_get_sync(&_gadget->dev);
f01ef574 1402 hw_device_reset(udc);
d3595d13 1403 hw_device_state(udc, udc->ep0out->qh.dma);
f01ef574 1404 } else {
d3595d13 1405 hw_device_state(udc, 0);
f01ef574
PK
1406 if (udc->udc_driver->notify_event)
1407 udc->udc_driver->notify_event(udc,
1408 CI13XXX_CONTROLLER_STOPPED_EVENT);
1409 _gadget_stop_activity(&udc->gadget);
c036019e 1410 pm_runtime_put_sync(&_gadget->dev);
f01ef574
PK
1411 }
1412 }
1413
1414 return 0;
1415}
1416
e2b61c1d
PK
1417static int ci13xxx_wakeup(struct usb_gadget *_gadget)
1418{
1419 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1420 unsigned long flags;
1421 int ret = 0;
1422
d3595d13 1423 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK
1424 if (!udc->remote_wakeup) {
1425 ret = -EOPNOTSUPP;
e2b61c1d
PK
1426 goto out;
1427 }
262c1632 1428 if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
e2b61c1d 1429 ret = -EINVAL;
e2b61c1d
PK
1430 goto out;
1431 }
262c1632 1432 hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
e2b61c1d 1433out:
d3595d13 1434 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d
PK
1435 return ret;
1436}
1437
d860852e
PK
1438static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1439{
1440 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1441
1442 if (udc->transceiver)
b96d3b08 1443 return usb_phy_set_power(udc->transceiver, mA);
d860852e
PK
1444 return -ENOTSUPP;
1445}
1446
1f339d84
AS
1447static int ci13xxx_start(struct usb_gadget *gadget,
1448 struct usb_gadget_driver *driver);
1449static int ci13xxx_stop(struct usb_gadget *gadget,
1450 struct usb_gadget_driver *driver);
aa69a809
DL
1451/**
1452 * Device operations part of the API to the USB controller hardware,
1453 * which don't involve endpoints (or i/o)
1454 * Check "usb_gadget.h" for details
1455 */
f01ef574
PK
1456static const struct usb_gadget_ops usb_gadget_ops = {
1457 .vbus_session = ci13xxx_vbus_session,
e2b61c1d 1458 .wakeup = ci13xxx_wakeup,
d860852e 1459 .vbus_draw = ci13xxx_vbus_draw,
1f339d84
AS
1460 .udc_start = ci13xxx_start,
1461 .udc_stop = ci13xxx_stop,
f01ef574 1462};
aa69a809 1463
790c2d52 1464static int init_eps(struct ci13xxx *udc)
aa69a809 1465{
790c2d52 1466 int retval = 0, i, j;
aa69a809 1467
790c2d52 1468 for (i = 0; i < udc->hw_ep_max/2; i++)
ca9cfea0 1469 for (j = RX; j <= TX; j++) {
d3595d13 1470 int k = i + j * udc->hw_ep_max/2;
ca9cfea0 1471 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
aa69a809 1472
ca9cfea0
PK
1473 scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
1474 (j == TX) ? "in" : "out");
aa69a809 1475
d3595d13
AS
1476 mEp->udc = udc;
1477 mEp->lock = &udc->lock;
ca9cfea0
PK
1478 mEp->device = &udc->gadget.dev;
1479 mEp->td_pool = udc->td_pool;
aa69a809 1480
ca9cfea0
PK
1481 mEp->ep.name = mEp->name;
1482 mEp->ep.ops = &usb_ep_ops;
1483 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
aa69a809 1484
ca9cfea0 1485 INIT_LIST_HEAD(&mEp->qh.queue);
ca9cfea0 1486 mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
790c2d52 1487 &mEp->qh.dma);
ca9cfea0 1488 if (mEp->qh.ptr == NULL)
aa69a809
DL
1489 retval = -ENOMEM;
1490 else
ca9cfea0
PK
1491 memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
1492
d36ade60
AS
1493 /*
1494 * set up shorthands for ep0 out and in endpoints,
1495 * don't add to gadget's ep_list
1496 */
1497 if (i == 0) {
1498 if (j == RX)
1499 udc->ep0out = mEp;
1500 else
1501 udc->ep0in = mEp;
1502
ca9cfea0 1503 continue;
d36ade60 1504 }
ca9cfea0 1505
aa69a809 1506 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
ca9cfea0 1507 }
790c2d52
AS
1508
1509 return retval;
1510}
1511
1512/**
1513 * ci13xxx_start: register a gadget driver
1f339d84 1514 * @gadget: our gadget
790c2d52 1515 * @driver: the driver being registered
790c2d52 1516 *
790c2d52
AS
1517 * Interrupts are enabled here.
1518 */
1f339d84
AS
1519static int ci13xxx_start(struct usb_gadget *gadget,
1520 struct usb_gadget_driver *driver)
790c2d52 1521{
1f339d84 1522 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
790c2d52 1523 unsigned long flags;
790c2d52
AS
1524 int retval = -ENOMEM;
1525
1f339d84 1526 if (driver->disconnect == NULL)
790c2d52 1527 return -EINVAL;
790c2d52 1528
790c2d52 1529
d36ade60
AS
1530 udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
1531 retval = usb_ep_enable(&udc->ep0out->ep);
ac1aa6a2
A
1532 if (retval)
1533 return retval;
877c1f54 1534
d36ade60
AS
1535 udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
1536 retval = usb_ep_enable(&udc->ep0in->ep);
ac1aa6a2
A
1537 if (retval)
1538 return retval;
d3595d13 1539 spin_lock_irqsave(&udc->lock, flags);
aa69a809 1540
49d3df53 1541 udc->driver = driver;
c036019e 1542 pm_runtime_get_sync(&udc->gadget.dev);
f01ef574
PK
1543 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
1544 if (udc->vbus_active) {
1545 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
1546 hw_device_reset(udc);
1547 } else {
c036019e 1548 pm_runtime_put_sync(&udc->gadget.dev);
f01ef574
PK
1549 goto done;
1550 }
1551 }
1552
d3595d13 1553 retval = hw_device_state(udc, udc->ep0out->qh.dma);
c036019e
PK
1554 if (retval)
1555 pm_runtime_put_sync(&udc->gadget.dev);
aa69a809
DL
1556
1557 done:
d3595d13 1558 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL
1559 return retval;
1560}
aa69a809
DL
1561
1562/**
0f91349b 1563 * ci13xxx_stop: unregister a gadget driver
aa69a809 1564 */
1f339d84
AS
1565static int ci13xxx_stop(struct usb_gadget *gadget,
1566 struct usb_gadget_driver *driver)
aa69a809 1567{
1f339d84
AS
1568 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1569 unsigned long flags;
aa69a809 1570
d3595d13 1571 spin_lock_irqsave(&udc->lock, flags);
aa69a809 1572
f01ef574
PK
1573 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
1574 udc->vbus_active) {
d3595d13 1575 hw_device_state(udc, 0);
f01ef574
PK
1576 if (udc->udc_driver->notify_event)
1577 udc->udc_driver->notify_event(udc,
1578 CI13XXX_CONTROLLER_STOPPED_EVENT);
1f339d84 1579 udc->driver = NULL;
d3595d13 1580 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 1581 _gadget_stop_activity(&udc->gadget);
d3595d13 1582 spin_lock_irqsave(&udc->lock, flags);
c036019e 1583 pm_runtime_put(&udc->gadget.dev);
f01ef574 1584 }
aa69a809 1585
d3595d13 1586 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 1587
aa69a809
DL
1588 return 0;
1589}
aa69a809
DL
1590
1591/******************************************************************************
1592 * BUS block
1593 *****************************************************************************/
1594/**
5f36e231 1595 * udc_irq: udc interrupt handler
aa69a809
DL
1596 *
1597 * This function returns IRQ_HANDLED if the IRQ has been handled
1598 * It locks access to registers
1599 */
5f36e231 1600static irqreturn_t udc_irq(struct ci13xxx *udc)
aa69a809 1601{
aa69a809
DL
1602 irqreturn_t retval;
1603 u32 intr;
1604
f639554b 1605 if (udc == NULL)
aa69a809 1606 return IRQ_HANDLED;
aa69a809 1607
d3595d13 1608 spin_lock(&udc->lock);
f01ef574
PK
1609
1610 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
262c1632
AS
1611 if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
1612 USBMODE_CM_DEVICE) {
d3595d13 1613 spin_unlock(&udc->lock);
f01ef574
PK
1614 return IRQ_NONE;
1615 }
1616 }
d3595d13 1617 intr = hw_test_and_clear_intr_active(udc);
e443b333 1618 dbg_interrupt(intr);
aa69a809 1619
e443b333 1620 if (intr) {
aa69a809 1621 /* order defines priority - do NOT change it */
e443b333 1622 if (USBi_URI & intr)
aa69a809 1623 isr_reset_handler(udc);
e443b333 1624
aa69a809 1625 if (USBi_PCI & intr) {
d3595d13 1626 udc->gadget.speed = hw_port_is_high_speed(udc) ?
aa69a809 1627 USB_SPEED_HIGH : USB_SPEED_FULL;
7bb4fdc6 1628 if (udc->suspended && udc->driver->resume) {
d3595d13 1629 spin_unlock(&udc->lock);
e2b61c1d 1630 udc->driver->resume(&udc->gadget);
d3595d13 1631 spin_lock(&udc->lock);
e2b61c1d
PK
1632 udc->suspended = 0;
1633 }
aa69a809 1634 }
e443b333
AS
1635
1636 if (USBi_UI & intr)
aa69a809 1637 isr_tr_complete_handler(udc);
e443b333 1638
e2b61c1d 1639 if (USBi_SLI & intr) {
7bb4fdc6
MKB
1640 if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
1641 udc->driver->suspend) {
e2b61c1d 1642 udc->suspended = 1;
d3595d13 1643 spin_unlock(&udc->lock);
e2b61c1d 1644 udc->driver->suspend(&udc->gadget);
d3595d13 1645 spin_lock(&udc->lock);
e2b61c1d 1646 }
e2b61c1d 1647 }
aa69a809
DL
1648 retval = IRQ_HANDLED;
1649 } else {
aa69a809
DL
1650 retval = IRQ_NONE;
1651 }
d3595d13 1652 spin_unlock(&udc->lock);
aa69a809
DL
1653
1654 return retval;
1655}
1656
1657/**
1658 * udc_release: driver release function
1659 * @dev: device
1660 *
1661 * Currently does nothing
1662 */
1663static void udc_release(struct device *dev)
1664{
aa69a809
DL
1665}
1666
1667/**
5f36e231
AS
1668 * udc_start: initialize gadget role
1669 * @udc: chipidea controller
aa69a809 1670 */
5f36e231 1671static int udc_start(struct ci13xxx *udc)
aa69a809 1672{
5f36e231 1673 struct device *dev = udc->dev;
aa69a809
DL
1674 int retval = 0;
1675
5f36e231 1676 if (!udc)
aa69a809
DL
1677 return -EINVAL;
1678
d3595d13 1679 spin_lock_init(&udc->lock);
aa69a809 1680
f01ef574 1681 udc->gadget.ops = &usb_gadget_ops;
aa69a809 1682 udc->gadget.speed = USB_SPEED_UNKNOWN;
d327ab5b 1683 udc->gadget.max_speed = USB_SPEED_HIGH;
aa69a809 1684 udc->gadget.is_otg = 0;
5f36e231 1685 udc->gadget.name = udc->udc_driver->name;
aa69a809
DL
1686
1687 INIT_LIST_HEAD(&udc->gadget.ep_list);
aa69a809 1688
5df58524 1689 dev_set_name(&udc->gadget.dev, "gadget");
aa69a809 1690 udc->gadget.dev.dma_mask = dev->dma_mask;
61948ee4 1691 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
aa69a809
DL
1692 udc->gadget.dev.parent = dev;
1693 udc->gadget.dev.release = udc_release;
1694
790c2d52
AS
1695 /* alloc resources */
1696 udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
1697 sizeof(struct ci13xxx_qh),
1698 64, CI13XXX_PAGE_SIZE);
5f36e231
AS
1699 if (udc->qh_pool == NULL)
1700 return -ENOMEM;
790c2d52
AS
1701
1702 udc->td_pool = dma_pool_create("ci13xxx_td", dev,
1703 sizeof(struct ci13xxx_td),
1704 64, CI13XXX_PAGE_SIZE);
1705 if (udc->td_pool == NULL) {
1706 retval = -ENOMEM;
1707 goto free_qh_pool;
1708 }
1709
790c2d52
AS
1710 retval = init_eps(udc);
1711 if (retval)
1712 goto free_pools;
1713
1714 udc->gadget.ep0 = &udc->ep0in->ep;
f01ef574 1715
b96d3b08 1716 udc->transceiver = usb_get_transceiver();
f01ef574
PK
1717
1718 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
1719 if (udc->transceiver == NULL) {
1720 retval = -ENODEV;
790c2d52 1721 goto free_pools;
f01ef574
PK
1722 }
1723 }
1724
1725 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
1726 retval = hw_device_reset(udc);
1727 if (retval)
1728 goto put_transceiver;
1729 }
1730
aa69a809 1731 retval = device_register(&udc->gadget.dev);
f01ef574
PK
1732 if (retval) {
1733 put_device(&udc->gadget.dev);
1734 goto put_transceiver;
1735 }
aa69a809 1736
aa69a809 1737 retval = dbg_create_files(&udc->gadget.dev);
f01ef574
PK
1738 if (retval)
1739 goto unreg_device;
1740
1741 if (udc->transceiver) {
6e13c650
HK
1742 retval = otg_set_peripheral(udc->transceiver->otg,
1743 &udc->gadget);
f01ef574
PK
1744 if (retval)
1745 goto remove_dbg;
aa69a809 1746 }
0f91349b
SAS
1747
1748 retval = usb_add_gadget_udc(dev, &udc->gadget);
1749 if (retval)
1750 goto remove_trans;
1751
c036019e
PK
1752 pm_runtime_no_callbacks(&udc->gadget.dev);
1753 pm_runtime_enable(&udc->gadget.dev);
aa69a809 1754
aa69a809
DL
1755 return retval;
1756
0f91349b
SAS
1757remove_trans:
1758 if (udc->transceiver) {
6e13c650 1759 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
b96d3b08 1760 usb_put_transceiver(udc->transceiver);
0f91349b
SAS
1761 }
1762
0917ba84 1763 dev_err(dev, "error = %i\n", retval);
f01ef574 1764remove_dbg:
f01ef574 1765 dbg_remove_files(&udc->gadget.dev);
f01ef574
PK
1766unreg_device:
1767 device_unregister(&udc->gadget.dev);
1768put_transceiver:
1769 if (udc->transceiver)
b96d3b08 1770 usb_put_transceiver(udc->transceiver);
790c2d52
AS
1771free_pools:
1772 dma_pool_destroy(udc->td_pool);
1773free_qh_pool:
1774 dma_pool_destroy(udc->qh_pool);
aa69a809
DL
1775 return retval;
1776}
1777
1778/**
1779 * udc_remove: parent remove must call this to remove UDC
1780 *
1781 * No interrupts active, the IRQ has been released
1782 */
5f36e231 1783static void udc_stop(struct ci13xxx *udc)
aa69a809 1784{
790c2d52 1785 int i;
aa69a809 1786
0f089094 1787 if (udc == NULL)
aa69a809 1788 return;
0f089094 1789
0f91349b 1790 usb_del_gadget_udc(&udc->gadget);
aa69a809 1791
790c2d52
AS
1792 for (i = 0; i < udc->hw_ep_max; i++) {
1793 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1794
1795 dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
1796 }
1797
1798 dma_pool_destroy(udc->td_pool);
1799 dma_pool_destroy(udc->qh_pool);
1800
f01ef574 1801 if (udc->transceiver) {
5f36e231 1802 otg_set_peripheral(udc->transceiver->otg, NULL);
b96d3b08 1803 usb_put_transceiver(udc->transceiver);
f01ef574 1804 }
aa69a809 1805 dbg_remove_files(&udc->gadget.dev);
aa69a809 1806 device_unregister(&udc->gadget.dev);
5f36e231
AS
1807 /* my kobject is dynamic, I swear! */
1808 memset(&udc->gadget, 0, sizeof(udc->gadget));
1809}
1810
1811/**
1812 * ci_hdrc_gadget_init - initialize device related bits
1813 * ci: the controller
1814 *
1815 * This function enables the gadget role, if the device is "device capable".
1816 */
1817int ci_hdrc_gadget_init(struct ci13xxx *ci)
1818{
1819 struct ci_role_driver *rdrv;
1820
1821 if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
1822 return -ENXIO;
1823
1824 rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
1825 if (!rdrv)
1826 return -ENOMEM;
1827
1828 rdrv->start = udc_start;
1829 rdrv->stop = udc_stop;
1830 rdrv->irq = udc_irq;
1831 rdrv->name = "gadget";
1832 ci->roles[CI_ROLE_GADGET] = rdrv;
aa69a809 1833
5f36e231 1834 return 0;
aa69a809 1835}