]>
Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
8b9bc460 | 2 | /** |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
50 | static inline void __orr32(void __iomem *ptr, u32 val) | |
51 | { | |
95c8bc36 | 52 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
53 | } |
54 | ||
55 | static inline void __bic32(void __iomem *ptr, u32 val) | |
56 | { | |
95c8bc36 | 57 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
110 | * @increment: The value to increment by | |
111 | * | |
112 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
113 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
114 | */ | |
115 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
116 | { | |
117 | hs_ep->target_frame += hs_ep->interval; | |
118 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
119 | hs_ep->frame_overrun = 1; | |
120 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
121 | } else { | |
122 | hs_ep->frame_overrun = 0; | |
123 | } | |
124 | } | |
125 | ||
5b7d70c6 | 126 | /** |
1f91b4cc | 127 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
128 | * @hsotg: The device state |
129 | * @ints: A bitmask of the interrupts to enable | |
130 | */ | |
1f91b4cc | 131 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 132 | { |
95c8bc36 | 133 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
134 | u32 new_gsintmsk; |
135 | ||
136 | new_gsintmsk = gsintmsk | ints; | |
137 | ||
138 | if (new_gsintmsk != gsintmsk) { | |
139 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 140 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
141 | } |
142 | } | |
143 | ||
144 | /** | |
1f91b4cc | 145 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
146 | * @hsotg: The device state |
147 | * @ints: A bitmask of the interrupts to enable | |
148 | */ | |
1f91b4cc | 149 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 150 | { |
95c8bc36 | 151 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
152 | u32 new_gsintmsk; |
153 | ||
154 | new_gsintmsk = gsintmsk & ~ints; | |
155 | ||
156 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 157 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
158 | } |
159 | ||
160 | /** | |
1f91b4cc | 161 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
162 | * @hsotg: The device state |
163 | * @ep: The endpoint index | |
164 | * @dir_in: True if direction is in. | |
165 | * @en: The enable value, true to enable | |
166 | * | |
167 | * Set or clear the mask for an individual endpoint's interrupt | |
168 | * request. | |
169 | */ | |
1f91b4cc | 170 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 171 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
172 | unsigned int en) |
173 | { | |
174 | unsigned long flags; | |
175 | u32 bit = 1 << ep; | |
176 | u32 daint; | |
177 | ||
178 | if (!dir_in) | |
179 | bit <<= 16; | |
180 | ||
181 | local_irq_save(flags); | |
95c8bc36 | 182 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
183 | if (en) |
184 | daint |= bit; | |
185 | else | |
186 | daint &= ~bit; | |
95c8bc36 | 187 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
188 | local_irq_restore(flags); |
189 | } | |
190 | ||
c138ecfa SA |
191 | /** |
192 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
193 | */ | |
194 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
195 | { | |
196 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
197 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 198 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
199 | else |
200 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
201 | return hsotg->hw_params.num_dev_perio_in_ep; | |
202 | } | |
203 | ||
c138ecfa SA |
204 | /** |
205 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
206 | * device mode TX FIFOs | |
207 | */ | |
208 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
209 | { | |
c138ecfa SA |
210 | int addr; |
211 | int tx_addr_max; | |
212 | u32 np_tx_fifo_size; | |
213 | ||
214 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
215 | hsotg->params.g_np_tx_fifo_size); | |
216 | ||
217 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 218 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
219 | |
220 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
221 | if (tx_addr_max <= addr) | |
222 | return 0; | |
223 | ||
224 | return tx_addr_max - addr; | |
225 | } | |
226 | ||
227 | /** | |
228 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
229 | * TX FIFOs | |
230 | */ | |
231 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
232 | { | |
233 | int tx_fifo_count; | |
234 | int tx_fifo_depth; | |
235 | ||
236 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
237 | ||
238 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
239 | ||
240 | if (!tx_fifo_count) | |
241 | return tx_fifo_depth; | |
242 | else | |
243 | return tx_fifo_depth / tx_fifo_count; | |
244 | } | |
245 | ||
5b7d70c6 | 246 | /** |
1f91b4cc | 247 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
248 | * @hsotg: The device instance. |
249 | */ | |
1f91b4cc | 250 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 251 | { |
2317eacd | 252 | unsigned int ep; |
0f002d20 | 253 | unsigned int addr; |
1703a6d3 | 254 | int timeout; |
0f002d20 | 255 | u32 val; |
05ee799f | 256 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 257 | |
7fcbc95c GH |
258 | /* Reset fifo map if not correctly cleared during previous session */ |
259 | WARN_ON(hsotg->fifo_map); | |
260 | hsotg->fifo_map = 0; | |
261 | ||
0a176279 | 262 | /* set RX/NPTX FIFO sizes */ |
05ee799f JY |
263 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
264 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | | |
265 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), | |
266 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 267 | |
8b9bc460 LM |
268 | /* |
269 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
270 | * block have overlapping default addresses. This also ensures |
271 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
272 | * known values. |
273 | */ | |
0f002d20 BD |
274 | |
275 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 276 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 277 | |
8b9bc460 | 278 | /* |
0a176279 | 279 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
280 | * them to endpoints dynamically according to maxpacket size value of |
281 | * given endpoint. | |
8b9bc460 | 282 | */ |
2317eacd | 283 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 284 | if (!txfsz[ep]) |
3fa95385 JY |
285 | continue; |
286 | val = addr; | |
05ee799f JY |
287 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
288 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 289 | "insufficient fifo memory"); |
05ee799f | 290 | addr += txfsz[ep]; |
0f002d20 | 291 | |
2317eacd | 292 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
05ee799f | 293 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 294 | } |
1703a6d3 | 295 | |
f87c842f SA |
296 | dwc2_writel(hsotg->hw_params.total_fifo_size | |
297 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, | |
298 | hsotg->regs + GDFIFOCFG); | |
8b9bc460 LM |
299 | /* |
300 | * according to p428 of the design guide, we need to ensure that | |
301 | * all fifos are flushed before continuing | |
302 | */ | |
1703a6d3 | 303 | |
95c8bc36 | 304 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 305 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
306 | |
307 | /* wait until the fifos are both flushed */ | |
308 | timeout = 100; | |
309 | while (1) { | |
95c8bc36 | 310 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 311 | |
47a1685f | 312 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
313 | break; |
314 | ||
315 | if (--timeout == 0) { | |
316 | dev_err(hsotg->dev, | |
317 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
318 | __func__, val); | |
48b20bcb | 319 | break; |
1703a6d3 BD |
320 | } |
321 | ||
322 | udelay(1); | |
323 | } | |
324 | ||
325 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
326 | } |
327 | ||
328 | /** | |
329 | * @ep: USB endpoint to allocate request for. | |
330 | * @flags: Allocation flags | |
331 | * | |
332 | * Allocate a new USB request structure appropriate for the specified endpoint | |
333 | */ | |
1f91b4cc | 334 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 335 | gfp_t flags) |
5b7d70c6 | 336 | { |
1f91b4cc | 337 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 338 | |
ec33efe2 | 339 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
340 | if (!req) |
341 | return NULL; | |
342 | ||
343 | INIT_LIST_HEAD(&req->queue); | |
344 | ||
5b7d70c6 BD |
345 | return &req->req; |
346 | } | |
347 | ||
348 | /** | |
349 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
350 | * @hs_ep: The endpoint to query. | |
351 | * | |
352 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
353 | * used for an Interrupt or ISO transfer. | |
354 | */ | |
1f91b4cc | 355 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
356 | { |
357 | return hs_ep->periodic; | |
358 | } | |
359 | ||
360 | /** | |
1f91b4cc | 361 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
362 | * @hsotg: The device state. |
363 | * @hs_ep: The endpoint for the request | |
364 | * @hs_req: The request being processed. | |
365 | * | |
1f91b4cc | 366 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 367 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 368 | */ |
1f91b4cc | 369 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 370 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 371 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
372 | { |
373 | struct usb_request *req = &hs_req->req; | |
9da51974 | 374 | |
17d966a3 | 375 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
376 | } |
377 | ||
0f6b80c0 VA |
378 | /* |
379 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
380 | * for Control endpoint | |
381 | * @hsotg: The device state. | |
382 | * | |
383 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
384 | * Setup stage, per one for IN and OUT data/status transactions. | |
385 | */ | |
386 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
387 | { | |
388 | hsotg->setup_desc[0] = | |
389 | dmam_alloc_coherent(hsotg->dev, | |
390 | sizeof(struct dwc2_dma_desc), | |
391 | &hsotg->setup_desc_dma[0], | |
392 | GFP_KERNEL); | |
393 | if (!hsotg->setup_desc[0]) | |
394 | goto fail; | |
395 | ||
396 | hsotg->setup_desc[1] = | |
397 | dmam_alloc_coherent(hsotg->dev, | |
398 | sizeof(struct dwc2_dma_desc), | |
399 | &hsotg->setup_desc_dma[1], | |
400 | GFP_KERNEL); | |
401 | if (!hsotg->setup_desc[1]) | |
402 | goto fail; | |
403 | ||
404 | hsotg->ctrl_in_desc = | |
405 | dmam_alloc_coherent(hsotg->dev, | |
406 | sizeof(struct dwc2_dma_desc), | |
407 | &hsotg->ctrl_in_desc_dma, | |
408 | GFP_KERNEL); | |
409 | if (!hsotg->ctrl_in_desc) | |
410 | goto fail; | |
411 | ||
412 | hsotg->ctrl_out_desc = | |
413 | dmam_alloc_coherent(hsotg->dev, | |
414 | sizeof(struct dwc2_dma_desc), | |
415 | &hsotg->ctrl_out_desc_dma, | |
416 | GFP_KERNEL); | |
417 | if (!hsotg->ctrl_out_desc) | |
418 | goto fail; | |
419 | ||
420 | return 0; | |
421 | ||
422 | fail: | |
423 | return -ENOMEM; | |
424 | } | |
425 | ||
5b7d70c6 | 426 | /** |
1f91b4cc | 427 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
428 | * @hsotg: The controller state. |
429 | * @hs_ep: The endpoint we're going to write for. | |
430 | * @hs_req: The request to write data for. | |
431 | * | |
432 | * This is called when the TxFIFO has some space in it to hold a new | |
433 | * transmission and we have something to give it. The actual setup of | |
434 | * the data size is done elsewhere, so all we have to do is to actually | |
435 | * write the data. | |
436 | * | |
437 | * The return value is zero if there is more space (or nothing was done) | |
438 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
439 | * | |
440 | * This routine is only needed for PIO | |
8b9bc460 | 441 | */ |
1f91b4cc | 442 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 443 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 444 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
445 | { |
446 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 447 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
448 | int buf_pos = hs_req->req.actual; |
449 | int to_write = hs_ep->size_loaded; | |
450 | void *data; | |
451 | int can_write; | |
452 | int pkt_round; | |
4fca54aa | 453 | int max_transfer; |
5b7d70c6 BD |
454 | |
455 | to_write -= (buf_pos - hs_ep->last_load); | |
456 | ||
457 | /* if there's nothing to write, get out early */ | |
458 | if (to_write == 0) | |
459 | return 0; | |
460 | ||
10aebc77 | 461 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 462 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
463 | int size_left; |
464 | int size_done; | |
465 | ||
8b9bc460 LM |
466 | /* |
467 | * work out how much data was loaded so we can calculate | |
468 | * how much data is left in the fifo. | |
469 | */ | |
5b7d70c6 | 470 | |
47a1685f | 471 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 472 | |
8b9bc460 LM |
473 | /* |
474 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
475 | * previous data has been completely sent. |
476 | */ | |
477 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 478 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
479 | return -ENOSPC; |
480 | } | |
481 | ||
5b7d70c6 BD |
482 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
483 | __func__, size_left, | |
484 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
485 | ||
486 | /* how much of the data has moved */ | |
487 | size_done = hs_ep->size_loaded - size_left; | |
488 | ||
489 | /* how much data is left in the fifo */ | |
490 | can_write = hs_ep->fifo_load - size_done; | |
491 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
492 | __func__, can_write); | |
493 | ||
494 | can_write = hs_ep->fifo_size - can_write; | |
495 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
496 | __func__, can_write); | |
497 | ||
498 | if (can_write <= 0) { | |
1f91b4cc | 499 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
500 | return -ENOSPC; |
501 | } | |
10aebc77 | 502 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
503 | can_write = dwc2_readl(hsotg->regs + |
504 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
505 | |
506 | can_write &= 0xffff; | |
507 | can_write *= 4; | |
5b7d70c6 | 508 | } else { |
47a1685f | 509 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
510 | dev_dbg(hsotg->dev, |
511 | "%s: no queue slots available (0x%08x)\n", | |
512 | __func__, gnptxsts); | |
513 | ||
1f91b4cc | 514 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
515 | return -ENOSPC; |
516 | } | |
517 | ||
47a1685f | 518 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 519 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
520 | } |
521 | ||
4fca54aa RB |
522 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
523 | ||
524 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 525 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 526 | |
8b9bc460 LM |
527 | /* |
528 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
529 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
530 | * fragment of the end of the transfer in it. | |
531 | */ | |
811f3303 | 532 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
533 | can_write = 512; |
534 | ||
8b9bc460 LM |
535 | /* |
536 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 537 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
538 | * doing it. |
539 | */ | |
4fca54aa RB |
540 | if (to_write > max_transfer) { |
541 | to_write = max_transfer; | |
03e10e5a | 542 | |
5cb2ff0c RB |
543 | /* it's needed only when we do not use dedicated fifos */ |
544 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 545 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 546 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 547 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
548 | } |
549 | ||
5b7d70c6 BD |
550 | /* see if we can write data */ |
551 | ||
552 | if (to_write > can_write) { | |
553 | to_write = can_write; | |
4fca54aa | 554 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 555 | |
8b9bc460 LM |
556 | /* |
557 | * Round the write down to an | |
5b7d70c6 BD |
558 | * exact number of packets. |
559 | * | |
560 | * Note, we do not currently check to see if we can ever | |
561 | * write a full packet or not to the FIFO. | |
562 | */ | |
563 | ||
564 | if (pkt_round) | |
565 | to_write -= pkt_round; | |
566 | ||
8b9bc460 LM |
567 | /* |
568 | * enable correct FIFO interrupt to alert us when there | |
569 | * is more room left. | |
570 | */ | |
5b7d70c6 | 571 | |
5cb2ff0c RB |
572 | /* it's needed only when we do not use dedicated fifos */ |
573 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 574 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 575 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 576 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
577 | } |
578 | ||
579 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 580 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
581 | |
582 | if (to_write <= 0) | |
583 | return -ENOSPC; | |
584 | ||
585 | hs_req->req.actual = buf_pos + to_write; | |
586 | hs_ep->total_data += to_write; | |
587 | ||
588 | if (periodic) | |
589 | hs_ep->fifo_load += to_write; | |
590 | ||
591 | to_write = DIV_ROUND_UP(to_write, 4); | |
592 | data = hs_req->req.buf + buf_pos; | |
593 | ||
1a7ed5be | 594 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
595 | |
596 | return (to_write >= can_write) ? -ENOSPC : 0; | |
597 | } | |
598 | ||
599 | /** | |
600 | * get_ep_limit - get the maximum data legnth for this endpoint | |
601 | * @hs_ep: The endpoint | |
602 | * | |
603 | * Return the maximum data that can be queued in one go on a given endpoint | |
604 | * so that transfers that are too long can be split. | |
605 | */ | |
9da51974 | 606 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
607 | { |
608 | int index = hs_ep->index; | |
9da51974 JY |
609 | unsigned int maxsize; |
610 | unsigned int maxpkt; | |
5b7d70c6 BD |
611 | |
612 | if (index != 0) { | |
47a1685f DN |
613 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
614 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 615 | } else { |
9da51974 | 616 | maxsize = 64 + 64; |
66e5c643 | 617 | if (hs_ep->dir_in) |
47a1685f | 618 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 619 | else |
5b7d70c6 | 620 | maxpkt = 2; |
5b7d70c6 BD |
621 | } |
622 | ||
623 | /* we made the constant loading easier above by using +1 */ | |
624 | maxpkt--; | |
625 | maxsize--; | |
626 | ||
8b9bc460 LM |
627 | /* |
628 | * constrain by packet count if maxpkts*pktsize is greater | |
629 | * than the length register size. | |
630 | */ | |
5b7d70c6 BD |
631 | |
632 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
633 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
634 | ||
635 | return maxsize; | |
636 | } | |
637 | ||
381fc8f8 | 638 | /** |
38beaec6 JY |
639 | * dwc2_hsotg_read_frameno - read current frame number |
640 | * @hsotg: The device instance | |
641 | * | |
642 | * Return the current frame number | |
643 | */ | |
381fc8f8 VM |
644 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
645 | { | |
646 | u32 dsts; | |
647 | ||
648 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
649 | dsts &= DSTS_SOFFN_MASK; | |
650 | dsts >>= DSTS_SOFFN_SHIFT; | |
651 | ||
652 | return dsts; | |
653 | } | |
654 | ||
cf77b5fb VA |
655 | /** |
656 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
657 | * DMA descriptor chain prepared for specific endpoint | |
658 | * @hs_ep: The endpoint | |
659 | * | |
660 | * Return the maximum data that can be queued in one go on a given endpoint | |
661 | * depending on its descriptor chain capacity so that transfers that | |
662 | * are too long can be split. | |
663 | */ | |
664 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
665 | { | |
666 | int is_isoc = hs_ep->isochronous; | |
667 | unsigned int maxsize; | |
668 | ||
669 | if (is_isoc) | |
670 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
671 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
672 | else | |
673 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
674 | ||
675 | /* Above size of one descriptor was chosen, multiple it */ | |
676 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
677 | ||
678 | return maxsize; | |
679 | } | |
680 | ||
e02f9aa6 VA |
681 | /* |
682 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
683 | * @hs_ep: The endpoint | |
684 | * @mask: RX/TX bytes mask to be defined | |
685 | * | |
686 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
687 | * characteristics. | |
688 | * DMA descriptor transfer bytes limit depends on EP type: | |
689 | * Control out - MPS, | |
690 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
691 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
692 | * have concatenations from various descriptors within one packet. | |
693 | * | |
694 | * Selects corresponding mask for RX/TX bytes as well. | |
695 | */ | |
696 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
697 | { | |
698 | u32 mps = hs_ep->ep.maxpacket; | |
699 | int dir_in = hs_ep->dir_in; | |
700 | u32 desc_size = 0; | |
701 | ||
702 | if (!hs_ep->index && !dir_in) { | |
703 | desc_size = mps; | |
704 | *mask = DEV_DMA_NBYTES_MASK; | |
705 | } else if (hs_ep->isochronous) { | |
706 | if (dir_in) { | |
707 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
708 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
709 | } else { | |
710 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
711 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
712 | } | |
713 | } else { | |
714 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
715 | *mask = DEV_DMA_NBYTES_MASK; | |
716 | ||
717 | /* Round down desc_size to be mps multiple */ | |
718 | desc_size -= desc_size % mps; | |
719 | } | |
720 | ||
721 | return desc_size; | |
722 | } | |
723 | ||
724 | /* | |
725 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
726 | * @hs_ep: The endpoint | |
727 | * @dma_buff: DMA address to use | |
728 | * @len: Length of the transfer | |
729 | * | |
730 | * This function will iterate over descriptor chain and fill its entries | |
731 | * with corresponding information based on transfer data. | |
732 | */ | |
733 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
734 | dma_addr_t dma_buff, | |
735 | unsigned int len) | |
736 | { | |
737 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
738 | int dir_in = hs_ep->dir_in; | |
739 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
740 | u32 mps = hs_ep->ep.maxpacket; | |
741 | u32 maxsize = 0; | |
742 | u32 offset = 0; | |
743 | u32 mask = 0; | |
744 | int i; | |
745 | ||
746 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
747 | ||
748 | hs_ep->desc_count = (len / maxsize) + | |
749 | ((len % maxsize) ? 1 : 0); | |
750 | if (len == 0) | |
751 | hs_ep->desc_count = 1; | |
752 | ||
753 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
754 | desc->status = 0; | |
755 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
756 | << DEV_DMA_BUFF_STS_SHIFT); | |
757 | ||
758 | if (len > maxsize) { | |
759 | if (!hs_ep->index && !dir_in) | |
760 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
761 | ||
762 | desc->status |= (maxsize << | |
763 | DEV_DMA_NBYTES_SHIFT & mask); | |
764 | desc->buf = dma_buff + offset; | |
765 | ||
766 | len -= maxsize; | |
767 | offset += maxsize; | |
768 | } else { | |
769 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
770 | ||
771 | if (dir_in) | |
772 | desc->status |= (len % mps) ? DEV_DMA_SHORT : | |
773 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); | |
774 | if (len > maxsize) | |
775 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
776 | ||
777 | desc->status |= | |
778 | len << DEV_DMA_NBYTES_SHIFT & mask; | |
779 | desc->buf = dma_buff + offset; | |
780 | } | |
781 | ||
782 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
783 | desc->status |= (DEV_DMA_BUFF_STS_HREADY | |
784 | << DEV_DMA_BUFF_STS_SHIFT); | |
785 | desc++; | |
786 | } | |
787 | } | |
788 | ||
540ccba0 VA |
789 | /* |
790 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
791 | * @hs_ep: The isochronous endpoint. | |
792 | * @dma_buff: usb requests dma buffer. | |
793 | * @len: usb request transfer length. | |
794 | * | |
795 | * Finds out index of first free entry either in the bottom or up half of | |
796 | * descriptor chain depend on which is under SW control and not processed | |
797 | * by HW. Then fills that descriptor with the data of the arrived usb request, | |
798 | * frame info, sets Last and IOC bits increments next_desc. If filled | |
799 | * descriptor is not the first one, removes L bit from the previous descriptor | |
800 | * status. | |
801 | */ | |
802 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
803 | dma_addr_t dma_buff, unsigned int len) | |
804 | { | |
805 | struct dwc2_dma_desc *desc; | |
806 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
807 | u32 index; | |
808 | u32 maxsize = 0; | |
809 | u32 mask = 0; | |
810 | ||
811 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
812 | if (len > maxsize) { | |
813 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
814 | return -EINVAL; | |
815 | } | |
816 | ||
817 | /* | |
818 | * If SW has already filled half of chain, then return and wait for | |
819 | * the other chain to be processed by HW. | |
820 | */ | |
821 | if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2) | |
822 | return -EBUSY; | |
823 | ||
824 | /* Increment frame number by interval for IN */ | |
825 | if (hs_ep->dir_in) | |
826 | dwc2_gadget_incr_frame_num(hs_ep); | |
827 | ||
828 | index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num + | |
829 | hs_ep->next_desc; | |
830 | ||
831 | /* Sanity check of calculated index */ | |
832 | if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) || | |
833 | (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) { | |
834 | dev_err(hsotg->dev, "wrong index %d for iso chain\n", index); | |
835 | return -EINVAL; | |
836 | } | |
837 | ||
838 | desc = &hs_ep->desc_list[index]; | |
839 | ||
840 | /* Clear L bit of previous desc if more than one entries in the chain */ | |
841 | if (hs_ep->next_desc) | |
842 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
843 | ||
844 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
845 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
846 | ||
847 | desc->status = 0; | |
848 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
849 | ||
850 | desc->buf = dma_buff; | |
851 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
852 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
853 | ||
854 | if (hs_ep->dir_in) { | |
855 | desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) & | |
856 | DEV_DMA_ISOC_PID_MASK) | | |
857 | ((len % hs_ep->ep.maxpacket) ? | |
858 | DEV_DMA_SHORT : 0) | | |
859 | ((hs_ep->target_frame << | |
860 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
861 | DEV_DMA_ISOC_FRNUM_MASK); | |
862 | } | |
863 | ||
864 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
865 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
866 | ||
867 | /* Update index of last configured entry in the chain */ | |
868 | hs_ep->next_desc++; | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | /* | |
874 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
875 | * @hs_ep: The isochronous endpoint. | |
876 | * | |
877 | * Prepare first descriptor chain for isochronous endpoints. Afterwards | |
878 | * write DMA address to HW and enable the endpoint. | |
879 | * | |
880 | * Switch between descriptor chains via isoc_chain_num to give SW opportunity | |
881 | * to prepare second descriptor chain while first one is being processed by HW. | |
882 | */ | |
883 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
884 | { | |
885 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
886 | struct dwc2_hsotg_req *hs_req, *treq; | |
887 | int index = hs_ep->index; | |
888 | int ret; | |
889 | u32 dma_reg; | |
890 | u32 depctl; | |
891 | u32 ctrl; | |
892 | ||
893 | if (list_empty(&hs_ep->queue)) { | |
894 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); | |
895 | return; | |
896 | } | |
897 | ||
898 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { | |
899 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
900 | hs_req->req.length); | |
901 | if (ret) { | |
902 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
903 | break; | |
904 | } | |
905 | } | |
906 | ||
907 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
908 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
909 | ||
910 | /* write descriptor chain address to control register */ | |
911 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
912 | ||
913 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
914 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
915 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
916 | ||
917 | /* Switch ISOC descriptor chain number being processed by SW*/ | |
918 | hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1; | |
919 | hs_ep->next_desc = 0; | |
920 | } | |
921 | ||
5b7d70c6 | 922 | /** |
1f91b4cc | 923 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
924 | * @hsotg: The controller state. |
925 | * @hs_ep: The endpoint to process a request for | |
926 | * @hs_req: The request to start. | |
927 | * @continuing: True if we are doing more for the current request. | |
928 | * | |
929 | * Start the given request running by setting the endpoint registers | |
930 | * appropriately, and writing any data to the FIFOs. | |
931 | */ | |
1f91b4cc | 932 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 933 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 934 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
935 | bool continuing) |
936 | { | |
937 | struct usb_request *ureq = &hs_req->req; | |
938 | int index = hs_ep->index; | |
939 | int dir_in = hs_ep->dir_in; | |
940 | u32 epctrl_reg; | |
941 | u32 epsize_reg; | |
942 | u32 epsize; | |
943 | u32 ctrl; | |
9da51974 JY |
944 | unsigned int length; |
945 | unsigned int packets; | |
946 | unsigned int maxreq; | |
aa3e8bc8 | 947 | unsigned int dma_reg; |
5b7d70c6 BD |
948 | |
949 | if (index != 0) { | |
950 | if (hs_ep->req && !continuing) { | |
951 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
952 | WARN_ON(1); | |
953 | return; | |
954 | } else if (hs_ep->req != hs_req && continuing) { | |
955 | dev_err(hsotg->dev, | |
956 | "%s: continue different req\n", __func__); | |
957 | WARN_ON(1); | |
958 | return; | |
959 | } | |
960 | } | |
961 | ||
aa3e8bc8 | 962 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
963 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
964 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
965 | |
966 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 967 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
968 | hs_ep->dir_in ? "in" : "out"); |
969 | ||
9c39ddc6 | 970 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 971 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 972 | |
b2d4c54e | 973 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
974 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
975 | return; | |
976 | } | |
977 | ||
5b7d70c6 | 978 | length = ureq->length - ureq->actual; |
71225bee LM |
979 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
980 | ureq->length, ureq->actual); | |
5b7d70c6 | 981 | |
cf77b5fb VA |
982 | if (!using_desc_dma(hsotg)) |
983 | maxreq = get_ep_limit(hs_ep); | |
984 | else | |
985 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
986 | ||
5b7d70c6 BD |
987 | if (length > maxreq) { |
988 | int round = maxreq % hs_ep->ep.maxpacket; | |
989 | ||
990 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
991 | __func__, length, maxreq, round); | |
992 | ||
993 | /* round down to multiple of packets */ | |
994 | if (round) | |
995 | maxreq -= round; | |
996 | ||
997 | length = maxreq; | |
998 | } | |
999 | ||
1000 | if (length) | |
1001 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1002 | else | |
1003 | packets = 1; /* send one packet if length is zero. */ | |
1004 | ||
4fca54aa RB |
1005 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1006 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1007 | return; | |
1008 | } | |
1009 | ||
5b7d70c6 | 1010 | if (dir_in && index != 0) |
4fca54aa | 1011 | if (hs_ep->isochronous) |
47a1685f | 1012 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1013 | else |
47a1685f | 1014 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1015 | else |
1016 | epsize = 0; | |
1017 | ||
f71b5e25 MYK |
1018 | /* |
1019 | * zero length packet should be programmed on its own and should not | |
1020 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1021 | */ | |
1022 | if (dir_in && ureq->zero && !continuing) { | |
1023 | /* Test if zlp is actually required. */ | |
1024 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1025 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1026 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1027 | } |
1028 | ||
47a1685f DN |
1029 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1030 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1031 | |
1032 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1033 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1034 | ||
1035 | /* store the request as the current one we're doing */ | |
1036 | hs_ep->req = hs_req; | |
1037 | ||
aa3e8bc8 VA |
1038 | if (using_desc_dma(hsotg)) { |
1039 | u32 offset = 0; | |
1040 | u32 mps = hs_ep->ep.maxpacket; | |
1041 | ||
1042 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1043 | if (!dir_in) { | |
1044 | if (!index) | |
1045 | length = mps; | |
1046 | else if (length % mps) | |
1047 | length += (mps - (length % mps)); | |
1048 | } | |
5b7d70c6 | 1049 | |
8b9bc460 | 1050 | /* |
aa3e8bc8 VA |
1051 | * If more data to send, adjust DMA for EP0 out data stage. |
1052 | * ureq->dma stays unchanged, hence increment it by already | |
1053 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1054 | */ |
aa3e8bc8 VA |
1055 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1056 | continuing) | |
1057 | offset = ureq->actual; | |
1058 | ||
1059 | /* Fill DDMA chain entries */ | |
1060 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, | |
1061 | length); | |
1062 | ||
1063 | /* write descriptor chain address to control register */ | |
1064 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
5b7d70c6 | 1065 | |
aa3e8bc8 VA |
1066 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1067 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1068 | } else { | |
1069 | /* write size / packets */ | |
1070 | dwc2_writel(epsize, hsotg->regs + epsize_reg); | |
1071 | ||
729e6574 | 1072 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1073 | /* |
1074 | * write DMA address to control register, buffer | |
1075 | * already synced by dwc2_hsotg_ep_queue(). | |
1076 | */ | |
5b7d70c6 | 1077 | |
aa3e8bc8 VA |
1078 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
1079 | ||
1080 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1081 | __func__, &ureq->dma, dma_reg); | |
1082 | } | |
5b7d70c6 BD |
1083 | } |
1084 | ||
837e9f00 VM |
1085 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1086 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1087 | dwc2_gadget_incr_frame_num(hs_ep); | |
1088 | ||
1089 | if (hs_ep->target_frame & 0x1) | |
1090 | ctrl |= DXEPCTL_SETODDFR; | |
1091 | else | |
1092 | ctrl |= DXEPCTL_SETEVENFR; | |
1093 | } | |
1094 | ||
47a1685f | 1095 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1096 | |
fe0b94ab | 1097 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1098 | |
1099 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1100 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1101 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1102 | |
5b7d70c6 | 1103 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 1104 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 1105 | |
8b9bc460 LM |
1106 | /* |
1107 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1108 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1109 | * this information. |
1110 | */ | |
5b7d70c6 BD |
1111 | hs_ep->size_loaded = length; |
1112 | hs_ep->last_load = ureq->actual; | |
1113 | ||
1114 | if (dir_in && !using_dma(hsotg)) { | |
1115 | /* set these anyway, we may need them for non-periodic in */ | |
1116 | hs_ep->fifo_load = 0; | |
1117 | ||
1f91b4cc | 1118 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1119 | } |
1120 | ||
8b9bc460 LM |
1121 | /* |
1122 | * Note, trying to clear the NAK here causes problems with transmit | |
1123 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1124 | */ | |
5b7d70c6 BD |
1125 | |
1126 | /* check ep is enabled */ | |
95c8bc36 | 1127 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1128 | dev_dbg(hsotg->dev, |
9da51974 | 1129 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 1130 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 1131 | |
47a1685f | 1132 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 1133 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
1134 | |
1135 | /* enable ep interrupts */ | |
1f91b4cc | 1136 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1137 | } |
1138 | ||
1139 | /** | |
1f91b4cc | 1140 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1141 | * @hsotg: The device state. |
1142 | * @hs_ep: The endpoint the request is on. | |
1143 | * @req: The request being processed. | |
1144 | * | |
1145 | * We've been asked to queue a request, so ensure that the memory buffer | |
1146 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1147 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1148 | * DMA memory, then we map the memory and mark our request to allow us to | |
1149 | * cleanup on completion. | |
8b9bc460 | 1150 | */ |
1f91b4cc | 1151 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1152 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1153 | struct usb_request *req) |
1154 | { | |
e58ebcd1 | 1155 | int ret; |
5b7d70c6 | 1156 | |
e58ebcd1 FB |
1157 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1158 | if (ret) | |
1159 | goto dma_error; | |
5b7d70c6 BD |
1160 | |
1161 | return 0; | |
1162 | ||
1163 | dma_error: | |
1164 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1165 | __func__, req->buf, req->length); | |
1166 | ||
1167 | return -EIO; | |
1168 | } | |
1169 | ||
1f91b4cc | 1170 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1171 | struct dwc2_hsotg_ep *hs_ep, |
1172 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1173 | { |
1174 | void *req_buf = hs_req->req.buf; | |
1175 | ||
1176 | /* If dma is not being used or buffer is aligned */ | |
1177 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1178 | return 0; | |
1179 | ||
1180 | WARN_ON(hs_req->saved_req_buf); | |
1181 | ||
1182 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1183 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1184 | |
1185 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1186 | if (!hs_req->req.buf) { | |
1187 | hs_req->req.buf = req_buf; | |
1188 | dev_err(hsotg->dev, | |
1189 | "%s: unable to allocate memory for bounce buffer\n", | |
1190 | __func__); | |
1191 | return -ENOMEM; | |
1192 | } | |
1193 | ||
1194 | /* Save actual buffer */ | |
1195 | hs_req->saved_req_buf = req_buf; | |
1196 | ||
1197 | if (hs_ep->dir_in) | |
1198 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1199 | return 0; | |
1200 | } | |
1201 | ||
b98866c2 JY |
1202 | static void |
1203 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1204 | struct dwc2_hsotg_ep *hs_ep, | |
1205 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1206 | { |
1207 | /* If dma is not being used or buffer was aligned */ | |
1208 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1209 | return; | |
1210 | ||
1211 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1212 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1213 | ||
1214 | /* Copy data from bounce buffer on successful out transfer */ | |
1215 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1216 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1217 | hs_req->req.actual); |
7d24c1b5 MYK |
1218 | |
1219 | /* Free bounce buffer */ | |
1220 | kfree(hs_req->req.buf); | |
1221 | ||
1222 | hs_req->req.buf = hs_req->saved_req_buf; | |
1223 | hs_req->saved_req_buf = NULL; | |
1224 | } | |
1225 | ||
381fc8f8 VM |
1226 | /** |
1227 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1228 | * @hs_ep: The driver endpoint to check | |
1229 | * | |
1230 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1231 | * corresponding transfer. | |
1232 | */ | |
1233 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1234 | { | |
1235 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1236 | u32 target_frame = hs_ep->target_frame; | |
1237 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
1238 | bool frame_overrun = hs_ep->frame_overrun; | |
1239 | ||
1240 | if (!frame_overrun && current_frame >= target_frame) | |
1241 | return true; | |
1242 | ||
1243 | if (frame_overrun && current_frame >= target_frame && | |
1244 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1245 | return true; | |
1246 | ||
1247 | return false; | |
1248 | } | |
1249 | ||
e02f9aa6 VA |
1250 | /* |
1251 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1252 | * @hsotg: The driver state | |
1253 | * @hs_ep: the ep descriptor chain is for | |
1254 | * | |
1255 | * Called to update EP0 structure's pointers depend on stage of | |
1256 | * control transfer. | |
1257 | */ | |
1258 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1259 | struct dwc2_hsotg_ep *hs_ep) | |
1260 | { | |
1261 | switch (hsotg->ep0_state) { | |
1262 | case DWC2_EP0_SETUP: | |
1263 | case DWC2_EP0_STATUS_OUT: | |
1264 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1265 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1266 | break; | |
1267 | case DWC2_EP0_DATA_IN: | |
1268 | case DWC2_EP0_STATUS_IN: | |
1269 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1270 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1271 | break; | |
1272 | case DWC2_EP0_DATA_OUT: | |
1273 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1274 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1275 | break; | |
1276 | default: | |
1277 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1278 | hsotg->ep0_state); | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1f91b4cc | 1285 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1286 | gfp_t gfp_flags) |
5b7d70c6 | 1287 | { |
1f91b4cc FB |
1288 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1289 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1290 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1291 | bool first; |
7d24c1b5 | 1292 | int ret; |
5b7d70c6 BD |
1293 | |
1294 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1295 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1296 | req->zero, req->short_not_ok); | |
1297 | ||
7ababa92 GH |
1298 | /* Prevent new request submission when controller is suspended */ |
1299 | if (hs->lx_state == DWC2_L2) { | |
1300 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
9da51974 | 1301 | __func__); |
7ababa92 GH |
1302 | return -EAGAIN; |
1303 | } | |
1304 | ||
5b7d70c6 BD |
1305 | /* initialise status of the request */ |
1306 | INIT_LIST_HEAD(&hs_req->queue); | |
1307 | req->actual = 0; | |
1308 | req->status = -EINPROGRESS; | |
1309 | ||
1f91b4cc | 1310 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1311 | if (ret) |
1312 | return ret; | |
1313 | ||
5b7d70c6 BD |
1314 | /* if we're using DMA, sync the buffers as necessary */ |
1315 | if (using_dma(hs)) { | |
1f91b4cc | 1316 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1317 | if (ret) |
1318 | return ret; | |
1319 | } | |
e02f9aa6 VA |
1320 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1321 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1322 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1323 | if (ret) | |
1324 | return ret; | |
1325 | } | |
5b7d70c6 | 1326 | |
5b7d70c6 BD |
1327 | first = list_empty(&hs_ep->queue); |
1328 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1329 | ||
540ccba0 VA |
1330 | /* |
1331 | * Handle DDMA isochronous transfers separately - just add new entry | |
1332 | * to the half of descriptor chain that is not processed by HW. | |
1333 | * Transfer will be started once SW gets either one of NAK or | |
1334 | * OutTknEpDis interrupts. | |
1335 | */ | |
1336 | if (using_desc_dma(hs) && hs_ep->isochronous && | |
1337 | hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
1338 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
1339 | hs_req->req.length); | |
1340 | if (ret) | |
1341 | dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__); | |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | ||
837e9f00 VM |
1346 | if (first) { |
1347 | if (!hs_ep->isochronous) { | |
1348 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) | |
1353 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 1354 | |
837e9f00 VM |
1355 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1356 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1357 | } | |
5b7d70c6 BD |
1358 | return 0; |
1359 | } | |
1360 | ||
1f91b4cc | 1361 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1362 | gfp_t gfp_flags) |
5ad1d316 | 1363 | { |
1f91b4cc | 1364 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1365 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1366 | unsigned long flags = 0; |
1367 | int ret = 0; | |
1368 | ||
1369 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1370 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1371 | spin_unlock_irqrestore(&hs->lock, flags); |
1372 | ||
1373 | return ret; | |
1374 | } | |
1375 | ||
1f91b4cc | 1376 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1377 | struct usb_request *req) |
5b7d70c6 | 1378 | { |
1f91b4cc | 1379 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1380 | |
1381 | kfree(hs_req); | |
1382 | } | |
1383 | ||
1384 | /** | |
1f91b4cc | 1385 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1386 | * @ep: The endpoint the request was on. |
1387 | * @req: The request completed. | |
1388 | * | |
1389 | * Called on completion of any requests the driver itself | |
1390 | * submitted that need cleaning up. | |
1391 | */ | |
1f91b4cc | 1392 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1393 | struct usb_request *req) |
5b7d70c6 | 1394 | { |
1f91b4cc | 1395 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1396 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1397 | |
1398 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1399 | ||
1f91b4cc | 1400 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1401 | } |
1402 | ||
1403 | /** | |
1404 | * ep_from_windex - convert control wIndex value to endpoint | |
1405 | * @hsotg: The driver state. | |
1406 | * @windex: The control request wIndex field (in host order). | |
1407 | * | |
1408 | * Convert the given wIndex into a pointer to an driver endpoint | |
1409 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1410 | */ |
1f91b4cc | 1411 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1412 | u32 windex) |
5b7d70c6 | 1413 | { |
1f91b4cc | 1414 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1415 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1416 | int idx = windex & 0x7F; | |
1417 | ||
1418 | if (windex >= 0x100) | |
1419 | return NULL; | |
1420 | ||
b3f489b2 | 1421 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1422 | return NULL; |
1423 | ||
c6f5c050 MYK |
1424 | ep = index_to_ep(hsotg, idx, dir); |
1425 | ||
5b7d70c6 BD |
1426 | if (idx && ep->dir_in != dir) |
1427 | return NULL; | |
1428 | ||
1429 | return ep; | |
1430 | } | |
1431 | ||
9e14d0a5 | 1432 | /** |
1f91b4cc | 1433 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1434 | * @hsotg: The driver state. |
1435 | * @testmode: requested usb test mode | |
1436 | * Enable usb Test Mode requested by the Host. | |
1437 | */ | |
1f91b4cc | 1438 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1439 | { |
95c8bc36 | 1440 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
1441 | |
1442 | dctl &= ~DCTL_TSTCTL_MASK; | |
1443 | switch (testmode) { | |
1444 | case TEST_J: | |
1445 | case TEST_K: | |
1446 | case TEST_SE0_NAK: | |
1447 | case TEST_PACKET: | |
1448 | case TEST_FORCE_EN: | |
1449 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1450 | break; | |
1451 | default: | |
1452 | return -EINVAL; | |
1453 | } | |
95c8bc36 | 1454 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
1455 | return 0; |
1456 | } | |
1457 | ||
5b7d70c6 | 1458 | /** |
1f91b4cc | 1459 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1460 | * @hsotg: The device state |
1461 | * @ep: Endpoint 0 | |
1462 | * @buff: Buffer for request | |
1463 | * @length: Length of reply. | |
1464 | * | |
1465 | * Create a request and queue it on the given endpoint. This is useful as | |
1466 | * an internal method of sending replies to certain control requests, etc. | |
1467 | */ | |
1f91b4cc | 1468 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1469 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1470 | void *buff, |
1471 | int length) | |
1472 | { | |
1473 | struct usb_request *req; | |
1474 | int ret; | |
1475 | ||
1476 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1477 | ||
1f91b4cc | 1478 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1479 | hsotg->ep0_reply = req; |
1480 | if (!req) { | |
1481 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1482 | return -ENOMEM; | |
1483 | } | |
1484 | ||
1485 | req->buf = hsotg->ep0_buff; | |
1486 | req->length = length; | |
f71b5e25 MYK |
1487 | /* |
1488 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1489 | * STATUS stage. | |
1490 | */ | |
1491 | req->zero = 0; | |
1f91b4cc | 1492 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1493 | |
1494 | if (length) | |
1495 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1496 | |
1f91b4cc | 1497 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1498 | if (ret) { |
1499 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1500 | return ret; | |
1501 | } | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | /** | |
1f91b4cc | 1507 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1508 | * @hsotg: The device state |
1509 | * @ctrl: USB control request | |
1510 | */ | |
1f91b4cc | 1511 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1512 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1513 | { |
1f91b4cc FB |
1514 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1515 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1516 | __le16 reply; |
1517 | int ret; | |
1518 | ||
1519 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1520 | ||
1521 | if (!ep0->dir_in) { | |
1522 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1523 | return -EINVAL; | |
1524 | } | |
1525 | ||
1526 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1527 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1528 | /* |
1529 | * bit 0 => self powered | |
1530 | * bit 1 => remote wakeup | |
1531 | */ | |
1532 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1533 | break; |
1534 | ||
1535 | case USB_RECIP_INTERFACE: | |
1536 | /* currently, the data result should be zero */ | |
1537 | reply = cpu_to_le16(0); | |
1538 | break; | |
1539 | ||
1540 | case USB_RECIP_ENDPOINT: | |
1541 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1542 | if (!ep) | |
1543 | return -ENOENT; | |
1544 | ||
1545 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1546 | break; | |
1547 | ||
1548 | default: | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1553 | return -EINVAL; | |
1554 | ||
1f91b4cc | 1555 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1556 | if (ret) { |
1557 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1558 | return ret; | |
1559 | } | |
1560 | ||
1561 | return 1; | |
1562 | } | |
1563 | ||
51da43b5 | 1564 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1565 | |
9c39ddc6 AT |
1566 | /** |
1567 | * get_ep_head - return the first request on the endpoint | |
1568 | * @hs_ep: The controller endpoint to get | |
1569 | * | |
1570 | * Get the first request on the endpoint. | |
1571 | */ | |
1f91b4cc | 1572 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1573 | { |
ffc4b406 MY |
1574 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1575 | queue); | |
9c39ddc6 AT |
1576 | } |
1577 | ||
41cc4cd2 VM |
1578 | /** |
1579 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1580 | * @hs_ep: Endpoint structure | |
1581 | * | |
1582 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1583 | * in its handler. Hence we need to unmask it here to be able to do | |
1584 | * resynchronization. | |
1585 | */ | |
1586 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1587 | { | |
1588 | u32 mask; | |
1589 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1590 | int dir_in = hs_ep->dir_in; | |
1591 | struct dwc2_hsotg_req *hs_req; | |
1592 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1593 | ||
1594 | if (!list_empty(&hs_ep->queue)) { | |
1595 | hs_req = get_ep_head(hs_ep); | |
1596 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1597 | return; | |
1598 | } | |
1599 | if (!hs_ep->isochronous) | |
1600 | return; | |
1601 | ||
1602 | if (dir_in) { | |
1603 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1604 | __func__); | |
1605 | } else { | |
1606 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1607 | __func__); | |
1608 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1609 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1610 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1611 | } | |
1612 | } | |
1613 | ||
5b7d70c6 | 1614 | /** |
1f91b4cc | 1615 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1616 | * @hsotg: The device state |
1617 | * @ctrl: USB control request | |
1618 | */ | |
1f91b4cc | 1619 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1620 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1621 | { |
1f91b4cc FB |
1622 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1623 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1624 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1625 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1626 | int ret; |
bd9ef7bf | 1627 | bool halted; |
9e14d0a5 GH |
1628 | u32 recip; |
1629 | u32 wValue; | |
1630 | u32 wIndex; | |
5b7d70c6 BD |
1631 | |
1632 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1633 | __func__, set ? "SET" : "CLEAR"); | |
1634 | ||
9e14d0a5 GH |
1635 | wValue = le16_to_cpu(ctrl->wValue); |
1636 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1637 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1638 | ||
1639 | switch (recip) { | |
1640 | case USB_RECIP_DEVICE: | |
1641 | switch (wValue) { | |
1642 | case USB_DEVICE_TEST_MODE: | |
1643 | if ((wIndex & 0xff) != 0) | |
1644 | return -EINVAL; | |
1645 | if (!set) | |
1646 | return -EINVAL; | |
1647 | ||
1648 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1649 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1650 | if (ret) { |
1651 | dev_err(hsotg->dev, | |
1652 | "%s: failed to send reply\n", __func__); | |
1653 | return ret; | |
1654 | } | |
1655 | break; | |
1656 | default: | |
1657 | return -ENOENT; | |
1658 | } | |
1659 | break; | |
1660 | ||
1661 | case USB_RECIP_ENDPOINT: | |
1662 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1663 | if (!ep) { |
1664 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1665 | __func__, wIndex); |
5b7d70c6 BD |
1666 | return -ENOENT; |
1667 | } | |
1668 | ||
9e14d0a5 | 1669 | switch (wValue) { |
5b7d70c6 | 1670 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1671 | halted = ep->halted; |
1672 | ||
51da43b5 | 1673 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1674 | |
1f91b4cc | 1675 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1676 | if (ret) { |
1677 | dev_err(hsotg->dev, | |
1678 | "%s: failed to send reply\n", __func__); | |
1679 | return ret; | |
1680 | } | |
9c39ddc6 | 1681 | |
bd9ef7bf RB |
1682 | /* |
1683 | * we have to complete all requests for ep if it was | |
1684 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1685 | */ | |
1686 | ||
1687 | if (!set && halted) { | |
9c39ddc6 AT |
1688 | /* |
1689 | * If we have request in progress, | |
1690 | * then complete it | |
1691 | */ | |
1692 | if (ep->req) { | |
1693 | hs_req = ep->req; | |
1694 | ep->req = NULL; | |
1695 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1696 | if (hs_req->req.complete) { |
1697 | spin_unlock(&hsotg->lock); | |
1698 | usb_gadget_giveback_request( | |
1699 | &ep->ep, &hs_req->req); | |
1700 | spin_lock(&hsotg->lock); | |
1701 | } | |
9c39ddc6 AT |
1702 | } |
1703 | ||
1704 | /* If we have pending request, then start it */ | |
34c0887f | 1705 | if (!ep->req) |
41cc4cd2 | 1706 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1707 | } |
1708 | ||
5b7d70c6 BD |
1709 | break; |
1710 | ||
1711 | default: | |
1712 | return -ENOENT; | |
1713 | } | |
9e14d0a5 GH |
1714 | break; |
1715 | default: | |
1716 | return -ENOENT; | |
1717 | } | |
5b7d70c6 BD |
1718 | return 1; |
1719 | } | |
1720 | ||
1f91b4cc | 1721 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1722 | |
c9f721b2 | 1723 | /** |
1f91b4cc | 1724 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1725 | * @hsotg: The device state |
1726 | * | |
1727 | * Set stall for ep0 as response for setup request. | |
1728 | */ | |
1f91b4cc | 1729 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1730 | { |
1f91b4cc | 1731 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1732 | u32 reg; |
1733 | u32 ctrl; | |
1734 | ||
1735 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1736 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1737 | ||
1738 | /* | |
1739 | * DxEPCTL_Stall will be cleared by EP once it has | |
1740 | * taken effect, so no need to clear later. | |
1741 | */ | |
1742 | ||
95c8bc36 | 1743 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1744 | ctrl |= DXEPCTL_STALL; |
1745 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1746 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1747 | |
1748 | dev_dbg(hsotg->dev, | |
47a1685f | 1749 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1750 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1751 | |
1752 | /* | |
1753 | * complete won't be called, so we enqueue | |
1754 | * setup request here | |
1755 | */ | |
1f91b4cc | 1756 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1757 | } |
1758 | ||
5b7d70c6 | 1759 | /** |
1f91b4cc | 1760 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1761 | * @hsotg: The device state |
1762 | * @ctrl: The control request received | |
1763 | * | |
1764 | * The controller has received the SETUP phase of a control request, and | |
1765 | * needs to work out what to do next (and whether to pass it on to the | |
1766 | * gadget driver). | |
1767 | */ | |
1f91b4cc | 1768 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1769 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1770 | { |
1f91b4cc | 1771 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1772 | int ret = 0; |
1773 | u32 dcfg; | |
1774 | ||
e525e743 MYK |
1775 | dev_dbg(hsotg->dev, |
1776 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1777 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1778 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1779 | |
fe0b94ab MYK |
1780 | if (ctrl->wLength == 0) { |
1781 | ep0->dir_in = 1; | |
1782 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1783 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1784 | ep0->dir_in = 1; |
fe0b94ab MYK |
1785 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1786 | } else { | |
1787 | ep0->dir_in = 0; | |
1788 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1789 | } | |
5b7d70c6 BD |
1790 | |
1791 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1792 | switch (ctrl->bRequest) { | |
1793 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1794 | hsotg->connected = 1; |
95c8bc36 | 1795 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1796 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1797 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1798 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1799 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1800 | |
1801 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1802 | ||
1f91b4cc | 1803 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1804 | return; |
1805 | ||
1806 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1807 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1808 | break; |
1809 | ||
1810 | case USB_REQ_CLEAR_FEATURE: | |
1811 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1812 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1813 | break; |
1814 | } | |
1815 | } | |
1816 | ||
1817 | /* as a fallback, try delivering it to the driver to deal with */ | |
1818 | ||
1819 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1820 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1821 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1822 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1823 | if (ret < 0) |
1824 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1825 | } | |
1826 | ||
8b9bc460 LM |
1827 | /* |
1828 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1829 | * so respond with a STALL for the status stage to indicate failure. |
1830 | */ | |
1831 | ||
c9f721b2 | 1832 | if (ret < 0) |
1f91b4cc | 1833 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1834 | } |
1835 | ||
5b7d70c6 | 1836 | /** |
1f91b4cc | 1837 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1838 | * @ep: The endpoint the request was on. |
1839 | * @req: The request completed. | |
1840 | * | |
1841 | * Called on completion of any requests the driver itself submitted for | |
1842 | * EP0 setup packets | |
1843 | */ | |
1f91b4cc | 1844 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1845 | struct usb_request *req) |
5b7d70c6 | 1846 | { |
1f91b4cc | 1847 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1848 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1849 | |
1850 | if (req->status < 0) { | |
1851 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1852 | return; | |
1853 | } | |
1854 | ||
93f599f2 | 1855 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1856 | if (req->actual == 0) |
1f91b4cc | 1857 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1858 | else |
1f91b4cc | 1859 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1860 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1861 | } |
1862 | ||
1863 | /** | |
1f91b4cc | 1864 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1865 | * @hsotg: The device state. |
1866 | * | |
1867 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1868 | * received from the host. | |
1869 | */ | |
1f91b4cc | 1870 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1871 | { |
1872 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1873 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1874 | int ret; |
1875 | ||
1876 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1877 | ||
1878 | req->zero = 0; | |
1879 | req->length = 8; | |
1880 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1881 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1882 | |
1883 | if (!list_empty(&hs_req->queue)) { | |
1884 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1885 | return; | |
1886 | } | |
1887 | ||
c6f5c050 | 1888 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1889 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1890 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1891 | |
1f91b4cc | 1892 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1893 | if (ret < 0) { |
1894 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1895 | /* |
1896 | * Don't think there's much we can do other than watch the | |
1897 | * driver fail. | |
1898 | */ | |
5b7d70c6 BD |
1899 | } |
1900 | } | |
1901 | ||
1f91b4cc | 1902 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 1903 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
1904 | { |
1905 | u32 ctrl; | |
1906 | u8 index = hs_ep->index; | |
1907 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1908 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1909 | ||
ccb34a91 MYK |
1910 | if (hs_ep->dir_in) |
1911 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 1912 | index); |
ccb34a91 MYK |
1913 | else |
1914 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
1915 | index); |
1916 | if (using_desc_dma(hsotg)) { | |
1917 | /* Not specific buffer needed for ep0 ZLP */ | |
1918 | dma_addr_t dma = hs_ep->desc_list_dma; | |
fe0b94ab | 1919 | |
e02f9aa6 VA |
1920 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); |
1921 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); | |
1922 | } else { | |
1923 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1924 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1925 | epsiz_reg); | |
1926 | } | |
fe0b94ab | 1927 | |
95c8bc36 | 1928 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1929 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1930 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1931 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1932 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1933 | } |
1934 | ||
5b7d70c6 | 1935 | /** |
1f91b4cc | 1936 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1937 | * @hsotg: The device state. |
1938 | * @hs_ep: The endpoint the request was on. | |
1939 | * @hs_req: The request to complete. | |
1940 | * @result: The result code (0 => Ok, otherwise errno) | |
1941 | * | |
1942 | * The given request has finished, so call the necessary completion | |
1943 | * if it has one and then look to see if we can start a new request | |
1944 | * on the endpoint. | |
1945 | * | |
1946 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1947 | */ |
1f91b4cc | 1948 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 1949 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1950 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1951 | int result) |
1952 | { | |
5b7d70c6 BD |
1953 | if (!hs_req) { |
1954 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1955 | return; | |
1956 | } | |
1957 | ||
1958 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1959 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1960 | ||
8b9bc460 LM |
1961 | /* |
1962 | * only replace the status if we've not already set an error | |
1963 | * from a previous transaction | |
1964 | */ | |
5b7d70c6 BD |
1965 | |
1966 | if (hs_req->req.status == -EINPROGRESS) | |
1967 | hs_req->req.status = result; | |
1968 | ||
44583fec YL |
1969 | if (using_dma(hsotg)) |
1970 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1971 | ||
1f91b4cc | 1972 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1973 | |
5b7d70c6 BD |
1974 | hs_ep->req = NULL; |
1975 | list_del_init(&hs_req->queue); | |
1976 | ||
8b9bc460 LM |
1977 | /* |
1978 | * call the complete request with the locks off, just in case the | |
1979 | * request tries to queue more work for this endpoint. | |
1980 | */ | |
5b7d70c6 BD |
1981 | |
1982 | if (hs_req->req.complete) { | |
22258f49 | 1983 | spin_unlock(&hsotg->lock); |
304f7e5e | 1984 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1985 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1986 | } |
1987 | ||
540ccba0 VA |
1988 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
1989 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
1990 | return; | |
1991 | ||
8b9bc460 LM |
1992 | /* |
1993 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1994 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1995 | * so be careful when doing this. |
1996 | */ | |
5b7d70c6 | 1997 | |
34c0887f | 1998 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 1999 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2000 | } |
2001 | ||
540ccba0 VA |
2002 | /* |
2003 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2004 | * @hs_ep: The endpoint the request was on. | |
2005 | * | |
2006 | * Get first request from the ep queue, determine descriptor on which complete | |
2007 | * happened. SW based on isoc_chain_num discovers which half of the descriptor | |
2008 | * chain is currently in use by HW, adjusts dma_address and calculates index | |
2009 | * of completed descriptor based on the value of DEPDMA register. Update actual | |
2010 | * length of request, giveback to gadget. | |
2011 | */ | |
2012 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2013 | { | |
2014 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2015 | struct dwc2_hsotg_req *hs_req; | |
2016 | struct usb_request *ureq; | |
2017 | int index; | |
2018 | dma_addr_t dma_addr; | |
2019 | u32 dma_reg; | |
2020 | u32 depdma; | |
2021 | u32 desc_sts; | |
2022 | u32 mask; | |
2023 | ||
2024 | hs_req = get_ep_head(hs_ep); | |
2025 | if (!hs_req) { | |
2026 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2027 | return; | |
2028 | } | |
2029 | ureq = &hs_req->req; | |
2030 | ||
2031 | dma_addr = hs_ep->desc_list_dma; | |
2032 | ||
2033 | /* | |
2034 | * If lower half of descriptor chain is currently use by SW, | |
2035 | * that means higher half is being processed by HW, so shift | |
2036 | * DMA address to higher half of descriptor chain. | |
2037 | */ | |
2038 | if (!hs_ep->isoc_chain_num) | |
2039 | dma_addr += sizeof(struct dwc2_dma_desc) * | |
2040 | (MAX_DMA_DESC_NUM_GENERIC / 2); | |
2041 | ||
2042 | dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index); | |
2043 | depdma = dwc2_readl(hsotg->regs + dma_reg); | |
2044 | ||
2045 | index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1; | |
2046 | desc_sts = hs_ep->desc_list[index].status; | |
2047 | ||
2048 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2049 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2050 | ureq->actual = ureq->length - | |
2051 | ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT); | |
2052 | ||
95d2b037 VA |
2053 | /* Adjust actual length for ISOC Out if length is not align of 4 */ |
2054 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2055 | ureq->actual += 4 - (ureq->length & 0x3); | |
2056 | ||
540ccba0 VA |
2057 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2058 | } | |
2059 | ||
2060 | /* | |
2061 | * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any. | |
2062 | * @hs_ep: The isochronous endpoint to be re-enabled. | |
2063 | * | |
2064 | * If ep has been disabled due to last descriptor servicing (IN endpoint) or | |
2065 | * BNA (OUT endpoint) check the status of other half of descriptor chain that | |
2066 | * was under SW control till HW was busy and restart the endpoint if needed. | |
2067 | */ | |
2068 | static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2069 | { | |
2070 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2071 | u32 depctl; | |
2072 | u32 dma_reg; | |
2073 | u32 ctrl; | |
2074 | u32 dma_addr = hs_ep->desc_list_dma; | |
2075 | unsigned char index = hs_ep->index; | |
2076 | ||
2077 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
2078 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2079 | ||
2080 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
2081 | ||
2082 | /* | |
2083 | * EP was disabled if HW has processed last descriptor or BNA was set. | |
2084 | * So restart ep if SW has prepared new descriptor chain in ep_queue | |
2085 | * routine while HW was busy. | |
2086 | */ | |
2087 | if (!(ctrl & DXEPCTL_EPENA)) { | |
2088 | if (!hs_ep->next_desc) { | |
2089 | dev_dbg(hsotg->dev, "%s: No more ISOC requests\n", | |
2090 | __func__); | |
2091 | return; | |
2092 | } | |
2093 | ||
2094 | dma_addr += sizeof(struct dwc2_dma_desc) * | |
2095 | (MAX_DMA_DESC_NUM_GENERIC / 2) * | |
2096 | hs_ep->isoc_chain_num; | |
2097 | dwc2_writel(dma_addr, hsotg->regs + dma_reg); | |
2098 | ||
2099 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
2100 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
2101 | ||
2102 | /* Switch ISOC descriptor chain number being processed by SW*/ | |
2103 | hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1; | |
2104 | hs_ep->next_desc = 0; | |
2105 | ||
2106 | dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n", | |
2107 | __func__); | |
2108 | } | |
2109 | } | |
2110 | ||
5b7d70c6 | 2111 | /** |
1f91b4cc | 2112 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2113 | * @hsotg: The device state. |
2114 | * @ep_idx: The endpoint index for the data | |
2115 | * @size: The size of data in the fifo, in bytes | |
2116 | * | |
2117 | * The FIFO status shows there is data to read from the FIFO for a given | |
2118 | * endpoint, so sort out whether we need to read the data into a request | |
2119 | * that has been made for that endpoint. | |
2120 | */ | |
1f91b4cc | 2121 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2122 | { |
1f91b4cc FB |
2123 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2124 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 2125 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
2126 | int to_read; |
2127 | int max_req; | |
2128 | int read_ptr; | |
2129 | ||
2130 | if (!hs_req) { | |
95c8bc36 | 2131 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2132 | int ptr; |
2133 | ||
6b448af4 | 2134 | dev_dbg(hsotg->dev, |
9da51974 | 2135 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2136 | __func__, size, ep_idx, epctl); |
2137 | ||
2138 | /* dump the data from the FIFO, we've nothing we can do */ | |
2139 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 2140 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
2141 | |
2142 | return; | |
2143 | } | |
2144 | ||
5b7d70c6 BD |
2145 | to_read = size; |
2146 | read_ptr = hs_req->req.actual; | |
2147 | max_req = hs_req->req.length - read_ptr; | |
2148 | ||
a33e7136 BD |
2149 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2150 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2151 | ||
5b7d70c6 | 2152 | if (to_read > max_req) { |
8b9bc460 LM |
2153 | /* |
2154 | * more data appeared than we where willing | |
5b7d70c6 BD |
2155 | * to deal with in this request. |
2156 | */ | |
2157 | ||
2158 | /* currently we don't deal this */ | |
2159 | WARN_ON_ONCE(1); | |
2160 | } | |
2161 | ||
5b7d70c6 BD |
2162 | hs_ep->total_data += to_read; |
2163 | hs_req->req.actual += to_read; | |
2164 | to_read = DIV_ROUND_UP(to_read, 4); | |
2165 | ||
8b9bc460 LM |
2166 | /* |
2167 | * note, we might over-write the buffer end by 3 bytes depending on | |
2168 | * alignment of the data. | |
2169 | */ | |
1a7ed5be | 2170 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
2171 | } |
2172 | ||
2173 | /** | |
1f91b4cc | 2174 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2175 | * @hsotg: The device instance |
fe0b94ab | 2176 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2177 | * |
2178 | * Generate a zero-length IN packet request for terminating a SETUP | |
2179 | * transaction. | |
2180 | * | |
2181 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2182 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2183 | * the TxFIFO. |
2184 | */ | |
1f91b4cc | 2185 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2186 | { |
c6f5c050 | 2187 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2188 | hsotg->eps_out[0]->dir_in = dir_in; |
2189 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2190 | |
1f91b4cc | 2191 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2192 | } |
2193 | ||
ec1f9d9f | 2194 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2195 | u32 epctl_reg) |
ec1f9d9f RB |
2196 | { |
2197 | u32 ctrl; | |
2198 | ||
2199 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
2200 | if (ctrl & DXEPCTL_EOFRNUM) | |
2201 | ctrl |= DXEPCTL_SETEVENFR; | |
2202 | else | |
2203 | ctrl |= DXEPCTL_SETODDFR; | |
2204 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
2205 | } | |
2206 | ||
aa3e8bc8 VA |
2207 | /* |
2208 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2209 | * @hs_ep - The endpoint on which transfer went | |
2210 | * | |
2211 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2212 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2213 | */ | |
2214 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2215 | { | |
2216 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2217 | unsigned int bytes_rem = 0; | |
2218 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2219 | int i; | |
2220 | u32 status; | |
2221 | ||
2222 | if (!desc) | |
2223 | return -EINVAL; | |
2224 | ||
2225 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2226 | status = desc->status; | |
2227 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2228 | ||
2229 | if (status & DEV_DMA_STS_MASK) | |
2230 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2231 | i, status & DEV_DMA_STS_MASK); | |
2232 | } | |
2233 | ||
2234 | return bytes_rem; | |
2235 | } | |
2236 | ||
5b7d70c6 | 2237 | /** |
1f91b4cc | 2238 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2239 | * @hsotg: The device instance |
2240 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2241 | * |
2242 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2243 | * transfer for an OUT endpoint has been completed, either by a short | |
2244 | * packet or by the finish of a transfer. | |
8b9bc460 | 2245 | */ |
1f91b4cc | 2246 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2247 | { |
95c8bc36 | 2248 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
2249 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2250 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2251 | struct usb_request *req = &hs_req->req; |
9da51974 | 2252 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2253 | int result = 0; |
2254 | ||
2255 | if (!hs_req) { | |
2256 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2257 | return; | |
2258 | } | |
2259 | ||
fe0b94ab MYK |
2260 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2261 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2262 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2263 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2264 | return; |
2265 | } | |
2266 | ||
aa3e8bc8 VA |
2267 | if (using_desc_dma(hsotg)) |
2268 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2269 | ||
5b7d70c6 | 2270 | if (using_dma(hsotg)) { |
9da51974 | 2271 | unsigned int size_done; |
5b7d70c6 | 2272 | |
8b9bc460 LM |
2273 | /* |
2274 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2275 | * is left in the endpoint size register and then working it |
2276 | * out from the amount we loaded for the transfer. | |
2277 | * | |
2278 | * We need to do this as DMA pointers are always 32bit aligned | |
2279 | * so may overshoot/undershoot the transfer. | |
2280 | */ | |
2281 | ||
5b7d70c6 BD |
2282 | size_done = hs_ep->size_loaded - size_left; |
2283 | size_done += hs_ep->last_load; | |
2284 | ||
2285 | req->actual = size_done; | |
2286 | } | |
2287 | ||
a33e7136 BD |
2288 | /* if there is more request to do, schedule new transfer */ |
2289 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2290 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2291 | return; |
2292 | } | |
2293 | ||
5b7d70c6 BD |
2294 | if (req->actual < req->length && req->short_not_ok) { |
2295 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2296 | __func__, req->actual, req->length); | |
2297 | ||
8b9bc460 LM |
2298 | /* |
2299 | * todo - what should we return here? there's no one else | |
2300 | * even bothering to check the status. | |
2301 | */ | |
5b7d70c6 BD |
2302 | } |
2303 | ||
ef750c71 VA |
2304 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2305 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2306 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2307 | /* Move to STATUS IN */ |
1f91b4cc | 2308 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2309 | return; |
5b7d70c6 BD |
2310 | } |
2311 | ||
ec1f9d9f RB |
2312 | /* |
2313 | * Slave mode OUT transfers do not go through XferComplete so | |
2314 | * adjust the ISOC parity here. | |
2315 | */ | |
2316 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2317 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2318 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2319 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2320 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2321 | } |
2322 | ||
1f91b4cc | 2323 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2324 | } |
2325 | ||
5b7d70c6 | 2326 | /** |
1f91b4cc | 2327 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2328 | * @hsotg: The device instance |
2329 | * | |
2330 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2331 | * that requires processing, so find out what is in there and do the | |
2332 | * appropriate read. | |
2333 | * | |
25985edc | 2334 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2335 | * chunks, so if you have x packets received on an endpoint you'll get x |
2336 | * FIFO events delivered, each with a packet's worth of data in it. | |
2337 | * | |
2338 | * When using DMA, we should not be processing events from the RXFIFO | |
2339 | * as the actual data should be sent to the memory directly and we turn | |
2340 | * on the completion interrupts to get notifications of transfer completion. | |
2341 | */ | |
1f91b4cc | 2342 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2343 | { |
95c8bc36 | 2344 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
2345 | u32 epnum, status, size; |
2346 | ||
2347 | WARN_ON(using_dma(hsotg)); | |
2348 | ||
47a1685f DN |
2349 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2350 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2351 | |
47a1685f DN |
2352 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2353 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2354 | |
d7c747c5 | 2355 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2356 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2357 | |
47a1685f DN |
2358 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2359 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2360 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2361 | break; |
2362 | ||
47a1685f | 2363 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2364 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2365 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2366 | |
2367 | if (!using_dma(hsotg)) | |
1f91b4cc | 2368 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2369 | break; |
2370 | ||
47a1685f | 2371 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2372 | dev_dbg(hsotg->dev, |
2373 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2374 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2375 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 2376 | /* |
1f91b4cc | 2377 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2378 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2379 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2380 | */ | |
2381 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2382 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2383 | break; |
2384 | ||
47a1685f | 2385 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2386 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2387 | break; |
2388 | ||
47a1685f | 2389 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2390 | dev_dbg(hsotg->dev, |
2391 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2392 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2393 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 2394 | |
fe0b94ab MYK |
2395 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2396 | ||
1f91b4cc | 2397 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2398 | break; |
2399 | ||
2400 | default: | |
2401 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2402 | __func__, grxstsr); | |
2403 | ||
1f91b4cc | 2404 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2405 | break; |
2406 | } | |
2407 | } | |
2408 | ||
2409 | /** | |
1f91b4cc | 2410 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2411 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2412 | */ |
1f91b4cc | 2413 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2414 | { |
2415 | switch (mps) { | |
2416 | case 64: | |
94cb8fd6 | 2417 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2418 | case 32: |
94cb8fd6 | 2419 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2420 | case 16: |
94cb8fd6 | 2421 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2422 | case 8: |
94cb8fd6 | 2423 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2424 | } |
2425 | ||
2426 | /* bad max packet size, warn and return invalid result */ | |
2427 | WARN_ON(1); | |
2428 | return (u32)-1; | |
2429 | } | |
2430 | ||
2431 | /** | |
1f91b4cc | 2432 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2433 | * @hsotg: The driver state. |
2434 | * @ep: The index number of the endpoint | |
2435 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2436 | * @mc: The multicount value |
5b7d70c6 BD |
2437 | * |
2438 | * Configure the maximum packet size for the given endpoint, updating | |
2439 | * the hardware control registers to reflect this. | |
2440 | */ | |
1f91b4cc | 2441 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2442 | unsigned int ep, unsigned int mps, |
2443 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2444 | { |
1f91b4cc | 2445 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 | 2446 | void __iomem *regs = hsotg->regs; |
5b7d70c6 BD |
2447 | u32 reg; |
2448 | ||
c6f5c050 MYK |
2449 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2450 | if (!hs_ep) | |
2451 | return; | |
2452 | ||
5b7d70c6 | 2453 | if (ep == 0) { |
ee2c40de VM |
2454 | u32 mps_bytes = mps; |
2455 | ||
5b7d70c6 | 2456 | /* EP0 is a special case */ |
ee2c40de VM |
2457 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2458 | if (mps > 3) | |
5b7d70c6 | 2459 | goto bad_mps; |
ee2c40de | 2460 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2461 | hs_ep->mc = 1; |
5b7d70c6 | 2462 | } else { |
ee2c40de | 2463 | if (mps > 1024) |
5b7d70c6 | 2464 | goto bad_mps; |
ee2c40de VM |
2465 | hs_ep->mc = mc; |
2466 | if (mc > 3) | |
4fca54aa | 2467 | goto bad_mps; |
ee2c40de | 2468 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2469 | } |
2470 | ||
c6f5c050 | 2471 | if (dir_in) { |
95c8bc36 | 2472 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 | 2473 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2474 | reg |= mps; |
95c8bc36 | 2475 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 2476 | } else { |
95c8bc36 | 2477 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 2478 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2479 | reg |= mps; |
95c8bc36 | 2480 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 2481 | } |
5b7d70c6 BD |
2482 | |
2483 | return; | |
2484 | ||
2485 | bad_mps: | |
2486 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2487 | } | |
2488 | ||
9c39ddc6 | 2489 | /** |
1f91b4cc | 2490 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2491 | * @hsotg: The driver state |
2492 | * @idx: The index for the endpoint (0..15) | |
2493 | */ | |
1f91b4cc | 2494 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
2495 | { |
2496 | int timeout; | |
2497 | int val; | |
2498 | ||
95c8bc36 AS |
2499 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2500 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
2501 | |
2502 | /* wait until the fifo is flushed */ | |
2503 | timeout = 100; | |
2504 | ||
2505 | while (1) { | |
95c8bc36 | 2506 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 2507 | |
47a1685f | 2508 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
2509 | break; |
2510 | ||
2511 | if (--timeout == 0) { | |
2512 | dev_err(hsotg->dev, | |
2513 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
2514 | __func__, val); | |
e0cbe595 | 2515 | break; |
9c39ddc6 AT |
2516 | } |
2517 | ||
2518 | udelay(1); | |
2519 | } | |
2520 | } | |
5b7d70c6 BD |
2521 | |
2522 | /** | |
1f91b4cc | 2523 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2524 | * @hsotg: The driver state |
2525 | * @hs_ep: The driver endpoint to check. | |
2526 | * | |
2527 | * Check to see if there is a request that has data to send, and if so | |
2528 | * make an attempt to write data into the FIFO. | |
2529 | */ | |
1f91b4cc | 2530 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2531 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2532 | { |
1f91b4cc | 2533 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2534 | |
afcf4169 RB |
2535 | if (!hs_ep->dir_in || !hs_req) { |
2536 | /** | |
2537 | * if request is not enqueued, we disable interrupts | |
2538 | * for endpoints, excepting ep0 | |
2539 | */ | |
2540 | if (hs_ep->index != 0) | |
1f91b4cc | 2541 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2542 | hs_ep->dir_in, 0); |
5b7d70c6 | 2543 | return 0; |
afcf4169 | 2544 | } |
5b7d70c6 BD |
2545 | |
2546 | if (hs_req->req.actual < hs_req->req.length) { | |
2547 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2548 | hs_ep->index); | |
1f91b4cc | 2549 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2550 | } |
2551 | ||
2552 | return 0; | |
2553 | } | |
2554 | ||
2555 | /** | |
1f91b4cc | 2556 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2557 | * @hsotg: The device state. |
2558 | * @hs_ep: The endpoint that has just completed. | |
2559 | * | |
2560 | * An IN transfer has been completed, update the transfer's state and then | |
2561 | * call the relevant completion routines. | |
2562 | */ | |
1f91b4cc | 2563 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2564 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2565 | { |
1f91b4cc | 2566 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 2567 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2568 | int size_left, size_done; |
2569 | ||
2570 | if (!hs_req) { | |
2571 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2572 | return; | |
2573 | } | |
2574 | ||
d3ca0259 | 2575 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2576 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2577 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2578 | |
2579 | /* | |
2580 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2581 | * changed to IN. Change back to complete OUT transfer request | |
2582 | */ | |
2583 | hs_ep->dir_in = 0; | |
2584 | ||
1f91b4cc | 2585 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2586 | if (hsotg->test_mode) { |
2587 | int ret; | |
2588 | ||
1f91b4cc | 2589 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2590 | if (ret < 0) { |
2591 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2592 | hsotg->test_mode); |
1f91b4cc | 2593 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2594 | return; |
2595 | } | |
2596 | } | |
1f91b4cc | 2597 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2598 | return; |
2599 | } | |
2600 | ||
8b9bc460 LM |
2601 | /* |
2602 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2603 | * in the endpoint size register and then working it out from |
2604 | * the amount we loaded for the transfer. | |
2605 | * | |
2606 | * We do this even for DMA, as the transfer may have incremented | |
2607 | * past the end of the buffer (DMA transfers are always 32bit | |
2608 | * aligned). | |
2609 | */ | |
aa3e8bc8 VA |
2610 | if (using_desc_dma(hsotg)) { |
2611 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2612 | if (size_left < 0) | |
2613 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2614 | size_left); | |
2615 | } else { | |
2616 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2617 | } | |
5b7d70c6 BD |
2618 | |
2619 | size_done = hs_ep->size_loaded - size_left; | |
2620 | size_done += hs_ep->last_load; | |
2621 | ||
2622 | if (hs_req->req.actual != size_done) | |
2623 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2624 | __func__, hs_req->req.actual, size_done); | |
2625 | ||
2626 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2627 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2628 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2629 | ||
5b7d70c6 BD |
2630 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2631 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2632 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2633 | return; |
2634 | } | |
2635 | ||
f71b5e25 | 2636 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2637 | if (hs_ep->send_zlp) { |
1f91b4cc | 2638 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2639 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2640 | /* transfer will be completed on next complete interrupt */ |
2641 | return; | |
2642 | } | |
2643 | ||
fe0b94ab MYK |
2644 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2645 | /* Move to STATUS OUT */ | |
1f91b4cc | 2646 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2647 | return; |
2648 | } | |
2649 | ||
1f91b4cc | 2650 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2651 | } |
2652 | ||
32601588 VM |
2653 | /** |
2654 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2655 | * @hsotg: The device state. | |
2656 | * @idx: Index of ep. | |
2657 | * @dir_in: Endpoint direction 1-in 0-out. | |
2658 | * | |
2659 | * Reads for endpoint with given index and direction, by masking | |
2660 | * epint_reg with coresponding mask. | |
2661 | */ | |
2662 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2663 | unsigned int idx, int dir_in) | |
2664 | { | |
2665 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2666 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2667 | u32 ints; | |
2668 | u32 mask; | |
2669 | u32 diepempmsk; | |
2670 | ||
2671 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2672 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2673 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2674 | mask |= DXEPINT_SETUP_RCVD; | |
2675 | ||
2676 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2677 | ints &= mask; | |
2678 | return ints; | |
2679 | } | |
2680 | ||
bd9971f0 VM |
2681 | /** |
2682 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2683 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2684 | * | |
2685 | * This interrupt indicates that the endpoint has been disabled per the | |
2686 | * application's request. | |
2687 | * | |
2688 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2689 | * in case of ISOC completes current request. | |
2690 | * | |
2691 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2692 | * request starts it. | |
2693 | */ | |
2694 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2695 | { | |
2696 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2697 | struct dwc2_hsotg_req *hs_req; | |
2698 | unsigned char idx = hs_ep->index; | |
2699 | int dir_in = hs_ep->dir_in; | |
2700 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2701 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2702 | ||
2703 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2704 | ||
2705 | if (dir_in) { | |
2706 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2707 | ||
2708 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2709 | ||
2710 | if (hs_ep->isochronous) { | |
2711 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2712 | return; | |
2713 | } | |
2714 | ||
2715 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2716 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2717 | ||
2718 | dctl |= DCTL_CGNPINNAK; | |
2719 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2720 | } | |
2721 | return; | |
2722 | } | |
2723 | ||
2724 | if (dctl & DCTL_GOUTNAKSTS) { | |
2725 | dctl |= DCTL_CGOUTNAK; | |
2726 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2727 | } | |
2728 | ||
2729 | if (!hs_ep->isochronous) | |
2730 | return; | |
2731 | ||
2732 | if (list_empty(&hs_ep->queue)) { | |
2733 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2734 | __func__, hs_ep); | |
2735 | return; | |
2736 | } | |
2737 | ||
2738 | do { | |
2739 | hs_req = get_ep_head(hs_ep); | |
2740 | if (hs_req) | |
2741 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2742 | -ENODATA); | |
2743 | dwc2_gadget_incr_frame_num(hs_ep); | |
2744 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2745 | ||
2746 | dwc2_gadget_start_next_request(hs_ep); | |
2747 | } | |
2748 | ||
5321922c VM |
2749 | /** |
2750 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2751 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2752 | * | |
2753 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2754 | * first out token received from host while corresponding EP is disabled. | |
2755 | * | |
2756 | * Device does not know initial frame in which out token will come. For this | |
2757 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2758 | * getting this interrupt SW starts calculation for next transfer frame. | |
2759 | */ | |
2760 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2761 | { | |
2762 | struct dwc2_hsotg *hsotg = ep->parent; | |
2763 | int dir_in = ep->dir_in; | |
2764 | u32 doepmsk; | |
540ccba0 | 2765 | u32 tmp; |
5321922c VM |
2766 | |
2767 | if (dir_in || !ep->isochronous) | |
2768 | return; | |
2769 | ||
540ccba0 VA |
2770 | /* |
2771 | * Store frame in which irq was asserted here, as | |
2772 | * it can change while completing request below. | |
2773 | */ | |
2774 | tmp = dwc2_hsotg_read_frameno(hsotg); | |
2775 | ||
5321922c VM |
2776 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); |
2777 | ||
540ccba0 VA |
2778 | if (using_desc_dma(hsotg)) { |
2779 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2780 | /* Start first ISO Out */ | |
2781 | ep->target_frame = tmp; | |
2782 | dwc2_gadget_start_isoc_ddma(ep); | |
2783 | } | |
2784 | return; | |
2785 | } | |
2786 | ||
5321922c VM |
2787 | if (ep->interval > 1 && |
2788 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2789 | u32 dsts; | |
2790 | u32 ctrl; | |
2791 | ||
2792 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2793 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2794 | dwc2_gadget_incr_frame_num(ep); | |
2795 | ||
2796 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2797 | if (ep->target_frame & 0x1) | |
2798 | ctrl |= DXEPCTL_SETODDFR; | |
2799 | else | |
2800 | ctrl |= DXEPCTL_SETEVENFR; | |
2801 | ||
2802 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2803 | } | |
2804 | ||
2805 | dwc2_gadget_start_next_request(ep); | |
2806 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2807 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2808 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2809 | } | |
2810 | ||
2811 | /** | |
38beaec6 JY |
2812 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2813 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2814 | * | |
2815 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2816 | * first IN token received from host while corresponding EP is disabled. | |
2817 | * | |
2818 | * Device does not know when first one token will arrive from host. On first | |
2819 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2820 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2821 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2822 | * interrupt to obtain frame in which token has come and then based on the | |
2823 | * interval calculates next frame for transfer. | |
2824 | */ | |
5321922c VM |
2825 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2826 | { | |
2827 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2828 | int dir_in = hs_ep->dir_in; | |
2829 | ||
2830 | if (!dir_in || !hs_ep->isochronous) | |
2831 | return; | |
2832 | ||
2833 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2834 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
540ccba0 VA |
2835 | |
2836 | if (using_desc_dma(hsotg)) { | |
2837 | dwc2_gadget_start_isoc_ddma(hs_ep); | |
2838 | return; | |
2839 | } | |
2840 | ||
5321922c VM |
2841 | if (hs_ep->interval > 1) { |
2842 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2843 | DIEPCTL(hs_ep->index)); | |
2844 | if (hs_ep->target_frame & 0x1) | |
2845 | ctrl |= DXEPCTL_SETODDFR; | |
2846 | else | |
2847 | ctrl |= DXEPCTL_SETEVENFR; | |
2848 | ||
2849 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2850 | } | |
2851 | ||
2852 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2853 | get_ep_head(hs_ep), 0); | |
2854 | } | |
2855 | ||
2856 | dwc2_gadget_incr_frame_num(hs_ep); | |
2857 | } | |
2858 | ||
5b7d70c6 | 2859 | /** |
1f91b4cc | 2860 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2861 | * @hsotg: The driver state |
2862 | * @idx: The index for the endpoint (0..15) | |
2863 | * @dir_in: Set if this is an IN endpoint | |
2864 | * | |
2865 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2866 | */ |
1f91b4cc | 2867 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2868 | int dir_in) |
5b7d70c6 | 2869 | { |
1f91b4cc | 2870 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2871 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2872 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2873 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2874 | u32 ints; |
1479e841 | 2875 | u32 ctrl; |
5b7d70c6 | 2876 | |
32601588 | 2877 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2878 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2879 | |
a3395f0d | 2880 | /* Clear endpoint interrupts */ |
95c8bc36 | 2881 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2882 | |
c6f5c050 MYK |
2883 | if (!hs_ep) { |
2884 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2885 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2886 | return; |
2887 | } | |
2888 | ||
5b7d70c6 BD |
2889 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2890 | __func__, idx, dir_in ? "in" : "out", ints); | |
2891 | ||
b787d755 MYK |
2892 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2893 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2894 | ints &= ~DXEPINT_XFERCOMPL; | |
2895 | ||
f0afdb42 VA |
2896 | /* |
2897 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2898 | * stage and xfercomplete was generated without SETUP phase done | |
2899 | * interrupt. SW should parse received setup packet only after host's | |
2900 | * exit from setup phase of control transfer. | |
2901 | */ | |
2902 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2903 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2904 | ints &= ~DXEPINT_XFERCOMPL; | |
2905 | ||
837e9f00 | 2906 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2907 | dev_dbg(hsotg->dev, |
47a1685f | 2908 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2909 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2910 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2911 | |
540ccba0 VA |
2912 | /* In DDMA handle isochronous requests separately */ |
2913 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
2914 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
2915 | /* Try to start next isoc request */ | |
2916 | dwc2_gadget_start_next_isoc_ddma(hs_ep); | |
2917 | } else if (dir_in) { | |
2918 | /* | |
2919 | * We get OutDone from the FIFO, so we only | |
2920 | * need to look at completing IN requests here | |
2921 | * if operating slave mode | |
2922 | */ | |
837e9f00 VM |
2923 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2924 | dwc2_gadget_incr_frame_num(hs_ep); | |
2925 | ||
1f91b4cc | 2926 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2927 | if (ints & DXEPINT_NAKINTRPT) |
2928 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2929 | |
c9a64ea8 | 2930 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2931 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2932 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2933 | /* |
2934 | * We're using DMA, we need to fire an OutDone here | |
2935 | * as we ignore the RXFIFO. | |
2936 | */ | |
837e9f00 VM |
2937 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2938 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2939 | |
1f91b4cc | 2940 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2941 | } |
5b7d70c6 BD |
2942 | } |
2943 | ||
bd9971f0 VM |
2944 | if (ints & DXEPINT_EPDISBLD) |
2945 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2946 | |
5321922c VM |
2947 | if (ints & DXEPINT_OUTTKNEPDIS) |
2948 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2949 | ||
2950 | if (ints & DXEPINT_NAKINTRPT) | |
2951 | dwc2_gadget_handle_nak(hs_ep); | |
2952 | ||
47a1685f | 2953 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2954 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2955 | |
47a1685f | 2956 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2957 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2958 | ||
2959 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2960 | /* |
2961 | * this is the notification we've received a | |
5b7d70c6 BD |
2962 | * setup packet. In non-DMA mode we'd get this |
2963 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2964 | * the setup here. |
2965 | */ | |
5b7d70c6 BD |
2966 | |
2967 | if (dir_in) | |
2968 | WARN_ON_ONCE(1); | |
2969 | else | |
1f91b4cc | 2970 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2971 | } |
5b7d70c6 BD |
2972 | } |
2973 | ||
ef750c71 | 2974 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
2975 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
2976 | ||
ef750c71 VA |
2977 | /* Move to STATUS IN for DDMA */ |
2978 | if (using_desc_dma(hsotg)) | |
2979 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
2980 | } | |
2981 | ||
47a1685f | 2982 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2983 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2984 | |
540ccba0 VA |
2985 | if (ints & DXEPINT_BNAINTR) { |
2986 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
2987 | ||
2988 | /* | |
2989 | * Try to start next isoc request, if any. | |
2990 | * Sometimes the endpoint remains enabled after BNA interrupt | |
2991 | * assertion, which is not expected, hence we can enter here | |
2992 | * couple of times. | |
2993 | */ | |
2994 | if (hs_ep->isochronous) | |
2995 | dwc2_gadget_start_next_isoc_ddma(hs_ep); | |
2996 | } | |
2997 | ||
1479e841 | 2998 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2999 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3000 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3001 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3002 | __func__, idx); | |
5b7d70c6 BD |
3003 | } |
3004 | ||
3005 | /* this probably means something bad is happening */ | |
26ddef5d | 3006 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3007 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3008 | __func__, idx); | |
5b7d70c6 | 3009 | } |
10aebc77 BD |
3010 | |
3011 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3012 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3013 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3014 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3015 | __func__, idx); | |
70fa030f | 3016 | if (!using_dma(hsotg)) |
1f91b4cc | 3017 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3018 | } |
5b7d70c6 | 3019 | } |
5b7d70c6 BD |
3020 | } |
3021 | ||
3022 | /** | |
1f91b4cc | 3023 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3024 | * @hsotg: The device state. |
3025 | * | |
3026 | * Handle updating the device settings after the enumeration phase has | |
3027 | * been completed. | |
8b9bc460 | 3028 | */ |
1f91b4cc | 3029 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3030 | { |
95c8bc36 | 3031 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 3032 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3033 | |
8b9bc460 LM |
3034 | /* |
3035 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3036 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3037 | * we connected at. |
3038 | */ | |
5b7d70c6 BD |
3039 | |
3040 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3041 | ||
8b9bc460 LM |
3042 | /* |
3043 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3044 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3045 | * not advertise a 64byte MPS on EP0. |
3046 | */ | |
5b7d70c6 BD |
3047 | |
3048 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3049 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3050 | case DSTS_ENUMSPD_FS: |
3051 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3052 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3053 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3054 | ep_mps = 1023; |
5b7d70c6 BD |
3055 | break; |
3056 | ||
47a1685f | 3057 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3058 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3059 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3060 | ep_mps = 1024; |
5b7d70c6 BD |
3061 | break; |
3062 | ||
47a1685f | 3063 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3064 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3065 | ep0_mps = 8; |
3066 | ep_mps = 8; | |
8b9bc460 LM |
3067 | /* |
3068 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3069 | * moment, and the documentation seems to imply that it isn't |
3070 | * supported by the PHYs on some of the devices. | |
3071 | */ | |
3072 | break; | |
3073 | } | |
e538dfda MN |
3074 | dev_info(hsotg->dev, "new device is %s\n", |
3075 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3076 | |
8b9bc460 LM |
3077 | /* |
3078 | * we should now know the maximum packet size for an | |
3079 | * endpoint, so set the endpoints to a default value. | |
3080 | */ | |
5b7d70c6 BD |
3081 | |
3082 | if (ep0_mps) { | |
3083 | int i; | |
c6f5c050 | 3084 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3085 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3086 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3087 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3088 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3089 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3090 | 0, 1); | |
c6f5c050 | 3091 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3092 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3093 | 0, 0); | |
c6f5c050 | 3094 | } |
5b7d70c6 BD |
3095 | } |
3096 | ||
3097 | /* ensure after enumeration our EP0 is active */ | |
3098 | ||
1f91b4cc | 3099 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3100 | |
3101 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3102 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3103 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
3104 | } |
3105 | ||
3106 | /** | |
3107 | * kill_all_requests - remove all requests from the endpoint's queue | |
3108 | * @hsotg: The device state. | |
3109 | * @ep: The endpoint the requests may be on. | |
3110 | * @result: The result code to use. | |
5b7d70c6 BD |
3111 | * |
3112 | * Go through the requests on the given endpoint and mark them | |
3113 | * completed with the given result code. | |
3114 | */ | |
941fcce4 | 3115 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3116 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3117 | int result) |
5b7d70c6 | 3118 | { |
1f91b4cc | 3119 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3120 | unsigned int size; |
5b7d70c6 | 3121 | |
6b448af4 | 3122 | ep->req = NULL; |
5b7d70c6 | 3123 | |
6b448af4 | 3124 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3125 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3126 | result); |
6b448af4 | 3127 | |
b203d0a2 RB |
3128 | if (!hsotg->dedicated_fifos) |
3129 | return; | |
ad674a15 | 3130 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3131 | if (size < ep->fifo_size) |
1f91b4cc | 3132 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3133 | } |
3134 | ||
5b7d70c6 | 3135 | /** |
1f91b4cc | 3136 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3137 | * @hsotg: The device state. |
3138 | * | |
5e891342 LM |
3139 | * The device has been disconnected. Remove all current |
3140 | * transactions and signal the gadget driver that this | |
3141 | * has happened. | |
8b9bc460 | 3142 | */ |
1f91b4cc | 3143 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3144 | { |
9da51974 | 3145 | unsigned int ep; |
5b7d70c6 | 3146 | |
4ace06e8 MS |
3147 | if (!hsotg->connected) |
3148 | return; | |
3149 | ||
3150 | hsotg->connected = 0; | |
9e14d0a5 | 3151 | hsotg->test_mode = 0; |
c6f5c050 MYK |
3152 | |
3153 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
3154 | if (hsotg->eps_in[ep]) | |
3155 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
9da51974 | 3156 | -ESHUTDOWN); |
c6f5c050 MYK |
3157 | if (hsotg->eps_out[ep]) |
3158 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
9da51974 | 3159 | -ESHUTDOWN); |
c6f5c050 | 3160 | } |
5b7d70c6 BD |
3161 | |
3162 | call_gadget(hsotg, disconnect); | |
065d3931 | 3163 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3164 | |
3165 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3166 | } |
3167 | ||
3168 | /** | |
1f91b4cc | 3169 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3170 | * @hsotg: The device state: |
3171 | * @periodic: True if this is a periodic FIFO interrupt | |
3172 | */ | |
1f91b4cc | 3173 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3174 | { |
1f91b4cc | 3175 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3176 | int epno, ret; |
3177 | ||
3178 | /* look through for any more data to transmit */ | |
b3f489b2 | 3179 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3180 | ep = index_to_ep(hsotg, epno, 1); |
3181 | ||
3182 | if (!ep) | |
3183 | continue; | |
5b7d70c6 BD |
3184 | |
3185 | if (!ep->dir_in) | |
3186 | continue; | |
3187 | ||
3188 | if ((periodic && !ep->periodic) || | |
3189 | (!periodic && ep->periodic)) | |
3190 | continue; | |
3191 | ||
1f91b4cc | 3192 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3193 | if (ret < 0) |
3194 | break; | |
3195 | } | |
3196 | } | |
3197 | ||
5b7d70c6 | 3198 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3199 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3200 | GINTSTS_PTXFEMP | \ | |
3201 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3202 | |
8b9bc460 | 3203 | /** |
1f91b4cc | 3204 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
3205 | * @hsotg: The device state |
3206 | * | |
3207 | * Issue a soft reset to the core, and await the core finishing it. | |
3208 | */ | |
1f91b4cc | 3209 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3210 | bool is_usb_reset) |
308d734e | 3211 | { |
1ee6903b | 3212 | u32 intmsk; |
643cc4de | 3213 | u32 val; |
ecd9a7ad | 3214 | u32 usbcfg; |
79c3b5bb | 3215 | u32 dcfg = 0; |
643cc4de | 3216 | |
5390d438 MYK |
3217 | /* Kill any ep0 requests as controller will be reinitialized */ |
3218 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3219 | ||
643cc4de | 3220 | if (!is_usb_reset) |
6e6360b6 | 3221 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3222 | return; |
308d734e LM |
3223 | |
3224 | /* | |
3225 | * we must now enable ep0 ready for host detection and then | |
3226 | * set configuration. | |
3227 | */ | |
3228 | ||
ecd9a7ad PR |
3229 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3230 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3231 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 3232 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 3233 | |
79c3b5bb | 3234 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
38e9002b VM |
3235 | (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
3236 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { | |
79c3b5bb VA |
3237 | /* FS/LS Dedicated Transceiver Interface */ |
3238 | usbcfg |= GUSBCFG_PHYSEL; | |
3239 | } else { | |
3240 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
3241 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; | |
3242 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | | |
3243 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
3244 | } | |
ecd9a7ad | 3245 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
308d734e | 3246 | |
1f91b4cc | 3247 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3248 | |
643cc4de GH |
3249 | if (!is_usb_reset) |
3250 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 3251 | |
79c3b5bb | 3252 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3253 | |
3254 | switch (hsotg->params.speed) { | |
3255 | case DWC2_SPEED_PARAM_LOW: | |
3256 | dcfg |= DCFG_DEVSPD_LS; | |
3257 | break; | |
3258 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3259 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3260 | dcfg |= DCFG_DEVSPD_FS48; | |
3261 | else | |
3262 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3263 | break; |
3264 | default: | |
79c3b5bb VA |
3265 | dcfg |= DCFG_DEVSPD_HS; |
3266 | } | |
38e9002b | 3267 | |
79c3b5bb | 3268 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
308d734e LM |
3269 | |
3270 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 3271 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
3272 | |
3273 | /* Clear any pending interrupts */ | |
95c8bc36 | 3274 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 3275 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3276 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3277 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3278 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
f4736701 VA |
3279 | GINTSTS_USBSUSP | GINTSTS_WKUPINT; |
3280 | ||
3281 | if (!using_desc_dma(hsotg)) | |
3282 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3283 | |
95832c00 | 3284 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3285 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3286 | ||
3287 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e | 3288 | |
a5c18f11 | 3289 | if (using_dma(hsotg)) { |
95c8bc36 AS |
3290 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
3291 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
3292 | hsotg->regs + GAHBCFG); | |
a5c18f11 VA |
3293 | |
3294 | /* Set DDMA mode support in the core if needed */ | |
3295 | if (using_desc_dma(hsotg)) | |
3296 | __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN); | |
3297 | ||
3298 | } else { | |
95c8bc36 AS |
3299 | dwc2_writel(((hsotg->dedicated_fifos) ? |
3300 | (GAHBCFG_NP_TXF_EMP_LVL | | |
3301 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
3302 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
a5c18f11 | 3303 | } |
308d734e LM |
3304 | |
3305 | /* | |
8acc8296 RB |
3306 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3307 | * when we have no data to transfer. Otherwise we get being flooded by | |
3308 | * interrupts. | |
308d734e LM |
3309 | */ |
3310 | ||
95c8bc36 | 3311 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3312 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3313 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3314 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 3315 | hsotg->regs + DIEPMSK); |
308d734e LM |
3316 | |
3317 | /* | |
3318 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3319 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3320 | */ |
9d9a6b07 VA |
3321 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
3322 | DOEPMSK_STSPHSERCVDMSK) : 0) | | |
47a1685f | 3323 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3324 | DOEPMSK_SETUPMSK, |
47a1685f | 3325 | hsotg->regs + DOEPMSK); |
308d734e | 3326 | |
ec01f0b2 VA |
3327 | /* Enable BNA interrupt for DDMA */ |
3328 | if (using_desc_dma(hsotg)) | |
3329 | __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); | |
3330 | ||
95c8bc36 | 3331 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
3332 | |
3333 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3334 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3335 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3336 | |
3337 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3338 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3339 | |
3340 | /* | |
3341 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3342 | * the data. In DMA mode, we get events from the FIFO but also | |
3343 | * things we cannot process, so do not use it. | |
3344 | */ | |
3345 | if (!using_dma(hsotg)) | |
1f91b4cc | 3346 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3347 | |
3348 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3349 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3350 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3351 | |
643cc4de GH |
3352 | if (!is_usb_reset) { |
3353 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
3354 | udelay(10); /* see openiboot */ | |
3355 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
3356 | } | |
308d734e | 3357 | |
95c8bc36 | 3358 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
3359 | |
3360 | /* | |
94cb8fd6 | 3361 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3362 | * writing to the EPCTL register.. |
3363 | */ | |
3364 | ||
3365 | /* set to read 1 8byte packet */ | |
95c8bc36 | 3366 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 3367 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 3368 | |
95c8bc36 | 3369 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3370 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3371 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 3372 | hsotg->regs + DOEPCTL0); |
308d734e LM |
3373 | |
3374 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 3375 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 3376 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 3377 | |
1f91b4cc | 3378 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
3379 | |
3380 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3381 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3382 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3383 | |
3384 | /* clear global NAKs */ | |
643cc4de GH |
3385 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3386 | if (!is_usb_reset) | |
3387 | val |= DCTL_SFTDISCON; | |
3388 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
3389 | |
3390 | /* must be at-least 3ms to allow bus to see disconnect */ | |
3391 | mdelay(3); | |
3392 | ||
065d3931 | 3393 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
3394 | } |
3395 | ||
1f91b4cc | 3396 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3397 | { |
3398 | /* set the soft-disconnect bit */ | |
3399 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
3400 | } | |
ac3c81f3 | 3401 | |
1f91b4cc | 3402 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3403 | { |
308d734e | 3404 | /* remove the soft-disconnect and let's go */ |
47a1685f | 3405 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
3406 | } |
3407 | ||
381fc8f8 VM |
3408 | /** |
3409 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3410 | * @hsotg: The device state: | |
3411 | * | |
3412 | * This interrupt indicates one of the following conditions occurred while | |
3413 | * transmitting an ISOC transaction. | |
3414 | * - Corrupted IN Token for ISOC EP. | |
3415 | * - Packet not complete in FIFO. | |
3416 | * | |
3417 | * The following actions will be taken: | |
3418 | * - Determine the EP | |
3419 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3420 | */ | |
3421 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3422 | { | |
3423 | struct dwc2_hsotg_ep *hs_ep; | |
3424 | u32 epctrl; | |
3425 | u32 idx; | |
3426 | ||
3427 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3428 | ||
3429 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3430 | hs_ep = hsotg->eps_in[idx]; | |
3431 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); | |
3432 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
3433 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
3434 | epctrl |= DXEPCTL_SNAK; | |
3435 | epctrl |= DXEPCTL_EPDIS; | |
3436 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | /* Clear interrupt */ | |
3441 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
3442 | } | |
3443 | ||
3444 | /** | |
3445 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3446 | * @hsotg: The device state: | |
3447 | * | |
3448 | * This interrupt indicates one of the following conditions occurred while | |
3449 | * transmitting an ISOC transaction. | |
3450 | * - Corrupted OUT Token for ISOC EP. | |
3451 | * - Packet not complete in FIFO. | |
3452 | * | |
3453 | * The following actions will be taken: | |
3454 | * - Determine the EP | |
3455 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3456 | */ | |
3457 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3458 | { | |
3459 | u32 gintsts; | |
3460 | u32 gintmsk; | |
3461 | u32 epctrl; | |
3462 | struct dwc2_hsotg_ep *hs_ep; | |
3463 | int idx; | |
3464 | ||
3465 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3466 | ||
3467 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3468 | hs_ep = hsotg->eps_out[idx]; | |
3469 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
3470 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
3471 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
3472 | /* Unmask GOUTNAKEFF interrupt */ | |
3473 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3474 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
3475 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3476 | ||
3477 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
3478 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) | |
3479 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
3480 | } | |
3481 | } | |
3482 | ||
3483 | /* Clear interrupt */ | |
3484 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
3485 | } | |
3486 | ||
5b7d70c6 | 3487 | /** |
1f91b4cc | 3488 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3489 | * @irq: The IRQ number triggered |
3490 | * @pw: The pw value when registered the handler. | |
3491 | */ | |
1f91b4cc | 3492 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3493 | { |
941fcce4 | 3494 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3495 | int retry_count = 8; |
3496 | u32 gintsts; | |
3497 | u32 gintmsk; | |
3498 | ||
ee3de8d7 VM |
3499 | if (!dwc2_is_device_mode(hsotg)) |
3500 | return IRQ_NONE; | |
3501 | ||
5ad1d316 | 3502 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3503 | irq_retry: |
95c8bc36 AS |
3504 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
3505 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
3506 | |
3507 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3508 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3509 | ||
3510 | gintsts &= gintmsk; | |
3511 | ||
8fc37b82 MYK |
3512 | if (gintsts & GINTSTS_RESETDET) { |
3513 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3514 | ||
3515 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
3516 | ||
3517 | /* This event must be used only if controller is suspended */ | |
3518 | if (hsotg->lx_state == DWC2_L2) { | |
3519 | dwc2_exit_hibernation(hsotg, true); | |
3520 | hsotg->lx_state = DWC2_L0; | |
3521 | } | |
3522 | } | |
3523 | ||
3524 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
8fc37b82 MYK |
3525 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
3526 | u32 connected = hsotg->connected; | |
3527 | ||
3528 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3529 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
3530 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
3531 | ||
3532 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
3533 | ||
3534 | /* Report disconnection if it is not already done. */ | |
3535 | dwc2_hsotg_disconnect(hsotg); | |
3536 | ||
307bc11f MH |
3537 | /* Reset device address to zero */ |
3538 | __bic32(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); | |
3539 | ||
8fc37b82 MYK |
3540 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3541 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3542 | } | |
3543 | ||
47a1685f | 3544 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 3545 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 3546 | |
1f91b4cc | 3547 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3548 | } |
3549 | ||
47a1685f | 3550 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
3551 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
3552 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 3553 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3554 | int ep; |
3555 | ||
7e804650 | 3556 | daint &= daintmsk; |
47a1685f DN |
3557 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3558 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3559 | |
5b7d70c6 BD |
3560 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3561 | ||
cec87f1d MYK |
3562 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3563 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3564 | if (daint_out & 1) |
1f91b4cc | 3565 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3566 | } |
3567 | ||
cec87f1d MYK |
3568 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3569 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3570 | if (daint_in & 1) |
1f91b4cc | 3571 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3572 | } |
5b7d70c6 BD |
3573 | } |
3574 | ||
5b7d70c6 BD |
3575 | /* check both FIFOs */ |
3576 | ||
47a1685f | 3577 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3578 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3579 | ||
8b9bc460 LM |
3580 | /* |
3581 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3582 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3583 | * it needs re-enabling |
3584 | */ | |
5b7d70c6 | 3585 | |
1f91b4cc FB |
3586 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3587 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3588 | } |
3589 | ||
47a1685f | 3590 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3591 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3592 | ||
94cb8fd6 | 3593 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3594 | |
1f91b4cc FB |
3595 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3596 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3597 | } |
3598 | ||
47a1685f | 3599 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3600 | /* |
3601 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3602 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3603 | * set. |
3604 | */ | |
5b7d70c6 | 3605 | |
1f91b4cc | 3606 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3607 | } |
3608 | ||
47a1685f | 3609 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3610 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 3611 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
3612 | } |
3613 | ||
8b9bc460 LM |
3614 | /* |
3615 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3616 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3617 | * the occurrence. |
3618 | */ | |
5b7d70c6 | 3619 | |
47a1685f | 3620 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3621 | u8 idx; |
3622 | u32 epctrl; | |
3623 | u32 gintmsk; | |
3624 | struct dwc2_hsotg_ep *hs_ep; | |
3625 | ||
3626 | /* Mask this interrupt */ | |
3627 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3628 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
3629 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3630 | ||
3631 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
3632 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3633 | hs_ep = hsotg->eps_out[idx]; | |
3634 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
3635 | ||
3636 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
3637 | epctrl |= DXEPCTL_SNAK; | |
3638 | epctrl |= DXEPCTL_EPDIS; | |
3639 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
3640 | } | |
3641 | } | |
a3395f0d | 3642 | |
837e9f00 | 3643 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3644 | } |
3645 | ||
47a1685f | 3646 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3647 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3648 | ||
3be99cd0 | 3649 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3650 | |
1f91b4cc | 3651 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3652 | } |
3653 | ||
381fc8f8 VM |
3654 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3655 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3656 | |
381fc8f8 VM |
3657 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3658 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3659 | |
8b9bc460 LM |
3660 | /* |
3661 | * if we've had fifo events, we should try and go around the | |
3662 | * loop again to see if there's any point in returning yet. | |
3663 | */ | |
5b7d70c6 BD |
3664 | |
3665 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3666 | goto irq_retry; |
5b7d70c6 | 3667 | |
5ad1d316 LM |
3668 | spin_unlock(&hsotg->lock); |
3669 | ||
5b7d70c6 BD |
3670 | return IRQ_HANDLED; |
3671 | } | |
3672 | ||
a4f82771 VA |
3673 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3674 | u32 bit, u32 timeout) | |
3675 | { | |
3676 | u32 i; | |
3677 | ||
3678 | for (i = 0; i < timeout; i++) { | |
3679 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3680 | return 0; | |
3681 | udelay(1); | |
3682 | } | |
3683 | ||
3684 | return -ETIMEDOUT; | |
3685 | } | |
3686 | ||
3687 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3688 | struct dwc2_hsotg_ep *hs_ep) | |
3689 | { | |
3690 | u32 epctrl_reg; | |
3691 | u32 epint_reg; | |
3692 | ||
3693 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3694 | DOEPCTL(hs_ep->index); | |
3695 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3696 | DOEPINT(hs_ep->index); | |
3697 | ||
3698 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3699 | hs_ep->name); | |
3700 | ||
3701 | if (hs_ep->dir_in) { | |
3702 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
3703 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3704 | /* Wait for Nak effect */ | |
3705 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3706 | DXEPINT_INEPNAKEFF, 100)) | |
3707 | dev_warn(hsotg->dev, | |
3708 | "%s: timeout DIEPINT.NAKEFF\n", | |
3709 | __func__); | |
3710 | } else { | |
3711 | __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK); | |
3712 | /* Wait for Nak effect */ | |
3713 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3714 | GINTSTS_GINNAKEFF, 100)) | |
3715 | dev_warn(hsotg->dev, | |
3716 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3717 | __func__); | |
3718 | } | |
3719 | } else { | |
3720 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) | |
3721 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
3722 | ||
3723 | /* Wait for global nak to take effect */ | |
3724 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3725 | GINTSTS_GOUTNAKEFF, 100)) | |
3726 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3727 | __func__); | |
3728 | } | |
3729 | ||
3730 | /* Disable ep */ | |
3731 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3732 | ||
3733 | /* Wait for ep to be disabled */ | |
3734 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3735 | dev_warn(hsotg->dev, | |
3736 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3737 | ||
3738 | /* Clear EPDISBLD interrupt */ | |
3739 | __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); | |
3740 | ||
3741 | if (hs_ep->dir_in) { | |
3742 | unsigned short fifo_index; | |
3743 | ||
3744 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3745 | fifo_index = hs_ep->fifo_index; | |
3746 | else | |
3747 | fifo_index = 0; | |
3748 | ||
3749 | /* Flush TX FIFO */ | |
3750 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3751 | ||
3752 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3753 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
3754 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); | |
3755 | ||
3756 | } else { | |
3757 | /* Remove global NAKs */ | |
3758 | __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK); | |
3759 | } | |
3760 | } | |
3761 | ||
5b7d70c6 | 3762 | /** |
1f91b4cc | 3763 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3764 | * @ep: The USB endpint to configure |
3765 | * @desc: The USB endpoint descriptor to configure with. | |
3766 | * | |
3767 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3768 | */ |
1f91b4cc | 3769 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3770 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3771 | { |
1f91b4cc | 3772 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3773 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3774 | unsigned long flags; |
ca4c55ad | 3775 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3776 | u32 epctrl_reg; |
3777 | u32 epctrl; | |
3778 | u32 mps; | |
ee2c40de | 3779 | u32 mc; |
837e9f00 | 3780 | u32 mask; |
ca4c55ad MYK |
3781 | unsigned int dir_in; |
3782 | unsigned int i, val, size; | |
19c190f9 | 3783 | int ret = 0; |
5b7d70c6 BD |
3784 | |
3785 | dev_dbg(hsotg->dev, | |
3786 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3787 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3788 | desc->wMaxPacketSize, desc->bInterval); | |
3789 | ||
3790 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3791 | if (index == 0) { |
3792 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3793 | return -EINVAL; | |
3794 | } | |
5b7d70c6 BD |
3795 | |
3796 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3797 | if (dir_in != hs_ep->dir_in) { | |
3798 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3799 | return -EINVAL; | |
3800 | } | |
3801 | ||
29cc8897 | 3802 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3803 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3804 | |
1f91b4cc | 3805 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3806 | |
94cb8fd6 | 3807 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 3808 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3809 | |
3810 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3811 | __func__, epctrl, epctrl_reg); | |
3812 | ||
5f54c54b | 3813 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3814 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3815 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3816 | MAX_DMA_DESC_NUM_GENERIC * |
3817 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3818 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3819 | if (!hs_ep->desc_list) { |
3820 | ret = -ENOMEM; | |
3821 | goto error2; | |
3822 | } | |
3823 | } | |
3824 | ||
22258f49 | 3825 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3826 | |
47a1685f DN |
3827 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3828 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3829 | |
8b9bc460 LM |
3830 | /* |
3831 | * mark the endpoint as active, otherwise the core may ignore | |
3832 | * transactions entirely for this endpoint | |
3833 | */ | |
47a1685f | 3834 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3835 | |
5b7d70c6 | 3836 | /* update the endpoint state */ |
ee2c40de | 3837 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3838 | |
3839 | /* default, set to non-periodic */ | |
1479e841 | 3840 | hs_ep->isochronous = 0; |
5b7d70c6 | 3841 | hs_ep->periodic = 0; |
a18ed7b0 | 3842 | hs_ep->halted = 0; |
1479e841 | 3843 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3844 | |
5b7d70c6 BD |
3845 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
3846 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
3847 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3848 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3849 | hs_ep->isochronous = 1; |
142bd33f | 3850 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3851 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 VA |
3852 | hs_ep->isoc_chain_num = 0; |
3853 | hs_ep->next_desc = 0; | |
837e9f00 | 3854 | if (dir_in) { |
1479e841 | 3855 | hs_ep->periodic = 1; |
837e9f00 VM |
3856 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3857 | mask |= DIEPMSK_NAKMSK; | |
3858 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3859 | } else { | |
3860 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3861 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3862 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3863 | } | |
1479e841 | 3864 | break; |
5b7d70c6 BD |
3865 | |
3866 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3867 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3868 | break; |
3869 | ||
3870 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3871 | if (dir_in) |
5b7d70c6 | 3872 | hs_ep->periodic = 1; |
5b7d70c6 | 3873 | |
142bd33f VM |
3874 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3875 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3876 | ||
47a1685f | 3877 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3878 | break; |
3879 | ||
3880 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3881 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3882 | break; |
3883 | } | |
3884 | ||
8b9bc460 LM |
3885 | /* |
3886 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3887 | * a unique tx-fifo even if it is non-periodic. |
3888 | */ | |
21f3bb52 | 3889 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3890 | u32 fifo_index = 0; |
3891 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
3892 | |
3893 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 3894 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 3895 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 3896 | continue; |
95c8bc36 | 3897 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
9da51974 | 3898 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
3899 | if (val < size) |
3900 | continue; | |
ca4c55ad MYK |
3901 | /* Search for smallest acceptable fifo */ |
3902 | if (val < fifo_size) { | |
3903 | fifo_size = val; | |
3904 | fifo_index = i; | |
3905 | } | |
b203d0a2 | 3906 | } |
ca4c55ad | 3907 | if (!fifo_index) { |
5f2196bd MYK |
3908 | dev_err(hsotg->dev, |
3909 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 3910 | ret = -ENOMEM; |
5f54c54b | 3911 | goto error1; |
b585a48b | 3912 | } |
ca4c55ad MYK |
3913 | hsotg->fifo_map |= 1 << fifo_index; |
3914 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3915 | hs_ep->fifo_index = fifo_index; | |
3916 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3917 | } |
10aebc77 | 3918 | |
5b7d70c6 | 3919 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3920 | if (index && !hs_ep->isochronous) |
47a1685f | 3921 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3922 | |
3923 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3924 | __func__, epctrl); | |
3925 | ||
95c8bc36 | 3926 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3927 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3928 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3929 | |
3930 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3931 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3932 | |
5f54c54b | 3933 | error1: |
22258f49 | 3934 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
3935 | |
3936 | error2: | |
3937 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 3938 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
3939 | sizeof(struct dwc2_dma_desc), |
3940 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
3941 | hs_ep->desc_list = NULL; | |
3942 | } | |
3943 | ||
19c190f9 | 3944 | return ret; |
5b7d70c6 BD |
3945 | } |
3946 | ||
8b9bc460 | 3947 | /** |
1f91b4cc | 3948 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3949 | * @ep: The endpoint to disable. |
3950 | */ | |
1f91b4cc | 3951 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3952 | { |
1f91b4cc | 3953 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3954 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3955 | int dir_in = hs_ep->dir_in; |
3956 | int index = hs_ep->index; | |
3957 | unsigned long flags; | |
3958 | u32 epctrl_reg; | |
3959 | u32 ctrl; | |
3960 | ||
1e011293 | 3961 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 3962 | |
c6f5c050 | 3963 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
3964 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
3965 | return -EINVAL; | |
9b481092 JS |
3966 | } |
3967 | ||
3968 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3969 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
3970 | return -EINVAL; | |
5b7d70c6 BD |
3971 | } |
3972 | ||
94cb8fd6 | 3973 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 3974 | |
5ad1d316 | 3975 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3976 | |
95c8bc36 | 3977 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
a4f82771 VA |
3978 | |
3979 | if (ctrl & DXEPCTL_EPENA) | |
3980 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
3981 | ||
47a1685f DN |
3982 | ctrl &= ~DXEPCTL_EPENA; |
3983 | ctrl &= ~DXEPCTL_USBACTEP; | |
3984 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
3985 | |
3986 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 3987 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3988 | |
3989 | /* disable endpoint interrupts */ | |
1f91b4cc | 3990 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 3991 | |
1141ea01 MYK |
3992 | /* terminate all requests with shutdown */ |
3993 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
3994 | ||
1c07b20e RB |
3995 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
3996 | hs_ep->fifo_index = 0; | |
3997 | hs_ep->fifo_size = 0; | |
3998 | ||
22258f49 | 3999 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
4000 | return 0; |
4001 | } | |
4002 | ||
4003 | /** | |
4004 | * on_list - check request is on the given endpoint | |
4005 | * @ep: The endpoint to check. | |
4006 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4007 | */ |
1f91b4cc | 4008 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4009 | { |
1f91b4cc | 4010 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4011 | |
4012 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4013 | if (req == test) | |
4014 | return true; | |
4015 | } | |
4016 | ||
4017 | return false; | |
4018 | } | |
4019 | ||
8b9bc460 | 4020 | /** |
1f91b4cc | 4021 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4022 | * @ep: The endpoint to dequeue. |
4023 | * @req: The request to be removed from a queue. | |
4024 | */ | |
1f91b4cc | 4025 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4026 | { |
1f91b4cc FB |
4027 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4028 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4029 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4030 | unsigned long flags; |
4031 | ||
1e011293 | 4032 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4033 | |
22258f49 | 4034 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4035 | |
4036 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4037 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4038 | return -EINVAL; |
4039 | } | |
4040 | ||
c524dd5f MYK |
4041 | /* Dequeue already started request */ |
4042 | if (req == &hs_ep->req->req) | |
4043 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4044 | ||
1f91b4cc | 4045 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4046 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4047 | |
4048 | return 0; | |
4049 | } | |
4050 | ||
8b9bc460 | 4051 | /** |
1f91b4cc | 4052 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4053 | * @ep: The endpoint to set halt. |
4054 | * @value: Set or unset the halt. | |
51da43b5 VA |
4055 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4056 | * the endpoint is busy processing requests. | |
4057 | * | |
4058 | * We need to stall the endpoint immediately if request comes from set_feature | |
4059 | * protocol command handler. | |
8b9bc460 | 4060 | */ |
51da43b5 | 4061 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4062 | { |
1f91b4cc | 4063 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4064 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4065 | int index = hs_ep->index; |
5b7d70c6 BD |
4066 | u32 epreg; |
4067 | u32 epctl; | |
9c39ddc6 | 4068 | u32 xfertype; |
5b7d70c6 BD |
4069 | |
4070 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4071 | ||
c9f721b2 RB |
4072 | if (index == 0) { |
4073 | if (value) | |
1f91b4cc | 4074 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4075 | else |
4076 | dev_warn(hs->dev, | |
4077 | "%s: can't clear halt on ep0\n", __func__); | |
4078 | return 0; | |
4079 | } | |
4080 | ||
15186f10 VA |
4081 | if (hs_ep->isochronous) { |
4082 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4083 | return -EINVAL; | |
4084 | } | |
4085 | ||
51da43b5 VA |
4086 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4087 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4088 | ep->name); | |
4089 | return -EAGAIN; | |
4090 | } | |
4091 | ||
c6f5c050 MYK |
4092 | if (hs_ep->dir_in) { |
4093 | epreg = DIEPCTL(index); | |
95c8bc36 | 4094 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
4095 | |
4096 | if (value) { | |
5a350d53 | 4097 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4098 | if (epctl & DXEPCTL_EPENA) |
4099 | epctl |= DXEPCTL_EPDIS; | |
4100 | } else { | |
4101 | epctl &= ~DXEPCTL_STALL; | |
4102 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4103 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4104 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4105 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4106 | } |
95c8bc36 | 4107 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4108 | } else { |
c6f5c050 | 4109 | epreg = DOEPCTL(index); |
95c8bc36 | 4110 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 4111 | |
34c0887f | 4112 | if (value) { |
c6f5c050 | 4113 | epctl |= DXEPCTL_STALL; |
34c0887f | 4114 | } else { |
c6f5c050 MYK |
4115 | epctl &= ~DXEPCTL_STALL; |
4116 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4117 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4118 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4119 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4120 | } |
95c8bc36 | 4121 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4122 | } |
5b7d70c6 | 4123 | |
a18ed7b0 RB |
4124 | hs_ep->halted = value; |
4125 | ||
5b7d70c6 BD |
4126 | return 0; |
4127 | } | |
4128 | ||
5ad1d316 | 4129 | /** |
1f91b4cc | 4130 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4131 | * @ep: The endpoint to set halt. |
4132 | * @value: Set or unset the halt. | |
4133 | */ | |
1f91b4cc | 4134 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4135 | { |
1f91b4cc | 4136 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4137 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4138 | unsigned long flags = 0; |
4139 | int ret = 0; | |
4140 | ||
4141 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4142 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4143 | spin_unlock_irqrestore(&hs->lock, flags); |
4144 | ||
4145 | return ret; | |
4146 | } | |
4147 | ||
ebce561a | 4148 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc FB |
4149 | .enable = dwc2_hsotg_ep_enable, |
4150 | .disable = dwc2_hsotg_ep_disable, | |
4151 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
4152 | .free_request = dwc2_hsotg_ep_free_request, | |
4153 | .queue = dwc2_hsotg_ep_queue_lock, | |
4154 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4155 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4156 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4157 | }; |
4158 | ||
8b9bc460 | 4159 | /** |
9da51974 | 4160 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4161 | * @hsotg: The driver state |
4162 | */ | |
1f91b4cc | 4163 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 4164 | { |
fa4a8d72 | 4165 | u32 trdtim; |
ecd9a7ad | 4166 | u32 usbcfg; |
b3f489b2 LM |
4167 | /* unmask subset of endpoint interrupts */ |
4168 | ||
95c8bc36 AS |
4169 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
4170 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
4171 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 4172 | |
95c8bc36 AS |
4173 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
4174 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
4175 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 4176 | |
95c8bc36 | 4177 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
4178 | |
4179 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 4180 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4181 | |
b3f489b2 LM |
4182 | /* setup fifos */ |
4183 | ||
4184 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
4185 | dwc2_readl(hsotg->regs + GRXFSIZ), |
4186 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 4187 | |
1f91b4cc | 4188 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4189 | |
ecd9a7ad PR |
4190 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
4191 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
4192 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 4193 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 4194 | |
b3f489b2 | 4195 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 4196 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
4197 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
4198 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
4199 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 4200 | |
f5090044 GH |
4201 | if (using_dma(hsotg)) |
4202 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
4203 | } |
4204 | ||
8b9bc460 | 4205 | /** |
1f91b4cc | 4206 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4207 | * @gadget: The usb gadget state |
4208 | * @driver: The usb gadget driver | |
4209 | * | |
4210 | * Perform initialization to prepare udc device and driver | |
4211 | * to work. | |
4212 | */ | |
1f91b4cc | 4213 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4214 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4215 | { |
941fcce4 | 4216 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4217 | unsigned long flags; |
5b7d70c6 BD |
4218 | int ret; |
4219 | ||
4220 | if (!hsotg) { | |
a023da33 | 4221 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4222 | return -ENODEV; |
4223 | } | |
4224 | ||
4225 | if (!driver) { | |
4226 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4227 | return -EINVAL; | |
4228 | } | |
4229 | ||
7177aed4 | 4230 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4231 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4232 | |
f65f0f10 | 4233 | if (!driver->setup) { |
5b7d70c6 BD |
4234 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4235 | return -EINVAL; | |
4236 | } | |
4237 | ||
4238 | WARN_ON(hsotg->driver); | |
4239 | ||
4240 | driver->driver.bus = NULL; | |
4241 | hsotg->driver = driver; | |
7d7b2292 | 4242 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4243 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4244 | ||
09a75e85 MS |
4245 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4246 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4247 | if (ret) | |
4248 | goto err; | |
5b7d70c6 BD |
4249 | } |
4250 | ||
f6c01592 GH |
4251 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4252 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4253 | |
5b9451f8 | 4254 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4255 | if (dwc2_hw_is_device(hsotg)) { |
4256 | dwc2_hsotg_init(hsotg); | |
4257 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4258 | } | |
4259 | ||
dc6e69e6 | 4260 | hsotg->enabled = 0; |
5b9451f8 MS |
4261 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4262 | ||
5b7d70c6 | 4263 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4264 | |
5b7d70c6 BD |
4265 | return 0; |
4266 | ||
4267 | err: | |
4268 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4269 | return ret; |
4270 | } | |
4271 | ||
8b9bc460 | 4272 | /** |
1f91b4cc | 4273 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
4274 | * @gadget: The usb gadget state |
4275 | * @driver: The usb gadget driver | |
4276 | * | |
4277 | * Stop udc hw block and stay tunned for future transmissions | |
4278 | */ | |
1f91b4cc | 4279 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4280 | { |
941fcce4 | 4281 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4282 | unsigned long flags = 0; |
5b7d70c6 BD |
4283 | int ep; |
4284 | ||
4285 | if (!hsotg) | |
4286 | return -ENODEV; | |
4287 | ||
5b7d70c6 | 4288 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4289 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4290 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4291 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4292 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4293 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4294 | } |
5b7d70c6 | 4295 | |
2b19a52c LM |
4296 | spin_lock_irqsave(&hsotg->lock, flags); |
4297 | ||
32805c35 | 4298 | hsotg->driver = NULL; |
5b7d70c6 | 4299 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4300 | hsotg->enabled = 0; |
5b7d70c6 | 4301 | |
2b19a52c LM |
4302 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4303 | ||
f6c01592 GH |
4304 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4305 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4306 | |
09a75e85 MS |
4307 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4308 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4309 | |
4310 | return 0; | |
4311 | } | |
5b7d70c6 | 4312 | |
8b9bc460 | 4313 | /** |
1f91b4cc | 4314 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4315 | * @gadget: The usb gadget state |
4316 | * | |
4317 | * Read the {micro} frame number | |
4318 | */ | |
1f91b4cc | 4319 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4320 | { |
1f91b4cc | 4321 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4322 | } |
4323 | ||
a188b689 | 4324 | /** |
1f91b4cc | 4325 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4326 | * @gadget: The usb gadget state |
4327 | * @is_on: Current state of the USB PHY | |
4328 | * | |
4329 | * Connect/Disconnect the USB PHY pullup | |
4330 | */ | |
1f91b4cc | 4331 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4332 | { |
941fcce4 | 4333 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4334 | unsigned long flags = 0; |
4335 | ||
77ba9119 | 4336 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4337 | hsotg->op_state); |
77ba9119 GH |
4338 | |
4339 | /* Don't modify pullup state while in host mode */ | |
4340 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4341 | hsotg->enabled = is_on; | |
4342 | return 0; | |
4343 | } | |
a188b689 LM |
4344 | |
4345 | spin_lock_irqsave(&hsotg->lock, flags); | |
4346 | if (is_on) { | |
dc6e69e6 | 4347 | hsotg->enabled = 1; |
1f91b4cc FB |
4348 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
4349 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 4350 | } else { |
1f91b4cc FB |
4351 | dwc2_hsotg_core_disconnect(hsotg); |
4352 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4353 | hsotg->enabled = 0; |
a188b689 LM |
4354 | } |
4355 | ||
4356 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4357 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4358 | ||
4359 | return 0; | |
4360 | } | |
4361 | ||
1f91b4cc | 4362 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4363 | { |
4364 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4365 | unsigned long flags; | |
4366 | ||
4367 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4368 | spin_lock_irqsave(&hsotg->lock, flags); | |
4369 | ||
61f7223b GH |
4370 | /* |
4371 | * If controller is hibernated, it must exit from hibernation | |
4372 | * before being initialized / de-initialized | |
4373 | */ | |
4374 | if (hsotg->lx_state == DWC2_L2) | |
4375 | dwc2_exit_hibernation(hsotg, false); | |
4376 | ||
83d98223 | 4377 | if (is_active) { |
cd0e641c | 4378 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4379 | |
1f91b4cc | 4380 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 4381 | if (hsotg->enabled) |
1f91b4cc | 4382 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 4383 | } else { |
1f91b4cc FB |
4384 | dwc2_hsotg_core_disconnect(hsotg); |
4385 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4386 | } |
4387 | ||
4388 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4389 | return 0; | |
4390 | } | |
4391 | ||
596d696a | 4392 | /** |
1f91b4cc | 4393 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4394 | * @gadget: The usb gadget state |
4395 | * @mA: Amount of current | |
4396 | * | |
4397 | * Report how much power the device may consume to the phy. | |
4398 | */ | |
9da51974 | 4399 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4400 | { |
4401 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4402 | ||
4403 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4404 | return -ENOTSUPP; | |
4405 | return usb_phy_set_power(hsotg->uphy, mA); | |
4406 | } | |
4407 | ||
1f91b4cc FB |
4408 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4409 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4410 | .udc_start = dwc2_hsotg_udc_start, | |
4411 | .udc_stop = dwc2_hsotg_udc_stop, | |
4412 | .pullup = dwc2_hsotg_pullup, | |
4413 | .vbus_session = dwc2_hsotg_vbus_session, | |
4414 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4415 | }; |
4416 | ||
4417 | /** | |
1f91b4cc | 4418 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4419 | * @hsotg: The device state. |
4420 | * @hs_ep: The endpoint to be initialised. | |
4421 | * @epnum: The endpoint number | |
4422 | * | |
4423 | * Initialise the given endpoint (as part of the probe and device state | |
4424 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4425 | * direction information and other state that may be required. | |
4426 | */ | |
1f91b4cc | 4427 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4428 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4429 | int epnum, |
4430 | bool dir_in) | |
5b7d70c6 | 4431 | { |
5b7d70c6 BD |
4432 | char *dir; |
4433 | ||
4434 | if (epnum == 0) | |
4435 | dir = ""; | |
c6f5c050 | 4436 | else if (dir_in) |
5b7d70c6 | 4437 | dir = "in"; |
c6f5c050 MYK |
4438 | else |
4439 | dir = "out"; | |
5b7d70c6 | 4440 | |
c6f5c050 | 4441 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4442 | hs_ep->index = epnum; |
4443 | ||
4444 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4445 | ||
4446 | INIT_LIST_HEAD(&hs_ep->queue); | |
4447 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4448 | ||
5b7d70c6 BD |
4449 | /* add to the list of endpoints known by the gadget driver */ |
4450 | if (epnum) | |
4451 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4452 | ||
4453 | hs_ep->parent = hsotg; | |
4454 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4455 | |
4456 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4457 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4458 | else | |
4459 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4460 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4461 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4462 | |
2954522f RB |
4463 | if (epnum == 0) { |
4464 | hs_ep->ep.caps.type_control = true; | |
4465 | } else { | |
38e9002b VM |
4466 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4467 | hs_ep->ep.caps.type_iso = true; | |
4468 | hs_ep->ep.caps.type_bulk = true; | |
4469 | } | |
2954522f RB |
4470 | hs_ep->ep.caps.type_int = true; |
4471 | } | |
4472 | ||
4473 | if (dir_in) | |
4474 | hs_ep->ep.caps.dir_in = true; | |
4475 | else | |
4476 | hs_ep->ep.caps.dir_out = true; | |
4477 | ||
8b9bc460 LM |
4478 | /* |
4479 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4480 | * to be something valid. |
4481 | */ | |
4482 | ||
4483 | if (using_dma(hsotg)) { | |
47a1685f | 4484 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4485 | |
c6f5c050 | 4486 | if (dir_in) |
95c8bc36 | 4487 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 4488 | else |
95c8bc36 | 4489 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
4490 | } |
4491 | } | |
4492 | ||
b3f489b2 | 4493 | /** |
1f91b4cc | 4494 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
4495 | * @param: The device state |
4496 | * | |
4497 | * Read the USB core HW configuration registers | |
4498 | */ | |
1f91b4cc | 4499 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4500 | { |
c6f5c050 MYK |
4501 | u32 cfg; |
4502 | u32 ep_type; | |
4503 | u32 i; | |
4504 | ||
b3f489b2 | 4505 | /* check hardware configuration */ |
5b7d70c6 | 4506 | |
43e90349 JY |
4507 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4508 | ||
c6f5c050 MYK |
4509 | /* Add ep0 */ |
4510 | hsotg->num_of_eps++; | |
10aebc77 | 4511 | |
b98866c2 JY |
4512 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4513 | sizeof(struct dwc2_hsotg_ep), | |
4514 | GFP_KERNEL); | |
c6f5c050 MYK |
4515 | if (!hsotg->eps_in[0]) |
4516 | return -ENOMEM; | |
1f91b4cc | 4517 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4518 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4519 | ||
43e90349 | 4520 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4521 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4522 | ep_type = cfg & 3; |
4523 | /* Direction in or both */ | |
4524 | if (!(ep_type & 2)) { | |
4525 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4526 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4527 | if (!hsotg->eps_in[i]) |
4528 | return -ENOMEM; | |
4529 | } | |
4530 | /* Direction out or both */ | |
4531 | if (!(ep_type & 1)) { | |
4532 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4533 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4534 | if (!hsotg->eps_out[i]) |
4535 | return -ENOMEM; | |
4536 | } | |
4537 | } | |
4538 | ||
43e90349 JY |
4539 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4540 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4541 | |
cff9eb75 MS |
4542 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4543 | hsotg->num_of_eps, | |
4544 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4545 | hsotg->fifo_mem); | |
c6f5c050 | 4546 | return 0; |
5b7d70c6 BD |
4547 | } |
4548 | ||
8b9bc460 | 4549 | /** |
1f91b4cc | 4550 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
4551 | * @param: The device state |
4552 | */ | |
1f91b4cc | 4553 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4554 | { |
83a01804 | 4555 | #ifdef DEBUG |
5b7d70c6 BD |
4556 | struct device *dev = hsotg->dev; |
4557 | void __iomem *regs = hsotg->regs; | |
4558 | u32 val; | |
4559 | int idx; | |
4560 | ||
4561 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
4562 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
4563 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 4564 | |
f889f23d | 4565 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 4566 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
4567 | |
4568 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 4569 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
4570 | |
4571 | /* show periodic fifo settings */ | |
4572 | ||
364f8e93 | 4573 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 4574 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 4575 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4576 | val >> FIFOSIZE_DEPTH_SHIFT, |
4577 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4578 | } |
4579 | ||
364f8e93 | 4580 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4581 | dev_info(dev, |
4582 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
4583 | dwc2_readl(regs + DIEPCTL(idx)), |
4584 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
4585 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 4586 | |
95c8bc36 | 4587 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
4588 | dev_info(dev, |
4589 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
4590 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
4591 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
4592 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
4593 | } |
4594 | ||
4595 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 4596 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 4597 | #endif |
5b7d70c6 BD |
4598 | } |
4599 | ||
8b9bc460 | 4600 | /** |
117777b2 DN |
4601 | * dwc2_gadget_init - init function for gadget |
4602 | * @dwc2: The data structure for the DWC2 driver. | |
4603 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 4604 | */ |
117777b2 | 4605 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 4606 | { |
117777b2 | 4607 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4608 | int epnum; |
4609 | int ret; | |
43e90349 | 4610 | |
0a176279 GH |
4611 | /* Dump fifo information */ |
4612 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4613 | hsotg->params.g_np_tx_fifo_size); |
4614 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4615 | |
d327ab5b | 4616 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4617 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4618 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
4619 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4620 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4621 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4622 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4623 | |
1f91b4cc | 4624 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4625 | if (ret) { |
4626 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4627 | return ret; |
c6f5c050 MYK |
4628 | } |
4629 | ||
3f95001d MYK |
4630 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4631 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4632 | if (!hsotg->ctrl_buff) |
09a75e85 | 4633 | return -ENOMEM; |
3f95001d MYK |
4634 | |
4635 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4636 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4637 | if (!hsotg->ep0_buff) |
09a75e85 | 4638 | return -ENOMEM; |
3f95001d | 4639 | |
0f6b80c0 VA |
4640 | if (using_desc_dma(hsotg)) { |
4641 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4642 | if (ret < 0) | |
4643 | return ret; | |
4644 | } | |
4645 | ||
1f91b4cc | 4646 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
9da51974 | 4647 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 4648 | if (ret < 0) { |
db8178c3 | 4649 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4650 | return ret; |
eb3c56c5 MS |
4651 | } |
4652 | ||
b3f489b2 LM |
4653 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4654 | ||
4655 | if (hsotg->num_of_eps == 0) { | |
4656 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4657 | return -EINVAL; |
b3f489b2 LM |
4658 | } |
4659 | ||
b3f489b2 LM |
4660 | /* setup endpoint information */ |
4661 | ||
4662 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4663 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4664 | |
4665 | /* allocate EP0 request */ | |
4666 | ||
1f91b4cc | 4667 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4668 | GFP_KERNEL); |
4669 | if (!hsotg->ctrl_req) { | |
4670 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4671 | return -ENOMEM; |
b3f489b2 | 4672 | } |
5b7d70c6 BD |
4673 | |
4674 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4675 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4676 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4677 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4678 | epnum, 1); |
c6f5c050 | 4679 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4680 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4681 | epnum, 0); |
c6f5c050 | 4682 | } |
5b7d70c6 | 4683 | |
117777b2 | 4684 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 4685 | if (ret) |
09a75e85 | 4686 | return ret; |
0f91349b | 4687 | |
1f91b4cc | 4688 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4689 | |
5b7d70c6 | 4690 | return 0; |
5b7d70c6 BD |
4691 | } |
4692 | ||
8b9bc460 | 4693 | /** |
1f91b4cc | 4694 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
4695 | * @pdev: The platform information for the driver |
4696 | */ | |
1f91b4cc | 4697 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4698 | { |
0f91349b | 4699 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 4700 | |
5b7d70c6 BD |
4701 | return 0; |
4702 | } | |
4703 | ||
1f91b4cc | 4704 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4705 | { |
b83e333a | 4706 | unsigned long flags; |
b83e333a | 4707 | |
9e779778 | 4708 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4709 | return 0; |
9e779778 | 4710 | |
dc6e69e6 MS |
4711 | if (hsotg->driver) { |
4712 | int ep; | |
4713 | ||
b83e333a MS |
4714 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4715 | hsotg->driver->driver.name); | |
4716 | ||
dc6e69e6 MS |
4717 | spin_lock_irqsave(&hsotg->lock, flags); |
4718 | if (hsotg->enabled) | |
1f91b4cc FB |
4719 | dwc2_hsotg_core_disconnect(hsotg); |
4720 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4721 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4722 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4723 | |
c6f5c050 MYK |
4724 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4725 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4726 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4727 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4728 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4729 | } |
b83e333a MS |
4730 | } |
4731 | ||
09a75e85 | 4732 | return 0; |
b83e333a MS |
4733 | } |
4734 | ||
1f91b4cc | 4735 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4736 | { |
b83e333a | 4737 | unsigned long flags; |
b83e333a | 4738 | |
9e779778 | 4739 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4740 | return 0; |
9e779778 | 4741 | |
b83e333a MS |
4742 | if (hsotg->driver) { |
4743 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4744 | hsotg->driver->driver.name); | |
d00b4142 | 4745 | |
dc6e69e6 | 4746 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4747 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 4748 | if (hsotg->enabled) |
1f91b4cc | 4749 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
4750 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4751 | } | |
b83e333a | 4752 | |
09a75e85 | 4753 | return 0; |
b83e333a | 4754 | } |
58e52ff6 JY |
4755 | |
4756 | /** | |
4757 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4758 | * When suspending usb bus, registers needs to be backuped | |
4759 | * if controller power is disabled once suspended. | |
4760 | * | |
4761 | * @hsotg: Programming view of the DWC_otg controller | |
4762 | */ | |
4763 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4764 | { | |
4765 | struct dwc2_dregs_backup *dr; | |
4766 | int i; | |
4767 | ||
4768 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4769 | ||
4770 | /* Backup dev regs */ | |
4771 | dr = &hsotg->dr_backup; | |
4772 | ||
4773 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4774 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4775 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4776 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4777 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4778 | ||
4779 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4780 | /* Backup IN EPs */ | |
4781 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4782 | ||
4783 | /* Ensure DATA PID is correctly configured */ | |
4784 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4785 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4786 | else | |
4787 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4788 | ||
4789 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4790 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4791 | ||
4792 | /* Backup OUT EPs */ | |
4793 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4794 | ||
4795 | /* Ensure DATA PID is correctly configured */ | |
4796 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4797 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4798 | else | |
4799 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4800 | ||
4801 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4802 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
4803 | } | |
4804 | dr->valid = true; | |
4805 | return 0; | |
4806 | } | |
4807 | ||
4808 | /** | |
4809 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4810 | * When resuming usb bus, device registers needs to be restored | |
4811 | * if controller power were disabled. | |
4812 | * | |
4813 | * @hsotg: Programming view of the DWC_otg controller | |
4814 | */ | |
4815 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
4816 | { | |
4817 | struct dwc2_dregs_backup *dr; | |
4818 | u32 dctl; | |
4819 | int i; | |
4820 | ||
4821 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4822 | ||
4823 | /* Restore dev regs */ | |
4824 | dr = &hsotg->dr_backup; | |
4825 | if (!dr->valid) { | |
4826 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4827 | __func__); | |
4828 | return -EINVAL; | |
4829 | } | |
4830 | dr->valid = false; | |
4831 | ||
4832 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
4833 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4834 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
4835 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4836 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4837 | ||
4838 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4839 | /* Restore IN EPs */ | |
4840 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
4841 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
4842 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
4843 | ||
4844 | /* Restore OUT EPs */ | |
4845 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
4846 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
4847 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
4848 | } | |
4849 | ||
4850 | /* Set the Power-On Programming done bit */ | |
4851 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
4852 | dctl |= DCTL_PWRONPRGDONE; | |
4853 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
4854 | ||
4855 | return 0; | |
4856 | } |