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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/debugfs.h> | |
7ad8096e | 24 | #include <linux/mutex.h> |
5b7d70c6 BD |
25 | #include <linux/seq_file.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e50bf385 | 29 | #include <linux/clk.h> |
fc9a731e | 30 | #include <linux/regulator/consumer.h> |
c50f056c | 31 | #include <linux/of_platform.h> |
74084844 | 32 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
33 | |
34 | #include <linux/usb/ch9.h> | |
35 | #include <linux/usb/gadget.h> | |
b2e587db | 36 | #include <linux/usb/phy.h> |
126625e1 | 37 | #include <linux/platform_data/s3c-hsotg.h> |
9e14d0a5 | 38 | #include <linux/uaccess.h> |
5b7d70c6 | 39 | |
f7c0b143 | 40 | #include "core.h" |
941fcce4 | 41 | #include "hw.h" |
5b7d70c6 BD |
42 | |
43 | /* conversion functions */ | |
44 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
45 | { | |
46 | return container_of(req, struct s3c_hsotg_req, req); | |
47 | } | |
48 | ||
49 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
50 | { | |
51 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
52 | } | |
53 | ||
941fcce4 | 54 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 55 | { |
941fcce4 | 56 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
57 | } |
58 | ||
59 | static inline void __orr32(void __iomem *ptr, u32 val) | |
60 | { | |
61 | writel(readl(ptr) | val, ptr); | |
62 | } | |
63 | ||
64 | static inline void __bic32(void __iomem *ptr, u32 val) | |
65 | { | |
66 | writel(readl(ptr) & ~val, ptr); | |
67 | } | |
68 | ||
c6f5c050 MYK |
69 | static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
70 | u32 ep_index, u32 dir_in) | |
71 | { | |
72 | if (dir_in) | |
73 | return hsotg->eps_in[ep_index]; | |
74 | else | |
75 | return hsotg->eps_out[ep_index]; | |
76 | } | |
77 | ||
997f4f81 | 78 | /* forward declaration of functions */ |
941fcce4 | 79 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
80 | |
81 | /** | |
82 | * using_dma - return the DMA status of the driver. | |
83 | * @hsotg: The driver state. | |
84 | * | |
85 | * Return true if we're using DMA. | |
86 | * | |
87 | * Currently, we have the DMA support code worked into everywhere | |
88 | * that needs it, but the AMBA DMA implementation in the hardware can | |
89 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
90 | * as the CDC Ethernet cannot work as they often pass packets which are | |
91 | * not 32bit aligned. | |
92 | * | |
93 | * Unfortunately the choice to use DMA or not is global to the controller | |
94 | * and seems to be only settable when the controller is being put through | |
95 | * a core reset. This means we either need to fix the gadgets to take | |
96 | * account of DMA alignment, or add bounce buffers (yuerk). | |
97 | * | |
edd74be8 | 98 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 99 | */ |
941fcce4 | 100 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 101 | { |
edd74be8 | 102 | return hsotg->g_using_dma; |
5b7d70c6 BD |
103 | } |
104 | ||
105 | /** | |
106 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
107 | * @hsotg: The device state | |
108 | * @ints: A bitmask of the interrupts to enable | |
109 | */ | |
941fcce4 | 110 | static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 111 | { |
94cb8fd6 | 112 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
113 | u32 new_gsintmsk; |
114 | ||
115 | new_gsintmsk = gsintmsk | ints; | |
116 | ||
117 | if (new_gsintmsk != gsintmsk) { | |
118 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 119 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
120 | } |
121 | } | |
122 | ||
123 | /** | |
124 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
125 | * @hsotg: The device state | |
126 | * @ints: A bitmask of the interrupts to enable | |
127 | */ | |
941fcce4 | 128 | static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 129 | { |
94cb8fd6 | 130 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
131 | u32 new_gsintmsk; |
132 | ||
133 | new_gsintmsk = gsintmsk & ~ints; | |
134 | ||
135 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 136 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
137 | } |
138 | ||
139 | /** | |
140 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
141 | * @hsotg: The device state | |
142 | * @ep: The endpoint index | |
143 | * @dir_in: True if direction is in. | |
144 | * @en: The enable value, true to enable | |
145 | * | |
146 | * Set or clear the mask for an individual endpoint's interrupt | |
147 | * request. | |
148 | */ | |
941fcce4 | 149 | static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
150 | unsigned int ep, unsigned int dir_in, |
151 | unsigned int en) | |
152 | { | |
153 | unsigned long flags; | |
154 | u32 bit = 1 << ep; | |
155 | u32 daint; | |
156 | ||
157 | if (!dir_in) | |
158 | bit <<= 16; | |
159 | ||
160 | local_irq_save(flags); | |
94cb8fd6 | 161 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
162 | if (en) |
163 | daint |= bit; | |
164 | else | |
165 | daint &= ~bit; | |
94cb8fd6 | 166 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
167 | local_irq_restore(flags); |
168 | } | |
169 | ||
170 | /** | |
171 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
172 | * @hsotg: The device instance. | |
173 | */ | |
941fcce4 | 174 | static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 175 | { |
0f002d20 BD |
176 | unsigned int ep; |
177 | unsigned int addr; | |
1703a6d3 | 178 | int timeout; |
0f002d20 BD |
179 | u32 val; |
180 | ||
7fcbc95c GH |
181 | /* Reset fifo map if not correctly cleared during previous session */ |
182 | WARN_ON(hsotg->fifo_map); | |
183 | hsotg->fifo_map = 0; | |
184 | ||
0a176279 GH |
185 | /* set RX/NPTX FIFO sizes */ |
186 | writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); | |
187 | writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
188 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), | |
189 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 190 | |
8b9bc460 LM |
191 | /* |
192 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
193 | * block have overlapping default addresses. This also ensures |
194 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
195 | * known values. |
196 | */ | |
0f002d20 BD |
197 | |
198 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 199 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 200 | |
8b9bc460 | 201 | /* |
0a176279 | 202 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
203 | * them to endpoints dynamically according to maxpacket size value of |
204 | * given endpoint. | |
8b9bc460 | 205 | */ |
0a176279 GH |
206 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
207 | if (!hsotg->g_tx_fifo_sz[ep]) | |
208 | continue; | |
0f002d20 | 209 | val = addr; |
0a176279 GH |
210 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
211 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 212 | "insufficient fifo memory"); |
0a176279 | 213 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 214 | |
47a1685f | 215 | writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 216 | } |
1703a6d3 | 217 | |
8b9bc460 LM |
218 | /* |
219 | * according to p428 of the design guide, we need to ensure that | |
220 | * all fifos are flushed before continuing | |
221 | */ | |
1703a6d3 | 222 | |
47a1685f DN |
223 | writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
224 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
225 | |
226 | /* wait until the fifos are both flushed */ | |
227 | timeout = 100; | |
228 | while (1) { | |
94cb8fd6 | 229 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 230 | |
47a1685f | 231 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
232 | break; |
233 | ||
234 | if (--timeout == 0) { | |
235 | dev_err(hsotg->dev, | |
236 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
237 | __func__, val); | |
48b20bcb | 238 | break; |
1703a6d3 BD |
239 | } |
240 | ||
241 | udelay(1); | |
242 | } | |
243 | ||
244 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
245 | } |
246 | ||
247 | /** | |
248 | * @ep: USB endpoint to allocate request for. | |
249 | * @flags: Allocation flags | |
250 | * | |
251 | * Allocate a new USB request structure appropriate for the specified endpoint | |
252 | */ | |
0978f8c5 MB |
253 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
254 | gfp_t flags) | |
5b7d70c6 BD |
255 | { |
256 | struct s3c_hsotg_req *req; | |
257 | ||
258 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
259 | if (!req) | |
260 | return NULL; | |
261 | ||
262 | INIT_LIST_HEAD(&req->queue); | |
263 | ||
5b7d70c6 BD |
264 | return &req->req; |
265 | } | |
266 | ||
267 | /** | |
268 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
269 | * @hs_ep: The endpoint to query. | |
270 | * | |
271 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
272 | * used for an Interrupt or ISO transfer. | |
273 | */ | |
274 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
275 | { | |
276 | return hs_ep->periodic; | |
277 | } | |
278 | ||
279 | /** | |
280 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
281 | * @hsotg: The device state. | |
282 | * @hs_ep: The endpoint for the request | |
283 | * @hs_req: The request being processed. | |
284 | * | |
285 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
286 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 287 | */ |
941fcce4 | 288 | static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
289 | struct s3c_hsotg_ep *hs_ep, |
290 | struct s3c_hsotg_req *hs_req) | |
291 | { | |
292 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
293 | |
294 | /* ignore this if we're not moving any data */ | |
295 | if (hs_req->req.length == 0) | |
296 | return; | |
297 | ||
17d966a3 | 298 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
299 | } |
300 | ||
301 | /** | |
302 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
303 | * @hsotg: The controller state. | |
304 | * @hs_ep: The endpoint we're going to write for. | |
305 | * @hs_req: The request to write data for. | |
306 | * | |
307 | * This is called when the TxFIFO has some space in it to hold a new | |
308 | * transmission and we have something to give it. The actual setup of | |
309 | * the data size is done elsewhere, so all we have to do is to actually | |
310 | * write the data. | |
311 | * | |
312 | * The return value is zero if there is more space (or nothing was done) | |
313 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
314 | * | |
315 | * This routine is only needed for PIO | |
8b9bc460 | 316 | */ |
941fcce4 | 317 | static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
318 | struct s3c_hsotg_ep *hs_ep, |
319 | struct s3c_hsotg_req *hs_req) | |
320 | { | |
321 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 322 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
323 | int buf_pos = hs_req->req.actual; |
324 | int to_write = hs_ep->size_loaded; | |
325 | void *data; | |
326 | int can_write; | |
327 | int pkt_round; | |
4fca54aa | 328 | int max_transfer; |
5b7d70c6 BD |
329 | |
330 | to_write -= (buf_pos - hs_ep->last_load); | |
331 | ||
332 | /* if there's nothing to write, get out early */ | |
333 | if (to_write == 0) | |
334 | return 0; | |
335 | ||
10aebc77 | 336 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 337 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
338 | int size_left; |
339 | int size_done; | |
340 | ||
8b9bc460 LM |
341 | /* |
342 | * work out how much data was loaded so we can calculate | |
343 | * how much data is left in the fifo. | |
344 | */ | |
5b7d70c6 | 345 | |
47a1685f | 346 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 347 | |
8b9bc460 LM |
348 | /* |
349 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
350 | * previous data has been completely sent. |
351 | */ | |
352 | if (hs_ep->fifo_load != 0) { | |
47a1685f | 353 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
354 | return -ENOSPC; |
355 | } | |
356 | ||
5b7d70c6 BD |
357 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
358 | __func__, size_left, | |
359 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
360 | ||
361 | /* how much of the data has moved */ | |
362 | size_done = hs_ep->size_loaded - size_left; | |
363 | ||
364 | /* how much data is left in the fifo */ | |
365 | can_write = hs_ep->fifo_load - size_done; | |
366 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
367 | __func__, can_write); | |
368 | ||
369 | can_write = hs_ep->fifo_size - can_write; | |
370 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
371 | __func__, can_write); | |
372 | ||
373 | if (can_write <= 0) { | |
47a1685f | 374 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
375 | return -ENOSPC; |
376 | } | |
10aebc77 | 377 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 378 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
379 | |
380 | can_write &= 0xffff; | |
381 | can_write *= 4; | |
5b7d70c6 | 382 | } else { |
47a1685f | 383 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
384 | dev_dbg(hsotg->dev, |
385 | "%s: no queue slots available (0x%08x)\n", | |
386 | __func__, gnptxsts); | |
387 | ||
47a1685f | 388 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
389 | return -ENOSPC; |
390 | } | |
391 | ||
47a1685f | 392 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 393 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
394 | } |
395 | ||
4fca54aa RB |
396 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
397 | ||
398 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
399 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 400 | |
8b9bc460 LM |
401 | /* |
402 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
403 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
404 | * fragment of the end of the transfer in it. | |
405 | */ | |
811f3303 | 406 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
407 | can_write = 512; |
408 | ||
8b9bc460 LM |
409 | /* |
410 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 411 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
412 | * doing it. |
413 | */ | |
4fca54aa RB |
414 | if (to_write > max_transfer) { |
415 | to_write = max_transfer; | |
03e10e5a | 416 | |
5cb2ff0c RB |
417 | /* it's needed only when we do not use dedicated fifos */ |
418 | if (!hsotg->dedicated_fifos) | |
419 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
420 | periodic ? GINTSTS_PTXFEMP : |
421 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
422 | } |
423 | ||
5b7d70c6 BD |
424 | /* see if we can write data */ |
425 | ||
426 | if (to_write > can_write) { | |
427 | to_write = can_write; | |
4fca54aa | 428 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 429 | |
8b9bc460 LM |
430 | /* |
431 | * Round the write down to an | |
5b7d70c6 BD |
432 | * exact number of packets. |
433 | * | |
434 | * Note, we do not currently check to see if we can ever | |
435 | * write a full packet or not to the FIFO. | |
436 | */ | |
437 | ||
438 | if (pkt_round) | |
439 | to_write -= pkt_round; | |
440 | ||
8b9bc460 LM |
441 | /* |
442 | * enable correct FIFO interrupt to alert us when there | |
443 | * is more room left. | |
444 | */ | |
5b7d70c6 | 445 | |
5cb2ff0c RB |
446 | /* it's needed only when we do not use dedicated fifos */ |
447 | if (!hsotg->dedicated_fifos) | |
448 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
449 | periodic ? GINTSTS_PTXFEMP : |
450 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
451 | } |
452 | ||
453 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
454 | to_write, hs_req->req.length, can_write, buf_pos); | |
455 | ||
456 | if (to_write <= 0) | |
457 | return -ENOSPC; | |
458 | ||
459 | hs_req->req.actual = buf_pos + to_write; | |
460 | hs_ep->total_data += to_write; | |
461 | ||
462 | if (periodic) | |
463 | hs_ep->fifo_load += to_write; | |
464 | ||
465 | to_write = DIV_ROUND_UP(to_write, 4); | |
466 | data = hs_req->req.buf + buf_pos; | |
467 | ||
1a7ed5be | 468 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
469 | |
470 | return (to_write >= can_write) ? -ENOSPC : 0; | |
471 | } | |
472 | ||
473 | /** | |
474 | * get_ep_limit - get the maximum data legnth for this endpoint | |
475 | * @hs_ep: The endpoint | |
476 | * | |
477 | * Return the maximum data that can be queued in one go on a given endpoint | |
478 | * so that transfers that are too long can be split. | |
479 | */ | |
480 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
481 | { | |
482 | int index = hs_ep->index; | |
483 | unsigned maxsize; | |
484 | unsigned maxpkt; | |
485 | ||
486 | if (index != 0) { | |
47a1685f DN |
487 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
488 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 489 | } else { |
b05ca580 | 490 | maxsize = 64+64; |
66e5c643 | 491 | if (hs_ep->dir_in) |
47a1685f | 492 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 493 | else |
5b7d70c6 | 494 | maxpkt = 2; |
5b7d70c6 BD |
495 | } |
496 | ||
497 | /* we made the constant loading easier above by using +1 */ | |
498 | maxpkt--; | |
499 | maxsize--; | |
500 | ||
8b9bc460 LM |
501 | /* |
502 | * constrain by packet count if maxpkts*pktsize is greater | |
503 | * than the length register size. | |
504 | */ | |
5b7d70c6 BD |
505 | |
506 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
507 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
508 | ||
509 | return maxsize; | |
510 | } | |
511 | ||
512 | /** | |
513 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
514 | * @hsotg: The controller state. | |
515 | * @hs_ep: The endpoint to process a request for | |
516 | * @hs_req: The request to start. | |
517 | * @continuing: True if we are doing more for the current request. | |
518 | * | |
519 | * Start the given request running by setting the endpoint registers | |
520 | * appropriately, and writing any data to the FIFOs. | |
521 | */ | |
941fcce4 | 522 | static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
523 | struct s3c_hsotg_ep *hs_ep, |
524 | struct s3c_hsotg_req *hs_req, | |
525 | bool continuing) | |
526 | { | |
527 | struct usb_request *ureq = &hs_req->req; | |
528 | int index = hs_ep->index; | |
529 | int dir_in = hs_ep->dir_in; | |
530 | u32 epctrl_reg; | |
531 | u32 epsize_reg; | |
532 | u32 epsize; | |
533 | u32 ctrl; | |
534 | unsigned length; | |
535 | unsigned packets; | |
536 | unsigned maxreq; | |
537 | ||
538 | if (index != 0) { | |
539 | if (hs_ep->req && !continuing) { | |
540 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
541 | WARN_ON(1); | |
542 | return; | |
543 | } else if (hs_ep->req != hs_req && continuing) { | |
544 | dev_err(hsotg->dev, | |
545 | "%s: continue different req\n", __func__); | |
546 | WARN_ON(1); | |
547 | return; | |
548 | } | |
549 | } | |
550 | ||
94cb8fd6 LM |
551 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
552 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
553 | |
554 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
555 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
556 | hs_ep->dir_in ? "in" : "out"); | |
557 | ||
9c39ddc6 AT |
558 | /* If endpoint is stalled, we will restart request later */ |
559 | ctrl = readl(hsotg->regs + epctrl_reg); | |
560 | ||
47a1685f | 561 | if (ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
562 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
563 | return; | |
564 | } | |
565 | ||
5b7d70c6 | 566 | length = ureq->length - ureq->actual; |
71225bee LM |
567 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
568 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
569 | if (0) |
570 | dev_dbg(hsotg->dev, | |
0cc4cf6f | 571 | "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n", |
8b3bc14f | 572 | ureq->buf, length, &ureq->dma, |
5b7d70c6 BD |
573 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); |
574 | ||
575 | maxreq = get_ep_limit(hs_ep); | |
576 | if (length > maxreq) { | |
577 | int round = maxreq % hs_ep->ep.maxpacket; | |
578 | ||
579 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
580 | __func__, length, maxreq, round); | |
581 | ||
582 | /* round down to multiple of packets */ | |
583 | if (round) | |
584 | maxreq -= round; | |
585 | ||
586 | length = maxreq; | |
587 | } | |
588 | ||
589 | if (length) | |
590 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
591 | else | |
592 | packets = 1; /* send one packet if length is zero. */ | |
593 | ||
4fca54aa RB |
594 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
595 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
596 | return; | |
597 | } | |
598 | ||
5b7d70c6 | 599 | if (dir_in && index != 0) |
4fca54aa | 600 | if (hs_ep->isochronous) |
47a1685f | 601 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 602 | else |
47a1685f | 603 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
604 | else |
605 | epsize = 0; | |
606 | ||
f71b5e25 MYK |
607 | /* |
608 | * zero length packet should be programmed on its own and should not | |
609 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
610 | */ | |
611 | if (dir_in && ureq->zero && !continuing) { | |
612 | /* Test if zlp is actually required. */ | |
613 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
614 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 615 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
616 | } |
617 | ||
47a1685f DN |
618 | epsize |= DXEPTSIZ_PKTCNT(packets); |
619 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
620 | |
621 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
622 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
623 | ||
624 | /* store the request as the current one we're doing */ | |
625 | hs_ep->req = hs_req; | |
626 | ||
627 | /* write size / packets */ | |
628 | writel(epsize, hsotg->regs + epsize_reg); | |
629 | ||
db1d8ba3 | 630 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
631 | unsigned int dma_reg; |
632 | ||
8b9bc460 LM |
633 | /* |
634 | * write DMA address to control register, buffer already | |
635 | * synced by s3c_hsotg_ep_queue(). | |
636 | */ | |
5b7d70c6 | 637 | |
94cb8fd6 | 638 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
639 | writel(ureq->dma, hsotg->regs + dma_reg); |
640 | ||
0cc4cf6f | 641 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 642 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
643 | } |
644 | ||
47a1685f DN |
645 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
646 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 647 | |
fe0b94ab | 648 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
649 | |
650 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 651 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 652 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 653 | |
5b7d70c6 BD |
654 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
655 | writel(ctrl, hsotg->regs + epctrl_reg); | |
656 | ||
8b9bc460 LM |
657 | /* |
658 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 659 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
660 | * this information. |
661 | */ | |
5b7d70c6 BD |
662 | hs_ep->size_loaded = length; |
663 | hs_ep->last_load = ureq->actual; | |
664 | ||
665 | if (dir_in && !using_dma(hsotg)) { | |
666 | /* set these anyway, we may need them for non-periodic in */ | |
667 | hs_ep->fifo_load = 0; | |
668 | ||
669 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
670 | } | |
671 | ||
8b9bc460 LM |
672 | /* |
673 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
674 | * to debugging to see what is going on. | |
675 | */ | |
5b7d70c6 | 676 | if (dir_in) |
47a1685f | 677 | writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 678 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 679 | |
8b9bc460 LM |
680 | /* |
681 | * Note, trying to clear the NAK here causes problems with transmit | |
682 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
683 | */ | |
5b7d70c6 BD |
684 | |
685 | /* check ep is enabled */ | |
47a1685f | 686 | if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 687 | dev_dbg(hsotg->dev, |
47a1685f | 688 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
5b7d70c6 BD |
689 | index, readl(hsotg->regs + epctrl_reg)); |
690 | ||
47a1685f | 691 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
5b7d70c6 | 692 | __func__, readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
693 | |
694 | /* enable ep interrupts */ | |
695 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
696 | } |
697 | ||
698 | /** | |
699 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
700 | * @hsotg: The device state. | |
701 | * @hs_ep: The endpoint the request is on. | |
702 | * @req: The request being processed. | |
703 | * | |
704 | * We've been asked to queue a request, so ensure that the memory buffer | |
705 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
706 | * then ensure the buffer has been synced to memory. If our buffer has no | |
707 | * DMA memory, then we map the memory and mark our request to allow us to | |
708 | * cleanup on completion. | |
8b9bc460 | 709 | */ |
941fcce4 | 710 | static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
711 | struct s3c_hsotg_ep *hs_ep, |
712 | struct usb_request *req) | |
713 | { | |
5b7d70c6 | 714 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 715 | int ret; |
5b7d70c6 BD |
716 | |
717 | /* if the length is zero, ignore the DMA data */ | |
718 | if (hs_req->req.length == 0) | |
719 | return 0; | |
720 | ||
e58ebcd1 FB |
721 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
722 | if (ret) | |
723 | goto dma_error; | |
5b7d70c6 BD |
724 | |
725 | return 0; | |
726 | ||
727 | dma_error: | |
728 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
729 | __func__, req->buf, req->length); | |
730 | ||
731 | return -EIO; | |
732 | } | |
733 | ||
734 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
735 | gfp_t gfp_flags) | |
736 | { | |
737 | struct s3c_hsotg_req *hs_req = our_req(req); | |
738 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 739 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
740 | bool first; |
741 | ||
742 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
743 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
744 | req->zero, req->short_not_ok); | |
745 | ||
746 | /* initialise status of the request */ | |
747 | INIT_LIST_HEAD(&hs_req->queue); | |
748 | req->actual = 0; | |
749 | req->status = -EINPROGRESS; | |
750 | ||
751 | /* if we're using DMA, sync the buffers as necessary */ | |
752 | if (using_dma(hs)) { | |
753 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
754 | if (ret) | |
755 | return ret; | |
756 | } | |
757 | ||
5b7d70c6 BD |
758 | first = list_empty(&hs_ep->queue); |
759 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
760 | ||
761 | if (first) | |
762 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
763 | ||
5b7d70c6 BD |
764 | return 0; |
765 | } | |
766 | ||
5ad1d316 LM |
767 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
768 | gfp_t gfp_flags) | |
769 | { | |
770 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 771 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
772 | unsigned long flags = 0; |
773 | int ret = 0; | |
774 | ||
775 | spin_lock_irqsave(&hs->lock, flags); | |
776 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
777 | spin_unlock_irqrestore(&hs->lock, flags); | |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
5b7d70c6 BD |
782 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
783 | struct usb_request *req) | |
784 | { | |
785 | struct s3c_hsotg_req *hs_req = our_req(req); | |
786 | ||
787 | kfree(hs_req); | |
788 | } | |
789 | ||
790 | /** | |
791 | * s3c_hsotg_complete_oursetup - setup completion callback | |
792 | * @ep: The endpoint the request was on. | |
793 | * @req: The request completed. | |
794 | * | |
795 | * Called on completion of any requests the driver itself | |
796 | * submitted that need cleaning up. | |
797 | */ | |
798 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
799 | struct usb_request *req) | |
800 | { | |
801 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 802 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
803 | |
804 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
805 | ||
806 | s3c_hsotg_ep_free_request(ep, req); | |
807 | } | |
808 | ||
809 | /** | |
810 | * ep_from_windex - convert control wIndex value to endpoint | |
811 | * @hsotg: The driver state. | |
812 | * @windex: The control request wIndex field (in host order). | |
813 | * | |
814 | * Convert the given wIndex into a pointer to an driver endpoint | |
815 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 816 | */ |
941fcce4 | 817 | static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
818 | u32 windex) |
819 | { | |
c6f5c050 | 820 | struct s3c_hsotg_ep *ep; |
5b7d70c6 BD |
821 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
822 | int idx = windex & 0x7F; | |
823 | ||
824 | if (windex >= 0x100) | |
825 | return NULL; | |
826 | ||
b3f489b2 | 827 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
828 | return NULL; |
829 | ||
c6f5c050 MYK |
830 | ep = index_to_ep(hsotg, idx, dir); |
831 | ||
5b7d70c6 BD |
832 | if (idx && ep->dir_in != dir) |
833 | return NULL; | |
834 | ||
835 | return ep; | |
836 | } | |
837 | ||
9e14d0a5 GH |
838 | /** |
839 | * s3c_hsotg_set_test_mode - Enable usb Test Modes | |
840 | * @hsotg: The driver state. | |
841 | * @testmode: requested usb test mode | |
842 | * Enable usb Test Mode requested by the Host. | |
843 | */ | |
844 | static int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) | |
845 | { | |
846 | int dctl = readl(hsotg->regs + DCTL); | |
847 | ||
848 | dctl &= ~DCTL_TSTCTL_MASK; | |
849 | switch (testmode) { | |
850 | case TEST_J: | |
851 | case TEST_K: | |
852 | case TEST_SE0_NAK: | |
853 | case TEST_PACKET: | |
854 | case TEST_FORCE_EN: | |
855 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
856 | break; | |
857 | default: | |
858 | return -EINVAL; | |
859 | } | |
860 | writel(dctl, hsotg->regs + DCTL); | |
861 | return 0; | |
862 | } | |
863 | ||
5b7d70c6 BD |
864 | /** |
865 | * s3c_hsotg_send_reply - send reply to control request | |
866 | * @hsotg: The device state | |
867 | * @ep: Endpoint 0 | |
868 | * @buff: Buffer for request | |
869 | * @length: Length of reply. | |
870 | * | |
871 | * Create a request and queue it on the given endpoint. This is useful as | |
872 | * an internal method of sending replies to certain control requests, etc. | |
873 | */ | |
941fcce4 | 874 | static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
875 | struct s3c_hsotg_ep *ep, |
876 | void *buff, | |
877 | int length) | |
878 | { | |
879 | struct usb_request *req; | |
880 | int ret; | |
881 | ||
882 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
883 | ||
884 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
885 | hsotg->ep0_reply = req; | |
886 | if (!req) { | |
887 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
888 | return -ENOMEM; | |
889 | } | |
890 | ||
891 | req->buf = hsotg->ep0_buff; | |
892 | req->length = length; | |
f71b5e25 MYK |
893 | /* |
894 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
895 | * STATUS stage. | |
896 | */ | |
897 | req->zero = 0; | |
5b7d70c6 BD |
898 | req->complete = s3c_hsotg_complete_oursetup; |
899 | ||
900 | if (length) | |
901 | memcpy(req->buf, buff, length); | |
5b7d70c6 BD |
902 | |
903 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
904 | if (ret) { | |
905 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
906 | return ret; | |
907 | } | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
914 | * @hsotg: The device state | |
915 | * @ctrl: USB control request | |
916 | */ | |
941fcce4 | 917 | static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
918 | struct usb_ctrlrequest *ctrl) |
919 | { | |
c6f5c050 | 920 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
921 | struct s3c_hsotg_ep *ep; |
922 | __le16 reply; | |
923 | int ret; | |
924 | ||
925 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
926 | ||
927 | if (!ep0->dir_in) { | |
928 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
929 | return -EINVAL; | |
930 | } | |
931 | ||
932 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
933 | case USB_RECIP_DEVICE: | |
934 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
935 | * bit 1 => remote wakeup */ | |
936 | break; | |
937 | ||
938 | case USB_RECIP_INTERFACE: | |
939 | /* currently, the data result should be zero */ | |
940 | reply = cpu_to_le16(0); | |
941 | break; | |
942 | ||
943 | case USB_RECIP_ENDPOINT: | |
944 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
945 | if (!ep) | |
946 | return -ENOENT; | |
947 | ||
948 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
949 | break; | |
950 | ||
951 | default: | |
952 | return 0; | |
953 | } | |
954 | ||
955 | if (le16_to_cpu(ctrl->wLength) != 2) | |
956 | return -EINVAL; | |
957 | ||
958 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
959 | if (ret) { | |
960 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
961 | return ret; | |
962 | } | |
963 | ||
964 | return 1; | |
965 | } | |
966 | ||
967 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
968 | ||
9c39ddc6 AT |
969 | /** |
970 | * get_ep_head - return the first request on the endpoint | |
971 | * @hs_ep: The controller endpoint to get | |
972 | * | |
973 | * Get the first request on the endpoint. | |
974 | */ | |
975 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
976 | { | |
977 | if (list_empty(&hs_ep->queue)) | |
978 | return NULL; | |
979 | ||
980 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
981 | } | |
982 | ||
5b7d70c6 | 983 | /** |
58f7c43e | 984 | * s3c_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
985 | * @hsotg: The device state |
986 | * @ctrl: USB control request | |
987 | */ | |
941fcce4 | 988 | static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
989 | struct usb_ctrlrequest *ctrl) |
990 | { | |
c6f5c050 | 991 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
9c39ddc6 AT |
992 | struct s3c_hsotg_req *hs_req; |
993 | bool restart; | |
5b7d70c6 BD |
994 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
995 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 996 | int ret; |
bd9ef7bf | 997 | bool halted; |
9e14d0a5 GH |
998 | u32 recip; |
999 | u32 wValue; | |
1000 | u32 wIndex; | |
5b7d70c6 BD |
1001 | |
1002 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1003 | __func__, set ? "SET" : "CLEAR"); | |
1004 | ||
9e14d0a5 GH |
1005 | wValue = le16_to_cpu(ctrl->wValue); |
1006 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1007 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1008 | ||
1009 | switch (recip) { | |
1010 | case USB_RECIP_DEVICE: | |
1011 | switch (wValue) { | |
1012 | case USB_DEVICE_TEST_MODE: | |
1013 | if ((wIndex & 0xff) != 0) | |
1014 | return -EINVAL; | |
1015 | if (!set) | |
1016 | return -EINVAL; | |
1017 | ||
1018 | hsotg->test_mode = wIndex >> 8; | |
1019 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1020 | if (ret) { | |
1021 | dev_err(hsotg->dev, | |
1022 | "%s: failed to send reply\n", __func__); | |
1023 | return ret; | |
1024 | } | |
1025 | break; | |
1026 | default: | |
1027 | return -ENOENT; | |
1028 | } | |
1029 | break; | |
1030 | ||
1031 | case USB_RECIP_ENDPOINT: | |
1032 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1033 | if (!ep) { |
1034 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1035 | __func__, wIndex); |
5b7d70c6 BD |
1036 | return -ENOENT; |
1037 | } | |
1038 | ||
9e14d0a5 | 1039 | switch (wValue) { |
5b7d70c6 | 1040 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1041 | halted = ep->halted; |
1042 | ||
5b7d70c6 | 1043 | s3c_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c AT |
1044 | |
1045 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1046 | if (ret) { | |
1047 | dev_err(hsotg->dev, | |
1048 | "%s: failed to send reply\n", __func__); | |
1049 | return ret; | |
1050 | } | |
9c39ddc6 | 1051 | |
bd9ef7bf RB |
1052 | /* |
1053 | * we have to complete all requests for ep if it was | |
1054 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1055 | */ | |
1056 | ||
1057 | if (!set && halted) { | |
9c39ddc6 AT |
1058 | /* |
1059 | * If we have request in progress, | |
1060 | * then complete it | |
1061 | */ | |
1062 | if (ep->req) { | |
1063 | hs_req = ep->req; | |
1064 | ep->req = NULL; | |
1065 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1066 | if (hs_req->req.complete) { |
1067 | spin_unlock(&hsotg->lock); | |
1068 | usb_gadget_giveback_request( | |
1069 | &ep->ep, &hs_req->req); | |
1070 | spin_lock(&hsotg->lock); | |
1071 | } | |
9c39ddc6 AT |
1072 | } |
1073 | ||
1074 | /* If we have pending request, then start it */ | |
c00dd4a6 GH |
1075 | if (!ep->req) { |
1076 | restart = !list_empty(&ep->queue); | |
1077 | if (restart) { | |
1078 | hs_req = get_ep_head(ep); | |
1079 | s3c_hsotg_start_req(hsotg, ep, | |
1080 | hs_req, false); | |
1081 | } | |
9c39ddc6 AT |
1082 | } |
1083 | } | |
1084 | ||
5b7d70c6 BD |
1085 | break; |
1086 | ||
1087 | default: | |
1088 | return -ENOENT; | |
1089 | } | |
9e14d0a5 GH |
1090 | break; |
1091 | default: | |
1092 | return -ENOENT; | |
1093 | } | |
5b7d70c6 BD |
1094 | return 1; |
1095 | } | |
1096 | ||
941fcce4 | 1097 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1098 | |
c9f721b2 RB |
1099 | /** |
1100 | * s3c_hsotg_stall_ep0 - stall ep0 | |
1101 | * @hsotg: The device state | |
1102 | * | |
1103 | * Set stall for ep0 as response for setup request. | |
1104 | */ | |
941fcce4 | 1105 | static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1106 | { |
c6f5c050 | 1107 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1108 | u32 reg; |
1109 | u32 ctrl; | |
1110 | ||
1111 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1112 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1113 | ||
1114 | /* | |
1115 | * DxEPCTL_Stall will be cleared by EP once it has | |
1116 | * taken effect, so no need to clear later. | |
1117 | */ | |
1118 | ||
1119 | ctrl = readl(hsotg->regs + reg); | |
47a1685f DN |
1120 | ctrl |= DXEPCTL_STALL; |
1121 | ctrl |= DXEPCTL_CNAK; | |
c9f721b2 RB |
1122 | writel(ctrl, hsotg->regs + reg); |
1123 | ||
1124 | dev_dbg(hsotg->dev, | |
47a1685f | 1125 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
c9f721b2 RB |
1126 | ctrl, reg, readl(hsotg->regs + reg)); |
1127 | ||
1128 | /* | |
1129 | * complete won't be called, so we enqueue | |
1130 | * setup request here | |
1131 | */ | |
1132 | s3c_hsotg_enqueue_setup(hsotg); | |
1133 | } | |
1134 | ||
5b7d70c6 BD |
1135 | /** |
1136 | * s3c_hsotg_process_control - process a control request | |
1137 | * @hsotg: The device state | |
1138 | * @ctrl: The control request received | |
1139 | * | |
1140 | * The controller has received the SETUP phase of a control request, and | |
1141 | * needs to work out what to do next (and whether to pass it on to the | |
1142 | * gadget driver). | |
1143 | */ | |
941fcce4 | 1144 | static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1145 | struct usb_ctrlrequest *ctrl) |
1146 | { | |
c6f5c050 | 1147 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1148 | int ret = 0; |
1149 | u32 dcfg; | |
1150 | ||
5b7d70c6 BD |
1151 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", |
1152 | ctrl->bRequest, ctrl->bRequestType, | |
1153 | ctrl->wValue, ctrl->wLength); | |
1154 | ||
fe0b94ab MYK |
1155 | if (ctrl->wLength == 0) { |
1156 | ep0->dir_in = 1; | |
1157 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1158 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1159 | ep0->dir_in = 1; |
fe0b94ab MYK |
1160 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1161 | } else { | |
1162 | ep0->dir_in = 0; | |
1163 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1164 | } | |
5b7d70c6 BD |
1165 | |
1166 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1167 | switch (ctrl->bRequest) { | |
1168 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1169 | hsotg->connected = 1; |
94cb8fd6 | 1170 | dcfg = readl(hsotg->regs + DCFG); |
47a1685f | 1171 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1172 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1173 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
94cb8fd6 | 1174 | writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1175 | |
1176 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1177 | ||
1178 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1179 | return; | |
1180 | ||
1181 | case USB_REQ_GET_STATUS: | |
1182 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1183 | break; | |
1184 | ||
1185 | case USB_REQ_CLEAR_FEATURE: | |
1186 | case USB_REQ_SET_FEATURE: | |
1187 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1188 | break; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | /* as a fallback, try delivering it to the driver to deal with */ | |
1193 | ||
1194 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1195 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1196 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1197 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1198 | if (ret < 0) |
1199 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1200 | } | |
1201 | ||
8b9bc460 LM |
1202 | /* |
1203 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1204 | * so respond with a STALL for the status stage to indicate failure. |
1205 | */ | |
1206 | ||
c9f721b2 RB |
1207 | if (ret < 0) |
1208 | s3c_hsotg_stall_ep0(hsotg); | |
5b7d70c6 BD |
1209 | } |
1210 | ||
5b7d70c6 BD |
1211 | /** |
1212 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1213 | * @ep: The endpoint the request was on. | |
1214 | * @req: The request completed. | |
1215 | * | |
1216 | * Called on completion of any requests the driver itself submitted for | |
1217 | * EP0 setup packets | |
1218 | */ | |
1219 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1220 | struct usb_request *req) | |
1221 | { | |
1222 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1223 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1224 | |
1225 | if (req->status < 0) { | |
1226 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1227 | return; | |
1228 | } | |
1229 | ||
93f599f2 | 1230 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1231 | if (req->actual == 0) |
1232 | s3c_hsotg_enqueue_setup(hsotg); | |
1233 | else | |
1234 | s3c_hsotg_process_control(hsotg, req->buf); | |
93f599f2 | 1235 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1236 | } |
1237 | ||
1238 | /** | |
1239 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1240 | * @hsotg: The device state. | |
1241 | * | |
1242 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1243 | * received from the host. | |
1244 | */ | |
941fcce4 | 1245 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1246 | { |
1247 | struct usb_request *req = hsotg->ctrl_req; | |
1248 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1249 | int ret; | |
1250 | ||
1251 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1252 | ||
1253 | req->zero = 0; | |
1254 | req->length = 8; | |
1255 | req->buf = hsotg->ctrl_buff; | |
1256 | req->complete = s3c_hsotg_complete_setup; | |
1257 | ||
1258 | if (!list_empty(&hs_req->queue)) { | |
1259 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1260 | return; | |
1261 | } | |
1262 | ||
c6f5c050 | 1263 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1264 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1265 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1266 | |
c6f5c050 | 1267 | ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1268 | if (ret < 0) { |
1269 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1270 | /* |
1271 | * Don't think there's much we can do other than watch the | |
1272 | * driver fail. | |
1273 | */ | |
5b7d70c6 BD |
1274 | } |
1275 | } | |
1276 | ||
fe0b94ab MYK |
1277 | static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1278 | struct s3c_hsotg_ep *hs_ep) | |
1279 | { | |
1280 | u32 ctrl; | |
1281 | u8 index = hs_ep->index; | |
1282 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1283 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1284 | ||
1285 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index); | |
1286 | ||
1287 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1288 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1289 | epsiz_reg); | |
1290 | ||
1291 | ctrl = readl(hsotg->regs + epctl_reg); | |
1292 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ | |
1293 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1294 | ctrl |= DXEPCTL_USBACTEP; | |
1295 | writel(ctrl, hsotg->regs + epctl_reg); | |
1296 | } | |
1297 | ||
5b7d70c6 BD |
1298 | /** |
1299 | * s3c_hsotg_complete_request - complete a request given to us | |
1300 | * @hsotg: The device state. | |
1301 | * @hs_ep: The endpoint the request was on. | |
1302 | * @hs_req: The request to complete. | |
1303 | * @result: The result code (0 => Ok, otherwise errno) | |
1304 | * | |
1305 | * The given request has finished, so call the necessary completion | |
1306 | * if it has one and then look to see if we can start a new request | |
1307 | * on the endpoint. | |
1308 | * | |
1309 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1310 | */ |
941fcce4 | 1311 | static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1312 | struct s3c_hsotg_ep *hs_ep, |
1313 | struct s3c_hsotg_req *hs_req, | |
1314 | int result) | |
1315 | { | |
1316 | bool restart; | |
1317 | ||
1318 | if (!hs_req) { | |
1319 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1320 | return; | |
1321 | } | |
1322 | ||
1323 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1324 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1325 | ||
8b9bc460 LM |
1326 | /* |
1327 | * only replace the status if we've not already set an error | |
1328 | * from a previous transaction | |
1329 | */ | |
5b7d70c6 BD |
1330 | |
1331 | if (hs_req->req.status == -EINPROGRESS) | |
1332 | hs_req->req.status = result; | |
1333 | ||
1334 | hs_ep->req = NULL; | |
1335 | list_del_init(&hs_req->queue); | |
1336 | ||
1337 | if (using_dma(hsotg)) | |
1338 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1339 | ||
8b9bc460 LM |
1340 | /* |
1341 | * call the complete request with the locks off, just in case the | |
1342 | * request tries to queue more work for this endpoint. | |
1343 | */ | |
5b7d70c6 BD |
1344 | |
1345 | if (hs_req->req.complete) { | |
22258f49 | 1346 | spin_unlock(&hsotg->lock); |
304f7e5e | 1347 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1348 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1349 | } |
1350 | ||
8b9bc460 LM |
1351 | /* |
1352 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1353 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1354 | * so be careful when doing this. |
1355 | */ | |
5b7d70c6 BD |
1356 | |
1357 | if (!hs_ep->req && result >= 0) { | |
1358 | restart = !list_empty(&hs_ep->queue); | |
1359 | if (restart) { | |
1360 | hs_req = get_ep_head(hs_ep); | |
1361 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1362 | } | |
1363 | } | |
1364 | } | |
1365 | ||
5b7d70c6 BD |
1366 | /** |
1367 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1368 | * @hsotg: The device state. | |
1369 | * @ep_idx: The endpoint index for the data | |
1370 | * @size: The size of data in the fifo, in bytes | |
1371 | * | |
1372 | * The FIFO status shows there is data to read from the FIFO for a given | |
1373 | * endpoint, so sort out whether we need to read the data into a request | |
1374 | * that has been made for that endpoint. | |
1375 | */ | |
941fcce4 | 1376 | static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1377 | { |
c6f5c050 | 1378 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
5b7d70c6 | 1379 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
94cb8fd6 | 1380 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1381 | int to_read; |
1382 | int max_req; | |
1383 | int read_ptr; | |
1384 | ||
22258f49 | 1385 | |
5b7d70c6 | 1386 | if (!hs_req) { |
94cb8fd6 | 1387 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1388 | int ptr; |
1389 | ||
6b448af4 | 1390 | dev_dbg(hsotg->dev, |
47a1685f | 1391 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1392 | __func__, size, ep_idx, epctl); |
1393 | ||
1394 | /* dump the data from the FIFO, we've nothing we can do */ | |
1395 | for (ptr = 0; ptr < size; ptr += 4) | |
1396 | (void)readl(fifo); | |
1397 | ||
1398 | return; | |
1399 | } | |
1400 | ||
5b7d70c6 BD |
1401 | to_read = size; |
1402 | read_ptr = hs_req->req.actual; | |
1403 | max_req = hs_req->req.length - read_ptr; | |
1404 | ||
a33e7136 BD |
1405 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1406 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1407 | ||
5b7d70c6 | 1408 | if (to_read > max_req) { |
8b9bc460 LM |
1409 | /* |
1410 | * more data appeared than we where willing | |
5b7d70c6 BD |
1411 | * to deal with in this request. |
1412 | */ | |
1413 | ||
1414 | /* currently we don't deal this */ | |
1415 | WARN_ON_ONCE(1); | |
1416 | } | |
1417 | ||
5b7d70c6 BD |
1418 | hs_ep->total_data += to_read; |
1419 | hs_req->req.actual += to_read; | |
1420 | to_read = DIV_ROUND_UP(to_read, 4); | |
1421 | ||
8b9bc460 LM |
1422 | /* |
1423 | * note, we might over-write the buffer end by 3 bytes depending on | |
1424 | * alignment of the data. | |
1425 | */ | |
1a7ed5be | 1426 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1427 | } |
1428 | ||
1429 | /** | |
fe0b94ab | 1430 | * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1431 | * @hsotg: The device instance |
fe0b94ab | 1432 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1433 | * |
1434 | * Generate a zero-length IN packet request for terminating a SETUP | |
1435 | * transaction. | |
1436 | * | |
1437 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1438 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1439 | * the TxFIFO. |
1440 | */ | |
fe0b94ab | 1441 | static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1442 | { |
c6f5c050 | 1443 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1444 | hsotg->eps_out[0]->dir_in = dir_in; |
1445 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1446 | |
fe0b94ab | 1447 | s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1448 | } |
1449 | ||
1450 | /** | |
1451 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1452 | * @hsotg: The device instance | |
1453 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1454 | * |
1455 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1456 | * transfer for an OUT endpoint has been completed, either by a short | |
1457 | * packet or by the finish of a transfer. | |
8b9bc460 | 1458 | */ |
fe0b94ab | 1459 | static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1460 | { |
94cb8fd6 | 1461 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
c6f5c050 | 1462 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
5b7d70c6 BD |
1463 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
1464 | struct usb_request *req = &hs_req->req; | |
47a1685f | 1465 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1466 | int result = 0; |
1467 | ||
1468 | if (!hs_req) { | |
1469 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1470 | return; | |
1471 | } | |
1472 | ||
fe0b94ab MYK |
1473 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1474 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1475 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
1476 | s3c_hsotg_enqueue_setup(hsotg); | |
1477 | return; | |
1478 | } | |
1479 | ||
5b7d70c6 | 1480 | if (using_dma(hsotg)) { |
5b7d70c6 | 1481 | unsigned size_done; |
5b7d70c6 | 1482 | |
8b9bc460 LM |
1483 | /* |
1484 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1485 | * is left in the endpoint size register and then working it |
1486 | * out from the amount we loaded for the transfer. | |
1487 | * | |
1488 | * We need to do this as DMA pointers are always 32bit aligned | |
1489 | * so may overshoot/undershoot the transfer. | |
1490 | */ | |
1491 | ||
5b7d70c6 BD |
1492 | size_done = hs_ep->size_loaded - size_left; |
1493 | size_done += hs_ep->last_load; | |
1494 | ||
1495 | req->actual = size_done; | |
1496 | } | |
1497 | ||
a33e7136 BD |
1498 | /* if there is more request to do, schedule new transfer */ |
1499 | if (req->actual < req->length && size_left == 0) { | |
1500 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1501 | return; | |
1502 | } | |
1503 | ||
5b7d70c6 BD |
1504 | if (req->actual < req->length && req->short_not_ok) { |
1505 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1506 | __func__, req->actual, req->length); | |
1507 | ||
8b9bc460 LM |
1508 | /* |
1509 | * todo - what should we return here? there's no one else | |
1510 | * even bothering to check the status. | |
1511 | */ | |
5b7d70c6 BD |
1512 | } |
1513 | ||
fe0b94ab MYK |
1514 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1515 | /* Move to STATUS IN */ | |
1516 | s3c_hsotg_ep0_zlp(hsotg, true); | |
1517 | return; | |
5b7d70c6 BD |
1518 | } |
1519 | ||
5ad1d316 | 1520 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1521 | } |
1522 | ||
1523 | /** | |
1524 | * s3c_hsotg_read_frameno - read current frame number | |
1525 | * @hsotg: The device instance | |
1526 | * | |
1527 | * Return the current frame number | |
8b9bc460 | 1528 | */ |
941fcce4 | 1529 | static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1530 | { |
1531 | u32 dsts; | |
1532 | ||
94cb8fd6 LM |
1533 | dsts = readl(hsotg->regs + DSTS); |
1534 | dsts &= DSTS_SOFFN_MASK; | |
1535 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1536 | |
1537 | return dsts; | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1542 | * @hsotg: The device instance | |
1543 | * | |
1544 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1545 | * that requires processing, so find out what is in there and do the | |
1546 | * appropriate read. | |
1547 | * | |
25985edc | 1548 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1549 | * chunks, so if you have x packets received on an endpoint you'll get x |
1550 | * FIFO events delivered, each with a packet's worth of data in it. | |
1551 | * | |
1552 | * When using DMA, we should not be processing events from the RXFIFO | |
1553 | * as the actual data should be sent to the memory directly and we turn | |
1554 | * on the completion interrupts to get notifications of transfer completion. | |
1555 | */ | |
941fcce4 | 1556 | static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1557 | { |
94cb8fd6 | 1558 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1559 | u32 epnum, status, size; |
1560 | ||
1561 | WARN_ON(using_dma(hsotg)); | |
1562 | ||
47a1685f DN |
1563 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1564 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1565 | |
47a1685f DN |
1566 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1567 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 BD |
1568 | |
1569 | if (1) | |
1570 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1571 | __func__, grxstsr, size, epnum); | |
1572 | ||
47a1685f DN |
1573 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1574 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1575 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1576 | break; |
1577 | ||
47a1685f | 1578 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 BD |
1579 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1580 | s3c_hsotg_read_frameno(hsotg)); | |
1581 | ||
1582 | if (!using_dma(hsotg)) | |
fe0b94ab | 1583 | s3c_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1584 | break; |
1585 | ||
47a1685f | 1586 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1587 | dev_dbg(hsotg->dev, |
1588 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1589 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1590 | readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab MYK |
1591 | /* |
1592 | * Call s3c_hsotg_handle_outdone here if it was not called from | |
1593 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't | |
1594 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1595 | */ | |
1596 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1597 | s3c_hsotg_handle_outdone(hsotg, epnum); | |
5b7d70c6 BD |
1598 | break; |
1599 | ||
47a1685f | 1600 | case GRXSTS_PKTSTS_OUTRX: |
5b7d70c6 BD |
1601 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1602 | break; | |
1603 | ||
47a1685f | 1604 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1605 | dev_dbg(hsotg->dev, |
1606 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1607 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1608 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1609 | |
fe0b94ab MYK |
1610 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1611 | ||
5b7d70c6 BD |
1612 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1613 | break; | |
1614 | ||
1615 | default: | |
1616 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1617 | __func__, grxstsr); | |
1618 | ||
1619 | s3c_hsotg_dump(hsotg); | |
1620 | break; | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | /** | |
1625 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1626 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1627 | */ |
5b7d70c6 BD |
1628 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1629 | { | |
1630 | switch (mps) { | |
1631 | case 64: | |
94cb8fd6 | 1632 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1633 | case 32: |
94cb8fd6 | 1634 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1635 | case 16: |
94cb8fd6 | 1636 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1637 | case 8: |
94cb8fd6 | 1638 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1639 | } |
1640 | ||
1641 | /* bad max packet size, warn and return invalid result */ | |
1642 | WARN_ON(1); | |
1643 | return (u32)-1; | |
1644 | } | |
1645 | ||
1646 | /** | |
1647 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1648 | * @hsotg: The driver state. | |
1649 | * @ep: The index number of the endpoint | |
1650 | * @mps: The maximum packet size in bytes | |
1651 | * | |
1652 | * Configure the maximum packet size for the given endpoint, updating | |
1653 | * the hardware control registers to reflect this. | |
1654 | */ | |
941fcce4 | 1655 | static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1656 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1657 | { |
c6f5c050 | 1658 | struct s3c_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1659 | void __iomem *regs = hsotg->regs; |
1660 | u32 mpsval; | |
4fca54aa | 1661 | u32 mcval; |
5b7d70c6 BD |
1662 | u32 reg; |
1663 | ||
c6f5c050 MYK |
1664 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1665 | if (!hs_ep) | |
1666 | return; | |
1667 | ||
5b7d70c6 BD |
1668 | if (ep == 0) { |
1669 | /* EP0 is a special case */ | |
1670 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1671 | if (mpsval > 3) | |
1672 | goto bad_mps; | |
e9edd199 | 1673 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1674 | hs_ep->mc = 1; |
5b7d70c6 | 1675 | } else { |
47a1685f | 1676 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1677 | if (mpsval > 1024) |
5b7d70c6 | 1678 | goto bad_mps; |
4fca54aa RB |
1679 | mcval = ((mps >> 11) & 0x3) + 1; |
1680 | hs_ep->mc = mcval; | |
1681 | if (mcval > 3) | |
1682 | goto bad_mps; | |
e9edd199 | 1683 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1684 | } |
1685 | ||
c6f5c050 MYK |
1686 | if (dir_in) { |
1687 | reg = readl(regs + DIEPCTL(ep)); | |
1688 | reg &= ~DXEPCTL_MPS_MASK; | |
1689 | reg |= mpsval; | |
1690 | writel(reg, regs + DIEPCTL(ep)); | |
1691 | } else { | |
94cb8fd6 | 1692 | reg = readl(regs + DOEPCTL(ep)); |
47a1685f | 1693 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1694 | reg |= mpsval; |
94cb8fd6 | 1695 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1696 | } |
5b7d70c6 BD |
1697 | |
1698 | return; | |
1699 | ||
1700 | bad_mps: | |
1701 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1702 | } | |
1703 | ||
9c39ddc6 AT |
1704 | /** |
1705 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1706 | * @hsotg: The driver state | |
1707 | * @idx: The index for the endpoint (0..15) | |
1708 | */ | |
941fcce4 | 1709 | static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1710 | { |
1711 | int timeout; | |
1712 | int val; | |
1713 | ||
47a1685f | 1714 | writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
94cb8fd6 | 1715 | hsotg->regs + GRSTCTL); |
9c39ddc6 AT |
1716 | |
1717 | /* wait until the fifo is flushed */ | |
1718 | timeout = 100; | |
1719 | ||
1720 | while (1) { | |
94cb8fd6 | 1721 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1722 | |
47a1685f | 1723 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1724 | break; |
1725 | ||
1726 | if (--timeout == 0) { | |
1727 | dev_err(hsotg->dev, | |
1728 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1729 | __func__, val); | |
e0cbe595 | 1730 | break; |
9c39ddc6 AT |
1731 | } |
1732 | ||
1733 | udelay(1); | |
1734 | } | |
1735 | } | |
5b7d70c6 BD |
1736 | |
1737 | /** | |
1738 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1739 | * @hsotg: The driver state | |
1740 | * @hs_ep: The driver endpoint to check. | |
1741 | * | |
1742 | * Check to see if there is a request that has data to send, and if so | |
1743 | * make an attempt to write data into the FIFO. | |
1744 | */ | |
941fcce4 | 1745 | static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1746 | struct s3c_hsotg_ep *hs_ep) |
1747 | { | |
1748 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1749 | ||
afcf4169 RB |
1750 | if (!hs_ep->dir_in || !hs_req) { |
1751 | /** | |
1752 | * if request is not enqueued, we disable interrupts | |
1753 | * for endpoints, excepting ep0 | |
1754 | */ | |
1755 | if (hs_ep->index != 0) | |
1756 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1757 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1758 | return 0; |
afcf4169 | 1759 | } |
5b7d70c6 BD |
1760 | |
1761 | if (hs_req->req.actual < hs_req->req.length) { | |
1762 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1763 | hs_ep->index); | |
1764 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1765 | } | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | /** | |
1771 | * s3c_hsotg_complete_in - complete IN transfer | |
1772 | * @hsotg: The device state. | |
1773 | * @hs_ep: The endpoint that has just completed. | |
1774 | * | |
1775 | * An IN transfer has been completed, update the transfer's state and then | |
1776 | * call the relevant completion routines. | |
1777 | */ | |
941fcce4 | 1778 | static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1779 | struct s3c_hsotg_ep *hs_ep) |
1780 | { | |
1781 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1782 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1783 | int size_left, size_done; |
1784 | ||
1785 | if (!hs_req) { | |
1786 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1787 | return; | |
1788 | } | |
1789 | ||
d3ca0259 | 1790 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1791 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1792 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
5ad1d316 | 1793 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1794 | if (hsotg->test_mode) { |
1795 | int ret; | |
1796 | ||
1797 | ret = s3c_hsotg_set_test_mode(hsotg, hsotg->test_mode); | |
1798 | if (ret < 0) { | |
1799 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1800 | hsotg->test_mode); | |
1801 | s3c_hsotg_stall_ep0(hsotg); | |
1802 | return; | |
1803 | } | |
1804 | } | |
fe0b94ab | 1805 | s3c_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1806 | return; |
1807 | } | |
1808 | ||
8b9bc460 LM |
1809 | /* |
1810 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1811 | * in the endpoint size register and then working it out from |
1812 | * the amount we loaded for the transfer. | |
1813 | * | |
1814 | * We do this even for DMA, as the transfer may have incremented | |
1815 | * past the end of the buffer (DMA transfers are always 32bit | |
1816 | * aligned). | |
1817 | */ | |
1818 | ||
47a1685f | 1819 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1820 | |
1821 | size_done = hs_ep->size_loaded - size_left; | |
1822 | size_done += hs_ep->last_load; | |
1823 | ||
1824 | if (hs_req->req.actual != size_done) | |
1825 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1826 | __func__, hs_req->req.actual, size_done); | |
1827 | ||
1828 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1829 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1830 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1831 | ||
5b7d70c6 BD |
1832 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1833 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1834 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
fe0b94ab MYK |
1835 | return; |
1836 | } | |
1837 | ||
f71b5e25 | 1838 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1839 | if (hs_ep->send_zlp) { |
f71b5e25 | 1840 | s3c_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1841 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1842 | /* transfer will be completed on next complete interrupt */ |
1843 | return; | |
1844 | } | |
1845 | ||
fe0b94ab MYK |
1846 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1847 | /* Move to STATUS OUT */ | |
1848 | s3c_hsotg_ep0_zlp(hsotg, false); | |
1849 | return; | |
1850 | } | |
1851 | ||
1852 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
5b7d70c6 BD |
1853 | } |
1854 | ||
1855 | /** | |
1856 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1857 | * @hsotg: The driver state | |
1858 | * @idx: The index for the endpoint (0..15) | |
1859 | * @dir_in: Set if this is an IN endpoint | |
1860 | * | |
1861 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1862 | */ |
941fcce4 | 1863 | static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1864 | int dir_in) |
1865 | { | |
c6f5c050 | 1866 | struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1867 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1868 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1869 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1870 | u32 ints; |
1479e841 | 1871 | u32 ctrl; |
5b7d70c6 BD |
1872 | |
1873 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1874 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1875 | |
a3395f0d AT |
1876 | /* Clear endpoint interrupts */ |
1877 | writel(ints, hsotg->regs + epint_reg); | |
1878 | ||
c6f5c050 MYK |
1879 | if (!hs_ep) { |
1880 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1881 | __func__, idx, dir_in ? "in" : "out"); | |
1882 | return; | |
1883 | } | |
1884 | ||
5b7d70c6 BD |
1885 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1886 | __func__, idx, dir_in ? "in" : "out", ints); | |
1887 | ||
b787d755 MYK |
1888 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1889 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1890 | ints &= ~DXEPINT_XFERCOMPL; | |
1891 | ||
47a1685f | 1892 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1893 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1894 | if (ctrl & DXEPCTL_EOFRNUM) |
1895 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1896 | else |
47a1685f | 1897 | ctrl |= DXEPCTL_SETODDFR; |
1479e841 RB |
1898 | writel(ctrl, hsotg->regs + epctl_reg); |
1899 | } | |
1900 | ||
5b7d70c6 | 1901 | dev_dbg(hsotg->dev, |
47a1685f | 1902 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
5b7d70c6 BD |
1903 | __func__, readl(hsotg->regs + epctl_reg), |
1904 | readl(hsotg->regs + epsiz_reg)); | |
1905 | ||
8b9bc460 LM |
1906 | /* |
1907 | * we get OutDone from the FIFO, so we only need to look | |
1908 | * at completing IN requests here | |
1909 | */ | |
5b7d70c6 BD |
1910 | if (dir_in) { |
1911 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1912 | ||
c9a64ea8 | 1913 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1914 | s3c_hsotg_enqueue_setup(hsotg); |
1915 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1916 | /* |
1917 | * We're using DMA, we need to fire an OutDone here | |
1918 | * as we ignore the RXFIFO. | |
1919 | */ | |
5b7d70c6 | 1920 | |
fe0b94ab | 1921 | s3c_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 1922 | } |
5b7d70c6 BD |
1923 | } |
1924 | ||
47a1685f | 1925 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1926 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1927 | |
9c39ddc6 AT |
1928 | if (dir_in) { |
1929 | int epctl = readl(hsotg->regs + epctl_reg); | |
1930 | ||
b203d0a2 | 1931 | s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 1932 | |
47a1685f DN |
1933 | if ((epctl & DXEPCTL_STALL) && |
1934 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
94cb8fd6 | 1935 | int dctl = readl(hsotg->regs + DCTL); |
9c39ddc6 | 1936 | |
47a1685f | 1937 | dctl |= DCTL_CGNPINNAK; |
94cb8fd6 | 1938 | writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
1939 | } |
1940 | } | |
1941 | } | |
1942 | ||
47a1685f | 1943 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 1944 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1945 | |
47a1685f | 1946 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
1947 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
1948 | ||
1949 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
1950 | /* |
1951 | * this is the notification we've received a | |
5b7d70c6 BD |
1952 | * setup packet. In non-DMA mode we'd get this |
1953 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
1954 | * the setup here. |
1955 | */ | |
5b7d70c6 BD |
1956 | |
1957 | if (dir_in) | |
1958 | WARN_ON_ONCE(1); | |
1959 | else | |
fe0b94ab | 1960 | s3c_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 1961 | } |
5b7d70c6 BD |
1962 | } |
1963 | ||
47a1685f | 1964 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 1965 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 1966 | |
1479e841 | 1967 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 1968 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 1969 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
1970 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
1971 | __func__, idx); | |
5b7d70c6 BD |
1972 | } |
1973 | ||
1974 | /* this probably means something bad is happening */ | |
47a1685f | 1975 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
1976 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
1977 | __func__, idx); | |
5b7d70c6 | 1978 | } |
10aebc77 BD |
1979 | |
1980 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1981 | if (hsotg->dedicated_fifos && | |
47a1685f | 1982 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
1983 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
1984 | __func__, idx); | |
70fa030f AT |
1985 | if (!using_dma(hsotg)) |
1986 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1987 | } |
5b7d70c6 | 1988 | } |
5b7d70c6 BD |
1989 | } |
1990 | ||
1991 | /** | |
1992 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1993 | * @hsotg: The device state. | |
1994 | * | |
1995 | * Handle updating the device settings after the enumeration phase has | |
1996 | * been completed. | |
8b9bc460 | 1997 | */ |
941fcce4 | 1998 | static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1999 | { |
94cb8fd6 | 2000 | u32 dsts = readl(hsotg->regs + DSTS); |
9b2667f1 | 2001 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2002 | |
8b9bc460 LM |
2003 | /* |
2004 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2005 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2006 | * we connected at. |
2007 | */ | |
5b7d70c6 BD |
2008 | |
2009 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2010 | ||
8b9bc460 LM |
2011 | /* |
2012 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2013 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2014 | * not advertise a 64byte MPS on EP0. |
2015 | */ | |
5b7d70c6 BD |
2016 | |
2017 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
2018 | switch (dsts & DSTS_ENUMSPD_MASK) { |
2019 | case DSTS_ENUMSPD_FS: | |
2020 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2021 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2022 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2023 | ep_mps = 1023; |
5b7d70c6 BD |
2024 | break; |
2025 | ||
47a1685f | 2026 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2027 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2028 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2029 | ep_mps = 1024; |
5b7d70c6 BD |
2030 | break; |
2031 | ||
47a1685f | 2032 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2033 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2034 | /* |
2035 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2036 | * moment, and the documentation seems to imply that it isn't |
2037 | * supported by the PHYs on some of the devices. | |
2038 | */ | |
2039 | break; | |
2040 | } | |
e538dfda MN |
2041 | dev_info(hsotg->dev, "new device is %s\n", |
2042 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2043 | |
8b9bc460 LM |
2044 | /* |
2045 | * we should now know the maximum packet size for an | |
2046 | * endpoint, so set the endpoints to a default value. | |
2047 | */ | |
5b7d70c6 BD |
2048 | |
2049 | if (ep0_mps) { | |
2050 | int i; | |
c6f5c050 MYK |
2051 | /* Initialize ep0 for both in and out directions */ |
2052 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); | |
2053 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
2054 | for (i = 1; i < hsotg->num_of_eps; i++) { | |
2055 | if (hsotg->eps_in[i]) | |
2056 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); | |
2057 | if (hsotg->eps_out[i]) | |
2058 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); | |
2059 | } | |
5b7d70c6 BD |
2060 | } |
2061 | ||
2062 | /* ensure after enumeration our EP0 is active */ | |
2063 | ||
2064 | s3c_hsotg_enqueue_setup(hsotg); | |
2065 | ||
2066 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2067 | readl(hsotg->regs + DIEPCTL0), |
2068 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2069 | } |
2070 | ||
2071 | /** | |
2072 | * kill_all_requests - remove all requests from the endpoint's queue | |
2073 | * @hsotg: The device state. | |
2074 | * @ep: The endpoint the requests may be on. | |
2075 | * @result: The result code to use. | |
5b7d70c6 BD |
2076 | * |
2077 | * Go through the requests on the given endpoint and mark them | |
2078 | * completed with the given result code. | |
2079 | */ | |
941fcce4 | 2080 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 2081 | struct s3c_hsotg_ep *ep, |
6b448af4 | 2082 | int result) |
5b7d70c6 BD |
2083 | { |
2084 | struct s3c_hsotg_req *req, *treq; | |
b203d0a2 | 2085 | unsigned size; |
5b7d70c6 | 2086 | |
6b448af4 | 2087 | ep->req = NULL; |
5b7d70c6 | 2088 | |
6b448af4 | 2089 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
5b7d70c6 BD |
2090 | s3c_hsotg_complete_request(hsotg, ep, req, |
2091 | result); | |
6b448af4 | 2092 | |
b203d0a2 RB |
2093 | if (!hsotg->dedicated_fifos) |
2094 | return; | |
2095 | size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; | |
2096 | if (size < ep->fifo_size) | |
2097 | s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); | |
5b7d70c6 BD |
2098 | } |
2099 | ||
5b7d70c6 | 2100 | /** |
5e891342 | 2101 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2102 | * @hsotg: The device state. |
2103 | * | |
5e891342 LM |
2104 | * The device has been disconnected. Remove all current |
2105 | * transactions and signal the gadget driver that this | |
2106 | * has happened. | |
8b9bc460 | 2107 | */ |
4ace06e8 | 2108 | void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2109 | { |
2110 | unsigned ep; | |
2111 | ||
4ace06e8 MS |
2112 | if (!hsotg->connected) |
2113 | return; | |
2114 | ||
2115 | hsotg->connected = 0; | |
9e14d0a5 | 2116 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2117 | |
2118 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2119 | if (hsotg->eps_in[ep]) | |
2120 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2121 | -ESHUTDOWN); | |
2122 | if (hsotg->eps_out[ep]) | |
2123 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2124 | -ESHUTDOWN); | |
2125 | } | |
5b7d70c6 BD |
2126 | |
2127 | call_gadget(hsotg, disconnect); | |
2128 | } | |
4ace06e8 | 2129 | EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect); |
5b7d70c6 BD |
2130 | |
2131 | /** | |
2132 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2133 | * @hsotg: The device state: | |
2134 | * @periodic: True if this is a periodic FIFO interrupt | |
2135 | */ | |
941fcce4 | 2136 | static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 BD |
2137 | { |
2138 | struct s3c_hsotg_ep *ep; | |
2139 | int epno, ret; | |
2140 | ||
2141 | /* look through for any more data to transmit */ | |
b3f489b2 | 2142 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2143 | ep = index_to_ep(hsotg, epno, 1); |
2144 | ||
2145 | if (!ep) | |
2146 | continue; | |
5b7d70c6 BD |
2147 | |
2148 | if (!ep->dir_in) | |
2149 | continue; | |
2150 | ||
2151 | if ((periodic && !ep->periodic) || | |
2152 | (!periodic && ep->periodic)) | |
2153 | continue; | |
2154 | ||
2155 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2156 | if (ret < 0) | |
2157 | break; | |
2158 | } | |
2159 | } | |
2160 | ||
5b7d70c6 | 2161 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2162 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2163 | GINTSTS_PTXFEMP | \ | |
2164 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2165 | |
308d734e LM |
2166 | /** |
2167 | * s3c_hsotg_corereset - issue softreset to the core | |
2168 | * @hsotg: The device state | |
2169 | * | |
2170 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2171 | */ |
941fcce4 | 2172 | static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg) |
308d734e LM |
2173 | { |
2174 | int timeout; | |
2175 | u32 grstctl; | |
2176 | ||
2177 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2178 | ||
2179 | /* issue soft reset */ | |
47a1685f | 2180 | writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2181 | |
2868fea2 | 2182 | timeout = 10000; |
308d734e | 2183 | do { |
94cb8fd6 | 2184 | grstctl = readl(hsotg->regs + GRSTCTL); |
47a1685f | 2185 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2186 | |
47a1685f | 2187 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2188 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2189 | return -EINVAL; | |
2190 | } | |
2191 | ||
2868fea2 | 2192 | timeout = 10000; |
308d734e LM |
2193 | |
2194 | while (1) { | |
94cb8fd6 | 2195 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2196 | |
2197 | if (timeout-- < 0) { | |
2198 | dev_info(hsotg->dev, | |
2199 | "%s: reset failed, GRSTCTL=%08x\n", | |
2200 | __func__, grstctl); | |
2201 | return -ETIMEDOUT; | |
2202 | } | |
2203 | ||
47a1685f | 2204 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2205 | continue; |
2206 | ||
2207 | break; /* reset done */ | |
2208 | } | |
2209 | ||
2210 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2211 | return 0; | |
2212 | } | |
2213 | ||
8b9bc460 LM |
2214 | /** |
2215 | * s3c_hsotg_core_init - issue softreset to the core | |
2216 | * @hsotg: The device state | |
2217 | * | |
2218 | * Issue a soft reset to the core, and await the core finishing it. | |
2219 | */ | |
510ffaa4 | 2220 | void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg) |
308d734e LM |
2221 | { |
2222 | s3c_hsotg_corereset(hsotg); | |
2223 | ||
2224 | /* | |
2225 | * we must now enable ep0 ready for host detection and then | |
2226 | * set configuration. | |
2227 | */ | |
2228 | ||
2229 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2230 | writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
94cb8fd6 | 2231 | (0x5 << 10), hsotg->regs + GUSBCFG); |
308d734e LM |
2232 | |
2233 | s3c_hsotg_init_fifo(hsotg); | |
2234 | ||
47a1685f | 2235 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 2236 | |
47a1685f | 2237 | writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2238 | |
2239 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2240 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2241 | |
2242 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2243 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2244 | |
47a1685f DN |
2245 | writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
2246 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | | |
2247 | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | | |
2248 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2249 | GINTSTS_USBSUSP | GINTSTS_WKUPINT, | |
2250 | hsotg->regs + GINTMSK); | |
308d734e LM |
2251 | |
2252 | if (using_dma(hsotg)) | |
47a1685f | 2253 | writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
5f05048e | 2254 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), |
94cb8fd6 | 2255 | hsotg->regs + GAHBCFG); |
308d734e | 2256 | else |
47a1685f DN |
2257 | writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | |
2258 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2259 | GAHBCFG_GLBL_INTR_EN, | |
8acc8296 | 2260 | hsotg->regs + GAHBCFG); |
308d734e LM |
2261 | |
2262 | /* | |
8acc8296 RB |
2263 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2264 | * when we have no data to transfer. Otherwise we get being flooded by | |
2265 | * interrupts. | |
308d734e LM |
2266 | */ |
2267 | ||
6ff2e832 MYK |
2268 | writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
2269 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | | |
47a1685f DN |
2270 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2271 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2272 | DIEPMSK_INTKNEPMISMSK, | |
2273 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2274 | |
2275 | /* | |
2276 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2277 | * DMA mode we may need this. | |
2278 | */ | |
47a1685f DN |
2279 | writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
2280 | DIEPMSK_TIMEOUTMSK) : 0) | | |
2281 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2282 | DOEPMSK_SETUPMSK, | |
2283 | hsotg->regs + DOEPMSK); | |
308d734e | 2284 | |
94cb8fd6 | 2285 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2286 | |
2287 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2288 | readl(hsotg->regs + DIEPCTL0), |
2289 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2290 | |
2291 | /* enable in and out endpoint interrupts */ | |
47a1685f | 2292 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2293 | |
2294 | /* | |
2295 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2296 | * the data. In DMA mode, we get events from the FIFO but also | |
2297 | * things we cannot process, so do not use it. | |
2298 | */ | |
2299 | if (!using_dma(hsotg)) | |
47a1685f | 2300 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2301 | |
2302 | /* Enable interrupts for EP0 in and out */ | |
2303 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2304 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2305 | ||
47a1685f | 2306 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2307 | udelay(10); /* see openiboot */ |
47a1685f | 2308 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2309 | |
94cb8fd6 | 2310 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2311 | |
2312 | /* | |
94cb8fd6 | 2313 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2314 | * writing to the EPCTL register.. |
2315 | */ | |
2316 | ||
2317 | /* set to read 1 8byte packet */ | |
47a1685f DN |
2318 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2319 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); | |
308d734e | 2320 | |
c6f5c050 | 2321 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2322 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2323 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2324 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2325 | |
2326 | /* enable, but don't activate EP0in */ | |
c6f5c050 | 2327 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2328 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e LM |
2329 | |
2330 | s3c_hsotg_enqueue_setup(hsotg); | |
2331 | ||
2332 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2333 | readl(hsotg->regs + DIEPCTL0), |
2334 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2335 | |
2336 | /* clear global NAKs */ | |
ad38dc5d | 2337 | writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON, |
94cb8fd6 | 2338 | hsotg->regs + DCTL); |
308d734e LM |
2339 | |
2340 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2341 | mdelay(3); | |
2342 | ||
ac3c81f3 | 2343 | hsotg->last_rst = jiffies; |
ad38dc5d MS |
2344 | } |
2345 | ||
941fcce4 | 2346 | static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2347 | { |
2348 | /* set the soft-disconnect bit */ | |
2349 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2350 | } | |
ac3c81f3 | 2351 | |
510ffaa4 | 2352 | void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2353 | { |
308d734e | 2354 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2355 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2356 | } |
2357 | ||
5b7d70c6 BD |
2358 | /** |
2359 | * s3c_hsotg_irq - handle device interrupt | |
2360 | * @irq: The IRQ number triggered | |
2361 | * @pw: The pw value when registered the handler. | |
2362 | */ | |
2363 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2364 | { | |
941fcce4 | 2365 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2366 | int retry_count = 8; |
2367 | u32 gintsts; | |
2368 | u32 gintmsk; | |
2369 | ||
5ad1d316 | 2370 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2371 | irq_retry: |
94cb8fd6 LM |
2372 | gintsts = readl(hsotg->regs + GINTSTS); |
2373 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2374 | |
2375 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2376 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2377 | ||
2378 | gintsts &= gintmsk; | |
2379 | ||
47a1685f DN |
2380 | if (gintsts & GINTSTS_ENUMDONE) { |
2381 | writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2382 | |
2383 | s3c_hsotg_irq_enumdone(hsotg); | |
5b7d70c6 BD |
2384 | } |
2385 | ||
47a1685f | 2386 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
94cb8fd6 | 2387 | u32 daint = readl(hsotg->regs + DAINT); |
7e804650 RB |
2388 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2389 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2390 | int ep; |
2391 | ||
7e804650 | 2392 | daint &= daintmsk; |
47a1685f DN |
2393 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2394 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2395 | |
5b7d70c6 BD |
2396 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2397 | ||
cec87f1d MYK |
2398 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2399 | ep++, daint_out >>= 1) { | |
5b7d70c6 BD |
2400 | if (daint_out & 1) |
2401 | s3c_hsotg_epint(hsotg, ep, 0); | |
2402 | } | |
2403 | ||
cec87f1d MYK |
2404 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2405 | ep++, daint_in >>= 1) { | |
5b7d70c6 BD |
2406 | if (daint_in & 1) |
2407 | s3c_hsotg_epint(hsotg, ep, 1); | |
2408 | } | |
5b7d70c6 BD |
2409 | } |
2410 | ||
47a1685f | 2411 | if (gintsts & GINTSTS_USBRST) { |
12a1f4dc | 2412 | |
94cb8fd6 | 2413 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2414 | |
9599815d | 2415 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
5b7d70c6 | 2416 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
94cb8fd6 | 2417 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2418 | |
47a1685f | 2419 | writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2420 | |
6d713c15 MYK |
2421 | /* Report disconnection if it is not already done. */ |
2422 | s3c_hsotg_disconnect(hsotg); | |
2423 | ||
94cb8fd6 | 2424 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2425 | if (time_after(jiffies, hsotg->last_rst + |
2426 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2427 | |
c6f5c050 | 2428 | kill_all_requests(hsotg, hsotg->eps_out[0], |
6b448af4 | 2429 | -ECONNRESET); |
5b7d70c6 | 2430 | |
ad38dc5d MS |
2431 | s3c_hsotg_core_init_disconnected(hsotg); |
2432 | s3c_hsotg_core_connect(hsotg); | |
12a1f4dc LM |
2433 | } |
2434 | } | |
5b7d70c6 BD |
2435 | } |
2436 | ||
2437 | /* check both FIFOs */ | |
2438 | ||
47a1685f | 2439 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2440 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2441 | ||
8b9bc460 LM |
2442 | /* |
2443 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2444 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2445 | * it needs re-enabling |
2446 | */ | |
5b7d70c6 | 2447 | |
47a1685f | 2448 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 | 2449 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2450 | } |
2451 | ||
47a1685f | 2452 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2453 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2454 | ||
94cb8fd6 | 2455 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2456 | |
47a1685f | 2457 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 | 2458 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2459 | } |
2460 | ||
47a1685f | 2461 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2462 | /* |
2463 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2464 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2465 | * set. |
2466 | */ | |
5b7d70c6 BD |
2467 | |
2468 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2469 | } |
2470 | ||
47a1685f | 2471 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2472 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
47a1685f | 2473 | writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2474 | } |
2475 | ||
8b9bc460 LM |
2476 | /* |
2477 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2478 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2479 | * the occurrence. |
2480 | */ | |
5b7d70c6 | 2481 | |
47a1685f | 2482 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2483 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2484 | ||
47a1685f | 2485 | writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2486 | |
2487 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2488 | } |
2489 | ||
47a1685f | 2490 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2491 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2492 | ||
47a1685f | 2493 | writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2494 | |
2495 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2496 | } |
2497 | ||
8b9bc460 LM |
2498 | /* |
2499 | * if we've had fifo events, we should try and go around the | |
2500 | * loop again to see if there's any point in returning yet. | |
2501 | */ | |
5b7d70c6 BD |
2502 | |
2503 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2504 | goto irq_retry; | |
2505 | ||
5ad1d316 LM |
2506 | spin_unlock(&hsotg->lock); |
2507 | ||
5b7d70c6 BD |
2508 | return IRQ_HANDLED; |
2509 | } | |
2510 | ||
2511 | /** | |
2512 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2513 | * @ep: The USB endpint to configure | |
2514 | * @desc: The USB endpoint descriptor to configure with. | |
2515 | * | |
2516 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2517 | */ |
5b7d70c6 BD |
2518 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2519 | const struct usb_endpoint_descriptor *desc) | |
2520 | { | |
2521 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2522 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2523 | unsigned long flags; |
ca4c55ad | 2524 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2525 | u32 epctrl_reg; |
2526 | u32 epctrl; | |
2527 | u32 mps; | |
ca4c55ad MYK |
2528 | unsigned int dir_in; |
2529 | unsigned int i, val, size; | |
19c190f9 | 2530 | int ret = 0; |
5b7d70c6 BD |
2531 | |
2532 | dev_dbg(hsotg->dev, | |
2533 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2534 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2535 | desc->wMaxPacketSize, desc->bInterval); | |
2536 | ||
2537 | /* not to be called for EP0 */ | |
2538 | WARN_ON(index == 0); | |
2539 | ||
2540 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2541 | if (dir_in != hs_ep->dir_in) { | |
2542 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2543 | return -EINVAL; | |
2544 | } | |
2545 | ||
29cc8897 | 2546 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2547 | |
2548 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2549 | ||
94cb8fd6 | 2550 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2551 | epctrl = readl(hsotg->regs + epctrl_reg); |
2552 | ||
2553 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2554 | __func__, epctrl, epctrl_reg); | |
2555 | ||
22258f49 | 2556 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2557 | |
47a1685f DN |
2558 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2559 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2560 | |
8b9bc460 LM |
2561 | /* |
2562 | * mark the endpoint as active, otherwise the core may ignore | |
2563 | * transactions entirely for this endpoint | |
2564 | */ | |
47a1685f | 2565 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2566 | |
8b9bc460 LM |
2567 | /* |
2568 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2569 | * do something with data that we've yet got a request to process |
2570 | * since the RXFIFO will take data for an endpoint even if the | |
2571 | * size register hasn't been set. | |
2572 | */ | |
2573 | ||
47a1685f | 2574 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2575 | |
2576 | /* update the endpoint state */ | |
c6f5c050 | 2577 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2578 | |
2579 | /* default, set to non-periodic */ | |
1479e841 | 2580 | hs_ep->isochronous = 0; |
5b7d70c6 | 2581 | hs_ep->periodic = 0; |
a18ed7b0 | 2582 | hs_ep->halted = 0; |
1479e841 | 2583 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2584 | |
4fca54aa RB |
2585 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2586 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2587 | ||
5b7d70c6 BD |
2588 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2589 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2590 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2591 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2592 | hs_ep->isochronous = 1; |
2593 | if (dir_in) | |
2594 | hs_ep->periodic = 1; | |
2595 | break; | |
5b7d70c6 BD |
2596 | |
2597 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2598 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2599 | break; |
2600 | ||
2601 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2602 | if (dir_in) |
5b7d70c6 | 2603 | hs_ep->periodic = 1; |
5b7d70c6 | 2604 | |
47a1685f | 2605 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2606 | break; |
2607 | ||
2608 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2609 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2610 | break; |
2611 | } | |
2612 | ||
4556e12c MYK |
2613 | /* If fifo is already allocated for this ep */ |
2614 | if (hs_ep->fifo_index) { | |
2615 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
2616 | /* If bigger fifo is required deallocate current one */ | |
2617 | if (size > hs_ep->fifo_size) { | |
2618 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
2619 | hs_ep->fifo_index = 0; | |
2620 | hs_ep->fifo_size = 0; | |
2621 | } | |
2622 | } | |
2623 | ||
8b9bc460 LM |
2624 | /* |
2625 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2626 | * a unique tx-fifo even if it is non-periodic. |
2627 | */ | |
4556e12c | 2628 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
2629 | u32 fifo_index = 0; |
2630 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 2631 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 2632 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2633 | if (hsotg->fifo_map & (1<<i)) |
2634 | continue; | |
2635 | val = readl(hsotg->regs + DPTXFSIZN(i)); | |
2636 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; | |
2637 | if (val < size) | |
2638 | continue; | |
ca4c55ad MYK |
2639 | /* Search for smallest acceptable fifo */ |
2640 | if (val < fifo_size) { | |
2641 | fifo_size = val; | |
2642 | fifo_index = i; | |
2643 | } | |
b203d0a2 | 2644 | } |
ca4c55ad | 2645 | if (!fifo_index) { |
5f2196bd MYK |
2646 | dev_err(hsotg->dev, |
2647 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2648 | ret = -ENOMEM; |
2649 | goto error; | |
2650 | } | |
ca4c55ad MYK |
2651 | hsotg->fifo_map |= 1 << fifo_index; |
2652 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
2653 | hs_ep->fifo_index = fifo_index; | |
2654 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 2655 | } |
10aebc77 | 2656 | |
5b7d70c6 BD |
2657 | /* for non control endpoints, set PID to D0 */ |
2658 | if (index) | |
47a1685f | 2659 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2660 | |
2661 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2662 | __func__, epctrl); | |
2663 | ||
2664 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2665 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2666 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2667 | ||
2668 | /* enable the endpoint interrupt */ | |
2669 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2670 | ||
b585a48b | 2671 | error: |
22258f49 | 2672 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2673 | return ret; |
5b7d70c6 BD |
2674 | } |
2675 | ||
8b9bc460 LM |
2676 | /** |
2677 | * s3c_hsotg_ep_disable - disable given endpoint | |
2678 | * @ep: The endpoint to disable. | |
2679 | */ | |
62f4f065 | 2680 | static int s3c_hsotg_ep_disable_force(struct usb_ep *ep, bool force) |
5b7d70c6 BD |
2681 | { |
2682 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2683 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2684 | int dir_in = hs_ep->dir_in; |
2685 | int index = hs_ep->index; | |
2686 | unsigned long flags; | |
2687 | u32 epctrl_reg; | |
2688 | u32 ctrl; | |
2689 | ||
1e011293 | 2690 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2691 | |
c6f5c050 | 2692 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2693 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2694 | return -EINVAL; | |
2695 | } | |
2696 | ||
94cb8fd6 | 2697 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2698 | |
5ad1d316 | 2699 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2700 | |
b203d0a2 RB |
2701 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2702 | hs_ep->fifo_index = 0; | |
2703 | hs_ep->fifo_size = 0; | |
5b7d70c6 BD |
2704 | |
2705 | ctrl = readl(hsotg->regs + epctrl_reg); | |
47a1685f DN |
2706 | ctrl &= ~DXEPCTL_EPENA; |
2707 | ctrl &= ~DXEPCTL_USBACTEP; | |
2708 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2709 | |
2710 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2711 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2712 | ||
2713 | /* disable endpoint interrupts */ | |
2714 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2715 | ||
1141ea01 MYK |
2716 | /* terminate all requests with shutdown */ |
2717 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2718 | ||
22258f49 | 2719 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2720 | return 0; |
2721 | } | |
2722 | ||
62f4f065 RB |
2723 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2724 | { | |
2725 | return s3c_hsotg_ep_disable_force(ep, false); | |
2726 | } | |
5b7d70c6 BD |
2727 | /** |
2728 | * on_list - check request is on the given endpoint | |
2729 | * @ep: The endpoint to check. | |
2730 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2731 | */ |
5b7d70c6 BD |
2732 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2733 | { | |
2734 | struct s3c_hsotg_req *req, *treq; | |
2735 | ||
2736 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2737 | if (req == test) | |
2738 | return true; | |
2739 | } | |
2740 | ||
2741 | return false; | |
2742 | } | |
2743 | ||
8b9bc460 LM |
2744 | /** |
2745 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2746 | * @ep: The endpoint to dequeue. | |
2747 | * @req: The request to be removed from a queue. | |
2748 | */ | |
5b7d70c6 BD |
2749 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2750 | { | |
2751 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2752 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2753 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2754 | unsigned long flags; |
2755 | ||
1e011293 | 2756 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2757 | |
22258f49 | 2758 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2759 | |
2760 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2761 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2762 | return -EINVAL; |
2763 | } | |
2764 | ||
2765 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2766 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2767 | |
2768 | return 0; | |
2769 | } | |
2770 | ||
8b9bc460 LM |
2771 | /** |
2772 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2773 | * @ep: The endpoint to set halt. | |
2774 | * @value: Set or unset the halt. | |
2775 | */ | |
5b7d70c6 BD |
2776 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2777 | { | |
2778 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2779 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2780 | int index = hs_ep->index; |
5b7d70c6 BD |
2781 | u32 epreg; |
2782 | u32 epctl; | |
9c39ddc6 | 2783 | u32 xfertype; |
5b7d70c6 BD |
2784 | |
2785 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2786 | ||
c9f721b2 RB |
2787 | if (index == 0) { |
2788 | if (value) | |
2789 | s3c_hsotg_stall_ep0(hs); | |
2790 | else | |
2791 | dev_warn(hs->dev, | |
2792 | "%s: can't clear halt on ep0\n", __func__); | |
2793 | return 0; | |
2794 | } | |
2795 | ||
c6f5c050 MYK |
2796 | if (hs_ep->dir_in) { |
2797 | epreg = DIEPCTL(index); | |
2798 | epctl = readl(hs->regs + epreg); | |
2799 | ||
2800 | if (value) { | |
2801 | epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; | |
2802 | if (epctl & DXEPCTL_EPENA) | |
2803 | epctl |= DXEPCTL_EPDIS; | |
2804 | } else { | |
2805 | epctl &= ~DXEPCTL_STALL; | |
2806 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2807 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2808 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2809 | epctl |= DXEPCTL_SETD0PID; | |
2810 | } | |
2811 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2812 | } else { |
5b7d70c6 | 2813 | |
c6f5c050 MYK |
2814 | epreg = DOEPCTL(index); |
2815 | epctl = readl(hs->regs + epreg); | |
5b7d70c6 | 2816 | |
c6f5c050 MYK |
2817 | if (value) |
2818 | epctl |= DXEPCTL_STALL; | |
2819 | else { | |
2820 | epctl &= ~DXEPCTL_STALL; | |
2821 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2822 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2823 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2824 | epctl |= DXEPCTL_SETD0PID; | |
2825 | } | |
2826 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2827 | } |
5b7d70c6 | 2828 | |
a18ed7b0 RB |
2829 | hs_ep->halted = value; |
2830 | ||
5b7d70c6 BD |
2831 | return 0; |
2832 | } | |
2833 | ||
5ad1d316 LM |
2834 | /** |
2835 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2836 | * @ep: The endpoint to set halt. | |
2837 | * @value: Set or unset the halt. | |
2838 | */ | |
2839 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2840 | { | |
2841 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2842 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
2843 | unsigned long flags = 0; |
2844 | int ret = 0; | |
2845 | ||
2846 | spin_lock_irqsave(&hs->lock, flags); | |
2847 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2848 | spin_unlock_irqrestore(&hs->lock, flags); | |
2849 | ||
2850 | return ret; | |
2851 | } | |
2852 | ||
5b7d70c6 BD |
2853 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2854 | .enable = s3c_hsotg_ep_enable, | |
2855 | .disable = s3c_hsotg_ep_disable, | |
2856 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2857 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2858 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2859 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2860 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2861 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2862 | }; |
2863 | ||
41188786 LM |
2864 | /** |
2865 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2866 | * @hsotg: The driver state |
41188786 LM |
2867 | * |
2868 | * A wrapper for platform code responsible for controlling | |
2869 | * low-level USB code | |
2870 | */ | |
941fcce4 | 2871 | static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2872 | { |
2873 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2874 | ||
2875 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 2876 | |
ca2c5ba8 | 2877 | if (hsotg->uphy) |
74084844 | 2878 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 2879 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 2880 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2881 | else { |
2882 | phy_init(hsotg->phy); | |
2883 | phy_power_on(hsotg->phy); | |
2884 | } | |
41188786 LM |
2885 | } |
2886 | ||
2887 | /** | |
2888 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2889 | * @hsotg: The driver state |
41188786 LM |
2890 | * |
2891 | * A wrapper for platform code responsible for controlling | |
2892 | * low-level USB code | |
2893 | */ | |
941fcce4 | 2894 | static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2895 | { |
2896 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2897 | ||
ca2c5ba8 | 2898 | if (hsotg->uphy) |
74084844 | 2899 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 2900 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 2901 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2902 | else { |
2903 | phy_power_off(hsotg->phy); | |
2904 | phy_exit(hsotg->phy); | |
2905 | } | |
41188786 LM |
2906 | } |
2907 | ||
8b9bc460 LM |
2908 | /** |
2909 | * s3c_hsotg_init - initalize the usb core | |
2910 | * @hsotg: The driver state | |
2911 | */ | |
941fcce4 | 2912 | static void s3c_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
2913 | { |
2914 | /* unmask subset of endpoint interrupts */ | |
2915 | ||
47a1685f DN |
2916 | writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
2917 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
2918 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2919 | |
47a1685f DN |
2920 | writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
2921 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
2922 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2923 | |
94cb8fd6 | 2924 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2925 | |
2926 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 2927 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 LM |
2928 | |
2929 | if (0) { | |
2930 | /* post global nak until we're ready */ | |
47a1685f | 2931 | writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, |
94cb8fd6 | 2932 | hsotg->regs + DCTL); |
b3f489b2 LM |
2933 | } |
2934 | ||
2935 | /* setup fifos */ | |
2936 | ||
2937 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2938 | readl(hsotg->regs + GRXFSIZ), |
2939 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2940 | |
2941 | s3c_hsotg_init_fifo(hsotg); | |
2942 | ||
2943 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2944 | writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), |
94cb8fd6 | 2945 | hsotg->regs + GUSBCFG); |
b3f489b2 | 2946 | |
f5090044 GH |
2947 | if (using_dma(hsotg)) |
2948 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
2949 | } |
2950 | ||
8b9bc460 LM |
2951 | /** |
2952 | * s3c_hsotg_udc_start - prepare the udc for work | |
2953 | * @gadget: The usb gadget state | |
2954 | * @driver: The usb gadget driver | |
2955 | * | |
2956 | * Perform initialization to prepare udc device and driver | |
2957 | * to work. | |
2958 | */ | |
f65f0f10 LM |
2959 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2960 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2961 | { |
941fcce4 | 2962 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 2963 | unsigned long flags; |
5b7d70c6 BD |
2964 | int ret; |
2965 | ||
2966 | if (!hsotg) { | |
a023da33 | 2967 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2968 | return -ENODEV; |
2969 | } | |
2970 | ||
2971 | if (!driver) { | |
2972 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2973 | return -EINVAL; | |
2974 | } | |
2975 | ||
7177aed4 | 2976 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2977 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2978 | |
f65f0f10 | 2979 | if (!driver->setup) { |
5b7d70c6 BD |
2980 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2981 | return -EINVAL; | |
2982 | } | |
2983 | ||
7ad8096e | 2984 | mutex_lock(&hsotg->init_mutex); |
5b7d70c6 BD |
2985 | WARN_ON(hsotg->driver); |
2986 | ||
2987 | driver->driver.bus = NULL; | |
2988 | hsotg->driver = driver; | |
7d7b2292 | 2989 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2990 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2991 | ||
d00b4142 RB |
2992 | clk_enable(hsotg->clk); |
2993 | ||
f65f0f10 LM |
2994 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2995 | hsotg->supplies); | |
5b7d70c6 | 2996 | if (ret) { |
f65f0f10 | 2997 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
2998 | goto err; |
2999 | } | |
3000 | ||
c816c47f | 3001 | s3c_hsotg_phy_enable(hsotg); |
f6c01592 GH |
3002 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3003 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3004 | |
5b9451f8 MS |
3005 | spin_lock_irqsave(&hsotg->lock, flags); |
3006 | s3c_hsotg_init(hsotg); | |
3007 | s3c_hsotg_core_init_disconnected(hsotg); | |
dc6e69e6 | 3008 | hsotg->enabled = 0; |
5b9451f8 MS |
3009 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3010 | ||
5b7d70c6 | 3011 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3012 | |
7ad8096e MS |
3013 | mutex_unlock(&hsotg->init_mutex); |
3014 | ||
5b7d70c6 BD |
3015 | return 0; |
3016 | ||
3017 | err: | |
7ad8096e | 3018 | mutex_unlock(&hsotg->init_mutex); |
5b7d70c6 | 3019 | hsotg->driver = NULL; |
5b7d70c6 BD |
3020 | return ret; |
3021 | } | |
3022 | ||
8b9bc460 LM |
3023 | /** |
3024 | * s3c_hsotg_udc_stop - stop the udc | |
3025 | * @gadget: The usb gadget state | |
3026 | * @driver: The usb gadget driver | |
3027 | * | |
3028 | * Stop udc hw block and stay tunned for future transmissions | |
3029 | */ | |
22835b80 | 3030 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3031 | { |
941fcce4 | 3032 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3033 | unsigned long flags = 0; |
5b7d70c6 BD |
3034 | int ep; |
3035 | ||
3036 | if (!hsotg) | |
3037 | return -ENODEV; | |
3038 | ||
7ad8096e MS |
3039 | mutex_lock(&hsotg->init_mutex); |
3040 | ||
5b7d70c6 | 3041 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3042 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3043 | if (hsotg->eps_in[ep]) | |
3044 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3045 | if (hsotg->eps_out[ep]) | |
3046 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3047 | } | |
5b7d70c6 | 3048 | |
2b19a52c LM |
3049 | spin_lock_irqsave(&hsotg->lock, flags); |
3050 | ||
32805c35 | 3051 | hsotg->driver = NULL; |
5b7d70c6 | 3052 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3053 | hsotg->enabled = 0; |
5b7d70c6 | 3054 | |
2b19a52c LM |
3055 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3056 | ||
f6c01592 GH |
3057 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3058 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f MS |
3059 | s3c_hsotg_phy_disable(hsotg); |
3060 | ||
c8c10253 | 3061 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 | 3062 | |
d00b4142 RB |
3063 | clk_disable(hsotg->clk); |
3064 | ||
7ad8096e MS |
3065 | mutex_unlock(&hsotg->init_mutex); |
3066 | ||
5b7d70c6 BD |
3067 | return 0; |
3068 | } | |
5b7d70c6 | 3069 | |
8b9bc460 LM |
3070 | /** |
3071 | * s3c_hsotg_gadget_getframe - read the frame number | |
3072 | * @gadget: The usb gadget state | |
3073 | * | |
3074 | * Read the {micro} frame number | |
3075 | */ | |
5b7d70c6 BD |
3076 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
3077 | { | |
3078 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
3079 | } | |
3080 | ||
a188b689 LM |
3081 | /** |
3082 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
3083 | * @gadget: The usb gadget state | |
3084 | * @is_on: Current state of the USB PHY | |
3085 | * | |
3086 | * Connect/Disconnect the USB PHY pullup | |
3087 | */ | |
3088 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
3089 | { | |
941fcce4 | 3090 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3091 | unsigned long flags = 0; |
3092 | ||
d784f1e5 | 3093 | dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on); |
a188b689 | 3094 | |
7ad8096e | 3095 | mutex_lock(&hsotg->init_mutex); |
a188b689 LM |
3096 | spin_lock_irqsave(&hsotg->lock, flags); |
3097 | if (is_on) { | |
d00b4142 | 3098 | clk_enable(hsotg->clk); |
dc6e69e6 | 3099 | hsotg->enabled = 1; |
ad38dc5d | 3100 | s3c_hsotg_core_connect(hsotg); |
a188b689 | 3101 | } else { |
5b9451f8 | 3102 | s3c_hsotg_core_disconnect(hsotg); |
6d13673e | 3103 | s3c_hsotg_disconnect(hsotg); |
dc6e69e6 | 3104 | hsotg->enabled = 0; |
d00b4142 | 3105 | clk_disable(hsotg->clk); |
a188b689 LM |
3106 | } |
3107 | ||
3108 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3109 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7ad8096e | 3110 | mutex_unlock(&hsotg->init_mutex); |
a188b689 LM |
3111 | |
3112 | return 0; | |
3113 | } | |
3114 | ||
83d98223 GH |
3115 | static int s3c_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
3116 | { | |
3117 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3118 | unsigned long flags; | |
3119 | ||
3120 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3121 | spin_lock_irqsave(&hsotg->lock, flags); | |
3122 | ||
3123 | if (is_active) { | |
3124 | /* Kill any ep0 requests as controller will be reinitialized */ | |
3125 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3126 | s3c_hsotg_core_init_disconnected(hsotg); | |
3127 | if (hsotg->enabled) | |
3128 | s3c_hsotg_core_connect(hsotg); | |
3129 | } else { | |
3130 | s3c_hsotg_core_disconnect(hsotg); | |
3131 | s3c_hsotg_disconnect(hsotg); | |
3132 | } | |
3133 | ||
3134 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3135 | return 0; | |
3136 | } | |
3137 | ||
596d696a GH |
3138 | /** |
3139 | * s3c_hsotg_vbus_draw - report bMaxPower field | |
3140 | * @gadget: The usb gadget state | |
3141 | * @mA: Amount of current | |
3142 | * | |
3143 | * Report how much power the device may consume to the phy. | |
3144 | */ | |
3145 | static int s3c_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
3146 | { | |
3147 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3148 | ||
3149 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3150 | return -ENOTSUPP; | |
3151 | return usb_phy_set_power(hsotg->uphy, mA); | |
3152 | } | |
3153 | ||
eeef4587 | 3154 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 3155 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
3156 | .udc_start = s3c_hsotg_udc_start, |
3157 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 3158 | .pullup = s3c_hsotg_pullup, |
83d98223 | 3159 | .vbus_session = s3c_hsotg_vbus_session, |
596d696a | 3160 | .vbus_draw = s3c_hsotg_vbus_draw, |
5b7d70c6 BD |
3161 | }; |
3162 | ||
3163 | /** | |
3164 | * s3c_hsotg_initep - initialise a single endpoint | |
3165 | * @hsotg: The device state. | |
3166 | * @hs_ep: The endpoint to be initialised. | |
3167 | * @epnum: The endpoint number | |
3168 | * | |
3169 | * Initialise the given endpoint (as part of the probe and device state | |
3170 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3171 | * direction information and other state that may be required. | |
3172 | */ | |
941fcce4 | 3173 | static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 3174 | struct s3c_hsotg_ep *hs_ep, |
c6f5c050 MYK |
3175 | int epnum, |
3176 | bool dir_in) | |
5b7d70c6 | 3177 | { |
5b7d70c6 BD |
3178 | char *dir; |
3179 | ||
3180 | if (epnum == 0) | |
3181 | dir = ""; | |
c6f5c050 | 3182 | else if (dir_in) |
5b7d70c6 | 3183 | dir = "in"; |
c6f5c050 MYK |
3184 | else |
3185 | dir = "out"; | |
5b7d70c6 | 3186 | |
c6f5c050 | 3187 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3188 | hs_ep->index = epnum; |
3189 | ||
3190 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3191 | ||
3192 | INIT_LIST_HEAD(&hs_ep->queue); | |
3193 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3194 | ||
5b7d70c6 BD |
3195 | /* add to the list of endpoints known by the gadget driver */ |
3196 | if (epnum) | |
3197 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3198 | ||
3199 | hs_ep->parent = hsotg; | |
3200 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3201 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
5b7d70c6 BD |
3202 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3203 | ||
8b9bc460 LM |
3204 | /* |
3205 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3206 | * to be something valid. |
3207 | */ | |
3208 | ||
3209 | if (using_dma(hsotg)) { | |
47a1685f | 3210 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 MYK |
3211 | if (dir_in) |
3212 | writel(next, hsotg->regs + DIEPCTL(epnum)); | |
3213 | else | |
3214 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3215 | } |
3216 | } | |
3217 | ||
b3f489b2 LM |
3218 | /** |
3219 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3220 | * @param: The device state | |
3221 | * | |
3222 | * Read the USB core HW configuration registers | |
3223 | */ | |
c6f5c050 | 3224 | static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3225 | { |
c6f5c050 MYK |
3226 | u32 cfg; |
3227 | u32 ep_type; | |
3228 | u32 i; | |
3229 | ||
b3f489b2 | 3230 | /* check hardware configuration */ |
5b7d70c6 | 3231 | |
c6f5c050 MYK |
3232 | cfg = readl(hsotg->regs + GHWCFG2); |
3233 | hsotg->num_of_eps = (cfg >> 10) & 0xF; | |
3234 | /* Add ep0 */ | |
3235 | hsotg->num_of_eps++; | |
10aebc77 | 3236 | |
c6f5c050 MYK |
3237 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep), |
3238 | GFP_KERNEL); | |
3239 | if (!hsotg->eps_in[0]) | |
3240 | return -ENOMEM; | |
3241 | /* Same s3c_hsotg_ep is used in both directions for ep0 */ | |
3242 | hsotg->eps_out[0] = hsotg->eps_in[0]; | |
3243 | ||
3244 | cfg = readl(hsotg->regs + GHWCFG1); | |
3245 | for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) { | |
3246 | ep_type = cfg & 3; | |
3247 | /* Direction in or both */ | |
3248 | if (!(ep_type & 2)) { | |
3249 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
3250 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3251 | if (!hsotg->eps_in[i]) | |
3252 | return -ENOMEM; | |
3253 | } | |
3254 | /* Direction out or both */ | |
3255 | if (!(ep_type & 1)) { | |
3256 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
3257 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3258 | if (!hsotg->eps_out[i]) | |
3259 | return -ENOMEM; | |
3260 | } | |
3261 | } | |
3262 | ||
3263 | cfg = readl(hsotg->regs + GHWCFG3); | |
3264 | hsotg->fifo_mem = (cfg >> 16); | |
10aebc77 | 3265 | |
c6f5c050 MYK |
3266 | cfg = readl(hsotg->regs + GHWCFG4); |
3267 | hsotg->dedicated_fifos = (cfg >> 25) & 1; | |
10aebc77 | 3268 | |
cff9eb75 MS |
3269 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3270 | hsotg->num_of_eps, | |
3271 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3272 | hsotg->fifo_mem); | |
c6f5c050 | 3273 | return 0; |
5b7d70c6 BD |
3274 | } |
3275 | ||
8b9bc460 LM |
3276 | /** |
3277 | * s3c_hsotg_dump - dump state of the udc | |
3278 | * @param: The device state | |
3279 | */ | |
941fcce4 | 3280 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3281 | { |
83a01804 | 3282 | #ifdef DEBUG |
5b7d70c6 BD |
3283 | struct device *dev = hsotg->dev; |
3284 | void __iomem *regs = hsotg->regs; | |
3285 | u32 val; | |
3286 | int idx; | |
3287 | ||
3288 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3289 | readl(regs + DCFG), readl(regs + DCTL), |
3290 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3291 | |
3292 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3293 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3294 | |
3295 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3296 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3297 | |
3298 | /* show periodic fifo settings */ | |
3299 | ||
364f8e93 | 3300 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3301 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3302 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3303 | val >> FIFOSIZE_DEPTH_SHIFT, |
3304 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3305 | } |
3306 | ||
364f8e93 | 3307 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3308 | dev_info(dev, |
3309 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3310 | readl(regs + DIEPCTL(idx)), |
3311 | readl(regs + DIEPTSIZ(idx)), | |
3312 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3313 | |
94cb8fd6 | 3314 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3315 | dev_info(dev, |
3316 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3317 | idx, readl(regs + DOEPCTL(idx)), |
3318 | readl(regs + DOEPTSIZ(idx)), | |
3319 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3320 | |
3321 | } | |
3322 | ||
3323 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3324 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3325 | #endif |
5b7d70c6 BD |
3326 | } |
3327 | ||
9e14d0a5 GH |
3328 | /** |
3329 | * testmode_write - debugfs: change usb test mode | |
3330 | * @seq: The seq file to write to. | |
3331 | * @v: Unused parameter. | |
3332 | * | |
3333 | * This debugfs entry modify the current usb test mode. | |
3334 | */ | |
3335 | static ssize_t testmode_write(struct file *file, const char __user *ubuf, size_t | |
3336 | count, loff_t *ppos) | |
3337 | { | |
3338 | struct seq_file *s = file->private_data; | |
3339 | struct dwc2_hsotg *hsotg = s->private; | |
3340 | unsigned long flags; | |
3341 | u32 testmode = 0; | |
3342 | char buf[32]; | |
3343 | ||
3344 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) | |
3345 | return -EFAULT; | |
3346 | ||
3347 | if (!strncmp(buf, "test_j", 6)) | |
3348 | testmode = TEST_J; | |
3349 | else if (!strncmp(buf, "test_k", 6)) | |
3350 | testmode = TEST_K; | |
3351 | else if (!strncmp(buf, "test_se0_nak", 12)) | |
3352 | testmode = TEST_SE0_NAK; | |
3353 | else if (!strncmp(buf, "test_packet", 11)) | |
3354 | testmode = TEST_PACKET; | |
3355 | else if (!strncmp(buf, "test_force_enable", 17)) | |
3356 | testmode = TEST_FORCE_EN; | |
3357 | else | |
3358 | testmode = 0; | |
3359 | ||
3360 | spin_lock_irqsave(&hsotg->lock, flags); | |
3361 | s3c_hsotg_set_test_mode(hsotg, testmode); | |
3362 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3363 | return count; | |
3364 | } | |
3365 | ||
3366 | /** | |
3367 | * testmode_show - debugfs: show usb test mode state | |
3368 | * @seq: The seq file to write to. | |
3369 | * @v: Unused parameter. | |
3370 | * | |
3371 | * This debugfs entry shows which usb test mode is currently enabled. | |
3372 | */ | |
3373 | static int testmode_show(struct seq_file *s, void *unused) | |
3374 | { | |
3375 | struct dwc2_hsotg *hsotg = s->private; | |
3376 | unsigned long flags; | |
3377 | int dctl; | |
3378 | ||
3379 | spin_lock_irqsave(&hsotg->lock, flags); | |
3380 | dctl = readl(hsotg->regs + DCTL); | |
3381 | dctl &= DCTL_TSTCTL_MASK; | |
3382 | dctl >>= DCTL_TSTCTL_SHIFT; | |
3383 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3384 | ||
3385 | switch (dctl) { | |
3386 | case 0: | |
3387 | seq_puts(s, "no test\n"); | |
3388 | break; | |
3389 | case TEST_J: | |
3390 | seq_puts(s, "test_j\n"); | |
3391 | break; | |
3392 | case TEST_K: | |
3393 | seq_puts(s, "test_k\n"); | |
3394 | break; | |
3395 | case TEST_SE0_NAK: | |
3396 | seq_puts(s, "test_se0_nak\n"); | |
3397 | break; | |
3398 | case TEST_PACKET: | |
3399 | seq_puts(s, "test_packet\n"); | |
3400 | break; | |
3401 | case TEST_FORCE_EN: | |
3402 | seq_puts(s, "test_force_enable\n"); | |
3403 | break; | |
3404 | default: | |
3405 | seq_printf(s, "UNKNOWN %d\n", dctl); | |
3406 | } | |
3407 | ||
3408 | return 0; | |
3409 | } | |
3410 | ||
3411 | static int testmode_open(struct inode *inode, struct file *file) | |
3412 | { | |
3413 | return single_open(file, testmode_show, inode->i_private); | |
3414 | } | |
3415 | ||
3416 | static const struct file_operations testmode_fops = { | |
3417 | .owner = THIS_MODULE, | |
3418 | .open = testmode_open, | |
3419 | .write = testmode_write, | |
3420 | .read = seq_read, | |
3421 | .llseek = seq_lseek, | |
3422 | .release = single_release, | |
3423 | }; | |
3424 | ||
5b7d70c6 BD |
3425 | /** |
3426 | * state_show - debugfs: show overall driver and device state. | |
3427 | * @seq: The seq file to write to. | |
3428 | * @v: Unused parameter. | |
3429 | * | |
3430 | * This debugfs entry shows the overall state of the hardware and | |
3431 | * some general information about each of the endpoints available | |
3432 | * to the system. | |
3433 | */ | |
3434 | static int state_show(struct seq_file *seq, void *v) | |
3435 | { | |
941fcce4 | 3436 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3437 | void __iomem *regs = hsotg->regs; |
3438 | int idx; | |
3439 | ||
3440 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3441 | readl(regs + DCFG), |
3442 | readl(regs + DCTL), | |
3443 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3444 | |
3445 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3446 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3447 | |
3448 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3449 | readl(regs + GINTMSK), |
3450 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3451 | |
3452 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3453 | readl(regs + DAINTMSK), |
3454 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3455 | |
3456 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3457 | readl(regs + GNPTXSTS), |
3458 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3459 | |
a023da33 | 3460 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 | 3461 | |
364f8e93 | 3462 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3463 | u32 in, out; |
3464 | ||
94cb8fd6 LM |
3465 | in = readl(regs + DIEPCTL(idx)); |
3466 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3467 | |
3468 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3469 | idx, in, out); | |
3470 | ||
94cb8fd6 LM |
3471 | in = readl(regs + DIEPTSIZ(idx)); |
3472 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3473 | |
3474 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3475 | in, out); | |
3476 | ||
a023da33 | 3477 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3478 | } |
3479 | ||
3480 | return 0; | |
3481 | } | |
3482 | ||
3483 | static int state_open(struct inode *inode, struct file *file) | |
3484 | { | |
3485 | return single_open(file, state_show, inode->i_private); | |
3486 | } | |
3487 | ||
3488 | static const struct file_operations state_fops = { | |
3489 | .owner = THIS_MODULE, | |
3490 | .open = state_open, | |
3491 | .read = seq_read, | |
3492 | .llseek = seq_lseek, | |
3493 | .release = single_release, | |
3494 | }; | |
3495 | ||
3496 | /** | |
3497 | * fifo_show - debugfs: show the fifo information | |
3498 | * @seq: The seq_file to write data to. | |
3499 | * @v: Unused parameter. | |
3500 | * | |
3501 | * Show the FIFO information for the overall fifo and all the | |
3502 | * periodic transmission FIFOs. | |
8b9bc460 | 3503 | */ |
5b7d70c6 BD |
3504 | static int fifo_show(struct seq_file *seq, void *v) |
3505 | { | |
941fcce4 | 3506 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3507 | void __iomem *regs = hsotg->regs; |
3508 | u32 val; | |
3509 | int idx; | |
3510 | ||
a023da33 | 3511 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3512 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3513 | |
94cb8fd6 | 3514 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3515 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
47a1685f DN |
3516 | val >> FIFOSIZE_DEPTH_SHIFT, |
3517 | val & FIFOSIZE_DEPTH_MASK); | |
5b7d70c6 | 3518 | |
a023da33 | 3519 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 | 3520 | |
364f8e93 | 3521 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3522 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 BD |
3523 | |
3524 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
47a1685f DN |
3525 | val >> FIFOSIZE_DEPTH_SHIFT, |
3526 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3527 | } |
3528 | ||
3529 | return 0; | |
3530 | } | |
3531 | ||
3532 | static int fifo_open(struct inode *inode, struct file *file) | |
3533 | { | |
3534 | return single_open(file, fifo_show, inode->i_private); | |
3535 | } | |
3536 | ||
3537 | static const struct file_operations fifo_fops = { | |
3538 | .owner = THIS_MODULE, | |
3539 | .open = fifo_open, | |
3540 | .read = seq_read, | |
3541 | .llseek = seq_lseek, | |
3542 | .release = single_release, | |
3543 | }; | |
3544 | ||
3545 | ||
3546 | static const char *decode_direction(int is_in) | |
3547 | { | |
3548 | return is_in ? "in" : "out"; | |
3549 | } | |
3550 | ||
3551 | /** | |
3552 | * ep_show - debugfs: show the state of an endpoint. | |
3553 | * @seq: The seq_file to write data to. | |
3554 | * @v: Unused parameter. | |
3555 | * | |
3556 | * This debugfs entry shows the state of the given endpoint (one is | |
3557 | * registered for each available). | |
8b9bc460 | 3558 | */ |
5b7d70c6 BD |
3559 | static int ep_show(struct seq_file *seq, void *v) |
3560 | { | |
3561 | struct s3c_hsotg_ep *ep = seq->private; | |
941fcce4 | 3562 | struct dwc2_hsotg *hsotg = ep->parent; |
5b7d70c6 BD |
3563 | struct s3c_hsotg_req *req; |
3564 | void __iomem *regs = hsotg->regs; | |
3565 | int index = ep->index; | |
3566 | int show_limit = 15; | |
3567 | unsigned long flags; | |
3568 | ||
3569 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3570 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3571 | ||
3572 | /* first show the register state */ | |
3573 | ||
3574 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3575 | readl(regs + DIEPCTL(index)), |
3576 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3577 | |
3578 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3579 | readl(regs + DIEPDMA(index)), |
3580 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3581 | |
3582 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3583 | readl(regs + DIEPINT(index)), |
3584 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3585 | |
3586 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3587 | readl(regs + DIEPTSIZ(index)), |
3588 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3589 | |
a023da33 | 3590 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3591 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3592 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3593 | ||
3594 | seq_printf(seq, "request list (%p,%p):\n", | |
3595 | ep->queue.next, ep->queue.prev); | |
3596 | ||
22258f49 | 3597 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3598 | |
3599 | list_for_each_entry(req, &ep->queue, queue) { | |
3600 | if (--show_limit < 0) { | |
a023da33 | 3601 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3602 | break; |
3603 | } | |
3604 | ||
3605 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3606 | req == ep->req ? '*' : ' ', | |
3607 | req, req->req.length, req->req.buf); | |
3608 | seq_printf(seq, "%d done, res %d\n", | |
3609 | req->req.actual, req->req.status); | |
3610 | } | |
3611 | ||
22258f49 | 3612 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3613 | |
3614 | return 0; | |
3615 | } | |
3616 | ||
3617 | static int ep_open(struct inode *inode, struct file *file) | |
3618 | { | |
3619 | return single_open(file, ep_show, inode->i_private); | |
3620 | } | |
3621 | ||
3622 | static const struct file_operations ep_fops = { | |
3623 | .owner = THIS_MODULE, | |
3624 | .open = ep_open, | |
3625 | .read = seq_read, | |
3626 | .llseek = seq_lseek, | |
3627 | .release = single_release, | |
3628 | }; | |
3629 | ||
3630 | /** | |
3631 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3632 | * @hsotg: The driver state | |
3633 | * | |
3634 | * Create the debugfs files to allow the user to get information | |
3635 | * about the state of the system. The directory name is created | |
3636 | * with the same name as the device itself, in case we end up | |
3637 | * with multiple blocks in future systems. | |
8b9bc460 | 3638 | */ |
941fcce4 | 3639 | static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3640 | { |
3641 | struct dentry *root; | |
3642 | unsigned epidx; | |
3643 | ||
3644 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3645 | hsotg->debug_root = root; | |
3646 | if (IS_ERR(root)) { | |
3647 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3648 | return; | |
3649 | } | |
3650 | ||
3651 | /* create general state file */ | |
3652 | ||
3653 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3654 | hsotg, &state_fops); | |
3655 | ||
3656 | if (IS_ERR(hsotg->debug_file)) | |
3657 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3658 | ||
9e14d0a5 GH |
3659 | hsotg->debug_testmode = debugfs_create_file("testmode", |
3660 | S_IRUGO | S_IWUSR, root, | |
3661 | hsotg, &testmode_fops); | |
3662 | ||
3663 | if (IS_ERR(hsotg->debug_testmode)) | |
3664 | dev_err(hsotg->dev, "%s: failed to create testmode\n", | |
3665 | __func__); | |
3666 | ||
5b7d70c6 BD |
3667 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, |
3668 | hsotg, &fifo_fops); | |
3669 | ||
3670 | if (IS_ERR(hsotg->debug_fifo)) | |
3671 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3672 | ||
c6f5c050 | 3673 | /* Create one file for each out endpoint */ |
b3f489b2 | 3674 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 | 3675 | struct s3c_hsotg_ep *ep; |
5b7d70c6 | 3676 | |
c6f5c050 MYK |
3677 | ep = hsotg->eps_out[epidx]; |
3678 | if (ep) { | |
3679 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3680 | root, ep, &ep_fops); | |
5b7d70c6 | 3681 | |
c6f5c050 MYK |
3682 | if (IS_ERR(ep->debugfs)) |
3683 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3684 | ep->name); | |
3685 | } | |
3686 | } | |
3687 | /* Create one file for each in endpoint. EP0 is handled with out eps */ | |
3688 | for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) { | |
3689 | struct s3c_hsotg_ep *ep; | |
3690 | ||
3691 | ep = hsotg->eps_in[epidx]; | |
3692 | if (ep) { | |
3693 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3694 | root, ep, &ep_fops); | |
3695 | ||
3696 | if (IS_ERR(ep->debugfs)) | |
3697 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3698 | ep->name); | |
3699 | } | |
5b7d70c6 BD |
3700 | } |
3701 | } | |
3702 | ||
3703 | /** | |
3704 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3705 | * @hsotg: The driver state | |
3706 | * | |
3707 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3708 | */ |
941fcce4 | 3709 | static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3710 | { |
3711 | unsigned epidx; | |
3712 | ||
b3f489b2 | 3713 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 MYK |
3714 | if (hsotg->eps_in[epidx]) |
3715 | debugfs_remove(hsotg->eps_in[epidx]->debugfs); | |
3716 | if (hsotg->eps_out[epidx]) | |
3717 | debugfs_remove(hsotg->eps_out[epidx]->debugfs); | |
5b7d70c6 BD |
3718 | } |
3719 | ||
3720 | debugfs_remove(hsotg->debug_file); | |
9e14d0a5 | 3721 | debugfs_remove(hsotg->debug_testmode); |
5b7d70c6 BD |
3722 | debugfs_remove(hsotg->debug_fifo); |
3723 | debugfs_remove(hsotg->debug_root); | |
3724 | } | |
3725 | ||
edd74be8 GH |
3726 | #ifdef CONFIG_OF |
3727 | static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) | |
3728 | { | |
3729 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3730 | u32 len = 0; |
3731 | u32 i = 0; | |
edd74be8 GH |
3732 | |
3733 | /* Enable dma if requested in device tree */ | |
3734 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3735 | |
3736 | /* | |
3737 | * Register TX periodic fifo size per endpoint. | |
3738 | * EP0 is excluded since it has no fifo configuration. | |
3739 | */ | |
3740 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3741 | goto rx_fifo; | |
3742 | ||
3743 | len /= sizeof(u32); | |
3744 | ||
3745 | /* Read tx fifo sizes other than ep0 */ | |
3746 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3747 | &hsotg->g_tx_fifo_sz[1], len)) | |
3748 | goto rx_fifo; | |
3749 | ||
3750 | /* Add ep0 */ | |
3751 | len++; | |
3752 | ||
3753 | /* Make remaining TX fifos unavailable */ | |
3754 | if (len < MAX_EPS_CHANNELS) { | |
3755 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3756 | hsotg->g_tx_fifo_sz[i] = 0; | |
3757 | } | |
3758 | ||
3759 | rx_fifo: | |
3760 | /* Register RX fifo size */ | |
3761 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3762 | ||
3763 | /* Register NPTX fifo size */ | |
3764 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3765 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3766 | } |
3767 | #else | |
3768 | static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } | |
3769 | #endif | |
3770 | ||
8b9bc460 | 3771 | /** |
117777b2 DN |
3772 | * dwc2_gadget_init - init function for gadget |
3773 | * @dwc2: The data structure for the DWC2 driver. | |
3774 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3775 | */ |
117777b2 | 3776 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3777 | { |
117777b2 DN |
3778 | struct device *dev = hsotg->dev; |
3779 | struct s3c_hsotg_plat *plat = dev->platform_data; | |
5b7d70c6 BD |
3780 | int epnum; |
3781 | int ret; | |
fc9a731e | 3782 | int i; |
0a176279 | 3783 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3784 | |
1b59fc7e KD |
3785 | /* Set default UTMI width */ |
3786 | hsotg->phyif = GUSBCFG_PHYIF16; | |
3787 | ||
edd74be8 GH |
3788 | s3c_hsotg_of_probe(hsotg); |
3789 | ||
0a176279 GH |
3790 | /* Initialize to legacy fifo configuration values */ |
3791 | hsotg->g_rx_fifo_sz = 2048; | |
3792 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3793 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3794 | /* Device tree specific probe */ | |
3795 | s3c_hsotg_of_probe(hsotg); | |
3796 | /* Dump fifo information */ | |
3797 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3798 | hsotg->g_np_g_tx_fifo_sz); | |
3799 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3800 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3801 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3802 | hsotg->g_tx_fifo_sz[i]); | |
74084844 | 3803 | /* |
135b3c43 YL |
3804 | * If platform probe couldn't find a generic PHY or an old style |
3805 | * USB PHY, fall back to pdata | |
74084844 | 3806 | */ |
135b3c43 YL |
3807 | if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) { |
3808 | plat = dev_get_platdata(dev); | |
3809 | if (!plat) { | |
3810 | dev_err(dev, | |
3811 | "no platform data or transceiver defined\n"); | |
3812 | return -EPROBE_DEFER; | |
3813 | } | |
3814 | hsotg->plat = plat; | |
3815 | } else if (hsotg->phy) { | |
1b59fc7e KD |
3816 | /* |
3817 | * If using the generic PHY framework, check if the PHY bus | |
3818 | * width is 8-bit and set the phyif appropriately. | |
3819 | */ | |
135b3c43 | 3820 | if (phy_get_bus_width(hsotg->phy) == 8) |
1b59fc7e KD |
3821 | hsotg->phyif = GUSBCFG_PHYIF8; |
3822 | } | |
b2e587db | 3823 | |
117777b2 | 3824 | hsotg->clk = devm_clk_get(dev, "otg"); |
31ee04de | 3825 | if (IS_ERR(hsotg->clk)) { |
8d736d8a | 3826 | hsotg->clk = NULL; |
f415fbd1 | 3827 | dev_dbg(dev, "cannot get otg clock\n"); |
5b7d70c6 BD |
3828 | } |
3829 | ||
d327ab5b | 3830 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3831 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3832 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3833 | |
5b7d70c6 BD |
3834 | /* reset the system */ |
3835 | ||
f415fbd1 DN |
3836 | ret = clk_prepare_enable(hsotg->clk); |
3837 | if (ret) { | |
3838 | dev_err(dev, "failed to enable otg clk\n"); | |
3839 | goto err_clk; | |
3840 | } | |
3841 | ||
31ee04de | 3842 | |
fc9a731e LM |
3843 | /* regulators */ |
3844 | ||
3845 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3846 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3847 | ||
cd76213e | 3848 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3849 | hsotg->supplies); |
3850 | if (ret) { | |
3851 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3852 | goto err_clk; |
fc9a731e LM |
3853 | } |
3854 | ||
3855 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3856 | hsotg->supplies); | |
3857 | ||
3858 | if (ret) { | |
941fcce4 | 3859 | dev_err(dev, "failed to enable supplies: %d\n", ret); |
c139ec27 | 3860 | goto err_clk; |
fc9a731e LM |
3861 | } |
3862 | ||
41188786 LM |
3863 | /* usb phy enable */ |
3864 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3865 | |
1b7a66b4 GH |
3866 | /* |
3867 | * Force Device mode before initialization. | |
3868 | * This allows correctly configuring fifo for device mode. | |
3869 | */ | |
3870 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE); | |
3871 | __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3872 | ||
3873 | /* | |
3874 | * According to Synopsys databook, this sleep is needed for the force | |
3875 | * device mode to take effect. | |
3876 | */ | |
3877 | msleep(25); | |
3878 | ||
5b7d70c6 | 3879 | s3c_hsotg_corereset(hsotg); |
c6f5c050 MYK |
3880 | ret = s3c_hsotg_hw_cfg(hsotg); |
3881 | if (ret) { | |
3882 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
3883 | goto err_clk; | |
3884 | } | |
3885 | ||
cff9eb75 | 3886 | s3c_hsotg_init(hsotg); |
b3f489b2 | 3887 | |
1b7a66b4 GH |
3888 | /* Switch back to default configuration */ |
3889 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3890 | ||
3f95001d MYK |
3891 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3892 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3893 | if (!hsotg->ctrl_buff) { | |
3894 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
3895 | ret = -ENOMEM; | |
3896 | goto err_supplies; | |
3897 | } | |
3898 | ||
3899 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3900 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3901 | if (!hsotg->ep0_buff) { | |
3902 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
3903 | ret = -ENOMEM; | |
3904 | goto err_supplies; | |
3905 | } | |
3906 | ||
db8178c3 DN |
3907 | ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED, |
3908 | dev_name(hsotg->dev), hsotg); | |
eb3c56c5 MS |
3909 | if (ret < 0) { |
3910 | s3c_hsotg_phy_disable(hsotg); | |
3911 | clk_disable_unprepare(hsotg->clk); | |
3912 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3913 | hsotg->supplies); | |
db8178c3 | 3914 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
c139ec27 | 3915 | goto err_supplies; |
eb3c56c5 MS |
3916 | } |
3917 | ||
b3f489b2 LM |
3918 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3919 | ||
3920 | if (hsotg->num_of_eps == 0) { | |
3921 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3922 | ret = -EINVAL; |
b3f489b2 LM |
3923 | goto err_supplies; |
3924 | } | |
3925 | ||
b3f489b2 LM |
3926 | /* setup endpoint information */ |
3927 | ||
3928 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3929 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3930 | |
3931 | /* allocate EP0 request */ | |
3932 | ||
c6f5c050 | 3933 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3934 | GFP_KERNEL); |
3935 | if (!hsotg->ctrl_req) { | |
3936 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3937 | ret = -ENOMEM; |
c6f5c050 | 3938 | goto err_supplies; |
b3f489b2 | 3939 | } |
5b7d70c6 BD |
3940 | |
3941 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3942 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3943 | if (hsotg->eps_in[epnum]) | |
3944 | s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum], | |
3945 | epnum, 1); | |
3946 | if (hsotg->eps_out[epnum]) | |
3947 | s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum], | |
3948 | epnum, 0); | |
3949 | } | |
5b7d70c6 | 3950 | |
f65f0f10 | 3951 | /* disable power and clock */ |
3a8146aa | 3952 | s3c_hsotg_phy_disable(hsotg); |
f65f0f10 LM |
3953 | |
3954 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3955 | hsotg->supplies); | |
3956 | if (ret) { | |
117777b2 | 3957 | dev_err(dev, "failed to disable supplies: %d\n", ret); |
c6f5c050 | 3958 | goto err_supplies; |
f65f0f10 LM |
3959 | } |
3960 | ||
117777b2 | 3961 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3962 | if (ret) |
c6f5c050 | 3963 | goto err_supplies; |
0f91349b | 3964 | |
5b7d70c6 BD |
3965 | s3c_hsotg_create_debug(hsotg); |
3966 | ||
3967 | s3c_hsotg_dump(hsotg); | |
3968 | ||
5b7d70c6 BD |
3969 | return 0; |
3970 | ||
fc9a731e | 3971 | err_supplies: |
41188786 | 3972 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3973 | err_clk: |
1d144c67 | 3974 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3975 | |
5b7d70c6 BD |
3976 | return ret; |
3977 | } | |
117777b2 | 3978 | EXPORT_SYMBOL_GPL(dwc2_gadget_init); |
5b7d70c6 | 3979 | |
8b9bc460 LM |
3980 | /** |
3981 | * s3c_hsotg_remove - remove function for hsotg driver | |
3982 | * @pdev: The platform information for the driver | |
3983 | */ | |
117777b2 | 3984 | int s3c_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3985 | { |
0f91349b | 3986 | usb_del_gadget_udc(&hsotg->gadget); |
5b7d70c6 | 3987 | s3c_hsotg_delete_debug(hsotg); |
04b4a0fc | 3988 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3989 | |
5b7d70c6 BD |
3990 | return 0; |
3991 | } | |
117777b2 | 3992 | EXPORT_SYMBOL_GPL(s3c_hsotg_remove); |
5b7d70c6 | 3993 | |
117777b2 | 3994 | int s3c_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3995 | { |
b83e333a MS |
3996 | unsigned long flags; |
3997 | int ret = 0; | |
3998 | ||
7ad8096e MS |
3999 | mutex_lock(&hsotg->init_mutex); |
4000 | ||
dc6e69e6 MS |
4001 | if (hsotg->driver) { |
4002 | int ep; | |
4003 | ||
b83e333a MS |
4004 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4005 | hsotg->driver->driver.name); | |
4006 | ||
dc6e69e6 MS |
4007 | spin_lock_irqsave(&hsotg->lock, flags); |
4008 | if (hsotg->enabled) | |
4009 | s3c_hsotg_core_disconnect(hsotg); | |
4010 | s3c_hsotg_disconnect(hsotg); | |
4011 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4012 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4013 | |
dc6e69e6 | 4014 | s3c_hsotg_phy_disable(hsotg); |
b83e333a | 4015 | |
c6f5c050 MYK |
4016 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4017 | if (hsotg->eps_in[ep]) | |
4018 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
4019 | if (hsotg->eps_out[ep]) | |
4020 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
4021 | } | |
b83e333a MS |
4022 | |
4023 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
4024 | hsotg->supplies); | |
d00b4142 | 4025 | clk_disable(hsotg->clk); |
b83e333a MS |
4026 | } |
4027 | ||
7ad8096e MS |
4028 | mutex_unlock(&hsotg->init_mutex); |
4029 | ||
b83e333a MS |
4030 | return ret; |
4031 | } | |
117777b2 | 4032 | EXPORT_SYMBOL_GPL(s3c_hsotg_suspend); |
b83e333a | 4033 | |
117777b2 | 4034 | int s3c_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4035 | { |
b83e333a MS |
4036 | unsigned long flags; |
4037 | int ret = 0; | |
4038 | ||
7ad8096e MS |
4039 | mutex_lock(&hsotg->init_mutex); |
4040 | ||
b83e333a MS |
4041 | if (hsotg->driver) { |
4042 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4043 | hsotg->driver->driver.name); | |
d00b4142 RB |
4044 | |
4045 | clk_enable(hsotg->clk); | |
b83e333a | 4046 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
dc6e69e6 | 4047 | hsotg->supplies); |
b83e333a | 4048 | |
dc6e69e6 | 4049 | s3c_hsotg_phy_enable(hsotg); |
b83e333a | 4050 | |
dc6e69e6 MS |
4051 | spin_lock_irqsave(&hsotg->lock, flags); |
4052 | s3c_hsotg_core_init_disconnected(hsotg); | |
4053 | if (hsotg->enabled) | |
4054 | s3c_hsotg_core_connect(hsotg); | |
4055 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4056 | } | |
7ad8096e | 4057 | mutex_unlock(&hsotg->init_mutex); |
b83e333a MS |
4058 | |
4059 | return ret; | |
4060 | } | |
117777b2 | 4061 | EXPORT_SYMBOL_GPL(s3c_hsotg_resume); |