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Commit | Line | Data |
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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
c50f056c | 28 | #include <linux/of_platform.h> |
5b7d70c6 BD |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
b2e587db | 32 | #include <linux/usb/phy.h> |
5b7d70c6 | 33 | |
f7c0b143 | 34 | #include "core.h" |
941fcce4 | 35 | #include "hw.h" |
5b7d70c6 BD |
36 | |
37 | /* conversion functions */ | |
1f91b4cc | 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 39 | { |
1f91b4cc | 40 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
41 | } |
42 | ||
1f91b4cc | 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 44 | { |
1f91b4cc | 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
46 | } |
47 | ||
941fcce4 | 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 49 | { |
941fcce4 | 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
51 | } |
52 | ||
53 | static inline void __orr32(void __iomem *ptr, u32 val) | |
54 | { | |
95c8bc36 | 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __bic32(void __iomem *ptr, u32 val) | |
59 | { | |
95c8bc36 | 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
61 | } |
62 | ||
1f91b4cc | 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
64 | u32 ep_index, u32 dir_in) |
65 | { | |
66 | if (dir_in) | |
67 | return hsotg->eps_in[ep_index]; | |
68 | else | |
69 | return hsotg->eps_out[ep_index]; | |
70 | } | |
71 | ||
997f4f81 | 72 | /* forward declaration of functions */ |
1f91b4cc | 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
74 | |
75 | /** | |
76 | * using_dma - return the DMA status of the driver. | |
77 | * @hsotg: The driver state. | |
78 | * | |
79 | * Return true if we're using DMA. | |
80 | * | |
81 | * Currently, we have the DMA support code worked into everywhere | |
82 | * that needs it, but the AMBA DMA implementation in the hardware can | |
83 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
84 | * as the CDC Ethernet cannot work as they often pass packets which are | |
85 | * not 32bit aligned. | |
86 | * | |
87 | * Unfortunately the choice to use DMA or not is global to the controller | |
88 | * and seems to be only settable when the controller is being put through | |
89 | * a core reset. This means we either need to fix the gadgets to take | |
90 | * account of DMA alignment, or add bounce buffers (yuerk). | |
91 | * | |
edd74be8 | 92 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 93 | */ |
941fcce4 | 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 95 | { |
edd74be8 | 96 | return hsotg->g_using_dma; |
5b7d70c6 BD |
97 | } |
98 | ||
92d1635d VM |
99 | /** |
100 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
101 | * @hs_ep: The endpoint | |
102 | * @increment: The value to increment by | |
103 | * | |
104 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
105 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
106 | */ | |
107 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
108 | { | |
109 | hs_ep->target_frame += hs_ep->interval; | |
110 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
111 | hs_ep->frame_overrun = 1; | |
112 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
113 | } else { | |
114 | hs_ep->frame_overrun = 0; | |
115 | } | |
116 | } | |
117 | ||
5b7d70c6 | 118 | /** |
1f91b4cc | 119 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
120 | * @hsotg: The device state |
121 | * @ints: A bitmask of the interrupts to enable | |
122 | */ | |
1f91b4cc | 123 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 124 | { |
95c8bc36 | 125 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
126 | u32 new_gsintmsk; |
127 | ||
128 | new_gsintmsk = gsintmsk | ints; | |
129 | ||
130 | if (new_gsintmsk != gsintmsk) { | |
131 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 132 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
133 | } |
134 | } | |
135 | ||
136 | /** | |
1f91b4cc | 137 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
138 | * @hsotg: The device state |
139 | * @ints: A bitmask of the interrupts to enable | |
140 | */ | |
1f91b4cc | 141 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 142 | { |
95c8bc36 | 143 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
144 | u32 new_gsintmsk; |
145 | ||
146 | new_gsintmsk = gsintmsk & ~ints; | |
147 | ||
148 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 149 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
150 | } |
151 | ||
152 | /** | |
1f91b4cc | 153 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
154 | * @hsotg: The device state |
155 | * @ep: The endpoint index | |
156 | * @dir_in: True if direction is in. | |
157 | * @en: The enable value, true to enable | |
158 | * | |
159 | * Set or clear the mask for an individual endpoint's interrupt | |
160 | * request. | |
161 | */ | |
1f91b4cc | 162 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
163 | unsigned int ep, unsigned int dir_in, |
164 | unsigned int en) | |
165 | { | |
166 | unsigned long flags; | |
167 | u32 bit = 1 << ep; | |
168 | u32 daint; | |
169 | ||
170 | if (!dir_in) | |
171 | bit <<= 16; | |
172 | ||
173 | local_irq_save(flags); | |
95c8bc36 | 174 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
175 | if (en) |
176 | daint |= bit; | |
177 | else | |
178 | daint &= ~bit; | |
95c8bc36 | 179 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
180 | local_irq_restore(flags); |
181 | } | |
182 | ||
183 | /** | |
1f91b4cc | 184 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
185 | * @hsotg: The device instance. |
186 | */ | |
1f91b4cc | 187 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 188 | { |
0f002d20 BD |
189 | unsigned int ep; |
190 | unsigned int addr; | |
1703a6d3 | 191 | int timeout; |
0f002d20 BD |
192 | u32 val; |
193 | ||
7fcbc95c GH |
194 | /* Reset fifo map if not correctly cleared during previous session */ |
195 | WARN_ON(hsotg->fifo_map); | |
196 | hsotg->fifo_map = 0; | |
197 | ||
0a176279 | 198 | /* set RX/NPTX FIFO sizes */ |
95c8bc36 AS |
199 | dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); |
200 | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
0a176279 GH |
201 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), |
202 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 203 | |
8b9bc460 LM |
204 | /* |
205 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
206 | * block have overlapping default addresses. This also ensures |
207 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
208 | * known values. |
209 | */ | |
0f002d20 BD |
210 | |
211 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 212 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 213 | |
8b9bc460 | 214 | /* |
0a176279 | 215 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
216 | * them to endpoints dynamically according to maxpacket size value of |
217 | * given endpoint. | |
8b9bc460 | 218 | */ |
0a176279 GH |
219 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
220 | if (!hsotg->g_tx_fifo_sz[ep]) | |
221 | continue; | |
0f002d20 | 222 | val = addr; |
0a176279 GH |
223 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
224 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 225 | "insufficient fifo memory"); |
0a176279 | 226 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 227 | |
95c8bc36 | 228 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 229 | } |
1703a6d3 | 230 | |
8b9bc460 LM |
231 | /* |
232 | * according to p428 of the design guide, we need to ensure that | |
233 | * all fifos are flushed before continuing | |
234 | */ | |
1703a6d3 | 235 | |
95c8bc36 | 236 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 237 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
238 | |
239 | /* wait until the fifos are both flushed */ | |
240 | timeout = 100; | |
241 | while (1) { | |
95c8bc36 | 242 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 243 | |
47a1685f | 244 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
245 | break; |
246 | ||
247 | if (--timeout == 0) { | |
248 | dev_err(hsotg->dev, | |
249 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
250 | __func__, val); | |
48b20bcb | 251 | break; |
1703a6d3 BD |
252 | } |
253 | ||
254 | udelay(1); | |
255 | } | |
256 | ||
257 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
258 | } |
259 | ||
260 | /** | |
261 | * @ep: USB endpoint to allocate request for. | |
262 | * @flags: Allocation flags | |
263 | * | |
264 | * Allocate a new USB request structure appropriate for the specified endpoint | |
265 | */ | |
1f91b4cc | 266 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 267 | gfp_t flags) |
5b7d70c6 | 268 | { |
1f91b4cc | 269 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 270 | |
1f91b4cc | 271 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
272 | if (!req) |
273 | return NULL; | |
274 | ||
275 | INIT_LIST_HEAD(&req->queue); | |
276 | ||
5b7d70c6 BD |
277 | return &req->req; |
278 | } | |
279 | ||
280 | /** | |
281 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
282 | * @hs_ep: The endpoint to query. | |
283 | * | |
284 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
285 | * used for an Interrupt or ISO transfer. | |
286 | */ | |
1f91b4cc | 287 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
288 | { |
289 | return hs_ep->periodic; | |
290 | } | |
291 | ||
292 | /** | |
1f91b4cc | 293 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
294 | * @hsotg: The device state. |
295 | * @hs_ep: The endpoint for the request | |
296 | * @hs_req: The request being processed. | |
297 | * | |
1f91b4cc | 298 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 299 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 300 | */ |
1f91b4cc FB |
301 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
302 | struct dwc2_hsotg_ep *hs_ep, | |
303 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
304 | { |
305 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
306 | |
307 | /* ignore this if we're not moving any data */ | |
308 | if (hs_req->req.length == 0) | |
309 | return; | |
310 | ||
17d966a3 | 311 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
312 | } |
313 | ||
314 | /** | |
1f91b4cc | 315 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
316 | * @hsotg: The controller state. |
317 | * @hs_ep: The endpoint we're going to write for. | |
318 | * @hs_req: The request to write data for. | |
319 | * | |
320 | * This is called when the TxFIFO has some space in it to hold a new | |
321 | * transmission and we have something to give it. The actual setup of | |
322 | * the data size is done elsewhere, so all we have to do is to actually | |
323 | * write the data. | |
324 | * | |
325 | * The return value is zero if there is more space (or nothing was done) | |
326 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
327 | * | |
328 | * This routine is only needed for PIO | |
8b9bc460 | 329 | */ |
1f91b4cc FB |
330 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
331 | struct dwc2_hsotg_ep *hs_ep, | |
332 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
333 | { |
334 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 335 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
336 | int buf_pos = hs_req->req.actual; |
337 | int to_write = hs_ep->size_loaded; | |
338 | void *data; | |
339 | int can_write; | |
340 | int pkt_round; | |
4fca54aa | 341 | int max_transfer; |
5b7d70c6 BD |
342 | |
343 | to_write -= (buf_pos - hs_ep->last_load); | |
344 | ||
345 | /* if there's nothing to write, get out early */ | |
346 | if (to_write == 0) | |
347 | return 0; | |
348 | ||
10aebc77 | 349 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 350 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
351 | int size_left; |
352 | int size_done; | |
353 | ||
8b9bc460 LM |
354 | /* |
355 | * work out how much data was loaded so we can calculate | |
356 | * how much data is left in the fifo. | |
357 | */ | |
5b7d70c6 | 358 | |
47a1685f | 359 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 360 | |
8b9bc460 LM |
361 | /* |
362 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
363 | * previous data has been completely sent. |
364 | */ | |
365 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 366 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
367 | return -ENOSPC; |
368 | } | |
369 | ||
5b7d70c6 BD |
370 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
371 | __func__, size_left, | |
372 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
373 | ||
374 | /* how much of the data has moved */ | |
375 | size_done = hs_ep->size_loaded - size_left; | |
376 | ||
377 | /* how much data is left in the fifo */ | |
378 | can_write = hs_ep->fifo_load - size_done; | |
379 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
380 | __func__, can_write); | |
381 | ||
382 | can_write = hs_ep->fifo_size - can_write; | |
383 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
384 | __func__, can_write); | |
385 | ||
386 | if (can_write <= 0) { | |
1f91b4cc | 387 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
388 | return -ENOSPC; |
389 | } | |
10aebc77 | 390 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
95c8bc36 | 391 | can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
392 | |
393 | can_write &= 0xffff; | |
394 | can_write *= 4; | |
5b7d70c6 | 395 | } else { |
47a1685f | 396 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
397 | dev_dbg(hsotg->dev, |
398 | "%s: no queue slots available (0x%08x)\n", | |
399 | __func__, gnptxsts); | |
400 | ||
1f91b4cc | 401 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
402 | return -ENOSPC; |
403 | } | |
404 | ||
47a1685f | 405 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 406 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
407 | } |
408 | ||
4fca54aa RB |
409 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
410 | ||
411 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
412 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 413 | |
8b9bc460 LM |
414 | /* |
415 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
416 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
417 | * fragment of the end of the transfer in it. | |
418 | */ | |
811f3303 | 419 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
420 | can_write = 512; |
421 | ||
8b9bc460 LM |
422 | /* |
423 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 424 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
425 | * doing it. |
426 | */ | |
4fca54aa RB |
427 | if (to_write > max_transfer) { |
428 | to_write = max_transfer; | |
03e10e5a | 429 | |
5cb2ff0c RB |
430 | /* it's needed only when we do not use dedicated fifos */ |
431 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 432 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
433 | periodic ? GINTSTS_PTXFEMP : |
434 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
435 | } |
436 | ||
5b7d70c6 BD |
437 | /* see if we can write data */ |
438 | ||
439 | if (to_write > can_write) { | |
440 | to_write = can_write; | |
4fca54aa | 441 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 442 | |
8b9bc460 LM |
443 | /* |
444 | * Round the write down to an | |
5b7d70c6 BD |
445 | * exact number of packets. |
446 | * | |
447 | * Note, we do not currently check to see if we can ever | |
448 | * write a full packet or not to the FIFO. | |
449 | */ | |
450 | ||
451 | if (pkt_round) | |
452 | to_write -= pkt_round; | |
453 | ||
8b9bc460 LM |
454 | /* |
455 | * enable correct FIFO interrupt to alert us when there | |
456 | * is more room left. | |
457 | */ | |
5b7d70c6 | 458 | |
5cb2ff0c RB |
459 | /* it's needed only when we do not use dedicated fifos */ |
460 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 461 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
462 | periodic ? GINTSTS_PTXFEMP : |
463 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
464 | } |
465 | ||
466 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
467 | to_write, hs_req->req.length, can_write, buf_pos); | |
468 | ||
469 | if (to_write <= 0) | |
470 | return -ENOSPC; | |
471 | ||
472 | hs_req->req.actual = buf_pos + to_write; | |
473 | hs_ep->total_data += to_write; | |
474 | ||
475 | if (periodic) | |
476 | hs_ep->fifo_load += to_write; | |
477 | ||
478 | to_write = DIV_ROUND_UP(to_write, 4); | |
479 | data = hs_req->req.buf + buf_pos; | |
480 | ||
1a7ed5be | 481 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
482 | |
483 | return (to_write >= can_write) ? -ENOSPC : 0; | |
484 | } | |
485 | ||
486 | /** | |
487 | * get_ep_limit - get the maximum data legnth for this endpoint | |
488 | * @hs_ep: The endpoint | |
489 | * | |
490 | * Return the maximum data that can be queued in one go on a given endpoint | |
491 | * so that transfers that are too long can be split. | |
492 | */ | |
1f91b4cc | 493 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
494 | { |
495 | int index = hs_ep->index; | |
496 | unsigned maxsize; | |
497 | unsigned maxpkt; | |
498 | ||
499 | if (index != 0) { | |
47a1685f DN |
500 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
501 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 502 | } else { |
b05ca580 | 503 | maxsize = 64+64; |
66e5c643 | 504 | if (hs_ep->dir_in) |
47a1685f | 505 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 506 | else |
5b7d70c6 | 507 | maxpkt = 2; |
5b7d70c6 BD |
508 | } |
509 | ||
510 | /* we made the constant loading easier above by using +1 */ | |
511 | maxpkt--; | |
512 | maxsize--; | |
513 | ||
8b9bc460 LM |
514 | /* |
515 | * constrain by packet count if maxpkts*pktsize is greater | |
516 | * than the length register size. | |
517 | */ | |
5b7d70c6 BD |
518 | |
519 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
520 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
521 | ||
522 | return maxsize; | |
523 | } | |
524 | ||
381fc8f8 VM |
525 | /** |
526 | * dwc2_hsotg_read_frameno - read current frame number | |
527 | * @hsotg: The device instance | |
528 | * | |
529 | * Return the current frame number | |
530 | */ | |
531 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) | |
532 | { | |
533 | u32 dsts; | |
534 | ||
535 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
536 | dsts &= DSTS_SOFFN_MASK; | |
537 | dsts >>= DSTS_SOFFN_SHIFT; | |
538 | ||
539 | return dsts; | |
540 | } | |
541 | ||
5b7d70c6 | 542 | /** |
1f91b4cc | 543 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
544 | * @hsotg: The controller state. |
545 | * @hs_ep: The endpoint to process a request for | |
546 | * @hs_req: The request to start. | |
547 | * @continuing: True if we are doing more for the current request. | |
548 | * | |
549 | * Start the given request running by setting the endpoint registers | |
550 | * appropriately, and writing any data to the FIFOs. | |
551 | */ | |
1f91b4cc FB |
552 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
553 | struct dwc2_hsotg_ep *hs_ep, | |
554 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
555 | bool continuing) |
556 | { | |
557 | struct usb_request *ureq = &hs_req->req; | |
558 | int index = hs_ep->index; | |
559 | int dir_in = hs_ep->dir_in; | |
560 | u32 epctrl_reg; | |
561 | u32 epsize_reg; | |
562 | u32 epsize; | |
563 | u32 ctrl; | |
564 | unsigned length; | |
565 | unsigned packets; | |
566 | unsigned maxreq; | |
567 | ||
568 | if (index != 0) { | |
569 | if (hs_ep->req && !continuing) { | |
570 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
571 | WARN_ON(1); | |
572 | return; | |
573 | } else if (hs_ep->req != hs_req && continuing) { | |
574 | dev_err(hsotg->dev, | |
575 | "%s: continue different req\n", __func__); | |
576 | WARN_ON(1); | |
577 | return; | |
578 | } | |
579 | } | |
580 | ||
94cb8fd6 LM |
581 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
582 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
583 | |
584 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 585 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
586 | hs_ep->dir_in ? "in" : "out"); |
587 | ||
9c39ddc6 | 588 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 589 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 590 | |
b2d4c54e | 591 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
592 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
593 | return; | |
594 | } | |
595 | ||
5b7d70c6 | 596 | length = ureq->length - ureq->actual; |
71225bee LM |
597 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
598 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
599 | |
600 | maxreq = get_ep_limit(hs_ep); | |
601 | if (length > maxreq) { | |
602 | int round = maxreq % hs_ep->ep.maxpacket; | |
603 | ||
604 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
605 | __func__, length, maxreq, round); | |
606 | ||
607 | /* round down to multiple of packets */ | |
608 | if (round) | |
609 | maxreq -= round; | |
610 | ||
611 | length = maxreq; | |
612 | } | |
613 | ||
614 | if (length) | |
615 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
616 | else | |
617 | packets = 1; /* send one packet if length is zero. */ | |
618 | ||
4fca54aa RB |
619 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
620 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
621 | return; | |
622 | } | |
623 | ||
5b7d70c6 | 624 | if (dir_in && index != 0) |
4fca54aa | 625 | if (hs_ep->isochronous) |
47a1685f | 626 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 627 | else |
47a1685f | 628 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
629 | else |
630 | epsize = 0; | |
631 | ||
f71b5e25 MYK |
632 | /* |
633 | * zero length packet should be programmed on its own and should not | |
634 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
635 | */ | |
636 | if (dir_in && ureq->zero && !continuing) { | |
637 | /* Test if zlp is actually required. */ | |
638 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
639 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 640 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
641 | } |
642 | ||
47a1685f DN |
643 | epsize |= DXEPTSIZ_PKTCNT(packets); |
644 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
645 | |
646 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
647 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
648 | ||
649 | /* store the request as the current one we're doing */ | |
650 | hs_ep->req = hs_req; | |
651 | ||
652 | /* write size / packets */ | |
95c8bc36 | 653 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 654 | |
db1d8ba3 | 655 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
656 | unsigned int dma_reg; |
657 | ||
8b9bc460 LM |
658 | /* |
659 | * write DMA address to control register, buffer already | |
1f91b4cc | 660 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 661 | */ |
5b7d70c6 | 662 | |
94cb8fd6 | 663 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 664 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 665 | |
0cc4cf6f | 666 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 667 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
668 | } |
669 | ||
47a1685f | 670 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 671 | |
fe0b94ab | 672 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
673 | |
674 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 675 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 676 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 677 | |
5b7d70c6 | 678 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 679 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 680 | |
8b9bc460 LM |
681 | /* |
682 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 683 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
684 | * this information. |
685 | */ | |
5b7d70c6 BD |
686 | hs_ep->size_loaded = length; |
687 | hs_ep->last_load = ureq->actual; | |
688 | ||
689 | if (dir_in && !using_dma(hsotg)) { | |
690 | /* set these anyway, we may need them for non-periodic in */ | |
691 | hs_ep->fifo_load = 0; | |
692 | ||
1f91b4cc | 693 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
694 | } |
695 | ||
8b9bc460 LM |
696 | /* |
697 | * Note, trying to clear the NAK here causes problems with transmit | |
698 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
699 | */ | |
5b7d70c6 BD |
700 | |
701 | /* check ep is enabled */ | |
95c8bc36 | 702 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 703 | dev_dbg(hsotg->dev, |
47a1685f | 704 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 705 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 706 | |
47a1685f | 707 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 708 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
709 | |
710 | /* enable ep interrupts */ | |
1f91b4cc | 711 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
712 | } |
713 | ||
714 | /** | |
1f91b4cc | 715 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
716 | * @hsotg: The device state. |
717 | * @hs_ep: The endpoint the request is on. | |
718 | * @req: The request being processed. | |
719 | * | |
720 | * We've been asked to queue a request, so ensure that the memory buffer | |
721 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
722 | * then ensure the buffer has been synced to memory. If our buffer has no | |
723 | * DMA memory, then we map the memory and mark our request to allow us to | |
724 | * cleanup on completion. | |
8b9bc460 | 725 | */ |
1f91b4cc FB |
726 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
727 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
728 | struct usb_request *req) |
729 | { | |
1f91b4cc | 730 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 731 | int ret; |
5b7d70c6 BD |
732 | |
733 | /* if the length is zero, ignore the DMA data */ | |
734 | if (hs_req->req.length == 0) | |
735 | return 0; | |
736 | ||
e58ebcd1 FB |
737 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
738 | if (ret) | |
739 | goto dma_error; | |
5b7d70c6 BD |
740 | |
741 | return 0; | |
742 | ||
743 | dma_error: | |
744 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
745 | __func__, req->buf, req->length); | |
746 | ||
747 | return -EIO; | |
748 | } | |
749 | ||
1f91b4cc FB |
750 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
751 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
752 | { |
753 | void *req_buf = hs_req->req.buf; | |
754 | ||
755 | /* If dma is not being used or buffer is aligned */ | |
756 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
757 | return 0; | |
758 | ||
759 | WARN_ON(hs_req->saved_req_buf); | |
760 | ||
761 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
762 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
763 | ||
764 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
765 | if (!hs_req->req.buf) { | |
766 | hs_req->req.buf = req_buf; | |
767 | dev_err(hsotg->dev, | |
768 | "%s: unable to allocate memory for bounce buffer\n", | |
769 | __func__); | |
770 | return -ENOMEM; | |
771 | } | |
772 | ||
773 | /* Save actual buffer */ | |
774 | hs_req->saved_req_buf = req_buf; | |
775 | ||
776 | if (hs_ep->dir_in) | |
777 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
778 | return 0; | |
779 | } | |
780 | ||
1f91b4cc FB |
781 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
782 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
783 | { |
784 | /* If dma is not being used or buffer was aligned */ | |
785 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
786 | return; | |
787 | ||
788 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
789 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
790 | ||
791 | /* Copy data from bounce buffer on successful out transfer */ | |
792 | if (!hs_ep->dir_in && !hs_req->req.status) | |
793 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
794 | hs_req->req.actual); | |
795 | ||
796 | /* Free bounce buffer */ | |
797 | kfree(hs_req->req.buf); | |
798 | ||
799 | hs_req->req.buf = hs_req->saved_req_buf; | |
800 | hs_req->saved_req_buf = NULL; | |
801 | } | |
802 | ||
381fc8f8 VM |
803 | /** |
804 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
805 | * @hs_ep: The driver endpoint to check | |
806 | * | |
807 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
808 | * corresponding transfer. | |
809 | */ | |
810 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
811 | { | |
812 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
813 | u32 target_frame = hs_ep->target_frame; | |
814 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
815 | bool frame_overrun = hs_ep->frame_overrun; | |
816 | ||
817 | if (!frame_overrun && current_frame >= target_frame) | |
818 | return true; | |
819 | ||
820 | if (frame_overrun && current_frame >= target_frame && | |
821 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
822 | return true; | |
823 | ||
824 | return false; | |
825 | } | |
826 | ||
1f91b4cc | 827 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
828 | gfp_t gfp_flags) |
829 | { | |
1f91b4cc FB |
830 | struct dwc2_hsotg_req *hs_req = our_req(req); |
831 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 832 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 833 | bool first; |
7d24c1b5 | 834 | int ret; |
5b7d70c6 BD |
835 | |
836 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
837 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
838 | req->zero, req->short_not_ok); | |
839 | ||
7ababa92 GH |
840 | /* Prevent new request submission when controller is suspended */ |
841 | if (hs->lx_state == DWC2_L2) { | |
842 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
843 | __func__); | |
844 | return -EAGAIN; | |
845 | } | |
846 | ||
5b7d70c6 BD |
847 | /* initialise status of the request */ |
848 | INIT_LIST_HEAD(&hs_req->queue); | |
849 | req->actual = 0; | |
850 | req->status = -EINPROGRESS; | |
851 | ||
1f91b4cc | 852 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
853 | if (ret) |
854 | return ret; | |
855 | ||
5b7d70c6 BD |
856 | /* if we're using DMA, sync the buffers as necessary */ |
857 | if (using_dma(hs)) { | |
1f91b4cc | 858 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
859 | if (ret) |
860 | return ret; | |
861 | } | |
862 | ||
5b7d70c6 BD |
863 | first = list_empty(&hs_ep->queue); |
864 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
865 | ||
866 | if (first) | |
1f91b4cc | 867 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
5b7d70c6 | 868 | |
5b7d70c6 BD |
869 | return 0; |
870 | } | |
871 | ||
1f91b4cc | 872 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
873 | gfp_t gfp_flags) |
874 | { | |
1f91b4cc | 875 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 876 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
877 | unsigned long flags = 0; |
878 | int ret = 0; | |
879 | ||
880 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 881 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
882 | spin_unlock_irqrestore(&hs->lock, flags); |
883 | ||
884 | return ret; | |
885 | } | |
886 | ||
1f91b4cc | 887 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
888 | struct usb_request *req) |
889 | { | |
1f91b4cc | 890 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
891 | |
892 | kfree(hs_req); | |
893 | } | |
894 | ||
895 | /** | |
1f91b4cc | 896 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
897 | * @ep: The endpoint the request was on. |
898 | * @req: The request completed. | |
899 | * | |
900 | * Called on completion of any requests the driver itself | |
901 | * submitted that need cleaning up. | |
902 | */ | |
1f91b4cc | 903 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
904 | struct usb_request *req) |
905 | { | |
1f91b4cc | 906 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 907 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
908 | |
909 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
910 | ||
1f91b4cc | 911 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
912 | } |
913 | ||
914 | /** | |
915 | * ep_from_windex - convert control wIndex value to endpoint | |
916 | * @hsotg: The driver state. | |
917 | * @windex: The control request wIndex field (in host order). | |
918 | * | |
919 | * Convert the given wIndex into a pointer to an driver endpoint | |
920 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 921 | */ |
1f91b4cc | 922 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
923 | u32 windex) |
924 | { | |
1f91b4cc | 925 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
926 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
927 | int idx = windex & 0x7F; | |
928 | ||
929 | if (windex >= 0x100) | |
930 | return NULL; | |
931 | ||
b3f489b2 | 932 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
933 | return NULL; |
934 | ||
c6f5c050 MYK |
935 | ep = index_to_ep(hsotg, idx, dir); |
936 | ||
5b7d70c6 BD |
937 | if (idx && ep->dir_in != dir) |
938 | return NULL; | |
939 | ||
940 | return ep; | |
941 | } | |
942 | ||
9e14d0a5 | 943 | /** |
1f91b4cc | 944 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
945 | * @hsotg: The driver state. |
946 | * @testmode: requested usb test mode | |
947 | * Enable usb Test Mode requested by the Host. | |
948 | */ | |
1f91b4cc | 949 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 950 | { |
95c8bc36 | 951 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
952 | |
953 | dctl &= ~DCTL_TSTCTL_MASK; | |
954 | switch (testmode) { | |
955 | case TEST_J: | |
956 | case TEST_K: | |
957 | case TEST_SE0_NAK: | |
958 | case TEST_PACKET: | |
959 | case TEST_FORCE_EN: | |
960 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
961 | break; | |
962 | default: | |
963 | return -EINVAL; | |
964 | } | |
95c8bc36 | 965 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
966 | return 0; |
967 | } | |
968 | ||
5b7d70c6 | 969 | /** |
1f91b4cc | 970 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
971 | * @hsotg: The device state |
972 | * @ep: Endpoint 0 | |
973 | * @buff: Buffer for request | |
974 | * @length: Length of reply. | |
975 | * | |
976 | * Create a request and queue it on the given endpoint. This is useful as | |
977 | * an internal method of sending replies to certain control requests, etc. | |
978 | */ | |
1f91b4cc FB |
979 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
980 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
981 | void *buff, |
982 | int length) | |
983 | { | |
984 | struct usb_request *req; | |
985 | int ret; | |
986 | ||
987 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
988 | ||
1f91b4cc | 989 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
990 | hsotg->ep0_reply = req; |
991 | if (!req) { | |
992 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
993 | return -ENOMEM; | |
994 | } | |
995 | ||
996 | req->buf = hsotg->ep0_buff; | |
997 | req->length = length; | |
f71b5e25 MYK |
998 | /* |
999 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1000 | * STATUS stage. | |
1001 | */ | |
1002 | req->zero = 0; | |
1f91b4cc | 1003 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1004 | |
1005 | if (length) | |
1006 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1007 | |
1f91b4cc | 1008 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1009 | if (ret) { |
1010 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1011 | return ret; | |
1012 | } | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | /** | |
1f91b4cc | 1018 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1019 | * @hsotg: The device state |
1020 | * @ctrl: USB control request | |
1021 | */ | |
1f91b4cc | 1022 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1023 | struct usb_ctrlrequest *ctrl) |
1024 | { | |
1f91b4cc FB |
1025 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1026 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1027 | __le16 reply; |
1028 | int ret; | |
1029 | ||
1030 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1031 | ||
1032 | if (!ep0->dir_in) { | |
1033 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1034 | return -EINVAL; | |
1035 | } | |
1036 | ||
1037 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1038 | case USB_RECIP_DEVICE: | |
1039 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
1040 | * bit 1 => remote wakeup */ | |
1041 | break; | |
1042 | ||
1043 | case USB_RECIP_INTERFACE: | |
1044 | /* currently, the data result should be zero */ | |
1045 | reply = cpu_to_le16(0); | |
1046 | break; | |
1047 | ||
1048 | case USB_RECIP_ENDPOINT: | |
1049 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1050 | if (!ep) | |
1051 | return -ENOENT; | |
1052 | ||
1053 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1054 | break; | |
1055 | ||
1056 | default: | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1061 | return -EINVAL; | |
1062 | ||
1f91b4cc | 1063 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1064 | if (ret) { |
1065 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1066 | return ret; | |
1067 | } | |
1068 | ||
1069 | return 1; | |
1070 | } | |
1071 | ||
51da43b5 | 1072 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1073 | |
9c39ddc6 AT |
1074 | /** |
1075 | * get_ep_head - return the first request on the endpoint | |
1076 | * @hs_ep: The controller endpoint to get | |
1077 | * | |
1078 | * Get the first request on the endpoint. | |
1079 | */ | |
1f91b4cc | 1080 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 AT |
1081 | { |
1082 | if (list_empty(&hs_ep->queue)) | |
1083 | return NULL; | |
1084 | ||
1f91b4cc | 1085 | return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue); |
9c39ddc6 AT |
1086 | } |
1087 | ||
41cc4cd2 VM |
1088 | /** |
1089 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1090 | * @hs_ep: Endpoint structure | |
1091 | * | |
1092 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1093 | * in its handler. Hence we need to unmask it here to be able to do | |
1094 | * resynchronization. | |
1095 | */ | |
1096 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1097 | { | |
1098 | u32 mask; | |
1099 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1100 | int dir_in = hs_ep->dir_in; | |
1101 | struct dwc2_hsotg_req *hs_req; | |
1102 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1103 | ||
1104 | if (!list_empty(&hs_ep->queue)) { | |
1105 | hs_req = get_ep_head(hs_ep); | |
1106 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1107 | return; | |
1108 | } | |
1109 | if (!hs_ep->isochronous) | |
1110 | return; | |
1111 | ||
1112 | if (dir_in) { | |
1113 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1114 | __func__); | |
1115 | } else { | |
1116 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1117 | __func__); | |
1118 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1119 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1120 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1121 | } | |
1122 | } | |
1123 | ||
5b7d70c6 | 1124 | /** |
1f91b4cc | 1125 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1126 | * @hsotg: The device state |
1127 | * @ctrl: USB control request | |
1128 | */ | |
1f91b4cc | 1129 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1130 | struct usb_ctrlrequest *ctrl) |
1131 | { | |
1f91b4cc FB |
1132 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1133 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1134 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1135 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1136 | int ret; |
bd9ef7bf | 1137 | bool halted; |
9e14d0a5 GH |
1138 | u32 recip; |
1139 | u32 wValue; | |
1140 | u32 wIndex; | |
5b7d70c6 BD |
1141 | |
1142 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1143 | __func__, set ? "SET" : "CLEAR"); | |
1144 | ||
9e14d0a5 GH |
1145 | wValue = le16_to_cpu(ctrl->wValue); |
1146 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1147 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1148 | ||
1149 | switch (recip) { | |
1150 | case USB_RECIP_DEVICE: | |
1151 | switch (wValue) { | |
1152 | case USB_DEVICE_TEST_MODE: | |
1153 | if ((wIndex & 0xff) != 0) | |
1154 | return -EINVAL; | |
1155 | if (!set) | |
1156 | return -EINVAL; | |
1157 | ||
1158 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1159 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1160 | if (ret) { |
1161 | dev_err(hsotg->dev, | |
1162 | "%s: failed to send reply\n", __func__); | |
1163 | return ret; | |
1164 | } | |
1165 | break; | |
1166 | default: | |
1167 | return -ENOENT; | |
1168 | } | |
1169 | break; | |
1170 | ||
1171 | case USB_RECIP_ENDPOINT: | |
1172 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1173 | if (!ep) { |
1174 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1175 | __func__, wIndex); |
5b7d70c6 BD |
1176 | return -ENOENT; |
1177 | } | |
1178 | ||
9e14d0a5 | 1179 | switch (wValue) { |
5b7d70c6 | 1180 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1181 | halted = ep->halted; |
1182 | ||
51da43b5 | 1183 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1184 | |
1f91b4cc | 1185 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1186 | if (ret) { |
1187 | dev_err(hsotg->dev, | |
1188 | "%s: failed to send reply\n", __func__); | |
1189 | return ret; | |
1190 | } | |
9c39ddc6 | 1191 | |
bd9ef7bf RB |
1192 | /* |
1193 | * we have to complete all requests for ep if it was | |
1194 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1195 | */ | |
1196 | ||
1197 | if (!set && halted) { | |
9c39ddc6 AT |
1198 | /* |
1199 | * If we have request in progress, | |
1200 | * then complete it | |
1201 | */ | |
1202 | if (ep->req) { | |
1203 | hs_req = ep->req; | |
1204 | ep->req = NULL; | |
1205 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1206 | if (hs_req->req.complete) { |
1207 | spin_unlock(&hsotg->lock); | |
1208 | usb_gadget_giveback_request( | |
1209 | &ep->ep, &hs_req->req); | |
1210 | spin_lock(&hsotg->lock); | |
1211 | } | |
9c39ddc6 AT |
1212 | } |
1213 | ||
1214 | /* If we have pending request, then start it */ | |
c00dd4a6 | 1215 | if (!ep->req) { |
41cc4cd2 | 1216 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1217 | } |
1218 | } | |
1219 | ||
5b7d70c6 BD |
1220 | break; |
1221 | ||
1222 | default: | |
1223 | return -ENOENT; | |
1224 | } | |
9e14d0a5 GH |
1225 | break; |
1226 | default: | |
1227 | return -ENOENT; | |
1228 | } | |
5b7d70c6 BD |
1229 | return 1; |
1230 | } | |
1231 | ||
1f91b4cc | 1232 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1233 | |
c9f721b2 | 1234 | /** |
1f91b4cc | 1235 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1236 | * @hsotg: The device state |
1237 | * | |
1238 | * Set stall for ep0 as response for setup request. | |
1239 | */ | |
1f91b4cc | 1240 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1241 | { |
1f91b4cc | 1242 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1243 | u32 reg; |
1244 | u32 ctrl; | |
1245 | ||
1246 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1247 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1248 | ||
1249 | /* | |
1250 | * DxEPCTL_Stall will be cleared by EP once it has | |
1251 | * taken effect, so no need to clear later. | |
1252 | */ | |
1253 | ||
95c8bc36 | 1254 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1255 | ctrl |= DXEPCTL_STALL; |
1256 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1257 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1258 | |
1259 | dev_dbg(hsotg->dev, | |
47a1685f | 1260 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1261 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1262 | |
1263 | /* | |
1264 | * complete won't be called, so we enqueue | |
1265 | * setup request here | |
1266 | */ | |
1f91b4cc | 1267 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1268 | } |
1269 | ||
5b7d70c6 | 1270 | /** |
1f91b4cc | 1271 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1272 | * @hsotg: The device state |
1273 | * @ctrl: The control request received | |
1274 | * | |
1275 | * The controller has received the SETUP phase of a control request, and | |
1276 | * needs to work out what to do next (and whether to pass it on to the | |
1277 | * gadget driver). | |
1278 | */ | |
1f91b4cc | 1279 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1280 | struct usb_ctrlrequest *ctrl) |
1281 | { | |
1f91b4cc | 1282 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1283 | int ret = 0; |
1284 | u32 dcfg; | |
1285 | ||
e525e743 MYK |
1286 | dev_dbg(hsotg->dev, |
1287 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1288 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1289 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1290 | |
fe0b94ab MYK |
1291 | if (ctrl->wLength == 0) { |
1292 | ep0->dir_in = 1; | |
1293 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1294 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1295 | ep0->dir_in = 1; |
fe0b94ab MYK |
1296 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1297 | } else { | |
1298 | ep0->dir_in = 0; | |
1299 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1300 | } | |
5b7d70c6 BD |
1301 | |
1302 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1303 | switch (ctrl->bRequest) { | |
1304 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1305 | hsotg->connected = 1; |
95c8bc36 | 1306 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1307 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1308 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1309 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1310 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1311 | |
1312 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1313 | ||
1f91b4cc | 1314 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1315 | return; |
1316 | ||
1317 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1318 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1319 | break; |
1320 | ||
1321 | case USB_REQ_CLEAR_FEATURE: | |
1322 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1323 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1324 | break; |
1325 | } | |
1326 | } | |
1327 | ||
1328 | /* as a fallback, try delivering it to the driver to deal with */ | |
1329 | ||
1330 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1331 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1332 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1333 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1334 | if (ret < 0) |
1335 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1336 | } | |
1337 | ||
8b9bc460 LM |
1338 | /* |
1339 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1340 | * so respond with a STALL for the status stage to indicate failure. |
1341 | */ | |
1342 | ||
c9f721b2 | 1343 | if (ret < 0) |
1f91b4cc | 1344 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1345 | } |
1346 | ||
5b7d70c6 | 1347 | /** |
1f91b4cc | 1348 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1349 | * @ep: The endpoint the request was on. |
1350 | * @req: The request completed. | |
1351 | * | |
1352 | * Called on completion of any requests the driver itself submitted for | |
1353 | * EP0 setup packets | |
1354 | */ | |
1f91b4cc | 1355 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1356 | struct usb_request *req) |
1357 | { | |
1f91b4cc | 1358 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1359 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1360 | |
1361 | if (req->status < 0) { | |
1362 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1363 | return; | |
1364 | } | |
1365 | ||
93f599f2 | 1366 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1367 | if (req->actual == 0) |
1f91b4cc | 1368 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1369 | else |
1f91b4cc | 1370 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1371 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1372 | } |
1373 | ||
1374 | /** | |
1f91b4cc | 1375 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1376 | * @hsotg: The device state. |
1377 | * | |
1378 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1379 | * received from the host. | |
1380 | */ | |
1f91b4cc | 1381 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1382 | { |
1383 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1384 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1385 | int ret; |
1386 | ||
1387 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1388 | ||
1389 | req->zero = 0; | |
1390 | req->length = 8; | |
1391 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1392 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1393 | |
1394 | if (!list_empty(&hs_req->queue)) { | |
1395 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1396 | return; | |
1397 | } | |
1398 | ||
c6f5c050 | 1399 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1400 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1401 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1402 | |
1f91b4cc | 1403 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1404 | if (ret < 0) { |
1405 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1406 | /* |
1407 | * Don't think there's much we can do other than watch the | |
1408 | * driver fail. | |
1409 | */ | |
5b7d70c6 BD |
1410 | } |
1411 | } | |
1412 | ||
1f91b4cc FB |
1413 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1414 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1415 | { |
1416 | u32 ctrl; | |
1417 | u8 index = hs_ep->index; | |
1418 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1419 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1420 | ||
ccb34a91 MYK |
1421 | if (hs_ep->dir_in) |
1422 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1423 | index); | |
1424 | else | |
1425 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1426 | index); | |
fe0b94ab | 1427 | |
95c8bc36 AS |
1428 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1429 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1430 | epsiz_reg); | |
fe0b94ab | 1431 | |
95c8bc36 | 1432 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1433 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1434 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1435 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1436 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1437 | } |
1438 | ||
5b7d70c6 | 1439 | /** |
1f91b4cc | 1440 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1441 | * @hsotg: The device state. |
1442 | * @hs_ep: The endpoint the request was on. | |
1443 | * @hs_req: The request to complete. | |
1444 | * @result: The result code (0 => Ok, otherwise errno) | |
1445 | * | |
1446 | * The given request has finished, so call the necessary completion | |
1447 | * if it has one and then look to see if we can start a new request | |
1448 | * on the endpoint. | |
1449 | * | |
1450 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1451 | */ |
1f91b4cc FB |
1452 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1453 | struct dwc2_hsotg_ep *hs_ep, | |
1454 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1455 | int result) |
1456 | { | |
5b7d70c6 BD |
1457 | |
1458 | if (!hs_req) { | |
1459 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1460 | return; | |
1461 | } | |
1462 | ||
1463 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1464 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1465 | ||
8b9bc460 LM |
1466 | /* |
1467 | * only replace the status if we've not already set an error | |
1468 | * from a previous transaction | |
1469 | */ | |
5b7d70c6 BD |
1470 | |
1471 | if (hs_req->req.status == -EINPROGRESS) | |
1472 | hs_req->req.status = result; | |
1473 | ||
44583fec YL |
1474 | if (using_dma(hsotg)) |
1475 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1476 | ||
1f91b4cc | 1477 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1478 | |
5b7d70c6 BD |
1479 | hs_ep->req = NULL; |
1480 | list_del_init(&hs_req->queue); | |
1481 | ||
8b9bc460 LM |
1482 | /* |
1483 | * call the complete request with the locks off, just in case the | |
1484 | * request tries to queue more work for this endpoint. | |
1485 | */ | |
5b7d70c6 BD |
1486 | |
1487 | if (hs_req->req.complete) { | |
22258f49 | 1488 | spin_unlock(&hsotg->lock); |
304f7e5e | 1489 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1490 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1491 | } |
1492 | ||
8b9bc460 LM |
1493 | /* |
1494 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1495 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1496 | * so be careful when doing this. |
1497 | */ | |
5b7d70c6 BD |
1498 | |
1499 | if (!hs_ep->req && result >= 0) { | |
41cc4cd2 | 1500 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
1501 | } |
1502 | } | |
1503 | ||
5b7d70c6 | 1504 | /** |
1f91b4cc | 1505 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1506 | * @hsotg: The device state. |
1507 | * @ep_idx: The endpoint index for the data | |
1508 | * @size: The size of data in the fifo, in bytes | |
1509 | * | |
1510 | * The FIFO status shows there is data to read from the FIFO for a given | |
1511 | * endpoint, so sort out whether we need to read the data into a request | |
1512 | * that has been made for that endpoint. | |
1513 | */ | |
1f91b4cc | 1514 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1515 | { |
1f91b4cc FB |
1516 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1517 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1518 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1519 | int to_read; |
1520 | int max_req; | |
1521 | int read_ptr; | |
1522 | ||
22258f49 | 1523 | |
5b7d70c6 | 1524 | if (!hs_req) { |
95c8bc36 | 1525 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1526 | int ptr; |
1527 | ||
6b448af4 | 1528 | dev_dbg(hsotg->dev, |
47a1685f | 1529 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1530 | __func__, size, ep_idx, epctl); |
1531 | ||
1532 | /* dump the data from the FIFO, we've nothing we can do */ | |
1533 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1534 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1535 | |
1536 | return; | |
1537 | } | |
1538 | ||
5b7d70c6 BD |
1539 | to_read = size; |
1540 | read_ptr = hs_req->req.actual; | |
1541 | max_req = hs_req->req.length - read_ptr; | |
1542 | ||
a33e7136 BD |
1543 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1544 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1545 | ||
5b7d70c6 | 1546 | if (to_read > max_req) { |
8b9bc460 LM |
1547 | /* |
1548 | * more data appeared than we where willing | |
5b7d70c6 BD |
1549 | * to deal with in this request. |
1550 | */ | |
1551 | ||
1552 | /* currently we don't deal this */ | |
1553 | WARN_ON_ONCE(1); | |
1554 | } | |
1555 | ||
5b7d70c6 BD |
1556 | hs_ep->total_data += to_read; |
1557 | hs_req->req.actual += to_read; | |
1558 | to_read = DIV_ROUND_UP(to_read, 4); | |
1559 | ||
8b9bc460 LM |
1560 | /* |
1561 | * note, we might over-write the buffer end by 3 bytes depending on | |
1562 | * alignment of the data. | |
1563 | */ | |
1a7ed5be | 1564 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1565 | } |
1566 | ||
1567 | /** | |
1f91b4cc | 1568 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1569 | * @hsotg: The device instance |
fe0b94ab | 1570 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1571 | * |
1572 | * Generate a zero-length IN packet request for terminating a SETUP | |
1573 | * transaction. | |
1574 | * | |
1575 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1576 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1577 | * the TxFIFO. |
1578 | */ | |
1f91b4cc | 1579 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1580 | { |
c6f5c050 | 1581 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1582 | hsotg->eps_out[0]->dir_in = dir_in; |
1583 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1584 | |
1f91b4cc | 1585 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1586 | } |
1587 | ||
ec1f9d9f RB |
1588 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
1589 | u32 epctl_reg) | |
1590 | { | |
1591 | u32 ctrl; | |
1592 | ||
1593 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
1594 | if (ctrl & DXEPCTL_EOFRNUM) | |
1595 | ctrl |= DXEPCTL_SETEVENFR; | |
1596 | else | |
1597 | ctrl |= DXEPCTL_SETODDFR; | |
1598 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
1599 | } | |
1600 | ||
5b7d70c6 | 1601 | /** |
1f91b4cc | 1602 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1603 | * @hsotg: The device instance |
1604 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1605 | * |
1606 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1607 | * transfer for an OUT endpoint has been completed, either by a short | |
1608 | * packet or by the finish of a transfer. | |
8b9bc460 | 1609 | */ |
1f91b4cc | 1610 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1611 | { |
95c8bc36 | 1612 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1613 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1614 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1615 | struct usb_request *req = &hs_req->req; |
47a1685f | 1616 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1617 | int result = 0; |
1618 | ||
1619 | if (!hs_req) { | |
1620 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1621 | return; | |
1622 | } | |
1623 | ||
fe0b94ab MYK |
1624 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1625 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1626 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1627 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1628 | return; |
1629 | } | |
1630 | ||
5b7d70c6 | 1631 | if (using_dma(hsotg)) { |
5b7d70c6 | 1632 | unsigned size_done; |
5b7d70c6 | 1633 | |
8b9bc460 LM |
1634 | /* |
1635 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1636 | * is left in the endpoint size register and then working it |
1637 | * out from the amount we loaded for the transfer. | |
1638 | * | |
1639 | * We need to do this as DMA pointers are always 32bit aligned | |
1640 | * so may overshoot/undershoot the transfer. | |
1641 | */ | |
1642 | ||
5b7d70c6 BD |
1643 | size_done = hs_ep->size_loaded - size_left; |
1644 | size_done += hs_ep->last_load; | |
1645 | ||
1646 | req->actual = size_done; | |
1647 | } | |
1648 | ||
a33e7136 BD |
1649 | /* if there is more request to do, schedule new transfer */ |
1650 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1651 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1652 | return; |
1653 | } | |
1654 | ||
5b7d70c6 BD |
1655 | if (req->actual < req->length && req->short_not_ok) { |
1656 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1657 | __func__, req->actual, req->length); | |
1658 | ||
8b9bc460 LM |
1659 | /* |
1660 | * todo - what should we return here? there's no one else | |
1661 | * even bothering to check the status. | |
1662 | */ | |
5b7d70c6 BD |
1663 | } |
1664 | ||
fe0b94ab MYK |
1665 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1666 | /* Move to STATUS IN */ | |
1f91b4cc | 1667 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1668 | return; |
5b7d70c6 BD |
1669 | } |
1670 | ||
ec1f9d9f RB |
1671 | /* |
1672 | * Slave mode OUT transfers do not go through XferComplete so | |
1673 | * adjust the ISOC parity here. | |
1674 | */ | |
1675 | if (!using_dma(hsotg)) { | |
1676 | hs_ep->has_correct_parity = 1; | |
1677 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
1678 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
1679 | } | |
1680 | ||
1f91b4cc | 1681 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1682 | } |
1683 | ||
5b7d70c6 | 1684 | /** |
1f91b4cc | 1685 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1686 | * @hsotg: The device instance |
1687 | * | |
1688 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1689 | * that requires processing, so find out what is in there and do the | |
1690 | * appropriate read. | |
1691 | * | |
25985edc | 1692 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1693 | * chunks, so if you have x packets received on an endpoint you'll get x |
1694 | * FIFO events delivered, each with a packet's worth of data in it. | |
1695 | * | |
1696 | * When using DMA, we should not be processing events from the RXFIFO | |
1697 | * as the actual data should be sent to the memory directly and we turn | |
1698 | * on the completion interrupts to get notifications of transfer completion. | |
1699 | */ | |
1f91b4cc | 1700 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1701 | { |
95c8bc36 | 1702 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1703 | u32 epnum, status, size; |
1704 | ||
1705 | WARN_ON(using_dma(hsotg)); | |
1706 | ||
47a1685f DN |
1707 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1708 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1709 | |
47a1685f DN |
1710 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1711 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1712 | |
d7c747c5 | 1713 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1714 | __func__, grxstsr, size, epnum); |
1715 | ||
47a1685f DN |
1716 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1717 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1718 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1719 | break; |
1720 | ||
47a1685f | 1721 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1722 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1723 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1724 | |
1725 | if (!using_dma(hsotg)) | |
1f91b4cc | 1726 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1727 | break; |
1728 | ||
47a1685f | 1729 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1730 | dev_dbg(hsotg->dev, |
1731 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1732 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1733 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1734 | /* |
1f91b4cc | 1735 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1736 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1737 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1738 | */ | |
1739 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1740 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1741 | break; |
1742 | ||
47a1685f | 1743 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1744 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1745 | break; |
1746 | ||
47a1685f | 1747 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1748 | dev_dbg(hsotg->dev, |
1749 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1750 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1751 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1752 | |
fe0b94ab MYK |
1753 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1754 | ||
1f91b4cc | 1755 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1756 | break; |
1757 | ||
1758 | default: | |
1759 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1760 | __func__, grxstsr); | |
1761 | ||
1f91b4cc | 1762 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1763 | break; |
1764 | } | |
1765 | } | |
1766 | ||
1767 | /** | |
1f91b4cc | 1768 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1769 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1770 | */ |
1f91b4cc | 1771 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1772 | { |
1773 | switch (mps) { | |
1774 | case 64: | |
94cb8fd6 | 1775 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1776 | case 32: |
94cb8fd6 | 1777 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1778 | case 16: |
94cb8fd6 | 1779 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1780 | case 8: |
94cb8fd6 | 1781 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1782 | } |
1783 | ||
1784 | /* bad max packet size, warn and return invalid result */ | |
1785 | WARN_ON(1); | |
1786 | return (u32)-1; | |
1787 | } | |
1788 | ||
1789 | /** | |
1f91b4cc | 1790 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1791 | * @hsotg: The driver state. |
1792 | * @ep: The index number of the endpoint | |
1793 | * @mps: The maximum packet size in bytes | |
1794 | * | |
1795 | * Configure the maximum packet size for the given endpoint, updating | |
1796 | * the hardware control registers to reflect this. | |
1797 | */ | |
1f91b4cc | 1798 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1799 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1800 | { |
1f91b4cc | 1801 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1802 | void __iomem *regs = hsotg->regs; |
1803 | u32 mpsval; | |
4fca54aa | 1804 | u32 mcval; |
5b7d70c6 BD |
1805 | u32 reg; |
1806 | ||
c6f5c050 MYK |
1807 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1808 | if (!hs_ep) | |
1809 | return; | |
1810 | ||
5b7d70c6 BD |
1811 | if (ep == 0) { |
1812 | /* EP0 is a special case */ | |
1f91b4cc | 1813 | mpsval = dwc2_hsotg_ep0_mps(mps); |
5b7d70c6 BD |
1814 | if (mpsval > 3) |
1815 | goto bad_mps; | |
e9edd199 | 1816 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1817 | hs_ep->mc = 1; |
5b7d70c6 | 1818 | } else { |
47a1685f | 1819 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1820 | if (mpsval > 1024) |
5b7d70c6 | 1821 | goto bad_mps; |
4fca54aa RB |
1822 | mcval = ((mps >> 11) & 0x3) + 1; |
1823 | hs_ep->mc = mcval; | |
1824 | if (mcval > 3) | |
1825 | goto bad_mps; | |
e9edd199 | 1826 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1827 | } |
1828 | ||
c6f5c050 | 1829 | if (dir_in) { |
95c8bc36 | 1830 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 MYK |
1831 | reg &= ~DXEPCTL_MPS_MASK; |
1832 | reg |= mpsval; | |
95c8bc36 | 1833 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1834 | } else { |
95c8bc36 | 1835 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1836 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1837 | reg |= mpsval; |
95c8bc36 | 1838 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1839 | } |
5b7d70c6 BD |
1840 | |
1841 | return; | |
1842 | ||
1843 | bad_mps: | |
1844 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1845 | } | |
1846 | ||
9c39ddc6 | 1847 | /** |
1f91b4cc | 1848 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1849 | * @hsotg: The driver state |
1850 | * @idx: The index for the endpoint (0..15) | |
1851 | */ | |
1f91b4cc | 1852 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1853 | { |
1854 | int timeout; | |
1855 | int val; | |
1856 | ||
95c8bc36 AS |
1857 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1858 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1859 | |
1860 | /* wait until the fifo is flushed */ | |
1861 | timeout = 100; | |
1862 | ||
1863 | while (1) { | |
95c8bc36 | 1864 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1865 | |
47a1685f | 1866 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1867 | break; |
1868 | ||
1869 | if (--timeout == 0) { | |
1870 | dev_err(hsotg->dev, | |
1871 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1872 | __func__, val); | |
e0cbe595 | 1873 | break; |
9c39ddc6 AT |
1874 | } |
1875 | ||
1876 | udelay(1); | |
1877 | } | |
1878 | } | |
5b7d70c6 BD |
1879 | |
1880 | /** | |
1f91b4cc | 1881 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1882 | * @hsotg: The driver state |
1883 | * @hs_ep: The driver endpoint to check. | |
1884 | * | |
1885 | * Check to see if there is a request that has data to send, and if so | |
1886 | * make an attempt to write data into the FIFO. | |
1887 | */ | |
1f91b4cc FB |
1888 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1889 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1890 | { |
1f91b4cc | 1891 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1892 | |
afcf4169 RB |
1893 | if (!hs_ep->dir_in || !hs_req) { |
1894 | /** | |
1895 | * if request is not enqueued, we disable interrupts | |
1896 | * for endpoints, excepting ep0 | |
1897 | */ | |
1898 | if (hs_ep->index != 0) | |
1f91b4cc | 1899 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1900 | hs_ep->dir_in, 0); |
5b7d70c6 | 1901 | return 0; |
afcf4169 | 1902 | } |
5b7d70c6 BD |
1903 | |
1904 | if (hs_req->req.actual < hs_req->req.length) { | |
1905 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1906 | hs_ep->index); | |
1f91b4cc | 1907 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1908 | } |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1913 | /** | |
1f91b4cc | 1914 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1915 | * @hsotg: The device state. |
1916 | * @hs_ep: The endpoint that has just completed. | |
1917 | * | |
1918 | * An IN transfer has been completed, update the transfer's state and then | |
1919 | * call the relevant completion routines. | |
1920 | */ | |
1f91b4cc FB |
1921 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1922 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1923 | { |
1f91b4cc | 1924 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1925 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1926 | int size_left, size_done; |
1927 | ||
1928 | if (!hs_req) { | |
1929 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1930 | return; | |
1931 | } | |
1932 | ||
d3ca0259 | 1933 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1934 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1935 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1936 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1937 | if (hsotg->test_mode) { |
1938 | int ret; | |
1939 | ||
1f91b4cc | 1940 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1941 | if (ret < 0) { |
1942 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1943 | hsotg->test_mode); | |
1f91b4cc | 1944 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1945 | return; |
1946 | } | |
1947 | } | |
1f91b4cc | 1948 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1949 | return; |
1950 | } | |
1951 | ||
8b9bc460 LM |
1952 | /* |
1953 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1954 | * in the endpoint size register and then working it out from |
1955 | * the amount we loaded for the transfer. | |
1956 | * | |
1957 | * We do this even for DMA, as the transfer may have incremented | |
1958 | * past the end of the buffer (DMA transfers are always 32bit | |
1959 | * aligned). | |
1960 | */ | |
1961 | ||
47a1685f | 1962 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1963 | |
1964 | size_done = hs_ep->size_loaded - size_left; | |
1965 | size_done += hs_ep->last_load; | |
1966 | ||
1967 | if (hs_req->req.actual != size_done) | |
1968 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1969 | __func__, hs_req->req.actual, size_done); | |
1970 | ||
1971 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1972 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1973 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1974 | ||
5b7d70c6 BD |
1975 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1976 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 1977 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
1978 | return; |
1979 | } | |
1980 | ||
f71b5e25 | 1981 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1982 | if (hs_ep->send_zlp) { |
1f91b4cc | 1983 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1984 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1985 | /* transfer will be completed on next complete interrupt */ |
1986 | return; | |
1987 | } | |
1988 | ||
fe0b94ab MYK |
1989 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1990 | /* Move to STATUS OUT */ | |
1f91b4cc | 1991 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
1992 | return; |
1993 | } | |
1994 | ||
1f91b4cc | 1995 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1996 | } |
1997 | ||
32601588 VM |
1998 | /** |
1999 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2000 | * @hsotg: The device state. | |
2001 | * @idx: Index of ep. | |
2002 | * @dir_in: Endpoint direction 1-in 0-out. | |
2003 | * | |
2004 | * Reads for endpoint with given index and direction, by masking | |
2005 | * epint_reg with coresponding mask. | |
2006 | */ | |
2007 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2008 | unsigned int idx, int dir_in) | |
2009 | { | |
2010 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2011 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2012 | u32 ints; | |
2013 | u32 mask; | |
2014 | u32 diepempmsk; | |
2015 | ||
2016 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2017 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2018 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2019 | mask |= DXEPINT_SETUP_RCVD; | |
2020 | ||
2021 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2022 | ints &= mask; | |
2023 | return ints; | |
2024 | } | |
2025 | ||
bd9971f0 VM |
2026 | /** |
2027 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2028 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2029 | * | |
2030 | * This interrupt indicates that the endpoint has been disabled per the | |
2031 | * application's request. | |
2032 | * | |
2033 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2034 | * in case of ISOC completes current request. | |
2035 | * | |
2036 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2037 | * request starts it. | |
2038 | */ | |
2039 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2040 | { | |
2041 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2042 | struct dwc2_hsotg_req *hs_req; | |
2043 | unsigned char idx = hs_ep->index; | |
2044 | int dir_in = hs_ep->dir_in; | |
2045 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2046 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2047 | ||
2048 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2049 | ||
2050 | if (dir_in) { | |
2051 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2052 | ||
2053 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2054 | ||
2055 | if (hs_ep->isochronous) { | |
2056 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2057 | return; | |
2058 | } | |
2059 | ||
2060 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2061 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2062 | ||
2063 | dctl |= DCTL_CGNPINNAK; | |
2064 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2065 | } | |
2066 | return; | |
2067 | } | |
2068 | ||
2069 | if (dctl & DCTL_GOUTNAKSTS) { | |
2070 | dctl |= DCTL_CGOUTNAK; | |
2071 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2072 | } | |
2073 | ||
2074 | if (!hs_ep->isochronous) | |
2075 | return; | |
2076 | ||
2077 | if (list_empty(&hs_ep->queue)) { | |
2078 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2079 | __func__, hs_ep); | |
2080 | return; | |
2081 | } | |
2082 | ||
2083 | do { | |
2084 | hs_req = get_ep_head(hs_ep); | |
2085 | if (hs_req) | |
2086 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2087 | -ENODATA); | |
2088 | dwc2_gadget_incr_frame_num(hs_ep); | |
2089 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2090 | ||
2091 | dwc2_gadget_start_next_request(hs_ep); | |
2092 | } | |
2093 | ||
5321922c VM |
2094 | /** |
2095 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2096 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2097 | * | |
2098 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2099 | * first out token received from host while corresponding EP is disabled. | |
2100 | * | |
2101 | * Device does not know initial frame in which out token will come. For this | |
2102 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2103 | * getting this interrupt SW starts calculation for next transfer frame. | |
2104 | */ | |
2105 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2106 | { | |
2107 | struct dwc2_hsotg *hsotg = ep->parent; | |
2108 | int dir_in = ep->dir_in; | |
2109 | u32 doepmsk; | |
2110 | ||
2111 | if (dir_in || !ep->isochronous) | |
2112 | return; | |
2113 | ||
2114 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); | |
2115 | ||
2116 | if (ep->interval > 1 && | |
2117 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2118 | u32 dsts; | |
2119 | u32 ctrl; | |
2120 | ||
2121 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2122 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2123 | dwc2_gadget_incr_frame_num(ep); | |
2124 | ||
2125 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2126 | if (ep->target_frame & 0x1) | |
2127 | ctrl |= DXEPCTL_SETODDFR; | |
2128 | else | |
2129 | ctrl |= DXEPCTL_SETEVENFR; | |
2130 | ||
2131 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2132 | } | |
2133 | ||
2134 | dwc2_gadget_start_next_request(ep); | |
2135 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2136 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2137 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2138 | } | |
2139 | ||
2140 | /** | |
2141 | * dwc2_gadget_handle_nak - handle NAK interrupt | |
2142 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2143 | * | |
2144 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2145 | * first IN token received from host while corresponding EP is disabled. | |
2146 | * | |
2147 | * Device does not know when first one token will arrive from host. On first | |
2148 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2149 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2150 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2151 | * interrupt to obtain frame in which token has come and then based on the | |
2152 | * interval calculates next frame for transfer. | |
2153 | */ | |
2154 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) | |
2155 | { | |
2156 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2157 | int dir_in = hs_ep->dir_in; | |
2158 | ||
2159 | if (!dir_in || !hs_ep->isochronous) | |
2160 | return; | |
2161 | ||
2162 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2163 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2164 | if (hs_ep->interval > 1) { | |
2165 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2166 | DIEPCTL(hs_ep->index)); | |
2167 | if (hs_ep->target_frame & 0x1) | |
2168 | ctrl |= DXEPCTL_SETODDFR; | |
2169 | else | |
2170 | ctrl |= DXEPCTL_SETEVENFR; | |
2171 | ||
2172 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2173 | } | |
2174 | ||
2175 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2176 | get_ep_head(hs_ep), 0); | |
2177 | } | |
2178 | ||
2179 | dwc2_gadget_incr_frame_num(hs_ep); | |
2180 | } | |
2181 | ||
5b7d70c6 | 2182 | /** |
1f91b4cc | 2183 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2184 | * @hsotg: The driver state |
2185 | * @idx: The index for the endpoint (0..15) | |
2186 | * @dir_in: Set if this is an IN endpoint | |
2187 | * | |
2188 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2189 | */ |
1f91b4cc | 2190 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
2191 | int dir_in) |
2192 | { | |
1f91b4cc | 2193 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2194 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2195 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2196 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2197 | u32 ints; |
1479e841 | 2198 | u32 ctrl; |
5b7d70c6 | 2199 | |
32601588 | 2200 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2201 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2202 | |
a3395f0d | 2203 | /* Clear endpoint interrupts */ |
95c8bc36 | 2204 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2205 | |
c6f5c050 MYK |
2206 | if (!hs_ep) { |
2207 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
2208 | __func__, idx, dir_in ? "in" : "out"); | |
2209 | return; | |
2210 | } | |
2211 | ||
5b7d70c6 BD |
2212 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2213 | __func__, idx, dir_in ? "in" : "out", ints); | |
2214 | ||
b787d755 MYK |
2215 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2216 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2217 | ints &= ~DXEPINT_XFERCOMPL; | |
2218 | ||
47a1685f | 2219 | if (ints & DXEPINT_XFERCOMPL) { |
ec1f9d9f RB |
2220 | hs_ep->has_correct_parity = 1; |
2221 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
2222 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
1479e841 | 2223 | |
5b7d70c6 | 2224 | dev_dbg(hsotg->dev, |
47a1685f | 2225 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2226 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2227 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2228 | |
8b9bc460 LM |
2229 | /* |
2230 | * we get OutDone from the FIFO, so we only need to look | |
2231 | * at completing IN requests here | |
2232 | */ | |
5b7d70c6 | 2233 | if (dir_in) { |
1f91b4cc | 2234 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
5b7d70c6 | 2235 | |
c9a64ea8 | 2236 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2237 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2238 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2239 | /* |
2240 | * We're using DMA, we need to fire an OutDone here | |
2241 | * as we ignore the RXFIFO. | |
2242 | */ | |
5b7d70c6 | 2243 | |
1f91b4cc | 2244 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2245 | } |
5b7d70c6 BD |
2246 | } |
2247 | ||
bd9971f0 VM |
2248 | if (ints & DXEPINT_EPDISBLD) |
2249 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2250 | |
5321922c VM |
2251 | if (ints & DXEPINT_OUTTKNEPDIS) |
2252 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2253 | ||
2254 | if (ints & DXEPINT_NAKINTRPT) | |
2255 | dwc2_gadget_handle_nak(hs_ep); | |
2256 | ||
47a1685f | 2257 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2258 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2259 | |
47a1685f | 2260 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2261 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2262 | ||
2263 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2264 | /* |
2265 | * this is the notification we've received a | |
5b7d70c6 BD |
2266 | * setup packet. In non-DMA mode we'd get this |
2267 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2268 | * the setup here. |
2269 | */ | |
5b7d70c6 BD |
2270 | |
2271 | if (dir_in) | |
2272 | WARN_ON_ONCE(1); | |
2273 | else | |
1f91b4cc | 2274 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2275 | } |
5b7d70c6 BD |
2276 | } |
2277 | ||
47a1685f | 2278 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2279 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2280 | |
1479e841 | 2281 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2282 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2283 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2284 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2285 | __func__, idx); | |
5b7d70c6 BD |
2286 | } |
2287 | ||
2288 | /* this probably means something bad is happening */ | |
26ddef5d | 2289 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2290 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2291 | __func__, idx); | |
5b7d70c6 | 2292 | } |
10aebc77 BD |
2293 | |
2294 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2295 | if (hsotg->dedicated_fifos && | |
26ddef5d | 2296 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
2297 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2298 | __func__, idx); | |
70fa030f | 2299 | if (!using_dma(hsotg)) |
1f91b4cc | 2300 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2301 | } |
5b7d70c6 | 2302 | } |
5b7d70c6 BD |
2303 | } |
2304 | ||
2305 | /** | |
1f91b4cc | 2306 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2307 | * @hsotg: The device state. |
2308 | * | |
2309 | * Handle updating the device settings after the enumeration phase has | |
2310 | * been completed. | |
8b9bc460 | 2311 | */ |
1f91b4cc | 2312 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2313 | { |
95c8bc36 | 2314 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2315 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2316 | |
8b9bc460 LM |
2317 | /* |
2318 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2319 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2320 | * we connected at. |
2321 | */ | |
5b7d70c6 BD |
2322 | |
2323 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2324 | ||
8b9bc460 LM |
2325 | /* |
2326 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2327 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2328 | * not advertise a 64byte MPS on EP0. |
2329 | */ | |
5b7d70c6 BD |
2330 | |
2331 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 2332 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
2333 | case DSTS_ENUMSPD_FS: |
2334 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2335 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2336 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2337 | ep_mps = 1023; |
5b7d70c6 BD |
2338 | break; |
2339 | ||
47a1685f | 2340 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2341 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2342 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2343 | ep_mps = 1024; |
5b7d70c6 BD |
2344 | break; |
2345 | ||
47a1685f | 2346 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2347 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2348 | /* |
2349 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2350 | * moment, and the documentation seems to imply that it isn't |
2351 | * supported by the PHYs on some of the devices. | |
2352 | */ | |
2353 | break; | |
2354 | } | |
e538dfda MN |
2355 | dev_info(hsotg->dev, "new device is %s\n", |
2356 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2357 | |
8b9bc460 LM |
2358 | /* |
2359 | * we should now know the maximum packet size for an | |
2360 | * endpoint, so set the endpoints to a default value. | |
2361 | */ | |
5b7d70c6 BD |
2362 | |
2363 | if (ep0_mps) { | |
2364 | int i; | |
c6f5c050 | 2365 | /* Initialize ep0 for both in and out directions */ |
1f91b4cc FB |
2366 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); |
2367 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
c6f5c050 MYK |
2368 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2369 | if (hsotg->eps_in[i]) | |
1f91b4cc | 2370 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); |
c6f5c050 | 2371 | if (hsotg->eps_out[i]) |
1f91b4cc | 2372 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); |
c6f5c050 | 2373 | } |
5b7d70c6 BD |
2374 | } |
2375 | ||
2376 | /* ensure after enumeration our EP0 is active */ | |
2377 | ||
1f91b4cc | 2378 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2379 | |
2380 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2381 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2382 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2383 | } |
2384 | ||
2385 | /** | |
2386 | * kill_all_requests - remove all requests from the endpoint's queue | |
2387 | * @hsotg: The device state. | |
2388 | * @ep: The endpoint the requests may be on. | |
2389 | * @result: The result code to use. | |
5b7d70c6 BD |
2390 | * |
2391 | * Go through the requests on the given endpoint and mark them | |
2392 | * completed with the given result code. | |
2393 | */ | |
941fcce4 | 2394 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2395 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2396 | int result) |
5b7d70c6 | 2397 | { |
1f91b4cc | 2398 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2399 | unsigned size; |
5b7d70c6 | 2400 | |
6b448af4 | 2401 | ep->req = NULL; |
5b7d70c6 | 2402 | |
6b448af4 | 2403 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2404 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2405 | result); |
6b448af4 | 2406 | |
b203d0a2 RB |
2407 | if (!hsotg->dedicated_fifos) |
2408 | return; | |
95c8bc36 | 2409 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; |
b203d0a2 | 2410 | if (size < ep->fifo_size) |
1f91b4cc | 2411 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2412 | } |
2413 | ||
5b7d70c6 | 2414 | /** |
1f91b4cc | 2415 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2416 | * @hsotg: The device state. |
2417 | * | |
5e891342 LM |
2418 | * The device has been disconnected. Remove all current |
2419 | * transactions and signal the gadget driver that this | |
2420 | * has happened. | |
8b9bc460 | 2421 | */ |
1f91b4cc | 2422 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2423 | { |
2424 | unsigned ep; | |
2425 | ||
4ace06e8 MS |
2426 | if (!hsotg->connected) |
2427 | return; | |
2428 | ||
2429 | hsotg->connected = 0; | |
9e14d0a5 | 2430 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2431 | |
2432 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2433 | if (hsotg->eps_in[ep]) | |
2434 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2435 | -ESHUTDOWN); | |
2436 | if (hsotg->eps_out[ep]) | |
2437 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2438 | -ESHUTDOWN); | |
2439 | } | |
5b7d70c6 BD |
2440 | |
2441 | call_gadget(hsotg, disconnect); | |
065d3931 | 2442 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2443 | } |
2444 | ||
2445 | /** | |
1f91b4cc | 2446 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2447 | * @hsotg: The device state: |
2448 | * @periodic: True if this is a periodic FIFO interrupt | |
2449 | */ | |
1f91b4cc | 2450 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2451 | { |
1f91b4cc | 2452 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2453 | int epno, ret; |
2454 | ||
2455 | /* look through for any more data to transmit */ | |
b3f489b2 | 2456 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2457 | ep = index_to_ep(hsotg, epno, 1); |
2458 | ||
2459 | if (!ep) | |
2460 | continue; | |
5b7d70c6 BD |
2461 | |
2462 | if (!ep->dir_in) | |
2463 | continue; | |
2464 | ||
2465 | if ((periodic && !ep->periodic) || | |
2466 | (!periodic && ep->periodic)) | |
2467 | continue; | |
2468 | ||
1f91b4cc | 2469 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2470 | if (ret < 0) |
2471 | break; | |
2472 | } | |
2473 | } | |
2474 | ||
5b7d70c6 | 2475 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2476 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2477 | GINTSTS_PTXFEMP | \ | |
2478 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2479 | |
8b9bc460 | 2480 | /** |
1f91b4cc | 2481 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2482 | * @hsotg: The device state |
2483 | * | |
2484 | * Issue a soft reset to the core, and await the core finishing it. | |
2485 | */ | |
1f91b4cc | 2486 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2487 | bool is_usb_reset) |
308d734e | 2488 | { |
1ee6903b | 2489 | u32 intmsk; |
643cc4de | 2490 | u32 val; |
ecd9a7ad | 2491 | u32 usbcfg; |
643cc4de | 2492 | |
5390d438 MYK |
2493 | /* Kill any ep0 requests as controller will be reinitialized */ |
2494 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2495 | ||
643cc4de | 2496 | if (!is_usb_reset) |
241729ba | 2497 | if (dwc2_core_reset(hsotg)) |
86de4895 | 2498 | return; |
308d734e LM |
2499 | |
2500 | /* | |
2501 | * we must now enable ep0 ready for host detection and then | |
2502 | * set configuration. | |
2503 | */ | |
2504 | ||
ecd9a7ad PR |
2505 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
2506 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2507 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
2508 | GUSBCFG_HNPCAP); | |
2509 | ||
308d734e | 2510 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 2511 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
2512 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
2513 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
2514 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
308d734e | 2515 | |
1f91b4cc | 2516 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2517 | |
643cc4de GH |
2518 | if (!is_usb_reset) |
2519 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2520 | |
95c8bc36 | 2521 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2522 | |
2523 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2524 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2525 | |
2526 | /* Clear any pending interrupts */ | |
95c8bc36 | 2527 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2528 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2529 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2530 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2531 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
ec1f9d9f RB |
2532 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
2533 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b GH |
2534 | |
2535 | if (hsotg->core_params->external_id_pin_ctl <= 0) | |
2536 | intmsk |= GINTSTS_CONIDSTSCHNG; | |
2537 | ||
2538 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2539 | |
2540 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2541 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2542 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2543 | hsotg->regs + GAHBCFG); | |
308d734e | 2544 | else |
95c8bc36 AS |
2545 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2546 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2547 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2548 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2549 | |
2550 | /* | |
8acc8296 RB |
2551 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2552 | * when we have no data to transfer. Otherwise we get being flooded by | |
2553 | * interrupts. | |
308d734e LM |
2554 | */ |
2555 | ||
95c8bc36 | 2556 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2557 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f DN |
2558 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2559 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2560 | DIEPMSK_INTKNEPMISMSK, | |
2561 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2562 | |
2563 | /* | |
2564 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2565 | * DMA mode we may need this. | |
2566 | */ | |
95c8bc36 | 2567 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
47a1685f DN |
2568 | DIEPMSK_TIMEOUTMSK) : 0) | |
2569 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2570 | DOEPMSK_SETUPMSK, | |
2571 | hsotg->regs + DOEPMSK); | |
308d734e | 2572 | |
95c8bc36 | 2573 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2574 | |
2575 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2576 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2577 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2578 | |
2579 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2580 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2581 | |
2582 | /* | |
2583 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2584 | * the data. In DMA mode, we get events from the FIFO but also | |
2585 | * things we cannot process, so do not use it. | |
2586 | */ | |
2587 | if (!using_dma(hsotg)) | |
1f91b4cc | 2588 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2589 | |
2590 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2591 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2592 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2593 | |
643cc4de GH |
2594 | if (!is_usb_reset) { |
2595 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2596 | udelay(10); /* see openiboot */ | |
2597 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2598 | } | |
308d734e | 2599 | |
95c8bc36 | 2600 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2601 | |
2602 | /* | |
94cb8fd6 | 2603 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2604 | * writing to the EPCTL register.. |
2605 | */ | |
2606 | ||
2607 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2608 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2609 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2610 | |
95c8bc36 | 2611 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2612 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2613 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2614 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2615 | |
2616 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2617 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2618 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2619 | |
1f91b4cc | 2620 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2621 | |
2622 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2623 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2624 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2625 | |
2626 | /* clear global NAKs */ | |
643cc4de GH |
2627 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2628 | if (!is_usb_reset) | |
2629 | val |= DCTL_SFTDISCON; | |
2630 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2631 | |
2632 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2633 | mdelay(3); | |
2634 | ||
065d3931 | 2635 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2636 | } |
2637 | ||
1f91b4cc | 2638 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2639 | { |
2640 | /* set the soft-disconnect bit */ | |
2641 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2642 | } | |
ac3c81f3 | 2643 | |
1f91b4cc | 2644 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2645 | { |
308d734e | 2646 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2647 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2648 | } |
2649 | ||
381fc8f8 VM |
2650 | /** |
2651 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
2652 | * @hsotg: The device state: | |
2653 | * | |
2654 | * This interrupt indicates one of the following conditions occurred while | |
2655 | * transmitting an ISOC transaction. | |
2656 | * - Corrupted IN Token for ISOC EP. | |
2657 | * - Packet not complete in FIFO. | |
2658 | * | |
2659 | * The following actions will be taken: | |
2660 | * - Determine the EP | |
2661 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
2662 | */ | |
2663 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
2664 | { | |
2665 | struct dwc2_hsotg_ep *hs_ep; | |
2666 | u32 epctrl; | |
2667 | u32 idx; | |
2668 | ||
2669 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
2670 | ||
2671 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2672 | hs_ep = hsotg->eps_in[idx]; | |
2673 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); | |
2674 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2675 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2676 | epctrl |= DXEPCTL_SNAK; | |
2677 | epctrl |= DXEPCTL_EPDIS; | |
2678 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
2679 | } | |
2680 | } | |
2681 | ||
2682 | /* Clear interrupt */ | |
2683 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
2684 | } | |
2685 | ||
2686 | /** | |
2687 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
2688 | * @hsotg: The device state: | |
2689 | * | |
2690 | * This interrupt indicates one of the following conditions occurred while | |
2691 | * transmitting an ISOC transaction. | |
2692 | * - Corrupted OUT Token for ISOC EP. | |
2693 | * - Packet not complete in FIFO. | |
2694 | * | |
2695 | * The following actions will be taken: | |
2696 | * - Determine the EP | |
2697 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
2698 | */ | |
2699 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
2700 | { | |
2701 | u32 gintsts; | |
2702 | u32 gintmsk; | |
2703 | u32 epctrl; | |
2704 | struct dwc2_hsotg_ep *hs_ep; | |
2705 | int idx; | |
2706 | ||
2707 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
2708 | ||
2709 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2710 | hs_ep = hsotg->eps_out[idx]; | |
2711 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
2712 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2713 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2714 | /* Unmask GOUTNAKEFF interrupt */ | |
2715 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
2716 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
2717 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
2718 | ||
2719 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
2720 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) | |
2721 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
2722 | } | |
2723 | } | |
2724 | ||
2725 | /* Clear interrupt */ | |
2726 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
2727 | } | |
2728 | ||
5b7d70c6 | 2729 | /** |
1f91b4cc | 2730 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2731 | * @irq: The IRQ number triggered |
2732 | * @pw: The pw value when registered the handler. | |
2733 | */ | |
1f91b4cc | 2734 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2735 | { |
941fcce4 | 2736 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2737 | int retry_count = 8; |
2738 | u32 gintsts; | |
2739 | u32 gintmsk; | |
2740 | ||
ee3de8d7 VM |
2741 | if (!dwc2_is_device_mode(hsotg)) |
2742 | return IRQ_NONE; | |
2743 | ||
5ad1d316 | 2744 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2745 | irq_retry: |
95c8bc36 AS |
2746 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2747 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2748 | |
2749 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2750 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2751 | ||
2752 | gintsts &= gintmsk; | |
2753 | ||
8fc37b82 MYK |
2754 | if (gintsts & GINTSTS_RESETDET) { |
2755 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2756 | ||
2757 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
2758 | ||
2759 | /* This event must be used only if controller is suspended */ | |
2760 | if (hsotg->lx_state == DWC2_L2) { | |
2761 | dwc2_exit_hibernation(hsotg, true); | |
2762 | hsotg->lx_state = DWC2_L0; | |
2763 | } | |
2764 | } | |
2765 | ||
2766 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
2767 | ||
2768 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); | |
2769 | u32 connected = hsotg->connected; | |
2770 | ||
2771 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
2772 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2773 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
2774 | ||
2775 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
2776 | ||
2777 | /* Report disconnection if it is not already done. */ | |
2778 | dwc2_hsotg_disconnect(hsotg); | |
2779 | ||
2780 | if (usb_status & GOTGCTL_BSESVLD && connected) | |
2781 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
2782 | } | |
2783 | ||
47a1685f | 2784 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2785 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2786 | |
1f91b4cc | 2787 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2788 | } |
2789 | ||
47a1685f | 2790 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2791 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2792 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2793 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2794 | int ep; |
2795 | ||
7e804650 | 2796 | daint &= daintmsk; |
47a1685f DN |
2797 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2798 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2799 | |
5b7d70c6 BD |
2800 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2801 | ||
cec87f1d MYK |
2802 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2803 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2804 | if (daint_out & 1) |
1f91b4cc | 2805 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2806 | } |
2807 | ||
cec87f1d MYK |
2808 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2809 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2810 | if (daint_in & 1) |
1f91b4cc | 2811 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2812 | } |
5b7d70c6 BD |
2813 | } |
2814 | ||
5b7d70c6 BD |
2815 | /* check both FIFOs */ |
2816 | ||
47a1685f | 2817 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2818 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2819 | ||
8b9bc460 LM |
2820 | /* |
2821 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2822 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2823 | * it needs re-enabling |
2824 | */ | |
5b7d70c6 | 2825 | |
1f91b4cc FB |
2826 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2827 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2828 | } |
2829 | ||
47a1685f | 2830 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2831 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2832 | ||
94cb8fd6 | 2833 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2834 | |
1f91b4cc FB |
2835 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2836 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2837 | } |
2838 | ||
47a1685f | 2839 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2840 | /* |
2841 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2842 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2843 | * set. |
2844 | */ | |
5b7d70c6 | 2845 | |
1f91b4cc | 2846 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2847 | } |
2848 | ||
47a1685f | 2849 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2850 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2851 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2852 | } |
2853 | ||
8b9bc460 LM |
2854 | /* |
2855 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2856 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2857 | * the occurrence. |
2858 | */ | |
5b7d70c6 | 2859 | |
47a1685f | 2860 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2861 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2862 | ||
3be99cd0 | 2863 | __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK); |
a3395f0d | 2864 | |
1f91b4cc | 2865 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2866 | } |
2867 | ||
47a1685f | 2868 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2869 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2870 | ||
3be99cd0 | 2871 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 2872 | |
1f91b4cc | 2873 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2874 | } |
2875 | ||
381fc8f8 VM |
2876 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
2877 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 2878 | |
381fc8f8 VM |
2879 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
2880 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 2881 | |
8b9bc460 LM |
2882 | /* |
2883 | * if we've had fifo events, we should try and go around the | |
2884 | * loop again to see if there's any point in returning yet. | |
2885 | */ | |
5b7d70c6 BD |
2886 | |
2887 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2888 | goto irq_retry; | |
2889 | ||
5ad1d316 LM |
2890 | spin_unlock(&hsotg->lock); |
2891 | ||
5b7d70c6 BD |
2892 | return IRQ_HANDLED; |
2893 | } | |
2894 | ||
2895 | /** | |
1f91b4cc | 2896 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2897 | * @ep: The USB endpint to configure |
2898 | * @desc: The USB endpoint descriptor to configure with. | |
2899 | * | |
2900 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2901 | */ |
1f91b4cc | 2902 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2903 | const struct usb_endpoint_descriptor *desc) |
2904 | { | |
1f91b4cc | 2905 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2906 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2907 | unsigned long flags; |
ca4c55ad | 2908 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2909 | u32 epctrl_reg; |
2910 | u32 epctrl; | |
2911 | u32 mps; | |
ca4c55ad MYK |
2912 | unsigned int dir_in; |
2913 | unsigned int i, val, size; | |
19c190f9 | 2914 | int ret = 0; |
5b7d70c6 BD |
2915 | |
2916 | dev_dbg(hsotg->dev, | |
2917 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2918 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2919 | desc->wMaxPacketSize, desc->bInterval); | |
2920 | ||
2921 | /* not to be called for EP0 */ | |
8c3d6092 VA |
2922 | if (index == 0) { |
2923 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
2924 | return -EINVAL; | |
2925 | } | |
5b7d70c6 BD |
2926 | |
2927 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2928 | if (dir_in != hs_ep->dir_in) { | |
2929 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2930 | return -EINVAL; | |
2931 | } | |
2932 | ||
29cc8897 | 2933 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 | 2934 | |
1f91b4cc | 2935 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2936 | |
94cb8fd6 | 2937 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2938 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2939 | |
2940 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2941 | __func__, epctrl, epctrl_reg); | |
2942 | ||
22258f49 | 2943 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2944 | |
47a1685f DN |
2945 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2946 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2947 | |
8b9bc460 LM |
2948 | /* |
2949 | * mark the endpoint as active, otherwise the core may ignore | |
2950 | * transactions entirely for this endpoint | |
2951 | */ | |
47a1685f | 2952 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2953 | |
8b9bc460 LM |
2954 | /* |
2955 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2956 | * do something with data that we've yet got a request to process |
2957 | * since the RXFIFO will take data for an endpoint even if the | |
2958 | * size register hasn't been set. | |
2959 | */ | |
2960 | ||
47a1685f | 2961 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2962 | |
2963 | /* update the endpoint state */ | |
1f91b4cc | 2964 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2965 | |
2966 | /* default, set to non-periodic */ | |
1479e841 | 2967 | hs_ep->isochronous = 0; |
5b7d70c6 | 2968 | hs_ep->periodic = 0; |
a18ed7b0 | 2969 | hs_ep->halted = 0; |
1479e841 | 2970 | hs_ep->interval = desc->bInterval; |
4fca54aa | 2971 | |
5b7d70c6 BD |
2972 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2973 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2974 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2975 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 2976 | hs_ep->isochronous = 1; |
142bd33f | 2977 | hs_ep->interval = 1 << (desc->bInterval - 1); |
1479e841 RB |
2978 | if (dir_in) |
2979 | hs_ep->periodic = 1; | |
2980 | break; | |
5b7d70c6 BD |
2981 | |
2982 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2983 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2984 | break; |
2985 | ||
2986 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2987 | if (dir_in) |
5b7d70c6 | 2988 | hs_ep->periodic = 1; |
5b7d70c6 | 2989 | |
142bd33f VM |
2990 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
2991 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
2992 | ||
47a1685f | 2993 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2994 | break; |
2995 | ||
2996 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2997 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2998 | break; |
2999 | } | |
3000 | ||
4556e12c MYK |
3001 | /* If fifo is already allocated for this ep */ |
3002 | if (hs_ep->fifo_index) { | |
3003 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
3004 | /* If bigger fifo is required deallocate current one */ | |
3005 | if (size > hs_ep->fifo_size) { | |
3006 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
3007 | hs_ep->fifo_index = 0; | |
3008 | hs_ep->fifo_size = 0; | |
3009 | } | |
3010 | } | |
3011 | ||
8b9bc460 LM |
3012 | /* |
3013 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3014 | * a unique tx-fifo even if it is non-periodic. |
3015 | */ | |
4556e12c | 3016 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
3017 | u32 fifo_index = 0; |
3018 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 3019 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 3020 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
3021 | if (hsotg->fifo_map & (1<<i)) |
3022 | continue; | |
95c8bc36 | 3023 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
3024 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
3025 | if (val < size) | |
3026 | continue; | |
ca4c55ad MYK |
3027 | /* Search for smallest acceptable fifo */ |
3028 | if (val < fifo_size) { | |
3029 | fifo_size = val; | |
3030 | fifo_index = i; | |
3031 | } | |
b203d0a2 | 3032 | } |
ca4c55ad | 3033 | if (!fifo_index) { |
5f2196bd MYK |
3034 | dev_err(hsotg->dev, |
3035 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
3036 | ret = -ENOMEM; |
3037 | goto error; | |
3038 | } | |
ca4c55ad MYK |
3039 | hsotg->fifo_map |= 1 << fifo_index; |
3040 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3041 | hs_ep->fifo_index = fifo_index; | |
3042 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3043 | } |
10aebc77 | 3044 | |
5b7d70c6 BD |
3045 | /* for non control endpoints, set PID to D0 */ |
3046 | if (index) | |
47a1685f | 3047 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3048 | |
3049 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3050 | __func__, epctrl); | |
3051 | ||
95c8bc36 | 3052 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3053 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3054 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3055 | |
3056 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3057 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3058 | |
b585a48b | 3059 | error: |
22258f49 | 3060 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 3061 | return ret; |
5b7d70c6 BD |
3062 | } |
3063 | ||
8b9bc460 | 3064 | /** |
1f91b4cc | 3065 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3066 | * @ep: The endpoint to disable. |
3067 | */ | |
1f91b4cc | 3068 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3069 | { |
1f91b4cc | 3070 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3071 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3072 | int dir_in = hs_ep->dir_in; |
3073 | int index = hs_ep->index; | |
3074 | unsigned long flags; | |
3075 | u32 epctrl_reg; | |
3076 | u32 ctrl; | |
3077 | ||
1e011293 | 3078 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 3079 | |
c6f5c050 | 3080 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
3081 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
3082 | return -EINVAL; | |
3083 | } | |
3084 | ||
94cb8fd6 | 3085 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 3086 | |
5ad1d316 | 3087 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3088 | |
b203d0a2 RB |
3089 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
3090 | hs_ep->fifo_index = 0; | |
3091 | hs_ep->fifo_size = 0; | |
5b7d70c6 | 3092 | |
95c8bc36 | 3093 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
3094 | ctrl &= ~DXEPCTL_EPENA; |
3095 | ctrl &= ~DXEPCTL_USBACTEP; | |
3096 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
3097 | |
3098 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 3099 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3100 | |
3101 | /* disable endpoint interrupts */ | |
1f91b4cc | 3102 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 3103 | |
1141ea01 MYK |
3104 | /* terminate all requests with shutdown */ |
3105 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
3106 | ||
22258f49 | 3107 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3108 | return 0; |
3109 | } | |
3110 | ||
3111 | /** | |
3112 | * on_list - check request is on the given endpoint | |
3113 | * @ep: The endpoint to check. | |
3114 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 3115 | */ |
1f91b4cc | 3116 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 3117 | { |
1f91b4cc | 3118 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
3119 | |
3120 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
3121 | if (req == test) | |
3122 | return true; | |
3123 | } | |
3124 | ||
3125 | return false; | |
3126 | } | |
3127 | ||
c524dd5f MYK |
3128 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3129 | u32 bit, u32 timeout) | |
3130 | { | |
3131 | u32 i; | |
3132 | ||
3133 | for (i = 0; i < timeout; i++) { | |
3134 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3135 | return 0; | |
3136 | udelay(1); | |
3137 | } | |
3138 | ||
3139 | return -ETIMEDOUT; | |
3140 | } | |
3141 | ||
3142 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3143 | struct dwc2_hsotg_ep *hs_ep) | |
3144 | { | |
3145 | u32 epctrl_reg; | |
3146 | u32 epint_reg; | |
3147 | ||
3148 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3149 | DOEPCTL(hs_ep->index); | |
3150 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3151 | DOEPINT(hs_ep->index); | |
3152 | ||
3153 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3154 | hs_ep->name); | |
3155 | if (hs_ep->dir_in) { | |
3156 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3157 | /* Wait for Nak effect */ | |
3158 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3159 | DXEPINT_INEPNAKEFF, 100)) | |
3160 | dev_warn(hsotg->dev, | |
3161 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
3162 | } else { | |
6b58cb07 VM |
3163 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3164 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
c524dd5f MYK |
3165 | |
3166 | /* Wait for global nak to take effect */ | |
3167 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
0676c7e7 | 3168 | GINTSTS_GOUTNAKEFF, 100)) |
c524dd5f | 3169 | dev_warn(hsotg->dev, |
0676c7e7 | 3170 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
c524dd5f MYK |
3171 | } |
3172 | ||
3173 | /* Disable ep */ | |
3174 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3175 | ||
3176 | /* Wait for ep to be disabled */ | |
3177 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3178 | dev_warn(hsotg->dev, | |
3179 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3180 | ||
3181 | if (hs_ep->dir_in) { | |
3182 | if (hsotg->dedicated_fifos) { | |
3183 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
3184 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
3185 | /* Wait for fifo flush */ | |
3186 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
3187 | GRSTCTL_TXFFLSH, 100)) | |
3188 | dev_warn(hsotg->dev, | |
3189 | "%s: timeout flushing fifos\n", | |
3190 | __func__); | |
3191 | } | |
3192 | /* TODO: Flush shared tx fifo */ | |
3193 | } else { | |
3194 | /* Remove global NAKs */ | |
0676c7e7 | 3195 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
3196 | } |
3197 | } | |
3198 | ||
8b9bc460 | 3199 | /** |
1f91b4cc | 3200 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
3201 | * @ep: The endpoint to dequeue. |
3202 | * @req: The request to be removed from a queue. | |
3203 | */ | |
1f91b4cc | 3204 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 3205 | { |
1f91b4cc FB |
3206 | struct dwc2_hsotg_req *hs_req = our_req(req); |
3207 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 3208 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
3209 | unsigned long flags; |
3210 | ||
1e011293 | 3211 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 3212 | |
22258f49 | 3213 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
3214 | |
3215 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 3216 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3217 | return -EINVAL; |
3218 | } | |
3219 | ||
c524dd5f MYK |
3220 | /* Dequeue already started request */ |
3221 | if (req == &hs_ep->req->req) | |
3222 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
3223 | ||
1f91b4cc | 3224 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 3225 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3226 | |
3227 | return 0; | |
3228 | } | |
3229 | ||
8b9bc460 | 3230 | /** |
1f91b4cc | 3231 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
3232 | * @ep: The endpoint to set halt. |
3233 | * @value: Set or unset the halt. | |
51da43b5 VA |
3234 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
3235 | * the endpoint is busy processing requests. | |
3236 | * | |
3237 | * We need to stall the endpoint immediately if request comes from set_feature | |
3238 | * protocol command handler. | |
8b9bc460 | 3239 | */ |
51da43b5 | 3240 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 3241 | { |
1f91b4cc | 3242 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3243 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 3244 | int index = hs_ep->index; |
5b7d70c6 BD |
3245 | u32 epreg; |
3246 | u32 epctl; | |
9c39ddc6 | 3247 | u32 xfertype; |
5b7d70c6 BD |
3248 | |
3249 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
3250 | ||
c9f721b2 RB |
3251 | if (index == 0) { |
3252 | if (value) | |
1f91b4cc | 3253 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
3254 | else |
3255 | dev_warn(hs->dev, | |
3256 | "%s: can't clear halt on ep0\n", __func__); | |
3257 | return 0; | |
3258 | } | |
3259 | ||
15186f10 VA |
3260 | if (hs_ep->isochronous) { |
3261 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
3262 | return -EINVAL; | |
3263 | } | |
3264 | ||
51da43b5 VA |
3265 | if (!now && value && !list_empty(&hs_ep->queue)) { |
3266 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
3267 | ep->name); | |
3268 | return -EAGAIN; | |
3269 | } | |
3270 | ||
c6f5c050 MYK |
3271 | if (hs_ep->dir_in) { |
3272 | epreg = DIEPCTL(index); | |
95c8bc36 | 3273 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
3274 | |
3275 | if (value) { | |
5a350d53 | 3276 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
3277 | if (epctl & DXEPCTL_EPENA) |
3278 | epctl |= DXEPCTL_EPDIS; | |
3279 | } else { | |
3280 | epctl &= ~DXEPCTL_STALL; | |
3281 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3282 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3283 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3284 | epctl |= DXEPCTL_SETD0PID; | |
3285 | } | |
95c8bc36 | 3286 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3287 | } else { |
5b7d70c6 | 3288 | |
c6f5c050 | 3289 | epreg = DOEPCTL(index); |
95c8bc36 | 3290 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 3291 | |
c6f5c050 MYK |
3292 | if (value) |
3293 | epctl |= DXEPCTL_STALL; | |
3294 | else { | |
3295 | epctl &= ~DXEPCTL_STALL; | |
3296 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3297 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3298 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3299 | epctl |= DXEPCTL_SETD0PID; | |
3300 | } | |
95c8bc36 | 3301 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3302 | } |
5b7d70c6 | 3303 | |
a18ed7b0 RB |
3304 | hs_ep->halted = value; |
3305 | ||
5b7d70c6 BD |
3306 | return 0; |
3307 | } | |
3308 | ||
5ad1d316 | 3309 | /** |
1f91b4cc | 3310 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
3311 | * @ep: The endpoint to set halt. |
3312 | * @value: Set or unset the halt. | |
3313 | */ | |
1f91b4cc | 3314 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3315 | { |
1f91b4cc | 3316 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3317 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3318 | unsigned long flags = 0; |
3319 | int ret = 0; | |
3320 | ||
3321 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 3322 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
3323 | spin_unlock_irqrestore(&hs->lock, flags); |
3324 | ||
3325 | return ret; | |
3326 | } | |
3327 | ||
1f91b4cc FB |
3328 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3329 | .enable = dwc2_hsotg_ep_enable, | |
3330 | .disable = dwc2_hsotg_ep_disable, | |
3331 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3332 | .free_request = dwc2_hsotg_ep_free_request, | |
3333 | .queue = dwc2_hsotg_ep_queue_lock, | |
3334 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3335 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3336 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3337 | }; |
3338 | ||
8b9bc460 | 3339 | /** |
1f91b4cc | 3340 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3341 | * @hsotg: The driver state |
3342 | */ | |
1f91b4cc | 3343 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3344 | { |
fa4a8d72 | 3345 | u32 trdtim; |
ecd9a7ad | 3346 | u32 usbcfg; |
b3f489b2 LM |
3347 | /* unmask subset of endpoint interrupts */ |
3348 | ||
95c8bc36 AS |
3349 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3350 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3351 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3352 | |
95c8bc36 AS |
3353 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3354 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3355 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3356 | |
95c8bc36 | 3357 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3358 | |
3359 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3360 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3361 | |
b3f489b2 LM |
3362 | /* setup fifos */ |
3363 | ||
3364 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3365 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3366 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3367 | |
1f91b4cc | 3368 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 3369 | |
ecd9a7ad PR |
3370 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3371 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3372 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
3373 | GUSBCFG_HNPCAP); | |
3374 | ||
b3f489b2 | 3375 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 3376 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
3377 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
3378 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
3379 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 3380 | |
f5090044 GH |
3381 | if (using_dma(hsotg)) |
3382 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3383 | } |
3384 | ||
8b9bc460 | 3385 | /** |
1f91b4cc | 3386 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3387 | * @gadget: The usb gadget state |
3388 | * @driver: The usb gadget driver | |
3389 | * | |
3390 | * Perform initialization to prepare udc device and driver | |
3391 | * to work. | |
3392 | */ | |
1f91b4cc | 3393 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3394 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3395 | { |
941fcce4 | 3396 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3397 | unsigned long flags; |
5b7d70c6 BD |
3398 | int ret; |
3399 | ||
3400 | if (!hsotg) { | |
a023da33 | 3401 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3402 | return -ENODEV; |
3403 | } | |
3404 | ||
3405 | if (!driver) { | |
3406 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3407 | return -EINVAL; | |
3408 | } | |
3409 | ||
7177aed4 | 3410 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3411 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3412 | |
f65f0f10 | 3413 | if (!driver->setup) { |
5b7d70c6 BD |
3414 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3415 | return -EINVAL; | |
3416 | } | |
3417 | ||
3418 | WARN_ON(hsotg->driver); | |
3419 | ||
3420 | driver->driver.bus = NULL; | |
3421 | hsotg->driver = driver; | |
7d7b2292 | 3422 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3423 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3424 | ||
09a75e85 MS |
3425 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
3426 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
3427 | if (ret) | |
3428 | goto err; | |
5b7d70c6 BD |
3429 | } |
3430 | ||
f6c01592 GH |
3431 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3432 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3433 | |
5b9451f8 | 3434 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc FB |
3435 | dwc2_hsotg_init(hsotg); |
3436 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
dc6e69e6 | 3437 | hsotg->enabled = 0; |
5b9451f8 MS |
3438 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3439 | ||
5b7d70c6 | 3440 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3441 | |
5b7d70c6 BD |
3442 | return 0; |
3443 | ||
3444 | err: | |
3445 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3446 | return ret; |
3447 | } | |
3448 | ||
8b9bc460 | 3449 | /** |
1f91b4cc | 3450 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3451 | * @gadget: The usb gadget state |
3452 | * @driver: The usb gadget driver | |
3453 | * | |
3454 | * Stop udc hw block and stay tunned for future transmissions | |
3455 | */ | |
1f91b4cc | 3456 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3457 | { |
941fcce4 | 3458 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3459 | unsigned long flags = 0; |
5b7d70c6 BD |
3460 | int ep; |
3461 | ||
3462 | if (!hsotg) | |
3463 | return -ENODEV; | |
3464 | ||
5b7d70c6 | 3465 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3466 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3467 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3468 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3469 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3470 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3471 | } |
5b7d70c6 | 3472 | |
2b19a52c LM |
3473 | spin_lock_irqsave(&hsotg->lock, flags); |
3474 | ||
32805c35 | 3475 | hsotg->driver = NULL; |
5b7d70c6 | 3476 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3477 | hsotg->enabled = 0; |
5b7d70c6 | 3478 | |
2b19a52c LM |
3479 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3480 | ||
f6c01592 GH |
3481 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3482 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 3483 | |
09a75e85 MS |
3484 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3485 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
3486 | |
3487 | return 0; | |
3488 | } | |
5b7d70c6 | 3489 | |
8b9bc460 | 3490 | /** |
1f91b4cc | 3491 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3492 | * @gadget: The usb gadget state |
3493 | * | |
3494 | * Read the {micro} frame number | |
3495 | */ | |
1f91b4cc | 3496 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3497 | { |
1f91b4cc | 3498 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3499 | } |
3500 | ||
a188b689 | 3501 | /** |
1f91b4cc | 3502 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3503 | * @gadget: The usb gadget state |
3504 | * @is_on: Current state of the USB PHY | |
3505 | * | |
3506 | * Connect/Disconnect the USB PHY pullup | |
3507 | */ | |
1f91b4cc | 3508 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3509 | { |
941fcce4 | 3510 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3511 | unsigned long flags = 0; |
3512 | ||
77ba9119 GH |
3513 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3514 | hsotg->op_state); | |
3515 | ||
3516 | /* Don't modify pullup state while in host mode */ | |
3517 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3518 | hsotg->enabled = is_on; | |
3519 | return 0; | |
3520 | } | |
a188b689 LM |
3521 | |
3522 | spin_lock_irqsave(&hsotg->lock, flags); | |
3523 | if (is_on) { | |
dc6e69e6 | 3524 | hsotg->enabled = 1; |
1f91b4cc FB |
3525 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3526 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3527 | } else { |
1f91b4cc FB |
3528 | dwc2_hsotg_core_disconnect(hsotg); |
3529 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3530 | hsotg->enabled = 0; |
a188b689 LM |
3531 | } |
3532 | ||
3533 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3534 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3535 | ||
3536 | return 0; | |
3537 | } | |
3538 | ||
1f91b4cc | 3539 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3540 | { |
3541 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3542 | unsigned long flags; | |
3543 | ||
3544 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3545 | spin_lock_irqsave(&hsotg->lock, flags); | |
3546 | ||
61f7223b GH |
3547 | /* |
3548 | * If controller is hibernated, it must exit from hibernation | |
3549 | * before being initialized / de-initialized | |
3550 | */ | |
3551 | if (hsotg->lx_state == DWC2_L2) | |
3552 | dwc2_exit_hibernation(hsotg, false); | |
3553 | ||
83d98223 | 3554 | if (is_active) { |
cd0e641c | 3555 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3556 | |
1f91b4cc | 3557 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3558 | if (hsotg->enabled) |
1f91b4cc | 3559 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3560 | } else { |
1f91b4cc FB |
3561 | dwc2_hsotg_core_disconnect(hsotg); |
3562 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3563 | } |
3564 | ||
3565 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3566 | return 0; | |
3567 | } | |
3568 | ||
596d696a | 3569 | /** |
1f91b4cc | 3570 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3571 | * @gadget: The usb gadget state |
3572 | * @mA: Amount of current | |
3573 | * | |
3574 | * Report how much power the device may consume to the phy. | |
3575 | */ | |
1f91b4cc | 3576 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3577 | { |
3578 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3579 | ||
3580 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3581 | return -ENOTSUPP; | |
3582 | return usb_phy_set_power(hsotg->uphy, mA); | |
3583 | } | |
3584 | ||
1f91b4cc FB |
3585 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3586 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3587 | .udc_start = dwc2_hsotg_udc_start, | |
3588 | .udc_stop = dwc2_hsotg_udc_stop, | |
3589 | .pullup = dwc2_hsotg_pullup, | |
3590 | .vbus_session = dwc2_hsotg_vbus_session, | |
3591 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3592 | }; |
3593 | ||
3594 | /** | |
1f91b4cc | 3595 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3596 | * @hsotg: The device state. |
3597 | * @hs_ep: The endpoint to be initialised. | |
3598 | * @epnum: The endpoint number | |
3599 | * | |
3600 | * Initialise the given endpoint (as part of the probe and device state | |
3601 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3602 | * direction information and other state that may be required. | |
3603 | */ | |
1f91b4cc FB |
3604 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3605 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3606 | int epnum, |
3607 | bool dir_in) | |
5b7d70c6 | 3608 | { |
5b7d70c6 BD |
3609 | char *dir; |
3610 | ||
3611 | if (epnum == 0) | |
3612 | dir = ""; | |
c6f5c050 | 3613 | else if (dir_in) |
5b7d70c6 | 3614 | dir = "in"; |
c6f5c050 MYK |
3615 | else |
3616 | dir = "out"; | |
5b7d70c6 | 3617 | |
c6f5c050 | 3618 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3619 | hs_ep->index = epnum; |
3620 | ||
3621 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3622 | ||
3623 | INIT_LIST_HEAD(&hs_ep->queue); | |
3624 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3625 | ||
5b7d70c6 BD |
3626 | /* add to the list of endpoints known by the gadget driver */ |
3627 | if (epnum) | |
3628 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3629 | ||
3630 | hs_ep->parent = hsotg; | |
3631 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3632 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3633 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3634 | |
2954522f RB |
3635 | if (epnum == 0) { |
3636 | hs_ep->ep.caps.type_control = true; | |
3637 | } else { | |
3638 | hs_ep->ep.caps.type_iso = true; | |
3639 | hs_ep->ep.caps.type_bulk = true; | |
3640 | hs_ep->ep.caps.type_int = true; | |
3641 | } | |
3642 | ||
3643 | if (dir_in) | |
3644 | hs_ep->ep.caps.dir_in = true; | |
3645 | else | |
3646 | hs_ep->ep.caps.dir_out = true; | |
3647 | ||
8b9bc460 LM |
3648 | /* |
3649 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3650 | * to be something valid. |
3651 | */ | |
3652 | ||
3653 | if (using_dma(hsotg)) { | |
47a1685f | 3654 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3655 | if (dir_in) |
95c8bc36 | 3656 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3657 | else |
95c8bc36 | 3658 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3659 | } |
3660 | } | |
3661 | ||
b3f489b2 | 3662 | /** |
1f91b4cc | 3663 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3664 | * @param: The device state |
3665 | * | |
3666 | * Read the USB core HW configuration registers | |
3667 | */ | |
1f91b4cc | 3668 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3669 | { |
c6f5c050 MYK |
3670 | u32 cfg; |
3671 | u32 ep_type; | |
3672 | u32 i; | |
3673 | ||
b3f489b2 | 3674 | /* check hardware configuration */ |
5b7d70c6 | 3675 | |
43e90349 JY |
3676 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
3677 | ||
c6f5c050 MYK |
3678 | /* Add ep0 */ |
3679 | hsotg->num_of_eps++; | |
10aebc77 | 3680 | |
1f91b4cc | 3681 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3682 | GFP_KERNEL); |
3683 | if (!hsotg->eps_in[0]) | |
3684 | return -ENOMEM; | |
1f91b4cc | 3685 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3686 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3687 | ||
43e90349 | 3688 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 3689 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3690 | ep_type = cfg & 3; |
3691 | /* Direction in or both */ | |
3692 | if (!(ep_type & 2)) { | |
3693 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3694 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3695 | if (!hsotg->eps_in[i]) |
3696 | return -ENOMEM; | |
3697 | } | |
3698 | /* Direction out or both */ | |
3699 | if (!(ep_type & 1)) { | |
3700 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3701 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3702 | if (!hsotg->eps_out[i]) |
3703 | return -ENOMEM; | |
3704 | } | |
3705 | } | |
3706 | ||
43e90349 JY |
3707 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
3708 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 3709 | |
cff9eb75 MS |
3710 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3711 | hsotg->num_of_eps, | |
3712 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3713 | hsotg->fifo_mem); | |
c6f5c050 | 3714 | return 0; |
5b7d70c6 BD |
3715 | } |
3716 | ||
8b9bc460 | 3717 | /** |
1f91b4cc | 3718 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3719 | * @param: The device state |
3720 | */ | |
1f91b4cc | 3721 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3722 | { |
83a01804 | 3723 | #ifdef DEBUG |
5b7d70c6 BD |
3724 | struct device *dev = hsotg->dev; |
3725 | void __iomem *regs = hsotg->regs; | |
3726 | u32 val; | |
3727 | int idx; | |
3728 | ||
3729 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3730 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3731 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3732 | |
f889f23d | 3733 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3734 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3735 | |
3736 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3737 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3738 | |
3739 | /* show periodic fifo settings */ | |
3740 | ||
364f8e93 | 3741 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3742 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3743 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3744 | val >> FIFOSIZE_DEPTH_SHIFT, |
3745 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3746 | } |
3747 | ||
364f8e93 | 3748 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3749 | dev_info(dev, |
3750 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3751 | dwc2_readl(regs + DIEPCTL(idx)), |
3752 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3753 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3754 | |
95c8bc36 | 3755 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3756 | dev_info(dev, |
3757 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3758 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3759 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3760 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3761 | |
3762 | } | |
3763 | ||
3764 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3765 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3766 | #endif |
5b7d70c6 BD |
3767 | } |
3768 | ||
edd74be8 | 3769 | #ifdef CONFIG_OF |
1f91b4cc | 3770 | static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) |
edd74be8 GH |
3771 | { |
3772 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3773 | u32 len = 0; |
3774 | u32 i = 0; | |
edd74be8 GH |
3775 | |
3776 | /* Enable dma if requested in device tree */ | |
3777 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3778 | |
3779 | /* | |
3780 | * Register TX periodic fifo size per endpoint. | |
3781 | * EP0 is excluded since it has no fifo configuration. | |
3782 | */ | |
3783 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3784 | goto rx_fifo; | |
3785 | ||
3786 | len /= sizeof(u32); | |
3787 | ||
3788 | /* Read tx fifo sizes other than ep0 */ | |
3789 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3790 | &hsotg->g_tx_fifo_sz[1], len)) | |
3791 | goto rx_fifo; | |
3792 | ||
3793 | /* Add ep0 */ | |
3794 | len++; | |
3795 | ||
3796 | /* Make remaining TX fifos unavailable */ | |
3797 | if (len < MAX_EPS_CHANNELS) { | |
3798 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3799 | hsotg->g_tx_fifo_sz[i] = 0; | |
3800 | } | |
3801 | ||
3802 | rx_fifo: | |
3803 | /* Register RX fifo size */ | |
3804 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3805 | ||
3806 | /* Register NPTX fifo size */ | |
3807 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3808 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3809 | } |
3810 | #else | |
1f91b4cc | 3811 | static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } |
edd74be8 GH |
3812 | #endif |
3813 | ||
8b9bc460 | 3814 | /** |
117777b2 DN |
3815 | * dwc2_gadget_init - init function for gadget |
3816 | * @dwc2: The data structure for the DWC2 driver. | |
3817 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3818 | */ |
117777b2 | 3819 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3820 | { |
117777b2 | 3821 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
3822 | int epnum; |
3823 | int ret; | |
fc9a731e | 3824 | int i; |
0a176279 | 3825 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3826 | |
0a176279 GH |
3827 | /* Initialize to legacy fifo configuration values */ |
3828 | hsotg->g_rx_fifo_sz = 2048; | |
3829 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3830 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3831 | /* Device tree specific probe */ | |
1f91b4cc | 3832 | dwc2_hsotg_of_probe(hsotg); |
43e90349 JY |
3833 | |
3834 | /* Check against largest possible value. */ | |
3835 | if (hsotg->g_np_g_tx_fifo_sz > | |
3836 | hsotg->hw_params.dev_nperio_tx_fifo_size) { | |
3837 | dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n", | |
3838 | hsotg->g_np_g_tx_fifo_sz, | |
3839 | hsotg->hw_params.dev_nperio_tx_fifo_size); | |
3840 | hsotg->g_np_g_tx_fifo_sz = | |
3841 | hsotg->hw_params.dev_nperio_tx_fifo_size; | |
3842 | } | |
3843 | ||
0a176279 GH |
3844 | /* Dump fifo information */ |
3845 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3846 | hsotg->g_np_g_tx_fifo_sz); | |
3847 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3848 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3849 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3850 | hsotg->g_tx_fifo_sz[i]); | |
5b7d70c6 | 3851 | |
d327ab5b | 3852 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3853 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3854 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3855 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3856 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3857 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3858 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3859 | |
1f91b4cc | 3860 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
3861 | if (ret) { |
3862 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 3863 | return ret; |
c6f5c050 MYK |
3864 | } |
3865 | ||
3f95001d MYK |
3866 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3867 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3868 | if (!hsotg->ctrl_buff) { | |
3869 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
09a75e85 | 3870 | return -ENOMEM; |
3f95001d MYK |
3871 | } |
3872 | ||
3873 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3874 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3875 | if (!hsotg->ep0_buff) { | |
3876 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
09a75e85 | 3877 | return -ENOMEM; |
3f95001d MYK |
3878 | } |
3879 | ||
1f91b4cc | 3880 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3881 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3882 | if (ret < 0) { |
db8178c3 | 3883 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 3884 | return ret; |
eb3c56c5 MS |
3885 | } |
3886 | ||
b3f489b2 LM |
3887 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3888 | ||
3889 | if (hsotg->num_of_eps == 0) { | |
3890 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 3891 | return -EINVAL; |
b3f489b2 LM |
3892 | } |
3893 | ||
b3f489b2 LM |
3894 | /* setup endpoint information */ |
3895 | ||
3896 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3897 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3898 | |
3899 | /* allocate EP0 request */ | |
3900 | ||
1f91b4cc | 3901 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3902 | GFP_KERNEL); |
3903 | if (!hsotg->ctrl_req) { | |
3904 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 3905 | return -ENOMEM; |
b3f489b2 | 3906 | } |
5b7d70c6 BD |
3907 | |
3908 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3909 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3910 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3911 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3912 | epnum, 1); |
3913 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3914 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3915 | epnum, 0); |
3916 | } | |
5b7d70c6 | 3917 | |
117777b2 | 3918 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3919 | if (ret) |
09a75e85 | 3920 | return ret; |
0f91349b | 3921 | |
1f91b4cc | 3922 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3923 | |
5b7d70c6 | 3924 | return 0; |
5b7d70c6 BD |
3925 | } |
3926 | ||
8b9bc460 | 3927 | /** |
1f91b4cc | 3928 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3929 | * @pdev: The platform information for the driver |
3930 | */ | |
1f91b4cc | 3931 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3932 | { |
0f91349b | 3933 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 3934 | |
5b7d70c6 BD |
3935 | return 0; |
3936 | } | |
3937 | ||
1f91b4cc | 3938 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3939 | { |
b83e333a | 3940 | unsigned long flags; |
b83e333a | 3941 | |
9e779778 | 3942 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 3943 | return 0; |
9e779778 | 3944 | |
dc6e69e6 MS |
3945 | if (hsotg->driver) { |
3946 | int ep; | |
3947 | ||
b83e333a MS |
3948 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3949 | hsotg->driver->driver.name); | |
3950 | ||
dc6e69e6 MS |
3951 | spin_lock_irqsave(&hsotg->lock, flags); |
3952 | if (hsotg->enabled) | |
1f91b4cc FB |
3953 | dwc2_hsotg_core_disconnect(hsotg); |
3954 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3955 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3956 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3957 | |
c6f5c050 MYK |
3958 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3959 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3960 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3961 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3962 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3963 | } |
b83e333a MS |
3964 | } |
3965 | ||
09a75e85 | 3966 | return 0; |
b83e333a MS |
3967 | } |
3968 | ||
1f91b4cc | 3969 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3970 | { |
b83e333a | 3971 | unsigned long flags; |
b83e333a | 3972 | |
9e779778 | 3973 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 3974 | return 0; |
9e779778 | 3975 | |
b83e333a MS |
3976 | if (hsotg->driver) { |
3977 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3978 | hsotg->driver->driver.name); | |
d00b4142 | 3979 | |
dc6e69e6 | 3980 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3981 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3982 | if (hsotg->enabled) |
1f91b4cc | 3983 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3984 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3985 | } | |
b83e333a | 3986 | |
09a75e85 | 3987 | return 0; |
b83e333a | 3988 | } |
58e52ff6 JY |
3989 | |
3990 | /** | |
3991 | * dwc2_backup_device_registers() - Backup controller device registers. | |
3992 | * When suspending usb bus, registers needs to be backuped | |
3993 | * if controller power is disabled once suspended. | |
3994 | * | |
3995 | * @hsotg: Programming view of the DWC_otg controller | |
3996 | */ | |
3997 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
3998 | { | |
3999 | struct dwc2_dregs_backup *dr; | |
4000 | int i; | |
4001 | ||
4002 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4003 | ||
4004 | /* Backup dev regs */ | |
4005 | dr = &hsotg->dr_backup; | |
4006 | ||
4007 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4008 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4009 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4010 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4011 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4012 | ||
4013 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4014 | /* Backup IN EPs */ | |
4015 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4016 | ||
4017 | /* Ensure DATA PID is correctly configured */ | |
4018 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4019 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4020 | else | |
4021 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4022 | ||
4023 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4024 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4025 | ||
4026 | /* Backup OUT EPs */ | |
4027 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4028 | ||
4029 | /* Ensure DATA PID is correctly configured */ | |
4030 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4031 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4032 | else | |
4033 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4034 | ||
4035 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4036 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
4037 | } | |
4038 | dr->valid = true; | |
4039 | return 0; | |
4040 | } | |
4041 | ||
4042 | /** | |
4043 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4044 | * When resuming usb bus, device registers needs to be restored | |
4045 | * if controller power were disabled. | |
4046 | * | |
4047 | * @hsotg: Programming view of the DWC_otg controller | |
4048 | */ | |
4049 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
4050 | { | |
4051 | struct dwc2_dregs_backup *dr; | |
4052 | u32 dctl; | |
4053 | int i; | |
4054 | ||
4055 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4056 | ||
4057 | /* Restore dev regs */ | |
4058 | dr = &hsotg->dr_backup; | |
4059 | if (!dr->valid) { | |
4060 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4061 | __func__); | |
4062 | return -EINVAL; | |
4063 | } | |
4064 | dr->valid = false; | |
4065 | ||
4066 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
4067 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4068 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
4069 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4070 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4071 | ||
4072 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4073 | /* Restore IN EPs */ | |
4074 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
4075 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
4076 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
4077 | ||
4078 | /* Restore OUT EPs */ | |
4079 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
4080 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
4081 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
4082 | } | |
4083 | ||
4084 | /* Set the Power-On Programming done bit */ | |
4085 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
4086 | dctl |= DCTL_PWRONPRGDONE; | |
4087 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
4088 | ||
4089 | return 0; | |
4090 | } |