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Commit | Line | Data |
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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/debugfs.h> | |
24 | #include <linux/seq_file.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
e50bf385 | 28 | #include <linux/clk.h> |
fc9a731e | 29 | #include <linux/regulator/consumer.h> |
c50f056c | 30 | #include <linux/of_platform.h> |
74084844 | 31 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
32 | |
33 | #include <linux/usb/ch9.h> | |
34 | #include <linux/usb/gadget.h> | |
b2e587db | 35 | #include <linux/usb/phy.h> |
126625e1 | 36 | #include <linux/platform_data/s3c-hsotg.h> |
5b7d70c6 | 37 | |
f7c0b143 | 38 | #include "core.h" |
5b7d70c6 BD |
39 | |
40 | /* conversion functions */ | |
41 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
42 | { | |
43 | return container_of(req, struct s3c_hsotg_req, req); | |
44 | } | |
45 | ||
46 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
47 | { | |
48 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
49 | } | |
50 | ||
51 | static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget) | |
52 | { | |
53 | return container_of(gadget, struct s3c_hsotg, gadget); | |
54 | } | |
55 | ||
56 | static inline void __orr32(void __iomem *ptr, u32 val) | |
57 | { | |
58 | writel(readl(ptr) | val, ptr); | |
59 | } | |
60 | ||
61 | static inline void __bic32(void __iomem *ptr, u32 val) | |
62 | { | |
63 | writel(readl(ptr) & ~val, ptr); | |
64 | } | |
65 | ||
66 | /* forward decleration of functions */ | |
67 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg); | |
68 | ||
69 | /** | |
70 | * using_dma - return the DMA status of the driver. | |
71 | * @hsotg: The driver state. | |
72 | * | |
73 | * Return true if we're using DMA. | |
74 | * | |
75 | * Currently, we have the DMA support code worked into everywhere | |
76 | * that needs it, but the AMBA DMA implementation in the hardware can | |
77 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
78 | * as the CDC Ethernet cannot work as they often pass packets which are | |
79 | * not 32bit aligned. | |
80 | * | |
81 | * Unfortunately the choice to use DMA or not is global to the controller | |
82 | * and seems to be only settable when the controller is being put through | |
83 | * a core reset. This means we either need to fix the gadgets to take | |
84 | * account of DMA alignment, or add bounce buffers (yuerk). | |
85 | * | |
86 | * Until this issue is sorted out, we always return 'false'. | |
87 | */ | |
88 | static inline bool using_dma(struct s3c_hsotg *hsotg) | |
89 | { | |
90 | return false; /* support is not complete */ | |
91 | } | |
92 | ||
93 | /** | |
94 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
95 | * @hsotg: The device state | |
96 | * @ints: A bitmask of the interrupts to enable | |
97 | */ | |
98 | static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
99 | { | |
94cb8fd6 | 100 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
101 | u32 new_gsintmsk; |
102 | ||
103 | new_gsintmsk = gsintmsk | ints; | |
104 | ||
105 | if (new_gsintmsk != gsintmsk) { | |
106 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 107 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
108 | } |
109 | } | |
110 | ||
111 | /** | |
112 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
113 | * @hsotg: The device state | |
114 | * @ints: A bitmask of the interrupts to enable | |
115 | */ | |
116 | static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
117 | { | |
94cb8fd6 | 118 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
119 | u32 new_gsintmsk; |
120 | ||
121 | new_gsintmsk = gsintmsk & ~ints; | |
122 | ||
123 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 124 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
125 | } |
126 | ||
127 | /** | |
128 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
129 | * @hsotg: The device state | |
130 | * @ep: The endpoint index | |
131 | * @dir_in: True if direction is in. | |
132 | * @en: The enable value, true to enable | |
133 | * | |
134 | * Set or clear the mask for an individual endpoint's interrupt | |
135 | * request. | |
136 | */ | |
137 | static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg, | |
138 | unsigned int ep, unsigned int dir_in, | |
139 | unsigned int en) | |
140 | { | |
141 | unsigned long flags; | |
142 | u32 bit = 1 << ep; | |
143 | u32 daint; | |
144 | ||
145 | if (!dir_in) | |
146 | bit <<= 16; | |
147 | ||
148 | local_irq_save(flags); | |
94cb8fd6 | 149 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
150 | if (en) |
151 | daint |= bit; | |
152 | else | |
153 | daint &= ~bit; | |
94cb8fd6 | 154 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
155 | local_irq_restore(flags); |
156 | } | |
157 | ||
158 | /** | |
159 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
160 | * @hsotg: The device instance. | |
161 | */ | |
162 | static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) | |
163 | { | |
0f002d20 BD |
164 | unsigned int ep; |
165 | unsigned int addr; | |
166 | unsigned int size; | |
1703a6d3 | 167 | int timeout; |
0f002d20 BD |
168 | u32 val; |
169 | ||
6d091ee7 | 170 | /* set FIFO sizes to 2048/1024 */ |
5b7d70c6 | 171 | |
94cb8fd6 | 172 | writel(2048, hsotg->regs + GRXFSIZ); |
47a1685f DN |
173 | writel((2048 << FIFOSIZE_STARTADDR_SHIFT) | |
174 | (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 175 | |
8b9bc460 LM |
176 | /* |
177 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
178 | * block have overlapping default addresses. This also ensures |
179 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
180 | * known values. |
181 | */ | |
0f002d20 BD |
182 | |
183 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
184 | addr = 2048 + 1024; | |
185 | size = 768; | |
186 | ||
8b9bc460 LM |
187 | /* |
188 | * currently we allocate TX FIFOs for all possible endpoints, | |
189 | * and assume that they are all the same size. | |
190 | */ | |
0f002d20 | 191 | |
f7a83fe1 | 192 | for (ep = 1; ep <= 15; ep++) { |
0f002d20 | 193 | val = addr; |
47a1685f | 194 | val |= size << FIFOSIZE_DEPTH_SHIFT; |
0f002d20 BD |
195 | addr += size; |
196 | ||
47a1685f | 197 | writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 198 | } |
1703a6d3 | 199 | |
8b9bc460 LM |
200 | /* |
201 | * according to p428 of the design guide, we need to ensure that | |
202 | * all fifos are flushed before continuing | |
203 | */ | |
1703a6d3 | 204 | |
47a1685f DN |
205 | writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
206 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
207 | |
208 | /* wait until the fifos are both flushed */ | |
209 | timeout = 100; | |
210 | while (1) { | |
94cb8fd6 | 211 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 212 | |
47a1685f | 213 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
214 | break; |
215 | ||
216 | if (--timeout == 0) { | |
217 | dev_err(hsotg->dev, | |
218 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
219 | __func__, val); | |
220 | } | |
221 | ||
222 | udelay(1); | |
223 | } | |
224 | ||
225 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
226 | } |
227 | ||
228 | /** | |
229 | * @ep: USB endpoint to allocate request for. | |
230 | * @flags: Allocation flags | |
231 | * | |
232 | * Allocate a new USB request structure appropriate for the specified endpoint | |
233 | */ | |
0978f8c5 MB |
234 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
235 | gfp_t flags) | |
5b7d70c6 BD |
236 | { |
237 | struct s3c_hsotg_req *req; | |
238 | ||
239 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
240 | if (!req) | |
241 | return NULL; | |
242 | ||
243 | INIT_LIST_HEAD(&req->queue); | |
244 | ||
5b7d70c6 BD |
245 | return &req->req; |
246 | } | |
247 | ||
248 | /** | |
249 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
250 | * @hs_ep: The endpoint to query. | |
251 | * | |
252 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
253 | * used for an Interrupt or ISO transfer. | |
254 | */ | |
255 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
256 | { | |
257 | return hs_ep->periodic; | |
258 | } | |
259 | ||
260 | /** | |
261 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
262 | * @hsotg: The device state. | |
263 | * @hs_ep: The endpoint for the request | |
264 | * @hs_req: The request being processed. | |
265 | * | |
266 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
267 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 268 | */ |
5b7d70c6 BD |
269 | static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg, |
270 | struct s3c_hsotg_ep *hs_ep, | |
271 | struct s3c_hsotg_req *hs_req) | |
272 | { | |
273 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
274 | |
275 | /* ignore this if we're not moving any data */ | |
276 | if (hs_req->req.length == 0) | |
277 | return; | |
278 | ||
17d966a3 | 279 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
280 | } |
281 | ||
282 | /** | |
283 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
284 | * @hsotg: The controller state. | |
285 | * @hs_ep: The endpoint we're going to write for. | |
286 | * @hs_req: The request to write data for. | |
287 | * | |
288 | * This is called when the TxFIFO has some space in it to hold a new | |
289 | * transmission and we have something to give it. The actual setup of | |
290 | * the data size is done elsewhere, so all we have to do is to actually | |
291 | * write the data. | |
292 | * | |
293 | * The return value is zero if there is more space (or nothing was done) | |
294 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
295 | * | |
296 | * This routine is only needed for PIO | |
8b9bc460 | 297 | */ |
5b7d70c6 BD |
298 | static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg, |
299 | struct s3c_hsotg_ep *hs_ep, | |
300 | struct s3c_hsotg_req *hs_req) | |
301 | { | |
302 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 303 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
304 | int buf_pos = hs_req->req.actual; |
305 | int to_write = hs_ep->size_loaded; | |
306 | void *data; | |
307 | int can_write; | |
308 | int pkt_round; | |
4fca54aa | 309 | int max_transfer; |
5b7d70c6 BD |
310 | |
311 | to_write -= (buf_pos - hs_ep->last_load); | |
312 | ||
313 | /* if there's nothing to write, get out early */ | |
314 | if (to_write == 0) | |
315 | return 0; | |
316 | ||
10aebc77 | 317 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 318 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
319 | int size_left; |
320 | int size_done; | |
321 | ||
8b9bc460 LM |
322 | /* |
323 | * work out how much data was loaded so we can calculate | |
324 | * how much data is left in the fifo. | |
325 | */ | |
5b7d70c6 | 326 | |
47a1685f | 327 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 328 | |
8b9bc460 LM |
329 | /* |
330 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
331 | * previous data has been completely sent. |
332 | */ | |
333 | if (hs_ep->fifo_load != 0) { | |
47a1685f | 334 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
335 | return -ENOSPC; |
336 | } | |
337 | ||
5b7d70c6 BD |
338 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
339 | __func__, size_left, | |
340 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
341 | ||
342 | /* how much of the data has moved */ | |
343 | size_done = hs_ep->size_loaded - size_left; | |
344 | ||
345 | /* how much data is left in the fifo */ | |
346 | can_write = hs_ep->fifo_load - size_done; | |
347 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
348 | __func__, can_write); | |
349 | ||
350 | can_write = hs_ep->fifo_size - can_write; | |
351 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
352 | __func__, can_write); | |
353 | ||
354 | if (can_write <= 0) { | |
47a1685f | 355 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
356 | return -ENOSPC; |
357 | } | |
10aebc77 | 358 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 359 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
360 | |
361 | can_write &= 0xffff; | |
362 | can_write *= 4; | |
5b7d70c6 | 363 | } else { |
47a1685f | 364 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
365 | dev_dbg(hsotg->dev, |
366 | "%s: no queue slots available (0x%08x)\n", | |
367 | __func__, gnptxsts); | |
368 | ||
47a1685f | 369 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
370 | return -ENOSPC; |
371 | } | |
372 | ||
47a1685f | 373 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 374 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
375 | } |
376 | ||
4fca54aa RB |
377 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
378 | ||
379 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
380 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 381 | |
8b9bc460 LM |
382 | /* |
383 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
384 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
385 | * fragment of the end of the transfer in it. | |
386 | */ | |
811f3303 | 387 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
388 | can_write = 512; |
389 | ||
8b9bc460 LM |
390 | /* |
391 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 392 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
393 | * doing it. |
394 | */ | |
4fca54aa RB |
395 | if (to_write > max_transfer) { |
396 | to_write = max_transfer; | |
03e10e5a | 397 | |
5cb2ff0c RB |
398 | /* it's needed only when we do not use dedicated fifos */ |
399 | if (!hsotg->dedicated_fifos) | |
400 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
401 | periodic ? GINTSTS_PTXFEMP : |
402 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
403 | } |
404 | ||
5b7d70c6 BD |
405 | /* see if we can write data */ |
406 | ||
407 | if (to_write > can_write) { | |
408 | to_write = can_write; | |
4fca54aa | 409 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 410 | |
8b9bc460 LM |
411 | /* |
412 | * Round the write down to an | |
5b7d70c6 BD |
413 | * exact number of packets. |
414 | * | |
415 | * Note, we do not currently check to see if we can ever | |
416 | * write a full packet or not to the FIFO. | |
417 | */ | |
418 | ||
419 | if (pkt_round) | |
420 | to_write -= pkt_round; | |
421 | ||
8b9bc460 LM |
422 | /* |
423 | * enable correct FIFO interrupt to alert us when there | |
424 | * is more room left. | |
425 | */ | |
5b7d70c6 | 426 | |
5cb2ff0c RB |
427 | /* it's needed only when we do not use dedicated fifos */ |
428 | if (!hsotg->dedicated_fifos) | |
429 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
430 | periodic ? GINTSTS_PTXFEMP : |
431 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
432 | } |
433 | ||
434 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
435 | to_write, hs_req->req.length, can_write, buf_pos); | |
436 | ||
437 | if (to_write <= 0) | |
438 | return -ENOSPC; | |
439 | ||
440 | hs_req->req.actual = buf_pos + to_write; | |
441 | hs_ep->total_data += to_write; | |
442 | ||
443 | if (periodic) | |
444 | hs_ep->fifo_load += to_write; | |
445 | ||
446 | to_write = DIV_ROUND_UP(to_write, 4); | |
447 | data = hs_req->req.buf + buf_pos; | |
448 | ||
1a7ed5be | 449 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
450 | |
451 | return (to_write >= can_write) ? -ENOSPC : 0; | |
452 | } | |
453 | ||
454 | /** | |
455 | * get_ep_limit - get the maximum data legnth for this endpoint | |
456 | * @hs_ep: The endpoint | |
457 | * | |
458 | * Return the maximum data that can be queued in one go on a given endpoint | |
459 | * so that transfers that are too long can be split. | |
460 | */ | |
461 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
462 | { | |
463 | int index = hs_ep->index; | |
464 | unsigned maxsize; | |
465 | unsigned maxpkt; | |
466 | ||
467 | if (index != 0) { | |
47a1685f DN |
468 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
469 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 470 | } else { |
b05ca580 | 471 | maxsize = 64+64; |
66e5c643 | 472 | if (hs_ep->dir_in) |
47a1685f | 473 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 474 | else |
5b7d70c6 | 475 | maxpkt = 2; |
5b7d70c6 BD |
476 | } |
477 | ||
478 | /* we made the constant loading easier above by using +1 */ | |
479 | maxpkt--; | |
480 | maxsize--; | |
481 | ||
8b9bc460 LM |
482 | /* |
483 | * constrain by packet count if maxpkts*pktsize is greater | |
484 | * than the length register size. | |
485 | */ | |
5b7d70c6 BD |
486 | |
487 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
488 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
489 | ||
490 | return maxsize; | |
491 | } | |
492 | ||
493 | /** | |
494 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
495 | * @hsotg: The controller state. | |
496 | * @hs_ep: The endpoint to process a request for | |
497 | * @hs_req: The request to start. | |
498 | * @continuing: True if we are doing more for the current request. | |
499 | * | |
500 | * Start the given request running by setting the endpoint registers | |
501 | * appropriately, and writing any data to the FIFOs. | |
502 | */ | |
503 | static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg, | |
504 | struct s3c_hsotg_ep *hs_ep, | |
505 | struct s3c_hsotg_req *hs_req, | |
506 | bool continuing) | |
507 | { | |
508 | struct usb_request *ureq = &hs_req->req; | |
509 | int index = hs_ep->index; | |
510 | int dir_in = hs_ep->dir_in; | |
511 | u32 epctrl_reg; | |
512 | u32 epsize_reg; | |
513 | u32 epsize; | |
514 | u32 ctrl; | |
515 | unsigned length; | |
516 | unsigned packets; | |
517 | unsigned maxreq; | |
518 | ||
519 | if (index != 0) { | |
520 | if (hs_ep->req && !continuing) { | |
521 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
522 | WARN_ON(1); | |
523 | return; | |
524 | } else if (hs_ep->req != hs_req && continuing) { | |
525 | dev_err(hsotg->dev, | |
526 | "%s: continue different req\n", __func__); | |
527 | WARN_ON(1); | |
528 | return; | |
529 | } | |
530 | } | |
531 | ||
94cb8fd6 LM |
532 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
533 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
534 | |
535 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
536 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
537 | hs_ep->dir_in ? "in" : "out"); | |
538 | ||
9c39ddc6 AT |
539 | /* If endpoint is stalled, we will restart request later */ |
540 | ctrl = readl(hsotg->regs + epctrl_reg); | |
541 | ||
47a1685f | 542 | if (ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
543 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
544 | return; | |
545 | } | |
546 | ||
5b7d70c6 | 547 | length = ureq->length - ureq->actual; |
71225bee LM |
548 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
549 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
550 | if (0) |
551 | dev_dbg(hsotg->dev, | |
0cc4cf6f | 552 | "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n", |
8b3bc14f | 553 | ureq->buf, length, &ureq->dma, |
5b7d70c6 BD |
554 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); |
555 | ||
556 | maxreq = get_ep_limit(hs_ep); | |
557 | if (length > maxreq) { | |
558 | int round = maxreq % hs_ep->ep.maxpacket; | |
559 | ||
560 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
561 | __func__, length, maxreq, round); | |
562 | ||
563 | /* round down to multiple of packets */ | |
564 | if (round) | |
565 | maxreq -= round; | |
566 | ||
567 | length = maxreq; | |
568 | } | |
569 | ||
570 | if (length) | |
571 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
572 | else | |
573 | packets = 1; /* send one packet if length is zero. */ | |
574 | ||
4fca54aa RB |
575 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
576 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
577 | return; | |
578 | } | |
579 | ||
5b7d70c6 | 580 | if (dir_in && index != 0) |
4fca54aa | 581 | if (hs_ep->isochronous) |
47a1685f | 582 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 583 | else |
47a1685f | 584 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
585 | else |
586 | epsize = 0; | |
587 | ||
588 | if (index != 0 && ureq->zero) { | |
8b9bc460 LM |
589 | /* |
590 | * test for the packets being exactly right for the | |
591 | * transfer | |
592 | */ | |
5b7d70c6 BD |
593 | |
594 | if (length == (packets * hs_ep->ep.maxpacket)) | |
595 | packets++; | |
596 | } | |
597 | ||
47a1685f DN |
598 | epsize |= DXEPTSIZ_PKTCNT(packets); |
599 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
600 | |
601 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
602 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
603 | ||
604 | /* store the request as the current one we're doing */ | |
605 | hs_ep->req = hs_req; | |
606 | ||
607 | /* write size / packets */ | |
608 | writel(epsize, hsotg->regs + epsize_reg); | |
609 | ||
db1d8ba3 | 610 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
611 | unsigned int dma_reg; |
612 | ||
8b9bc460 LM |
613 | /* |
614 | * write DMA address to control register, buffer already | |
615 | * synced by s3c_hsotg_ep_queue(). | |
616 | */ | |
5b7d70c6 | 617 | |
94cb8fd6 | 618 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
619 | writel(ureq->dma, hsotg->regs + dma_reg); |
620 | ||
0cc4cf6f | 621 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 622 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
623 | } |
624 | ||
47a1685f DN |
625 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
626 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee LM |
627 | |
628 | dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup); | |
629 | ||
630 | /* For Setup request do not clear NAK */ | |
631 | if (hsotg->setup && index == 0) | |
632 | hsotg->setup = 0; | |
633 | else | |
47a1685f | 634 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 635 | |
5b7d70c6 BD |
636 | |
637 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
638 | writel(ctrl, hsotg->regs + epctrl_reg); | |
639 | ||
8b9bc460 LM |
640 | /* |
641 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 642 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
643 | * this information. |
644 | */ | |
5b7d70c6 BD |
645 | hs_ep->size_loaded = length; |
646 | hs_ep->last_load = ureq->actual; | |
647 | ||
648 | if (dir_in && !using_dma(hsotg)) { | |
649 | /* set these anyway, we may need them for non-periodic in */ | |
650 | hs_ep->fifo_load = 0; | |
651 | ||
652 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
653 | } | |
654 | ||
8b9bc460 LM |
655 | /* |
656 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
657 | * to debugging to see what is going on. | |
658 | */ | |
5b7d70c6 | 659 | if (dir_in) |
47a1685f | 660 | writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 661 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 662 | |
8b9bc460 LM |
663 | /* |
664 | * Note, trying to clear the NAK here causes problems with transmit | |
665 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
666 | */ | |
5b7d70c6 BD |
667 | |
668 | /* check ep is enabled */ | |
47a1685f | 669 | if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
5b7d70c6 | 670 | dev_warn(hsotg->dev, |
47a1685f | 671 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
5b7d70c6 BD |
672 | index, readl(hsotg->regs + epctrl_reg)); |
673 | ||
47a1685f | 674 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
5b7d70c6 | 675 | __func__, readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
676 | |
677 | /* enable ep interrupts */ | |
678 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
679 | } |
680 | ||
681 | /** | |
682 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
683 | * @hsotg: The device state. | |
684 | * @hs_ep: The endpoint the request is on. | |
685 | * @req: The request being processed. | |
686 | * | |
687 | * We've been asked to queue a request, so ensure that the memory buffer | |
688 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
689 | * then ensure the buffer has been synced to memory. If our buffer has no | |
690 | * DMA memory, then we map the memory and mark our request to allow us to | |
691 | * cleanup on completion. | |
8b9bc460 | 692 | */ |
5b7d70c6 BD |
693 | static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg, |
694 | struct s3c_hsotg_ep *hs_ep, | |
695 | struct usb_request *req) | |
696 | { | |
5b7d70c6 | 697 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 698 | int ret; |
5b7d70c6 BD |
699 | |
700 | /* if the length is zero, ignore the DMA data */ | |
701 | if (hs_req->req.length == 0) | |
702 | return 0; | |
703 | ||
e58ebcd1 FB |
704 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
705 | if (ret) | |
706 | goto dma_error; | |
5b7d70c6 BD |
707 | |
708 | return 0; | |
709 | ||
710 | dma_error: | |
711 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
712 | __func__, req->buf, req->length); | |
713 | ||
714 | return -EIO; | |
715 | } | |
716 | ||
717 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
718 | gfp_t gfp_flags) | |
719 | { | |
720 | struct s3c_hsotg_req *hs_req = our_req(req); | |
721 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
722 | struct s3c_hsotg *hs = hs_ep->parent; | |
5b7d70c6 BD |
723 | bool first; |
724 | ||
725 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
726 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
727 | req->zero, req->short_not_ok); | |
728 | ||
729 | /* initialise status of the request */ | |
730 | INIT_LIST_HEAD(&hs_req->queue); | |
731 | req->actual = 0; | |
732 | req->status = -EINPROGRESS; | |
733 | ||
734 | /* if we're using DMA, sync the buffers as necessary */ | |
735 | if (using_dma(hs)) { | |
736 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
737 | if (ret) | |
738 | return ret; | |
739 | } | |
740 | ||
5b7d70c6 BD |
741 | first = list_empty(&hs_ep->queue); |
742 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
743 | ||
744 | if (first) | |
745 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
746 | ||
5b7d70c6 BD |
747 | return 0; |
748 | } | |
749 | ||
5ad1d316 LM |
750 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
751 | gfp_t gfp_flags) | |
752 | { | |
753 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
754 | struct s3c_hsotg *hs = hs_ep->parent; | |
755 | unsigned long flags = 0; | |
756 | int ret = 0; | |
757 | ||
758 | spin_lock_irqsave(&hs->lock, flags); | |
759 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
760 | spin_unlock_irqrestore(&hs->lock, flags); | |
761 | ||
762 | return ret; | |
763 | } | |
764 | ||
5b7d70c6 BD |
765 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
766 | struct usb_request *req) | |
767 | { | |
768 | struct s3c_hsotg_req *hs_req = our_req(req); | |
769 | ||
770 | kfree(hs_req); | |
771 | } | |
772 | ||
773 | /** | |
774 | * s3c_hsotg_complete_oursetup - setup completion callback | |
775 | * @ep: The endpoint the request was on. | |
776 | * @req: The request completed. | |
777 | * | |
778 | * Called on completion of any requests the driver itself | |
779 | * submitted that need cleaning up. | |
780 | */ | |
781 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
782 | struct usb_request *req) | |
783 | { | |
784 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
785 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
786 | ||
787 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
788 | ||
789 | s3c_hsotg_ep_free_request(ep, req); | |
790 | } | |
791 | ||
792 | /** | |
793 | * ep_from_windex - convert control wIndex value to endpoint | |
794 | * @hsotg: The driver state. | |
795 | * @windex: The control request wIndex field (in host order). | |
796 | * | |
797 | * Convert the given wIndex into a pointer to an driver endpoint | |
798 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 799 | */ |
5b7d70c6 BD |
800 | static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg, |
801 | u32 windex) | |
802 | { | |
803 | struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F]; | |
804 | int dir = (windex & USB_DIR_IN) ? 1 : 0; | |
805 | int idx = windex & 0x7F; | |
806 | ||
807 | if (windex >= 0x100) | |
808 | return NULL; | |
809 | ||
b3f489b2 | 810 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
811 | return NULL; |
812 | ||
813 | if (idx && ep->dir_in != dir) | |
814 | return NULL; | |
815 | ||
816 | return ep; | |
817 | } | |
818 | ||
819 | /** | |
820 | * s3c_hsotg_send_reply - send reply to control request | |
821 | * @hsotg: The device state | |
822 | * @ep: Endpoint 0 | |
823 | * @buff: Buffer for request | |
824 | * @length: Length of reply. | |
825 | * | |
826 | * Create a request and queue it on the given endpoint. This is useful as | |
827 | * an internal method of sending replies to certain control requests, etc. | |
828 | */ | |
829 | static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg, | |
830 | struct s3c_hsotg_ep *ep, | |
831 | void *buff, | |
832 | int length) | |
833 | { | |
834 | struct usb_request *req; | |
835 | int ret; | |
836 | ||
837 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
838 | ||
839 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
840 | hsotg->ep0_reply = req; | |
841 | if (!req) { | |
842 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
843 | return -ENOMEM; | |
844 | } | |
845 | ||
846 | req->buf = hsotg->ep0_buff; | |
847 | req->length = length; | |
848 | req->zero = 1; /* always do zero-length final transfer */ | |
849 | req->complete = s3c_hsotg_complete_oursetup; | |
850 | ||
851 | if (length) | |
852 | memcpy(req->buf, buff, length); | |
853 | else | |
854 | ep->sent_zlp = 1; | |
855 | ||
856 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
857 | if (ret) { | |
858 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
859 | return ret; | |
860 | } | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
865 | /** | |
866 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
867 | * @hsotg: The device state | |
868 | * @ctrl: USB control request | |
869 | */ | |
870 | static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg, | |
871 | struct usb_ctrlrequest *ctrl) | |
872 | { | |
873 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
874 | struct s3c_hsotg_ep *ep; | |
875 | __le16 reply; | |
876 | int ret; | |
877 | ||
878 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
879 | ||
880 | if (!ep0->dir_in) { | |
881 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
885 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
886 | case USB_RECIP_DEVICE: | |
887 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
888 | * bit 1 => remote wakeup */ | |
889 | break; | |
890 | ||
891 | case USB_RECIP_INTERFACE: | |
892 | /* currently, the data result should be zero */ | |
893 | reply = cpu_to_le16(0); | |
894 | break; | |
895 | ||
896 | case USB_RECIP_ENDPOINT: | |
897 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
898 | if (!ep) | |
899 | return -ENOENT; | |
900 | ||
901 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
902 | break; | |
903 | ||
904 | default: | |
905 | return 0; | |
906 | } | |
907 | ||
908 | if (le16_to_cpu(ctrl->wLength) != 2) | |
909 | return -EINVAL; | |
910 | ||
911 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
912 | if (ret) { | |
913 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
914 | return ret; | |
915 | } | |
916 | ||
917 | return 1; | |
918 | } | |
919 | ||
920 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
921 | ||
9c39ddc6 AT |
922 | /** |
923 | * get_ep_head - return the first request on the endpoint | |
924 | * @hs_ep: The controller endpoint to get | |
925 | * | |
926 | * Get the first request on the endpoint. | |
927 | */ | |
928 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
929 | { | |
930 | if (list_empty(&hs_ep->queue)) | |
931 | return NULL; | |
932 | ||
933 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
934 | } | |
935 | ||
5b7d70c6 BD |
936 | /** |
937 | * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE | |
938 | * @hsotg: The device state | |
939 | * @ctrl: USB control request | |
940 | */ | |
941 | static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg, | |
942 | struct usb_ctrlrequest *ctrl) | |
943 | { | |
26ab3d0c | 944 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; |
9c39ddc6 AT |
945 | struct s3c_hsotg_req *hs_req; |
946 | bool restart; | |
5b7d70c6 BD |
947 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
948 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 949 | int ret; |
bd9ef7bf | 950 | bool halted; |
5b7d70c6 BD |
951 | |
952 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
953 | __func__, set ? "SET" : "CLEAR"); | |
954 | ||
955 | if (ctrl->bRequestType == USB_RECIP_ENDPOINT) { | |
956 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
957 | if (!ep) { | |
958 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
959 | __func__, le16_to_cpu(ctrl->wIndex)); | |
960 | return -ENOENT; | |
961 | } | |
962 | ||
963 | switch (le16_to_cpu(ctrl->wValue)) { | |
964 | case USB_ENDPOINT_HALT: | |
bd9ef7bf RB |
965 | halted = ep->halted; |
966 | ||
5b7d70c6 | 967 | s3c_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c AT |
968 | |
969 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
970 | if (ret) { | |
971 | dev_err(hsotg->dev, | |
972 | "%s: failed to send reply\n", __func__); | |
973 | return ret; | |
974 | } | |
9c39ddc6 | 975 | |
bd9ef7bf RB |
976 | /* |
977 | * we have to complete all requests for ep if it was | |
978 | * halted, and the halt was cleared by CLEAR_FEATURE | |
979 | */ | |
980 | ||
981 | if (!set && halted) { | |
9c39ddc6 AT |
982 | /* |
983 | * If we have request in progress, | |
984 | * then complete it | |
985 | */ | |
986 | if (ep->req) { | |
987 | hs_req = ep->req; | |
988 | ep->req = NULL; | |
989 | list_del_init(&hs_req->queue); | |
990 | hs_req->req.complete(&ep->ep, | |
991 | &hs_req->req); | |
992 | } | |
993 | ||
994 | /* If we have pending request, then start it */ | |
995 | restart = !list_empty(&ep->queue); | |
996 | if (restart) { | |
997 | hs_req = get_ep_head(ep); | |
998 | s3c_hsotg_start_req(hsotg, ep, | |
999 | hs_req, false); | |
1000 | } | |
1001 | } | |
1002 | ||
5b7d70c6 BD |
1003 | break; |
1004 | ||
1005 | default: | |
1006 | return -ENOENT; | |
1007 | } | |
1008 | } else | |
1009 | return -ENOENT; /* currently only deal with endpoint */ | |
1010 | ||
1011 | return 1; | |
1012 | } | |
1013 | ||
ab93e014 | 1014 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg); |
d18f7116 | 1015 | static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg); |
ab93e014 | 1016 | |
c9f721b2 RB |
1017 | /** |
1018 | * s3c_hsotg_stall_ep0 - stall ep0 | |
1019 | * @hsotg: The device state | |
1020 | * | |
1021 | * Set stall for ep0 as response for setup request. | |
1022 | */ | |
e9ebe7c3 JH |
1023 | static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg) |
1024 | { | |
c9f721b2 RB |
1025 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; |
1026 | u32 reg; | |
1027 | u32 ctrl; | |
1028 | ||
1029 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1030 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1031 | ||
1032 | /* | |
1033 | * DxEPCTL_Stall will be cleared by EP once it has | |
1034 | * taken effect, so no need to clear later. | |
1035 | */ | |
1036 | ||
1037 | ctrl = readl(hsotg->regs + reg); | |
47a1685f DN |
1038 | ctrl |= DXEPCTL_STALL; |
1039 | ctrl |= DXEPCTL_CNAK; | |
c9f721b2 RB |
1040 | writel(ctrl, hsotg->regs + reg); |
1041 | ||
1042 | dev_dbg(hsotg->dev, | |
47a1685f | 1043 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
c9f721b2 RB |
1044 | ctrl, reg, readl(hsotg->regs + reg)); |
1045 | ||
1046 | /* | |
1047 | * complete won't be called, so we enqueue | |
1048 | * setup request here | |
1049 | */ | |
1050 | s3c_hsotg_enqueue_setup(hsotg); | |
1051 | } | |
1052 | ||
5b7d70c6 BD |
1053 | /** |
1054 | * s3c_hsotg_process_control - process a control request | |
1055 | * @hsotg: The device state | |
1056 | * @ctrl: The control request received | |
1057 | * | |
1058 | * The controller has received the SETUP phase of a control request, and | |
1059 | * needs to work out what to do next (and whether to pass it on to the | |
1060 | * gadget driver). | |
1061 | */ | |
1062 | static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg, | |
1063 | struct usb_ctrlrequest *ctrl) | |
1064 | { | |
1065 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
1066 | int ret = 0; | |
1067 | u32 dcfg; | |
1068 | ||
1069 | ep0->sent_zlp = 0; | |
1070 | ||
1071 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", | |
1072 | ctrl->bRequest, ctrl->bRequestType, | |
1073 | ctrl->wValue, ctrl->wLength); | |
1074 | ||
8b9bc460 LM |
1075 | /* |
1076 | * record the direction of the request, for later use when enquing | |
1077 | * packets onto EP0. | |
1078 | */ | |
5b7d70c6 BD |
1079 | |
1080 | ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0; | |
1081 | dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in); | |
1082 | ||
8b9bc460 LM |
1083 | /* |
1084 | * if we've no data with this request, then the last part of the | |
1085 | * transaction is going to implicitly be IN. | |
1086 | */ | |
5b7d70c6 BD |
1087 | if (ctrl->wLength == 0) |
1088 | ep0->dir_in = 1; | |
1089 | ||
1090 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1091 | switch (ctrl->bRequest) { | |
1092 | case USB_REQ_SET_ADDRESS: | |
d18f7116 | 1093 | s3c_hsotg_disconnect(hsotg); |
94cb8fd6 | 1094 | dcfg = readl(hsotg->regs + DCFG); |
47a1685f | 1095 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1096 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1097 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
94cb8fd6 | 1098 | writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1099 | |
1100 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1101 | ||
1102 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1103 | return; | |
1104 | ||
1105 | case USB_REQ_GET_STATUS: | |
1106 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1107 | break; | |
1108 | ||
1109 | case USB_REQ_CLEAR_FEATURE: | |
1110 | case USB_REQ_SET_FEATURE: | |
1111 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1112 | break; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | /* as a fallback, try delivering it to the driver to deal with */ | |
1117 | ||
1118 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1119 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1120 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1121 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1122 | if (ret < 0) |
1123 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1124 | } | |
1125 | ||
8b9bc460 LM |
1126 | /* |
1127 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1128 | * so respond with a STALL for the status stage to indicate failure. |
1129 | */ | |
1130 | ||
c9f721b2 RB |
1131 | if (ret < 0) |
1132 | s3c_hsotg_stall_ep0(hsotg); | |
5b7d70c6 BD |
1133 | } |
1134 | ||
5b7d70c6 BD |
1135 | /** |
1136 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1137 | * @ep: The endpoint the request was on. | |
1138 | * @req: The request completed. | |
1139 | * | |
1140 | * Called on completion of any requests the driver itself submitted for | |
1141 | * EP0 setup packets | |
1142 | */ | |
1143 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1144 | struct usb_request *req) | |
1145 | { | |
1146 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
1147 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
1148 | ||
1149 | if (req->status < 0) { | |
1150 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1151 | return; | |
1152 | } | |
1153 | ||
93f599f2 | 1154 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1155 | if (req->actual == 0) |
1156 | s3c_hsotg_enqueue_setup(hsotg); | |
1157 | else | |
1158 | s3c_hsotg_process_control(hsotg, req->buf); | |
93f599f2 | 1159 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1160 | } |
1161 | ||
1162 | /** | |
1163 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1164 | * @hsotg: The device state. | |
1165 | * | |
1166 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1167 | * received from the host. | |
1168 | */ | |
1169 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg) | |
1170 | { | |
1171 | struct usb_request *req = hsotg->ctrl_req; | |
1172 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1173 | int ret; | |
1174 | ||
1175 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1176 | ||
1177 | req->zero = 0; | |
1178 | req->length = 8; | |
1179 | req->buf = hsotg->ctrl_buff; | |
1180 | req->complete = s3c_hsotg_complete_setup; | |
1181 | ||
1182 | if (!list_empty(&hs_req->queue)) { | |
1183 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1184 | return; | |
1185 | } | |
1186 | ||
1187 | hsotg->eps[0].dir_in = 0; | |
1188 | ||
1189 | ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC); | |
1190 | if (ret < 0) { | |
1191 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1192 | /* |
1193 | * Don't think there's much we can do other than watch the | |
1194 | * driver fail. | |
1195 | */ | |
5b7d70c6 BD |
1196 | } |
1197 | } | |
1198 | ||
5b7d70c6 BD |
1199 | /** |
1200 | * s3c_hsotg_complete_request - complete a request given to us | |
1201 | * @hsotg: The device state. | |
1202 | * @hs_ep: The endpoint the request was on. | |
1203 | * @hs_req: The request to complete. | |
1204 | * @result: The result code (0 => Ok, otherwise errno) | |
1205 | * | |
1206 | * The given request has finished, so call the necessary completion | |
1207 | * if it has one and then look to see if we can start a new request | |
1208 | * on the endpoint. | |
1209 | * | |
1210 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1211 | */ |
5b7d70c6 BD |
1212 | static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg, |
1213 | struct s3c_hsotg_ep *hs_ep, | |
1214 | struct s3c_hsotg_req *hs_req, | |
1215 | int result) | |
1216 | { | |
1217 | bool restart; | |
1218 | ||
1219 | if (!hs_req) { | |
1220 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1221 | return; | |
1222 | } | |
1223 | ||
1224 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1225 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1226 | ||
8b9bc460 LM |
1227 | /* |
1228 | * only replace the status if we've not already set an error | |
1229 | * from a previous transaction | |
1230 | */ | |
5b7d70c6 BD |
1231 | |
1232 | if (hs_req->req.status == -EINPROGRESS) | |
1233 | hs_req->req.status = result; | |
1234 | ||
1235 | hs_ep->req = NULL; | |
1236 | list_del_init(&hs_req->queue); | |
1237 | ||
1238 | if (using_dma(hsotg)) | |
1239 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1240 | ||
8b9bc460 LM |
1241 | /* |
1242 | * call the complete request with the locks off, just in case the | |
1243 | * request tries to queue more work for this endpoint. | |
1244 | */ | |
5b7d70c6 BD |
1245 | |
1246 | if (hs_req->req.complete) { | |
22258f49 | 1247 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1248 | hs_req->req.complete(&hs_ep->ep, &hs_req->req); |
22258f49 | 1249 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1250 | } |
1251 | ||
8b9bc460 LM |
1252 | /* |
1253 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1254 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1255 | * so be careful when doing this. |
1256 | */ | |
5b7d70c6 BD |
1257 | |
1258 | if (!hs_ep->req && result >= 0) { | |
1259 | restart = !list_empty(&hs_ep->queue); | |
1260 | if (restart) { | |
1261 | hs_req = get_ep_head(hs_ep); | |
1262 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1263 | } | |
1264 | } | |
1265 | } | |
1266 | ||
5b7d70c6 BD |
1267 | /** |
1268 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1269 | * @hsotg: The device state. | |
1270 | * @ep_idx: The endpoint index for the data | |
1271 | * @size: The size of data in the fifo, in bytes | |
1272 | * | |
1273 | * The FIFO status shows there is data to read from the FIFO for a given | |
1274 | * endpoint, so sort out whether we need to read the data into a request | |
1275 | * that has been made for that endpoint. | |
1276 | */ | |
1277 | static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size) | |
1278 | { | |
1279 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx]; | |
1280 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1281 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1282 | int to_read; |
1283 | int max_req; | |
1284 | int read_ptr; | |
1285 | ||
22258f49 | 1286 | |
5b7d70c6 | 1287 | if (!hs_req) { |
94cb8fd6 | 1288 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1289 | int ptr; |
1290 | ||
1291 | dev_warn(hsotg->dev, | |
47a1685f | 1292 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1293 | __func__, size, ep_idx, epctl); |
1294 | ||
1295 | /* dump the data from the FIFO, we've nothing we can do */ | |
1296 | for (ptr = 0; ptr < size; ptr += 4) | |
1297 | (void)readl(fifo); | |
1298 | ||
1299 | return; | |
1300 | } | |
1301 | ||
5b7d70c6 BD |
1302 | to_read = size; |
1303 | read_ptr = hs_req->req.actual; | |
1304 | max_req = hs_req->req.length - read_ptr; | |
1305 | ||
a33e7136 BD |
1306 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1307 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1308 | ||
5b7d70c6 | 1309 | if (to_read > max_req) { |
8b9bc460 LM |
1310 | /* |
1311 | * more data appeared than we where willing | |
5b7d70c6 BD |
1312 | * to deal with in this request. |
1313 | */ | |
1314 | ||
1315 | /* currently we don't deal this */ | |
1316 | WARN_ON_ONCE(1); | |
1317 | } | |
1318 | ||
5b7d70c6 BD |
1319 | hs_ep->total_data += to_read; |
1320 | hs_req->req.actual += to_read; | |
1321 | to_read = DIV_ROUND_UP(to_read, 4); | |
1322 | ||
8b9bc460 LM |
1323 | /* |
1324 | * note, we might over-write the buffer end by 3 bytes depending on | |
1325 | * alignment of the data. | |
1326 | */ | |
1a7ed5be | 1327 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1328 | } |
1329 | ||
1330 | /** | |
1331 | * s3c_hsotg_send_zlp - send zero-length packet on control endpoint | |
1332 | * @hsotg: The device instance | |
1333 | * @req: The request currently on this endpoint | |
1334 | * | |
1335 | * Generate a zero-length IN packet request for terminating a SETUP | |
1336 | * transaction. | |
1337 | * | |
1338 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1339 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1340 | * the TxFIFO. |
1341 | */ | |
1342 | static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg, | |
1343 | struct s3c_hsotg_req *req) | |
1344 | { | |
1345 | u32 ctrl; | |
1346 | ||
1347 | if (!req) { | |
1348 | dev_warn(hsotg->dev, "%s: no request?\n", __func__); | |
1349 | return; | |
1350 | } | |
1351 | ||
1352 | if (req->req.length == 0) { | |
1353 | hsotg->eps[0].sent_zlp = 1; | |
1354 | s3c_hsotg_enqueue_setup(hsotg); | |
1355 | return; | |
1356 | } | |
1357 | ||
1358 | hsotg->eps[0].dir_in = 1; | |
1359 | hsotg->eps[0].sent_zlp = 1; | |
1360 | ||
1361 | dev_dbg(hsotg->dev, "sending zero-length packet\n"); | |
1362 | ||
1363 | /* issue a zero-sized packet to terminate this */ | |
47a1685f DN |
1364 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1365 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0)); | |
5b7d70c6 | 1366 | |
94cb8fd6 | 1367 | ctrl = readl(hsotg->regs + DIEPCTL0); |
47a1685f DN |
1368 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1369 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1370 | ctrl |= DXEPCTL_USBACTEP; | |
94cb8fd6 | 1371 | writel(ctrl, hsotg->regs + DIEPCTL0); |
5b7d70c6 BD |
1372 | } |
1373 | ||
1374 | /** | |
1375 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1376 | * @hsotg: The device instance | |
1377 | * @epnum: The endpoint received from | |
1378 | * @was_setup: Set if processing a SetupDone event. | |
1379 | * | |
1380 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1381 | * transfer for an OUT endpoint has been completed, either by a short | |
1382 | * packet or by the finish of a transfer. | |
8b9bc460 | 1383 | */ |
5b7d70c6 BD |
1384 | static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, |
1385 | int epnum, bool was_setup) | |
1386 | { | |
94cb8fd6 | 1387 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
5b7d70c6 BD |
1388 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; |
1389 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1390 | struct usb_request *req = &hs_req->req; | |
47a1685f | 1391 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1392 | int result = 0; |
1393 | ||
1394 | if (!hs_req) { | |
1395 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1396 | return; | |
1397 | } | |
1398 | ||
1399 | if (using_dma(hsotg)) { | |
5b7d70c6 | 1400 | unsigned size_done; |
5b7d70c6 | 1401 | |
8b9bc460 LM |
1402 | /* |
1403 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1404 | * is left in the endpoint size register and then working it |
1405 | * out from the amount we loaded for the transfer. | |
1406 | * | |
1407 | * We need to do this as DMA pointers are always 32bit aligned | |
1408 | * so may overshoot/undershoot the transfer. | |
1409 | */ | |
1410 | ||
5b7d70c6 BD |
1411 | size_done = hs_ep->size_loaded - size_left; |
1412 | size_done += hs_ep->last_load; | |
1413 | ||
1414 | req->actual = size_done; | |
1415 | } | |
1416 | ||
a33e7136 BD |
1417 | /* if there is more request to do, schedule new transfer */ |
1418 | if (req->actual < req->length && size_left == 0) { | |
1419 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1420 | return; | |
71225bee LM |
1421 | } else if (epnum == 0) { |
1422 | /* | |
1423 | * After was_setup = 1 => | |
1424 | * set CNAK for non Setup requests | |
1425 | */ | |
1426 | hsotg->setup = was_setup ? 0 : 1; | |
a33e7136 BD |
1427 | } |
1428 | ||
5b7d70c6 BD |
1429 | if (req->actual < req->length && req->short_not_ok) { |
1430 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1431 | __func__, req->actual, req->length); | |
1432 | ||
8b9bc460 LM |
1433 | /* |
1434 | * todo - what should we return here? there's no one else | |
1435 | * even bothering to check the status. | |
1436 | */ | |
5b7d70c6 BD |
1437 | } |
1438 | ||
1439 | if (epnum == 0) { | |
d3ca0259 LM |
1440 | /* |
1441 | * Condition req->complete != s3c_hsotg_complete_setup says: | |
1442 | * send ZLP when we have an asynchronous request from gadget | |
1443 | */ | |
5b7d70c6 BD |
1444 | if (!was_setup && req->complete != s3c_hsotg_complete_setup) |
1445 | s3c_hsotg_send_zlp(hsotg, hs_req); | |
1446 | } | |
1447 | ||
5ad1d316 | 1448 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1449 | } |
1450 | ||
1451 | /** | |
1452 | * s3c_hsotg_read_frameno - read current frame number | |
1453 | * @hsotg: The device instance | |
1454 | * | |
1455 | * Return the current frame number | |
8b9bc460 | 1456 | */ |
5b7d70c6 BD |
1457 | static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg) |
1458 | { | |
1459 | u32 dsts; | |
1460 | ||
94cb8fd6 LM |
1461 | dsts = readl(hsotg->regs + DSTS); |
1462 | dsts &= DSTS_SOFFN_MASK; | |
1463 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1464 | |
1465 | return dsts; | |
1466 | } | |
1467 | ||
1468 | /** | |
1469 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1470 | * @hsotg: The device instance | |
1471 | * | |
1472 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1473 | * that requires processing, so find out what is in there and do the | |
1474 | * appropriate read. | |
1475 | * | |
25985edc | 1476 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1477 | * chunks, so if you have x packets received on an endpoint you'll get x |
1478 | * FIFO events delivered, each with a packet's worth of data in it. | |
1479 | * | |
1480 | * When using DMA, we should not be processing events from the RXFIFO | |
1481 | * as the actual data should be sent to the memory directly and we turn | |
1482 | * on the completion interrupts to get notifications of transfer completion. | |
1483 | */ | |
0978f8c5 | 1484 | static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) |
5b7d70c6 | 1485 | { |
94cb8fd6 | 1486 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1487 | u32 epnum, status, size; |
1488 | ||
1489 | WARN_ON(using_dma(hsotg)); | |
1490 | ||
47a1685f DN |
1491 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1492 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1493 | |
47a1685f DN |
1494 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1495 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 BD |
1496 | |
1497 | if (1) | |
1498 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1499 | __func__, grxstsr, size, epnum); | |
1500 | ||
47a1685f DN |
1501 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1502 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1503 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1504 | break; |
1505 | ||
47a1685f | 1506 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 BD |
1507 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1508 | s3c_hsotg_read_frameno(hsotg)); | |
1509 | ||
1510 | if (!using_dma(hsotg)) | |
1511 | s3c_hsotg_handle_outdone(hsotg, epnum, false); | |
1512 | break; | |
1513 | ||
47a1685f | 1514 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1515 | dev_dbg(hsotg->dev, |
1516 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1517 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1518 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 BD |
1519 | |
1520 | s3c_hsotg_handle_outdone(hsotg, epnum, true); | |
1521 | break; | |
1522 | ||
47a1685f | 1523 | case GRXSTS_PKTSTS_OUTRX: |
5b7d70c6 BD |
1524 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1525 | break; | |
1526 | ||
47a1685f | 1527 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1528 | dev_dbg(hsotg->dev, |
1529 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1530 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1531 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 BD |
1532 | |
1533 | s3c_hsotg_rx_data(hsotg, epnum, size); | |
1534 | break; | |
1535 | ||
1536 | default: | |
1537 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1538 | __func__, grxstsr); | |
1539 | ||
1540 | s3c_hsotg_dump(hsotg); | |
1541 | break; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | /** | |
1546 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1547 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1548 | */ |
5b7d70c6 BD |
1549 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1550 | { | |
1551 | switch (mps) { | |
1552 | case 64: | |
94cb8fd6 | 1553 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1554 | case 32: |
94cb8fd6 | 1555 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1556 | case 16: |
94cb8fd6 | 1557 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1558 | case 8: |
94cb8fd6 | 1559 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1560 | } |
1561 | ||
1562 | /* bad max packet size, warn and return invalid result */ | |
1563 | WARN_ON(1); | |
1564 | return (u32)-1; | |
1565 | } | |
1566 | ||
1567 | /** | |
1568 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1569 | * @hsotg: The driver state. | |
1570 | * @ep: The index number of the endpoint | |
1571 | * @mps: The maximum packet size in bytes | |
1572 | * | |
1573 | * Configure the maximum packet size for the given endpoint, updating | |
1574 | * the hardware control registers to reflect this. | |
1575 | */ | |
1576 | static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg, | |
1577 | unsigned int ep, unsigned int mps) | |
1578 | { | |
1579 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep]; | |
1580 | void __iomem *regs = hsotg->regs; | |
1581 | u32 mpsval; | |
4fca54aa | 1582 | u32 mcval; |
5b7d70c6 BD |
1583 | u32 reg; |
1584 | ||
1585 | if (ep == 0) { | |
1586 | /* EP0 is a special case */ | |
1587 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1588 | if (mpsval > 3) | |
1589 | goto bad_mps; | |
e9edd199 | 1590 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1591 | hs_ep->mc = 1; |
5b7d70c6 | 1592 | } else { |
47a1685f | 1593 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1594 | if (mpsval > 1024) |
5b7d70c6 | 1595 | goto bad_mps; |
4fca54aa RB |
1596 | mcval = ((mps >> 11) & 0x3) + 1; |
1597 | hs_ep->mc = mcval; | |
1598 | if (mcval > 3) | |
1599 | goto bad_mps; | |
e9edd199 | 1600 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1601 | } |
1602 | ||
8b9bc460 LM |
1603 | /* |
1604 | * update both the in and out endpoint controldir_ registers, even | |
1605 | * if one of the directions may not be in use. | |
1606 | */ | |
5b7d70c6 | 1607 | |
94cb8fd6 | 1608 | reg = readl(regs + DIEPCTL(ep)); |
47a1685f | 1609 | reg &= ~DXEPCTL_MPS_MASK; |
5b7d70c6 | 1610 | reg |= mpsval; |
94cb8fd6 | 1611 | writel(reg, regs + DIEPCTL(ep)); |
5b7d70c6 | 1612 | |
659ad60c | 1613 | if (ep) { |
94cb8fd6 | 1614 | reg = readl(regs + DOEPCTL(ep)); |
47a1685f | 1615 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1616 | reg |= mpsval; |
94cb8fd6 | 1617 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1618 | } |
5b7d70c6 BD |
1619 | |
1620 | return; | |
1621 | ||
1622 | bad_mps: | |
1623 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1624 | } | |
1625 | ||
9c39ddc6 AT |
1626 | /** |
1627 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1628 | * @hsotg: The driver state | |
1629 | * @idx: The index for the endpoint (0..15) | |
1630 | */ | |
1631 | static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx) | |
1632 | { | |
1633 | int timeout; | |
1634 | int val; | |
1635 | ||
47a1685f | 1636 | writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
94cb8fd6 | 1637 | hsotg->regs + GRSTCTL); |
9c39ddc6 AT |
1638 | |
1639 | /* wait until the fifo is flushed */ | |
1640 | timeout = 100; | |
1641 | ||
1642 | while (1) { | |
94cb8fd6 | 1643 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1644 | |
47a1685f | 1645 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1646 | break; |
1647 | ||
1648 | if (--timeout == 0) { | |
1649 | dev_err(hsotg->dev, | |
1650 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1651 | __func__, val); | |
e0cbe595 | 1652 | break; |
9c39ddc6 AT |
1653 | } |
1654 | ||
1655 | udelay(1); | |
1656 | } | |
1657 | } | |
5b7d70c6 BD |
1658 | |
1659 | /** | |
1660 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1661 | * @hsotg: The driver state | |
1662 | * @hs_ep: The driver endpoint to check. | |
1663 | * | |
1664 | * Check to see if there is a request that has data to send, and if so | |
1665 | * make an attempt to write data into the FIFO. | |
1666 | */ | |
1667 | static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg, | |
1668 | struct s3c_hsotg_ep *hs_ep) | |
1669 | { | |
1670 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1671 | ||
afcf4169 RB |
1672 | if (!hs_ep->dir_in || !hs_req) { |
1673 | /** | |
1674 | * if request is not enqueued, we disable interrupts | |
1675 | * for endpoints, excepting ep0 | |
1676 | */ | |
1677 | if (hs_ep->index != 0) | |
1678 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1679 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1680 | return 0; |
afcf4169 | 1681 | } |
5b7d70c6 BD |
1682 | |
1683 | if (hs_req->req.actual < hs_req->req.length) { | |
1684 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1685 | hs_ep->index); | |
1686 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1687 | } | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
1692 | /** | |
1693 | * s3c_hsotg_complete_in - complete IN transfer | |
1694 | * @hsotg: The device state. | |
1695 | * @hs_ep: The endpoint that has just completed. | |
1696 | * | |
1697 | * An IN transfer has been completed, update the transfer's state and then | |
1698 | * call the relevant completion routines. | |
1699 | */ | |
1700 | static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg, | |
1701 | struct s3c_hsotg_ep *hs_ep) | |
1702 | { | |
1703 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1704 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1705 | int size_left, size_done; |
1706 | ||
1707 | if (!hs_req) { | |
1708 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1709 | return; | |
1710 | } | |
1711 | ||
d3ca0259 LM |
1712 | /* Finish ZLP handling for IN EP0 transactions */ |
1713 | if (hsotg->eps[0].sent_zlp) { | |
1714 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
5ad1d316 | 1715 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
d3ca0259 LM |
1716 | return; |
1717 | } | |
1718 | ||
8b9bc460 LM |
1719 | /* |
1720 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1721 | * in the endpoint size register and then working it out from |
1722 | * the amount we loaded for the transfer. | |
1723 | * | |
1724 | * We do this even for DMA, as the transfer may have incremented | |
1725 | * past the end of the buffer (DMA transfers are always 32bit | |
1726 | * aligned). | |
1727 | */ | |
1728 | ||
47a1685f | 1729 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1730 | |
1731 | size_done = hs_ep->size_loaded - size_left; | |
1732 | size_done += hs_ep->last_load; | |
1733 | ||
1734 | if (hs_req->req.actual != size_done) | |
1735 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1736 | __func__, hs_req->req.actual, size_done); | |
1737 | ||
1738 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1739 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1740 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1741 | ||
1742 | /* | |
1743 | * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0 | |
1744 | * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B | |
1745 | * ,256B ... ), after last MPS sized packet send IN ZLP packet to | |
1746 | * inform the host that no more data is available. | |
1747 | * The state of req.zero member is checked to be sure that the value to | |
1748 | * send is smaller than wValue expected from host. | |
1749 | * Check req.length to NOT send another ZLP when the current one is | |
1750 | * under completion (the one for which this completion has been called). | |
1751 | */ | |
1752 | if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero && | |
1753 | hs_req->req.length == hs_req->req.actual && | |
1754 | !(hs_req->req.length % hs_ep->ep.maxpacket)) { | |
1755 | ||
1756 | dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n"); | |
1757 | s3c_hsotg_send_zlp(hsotg, hs_req); | |
5b7d70c6 | 1758 | |
d3ca0259 LM |
1759 | return; |
1760 | } | |
5b7d70c6 BD |
1761 | |
1762 | if (!size_left && hs_req->req.actual < hs_req->req.length) { | |
1763 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1764 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1765 | } else | |
5ad1d316 | 1766 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1767 | } |
1768 | ||
1769 | /** | |
1770 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1771 | * @hsotg: The driver state | |
1772 | * @idx: The index for the endpoint (0..15) | |
1773 | * @dir_in: Set if this is an IN endpoint | |
1774 | * | |
1775 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1776 | */ |
5b7d70c6 BD |
1777 | static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, |
1778 | int dir_in) | |
1779 | { | |
1780 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx]; | |
94cb8fd6 LM |
1781 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1782 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1783 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1784 | u32 ints; |
1479e841 | 1785 | u32 ctrl; |
5b7d70c6 BD |
1786 | |
1787 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1788 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1789 | |
a3395f0d AT |
1790 | /* Clear endpoint interrupts */ |
1791 | writel(ints, hsotg->regs + epint_reg); | |
1792 | ||
5b7d70c6 BD |
1793 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1794 | __func__, idx, dir_in ? "in" : "out", ints); | |
1795 | ||
47a1685f | 1796 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1797 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1798 | if (ctrl & DXEPCTL_EOFRNUM) |
1799 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1800 | else |
47a1685f | 1801 | ctrl |= DXEPCTL_SETODDFR; |
1479e841 RB |
1802 | writel(ctrl, hsotg->regs + epctl_reg); |
1803 | } | |
1804 | ||
5b7d70c6 | 1805 | dev_dbg(hsotg->dev, |
47a1685f | 1806 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
5b7d70c6 BD |
1807 | __func__, readl(hsotg->regs + epctl_reg), |
1808 | readl(hsotg->regs + epsiz_reg)); | |
1809 | ||
8b9bc460 LM |
1810 | /* |
1811 | * we get OutDone from the FIFO, so we only need to look | |
1812 | * at completing IN requests here | |
1813 | */ | |
5b7d70c6 BD |
1814 | if (dir_in) { |
1815 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1816 | ||
c9a64ea8 | 1817 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1818 | s3c_hsotg_enqueue_setup(hsotg); |
1819 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1820 | /* |
1821 | * We're using DMA, we need to fire an OutDone here | |
1822 | * as we ignore the RXFIFO. | |
1823 | */ | |
5b7d70c6 BD |
1824 | |
1825 | s3c_hsotg_handle_outdone(hsotg, idx, false); | |
1826 | } | |
5b7d70c6 BD |
1827 | } |
1828 | ||
47a1685f | 1829 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1830 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1831 | |
9c39ddc6 AT |
1832 | if (dir_in) { |
1833 | int epctl = readl(hsotg->regs + epctl_reg); | |
1834 | ||
1835 | s3c_hsotg_txfifo_flush(hsotg, idx); | |
1836 | ||
47a1685f DN |
1837 | if ((epctl & DXEPCTL_STALL) && |
1838 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
94cb8fd6 | 1839 | int dctl = readl(hsotg->regs + DCTL); |
9c39ddc6 | 1840 | |
47a1685f | 1841 | dctl |= DCTL_CGNPINNAK; |
94cb8fd6 | 1842 | writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
1843 | } |
1844 | } | |
1845 | } | |
1846 | ||
47a1685f | 1847 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 1848 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1849 | |
47a1685f | 1850 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
1851 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
1852 | ||
1853 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
1854 | /* |
1855 | * this is the notification we've received a | |
5b7d70c6 BD |
1856 | * setup packet. In non-DMA mode we'd get this |
1857 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
1858 | * the setup here. |
1859 | */ | |
5b7d70c6 BD |
1860 | |
1861 | if (dir_in) | |
1862 | WARN_ON_ONCE(1); | |
1863 | else | |
1864 | s3c_hsotg_handle_outdone(hsotg, 0, true); | |
1865 | } | |
5b7d70c6 BD |
1866 | } |
1867 | ||
47a1685f | 1868 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 1869 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 1870 | |
1479e841 | 1871 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 1872 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 1873 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
1874 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
1875 | __func__, idx); | |
5b7d70c6 BD |
1876 | } |
1877 | ||
1878 | /* this probably means something bad is happening */ | |
47a1685f | 1879 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
1880 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
1881 | __func__, idx); | |
5b7d70c6 | 1882 | } |
10aebc77 BD |
1883 | |
1884 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1885 | if (hsotg->dedicated_fifos && | |
47a1685f | 1886 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
1887 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
1888 | __func__, idx); | |
70fa030f AT |
1889 | if (!using_dma(hsotg)) |
1890 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1891 | } |
5b7d70c6 | 1892 | } |
5b7d70c6 BD |
1893 | } |
1894 | ||
1895 | /** | |
1896 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1897 | * @hsotg: The device state. | |
1898 | * | |
1899 | * Handle updating the device settings after the enumeration phase has | |
1900 | * been completed. | |
8b9bc460 | 1901 | */ |
5b7d70c6 BD |
1902 | static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) |
1903 | { | |
94cb8fd6 | 1904 | u32 dsts = readl(hsotg->regs + DSTS); |
9b2667f1 | 1905 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 1906 | |
8b9bc460 LM |
1907 | /* |
1908 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 1909 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
1910 | * we connected at. |
1911 | */ | |
5b7d70c6 BD |
1912 | |
1913 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
1914 | ||
8b9bc460 LM |
1915 | /* |
1916 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 1917 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
1918 | * not advertise a 64byte MPS on EP0. |
1919 | */ | |
5b7d70c6 BD |
1920 | |
1921 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
1922 | switch (dsts & DSTS_ENUMSPD_MASK) { |
1923 | case DSTS_ENUMSPD_FS: | |
1924 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 1925 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 1926 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1927 | ep_mps = 1023; |
5b7d70c6 BD |
1928 | break; |
1929 | ||
47a1685f | 1930 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 1931 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 1932 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1933 | ep_mps = 1024; |
5b7d70c6 BD |
1934 | break; |
1935 | ||
47a1685f | 1936 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 1937 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
1938 | /* |
1939 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
1940 | * moment, and the documentation seems to imply that it isn't |
1941 | * supported by the PHYs on some of the devices. | |
1942 | */ | |
1943 | break; | |
1944 | } | |
e538dfda MN |
1945 | dev_info(hsotg->dev, "new device is %s\n", |
1946 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 1947 | |
8b9bc460 LM |
1948 | /* |
1949 | * we should now know the maximum packet size for an | |
1950 | * endpoint, so set the endpoints to a default value. | |
1951 | */ | |
5b7d70c6 BD |
1952 | |
1953 | if (ep0_mps) { | |
1954 | int i; | |
1955 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps); | |
b3f489b2 | 1956 | for (i = 1; i < hsotg->num_of_eps; i++) |
5b7d70c6 BD |
1957 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps); |
1958 | } | |
1959 | ||
1960 | /* ensure after enumeration our EP0 is active */ | |
1961 | ||
1962 | s3c_hsotg_enqueue_setup(hsotg); | |
1963 | ||
1964 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
1965 | readl(hsotg->regs + DIEPCTL0), |
1966 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
1967 | } |
1968 | ||
1969 | /** | |
1970 | * kill_all_requests - remove all requests from the endpoint's queue | |
1971 | * @hsotg: The device state. | |
1972 | * @ep: The endpoint the requests may be on. | |
1973 | * @result: The result code to use. | |
1974 | * @force: Force removal of any current requests | |
1975 | * | |
1976 | * Go through the requests on the given endpoint and mark them | |
1977 | * completed with the given result code. | |
1978 | */ | |
1979 | static void kill_all_requests(struct s3c_hsotg *hsotg, | |
1980 | struct s3c_hsotg_ep *ep, | |
1981 | int result, bool force) | |
1982 | { | |
1983 | struct s3c_hsotg_req *req, *treq; | |
5b7d70c6 BD |
1984 | |
1985 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
8b9bc460 LM |
1986 | /* |
1987 | * currently, we can't do much about an already | |
1988 | * running request on an in endpoint | |
1989 | */ | |
5b7d70c6 BD |
1990 | |
1991 | if (ep->req == req && ep->dir_in && !force) | |
1992 | continue; | |
1993 | ||
1994 | s3c_hsotg_complete_request(hsotg, ep, req, | |
1995 | result); | |
1996 | } | |
e9ebe7c3 | 1997 | if (hsotg->dedicated_fifos) |
b963a81a RB |
1998 | if ((readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4 < 3072) |
1999 | s3c_hsotg_txfifo_flush(hsotg, ep->index); | |
5b7d70c6 BD |
2000 | } |
2001 | ||
5b7d70c6 | 2002 | /** |
5e891342 | 2003 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2004 | * @hsotg: The device state. |
2005 | * | |
5e891342 LM |
2006 | * The device has been disconnected. Remove all current |
2007 | * transactions and signal the gadget driver that this | |
2008 | * has happened. | |
8b9bc460 | 2009 | */ |
5e891342 | 2010 | static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
2011 | { |
2012 | unsigned ep; | |
2013 | ||
b3f489b2 | 2014 | for (ep = 0; ep < hsotg->num_of_eps; ep++) |
5b7d70c6 BD |
2015 | kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true); |
2016 | ||
2017 | call_gadget(hsotg, disconnect); | |
2018 | } | |
2019 | ||
2020 | /** | |
2021 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2022 | * @hsotg: The device state: | |
2023 | * @periodic: True if this is a periodic FIFO interrupt | |
2024 | */ | |
2025 | static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic) | |
2026 | { | |
2027 | struct s3c_hsotg_ep *ep; | |
2028 | int epno, ret; | |
2029 | ||
2030 | /* look through for any more data to transmit */ | |
2031 | ||
b3f489b2 | 2032 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
5b7d70c6 BD |
2033 | ep = &hsotg->eps[epno]; |
2034 | ||
2035 | if (!ep->dir_in) | |
2036 | continue; | |
2037 | ||
2038 | if ((periodic && !ep->periodic) || | |
2039 | (!periodic && ep->periodic)) | |
2040 | continue; | |
2041 | ||
2042 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2043 | if (ret < 0) | |
2044 | break; | |
2045 | } | |
2046 | } | |
2047 | ||
5b7d70c6 | 2048 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2049 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2050 | GINTSTS_PTXFEMP | \ | |
2051 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2052 | |
308d734e LM |
2053 | /** |
2054 | * s3c_hsotg_corereset - issue softreset to the core | |
2055 | * @hsotg: The device state | |
2056 | * | |
2057 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2058 | */ |
308d734e LM |
2059 | static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg) |
2060 | { | |
2061 | int timeout; | |
2062 | u32 grstctl; | |
2063 | ||
2064 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2065 | ||
2066 | /* issue soft reset */ | |
47a1685f | 2067 | writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2068 | |
2868fea2 | 2069 | timeout = 10000; |
308d734e | 2070 | do { |
94cb8fd6 | 2071 | grstctl = readl(hsotg->regs + GRSTCTL); |
47a1685f | 2072 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2073 | |
47a1685f | 2074 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2075 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2076 | return -EINVAL; | |
2077 | } | |
2078 | ||
2868fea2 | 2079 | timeout = 10000; |
308d734e LM |
2080 | |
2081 | while (1) { | |
94cb8fd6 | 2082 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2083 | |
2084 | if (timeout-- < 0) { | |
2085 | dev_info(hsotg->dev, | |
2086 | "%s: reset failed, GRSTCTL=%08x\n", | |
2087 | __func__, grstctl); | |
2088 | return -ETIMEDOUT; | |
2089 | } | |
2090 | ||
47a1685f | 2091 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2092 | continue; |
2093 | ||
2094 | break; /* reset done */ | |
2095 | } | |
2096 | ||
2097 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2098 | return 0; | |
2099 | } | |
2100 | ||
8b9bc460 LM |
2101 | /** |
2102 | * s3c_hsotg_core_init - issue softreset to the core | |
2103 | * @hsotg: The device state | |
2104 | * | |
2105 | * Issue a soft reset to the core, and await the core finishing it. | |
2106 | */ | |
308d734e LM |
2107 | static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg) |
2108 | { | |
2109 | s3c_hsotg_corereset(hsotg); | |
2110 | ||
2111 | /* | |
2112 | * we must now enable ep0 ready for host detection and then | |
2113 | * set configuration. | |
2114 | */ | |
2115 | ||
2116 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2117 | writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
94cb8fd6 | 2118 | (0x5 << 10), hsotg->regs + GUSBCFG); |
308d734e LM |
2119 | |
2120 | s3c_hsotg_init_fifo(hsotg); | |
2121 | ||
47a1685f | 2122 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 2123 | |
47a1685f | 2124 | writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2125 | |
2126 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2127 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2128 | |
2129 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2130 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2131 | |
47a1685f DN |
2132 | writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
2133 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | | |
2134 | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | | |
2135 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2136 | GINTSTS_USBSUSP | GINTSTS_WKUPINT, | |
2137 | hsotg->regs + GINTMSK); | |
308d734e LM |
2138 | |
2139 | if (using_dma(hsotg)) | |
47a1685f DN |
2140 | writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2141 | GAHBCFG_HBSTLEN_INCR4, | |
94cb8fd6 | 2142 | hsotg->regs + GAHBCFG); |
308d734e | 2143 | else |
47a1685f DN |
2144 | writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | |
2145 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2146 | GAHBCFG_GLBL_INTR_EN, | |
8acc8296 | 2147 | hsotg->regs + GAHBCFG); |
308d734e LM |
2148 | |
2149 | /* | |
8acc8296 RB |
2150 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2151 | * when we have no data to transfer. Otherwise we get being flooded by | |
2152 | * interrupts. | |
308d734e LM |
2153 | */ |
2154 | ||
47a1685f DN |
2155 | writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY | |
2156 | DIEPMSK_INTKNTXFEMPMSK : 0) | | |
2157 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | | |
2158 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2159 | DIEPMSK_INTKNEPMISMSK, | |
2160 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2161 | |
2162 | /* | |
2163 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2164 | * DMA mode we may need this. | |
2165 | */ | |
47a1685f DN |
2166 | writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
2167 | DIEPMSK_TIMEOUTMSK) : 0) | | |
2168 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2169 | DOEPMSK_SETUPMSK, | |
2170 | hsotg->regs + DOEPMSK); | |
308d734e | 2171 | |
94cb8fd6 | 2172 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2173 | |
2174 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2175 | readl(hsotg->regs + DIEPCTL0), |
2176 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2177 | |
2178 | /* enable in and out endpoint interrupts */ | |
47a1685f | 2179 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2180 | |
2181 | /* | |
2182 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2183 | * the data. In DMA mode, we get events from the FIFO but also | |
2184 | * things we cannot process, so do not use it. | |
2185 | */ | |
2186 | if (!using_dma(hsotg)) | |
47a1685f | 2187 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2188 | |
2189 | /* Enable interrupts for EP0 in and out */ | |
2190 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2191 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2192 | ||
47a1685f | 2193 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2194 | udelay(10); /* see openiboot */ |
47a1685f | 2195 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2196 | |
94cb8fd6 | 2197 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2198 | |
2199 | /* | |
94cb8fd6 | 2200 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2201 | * writing to the EPCTL register.. |
2202 | */ | |
2203 | ||
2204 | /* set to read 1 8byte packet */ | |
47a1685f DN |
2205 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2206 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); | |
308d734e LM |
2207 | |
2208 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
47a1685f DN |
2209 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2210 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2211 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2212 | |
2213 | /* enable, but don't activate EP0in */ | |
2214 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
47a1685f | 2215 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e LM |
2216 | |
2217 | s3c_hsotg_enqueue_setup(hsotg); | |
2218 | ||
2219 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2220 | readl(hsotg->regs + DIEPCTL0), |
2221 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2222 | |
2223 | /* clear global NAKs */ | |
47a1685f | 2224 | writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK, |
94cb8fd6 | 2225 | hsotg->regs + DCTL); |
308d734e LM |
2226 | |
2227 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2228 | mdelay(3); | |
2229 | ||
2230 | /* remove the soft-disconnect and let's go */ | |
47a1685f | 2231 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2232 | } |
2233 | ||
5b7d70c6 BD |
2234 | /** |
2235 | * s3c_hsotg_irq - handle device interrupt | |
2236 | * @irq: The IRQ number triggered | |
2237 | * @pw: The pw value when registered the handler. | |
2238 | */ | |
2239 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2240 | { | |
2241 | struct s3c_hsotg *hsotg = pw; | |
2242 | int retry_count = 8; | |
2243 | u32 gintsts; | |
2244 | u32 gintmsk; | |
2245 | ||
5ad1d316 | 2246 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2247 | irq_retry: |
94cb8fd6 LM |
2248 | gintsts = readl(hsotg->regs + GINTSTS); |
2249 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2250 | |
2251 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2252 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2253 | ||
2254 | gintsts &= gintmsk; | |
2255 | ||
47a1685f | 2256 | if (gintsts & GINTSTS_OTGINT) { |
94cb8fd6 | 2257 | u32 otgint = readl(hsotg->regs + GOTGINT); |
5b7d70c6 BD |
2258 | |
2259 | dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); | |
2260 | ||
94cb8fd6 | 2261 | writel(otgint, hsotg->regs + GOTGINT); |
5b7d70c6 BD |
2262 | } |
2263 | ||
47a1685f | 2264 | if (gintsts & GINTSTS_SESSREQINT) { |
5b7d70c6 | 2265 | dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); |
47a1685f | 2266 | writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2267 | } |
2268 | ||
47a1685f DN |
2269 | if (gintsts & GINTSTS_ENUMDONE) { |
2270 | writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2271 | |
2272 | s3c_hsotg_irq_enumdone(hsotg); | |
5b7d70c6 BD |
2273 | } |
2274 | ||
47a1685f | 2275 | if (gintsts & GINTSTS_CONIDSTSCHNG) { |
5b7d70c6 | 2276 | dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", |
94cb8fd6 LM |
2277 | readl(hsotg->regs + DSTS), |
2278 | readl(hsotg->regs + GOTGCTL)); | |
5b7d70c6 | 2279 | |
47a1685f | 2280 | writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2281 | } |
2282 | ||
47a1685f | 2283 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
94cb8fd6 | 2284 | u32 daint = readl(hsotg->regs + DAINT); |
7e804650 RB |
2285 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2286 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2287 | int ep; |
2288 | ||
7e804650 | 2289 | daint &= daintmsk; |
47a1685f DN |
2290 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2291 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2292 | |
5b7d70c6 BD |
2293 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2294 | ||
2295 | for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) { | |
2296 | if (daint_out & 1) | |
2297 | s3c_hsotg_epint(hsotg, ep, 0); | |
2298 | } | |
2299 | ||
2300 | for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) { | |
2301 | if (daint_in & 1) | |
2302 | s3c_hsotg_epint(hsotg, ep, 1); | |
2303 | } | |
5b7d70c6 BD |
2304 | } |
2305 | ||
47a1685f | 2306 | if (gintsts & GINTSTS_USBRST) { |
12a1f4dc | 2307 | |
94cb8fd6 | 2308 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2309 | |
5b7d70c6 BD |
2310 | dev_info(hsotg->dev, "%s: USBRst\n", __func__); |
2311 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
94cb8fd6 | 2312 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2313 | |
47a1685f | 2314 | writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2315 | |
94cb8fd6 | 2316 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2317 | if (time_after(jiffies, hsotg->last_rst + |
2318 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2319 | |
12a1f4dc LM |
2320 | kill_all_requests(hsotg, &hsotg->eps[0], |
2321 | -ECONNRESET, true); | |
5b7d70c6 | 2322 | |
12a1f4dc LM |
2323 | s3c_hsotg_core_init(hsotg); |
2324 | hsotg->last_rst = jiffies; | |
2325 | } | |
2326 | } | |
5b7d70c6 BD |
2327 | } |
2328 | ||
2329 | /* check both FIFOs */ | |
2330 | ||
47a1685f | 2331 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2332 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2333 | ||
8b9bc460 LM |
2334 | /* |
2335 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2336 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2337 | * it needs re-enabling |
2338 | */ | |
5b7d70c6 | 2339 | |
47a1685f | 2340 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 | 2341 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2342 | } |
2343 | ||
47a1685f | 2344 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2345 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2346 | ||
94cb8fd6 | 2347 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2348 | |
47a1685f | 2349 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 | 2350 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2351 | } |
2352 | ||
47a1685f | 2353 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2354 | /* |
2355 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2356 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2357 | * set. |
2358 | */ | |
5b7d70c6 BD |
2359 | |
2360 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2361 | } |
2362 | ||
47a1685f | 2363 | if (gintsts & GINTSTS_MODEMIS) { |
5b7d70c6 | 2364 | dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); |
47a1685f | 2365 | writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2366 | } |
2367 | ||
47a1685f | 2368 | if (gintsts & GINTSTS_USBSUSP) { |
94cb8fd6 | 2369 | dev_info(hsotg->dev, "GINTSTS_USBSusp\n"); |
47a1685f | 2370 | writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2371 | |
2372 | call_gadget(hsotg, suspend); | |
2373 | } | |
2374 | ||
47a1685f | 2375 | if (gintsts & GINTSTS_WKUPINT) { |
94cb8fd6 | 2376 | dev_info(hsotg->dev, "GINTSTS_WkUpIn\n"); |
47a1685f | 2377 | writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2378 | |
2379 | call_gadget(hsotg, resume); | |
2380 | } | |
2381 | ||
47a1685f | 2382 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2383 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
47a1685f | 2384 | writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2385 | } |
2386 | ||
8b9bc460 LM |
2387 | /* |
2388 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2389 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2390 | * the occurrence. |
2391 | */ | |
5b7d70c6 | 2392 | |
47a1685f | 2393 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2394 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2395 | ||
47a1685f | 2396 | writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2397 | |
2398 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2399 | } |
2400 | ||
47a1685f | 2401 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2402 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2403 | ||
47a1685f | 2404 | writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2405 | |
2406 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2407 | } |
2408 | ||
8b9bc460 LM |
2409 | /* |
2410 | * if we've had fifo events, we should try and go around the | |
2411 | * loop again to see if there's any point in returning yet. | |
2412 | */ | |
5b7d70c6 BD |
2413 | |
2414 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2415 | goto irq_retry; | |
2416 | ||
5ad1d316 LM |
2417 | spin_unlock(&hsotg->lock); |
2418 | ||
5b7d70c6 BD |
2419 | return IRQ_HANDLED; |
2420 | } | |
2421 | ||
2422 | /** | |
2423 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2424 | * @ep: The USB endpint to configure | |
2425 | * @desc: The USB endpoint descriptor to configure with. | |
2426 | * | |
2427 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2428 | */ |
5b7d70c6 BD |
2429 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2430 | const struct usb_endpoint_descriptor *desc) | |
2431 | { | |
2432 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2433 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2434 | unsigned long flags; | |
2435 | int index = hs_ep->index; | |
2436 | u32 epctrl_reg; | |
2437 | u32 epctrl; | |
2438 | u32 mps; | |
2439 | int dir_in; | |
19c190f9 | 2440 | int ret = 0; |
5b7d70c6 BD |
2441 | |
2442 | dev_dbg(hsotg->dev, | |
2443 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2444 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2445 | desc->wMaxPacketSize, desc->bInterval); | |
2446 | ||
2447 | /* not to be called for EP0 */ | |
2448 | WARN_ON(index == 0); | |
2449 | ||
2450 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2451 | if (dir_in != hs_ep->dir_in) { | |
2452 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2453 | return -EINVAL; | |
2454 | } | |
2455 | ||
29cc8897 | 2456 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2457 | |
2458 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2459 | ||
94cb8fd6 | 2460 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2461 | epctrl = readl(hsotg->regs + epctrl_reg); |
2462 | ||
2463 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2464 | __func__, epctrl, epctrl_reg); | |
2465 | ||
22258f49 | 2466 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2467 | |
47a1685f DN |
2468 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2469 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2470 | |
8b9bc460 LM |
2471 | /* |
2472 | * mark the endpoint as active, otherwise the core may ignore | |
2473 | * transactions entirely for this endpoint | |
2474 | */ | |
47a1685f | 2475 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2476 | |
8b9bc460 LM |
2477 | /* |
2478 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2479 | * do something with data that we've yet got a request to process |
2480 | * since the RXFIFO will take data for an endpoint even if the | |
2481 | * size register hasn't been set. | |
2482 | */ | |
2483 | ||
47a1685f | 2484 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2485 | |
2486 | /* update the endpoint state */ | |
e9edd199 | 2487 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps); |
5b7d70c6 BD |
2488 | |
2489 | /* default, set to non-periodic */ | |
1479e841 | 2490 | hs_ep->isochronous = 0; |
5b7d70c6 | 2491 | hs_ep->periodic = 0; |
a18ed7b0 | 2492 | hs_ep->halted = 0; |
1479e841 | 2493 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2494 | |
4fca54aa RB |
2495 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2496 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2497 | ||
5b7d70c6 BD |
2498 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2499 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2500 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2501 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2502 | hs_ep->isochronous = 1; |
2503 | if (dir_in) | |
2504 | hs_ep->periodic = 1; | |
2505 | break; | |
5b7d70c6 BD |
2506 | |
2507 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2508 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2509 | break; |
2510 | ||
2511 | case USB_ENDPOINT_XFER_INT: | |
2512 | if (dir_in) { | |
8b9bc460 LM |
2513 | /* |
2514 | * Allocate our TxFNum by simply using the index | |
5b7d70c6 BD |
2515 | * of the endpoint for the moment. We could do |
2516 | * something better if the host indicates how | |
8b9bc460 LM |
2517 | * many FIFOs we are expecting to use. |
2518 | */ | |
5b7d70c6 BD |
2519 | |
2520 | hs_ep->periodic = 1; | |
47a1685f | 2521 | epctrl |= DXEPCTL_TXFNUM(index); |
5b7d70c6 BD |
2522 | } |
2523 | ||
47a1685f | 2524 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2525 | break; |
2526 | ||
2527 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2528 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2529 | break; |
2530 | } | |
2531 | ||
8b9bc460 LM |
2532 | /* |
2533 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2534 | * a unique tx-fifo even if it is non-periodic. |
2535 | */ | |
2536 | if (dir_in && hsotg->dedicated_fifos) | |
47a1685f | 2537 | epctrl |= DXEPCTL_TXFNUM(index); |
10aebc77 | 2538 | |
5b7d70c6 BD |
2539 | /* for non control endpoints, set PID to D0 */ |
2540 | if (index) | |
47a1685f | 2541 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2542 | |
2543 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2544 | __func__, epctrl); | |
2545 | ||
2546 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2547 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2548 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2549 | ||
2550 | /* enable the endpoint interrupt */ | |
2551 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2552 | ||
22258f49 | 2553 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2554 | return ret; |
5b7d70c6 BD |
2555 | } |
2556 | ||
8b9bc460 LM |
2557 | /** |
2558 | * s3c_hsotg_ep_disable - disable given endpoint | |
2559 | * @ep: The endpoint to disable. | |
2560 | */ | |
5b7d70c6 BD |
2561 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2562 | { | |
2563 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2564 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2565 | int dir_in = hs_ep->dir_in; | |
2566 | int index = hs_ep->index; | |
2567 | unsigned long flags; | |
2568 | u32 epctrl_reg; | |
2569 | u32 ctrl; | |
2570 | ||
2571 | dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep); | |
2572 | ||
2573 | if (ep == &hsotg->eps[0].ep) { | |
2574 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); | |
2575 | return -EINVAL; | |
2576 | } | |
2577 | ||
94cb8fd6 | 2578 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2579 | |
5ad1d316 | 2580 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
2581 | /* terminate all requests with shutdown */ |
2582 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); | |
2583 | ||
5b7d70c6 BD |
2584 | |
2585 | ctrl = readl(hsotg->regs + epctrl_reg); | |
47a1685f DN |
2586 | ctrl &= ~DXEPCTL_EPENA; |
2587 | ctrl &= ~DXEPCTL_USBACTEP; | |
2588 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2589 | |
2590 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2591 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2592 | ||
2593 | /* disable endpoint interrupts */ | |
2594 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2595 | ||
22258f49 | 2596 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2597 | return 0; |
2598 | } | |
2599 | ||
2600 | /** | |
2601 | * on_list - check request is on the given endpoint | |
2602 | * @ep: The endpoint to check. | |
2603 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2604 | */ |
5b7d70c6 BD |
2605 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2606 | { | |
2607 | struct s3c_hsotg_req *req, *treq; | |
2608 | ||
2609 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2610 | if (req == test) | |
2611 | return true; | |
2612 | } | |
2613 | ||
2614 | return false; | |
2615 | } | |
2616 | ||
8b9bc460 LM |
2617 | /** |
2618 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2619 | * @ep: The endpoint to dequeue. | |
2620 | * @req: The request to be removed from a queue. | |
2621 | */ | |
5b7d70c6 BD |
2622 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2623 | { | |
2624 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2625 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2626 | struct s3c_hsotg *hs = hs_ep->parent; | |
2627 | unsigned long flags; | |
2628 | ||
2629 | dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); | |
2630 | ||
22258f49 | 2631 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2632 | |
2633 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2634 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2635 | return -EINVAL; |
2636 | } | |
2637 | ||
2638 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2639 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2640 | |
2641 | return 0; | |
2642 | } | |
2643 | ||
8b9bc460 LM |
2644 | /** |
2645 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2646 | * @ep: The endpoint to set halt. | |
2647 | * @value: Set or unset the halt. | |
2648 | */ | |
5b7d70c6 BD |
2649 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2650 | { | |
2651 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2652 | struct s3c_hsotg *hs = hs_ep->parent; | |
2653 | int index = hs_ep->index; | |
5b7d70c6 BD |
2654 | u32 epreg; |
2655 | u32 epctl; | |
9c39ddc6 | 2656 | u32 xfertype; |
5b7d70c6 BD |
2657 | |
2658 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2659 | ||
c9f721b2 RB |
2660 | if (index == 0) { |
2661 | if (value) | |
2662 | s3c_hsotg_stall_ep0(hs); | |
2663 | else | |
2664 | dev_warn(hs->dev, | |
2665 | "%s: can't clear halt on ep0\n", __func__); | |
2666 | return 0; | |
2667 | } | |
2668 | ||
5b7d70c6 BD |
2669 | /* write both IN and OUT control registers */ |
2670 | ||
94cb8fd6 | 2671 | epreg = DIEPCTL(index); |
5b7d70c6 BD |
2672 | epctl = readl(hs->regs + epreg); |
2673 | ||
9c39ddc6 | 2674 | if (value) { |
47a1685f DN |
2675 | epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; |
2676 | if (epctl & DXEPCTL_EPENA) | |
2677 | epctl |= DXEPCTL_EPDIS; | |
9c39ddc6 | 2678 | } else { |
47a1685f DN |
2679 | epctl &= ~DXEPCTL_STALL; |
2680 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2681 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2682 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2683 | epctl |= DXEPCTL_SETD0PID; | |
9c39ddc6 | 2684 | } |
5b7d70c6 BD |
2685 | |
2686 | writel(epctl, hs->regs + epreg); | |
2687 | ||
94cb8fd6 | 2688 | epreg = DOEPCTL(index); |
5b7d70c6 BD |
2689 | epctl = readl(hs->regs + epreg); |
2690 | ||
2691 | if (value) | |
47a1685f | 2692 | epctl |= DXEPCTL_STALL; |
9c39ddc6 | 2693 | else { |
47a1685f DN |
2694 | epctl &= ~DXEPCTL_STALL; |
2695 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2696 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2697 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2698 | epctl |= DXEPCTL_SETD0PID; | |
9c39ddc6 | 2699 | } |
5b7d70c6 BD |
2700 | |
2701 | writel(epctl, hs->regs + epreg); | |
2702 | ||
a18ed7b0 RB |
2703 | hs_ep->halted = value; |
2704 | ||
5b7d70c6 BD |
2705 | return 0; |
2706 | } | |
2707 | ||
5ad1d316 LM |
2708 | /** |
2709 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2710 | * @ep: The endpoint to set halt. | |
2711 | * @value: Set or unset the halt. | |
2712 | */ | |
2713 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2714 | { | |
2715 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2716 | struct s3c_hsotg *hs = hs_ep->parent; | |
2717 | unsigned long flags = 0; | |
2718 | int ret = 0; | |
2719 | ||
2720 | spin_lock_irqsave(&hs->lock, flags); | |
2721 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2722 | spin_unlock_irqrestore(&hs->lock, flags); | |
2723 | ||
2724 | return ret; | |
2725 | } | |
2726 | ||
5b7d70c6 BD |
2727 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2728 | .enable = s3c_hsotg_ep_enable, | |
2729 | .disable = s3c_hsotg_ep_disable, | |
2730 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2731 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2732 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2733 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2734 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2735 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2736 | }; |
2737 | ||
41188786 LM |
2738 | /** |
2739 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2740 | * @hsotg: The driver state |
41188786 LM |
2741 | * |
2742 | * A wrapper for platform code responsible for controlling | |
2743 | * low-level USB code | |
2744 | */ | |
2745 | static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg) | |
2746 | { | |
2747 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2748 | ||
2749 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 2750 | |
ca2c5ba8 | 2751 | if (hsotg->uphy) |
74084844 | 2752 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 2753 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 2754 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2755 | else { |
2756 | phy_init(hsotg->phy); | |
2757 | phy_power_on(hsotg->phy); | |
2758 | } | |
41188786 LM |
2759 | } |
2760 | ||
2761 | /** | |
2762 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2763 | * @hsotg: The driver state |
41188786 LM |
2764 | * |
2765 | * A wrapper for platform code responsible for controlling | |
2766 | * low-level USB code | |
2767 | */ | |
2768 | static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg) | |
2769 | { | |
2770 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2771 | ||
ca2c5ba8 | 2772 | if (hsotg->uphy) |
74084844 | 2773 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 2774 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 2775 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2776 | else { |
2777 | phy_power_off(hsotg->phy); | |
2778 | phy_exit(hsotg->phy); | |
2779 | } | |
41188786 LM |
2780 | } |
2781 | ||
8b9bc460 LM |
2782 | /** |
2783 | * s3c_hsotg_init - initalize the usb core | |
2784 | * @hsotg: The driver state | |
2785 | */ | |
b3f489b2 LM |
2786 | static void s3c_hsotg_init(struct s3c_hsotg *hsotg) |
2787 | { | |
2788 | /* unmask subset of endpoint interrupts */ | |
2789 | ||
47a1685f DN |
2790 | writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
2791 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
2792 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2793 | |
47a1685f DN |
2794 | writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
2795 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
2796 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2797 | |
94cb8fd6 | 2798 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2799 | |
2800 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 2801 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 LM |
2802 | |
2803 | if (0) { | |
2804 | /* post global nak until we're ready */ | |
47a1685f | 2805 | writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, |
94cb8fd6 | 2806 | hsotg->regs + DCTL); |
b3f489b2 LM |
2807 | } |
2808 | ||
2809 | /* setup fifos */ | |
2810 | ||
2811 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2812 | readl(hsotg->regs + GRXFSIZ), |
2813 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2814 | |
2815 | s3c_hsotg_init_fifo(hsotg); | |
2816 | ||
2817 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2818 | writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), |
94cb8fd6 | 2819 | hsotg->regs + GUSBCFG); |
b3f489b2 | 2820 | |
47a1685f | 2821 | writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0, |
94cb8fd6 | 2822 | hsotg->regs + GAHBCFG); |
b3f489b2 LM |
2823 | } |
2824 | ||
8b9bc460 LM |
2825 | /** |
2826 | * s3c_hsotg_udc_start - prepare the udc for work | |
2827 | * @gadget: The usb gadget state | |
2828 | * @driver: The usb gadget driver | |
2829 | * | |
2830 | * Perform initialization to prepare udc device and driver | |
2831 | * to work. | |
2832 | */ | |
f65f0f10 LM |
2833 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2834 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2835 | { |
f99b2bfe | 2836 | struct s3c_hsotg *hsotg = to_hsotg(gadget); |
5b7d70c6 BD |
2837 | int ret; |
2838 | ||
2839 | if (!hsotg) { | |
a023da33 | 2840 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2841 | return -ENODEV; |
2842 | } | |
2843 | ||
2844 | if (!driver) { | |
2845 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2846 | return -EINVAL; | |
2847 | } | |
2848 | ||
7177aed4 | 2849 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2850 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2851 | |
f65f0f10 | 2852 | if (!driver->setup) { |
5b7d70c6 BD |
2853 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2854 | return -EINVAL; | |
2855 | } | |
2856 | ||
2857 | WARN_ON(hsotg->driver); | |
2858 | ||
2859 | driver->driver.bus = NULL; | |
2860 | hsotg->driver = driver; | |
7d7b2292 | 2861 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2862 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2863 | ||
f65f0f10 LM |
2864 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2865 | hsotg->supplies); | |
5b7d70c6 | 2866 | if (ret) { |
f65f0f10 | 2867 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
2868 | goto err; |
2869 | } | |
2870 | ||
12a1f4dc | 2871 | hsotg->last_rst = jiffies; |
5b7d70c6 BD |
2872 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
2873 | return 0; | |
2874 | ||
2875 | err: | |
2876 | hsotg->driver = NULL; | |
5b7d70c6 BD |
2877 | return ret; |
2878 | } | |
2879 | ||
8b9bc460 LM |
2880 | /** |
2881 | * s3c_hsotg_udc_stop - stop the udc | |
2882 | * @gadget: The usb gadget state | |
2883 | * @driver: The usb gadget driver | |
2884 | * | |
2885 | * Stop udc hw block and stay tunned for future transmissions | |
2886 | */ | |
f65f0f10 LM |
2887 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget, |
2888 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2889 | { |
f99b2bfe | 2890 | struct s3c_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 2891 | unsigned long flags = 0; |
5b7d70c6 BD |
2892 | int ep; |
2893 | ||
2894 | if (!hsotg) | |
2895 | return -ENODEV; | |
2896 | ||
5b7d70c6 | 2897 | /* all endpoints should be shutdown */ |
604eac3c | 2898 | for (ep = 1; ep < hsotg->num_of_eps; ep++) |
5b7d70c6 BD |
2899 | s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); |
2900 | ||
2b19a52c LM |
2901 | spin_lock_irqsave(&hsotg->lock, flags); |
2902 | ||
c8c10253 MS |
2903 | if (!driver) |
2904 | hsotg->driver = NULL; | |
2905 | ||
5b7d70c6 | 2906 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
5b7d70c6 | 2907 | |
2b19a52c LM |
2908 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2909 | ||
c8c10253 | 2910 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 BD |
2911 | |
2912 | return 0; | |
2913 | } | |
5b7d70c6 | 2914 | |
8b9bc460 LM |
2915 | /** |
2916 | * s3c_hsotg_gadget_getframe - read the frame number | |
2917 | * @gadget: The usb gadget state | |
2918 | * | |
2919 | * Read the {micro} frame number | |
2920 | */ | |
5b7d70c6 BD |
2921 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
2922 | { | |
2923 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
2924 | } | |
2925 | ||
a188b689 LM |
2926 | /** |
2927 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
2928 | * @gadget: The usb gadget state | |
2929 | * @is_on: Current state of the USB PHY | |
2930 | * | |
2931 | * Connect/Disconnect the USB PHY pullup | |
2932 | */ | |
2933 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
2934 | { | |
2935 | struct s3c_hsotg *hsotg = to_hsotg(gadget); | |
2936 | unsigned long flags = 0; | |
2937 | ||
d784f1e5 | 2938 | dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on); |
a188b689 LM |
2939 | |
2940 | spin_lock_irqsave(&hsotg->lock, flags); | |
2941 | if (is_on) { | |
2942 | s3c_hsotg_phy_enable(hsotg); | |
2943 | s3c_hsotg_core_init(hsotg); | |
2944 | } else { | |
a188b689 LM |
2945 | s3c_hsotg_phy_disable(hsotg); |
2946 | } | |
2947 | ||
2948 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
2949 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
2950 | ||
2951 | return 0; | |
2952 | } | |
2953 | ||
eeef4587 | 2954 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 2955 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
2956 | .udc_start = s3c_hsotg_udc_start, |
2957 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 2958 | .pullup = s3c_hsotg_pullup, |
5b7d70c6 BD |
2959 | }; |
2960 | ||
2961 | /** | |
2962 | * s3c_hsotg_initep - initialise a single endpoint | |
2963 | * @hsotg: The device state. | |
2964 | * @hs_ep: The endpoint to be initialised. | |
2965 | * @epnum: The endpoint number | |
2966 | * | |
2967 | * Initialise the given endpoint (as part of the probe and device state | |
2968 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
2969 | * direction information and other state that may be required. | |
2970 | */ | |
41ac7b3a | 2971 | static void s3c_hsotg_initep(struct s3c_hsotg *hsotg, |
5b7d70c6 BD |
2972 | struct s3c_hsotg_ep *hs_ep, |
2973 | int epnum) | |
2974 | { | |
2975 | u32 ptxfifo; | |
2976 | char *dir; | |
2977 | ||
2978 | if (epnum == 0) | |
2979 | dir = ""; | |
2980 | else if ((epnum % 2) == 0) { | |
2981 | dir = "out"; | |
2982 | } else { | |
2983 | dir = "in"; | |
2984 | hs_ep->dir_in = 1; | |
2985 | } | |
2986 | ||
2987 | hs_ep->index = epnum; | |
2988 | ||
2989 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
2990 | ||
2991 | INIT_LIST_HEAD(&hs_ep->queue); | |
2992 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
2993 | ||
5b7d70c6 BD |
2994 | /* add to the list of endpoints known by the gadget driver */ |
2995 | if (epnum) | |
2996 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
2997 | ||
2998 | hs_ep->parent = hsotg; | |
2999 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3000 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
5b7d70c6 BD |
3001 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3002 | ||
8b9bc460 LM |
3003 | /* |
3004 | * Read the FIFO size for the Periodic TX FIFO, even if we're | |
5b7d70c6 BD |
3005 | * an OUT endpoint, we may as well do this if in future the |
3006 | * code is changed to make each endpoint's direction changeable. | |
3007 | */ | |
3008 | ||
47a1685f DN |
3009 | ptxfifo = readl(hsotg->regs + DPTXFSIZN(epnum)); |
3010 | hs_ep->fifo_size = FIFOSIZE_DEPTH_GET(ptxfifo) * 4; | |
5b7d70c6 | 3011 | |
8b9bc460 LM |
3012 | /* |
3013 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3014 | * to be something valid. |
3015 | */ | |
3016 | ||
3017 | if (using_dma(hsotg)) { | |
47a1685f | 3018 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
94cb8fd6 LM |
3019 | writel(next, hsotg->regs + DIEPCTL(epnum)); |
3020 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3021 | } |
3022 | } | |
3023 | ||
b3f489b2 LM |
3024 | /** |
3025 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3026 | * @param: The device state | |
3027 | * | |
3028 | * Read the USB core HW configuration registers | |
3029 | */ | |
3030 | static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg) | |
5b7d70c6 | 3031 | { |
b3f489b2 LM |
3032 | u32 cfg2, cfg4; |
3033 | /* check hardware configuration */ | |
5b7d70c6 | 3034 | |
b3f489b2 LM |
3035 | cfg2 = readl(hsotg->regs + 0x48); |
3036 | hsotg->num_of_eps = (cfg2 >> 10) & 0xF; | |
10aebc77 | 3037 | |
b3f489b2 | 3038 | dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps); |
10aebc77 BD |
3039 | |
3040 | cfg4 = readl(hsotg->regs + 0x50); | |
3041 | hsotg->dedicated_fifos = (cfg4 >> 25) & 1; | |
3042 | ||
3043 | dev_info(hsotg->dev, "%s fifos\n", | |
3044 | hsotg->dedicated_fifos ? "dedicated" : "shared"); | |
5b7d70c6 BD |
3045 | } |
3046 | ||
8b9bc460 LM |
3047 | /** |
3048 | * s3c_hsotg_dump - dump state of the udc | |
3049 | * @param: The device state | |
3050 | */ | |
5b7d70c6 BD |
3051 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg) |
3052 | { | |
83a01804 | 3053 | #ifdef DEBUG |
5b7d70c6 BD |
3054 | struct device *dev = hsotg->dev; |
3055 | void __iomem *regs = hsotg->regs; | |
3056 | u32 val; | |
3057 | int idx; | |
3058 | ||
3059 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3060 | readl(regs + DCFG), readl(regs + DCTL), |
3061 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3062 | |
3063 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3064 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3065 | |
3066 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3067 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3068 | |
3069 | /* show periodic fifo settings */ | |
3070 | ||
3071 | for (idx = 1; idx <= 15; idx++) { | |
47a1685f | 3072 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3073 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3074 | val >> FIFOSIZE_DEPTH_SHIFT, |
3075 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3076 | } |
3077 | ||
3078 | for (idx = 0; idx < 15; idx++) { | |
3079 | dev_info(dev, | |
3080 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3081 | readl(regs + DIEPCTL(idx)), |
3082 | readl(regs + DIEPTSIZ(idx)), | |
3083 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3084 | |
94cb8fd6 | 3085 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3086 | dev_info(dev, |
3087 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3088 | idx, readl(regs + DOEPCTL(idx)), |
3089 | readl(regs + DOEPTSIZ(idx)), | |
3090 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3091 | |
3092 | } | |
3093 | ||
3094 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3095 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3096 | #endif |
5b7d70c6 BD |
3097 | } |
3098 | ||
5b7d70c6 BD |
3099 | /** |
3100 | * state_show - debugfs: show overall driver and device state. | |
3101 | * @seq: The seq file to write to. | |
3102 | * @v: Unused parameter. | |
3103 | * | |
3104 | * This debugfs entry shows the overall state of the hardware and | |
3105 | * some general information about each of the endpoints available | |
3106 | * to the system. | |
3107 | */ | |
3108 | static int state_show(struct seq_file *seq, void *v) | |
3109 | { | |
3110 | struct s3c_hsotg *hsotg = seq->private; | |
3111 | void __iomem *regs = hsotg->regs; | |
3112 | int idx; | |
3113 | ||
3114 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3115 | readl(regs + DCFG), |
3116 | readl(regs + DCTL), | |
3117 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3118 | |
3119 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3120 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3121 | |
3122 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3123 | readl(regs + GINTMSK), |
3124 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3125 | |
3126 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3127 | readl(regs + DAINTMSK), |
3128 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3129 | |
3130 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3131 | readl(regs + GNPTXSTS), |
3132 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3133 | |
a023da33 | 3134 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 BD |
3135 | |
3136 | for (idx = 0; idx < 15; idx++) { | |
3137 | u32 in, out; | |
3138 | ||
94cb8fd6 LM |
3139 | in = readl(regs + DIEPCTL(idx)); |
3140 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3141 | |
3142 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3143 | idx, in, out); | |
3144 | ||
94cb8fd6 LM |
3145 | in = readl(regs + DIEPTSIZ(idx)); |
3146 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3147 | |
3148 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3149 | in, out); | |
3150 | ||
a023da33 | 3151 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3152 | } |
3153 | ||
3154 | return 0; | |
3155 | } | |
3156 | ||
3157 | static int state_open(struct inode *inode, struct file *file) | |
3158 | { | |
3159 | return single_open(file, state_show, inode->i_private); | |
3160 | } | |
3161 | ||
3162 | static const struct file_operations state_fops = { | |
3163 | .owner = THIS_MODULE, | |
3164 | .open = state_open, | |
3165 | .read = seq_read, | |
3166 | .llseek = seq_lseek, | |
3167 | .release = single_release, | |
3168 | }; | |
3169 | ||
3170 | /** | |
3171 | * fifo_show - debugfs: show the fifo information | |
3172 | * @seq: The seq_file to write data to. | |
3173 | * @v: Unused parameter. | |
3174 | * | |
3175 | * Show the FIFO information for the overall fifo and all the | |
3176 | * periodic transmission FIFOs. | |
8b9bc460 | 3177 | */ |
5b7d70c6 BD |
3178 | static int fifo_show(struct seq_file *seq, void *v) |
3179 | { | |
3180 | struct s3c_hsotg *hsotg = seq->private; | |
3181 | void __iomem *regs = hsotg->regs; | |
3182 | u32 val; | |
3183 | int idx; | |
3184 | ||
a023da33 | 3185 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3186 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3187 | |
94cb8fd6 | 3188 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3189 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
47a1685f DN |
3190 | val >> FIFOSIZE_DEPTH_SHIFT, |
3191 | val & FIFOSIZE_DEPTH_MASK); | |
5b7d70c6 | 3192 | |
a023da33 | 3193 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 BD |
3194 | |
3195 | for (idx = 1; idx <= 15; idx++) { | |
47a1685f | 3196 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 BD |
3197 | |
3198 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
47a1685f DN |
3199 | val >> FIFOSIZE_DEPTH_SHIFT, |
3200 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3201 | } |
3202 | ||
3203 | return 0; | |
3204 | } | |
3205 | ||
3206 | static int fifo_open(struct inode *inode, struct file *file) | |
3207 | { | |
3208 | return single_open(file, fifo_show, inode->i_private); | |
3209 | } | |
3210 | ||
3211 | static const struct file_operations fifo_fops = { | |
3212 | .owner = THIS_MODULE, | |
3213 | .open = fifo_open, | |
3214 | .read = seq_read, | |
3215 | .llseek = seq_lseek, | |
3216 | .release = single_release, | |
3217 | }; | |
3218 | ||
3219 | ||
3220 | static const char *decode_direction(int is_in) | |
3221 | { | |
3222 | return is_in ? "in" : "out"; | |
3223 | } | |
3224 | ||
3225 | /** | |
3226 | * ep_show - debugfs: show the state of an endpoint. | |
3227 | * @seq: The seq_file to write data to. | |
3228 | * @v: Unused parameter. | |
3229 | * | |
3230 | * This debugfs entry shows the state of the given endpoint (one is | |
3231 | * registered for each available). | |
8b9bc460 | 3232 | */ |
5b7d70c6 BD |
3233 | static int ep_show(struct seq_file *seq, void *v) |
3234 | { | |
3235 | struct s3c_hsotg_ep *ep = seq->private; | |
3236 | struct s3c_hsotg *hsotg = ep->parent; | |
3237 | struct s3c_hsotg_req *req; | |
3238 | void __iomem *regs = hsotg->regs; | |
3239 | int index = ep->index; | |
3240 | int show_limit = 15; | |
3241 | unsigned long flags; | |
3242 | ||
3243 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3244 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3245 | ||
3246 | /* first show the register state */ | |
3247 | ||
3248 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3249 | readl(regs + DIEPCTL(index)), |
3250 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3251 | |
3252 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3253 | readl(regs + DIEPDMA(index)), |
3254 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3255 | |
3256 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3257 | readl(regs + DIEPINT(index)), |
3258 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3259 | |
3260 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3261 | readl(regs + DIEPTSIZ(index)), |
3262 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3263 | |
a023da33 | 3264 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3265 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3266 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3267 | ||
3268 | seq_printf(seq, "request list (%p,%p):\n", | |
3269 | ep->queue.next, ep->queue.prev); | |
3270 | ||
22258f49 | 3271 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3272 | |
3273 | list_for_each_entry(req, &ep->queue, queue) { | |
3274 | if (--show_limit < 0) { | |
a023da33 | 3275 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3276 | break; |
3277 | } | |
3278 | ||
3279 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3280 | req == ep->req ? '*' : ' ', | |
3281 | req, req->req.length, req->req.buf); | |
3282 | seq_printf(seq, "%d done, res %d\n", | |
3283 | req->req.actual, req->req.status); | |
3284 | } | |
3285 | ||
22258f49 | 3286 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3287 | |
3288 | return 0; | |
3289 | } | |
3290 | ||
3291 | static int ep_open(struct inode *inode, struct file *file) | |
3292 | { | |
3293 | return single_open(file, ep_show, inode->i_private); | |
3294 | } | |
3295 | ||
3296 | static const struct file_operations ep_fops = { | |
3297 | .owner = THIS_MODULE, | |
3298 | .open = ep_open, | |
3299 | .read = seq_read, | |
3300 | .llseek = seq_lseek, | |
3301 | .release = single_release, | |
3302 | }; | |
3303 | ||
3304 | /** | |
3305 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3306 | * @hsotg: The driver state | |
3307 | * | |
3308 | * Create the debugfs files to allow the user to get information | |
3309 | * about the state of the system. The directory name is created | |
3310 | * with the same name as the device itself, in case we end up | |
3311 | * with multiple blocks in future systems. | |
8b9bc460 | 3312 | */ |
41ac7b3a | 3313 | static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
3314 | { |
3315 | struct dentry *root; | |
3316 | unsigned epidx; | |
3317 | ||
3318 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3319 | hsotg->debug_root = root; | |
3320 | if (IS_ERR(root)) { | |
3321 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3322 | return; | |
3323 | } | |
3324 | ||
3325 | /* create general state file */ | |
3326 | ||
3327 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3328 | hsotg, &state_fops); | |
3329 | ||
3330 | if (IS_ERR(hsotg->debug_file)) | |
3331 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3332 | ||
3333 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, | |
3334 | hsotg, &fifo_fops); | |
3335 | ||
3336 | if (IS_ERR(hsotg->debug_fifo)) | |
3337 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3338 | ||
3339 | /* create one file for each endpoint */ | |
3340 | ||
b3f489b2 | 3341 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
5b7d70c6 BD |
3342 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; |
3343 | ||
3344 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3345 | root, ep, &ep_fops); | |
3346 | ||
3347 | if (IS_ERR(ep->debugfs)) | |
3348 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3349 | ep->name); | |
3350 | } | |
3351 | } | |
3352 | ||
3353 | /** | |
3354 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3355 | * @hsotg: The driver state | |
3356 | * | |
3357 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3358 | */ |
fb4e98ab | 3359 | static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
3360 | { |
3361 | unsigned epidx; | |
3362 | ||
b3f489b2 | 3363 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
5b7d70c6 BD |
3364 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; |
3365 | debugfs_remove(ep->debugfs); | |
3366 | } | |
3367 | ||
3368 | debugfs_remove(hsotg->debug_file); | |
3369 | debugfs_remove(hsotg->debug_fifo); | |
3370 | debugfs_remove(hsotg->debug_root); | |
3371 | } | |
3372 | ||
8b9bc460 LM |
3373 | /** |
3374 | * s3c_hsotg_probe - probe function for hsotg driver | |
3375 | * @pdev: The platform information for the driver | |
3376 | */ | |
f026a52d | 3377 | |
41ac7b3a | 3378 | static int s3c_hsotg_probe(struct platform_device *pdev) |
5b7d70c6 | 3379 | { |
e01ee9f5 | 3380 | struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev); |
74084844 MP |
3381 | struct phy *phy; |
3382 | struct usb_phy *uphy; | |
5b7d70c6 | 3383 | struct device *dev = &pdev->dev; |
b3f489b2 | 3384 | struct s3c_hsotg_ep *eps; |
5b7d70c6 BD |
3385 | struct s3c_hsotg *hsotg; |
3386 | struct resource *res; | |
3387 | int epnum; | |
3388 | int ret; | |
fc9a731e | 3389 | int i; |
5b7d70c6 | 3390 | |
338edabc | 3391 | hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL); |
d04477d8 | 3392 | if (!hsotg) |
5b7d70c6 | 3393 | return -ENOMEM; |
5b7d70c6 | 3394 | |
74084844 MP |
3395 | /* |
3396 | * Attempt to find a generic PHY, then look for an old style | |
3397 | * USB PHY, finally fall back to pdata | |
3398 | */ | |
3399 | phy = devm_phy_get(&pdev->dev, "usb2-phy"); | |
f4f5ba5e | 3400 | if (IS_ERR(phy)) { |
74084844 MP |
3401 | uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
3402 | if (IS_ERR(uphy)) { | |
3403 | /* Fallback for pdata */ | |
3404 | plat = dev_get_platdata(&pdev->dev); | |
3405 | if (!plat) { | |
3406 | dev_err(&pdev->dev, | |
3407 | "no platform data or transceiver defined\n"); | |
3408 | return -EPROBE_DEFER; | |
3409 | } | |
b2e587db | 3410 | hsotg->plat = plat; |
74084844 MP |
3411 | } else |
3412 | hsotg->uphy = uphy; | |
3413 | } else | |
b2e587db | 3414 | hsotg->phy = phy; |
b2e587db | 3415 | |
5b7d70c6 | 3416 | hsotg->dev = dev; |
5b7d70c6 | 3417 | |
84749c6d | 3418 | hsotg->clk = devm_clk_get(&pdev->dev, "otg"); |
31ee04de MS |
3419 | if (IS_ERR(hsotg->clk)) { |
3420 | dev_err(dev, "cannot get otg clock\n"); | |
338edabc | 3421 | return PTR_ERR(hsotg->clk); |
31ee04de MS |
3422 | } |
3423 | ||
5b7d70c6 BD |
3424 | platform_set_drvdata(pdev, hsotg); |
3425 | ||
3426 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
5b7d70c6 | 3427 | |
148e1134 TR |
3428 | hsotg->regs = devm_ioremap_resource(&pdev->dev, res); |
3429 | if (IS_ERR(hsotg->regs)) { | |
3430 | ret = PTR_ERR(hsotg->regs); | |
338edabc | 3431 | goto err_clk; |
5b7d70c6 BD |
3432 | } |
3433 | ||
3434 | ret = platform_get_irq(pdev, 0); | |
3435 | if (ret < 0) { | |
3436 | dev_err(dev, "cannot find IRQ\n"); | |
338edabc | 3437 | goto err_clk; |
5b7d70c6 BD |
3438 | } |
3439 | ||
22258f49 LM |
3440 | spin_lock_init(&hsotg->lock); |
3441 | ||
5b7d70c6 BD |
3442 | hsotg->irq = ret; |
3443 | ||
5b7d70c6 BD |
3444 | dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq); |
3445 | ||
d327ab5b | 3446 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3447 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3448 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3449 | |
5b7d70c6 BD |
3450 | /* reset the system */ |
3451 | ||
04b4a0fc | 3452 | clk_prepare_enable(hsotg->clk); |
31ee04de | 3453 | |
fc9a731e LM |
3454 | /* regulators */ |
3455 | ||
3456 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3457 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3458 | ||
cd76213e | 3459 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3460 | hsotg->supplies); |
3461 | if (ret) { | |
3462 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3463 | goto err_clk; |
fc9a731e LM |
3464 | } |
3465 | ||
3466 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3467 | hsotg->supplies); | |
3468 | ||
3469 | if (ret) { | |
3470 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); | |
3471 | goto err_supplies; | |
3472 | } | |
3473 | ||
f7e504c7 | 3474 | /* Set default UTMI width */ |
47a1685f | 3475 | hsotg->phyif = GUSBCFG_PHYIF16; |
f7e504c7 MP |
3476 | |
3477 | /* | |
3478 | * If using the generic PHY framework, check if the PHY bus | |
3479 | * width is 8-bit and set the phyif appropriately. | |
3480 | */ | |
3481 | if (hsotg->phy && (phy_get_bus_width(phy) == 8)) | |
47a1685f | 3482 | hsotg->phyif = GUSBCFG_PHYIF8; |
f7e504c7 | 3483 | |
41188786 LM |
3484 | /* usb phy enable */ |
3485 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3486 | |
5b7d70c6 BD |
3487 | s3c_hsotg_corereset(hsotg); |
3488 | s3c_hsotg_init(hsotg); | |
b3f489b2 LM |
3489 | s3c_hsotg_hw_cfg(hsotg); |
3490 | ||
eb3c56c5 MS |
3491 | ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0, |
3492 | dev_name(dev), hsotg); | |
3493 | if (ret < 0) { | |
3494 | s3c_hsotg_phy_disable(hsotg); | |
3495 | clk_disable_unprepare(hsotg->clk); | |
3496 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3497 | hsotg->supplies); | |
3498 | dev_err(dev, "cannot claim IRQ\n"); | |
3499 | goto err_clk; | |
3500 | } | |
3501 | ||
b3f489b2 LM |
3502 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3503 | ||
3504 | if (hsotg->num_of_eps == 0) { | |
3505 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3506 | ret = -EINVAL; |
b3f489b2 LM |
3507 | goto err_supplies; |
3508 | } | |
3509 | ||
3510 | eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep), | |
3511 | GFP_KERNEL); | |
3512 | if (!eps) { | |
dfdda5a0 | 3513 | ret = -ENOMEM; |
b3f489b2 LM |
3514 | goto err_supplies; |
3515 | } | |
3516 | ||
3517 | hsotg->eps = eps; | |
3518 | ||
3519 | /* setup endpoint information */ | |
3520 | ||
3521 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
3522 | hsotg->gadget.ep0 = &hsotg->eps[0].ep; | |
3523 | ||
3524 | /* allocate EP0 request */ | |
3525 | ||
3526 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep, | |
3527 | GFP_KERNEL); | |
3528 | if (!hsotg->ctrl_req) { | |
3529 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3530 | ret = -ENOMEM; |
b3f489b2 LM |
3531 | goto err_ep_mem; |
3532 | } | |
5b7d70c6 BD |
3533 | |
3534 | /* initialise the endpoints now the core has been initialised */ | |
b3f489b2 | 3535 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) |
5b7d70c6 BD |
3536 | s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum); |
3537 | ||
f65f0f10 LM |
3538 | /* disable power and clock */ |
3539 | ||
3540 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3541 | hsotg->supplies); | |
3542 | if (ret) { | |
3543 | dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret); | |
3544 | goto err_ep_mem; | |
3545 | } | |
3546 | ||
3547 | s3c_hsotg_phy_disable(hsotg); | |
3548 | ||
0f91349b SAS |
3549 | ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget); |
3550 | if (ret) | |
b3f489b2 | 3551 | goto err_ep_mem; |
0f91349b | 3552 | |
5b7d70c6 BD |
3553 | s3c_hsotg_create_debug(hsotg); |
3554 | ||
3555 | s3c_hsotg_dump(hsotg); | |
3556 | ||
5b7d70c6 BD |
3557 | return 0; |
3558 | ||
1d144c67 | 3559 | err_ep_mem: |
b3f489b2 | 3560 | kfree(eps); |
fc9a731e | 3561 | err_supplies: |
41188786 | 3562 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3563 | err_clk: |
1d144c67 | 3564 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3565 | |
5b7d70c6 BD |
3566 | return ret; |
3567 | } | |
3568 | ||
8b9bc460 LM |
3569 | /** |
3570 | * s3c_hsotg_remove - remove function for hsotg driver | |
3571 | * @pdev: The platform information for the driver | |
3572 | */ | |
fb4e98ab | 3573 | static int s3c_hsotg_remove(struct platform_device *pdev) |
5b7d70c6 BD |
3574 | { |
3575 | struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); | |
3576 | ||
0f91349b SAS |
3577 | usb_del_gadget_udc(&hsotg->gadget); |
3578 | ||
5b7d70c6 BD |
3579 | s3c_hsotg_delete_debug(hsotg); |
3580 | ||
f65f0f10 LM |
3581 | if (hsotg->driver) { |
3582 | /* should have been done already by driver model core */ | |
3583 | usb_gadget_unregister_driver(hsotg->driver); | |
3584 | } | |
5b7d70c6 | 3585 | |
04b4a0fc | 3586 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3587 | |
5b7d70c6 BD |
3588 | return 0; |
3589 | } | |
3590 | ||
b83e333a MS |
3591 | static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state) |
3592 | { | |
3593 | struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); | |
3594 | unsigned long flags; | |
3595 | int ret = 0; | |
3596 | ||
3597 | if (hsotg->driver) | |
3598 | dev_info(hsotg->dev, "suspending usb gadget %s\n", | |
3599 | hsotg->driver->driver.name); | |
3600 | ||
3601 | spin_lock_irqsave(&hsotg->lock, flags); | |
3602 | s3c_hsotg_disconnect(hsotg); | |
3603 | s3c_hsotg_phy_disable(hsotg); | |
3604 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3605 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3606 | ||
3607 | if (hsotg->driver) { | |
3608 | int ep; | |
3609 | for (ep = 0; ep < hsotg->num_of_eps; ep++) | |
3610 | s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); | |
3611 | ||
3612 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3613 | hsotg->supplies); | |
3614 | } | |
3615 | ||
3616 | return ret; | |
3617 | } | |
3618 | ||
3619 | static int s3c_hsotg_resume(struct platform_device *pdev) | |
3620 | { | |
3621 | struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); | |
3622 | unsigned long flags; | |
3623 | int ret = 0; | |
3624 | ||
3625 | if (hsotg->driver) { | |
3626 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3627 | hsotg->driver->driver.name); | |
3628 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3629 | hsotg->supplies); | |
3630 | } | |
3631 | ||
3632 | spin_lock_irqsave(&hsotg->lock, flags); | |
3633 | hsotg->last_rst = jiffies; | |
3634 | s3c_hsotg_phy_enable(hsotg); | |
3635 | s3c_hsotg_core_init(hsotg); | |
3636 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3637 | ||
3638 | return ret; | |
3639 | } | |
5b7d70c6 | 3640 | |
c50f056c TF |
3641 | #ifdef CONFIG_OF |
3642 | static const struct of_device_id s3c_hsotg_of_ids[] = { | |
3643 | { .compatible = "samsung,s3c6400-hsotg", }, | |
0d33d825 | 3644 | { .compatible = "snps,dwc2", }, |
c50f056c TF |
3645 | { /* sentinel */ } |
3646 | }; | |
3647 | MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids); | |
3648 | #endif | |
3649 | ||
5b7d70c6 BD |
3650 | static struct platform_driver s3c_hsotg_driver = { |
3651 | .driver = { | |
3652 | .name = "s3c-hsotg", | |
3653 | .owner = THIS_MODULE, | |
c50f056c | 3654 | .of_match_table = of_match_ptr(s3c_hsotg_of_ids), |
5b7d70c6 BD |
3655 | }, |
3656 | .probe = s3c_hsotg_probe, | |
7690417d | 3657 | .remove = s3c_hsotg_remove, |
5b7d70c6 BD |
3658 | .suspend = s3c_hsotg_suspend, |
3659 | .resume = s3c_hsotg_resume, | |
3660 | }; | |
3661 | ||
cc27c96c | 3662 | module_platform_driver(s3c_hsotg_driver); |
5b7d70c6 BD |
3663 | |
3664 | MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device"); | |
3665 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
3666 | MODULE_LICENSE("GPL"); | |
3667 | MODULE_ALIAS("platform:s3c-hsotg"); |