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5fd54ace | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
7359d482 PZ |
2 | /* |
3 | * hcd.c - DesignWare HS OTG Controller host-mode routines | |
4 | * | |
5 | * Copyright (C) 2004-2013 Synopsys, Inc. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. The names of the above-listed copyright holders may not be used | |
17 | * to endorse or promote products derived from this software without | |
18 | * specific prior written permission. | |
19 | * | |
20 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") as published by the Free Software | |
22 | * Foundation; either version 2 of the License, or (at your option) any | |
23 | * later version. | |
24 | * | |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
36 | */ | |
37 | ||
38 | /* | |
39 | * This file contains the core HCD code, and implements the Linux hc_driver | |
40 | * API | |
41 | */ | |
42 | #include <linux/kernel.h> | |
43 | #include <linux/module.h> | |
44 | #include <linux/spinlock.h> | |
45 | #include <linux/interrupt.h> | |
348becdc | 46 | #include <linux/platform_device.h> |
7359d482 PZ |
47 | #include <linux/dma-mapping.h> |
48 | #include <linux/delay.h> | |
49 | #include <linux/io.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/usb.h> | |
52 | ||
53 | #include <linux/usb/hcd.h> | |
54 | #include <linux/usb/ch11.h> | |
55 | ||
56 | #include "core.h" | |
57 | #include "hcd.h" | |
58 | ||
9156a7ef CY |
59 | static void dwc2_port_resume(struct dwc2_hsotg *hsotg); |
60 | ||
b02038fa JY |
61 | /* |
62 | * ========================================================================= | |
63 | * Host Core Layer Functions | |
64 | * ========================================================================= | |
65 | */ | |
66 | ||
67 | /** | |
68 | * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, | |
69 | * used in both device and host modes | |
70 | * | |
71 | * @hsotg: Programming view of the DWC_otg controller | |
72 | */ | |
73 | static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) | |
74 | { | |
75 | u32 intmsk; | |
76 | ||
77 | /* Clear any pending OTG Interrupts */ | |
78 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); | |
79 | ||
80 | /* Clear any pending interrupts */ | |
81 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
82 | ||
83 | /* Enable the interrupts in the GINTMSK */ | |
84 | intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; | |
85 | ||
95832c00 | 86 | if (!hsotg->params.host_dma) |
b02038fa | 87 | intmsk |= GINTSTS_RXFLVL; |
95832c00 | 88 | if (!hsotg->params.external_id_pin_ctl) |
b02038fa JY |
89 | intmsk |= GINTSTS_CONIDSTSCHNG; |
90 | ||
91 | intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | | |
92 | GINTSTS_SESSREQINT; | |
93 | ||
376f0401 SA |
94 | if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) |
95 | intmsk |= GINTSTS_LPMTRANRCVD; | |
96 | ||
b02038fa JY |
97 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); |
98 | } | |
99 | ||
100 | /* | |
101 | * Initializes the FSLSPClkSel field of the HCFG register depending on the | |
102 | * PHY type | |
103 | */ | |
104 | static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) | |
105 | { | |
106 | u32 hcfg, val; | |
107 | ||
108 | if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && | |
109 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && | |
95832c00 | 110 | hsotg->params.ulpi_fs_ls) || |
bea8e86c | 111 | hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { |
b02038fa JY |
112 | /* Full speed PHY */ |
113 | val = HCFG_FSLSPCLKSEL_48_MHZ; | |
114 | } else { | |
115 | /* High speed PHY running at full speed or high speed */ | |
116 | val = HCFG_FSLSPCLKSEL_30_60_MHZ; | |
117 | } | |
118 | ||
119 | dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); | |
120 | hcfg = dwc2_readl(hsotg->regs + HCFG); | |
121 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; | |
122 | hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; | |
123 | dwc2_writel(hcfg, hsotg->regs + HCFG); | |
124 | } | |
125 | ||
126 | static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) | |
127 | { | |
e35b1350 | 128 | u32 usbcfg, ggpio, i2cctl; |
b02038fa JY |
129 | int retval = 0; |
130 | ||
131 | /* | |
132 | * core_init() is now called on every switch so only call the | |
133 | * following for the first time through | |
134 | */ | |
135 | if (select_phy) { | |
136 | dev_dbg(hsotg->dev, "FS PHY selected\n"); | |
137 | ||
138 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
139 | if (!(usbcfg & GUSBCFG_PHYSEL)) { | |
140 | usbcfg |= GUSBCFG_PHYSEL; | |
141 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
142 | ||
143 | /* Reset after a PHY select */ | |
13b1f8e2 | 144 | retval = dwc2_core_reset(hsotg, false); |
b02038fa JY |
145 | |
146 | if (retval) { | |
147 | dev_err(hsotg->dev, | |
148 | "%s: Reset failed, aborting", __func__); | |
149 | return retval; | |
150 | } | |
151 | } | |
e35b1350 BH |
152 | |
153 | if (hsotg->params.activate_stm_fs_transceiver) { | |
154 | ggpio = dwc2_readl(hsotg->regs + GGPIO); | |
155 | if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { | |
156 | dev_dbg(hsotg->dev, "Activating transceiver\n"); | |
157 | /* | |
158 | * STM32F4x9 uses the GGPIO register as general | |
159 | * core configuration register. | |
160 | */ | |
161 | ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; | |
162 | dwc2_writel(ggpio, hsotg->regs + GGPIO); | |
163 | } | |
164 | } | |
b02038fa JY |
165 | } |
166 | ||
167 | /* | |
168 | * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also | |
169 | * do this on HNP Dev/Host mode switches (done in dev_init and | |
170 | * host_init). | |
171 | */ | |
172 | if (dwc2_is_host_mode(hsotg)) | |
173 | dwc2_init_fs_ls_pclk_sel(hsotg); | |
174 | ||
95832c00 | 175 | if (hsotg->params.i2c_enable) { |
b02038fa JY |
176 | dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); |
177 | ||
178 | /* Program GUSBCFG.OtgUtmiFsSel to I2C */ | |
179 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
180 | usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; | |
181 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
182 | ||
183 | /* Program GI2CCTL.I2CEn */ | |
184 | i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); | |
185 | i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; | |
186 | i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; | |
187 | i2cctl &= ~GI2CCTL_I2CEN; | |
188 | dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); | |
189 | i2cctl |= GI2CCTL_I2CEN; | |
190 | dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); | |
191 | } | |
192 | ||
193 | return retval; | |
194 | } | |
195 | ||
196 | static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) | |
197 | { | |
198 | u32 usbcfg, usbcfg_old; | |
199 | int retval = 0; | |
200 | ||
201 | if (!select_phy) | |
202 | return 0; | |
203 | ||
204 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
205 | usbcfg_old = usbcfg; | |
206 | ||
207 | /* | |
208 | * HS PHY parameters. These parameters are preserved during soft reset | |
209 | * so only program the first time. Do a soft reset immediately after | |
210 | * setting phyif. | |
211 | */ | |
bea8e86c | 212 | switch (hsotg->params.phy_type) { |
b02038fa JY |
213 | case DWC2_PHY_TYPE_PARAM_ULPI: |
214 | /* ULPI interface */ | |
215 | dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); | |
216 | usbcfg |= GUSBCFG_ULPI_UTMI_SEL; | |
217 | usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); | |
95832c00 | 218 | if (hsotg->params.phy_ulpi_ddr) |
b02038fa | 219 | usbcfg |= GUSBCFG_DDRSEL; |
b11633c4 DN |
220 | |
221 | /* Set external VBUS indicator as needed. */ | |
222 | if (hsotg->params.oc_disable) | |
223 | usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | | |
224 | GUSBCFG_INDICATORPASSTHROUGH); | |
b02038fa JY |
225 | break; |
226 | case DWC2_PHY_TYPE_PARAM_UTMI: | |
227 | /* UTMI+ interface */ | |
228 | dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); | |
229 | usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); | |
bea8e86c | 230 | if (hsotg->params.phy_utmi_width == 16) |
b02038fa JY |
231 | usbcfg |= GUSBCFG_PHYIF16; |
232 | break; | |
233 | default: | |
234 | dev_err(hsotg->dev, "FS PHY selected at HS!\n"); | |
235 | break; | |
236 | } | |
237 | ||
238 | if (usbcfg != usbcfg_old) { | |
239 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
240 | ||
241 | /* Reset after setting the PHY parameters */ | |
13b1f8e2 | 242 | retval = dwc2_core_reset(hsotg, false); |
b02038fa JY |
243 | if (retval) { |
244 | dev_err(hsotg->dev, | |
245 | "%s: Reset failed, aborting", __func__); | |
246 | return retval; | |
247 | } | |
248 | } | |
249 | ||
250 | return retval; | |
251 | } | |
252 | ||
253 | static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) | |
254 | { | |
255 | u32 usbcfg; | |
256 | int retval = 0; | |
257 | ||
38e9002b VM |
258 | if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
259 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && | |
bea8e86c | 260 | hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { |
38e9002b | 261 | /* If FS/LS mode with FS/LS PHY */ |
b02038fa JY |
262 | retval = dwc2_fs_phy_init(hsotg, select_phy); |
263 | if (retval) | |
264 | return retval; | |
265 | } else { | |
266 | /* High speed PHY */ | |
267 | retval = dwc2_hs_phy_init(hsotg, select_phy); | |
268 | if (retval) | |
269 | return retval; | |
270 | } | |
271 | ||
272 | if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && | |
273 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && | |
95832c00 | 274 | hsotg->params.ulpi_fs_ls) { |
b02038fa JY |
275 | dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); |
276 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
277 | usbcfg |= GUSBCFG_ULPI_FS_LS; | |
278 | usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; | |
279 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
280 | } else { | |
281 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
282 | usbcfg &= ~GUSBCFG_ULPI_FS_LS; | |
283 | usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; | |
284 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
285 | } | |
286 | ||
287 | return retval; | |
288 | } | |
289 | ||
290 | static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) | |
291 | { | |
292 | u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); | |
293 | ||
294 | switch (hsotg->hw_params.arch) { | |
295 | case GHWCFG2_EXT_DMA_ARCH: | |
296 | dev_err(hsotg->dev, "External DMA Mode not supported\n"); | |
297 | return -EINVAL; | |
298 | ||
299 | case GHWCFG2_INT_DMA_ARCH: | |
300 | dev_dbg(hsotg->dev, "Internal DMA Mode\n"); | |
bea8e86c | 301 | if (hsotg->params.ahbcfg != -1) { |
b02038fa | 302 | ahbcfg &= GAHBCFG_CTRL_MASK; |
bea8e86c | 303 | ahbcfg |= hsotg->params.ahbcfg & |
b02038fa JY |
304 | ~GAHBCFG_CTRL_MASK; |
305 | } | |
306 | break; | |
307 | ||
308 | case GHWCFG2_SLAVE_ONLY_ARCH: | |
309 | default: | |
310 | dev_dbg(hsotg->dev, "Slave Only Mode\n"); | |
311 | break; | |
312 | } | |
313 | ||
95832c00 | 314 | if (hsotg->params.host_dma) |
b02038fa | 315 | ahbcfg |= GAHBCFG_DMA_EN; |
9d729a7a RK |
316 | else |
317 | hsotg->params.dma_desc_enable = false; | |
b02038fa JY |
318 | |
319 | dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) | |
325 | { | |
326 | u32 usbcfg; | |
327 | ||
328 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
329 | usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); | |
330 | ||
331 | switch (hsotg->hw_params.op_mode) { | |
332 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: | |
bea8e86c | 333 | if (hsotg->params.otg_cap == |
b02038fa JY |
334 | DWC2_CAP_PARAM_HNP_SRP_CAPABLE) |
335 | usbcfg |= GUSBCFG_HNPCAP; | |
bea8e86c | 336 | if (hsotg->params.otg_cap != |
b02038fa JY |
337 | DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) |
338 | usbcfg |= GUSBCFG_SRPCAP; | |
339 | break; | |
340 | ||
341 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: | |
342 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: | |
343 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: | |
bea8e86c | 344 | if (hsotg->params.otg_cap != |
b02038fa JY |
345 | DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) |
346 | usbcfg |= GUSBCFG_SRPCAP; | |
347 | break; | |
348 | ||
349 | case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: | |
350 | case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: | |
351 | case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: | |
352 | default: | |
353 | break; | |
354 | } | |
355 | ||
356 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
357 | } | |
358 | ||
531ef5eb AD |
359 | static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) |
360 | { | |
a7ef2074 TV |
361 | int ret; |
362 | ||
531ef5eb | 363 | hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); |
a7ef2074 TV |
364 | if (IS_ERR(hsotg->vbus_supply)) { |
365 | ret = PTR_ERR(hsotg->vbus_supply); | |
366 | hsotg->vbus_supply = NULL; | |
367 | return ret == -ENODEV ? 0 : ret; | |
368 | } | |
531ef5eb AD |
369 | |
370 | return regulator_enable(hsotg->vbus_supply); | |
371 | } | |
372 | ||
373 | static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg) | |
374 | { | |
375 | if (hsotg->vbus_supply) | |
376 | return regulator_disable(hsotg->vbus_supply); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
b02038fa JY |
381 | /** |
382 | * dwc2_enable_host_interrupts() - Enables the Host mode interrupts | |
383 | * | |
384 | * @hsotg: Programming view of DWC_otg controller | |
385 | */ | |
386 | static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) | |
387 | { | |
388 | u32 intmsk; | |
389 | ||
390 | dev_dbg(hsotg->dev, "%s()\n", __func__); | |
391 | ||
392 | /* Disable all interrupts */ | |
393 | dwc2_writel(0, hsotg->regs + GINTMSK); | |
394 | dwc2_writel(0, hsotg->regs + HAINTMSK); | |
395 | ||
396 | /* Enable the common interrupts */ | |
397 | dwc2_enable_common_interrupts(hsotg); | |
398 | ||
399 | /* Enable host mode interrupts without disturbing common interrupts */ | |
400 | intmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
401 | intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; | |
402 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
403 | } | |
404 | ||
405 | /** | |
406 | * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts | |
407 | * | |
408 | * @hsotg: Programming view of DWC_otg controller | |
409 | */ | |
410 | static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) | |
411 | { | |
412 | u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
413 | ||
414 | /* Disable host mode interrupts without disturbing common interrupts */ | |
415 | intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | | |
416 | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); | |
417 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
418 | } | |
419 | ||
420 | /* | |
421 | * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size | |
422 | * For system that have a total fifo depth that is smaller than the default | |
423 | * RX + TX fifo size. | |
424 | * | |
425 | * @hsotg: Programming view of DWC_otg controller | |
426 | */ | |
427 | static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) | |
428 | { | |
bea8e86c | 429 | struct dwc2_core_params *params = &hsotg->params; |
b02038fa JY |
430 | struct dwc2_hw_params *hw = &hsotg->hw_params; |
431 | u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; | |
432 | ||
433 | total_fifo_size = hw->total_fifo_size; | |
434 | rxfsiz = params->host_rx_fifo_size; | |
435 | nptxfsiz = params->host_nperio_tx_fifo_size; | |
436 | ptxfsiz = params->host_perio_tx_fifo_size; | |
437 | ||
438 | /* | |
439 | * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth | |
440 | * allocation with support for high bandwidth endpoints. Synopsys | |
441 | * defines MPS(Max Packet size) for a periodic EP=1024, and for | |
442 | * non-periodic as 512. | |
443 | */ | |
444 | if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { | |
445 | /* | |
446 | * For Buffer DMA mode/Scatter Gather DMA mode | |
447 | * 2 * ((Largest Packet size / 4) + 1 + 1) + n | |
448 | * with n = number of host channel. | |
449 | * 2 * ((1024/4) + 2) = 516 | |
450 | */ | |
451 | rxfsiz = 516 + hw->host_channels; | |
452 | ||
453 | /* | |
454 | * min non-periodic tx fifo depth | |
455 | * 2 * (largest non-periodic USB packet used / 4) | |
456 | * 2 * (512/4) = 256 | |
457 | */ | |
458 | nptxfsiz = 256; | |
459 | ||
460 | /* | |
461 | * min periodic tx fifo depth | |
462 | * (largest packet size*MC)/4 | |
463 | * (1024 * 3)/4 = 768 | |
464 | */ | |
465 | ptxfsiz = 768; | |
466 | ||
467 | params->host_rx_fifo_size = rxfsiz; | |
468 | params->host_nperio_tx_fifo_size = nptxfsiz; | |
469 | params->host_perio_tx_fifo_size = ptxfsiz; | |
470 | } | |
471 | ||
472 | /* | |
473 | * If the summation of RX, NPTX and PTX fifo sizes is still | |
474 | * bigger than the total_fifo_size, then we have a problem. | |
475 | * | |
476 | * We won't be able to allocate as many endpoints. Right now, | |
477 | * we're just printing an error message, but ideally this FIFO | |
478 | * allocation algorithm would be improved in the future. | |
479 | * | |
480 | * FIXME improve this FIFO allocation algorithm. | |
481 | */ | |
482 | if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) | |
483 | dev_err(hsotg->dev, "invalid fifo sizes\n"); | |
484 | } | |
485 | ||
486 | static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) | |
487 | { | |
bea8e86c | 488 | struct dwc2_core_params *params = &hsotg->params; |
b02038fa JY |
489 | u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; |
490 | ||
491 | if (!params->enable_dynamic_fifo) | |
492 | return; | |
493 | ||
494 | dwc2_calculate_dynamic_fifo(hsotg); | |
495 | ||
496 | /* Rx FIFO */ | |
497 | grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); | |
498 | dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); | |
499 | grxfsiz &= ~GRXFSIZ_DEPTH_MASK; | |
500 | grxfsiz |= params->host_rx_fifo_size << | |
501 | GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; | |
502 | dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); | |
503 | dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", | |
504 | dwc2_readl(hsotg->regs + GRXFSIZ)); | |
505 | ||
506 | /* Non-periodic Tx FIFO */ | |
507 | dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", | |
508 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
509 | nptxfsiz = params->host_nperio_tx_fifo_size << | |
510 | FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; | |
511 | nptxfsiz |= params->host_rx_fifo_size << | |
512 | FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; | |
513 | dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); | |
514 | dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", | |
515 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
516 | ||
517 | /* Periodic Tx FIFO */ | |
518 | dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", | |
519 | dwc2_readl(hsotg->regs + HPTXFSIZ)); | |
520 | hptxfsiz = params->host_perio_tx_fifo_size << | |
521 | FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; | |
522 | hptxfsiz |= (params->host_rx_fifo_size + | |
523 | params->host_nperio_tx_fifo_size) << | |
524 | FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; | |
525 | dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); | |
526 | dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", | |
527 | dwc2_readl(hsotg->regs + HPTXFSIZ)); | |
528 | ||
95832c00 | 529 | if (hsotg->params.en_multiple_tx_fifo && |
e1f411d1 | 530 | hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { |
b02038fa | 531 | /* |
e1f411d1 | 532 | * This feature was implemented in 2.91a version |
b02038fa JY |
533 | * Global DFIFOCFG calculation for Host mode - |
534 | * include RxFIFO, NPTXFIFO and HPTXFIFO | |
535 | */ | |
536 | dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); | |
537 | dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; | |
538 | dfifocfg |= (params->host_rx_fifo_size + | |
539 | params->host_nperio_tx_fifo_size + | |
540 | params->host_perio_tx_fifo_size) << | |
541 | GDFIFOCFG_EPINFOBASE_SHIFT & | |
542 | GDFIFOCFG_EPINFOBASE_MASK; | |
543 | dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); | |
544 | } | |
545 | } | |
546 | ||
547 | /** | |
548 | * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for | |
549 | * the HFIR register according to PHY type and speed | |
550 | * | |
551 | * @hsotg: Programming view of DWC_otg controller | |
552 | * | |
553 | * NOTE: The caller can modify the value of the HFIR register only after the | |
554 | * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) | |
555 | * has been set | |
556 | */ | |
557 | u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) | |
558 | { | |
559 | u32 usbcfg; | |
560 | u32 hprt0; | |
561 | int clock = 60; /* default value */ | |
562 | ||
563 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
564 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); | |
565 | ||
566 | if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && | |
567 | !(usbcfg & GUSBCFG_PHYIF16)) | |
568 | clock = 60; | |
569 | if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == | |
570 | GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) | |
571 | clock = 48; | |
572 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && | |
573 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) | |
574 | clock = 30; | |
575 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && | |
576 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) | |
577 | clock = 60; | |
578 | if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && | |
579 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) | |
580 | clock = 48; | |
581 | if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && | |
582 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) | |
583 | clock = 48; | |
584 | if ((usbcfg & GUSBCFG_PHYSEL) && | |
585 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) | |
586 | clock = 48; | |
587 | ||
588 | if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) | |
589 | /* High speed case */ | |
590 | return 125 * clock - 1; | |
591 | ||
592 | /* FS/LS case */ | |
593 | return 1000 * clock - 1; | |
594 | } | |
595 | ||
596 | /** | |
597 | * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination | |
598 | * buffer | |
599 | * | |
6fb914d7 | 600 | * @hsotg: Programming view of DWC_otg controller |
b02038fa JY |
601 | * @dest: Destination buffer for the packet |
602 | * @bytes: Number of bytes to copy to the destination | |
603 | */ | |
604 | void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) | |
605 | { | |
606 | u32 __iomem *fifo = hsotg->regs + HCFIFO(0); | |
607 | u32 *data_buf = (u32 *)dest; | |
608 | int word_count = (bytes + 3) / 4; | |
609 | int i; | |
610 | ||
611 | /* | |
612 | * Todo: Account for the case where dest is not dword aligned. This | |
613 | * requires reading data from the FIFO into a u32 temp buffer, then | |
614 | * moving it into the data buffer. | |
615 | */ | |
616 | ||
617 | dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); | |
618 | ||
619 | for (i = 0; i < word_count; i++, data_buf++) | |
620 | *data_buf = dwc2_readl(fifo); | |
621 | } | |
622 | ||
623 | /** | |
624 | * dwc2_dump_channel_info() - Prints the state of a host channel | |
625 | * | |
626 | * @hsotg: Programming view of DWC_otg controller | |
627 | * @chan: Pointer to the channel to dump | |
628 | * | |
629 | * Must be called with interrupt disabled and spinlock held | |
630 | * | |
631 | * NOTE: This function will be removed once the peripheral controller code | |
632 | * is integrated and the driver is stable | |
633 | */ | |
634 | static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, | |
635 | struct dwc2_host_chan *chan) | |
636 | { | |
637 | #ifdef VERBOSE_DEBUG | |
bea8e86c | 638 | int num_channels = hsotg->params.host_channels; |
b02038fa JY |
639 | struct dwc2_qh *qh; |
640 | u32 hcchar; | |
641 | u32 hcsplt; | |
642 | u32 hctsiz; | |
643 | u32 hc_dma; | |
644 | int i; | |
645 | ||
646 | if (!chan) | |
647 | return; | |
648 | ||
649 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
650 | hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); | |
651 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); | |
652 | hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); | |
653 | ||
654 | dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); | |
655 | dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", | |
656 | hcchar, hcsplt); | |
657 | dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", | |
658 | hctsiz, hc_dma); | |
659 | dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", | |
660 | chan->dev_addr, chan->ep_num, chan->ep_is_in); | |
661 | dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); | |
662 | dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); | |
663 | dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); | |
664 | dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); | |
665 | dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); | |
666 | dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); | |
667 | dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", | |
668 | (unsigned long)chan->xfer_dma); | |
669 | dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); | |
670 | dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); | |
671 | dev_dbg(hsotg->dev, " NP inactive sched:\n"); | |
672 | list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, | |
673 | qh_list_entry) | |
674 | dev_dbg(hsotg->dev, " %p\n", qh); | |
38d2b5fb DA |
675 | dev_dbg(hsotg->dev, " NP waiting sched:\n"); |
676 | list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, | |
677 | qh_list_entry) | |
678 | dev_dbg(hsotg->dev, " %p\n", qh); | |
b02038fa JY |
679 | dev_dbg(hsotg->dev, " NP active sched:\n"); |
680 | list_for_each_entry(qh, &hsotg->non_periodic_sched_active, | |
681 | qh_list_entry) | |
682 | dev_dbg(hsotg->dev, " %p\n", qh); | |
683 | dev_dbg(hsotg->dev, " Channels:\n"); | |
684 | for (i = 0; i < num_channels; i++) { | |
685 | struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; | |
686 | ||
687 | dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); | |
688 | } | |
689 | #endif /* VERBOSE_DEBUG */ | |
690 | } | |
691 | ||
4411beba RK |
692 | static int _dwc2_hcd_start(struct usb_hcd *hcd); |
693 | ||
694 | static void dwc2_host_start(struct dwc2_hsotg *hsotg) | |
695 | { | |
696 | struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); | |
697 | ||
698 | hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); | |
699 | _dwc2_hcd_start(hcd); | |
700 | } | |
701 | ||
702 | static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) | |
703 | { | |
704 | struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); | |
705 | ||
706 | hcd->self.is_b_host = 0; | |
707 | } | |
708 | ||
709 | static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, | |
710 | int *hub_addr, int *hub_port) | |
711 | { | |
712 | struct urb *urb = context; | |
713 | ||
714 | if (urb->dev->tt) | |
715 | *hub_addr = urb->dev->tt->hub->devnum; | |
716 | else | |
717 | *hub_addr = 0; | |
718 | *hub_port = urb->dev->ttport; | |
719 | } | |
720 | ||
b02038fa JY |
721 | /* |
722 | * ========================================================================= | |
723 | * Low Level Host Channel Access Functions | |
724 | * ========================================================================= | |
725 | */ | |
726 | ||
727 | static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, | |
728 | struct dwc2_host_chan *chan) | |
729 | { | |
730 | u32 hcintmsk = HCINTMSK_CHHLTD; | |
731 | ||
732 | switch (chan->ep_type) { | |
733 | case USB_ENDPOINT_XFER_CONTROL: | |
734 | case USB_ENDPOINT_XFER_BULK: | |
735 | dev_vdbg(hsotg->dev, "control/bulk\n"); | |
736 | hcintmsk |= HCINTMSK_XFERCOMPL; | |
737 | hcintmsk |= HCINTMSK_STALL; | |
738 | hcintmsk |= HCINTMSK_XACTERR; | |
739 | hcintmsk |= HCINTMSK_DATATGLERR; | |
740 | if (chan->ep_is_in) { | |
741 | hcintmsk |= HCINTMSK_BBLERR; | |
742 | } else { | |
743 | hcintmsk |= HCINTMSK_NAK; | |
744 | hcintmsk |= HCINTMSK_NYET; | |
745 | if (chan->do_ping) | |
746 | hcintmsk |= HCINTMSK_ACK; | |
747 | } | |
748 | ||
749 | if (chan->do_split) { | |
750 | hcintmsk |= HCINTMSK_NAK; | |
751 | if (chan->complete_split) | |
752 | hcintmsk |= HCINTMSK_NYET; | |
753 | else | |
754 | hcintmsk |= HCINTMSK_ACK; | |
755 | } | |
756 | ||
757 | if (chan->error_state) | |
758 | hcintmsk |= HCINTMSK_ACK; | |
759 | break; | |
760 | ||
761 | case USB_ENDPOINT_XFER_INT: | |
762 | if (dbg_perio()) | |
763 | dev_vdbg(hsotg->dev, "intr\n"); | |
764 | hcintmsk |= HCINTMSK_XFERCOMPL; | |
765 | hcintmsk |= HCINTMSK_NAK; | |
766 | hcintmsk |= HCINTMSK_STALL; | |
767 | hcintmsk |= HCINTMSK_XACTERR; | |
768 | hcintmsk |= HCINTMSK_DATATGLERR; | |
769 | hcintmsk |= HCINTMSK_FRMOVRUN; | |
770 | ||
771 | if (chan->ep_is_in) | |
772 | hcintmsk |= HCINTMSK_BBLERR; | |
773 | if (chan->error_state) | |
774 | hcintmsk |= HCINTMSK_ACK; | |
775 | if (chan->do_split) { | |
776 | if (chan->complete_split) | |
777 | hcintmsk |= HCINTMSK_NYET; | |
778 | else | |
779 | hcintmsk |= HCINTMSK_ACK; | |
780 | } | |
781 | break; | |
782 | ||
783 | case USB_ENDPOINT_XFER_ISOC: | |
784 | if (dbg_perio()) | |
785 | dev_vdbg(hsotg->dev, "isoc\n"); | |
786 | hcintmsk |= HCINTMSK_XFERCOMPL; | |
787 | hcintmsk |= HCINTMSK_FRMOVRUN; | |
788 | hcintmsk |= HCINTMSK_ACK; | |
789 | ||
790 | if (chan->ep_is_in) { | |
791 | hcintmsk |= HCINTMSK_XACTERR; | |
792 | hcintmsk |= HCINTMSK_BBLERR; | |
793 | } | |
794 | break; | |
795 | default: | |
796 | dev_err(hsotg->dev, "## Unknown EP type ##\n"); | |
797 | break; | |
798 | } | |
799 | ||
800 | dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); | |
801 | if (dbg_hc(chan)) | |
802 | dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); | |
803 | } | |
804 | ||
805 | static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, | |
806 | struct dwc2_host_chan *chan) | |
807 | { | |
808 | u32 hcintmsk = HCINTMSK_CHHLTD; | |
809 | ||
810 | /* | |
811 | * For Descriptor DMA mode core halts the channel on AHB error. | |
812 | * Interrupt is not required. | |
813 | */ | |
95832c00 | 814 | if (!hsotg->params.dma_desc_enable) { |
b02038fa JY |
815 | if (dbg_hc(chan)) |
816 | dev_vdbg(hsotg->dev, "desc DMA disabled\n"); | |
817 | hcintmsk |= HCINTMSK_AHBERR; | |
818 | } else { | |
819 | if (dbg_hc(chan)) | |
820 | dev_vdbg(hsotg->dev, "desc DMA enabled\n"); | |
821 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
822 | hcintmsk |= HCINTMSK_XFERCOMPL; | |
823 | } | |
824 | ||
825 | if (chan->error_state && !chan->do_split && | |
826 | chan->ep_type != USB_ENDPOINT_XFER_ISOC) { | |
827 | if (dbg_hc(chan)) | |
828 | dev_vdbg(hsotg->dev, "setting ACK\n"); | |
829 | hcintmsk |= HCINTMSK_ACK; | |
830 | if (chan->ep_is_in) { | |
831 | hcintmsk |= HCINTMSK_DATATGLERR; | |
832 | if (chan->ep_type != USB_ENDPOINT_XFER_INT) | |
833 | hcintmsk |= HCINTMSK_NAK; | |
834 | } | |
835 | } | |
836 | ||
837 | dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); | |
838 | if (dbg_hc(chan)) | |
839 | dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); | |
840 | } | |
841 | ||
842 | static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, | |
843 | struct dwc2_host_chan *chan) | |
844 | { | |
845 | u32 intmsk; | |
846 | ||
95832c00 | 847 | if (hsotg->params.host_dma) { |
b02038fa JY |
848 | if (dbg_hc(chan)) |
849 | dev_vdbg(hsotg->dev, "DMA enabled\n"); | |
850 | dwc2_hc_enable_dma_ints(hsotg, chan); | |
851 | } else { | |
852 | if (dbg_hc(chan)) | |
853 | dev_vdbg(hsotg->dev, "DMA disabled\n"); | |
854 | dwc2_hc_enable_slave_ints(hsotg, chan); | |
855 | } | |
856 | ||
857 | /* Enable the top level host channel interrupt */ | |
858 | intmsk = dwc2_readl(hsotg->regs + HAINTMSK); | |
859 | intmsk |= 1 << chan->hc_num; | |
860 | dwc2_writel(intmsk, hsotg->regs + HAINTMSK); | |
861 | if (dbg_hc(chan)) | |
862 | dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); | |
863 | ||
864 | /* Make sure host channel interrupts are enabled */ | |
865 | intmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
866 | intmsk |= GINTSTS_HCHINT; | |
867 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
868 | if (dbg_hc(chan)) | |
869 | dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); | |
870 | } | |
871 | ||
872 | /** | |
873 | * dwc2_hc_init() - Prepares a host channel for transferring packets to/from | |
874 | * a specific endpoint | |
875 | * | |
876 | * @hsotg: Programming view of DWC_otg controller | |
877 | * @chan: Information needed to initialize the host channel | |
878 | * | |
879 | * The HCCHARn register is set up with the characteristics specified in chan. | |
880 | * Host channel interrupts that may need to be serviced while this transfer is | |
881 | * in progress are enabled. | |
882 | */ | |
883 | static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) | |
884 | { | |
885 | u8 hc_num = chan->hc_num; | |
886 | u32 hcintmsk; | |
887 | u32 hcchar; | |
888 | u32 hcsplt = 0; | |
889 | ||
890 | if (dbg_hc(chan)) | |
891 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
892 | ||
893 | /* Clear old interrupt conditions for this host channel */ | |
894 | hcintmsk = 0xffffffff; | |
895 | hcintmsk &= ~HCINTMSK_RESERVED14_31; | |
896 | dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); | |
897 | ||
898 | /* Enable channel interrupts required for this transfer */ | |
899 | dwc2_hc_enable_ints(hsotg, chan); | |
900 | ||
901 | /* | |
902 | * Program the HCCHARn register with the endpoint characteristics for | |
903 | * the current transfer | |
904 | */ | |
905 | hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; | |
906 | hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; | |
907 | if (chan->ep_is_in) | |
908 | hcchar |= HCCHAR_EPDIR; | |
909 | if (chan->speed == USB_SPEED_LOW) | |
910 | hcchar |= HCCHAR_LSPDDEV; | |
911 | hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; | |
912 | hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; | |
913 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); | |
914 | if (dbg_hc(chan)) { | |
915 | dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", | |
916 | hc_num, hcchar); | |
917 | ||
918 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", | |
919 | __func__, hc_num); | |
920 | dev_vdbg(hsotg->dev, " Dev Addr: %d\n", | |
921 | chan->dev_addr); | |
922 | dev_vdbg(hsotg->dev, " Ep Num: %d\n", | |
923 | chan->ep_num); | |
924 | dev_vdbg(hsotg->dev, " Is In: %d\n", | |
925 | chan->ep_is_in); | |
926 | dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", | |
927 | chan->speed == USB_SPEED_LOW); | |
928 | dev_vdbg(hsotg->dev, " Ep Type: %d\n", | |
929 | chan->ep_type); | |
930 | dev_vdbg(hsotg->dev, " Max Pkt: %d\n", | |
931 | chan->max_packet); | |
932 | } | |
933 | ||
934 | /* Program the HCSPLT register for SPLITs */ | |
935 | if (chan->do_split) { | |
936 | if (dbg_hc(chan)) | |
937 | dev_vdbg(hsotg->dev, | |
938 | "Programming HC %d with split --> %s\n", | |
939 | hc_num, | |
940 | chan->complete_split ? "CSPLIT" : "SSPLIT"); | |
941 | if (chan->complete_split) | |
942 | hcsplt |= HCSPLT_COMPSPLT; | |
943 | hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & | |
944 | HCSPLT_XACTPOS_MASK; | |
945 | hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & | |
946 | HCSPLT_HUBADDR_MASK; | |
947 | hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & | |
948 | HCSPLT_PRTADDR_MASK; | |
949 | if (dbg_hc(chan)) { | |
950 | dev_vdbg(hsotg->dev, " comp split %d\n", | |
951 | chan->complete_split); | |
952 | dev_vdbg(hsotg->dev, " xact pos %d\n", | |
953 | chan->xact_pos); | |
954 | dev_vdbg(hsotg->dev, " hub addr %d\n", | |
955 | chan->hub_addr); | |
956 | dev_vdbg(hsotg->dev, " hub port %d\n", | |
957 | chan->hub_port); | |
958 | dev_vdbg(hsotg->dev, " is_in %d\n", | |
959 | chan->ep_is_in); | |
960 | dev_vdbg(hsotg->dev, " Max Pkt %d\n", | |
961 | chan->max_packet); | |
962 | dev_vdbg(hsotg->dev, " xferlen %d\n", | |
963 | chan->xfer_len); | |
964 | } | |
965 | } | |
966 | ||
967 | dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); | |
968 | } | |
969 | ||
970 | /** | |
971 | * dwc2_hc_halt() - Attempts to halt a host channel | |
972 | * | |
973 | * @hsotg: Controller register interface | |
974 | * @chan: Host channel to halt | |
975 | * @halt_status: Reason for halting the channel | |
976 | * | |
977 | * This function should only be called in Slave mode or to abort a transfer in | |
978 | * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the | |
979 | * controller halts the channel when the transfer is complete or a condition | |
980 | * occurs that requires application intervention. | |
981 | * | |
982 | * In slave mode, checks for a free request queue entry, then sets the Channel | |
983 | * Enable and Channel Disable bits of the Host Channel Characteristics | |
984 | * register of the specified channel to intiate the halt. If there is no free | |
985 | * request queue entry, sets only the Channel Disable bit of the HCCHARn | |
986 | * register to flush requests for this channel. In the latter case, sets a | |
987 | * flag to indicate that the host channel needs to be halted when a request | |
988 | * queue slot is open. | |
989 | * | |
990 | * In DMA mode, always sets the Channel Enable and Channel Disable bits of the | |
991 | * HCCHARn register. The controller ensures there is space in the request | |
992 | * queue before submitting the halt request. | |
993 | * | |
994 | * Some time may elapse before the core flushes any posted requests for this | |
995 | * host channel and halts. The Channel Halted interrupt handler completes the | |
996 | * deactivation of the host channel. | |
997 | */ | |
998 | void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, | |
999 | enum dwc2_halt_status halt_status) | |
1000 | { | |
1001 | u32 nptxsts, hptxsts, hcchar; | |
1002 | ||
1003 | if (dbg_hc(chan)) | |
1004 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
a82c7abd MH |
1005 | |
1006 | /* | |
1007 | * In buffer DMA or external DMA mode channel can't be halted | |
1008 | * for non-split periodic channels. At the end of the next | |
1009 | * uframe/frame (in the worst case), the core generates a channel | |
1010 | * halted and disables the channel automatically. | |
1011 | */ | |
1012 | if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || | |
1013 | hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { | |
1014 | if (!chan->do_split && | |
1015 | (chan->ep_type == USB_ENDPOINT_XFER_ISOC || | |
1016 | chan->ep_type == USB_ENDPOINT_XFER_INT)) { | |
1017 | dev_err(hsotg->dev, "%s() Channel can't be halted\n", | |
1018 | __func__); | |
1019 | return; | |
1020 | } | |
1021 | } | |
1022 | ||
b02038fa JY |
1023 | if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) |
1024 | dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); | |
1025 | ||
1026 | if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || | |
1027 | halt_status == DWC2_HC_XFER_AHB_ERR) { | |
1028 | /* | |
1029 | * Disable all channel interrupts except Ch Halted. The QTD | |
1030 | * and QH state associated with this transfer has been cleared | |
1031 | * (in the case of URB_DEQUEUE), so the channel needs to be | |
1032 | * shut down carefully to prevent crashes. | |
1033 | */ | |
1034 | u32 hcintmsk = HCINTMSK_CHHLTD; | |
1035 | ||
1036 | dev_vdbg(hsotg->dev, "dequeue/error\n"); | |
1037 | dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); | |
1038 | ||
1039 | /* | |
1040 | * Make sure no other interrupts besides halt are currently | |
1041 | * pending. Handling another interrupt could cause a crash due | |
1042 | * to the QTD and QH state. | |
1043 | */ | |
1044 | dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); | |
1045 | ||
1046 | /* | |
1047 | * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR | |
1048 | * even if the channel was already halted for some other | |
1049 | * reason | |
1050 | */ | |
1051 | chan->halt_status = halt_status; | |
1052 | ||
1053 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
1054 | if (!(hcchar & HCCHAR_CHENA)) { | |
1055 | /* | |
1056 | * The channel is either already halted or it hasn't | |
1057 | * started yet. In DMA mode, the transfer may halt if | |
1058 | * it finishes normally or a condition occurs that | |
1059 | * requires driver intervention. Don't want to halt | |
1060 | * the channel again. In either Slave or DMA mode, | |
1061 | * it's possible that the transfer has been assigned | |
1062 | * to a channel, but not started yet when an URB is | |
1063 | * dequeued. Don't want to halt a channel that hasn't | |
1064 | * started yet. | |
1065 | */ | |
1066 | return; | |
1067 | } | |
1068 | } | |
1069 | if (chan->halt_pending) { | |
1070 | /* | |
1071 | * A halt has already been issued for this channel. This might | |
1072 | * happen when a transfer is aborted by a higher level in | |
1073 | * the stack. | |
1074 | */ | |
1075 | dev_vdbg(hsotg->dev, | |
1076 | "*** %s: Channel %d, chan->halt_pending already set ***\n", | |
1077 | __func__, chan->hc_num); | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
1082 | ||
1083 | /* No need to set the bit in DDMA for disabling the channel */ | |
1084 | /* TODO check it everywhere channel is disabled */ | |
95832c00 | 1085 | if (!hsotg->params.dma_desc_enable) { |
b02038fa JY |
1086 | if (dbg_hc(chan)) |
1087 | dev_vdbg(hsotg->dev, "desc DMA disabled\n"); | |
1088 | hcchar |= HCCHAR_CHENA; | |
1089 | } else { | |
1090 | if (dbg_hc(chan)) | |
1091 | dev_dbg(hsotg->dev, "desc DMA enabled\n"); | |
1092 | } | |
1093 | hcchar |= HCCHAR_CHDIS; | |
1094 | ||
95832c00 | 1095 | if (!hsotg->params.host_dma) { |
b02038fa JY |
1096 | if (dbg_hc(chan)) |
1097 | dev_vdbg(hsotg->dev, "DMA not enabled\n"); | |
1098 | hcchar |= HCCHAR_CHENA; | |
1099 | ||
1100 | /* Check for space in the request queue to issue the halt */ | |
1101 | if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || | |
1102 | chan->ep_type == USB_ENDPOINT_XFER_BULK) { | |
1103 | dev_vdbg(hsotg->dev, "control/bulk\n"); | |
1104 | nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); | |
1105 | if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { | |
1106 | dev_vdbg(hsotg->dev, "Disabling channel\n"); | |
1107 | hcchar &= ~HCCHAR_CHENA; | |
1108 | } | |
1109 | } else { | |
1110 | if (dbg_perio()) | |
1111 | dev_vdbg(hsotg->dev, "isoc/intr\n"); | |
1112 | hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); | |
1113 | if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || | |
1114 | hsotg->queuing_high_bandwidth) { | |
1115 | if (dbg_perio()) | |
1116 | dev_vdbg(hsotg->dev, "Disabling channel\n"); | |
1117 | hcchar &= ~HCCHAR_CHENA; | |
1118 | } | |
1119 | } | |
1120 | } else { | |
1121 | if (dbg_hc(chan)) | |
1122 | dev_vdbg(hsotg->dev, "DMA enabled\n"); | |
1123 | } | |
1124 | ||
1125 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); | |
1126 | chan->halt_status = halt_status; | |
1127 | ||
1128 | if (hcchar & HCCHAR_CHENA) { | |
1129 | if (dbg_hc(chan)) | |
1130 | dev_vdbg(hsotg->dev, "Channel enabled\n"); | |
1131 | chan->halt_pending = 1; | |
1132 | chan->halt_on_queue = 0; | |
1133 | } else { | |
1134 | if (dbg_hc(chan)) | |
1135 | dev_vdbg(hsotg->dev, "Channel disabled\n"); | |
1136 | chan->halt_on_queue = 1; | |
1137 | } | |
1138 | ||
1139 | if (dbg_hc(chan)) { | |
1140 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, | |
1141 | chan->hc_num); | |
1142 | dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", | |
1143 | hcchar); | |
1144 | dev_vdbg(hsotg->dev, " halt_pending: %d\n", | |
1145 | chan->halt_pending); | |
1146 | dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", | |
1147 | chan->halt_on_queue); | |
1148 | dev_vdbg(hsotg->dev, " halt_status: %d\n", | |
1149 | chan->halt_status); | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | /** | |
1154 | * dwc2_hc_cleanup() - Clears the transfer state for a host channel | |
1155 | * | |
1156 | * @hsotg: Programming view of DWC_otg controller | |
1157 | * @chan: Identifies the host channel to clean up | |
1158 | * | |
1159 | * This function is normally called after a transfer is done and the host | |
1160 | * channel is being released | |
1161 | */ | |
1162 | void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) | |
1163 | { | |
1164 | u32 hcintmsk; | |
1165 | ||
1166 | chan->xfer_started = 0; | |
1167 | ||
1168 | list_del_init(&chan->split_order_list_entry); | |
1169 | ||
1170 | /* | |
1171 | * Clear channel interrupt enables and any unhandled channel interrupt | |
1172 | * conditions | |
1173 | */ | |
1174 | dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); | |
1175 | hcintmsk = 0xffffffff; | |
1176 | hcintmsk &= ~HCINTMSK_RESERVED14_31; | |
1177 | dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); | |
1178 | } | |
1179 | ||
1180 | /** | |
1181 | * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in | |
1182 | * which frame a periodic transfer should occur | |
1183 | * | |
1184 | * @hsotg: Programming view of DWC_otg controller | |
1185 | * @chan: Identifies the host channel to set up and its properties | |
1186 | * @hcchar: Current value of the HCCHAR register for the specified host channel | |
1187 | * | |
1188 | * This function has no effect on non-periodic transfers | |
1189 | */ | |
1190 | static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, | |
1191 | struct dwc2_host_chan *chan, u32 *hcchar) | |
1192 | { | |
1193 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1194 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
1195 | int host_speed; | |
1196 | int xfer_ns; | |
1197 | int xfer_us; | |
1198 | int bytes_in_fifo; | |
1199 | u16 fifo_space; | |
1200 | u16 frame_number; | |
1201 | u16 wire_frame; | |
1202 | ||
1203 | /* | |
1204 | * Try to figure out if we're an even or odd frame. If we set | |
1205 | * even and the current frame number is even the the transfer | |
1206 | * will happen immediately. Similar if both are odd. If one is | |
1207 | * even and the other is odd then the transfer will happen when | |
1208 | * the frame number ticks. | |
1209 | * | |
1210 | * There's a bit of a balancing act to get this right. | |
1211 | * Sometimes we may want to send data in the current frame (AK | |
1212 | * right away). We might want to do this if the frame number | |
1213 | * _just_ ticked, but we might also want to do this in order | |
1214 | * to continue a split transaction that happened late in a | |
1215 | * microframe (so we didn't know to queue the next transfer | |
1216 | * until the frame number had ticked). The problem is that we | |
1217 | * need a lot of knowledge to know if there's actually still | |
1218 | * time to send things or if it would be better to wait until | |
1219 | * the next frame. | |
1220 | * | |
1221 | * We can look at how much time is left in the current frame | |
1222 | * and make a guess about whether we'll have time to transfer. | |
1223 | * We'll do that. | |
1224 | */ | |
1225 | ||
1226 | /* Get speed host is running at */ | |
1227 | host_speed = (chan->speed != USB_SPEED_HIGH && | |
1228 | !chan->do_split) ? chan->speed : USB_SPEED_HIGH; | |
1229 | ||
1230 | /* See how many bytes are in the periodic FIFO right now */ | |
1231 | fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & | |
1232 | TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; | |
1233 | bytes_in_fifo = sizeof(u32) * | |
bea8e86c | 1234 | (hsotg->params.host_perio_tx_fifo_size - |
b02038fa JY |
1235 | fifo_space); |
1236 | ||
1237 | /* | |
1238 | * Roughly estimate bus time for everything in the periodic | |
1239 | * queue + our new transfer. This is "rough" because we're | |
1240 | * using a function that makes takes into account IN/OUT | |
1241 | * and INT/ISO and we're just slamming in one value for all | |
1242 | * transfers. This should be an over-estimate and that should | |
1243 | * be OK, but we can probably tighten it. | |
1244 | */ | |
1245 | xfer_ns = usb_calc_bus_time(host_speed, false, false, | |
1246 | chan->xfer_len + bytes_in_fifo); | |
1247 | xfer_us = NS_TO_US(xfer_ns); | |
1248 | ||
1249 | /* See what frame number we'll be at by the time we finish */ | |
1250 | frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); | |
1251 | ||
1252 | /* This is when we were scheduled to be on the wire */ | |
1253 | wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); | |
1254 | ||
1255 | /* | |
1256 | * If we'd finish _after_ the frame we're scheduled in then | |
1257 | * it's hopeless. Just schedule right away and hope for the | |
1258 | * best. Note that it _might_ be wise to call back into the | |
1259 | * scheduler to pick a better frame, but this is better than | |
1260 | * nothing. | |
1261 | */ | |
1262 | if (dwc2_frame_num_gt(frame_number, wire_frame)) { | |
1263 | dwc2_sch_vdbg(hsotg, | |
1264 | "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", | |
1265 | chan->qh, wire_frame, frame_number, | |
1266 | dwc2_frame_num_dec(frame_number, | |
1267 | wire_frame)); | |
1268 | wire_frame = frame_number; | |
1269 | ||
1270 | /* | |
1271 | * We picked a different frame number; communicate this | |
1272 | * back to the scheduler so it doesn't try to schedule | |
1273 | * another in the same frame. | |
1274 | * | |
1275 | * Remember that next_active_frame is 1 before the wire | |
1276 | * frame. | |
1277 | */ | |
1278 | chan->qh->next_active_frame = | |
1279 | dwc2_frame_num_dec(frame_number, 1); | |
1280 | } | |
1281 | ||
1282 | if (wire_frame & 1) | |
1283 | *hcchar |= HCCHAR_ODDFRM; | |
1284 | else | |
1285 | *hcchar &= ~HCCHAR_ODDFRM; | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) | |
1290 | { | |
1291 | /* Set up the initial PID for the transfer */ | |
1292 | if (chan->speed == USB_SPEED_HIGH) { | |
1293 | if (chan->ep_is_in) { | |
1294 | if (chan->multi_count == 1) | |
1295 | chan->data_pid_start = DWC2_HC_PID_DATA0; | |
1296 | else if (chan->multi_count == 2) | |
1297 | chan->data_pid_start = DWC2_HC_PID_DATA1; | |
1298 | else | |
1299 | chan->data_pid_start = DWC2_HC_PID_DATA2; | |
1300 | } else { | |
1301 | if (chan->multi_count == 1) | |
1302 | chan->data_pid_start = DWC2_HC_PID_DATA0; | |
1303 | else | |
1304 | chan->data_pid_start = DWC2_HC_PID_MDATA; | |
1305 | } | |
1306 | } else { | |
1307 | chan->data_pid_start = DWC2_HC_PID_DATA0; | |
1308 | } | |
1309 | } | |
1310 | ||
7359d482 | 1311 | /** |
b02038fa JY |
1312 | * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with |
1313 | * the Host Channel | |
7359d482 PZ |
1314 | * |
1315 | * @hsotg: Programming view of DWC_otg controller | |
b02038fa | 1316 | * @chan: Information needed to initialize the host channel |
7359d482 | 1317 | * |
b02038fa JY |
1318 | * This function should only be called in Slave mode. For a channel associated |
1319 | * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel | |
1320 | * associated with a periodic EP, the periodic Tx FIFO is written. | |
7359d482 | 1321 | * |
b02038fa JY |
1322 | * Upon return the xfer_buf and xfer_count fields in chan are incremented by |
1323 | * the number of bytes written to the Tx FIFO. | |
7359d482 | 1324 | */ |
b02038fa JY |
1325 | static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, |
1326 | struct dwc2_host_chan *chan) | |
1327 | { | |
1328 | u32 i; | |
1329 | u32 remaining_count; | |
1330 | u32 byte_count; | |
1331 | u32 dword_count; | |
1332 | u32 __iomem *data_fifo; | |
1333 | u32 *data_buf = (u32 *)chan->xfer_buf; | |
1334 | ||
1335 | if (dbg_hc(chan)) | |
1336 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
1337 | ||
1338 | data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); | |
1339 | ||
1340 | remaining_count = chan->xfer_len - chan->xfer_count; | |
1341 | if (remaining_count > chan->max_packet) | |
1342 | byte_count = chan->max_packet; | |
1343 | else | |
1344 | byte_count = remaining_count; | |
1345 | ||
1346 | dword_count = (byte_count + 3) / 4; | |
1347 | ||
1348 | if (((unsigned long)data_buf & 0x3) == 0) { | |
1349 | /* xfer_buf is DWORD aligned */ | |
1350 | for (i = 0; i < dword_count; i++, data_buf++) | |
1351 | dwc2_writel(*data_buf, data_fifo); | |
1352 | } else { | |
1353 | /* xfer_buf is not DWORD aligned */ | |
1354 | for (i = 0; i < dword_count; i++, data_buf++) { | |
1355 | u32 data = data_buf[0] | data_buf[1] << 8 | | |
1356 | data_buf[2] << 16 | data_buf[3] << 24; | |
1357 | dwc2_writel(data, data_fifo); | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | chan->xfer_count += byte_count; | |
1362 | chan->xfer_buf += byte_count; | |
1363 | } | |
1364 | ||
1365 | /** | |
1366 | * dwc2_hc_do_ping() - Starts a PING transfer | |
1367 | * | |
1368 | * @hsotg: Programming view of DWC_otg controller | |
1369 | * @chan: Information needed to initialize the host channel | |
1370 | * | |
1371 | * This function should only be called in Slave mode. The Do Ping bit is set in | |
1372 | * the HCTSIZ register, then the channel is enabled. | |
1373 | */ | |
1374 | static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, | |
1375 | struct dwc2_host_chan *chan) | |
7359d482 | 1376 | { |
7359d482 | 1377 | u32 hcchar; |
7359d482 | 1378 | u32 hctsiz; |
7359d482 | 1379 | |
b02038fa JY |
1380 | if (dbg_hc(chan)) |
1381 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, | |
1382 | chan->hc_num); | |
1383 | ||
1384 | hctsiz = TSIZ_DOPNG; | |
1385 | hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; | |
1386 | dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); | |
7359d482 | 1387 | |
95c8bc36 | 1388 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); |
b02038fa JY |
1389 | hcchar |= HCCHAR_CHENA; |
1390 | hcchar &= ~HCCHAR_CHDIS; | |
1391 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); | |
1392 | } | |
7359d482 | 1393 | |
b02038fa JY |
1394 | /** |
1395 | * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host | |
1396 | * channel and starts the transfer | |
1397 | * | |
1398 | * @hsotg: Programming view of DWC_otg controller | |
1399 | * @chan: Information needed to initialize the host channel. The xfer_len value | |
1400 | * may be reduced to accommodate the max widths of the XferSize and | |
1401 | * PktCnt fields in the HCTSIZn register. The multi_count value may be | |
1402 | * changed to reflect the final xfer_len value. | |
1403 | * | |
1404 | * This function may be called in either Slave mode or DMA mode. In Slave mode, | |
1405 | * the caller must ensure that there is sufficient space in the request queue | |
1406 | * and Tx Data FIFO. | |
1407 | * | |
1408 | * For an OUT transfer in Slave mode, it loads a data packet into the | |
1409 | * appropriate FIFO. If necessary, additional data packets are loaded in the | |
1410 | * Host ISR. | |
1411 | * | |
1412 | * For an IN transfer in Slave mode, a data packet is requested. The data | |
1413 | * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, | |
1414 | * additional data packets are requested in the Host ISR. | |
1415 | * | |
1416 | * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ | |
1417 | * register along with a packet count of 1 and the channel is enabled. This | |
1418 | * causes a single PING transaction to occur. Other fields in HCTSIZ are | |
1419 | * simply set to 0 since no data transfer occurs in this case. | |
1420 | * | |
1421 | * For a PING transfer in DMA mode, the HCTSIZ register is initialized with | |
1422 | * all the information required to perform the subsequent data transfer. In | |
1423 | * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the | |
1424 | * controller performs the entire PING protocol, then starts the data | |
1425 | * transfer. | |
1426 | */ | |
1427 | static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, | |
1428 | struct dwc2_host_chan *chan) | |
1429 | { | |
bea8e86c JY |
1430 | u32 max_hc_xfer_size = hsotg->params.max_transfer_size; |
1431 | u16 max_hc_pkt_count = hsotg->params.max_packet_count; | |
b02038fa JY |
1432 | u32 hcchar; |
1433 | u32 hctsiz = 0; | |
1434 | u16 num_packets; | |
1435 | u32 ec_mc; | |
1436 | ||
1437 | if (dbg_hc(chan)) | |
1438 | dev_vdbg(hsotg->dev, "%s()\n", __func__); | |
1439 | ||
1440 | if (chan->do_ping) { | |
95832c00 | 1441 | if (!hsotg->params.host_dma) { |
b02038fa JY |
1442 | if (dbg_hc(chan)) |
1443 | dev_vdbg(hsotg->dev, "ping, no DMA\n"); | |
1444 | dwc2_hc_do_ping(hsotg, chan); | |
1445 | chan->xfer_started = 1; | |
1446 | return; | |
1447 | } | |
7359d482 | 1448 | |
b02038fa JY |
1449 | if (dbg_hc(chan)) |
1450 | dev_vdbg(hsotg->dev, "ping, DMA\n"); | |
1451 | ||
1452 | hctsiz |= TSIZ_DOPNG; | |
7359d482 | 1453 | } |
b02038fa JY |
1454 | |
1455 | if (chan->do_split) { | |
1456 | if (dbg_hc(chan)) | |
1457 | dev_vdbg(hsotg->dev, "split\n"); | |
1458 | num_packets = 1; | |
1459 | ||
1460 | if (chan->complete_split && !chan->ep_is_in) | |
1461 | /* | |
1462 | * For CSPLIT OUT Transfer, set the size to 0 so the | |
1463 | * core doesn't expect any data written to the FIFO | |
1464 | */ | |
1465 | chan->xfer_len = 0; | |
1466 | else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) | |
1467 | chan->xfer_len = chan->max_packet; | |
1468 | else if (!chan->ep_is_in && chan->xfer_len > 188) | |
1469 | chan->xfer_len = 188; | |
1470 | ||
1471 | hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & | |
1472 | TSIZ_XFERSIZE_MASK; | |
1473 | ||
1474 | /* For split set ec_mc for immediate retries */ | |
1475 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1476 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
1477 | ec_mc = 3; | |
1478 | else | |
1479 | ec_mc = 1; | |
1480 | } else { | |
1481 | if (dbg_hc(chan)) | |
1482 | dev_vdbg(hsotg->dev, "no split\n"); | |
1483 | /* | |
1484 | * Ensure that the transfer length and packet count will fit | |
1485 | * in the widths allocated for them in the HCTSIZn register | |
1486 | */ | |
1487 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1488 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
1489 | /* | |
1490 | * Make sure the transfer size is no larger than one | |
1491 | * (micro)frame's worth of data. (A check was done | |
1492 | * when the periodic transfer was accepted to ensure | |
1493 | * that a (micro)frame's worth of data can be | |
1494 | * programmed into a channel.) | |
1495 | */ | |
1496 | u32 max_periodic_len = | |
1497 | chan->multi_count * chan->max_packet; | |
1498 | ||
1499 | if (chan->xfer_len > max_periodic_len) | |
1500 | chan->xfer_len = max_periodic_len; | |
1501 | } else if (chan->xfer_len > max_hc_xfer_size) { | |
1502 | /* | |
1503 | * Make sure that xfer_len is a multiple of max packet | |
1504 | * size | |
1505 | */ | |
1506 | chan->xfer_len = | |
1507 | max_hc_xfer_size - chan->max_packet + 1; | |
1508 | } | |
1509 | ||
1510 | if (chan->xfer_len > 0) { | |
1511 | num_packets = (chan->xfer_len + chan->max_packet - 1) / | |
1512 | chan->max_packet; | |
1513 | if (num_packets > max_hc_pkt_count) { | |
1514 | num_packets = max_hc_pkt_count; | |
1515 | chan->xfer_len = num_packets * chan->max_packet; | |
1516 | } | |
1517 | } else { | |
1518 | /* Need 1 packet for transfer length of 0 */ | |
1519 | num_packets = 1; | |
1520 | } | |
1521 | ||
1522 | if (chan->ep_is_in) | |
1523 | /* | |
1524 | * Always program an integral # of max packets for IN | |
1525 | * transfers | |
1526 | */ | |
1527 | chan->xfer_len = num_packets * chan->max_packet; | |
1528 | ||
1529 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1530 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
1531 | /* | |
1532 | * Make sure that the multi_count field matches the | |
1533 | * actual transfer length | |
1534 | */ | |
1535 | chan->multi_count = num_packets; | |
1536 | ||
1537 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
1538 | dwc2_set_pid_isoc(chan); | |
1539 | ||
1540 | hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & | |
1541 | TSIZ_XFERSIZE_MASK; | |
1542 | ||
1543 | /* The ec_mc gets the multi_count for non-split */ | |
1544 | ec_mc = chan->multi_count; | |
1545 | } | |
1546 | ||
1547 | chan->start_pkt_count = num_packets; | |
1548 | hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; | |
1549 | hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & | |
1550 | TSIZ_SC_MC_PID_MASK; | |
1551 | dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); | |
1552 | if (dbg_hc(chan)) { | |
1553 | dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", | |
1554 | hctsiz, chan->hc_num); | |
1555 | ||
1556 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, | |
1557 | chan->hc_num); | |
1558 | dev_vdbg(hsotg->dev, " Xfer Size: %d\n", | |
1559 | (hctsiz & TSIZ_XFERSIZE_MASK) >> | |
1560 | TSIZ_XFERSIZE_SHIFT); | |
1561 | dev_vdbg(hsotg->dev, " Num Pkts: %d\n", | |
1562 | (hctsiz & TSIZ_PKTCNT_MASK) >> | |
1563 | TSIZ_PKTCNT_SHIFT); | |
1564 | dev_vdbg(hsotg->dev, " Start PID: %d\n", | |
1565 | (hctsiz & TSIZ_SC_MC_PID_MASK) >> | |
1566 | TSIZ_SC_MC_PID_SHIFT); | |
1567 | } | |
1568 | ||
95832c00 | 1569 | if (hsotg->params.host_dma) { |
b02038fa JY |
1570 | dwc2_writel((u32)chan->xfer_dma, |
1571 | hsotg->regs + HCDMA(chan->hc_num)); | |
1572 | if (dbg_hc(chan)) | |
1573 | dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", | |
1574 | (unsigned long)chan->xfer_dma, chan->hc_num); | |
1575 | } | |
1576 | ||
1577 | /* Start the split */ | |
1578 | if (chan->do_split) { | |
1579 | u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); | |
1580 | ||
1581 | hcsplt |= HCSPLT_SPLTENA; | |
1582 | dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); | |
1583 | } | |
1584 | ||
1585 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
1586 | hcchar &= ~HCCHAR_MULTICNT_MASK; | |
1587 | hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; | |
1588 | dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); | |
1589 | ||
1590 | if (hcchar & HCCHAR_CHDIS) | |
1591 | dev_warn(hsotg->dev, | |
1592 | "%s: chdis set, channel %d, hcchar 0x%08x\n", | |
1593 | __func__, chan->hc_num, hcchar); | |
1594 | ||
1595 | /* Set host channel enable after all other setup is complete */ | |
1596 | hcchar |= HCCHAR_CHENA; | |
1597 | hcchar &= ~HCCHAR_CHDIS; | |
1598 | ||
1599 | if (dbg_hc(chan)) | |
1600 | dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", | |
1601 | (hcchar & HCCHAR_MULTICNT_MASK) >> | |
1602 | HCCHAR_MULTICNT_SHIFT); | |
1603 | ||
1604 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); | |
1605 | if (dbg_hc(chan)) | |
1606 | dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, | |
1607 | chan->hc_num); | |
1608 | ||
1609 | chan->xfer_started = 1; | |
1610 | chan->requests++; | |
1611 | ||
95832c00 | 1612 | if (!hsotg->params.host_dma && |
b02038fa JY |
1613 | !chan->ep_is_in && chan->xfer_len > 0) |
1614 | /* Load OUT packet into the appropriate Tx FIFO */ | |
1615 | dwc2_hc_write_packet(hsotg, chan); | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a | |
1620 | * host channel and starts the transfer in Descriptor DMA mode | |
1621 | * | |
1622 | * @hsotg: Programming view of DWC_otg controller | |
1623 | * @chan: Information needed to initialize the host channel | |
1624 | * | |
1625 | * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. | |
1626 | * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field | |
1627 | * with micro-frame bitmap. | |
1628 | * | |
1629 | * Initializes HCDMA register with descriptor list address and CTD value then | |
1630 | * starts the transfer via enabling the channel. | |
1631 | */ | |
1632 | void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, | |
1633 | struct dwc2_host_chan *chan) | |
1634 | { | |
1635 | u32 hcchar; | |
1636 | u32 hctsiz = 0; | |
1637 | ||
1638 | if (chan->do_ping) | |
1639 | hctsiz |= TSIZ_DOPNG; | |
1640 | ||
1641 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
1642 | dwc2_set_pid_isoc(chan); | |
1643 | ||
1644 | /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ | |
1645 | hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & | |
1646 | TSIZ_SC_MC_PID_MASK; | |
1647 | ||
1648 | /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ | |
1649 | hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; | |
1650 | ||
1651 | /* Non-zero only for high-speed interrupt endpoints */ | |
1652 | hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; | |
1653 | ||
1654 | if (dbg_hc(chan)) { | |
1655 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, | |
1656 | chan->hc_num); | |
1657 | dev_vdbg(hsotg->dev, " Start PID: %d\n", | |
1658 | chan->data_pid_start); | |
1659 | dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); | |
1660 | } | |
1661 | ||
1662 | dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); | |
1663 | ||
1664 | dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, | |
1665 | chan->desc_list_sz, DMA_TO_DEVICE); | |
1666 | ||
1667 | dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); | |
1668 | ||
1669 | if (dbg_hc(chan)) | |
1670 | dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", | |
1671 | &chan->desc_list_addr, chan->hc_num); | |
1672 | ||
1673 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
1674 | hcchar &= ~HCCHAR_MULTICNT_MASK; | |
1675 | hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & | |
1676 | HCCHAR_MULTICNT_MASK; | |
1677 | ||
1678 | if (hcchar & HCCHAR_CHDIS) | |
1679 | dev_warn(hsotg->dev, | |
1680 | "%s: chdis set, channel %d, hcchar 0x%08x\n", | |
1681 | __func__, chan->hc_num, hcchar); | |
1682 | ||
1683 | /* Set host channel enable after all other setup is complete */ | |
1684 | hcchar |= HCCHAR_CHENA; | |
1685 | hcchar &= ~HCCHAR_CHDIS; | |
1686 | ||
1687 | if (dbg_hc(chan)) | |
1688 | dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", | |
1689 | (hcchar & HCCHAR_MULTICNT_MASK) >> | |
1690 | HCCHAR_MULTICNT_SHIFT); | |
1691 | ||
1692 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); | |
1693 | if (dbg_hc(chan)) | |
1694 | dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, | |
1695 | chan->hc_num); | |
1696 | ||
1697 | chan->xfer_started = 1; | |
1698 | chan->requests++; | |
1699 | } | |
1700 | ||
1701 | /** | |
1702 | * dwc2_hc_continue_transfer() - Continues a data transfer that was started by | |
1703 | * a previous call to dwc2_hc_start_transfer() | |
1704 | * | |
1705 | * @hsotg: Programming view of DWC_otg controller | |
1706 | * @chan: Information needed to initialize the host channel | |
1707 | * | |
1708 | * The caller must ensure there is sufficient space in the request queue and Tx | |
1709 | * Data FIFO. This function should only be called in Slave mode. In DMA mode, | |
1710 | * the controller acts autonomously to complete transfers programmed to a host | |
1711 | * channel. | |
1712 | * | |
1713 | * For an OUT transfer, a new data packet is loaded into the appropriate FIFO | |
1714 | * if there is any data remaining to be queued. For an IN transfer, another | |
1715 | * data packet is always requested. For the SETUP phase of a control transfer, | |
1716 | * this function does nothing. | |
1717 | * | |
1718 | * Return: 1 if a new request is queued, 0 if no more requests are required | |
1719 | * for this transfer | |
1720 | */ | |
1721 | static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, | |
1722 | struct dwc2_host_chan *chan) | |
1723 | { | |
1724 | if (dbg_hc(chan)) | |
1725 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, | |
1726 | chan->hc_num); | |
1727 | ||
1728 | if (chan->do_split) | |
1729 | /* SPLITs always queue just once per channel */ | |
1730 | return 0; | |
1731 | ||
1732 | if (chan->data_pid_start == DWC2_HC_PID_SETUP) | |
1733 | /* SETUPs are queued only once since they can't be NAK'd */ | |
1734 | return 0; | |
1735 | ||
1736 | if (chan->ep_is_in) { | |
1737 | /* | |
1738 | * Always queue another request for other IN transfers. If | |
1739 | * back-to-back INs are issued and NAKs are received for both, | |
1740 | * the driver may still be processing the first NAK when the | |
1741 | * second NAK is received. When the interrupt handler clears | |
1742 | * the NAK interrupt for the first NAK, the second NAK will | |
1743 | * not be seen. So we can't depend on the NAK interrupt | |
1744 | * handler to requeue a NAK'd request. Instead, IN requests | |
1745 | * are issued each time this function is called. When the | |
1746 | * transfer completes, the extra requests for the channel will | |
1747 | * be flushed. | |
1748 | */ | |
1749 | u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); | |
1750 | ||
1751 | dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); | |
1752 | hcchar |= HCCHAR_CHENA; | |
1753 | hcchar &= ~HCCHAR_CHDIS; | |
1754 | if (dbg_hc(chan)) | |
1755 | dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", | |
1756 | hcchar); | |
1757 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); | |
1758 | chan->requests++; | |
1759 | return 1; | |
1760 | } | |
1761 | ||
1762 | /* OUT transfers */ | |
1763 | ||
1764 | if (chan->xfer_count < chan->xfer_len) { | |
1765 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
1766 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
1767 | u32 hcchar = dwc2_readl(hsotg->regs + | |
1768 | HCCHAR(chan->hc_num)); | |
1769 | ||
1770 | dwc2_hc_set_even_odd_frame(hsotg, chan, | |
1771 | &hcchar); | |
1772 | } | |
1773 | ||
1774 | /* Load OUT packet into the appropriate Tx FIFO */ | |
1775 | dwc2_hc_write_packet(hsotg, chan); | |
1776 | chan->requests++; | |
1777 | return 1; | |
1778 | } | |
1779 | ||
1780 | return 0; | |
7359d482 PZ |
1781 | } |
1782 | ||
b02038fa JY |
1783 | /* |
1784 | * ========================================================================= | |
1785 | * HCD | |
1786 | * ========================================================================= | |
1787 | */ | |
1788 | ||
7359d482 PZ |
1789 | /* |
1790 | * Processes all the URBs in a single list of QHs. Completes them with | |
1791 | * -ETIMEDOUT and frees the QTD. | |
1792 | * | |
1793 | * Must be called with interrupt disabled and spinlock held | |
1794 | */ | |
1795 | static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, | |
1796 | struct list_head *qh_list) | |
1797 | { | |
1798 | struct dwc2_qh *qh, *qh_tmp; | |
1799 | struct dwc2_qtd *qtd, *qtd_tmp; | |
1800 | ||
1801 | list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { | |
1802 | list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, | |
1803 | qtd_list_entry) { | |
2e84da6e | 1804 | dwc2_host_complete(hsotg, qtd, -ECONNRESET); |
0d012b98 | 1805 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); |
7359d482 PZ |
1806 | } |
1807 | } | |
1808 | } | |
1809 | ||
1810 | static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, | |
1811 | struct list_head *qh_list) | |
1812 | { | |
1813 | struct dwc2_qtd *qtd, *qtd_tmp; | |
1814 | struct dwc2_qh *qh, *qh_tmp; | |
1815 | unsigned long flags; | |
1816 | ||
1817 | if (!qh_list->next) | |
1818 | /* The list hasn't been initialized yet */ | |
1819 | return; | |
1820 | ||
1821 | spin_lock_irqsave(&hsotg->lock, flags); | |
1822 | ||
1823 | /* Ensure there are no QTDs or URBs left */ | |
1824 | dwc2_kill_urbs_in_qh_list(hsotg, qh_list); | |
1825 | ||
1826 | list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { | |
1827 | dwc2_hcd_qh_unlink(hsotg, qh); | |
1828 | ||
1829 | /* Free each QTD in the QH's QTD list */ | |
1830 | list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, | |
1831 | qtd_list_entry) | |
1832 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); | |
1833 | ||
16e80218 DA |
1834 | if (qh->channel && qh->channel->qh == qh) |
1835 | qh->channel->qh = NULL; | |
1836 | ||
7359d482 PZ |
1837 | spin_unlock_irqrestore(&hsotg->lock, flags); |
1838 | dwc2_hcd_qh_free(hsotg, qh); | |
1839 | spin_lock_irqsave(&hsotg->lock, flags); | |
1840 | } | |
1841 | ||
1842 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
1843 | } | |
1844 | ||
1845 | /* | |
1846 | * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic | |
1847 | * and periodic schedules. The QTD associated with each URB is removed from | |
1848 | * the schedule and freed. This function may be called when a disconnect is | |
1849 | * detected or when the HCD is being stopped. | |
1850 | * | |
1851 | * Must be called with interrupt disabled and spinlock held | |
1852 | */ | |
1853 | static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) | |
1854 | { | |
1855 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); | |
38d2b5fb | 1856 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); |
7359d482 PZ |
1857 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); |
1858 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); | |
1859 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); | |
1860 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); | |
1861 | dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); | |
1862 | } | |
1863 | ||
1864 | /** | |
1865 | * dwc2_hcd_start() - Starts the HCD when switching to Host mode | |
1866 | * | |
1867 | * @hsotg: Pointer to struct dwc2_hsotg | |
1868 | */ | |
1869 | void dwc2_hcd_start(struct dwc2_hsotg *hsotg) | |
1870 | { | |
1871 | u32 hprt0; | |
1872 | ||
1873 | if (hsotg->op_state == OTG_STATE_B_HOST) { | |
1874 | /* | |
1875 | * Reset the port. During a HNP mode switch the reset | |
1876 | * needs to occur within 1ms and have a duration of at | |
1877 | * least 50ms. | |
1878 | */ | |
1879 | hprt0 = dwc2_read_hprt0(hsotg); | |
1880 | hprt0 |= HPRT0_RST; | |
95c8bc36 | 1881 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
1882 | } |
1883 | ||
1884 | queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, | |
1885 | msecs_to_jiffies(50)); | |
1886 | } | |
1887 | ||
1888 | /* Must be called with interrupt disabled and spinlock held */ | |
1889 | static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) | |
1890 | { | |
bea8e86c | 1891 | int num_channels = hsotg->params.host_channels; |
7359d482 PZ |
1892 | struct dwc2_host_chan *channel; |
1893 | u32 hcchar; | |
1894 | int i; | |
1895 | ||
95832c00 | 1896 | if (!hsotg->params.host_dma) { |
7359d482 PZ |
1897 | /* Flush out any channel requests in slave mode */ |
1898 | for (i = 0; i < num_channels; i++) { | |
1899 | channel = hsotg->hc_ptr_array[i]; | |
1900 | if (!list_empty(&channel->hc_list_entry)) | |
1901 | continue; | |
95c8bc36 | 1902 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); |
7359d482 PZ |
1903 | if (hcchar & HCCHAR_CHENA) { |
1904 | hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); | |
1905 | hcchar |= HCCHAR_CHDIS; | |
95c8bc36 | 1906 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); |
7359d482 PZ |
1907 | } |
1908 | } | |
1909 | } | |
1910 | ||
1911 | for (i = 0; i < num_channels; i++) { | |
1912 | channel = hsotg->hc_ptr_array[i]; | |
1913 | if (!list_empty(&channel->hc_list_entry)) | |
1914 | continue; | |
95c8bc36 | 1915 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); |
7359d482 PZ |
1916 | if (hcchar & HCCHAR_CHENA) { |
1917 | /* Halt the channel */ | |
1918 | hcchar |= HCCHAR_CHDIS; | |
95c8bc36 | 1919 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); |
7359d482 PZ |
1920 | } |
1921 | ||
1922 | dwc2_hc_cleanup(hsotg, channel); | |
1923 | list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); | |
1924 | /* | |
1925 | * Added for Descriptor DMA to prevent channel double cleanup in | |
1926 | * release_channel_ddma(), which is called from ep_disable when | |
1927 | * device disconnects | |
1928 | */ | |
1929 | channel->qh = NULL; | |
1930 | } | |
7252f1bf | 1931 | /* All channels have been freed, mark them available */ |
95832c00 | 1932 | if (hsotg->params.uframe_sched) { |
7252f1bf | 1933 | hsotg->available_host_channels = |
bea8e86c | 1934 | hsotg->params.host_channels; |
7252f1bf VP |
1935 | } else { |
1936 | hsotg->non_periodic_channels = 0; | |
1937 | hsotg->periodic_channels = 0; | |
1938 | } | |
7359d482 PZ |
1939 | } |
1940 | ||
6a659531 DA |
1941 | /** |
1942 | * dwc2_hcd_connect() - Handles connect of the HCD | |
1943 | * | |
1944 | * @hsotg: Pointer to struct dwc2_hsotg | |
1945 | * | |
1946 | * Must be called with interrupt disabled and spinlock held | |
1947 | */ | |
1948 | void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) | |
1949 | { | |
1950 | if (hsotg->lx_state != DWC2_L0) | |
1951 | usb_hcd_resume_root_hub(hsotg->priv); | |
1952 | ||
1953 | hsotg->flags.b.port_connect_status_change = 1; | |
1954 | hsotg->flags.b.port_connect_status = 1; | |
1955 | } | |
1956 | ||
7359d482 PZ |
1957 | /** |
1958 | * dwc2_hcd_disconnect() - Handles disconnect of the HCD | |
1959 | * | |
1960 | * @hsotg: Pointer to struct dwc2_hsotg | |
6a659531 | 1961 | * @force: If true, we won't try to reconnect even if we see device connected. |
7359d482 PZ |
1962 | * |
1963 | * Must be called with interrupt disabled and spinlock held | |
1964 | */ | |
6a659531 | 1965 | void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) |
7359d482 PZ |
1966 | { |
1967 | u32 intr; | |
6a659531 | 1968 | u32 hprt0; |
7359d482 PZ |
1969 | |
1970 | /* Set status flags for the hub driver */ | |
1971 | hsotg->flags.b.port_connect_status_change = 1; | |
1972 | hsotg->flags.b.port_connect_status = 0; | |
1973 | ||
1974 | /* | |
1975 | * Shutdown any transfers in process by clearing the Tx FIFO Empty | |
1976 | * interrupt mask and status bits and disabling subsequent host | |
1977 | * channel interrupts. | |
1978 | */ | |
95c8bc36 | 1979 | intr = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 | 1980 | intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); |
95c8bc36 | 1981 | dwc2_writel(intr, hsotg->regs + GINTMSK); |
7359d482 | 1982 | intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; |
95c8bc36 | 1983 | dwc2_writel(intr, hsotg->regs + GINTSTS); |
7359d482 PZ |
1984 | |
1985 | /* | |
1986 | * Turn off the vbus power only if the core has transitioned to device | |
1987 | * mode. If still in host mode, need to keep power on to detect a | |
1988 | * reconnection. | |
1989 | */ | |
1990 | if (dwc2_is_device_mode(hsotg)) { | |
1991 | if (hsotg->op_state != OTG_STATE_A_SUSPEND) { | |
1992 | dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); | |
95c8bc36 | 1993 | dwc2_writel(0, hsotg->regs + HPRT0); |
7359d482 PZ |
1994 | } |
1995 | ||
1996 | dwc2_disable_host_interrupts(hsotg); | |
1997 | } | |
1998 | ||
1999 | /* Respond with an error status to all URBs in the schedule */ | |
2000 | dwc2_kill_all_urbs(hsotg); | |
2001 | ||
2002 | if (dwc2_is_host_mode(hsotg)) | |
2003 | /* Clean up any host channels that were in use */ | |
2004 | dwc2_hcd_cleanup_channels(hsotg); | |
2005 | ||
2006 | dwc2_host_disconnect(hsotg); | |
6a659531 DA |
2007 | |
2008 | /* | |
2009 | * Add an extra check here to see if we're actually connected but | |
2010 | * we don't have a detection interrupt pending. This can happen if: | |
2011 | * 1. hardware sees connect | |
2012 | * 2. hardware sees disconnect | |
2013 | * 3. hardware sees connect | |
2014 | * 4. dwc2_port_intr() - clears connect interrupt | |
2015 | * 5. dwc2_handle_common_intr() - calls here | |
2016 | * | |
2017 | * Without the extra check here we will end calling disconnect | |
2018 | * and won't get any future interrupts to handle the connect. | |
2019 | */ | |
2020 | if (!force) { | |
2021 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); | |
2022 | if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) | |
2023 | dwc2_hcd_connect(hsotg); | |
2024 | } | |
7359d482 PZ |
2025 | } |
2026 | ||
2027 | /** | |
2028 | * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup | |
2029 | * | |
2030 | * @hsotg: Pointer to struct dwc2_hsotg | |
2031 | */ | |
2032 | static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) | |
2033 | { | |
1fb7f12d | 2034 | if (hsotg->bus_suspended) { |
7359d482 | 2035 | hsotg->flags.b.port_suspend_change = 1; |
b46146d5 | 2036 | usb_hcd_resume_root_hub(hsotg->priv); |
b46146d5 | 2037 | } |
1fb7f12d DA |
2038 | |
2039 | if (hsotg->lx_state == DWC2_L1) | |
2040 | hsotg->flags.b.port_l1_change = 1; | |
7359d482 PZ |
2041 | } |
2042 | ||
2043 | /** | |
2044 | * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner | |
2045 | * | |
2046 | * @hsotg: Pointer to struct dwc2_hsotg | |
2047 | * | |
2048 | * Must be called with interrupt disabled and spinlock held | |
2049 | */ | |
2050 | void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) | |
2051 | { | |
2052 | dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); | |
2053 | ||
2054 | /* | |
2055 | * The root hub should be disconnected before this function is called. | |
2056 | * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) | |
2057 | * and the QH lists (via ..._hcd_endpoint_disable). | |
2058 | */ | |
2059 | ||
2060 | /* Turn off all host-specific interrupts */ | |
2061 | dwc2_disable_host_interrupts(hsotg); | |
2062 | ||
2063 | /* Turn off the vbus power */ | |
2064 | dev_dbg(hsotg->dev, "PortPower off\n"); | |
95c8bc36 | 2065 | dwc2_writel(0, hsotg->regs + HPRT0); |
7359d482 PZ |
2066 | } |
2067 | ||
33ad261a | 2068 | /* Caller must hold driver lock */ |
7359d482 | 2069 | static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, |
b58e6cee | 2070 | struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, |
b5a468a6 | 2071 | struct dwc2_qtd *qtd) |
7359d482 | 2072 | { |
7359d482 PZ |
2073 | u32 intr_mask; |
2074 | int retval; | |
9f8144c6 | 2075 | int dev_speed; |
7359d482 PZ |
2076 | |
2077 | if (!hsotg->flags.b.port_connect_status) { | |
2078 | /* No longer connected */ | |
2079 | dev_err(hsotg->dev, "Not connected\n"); | |
2080 | return -ENODEV; | |
2081 | } | |
2082 | ||
9f8144c6 NH |
2083 | dev_speed = dwc2_host_get_speed(hsotg, urb->priv); |
2084 | ||
2085 | /* Some configurations cannot support LS traffic on a FS root port */ | |
2086 | if ((dev_speed == USB_SPEED_LOW) && | |
2087 | (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && | |
2088 | (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { | |
95c8bc36 | 2089 | u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); |
9f8144c6 NH |
2090 | u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; |
2091 | ||
2092 | if (prtspd == HPRT0_SPD_FULL_SPEED) | |
2093 | return -ENODEV; | |
2094 | } | |
2095 | ||
7359d482 | 2096 | if (!qtd) |
b5a468a6 | 2097 | return -EINVAL; |
7359d482 PZ |
2098 | |
2099 | dwc2_hcd_qtd_init(qtd, urb); | |
b58e6cee | 2100 | retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); |
9bda1aac | 2101 | if (retval) { |
7359d482 PZ |
2102 | dev_err(hsotg->dev, |
2103 | "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", | |
2104 | retval); | |
7359d482 PZ |
2105 | return retval; |
2106 | } | |
2107 | ||
95c8bc36 | 2108 | intr_mask = dwc2_readl(hsotg->regs + GINTMSK); |
9bda1aac | 2109 | if (!(intr_mask & GINTSTS_SOF)) { |
7359d482 PZ |
2110 | enum dwc2_transaction_type tr_type; |
2111 | ||
2112 | if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && | |
2113 | !(qtd->urb->flags & URB_GIVEBACK_ASAP)) | |
2114 | /* | |
2115 | * Do not schedule SG transactions until qtd has | |
2116 | * URB_GIVEBACK_ASAP set | |
2117 | */ | |
2118 | return 0; | |
2119 | ||
7359d482 PZ |
2120 | tr_type = dwc2_hcd_select_transactions(hsotg); |
2121 | if (tr_type != DWC2_TRANSACTION_NONE) | |
2122 | dwc2_hcd_queue_transactions(hsotg, tr_type); | |
7359d482 PZ |
2123 | } |
2124 | ||
9bda1aac | 2125 | return 0; |
7359d482 PZ |
2126 | } |
2127 | ||
2128 | /* Must be called with interrupt disabled and spinlock held */ | |
2129 | static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, | |
2130 | struct dwc2_hcd_urb *urb) | |
2131 | { | |
2132 | struct dwc2_qh *qh; | |
2133 | struct dwc2_qtd *urb_qtd; | |
2134 | ||
2135 | urb_qtd = urb->qtd; | |
2136 | if (!urb_qtd) { | |
2137 | dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); | |
2138 | return -EINVAL; | |
2139 | } | |
2140 | ||
2141 | qh = urb_qtd->qh; | |
2142 | if (!qh) { | |
2143 | dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); | |
2144 | return -EINVAL; | |
2145 | } | |
2146 | ||
0d012b98 PZ |
2147 | urb->priv = NULL; |
2148 | ||
7359d482 PZ |
2149 | if (urb_qtd->in_process && qh->channel) { |
2150 | dwc2_dump_channel_info(hsotg, qh->channel); | |
2151 | ||
2152 | /* The QTD is in process (it has been assigned to a channel) */ | |
2153 | if (hsotg->flags.b.port_connect_status) | |
2154 | /* | |
2155 | * If still connected (i.e. in host mode), halt the | |
2156 | * channel so it can be used for other transfers. If | |
2157 | * no longer connected, the host registers can't be | |
2158 | * written to halt the channel since the core is in | |
2159 | * device mode. | |
2160 | */ | |
2161 | dwc2_hc_halt(hsotg, qh->channel, | |
2162 | DWC2_HC_XFER_URB_DEQUEUE); | |
2163 | } | |
2164 | ||
2165 | /* | |
2166 | * Free the QTD and clean up the associated QH. Leave the QH in the | |
2167 | * schedule if it has any remaining QTDs. | |
2168 | */ | |
95832c00 | 2169 | if (!hsotg->params.dma_desc_enable) { |
7359d482 PZ |
2170 | u8 in_process = urb_qtd->in_process; |
2171 | ||
2172 | dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); | |
2173 | if (in_process) { | |
2174 | dwc2_hcd_qh_deactivate(hsotg, qh, 0); | |
2175 | qh->channel = NULL; | |
2176 | } else if (list_empty(&qh->qtd_list)) { | |
2177 | dwc2_hcd_qh_unlink(hsotg, qh); | |
2178 | } | |
2179 | } else { | |
2180 | dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); | |
2181 | } | |
2182 | ||
2183 | return 0; | |
2184 | } | |
2185 | ||
2186 | /* Must NOT be called with interrupt disabled or spinlock held */ | |
2187 | static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, | |
2188 | struct usb_host_endpoint *ep, int retry) | |
2189 | { | |
2190 | struct dwc2_qtd *qtd, *qtd_tmp; | |
2191 | struct dwc2_qh *qh; | |
2192 | unsigned long flags; | |
2193 | int rc; | |
2194 | ||
2195 | spin_lock_irqsave(&hsotg->lock, flags); | |
2196 | ||
2197 | qh = ep->hcpriv; | |
2198 | if (!qh) { | |
2199 | rc = -EINVAL; | |
2200 | goto err; | |
2201 | } | |
2202 | ||
2203 | while (!list_empty(&qh->qtd_list) && retry--) { | |
2204 | if (retry == 0) { | |
2205 | dev_err(hsotg->dev, | |
2206 | "## timeout in dwc2_hcd_endpoint_disable() ##\n"); | |
2207 | rc = -EBUSY; | |
2208 | goto err; | |
2209 | } | |
2210 | ||
2211 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
04a9db79 | 2212 | msleep(20); |
7359d482 PZ |
2213 | spin_lock_irqsave(&hsotg->lock, flags); |
2214 | qh = ep->hcpriv; | |
2215 | if (!qh) { | |
2216 | rc = -EINVAL; | |
2217 | goto err; | |
2218 | } | |
2219 | } | |
2220 | ||
2221 | dwc2_hcd_qh_unlink(hsotg, qh); | |
2222 | ||
2223 | /* Free each QTD in the QH's QTD list */ | |
2224 | list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) | |
2225 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); | |
2226 | ||
2227 | ep->hcpriv = NULL; | |
16e80218 DA |
2228 | |
2229 | if (qh->channel && qh->channel->qh == qh) | |
2230 | qh->channel->qh = NULL; | |
2231 | ||
7359d482 | 2232 | spin_unlock_irqrestore(&hsotg->lock, flags); |
16e80218 | 2233 | |
7359d482 PZ |
2234 | dwc2_hcd_qh_free(hsotg, qh); |
2235 | ||
2236 | return 0; | |
2237 | ||
2238 | err: | |
2239 | ep->hcpriv = NULL; | |
2240 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
2241 | ||
2242 | return rc; | |
2243 | } | |
2244 | ||
2245 | /* Must be called with interrupt disabled and spinlock held */ | |
2246 | static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, | |
2247 | struct usb_host_endpoint *ep) | |
2248 | { | |
2249 | struct dwc2_qh *qh = ep->hcpriv; | |
2250 | ||
2251 | if (!qh) | |
2252 | return -EINVAL; | |
2253 | ||
2254 | qh->data_toggle = DWC2_HC_PID_DATA0; | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
b02038fa JY |
2259 | /** |
2260 | * dwc2_core_init() - Initializes the DWC_otg controller registers and | |
2261 | * prepares the core for device mode or host mode operation | |
2262 | * | |
2263 | * @hsotg: Programming view of the DWC_otg controller | |
2264 | * @initial_setup: If true then this is the first init for this instance. | |
2265 | */ | |
65c9c4c6 | 2266 | int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) |
b02038fa JY |
2267 | { |
2268 | u32 usbcfg, otgctl; | |
2269 | int retval; | |
2270 | ||
2271 | dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); | |
2272 | ||
2273 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2274 | ||
2275 | /* Set ULPI External VBUS bit if needed */ | |
2276 | usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; | |
95832c00 | 2277 | if (hsotg->params.phy_ulpi_ext_vbus) |
b02038fa JY |
2278 | usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; |
2279 | ||
2280 | /* Set external TS Dline pulsing bit if needed */ | |
2281 | usbcfg &= ~GUSBCFG_TERMSELDLPULSE; | |
95832c00 | 2282 | if (hsotg->params.ts_dline) |
b02038fa JY |
2283 | usbcfg |= GUSBCFG_TERMSELDLPULSE; |
2284 | ||
2285 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
2286 | ||
2287 | /* | |
2288 | * Reset the Controller | |
2289 | * | |
2290 | * We only need to reset the controller if this is a re-init. | |
2291 | * For the first init we know for sure that earlier code reset us (it | |
2292 | * needed to in order to properly detect various parameters). | |
2293 | */ | |
2294 | if (!initial_setup) { | |
13b1f8e2 | 2295 | retval = dwc2_core_reset(hsotg, false); |
b02038fa JY |
2296 | if (retval) { |
2297 | dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", | |
2298 | __func__); | |
2299 | return retval; | |
2300 | } | |
2301 | } | |
2302 | ||
2303 | /* | |
2304 | * This needs to happen in FS mode before any other programming occurs | |
2305 | */ | |
2306 | retval = dwc2_phy_init(hsotg, initial_setup); | |
2307 | if (retval) | |
2308 | return retval; | |
2309 | ||
2310 | /* Program the GAHBCFG Register */ | |
2311 | retval = dwc2_gahbcfg_init(hsotg); | |
2312 | if (retval) | |
2313 | return retval; | |
2314 | ||
2315 | /* Program the GUSBCFG register */ | |
2316 | dwc2_gusbcfg_init(hsotg); | |
2317 | ||
2318 | /* Program the GOTGCTL register */ | |
2319 | otgctl = dwc2_readl(hsotg->regs + GOTGCTL); | |
2320 | otgctl &= ~GOTGCTL_OTGVER; | |
b02038fa | 2321 | dwc2_writel(otgctl, hsotg->regs + GOTGCTL); |
b02038fa JY |
2322 | |
2323 | /* Clear the SRP success bit for FS-I2c */ | |
2324 | hsotg->srp_success = 0; | |
2325 | ||
2326 | /* Enable common interrupts */ | |
2327 | dwc2_enable_common_interrupts(hsotg); | |
2328 | ||
2329 | /* | |
2330 | * Do device or host initialization based on mode during PCD and | |
2331 | * HCD initialization | |
2332 | */ | |
2333 | if (dwc2_is_host_mode(hsotg)) { | |
2334 | dev_dbg(hsotg->dev, "Host Mode\n"); | |
2335 | hsotg->op_state = OTG_STATE_A_HOST; | |
2336 | } else { | |
2337 | dev_dbg(hsotg->dev, "Device Mode\n"); | |
2338 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
2339 | } | |
2340 | ||
2341 | return 0; | |
2342 | } | |
2343 | ||
2344 | /** | |
2345 | * dwc2_core_host_init() - Initializes the DWC_otg controller registers for | |
2346 | * Host mode | |
2347 | * | |
2348 | * @hsotg: Programming view of DWC_otg controller | |
2349 | * | |
2350 | * This function flushes the Tx and Rx FIFOs and flushes any entries in the | |
2351 | * request queues. Host channels are reset to ensure that they are ready for | |
2352 | * performing transfers. | |
2353 | */ | |
2354 | static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) | |
2355 | { | |
92a8dd26 | 2356 | u32 hcfg, hfir, otgctl, usbcfg; |
b02038fa JY |
2357 | |
2358 | dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); | |
2359 | ||
92a8dd26 MH |
2360 | /* Set HS/FS Timeout Calibration to 7 (max available value). |
2361 | * The number of PHY clocks that the application programs in | |
2362 | * this field is added to the high/full speed interpacket timeout | |
2363 | * duration in the core to account for any additional delays | |
2364 | * introduced by the PHY. This can be required, because the delay | |
2365 | * introduced by the PHY in generating the linestate condition | |
2366 | * can vary from one PHY to another. | |
2367 | */ | |
2368 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2369 | usbcfg |= GUSBCFG_TOUTCAL(7); | |
2370 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
2371 | ||
b02038fa JY |
2372 | /* Restart the Phy Clock */ |
2373 | dwc2_writel(0, hsotg->regs + PCGCTL); | |
2374 | ||
2375 | /* Initialize Host Configuration Register */ | |
2376 | dwc2_init_fs_ls_pclk_sel(hsotg); | |
38e9002b VM |
2377 | if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
2378 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { | |
b02038fa JY |
2379 | hcfg = dwc2_readl(hsotg->regs + HCFG); |
2380 | hcfg |= HCFG_FSLSSUPP; | |
2381 | dwc2_writel(hcfg, hsotg->regs + HCFG); | |
2382 | } | |
2383 | ||
2384 | /* | |
2385 | * This bit allows dynamic reloading of the HFIR register during | |
2386 | * runtime. This bit needs to be programmed during initial configuration | |
2387 | * and its value must not be changed during runtime. | |
2388 | */ | |
95832c00 | 2389 | if (hsotg->params.reload_ctl) { |
b02038fa JY |
2390 | hfir = dwc2_readl(hsotg->regs + HFIR); |
2391 | hfir |= HFIR_RLDCTRL; | |
2392 | dwc2_writel(hfir, hsotg->regs + HFIR); | |
2393 | } | |
2394 | ||
95832c00 | 2395 | if (hsotg->params.dma_desc_enable) { |
b02038fa JY |
2396 | u32 op_mode = hsotg->hw_params.op_mode; |
2397 | ||
2398 | if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || | |
2399 | !hsotg->hw_params.dma_desc_enable || | |
2400 | op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || | |
2401 | op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || | |
2402 | op_mode == GHWCFG2_OP_MODE_UNDEFINED) { | |
2403 | dev_err(hsotg->dev, | |
2404 | "Hardware does not support descriptor DMA mode -\n"); | |
2405 | dev_err(hsotg->dev, | |
2406 | "falling back to buffer DMA mode.\n"); | |
95832c00 | 2407 | hsotg->params.dma_desc_enable = false; |
b02038fa JY |
2408 | } else { |
2409 | hcfg = dwc2_readl(hsotg->regs + HCFG); | |
2410 | hcfg |= HCFG_DESCDMA; | |
2411 | dwc2_writel(hcfg, hsotg->regs + HCFG); | |
2412 | } | |
2413 | } | |
2414 | ||
2415 | /* Configure data FIFO sizes */ | |
2416 | dwc2_config_fifos(hsotg); | |
2417 | ||
2418 | /* TODO - check this */ | |
2419 | /* Clear Host Set HNP Enable in the OTG Control Register */ | |
2420 | otgctl = dwc2_readl(hsotg->regs + GOTGCTL); | |
2421 | otgctl &= ~GOTGCTL_HSTSETHNPEN; | |
2422 | dwc2_writel(otgctl, hsotg->regs + GOTGCTL); | |
2423 | ||
2424 | /* Make sure the FIFOs are flushed */ | |
2425 | dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); | |
2426 | dwc2_flush_rx_fifo(hsotg); | |
2427 | ||
2428 | /* Clear Host Set HNP Enable in the OTG Control Register */ | |
2429 | otgctl = dwc2_readl(hsotg->regs + GOTGCTL); | |
2430 | otgctl &= ~GOTGCTL_HSTSETHNPEN; | |
2431 | dwc2_writel(otgctl, hsotg->regs + GOTGCTL); | |
2432 | ||
95832c00 | 2433 | if (!hsotg->params.dma_desc_enable) { |
b02038fa JY |
2434 | int num_channels, i; |
2435 | u32 hcchar; | |
2436 | ||
2437 | /* Flush out any leftover queued requests */ | |
bea8e86c | 2438 | num_channels = hsotg->params.host_channels; |
b02038fa JY |
2439 | for (i = 0; i < num_channels; i++) { |
2440 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); | |
2441 | hcchar &= ~HCCHAR_CHENA; | |
2442 | hcchar |= HCCHAR_CHDIS; | |
2443 | hcchar &= ~HCCHAR_EPDIR; | |
2444 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); | |
2445 | } | |
2446 | ||
2447 | /* Halt all channels to put them into a known state */ | |
2448 | for (i = 0; i < num_channels; i++) { | |
b02038fa JY |
2449 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); |
2450 | hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; | |
2451 | hcchar &= ~HCCHAR_EPDIR; | |
2452 | dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); | |
2453 | dev_dbg(hsotg->dev, "%s: Halt channel %d\n", | |
2454 | __func__, i); | |
79d6b8c5 SA |
2455 | |
2456 | if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), | |
2457 | HCCHAR_CHENA, 1000)) { | |
2458 | dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n", | |
2459 | i); | |
2460 | } | |
b02038fa JY |
2461 | } |
2462 | } | |
2463 | ||
66e77a24 RK |
2464 | /* Enable ACG feature in host mode, if supported */ |
2465 | dwc2_enable_acg(hsotg); | |
2466 | ||
b02038fa JY |
2467 | /* Turn on the vbus power */ |
2468 | dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); | |
2469 | if (hsotg->op_state == OTG_STATE_A_HOST) { | |
2470 | u32 hprt0 = dwc2_read_hprt0(hsotg); | |
2471 | ||
2472 | dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", | |
2473 | !!(hprt0 & HPRT0_PWR)); | |
2474 | if (!(hprt0 & HPRT0_PWR)) { | |
2475 | hprt0 |= HPRT0_PWR; | |
2476 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
2477 | } | |
2478 | } | |
2479 | ||
2480 | dwc2_enable_host_interrupts(hsotg); | |
2481 | } | |
2482 | ||
7359d482 PZ |
2483 | /* |
2484 | * Initializes dynamic portions of the DWC_otg HCD state | |
2485 | * | |
2486 | * Must be called with interrupt disabled and spinlock held | |
2487 | */ | |
2488 | static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) | |
2489 | { | |
2490 | struct dwc2_host_chan *chan, *chan_tmp; | |
2491 | int num_channels; | |
2492 | int i; | |
2493 | ||
2494 | hsotg->flags.d32 = 0; | |
7359d482 | 2495 | hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; |
20f2eb9c | 2496 | |
95832c00 | 2497 | if (hsotg->params.uframe_sched) { |
20f2eb9c | 2498 | hsotg->available_host_channels = |
bea8e86c | 2499 | hsotg->params.host_channels; |
20f2eb9c DC |
2500 | } else { |
2501 | hsotg->non_periodic_channels = 0; | |
2502 | hsotg->periodic_channels = 0; | |
2503 | } | |
7359d482 PZ |
2504 | |
2505 | /* | |
2506 | * Put all channels in the free channel list and clean up channel | |
2507 | * states | |
2508 | */ | |
2509 | list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, | |
2510 | hc_list_entry) | |
2511 | list_del_init(&chan->hc_list_entry); | |
2512 | ||
bea8e86c | 2513 | num_channels = hsotg->params.host_channels; |
7359d482 PZ |
2514 | for (i = 0; i < num_channels; i++) { |
2515 | chan = hsotg->hc_ptr_array[i]; | |
2516 | list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); | |
2517 | dwc2_hc_cleanup(hsotg, chan); | |
2518 | } | |
2519 | ||
2520 | /* Initialize the DWC core for host mode operation */ | |
2521 | dwc2_core_host_init(hsotg); | |
2522 | } | |
2523 | ||
2524 | static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, | |
2525 | struct dwc2_host_chan *chan, | |
2526 | struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) | |
2527 | { | |
2528 | int hub_addr, hub_port; | |
2529 | ||
2530 | chan->do_split = 1; | |
2531 | chan->xact_pos = qtd->isoc_split_pos; | |
2532 | chan->complete_split = qtd->complete_split; | |
2533 | dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); | |
2534 | chan->hub_addr = (u8)hub_addr; | |
2535 | chan->hub_port = (u8)hub_port; | |
2536 | } | |
2537 | ||
3bc04e28 DA |
2538 | static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, |
2539 | struct dwc2_host_chan *chan, | |
2540 | struct dwc2_qtd *qtd) | |
7359d482 PZ |
2541 | { |
2542 | struct dwc2_hcd_urb *urb = qtd->urb; | |
2543 | struct dwc2_hcd_iso_packet_desc *frame_desc; | |
2544 | ||
2545 | switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { | |
2546 | case USB_ENDPOINT_XFER_CONTROL: | |
2547 | chan->ep_type = USB_ENDPOINT_XFER_CONTROL; | |
2548 | ||
2549 | switch (qtd->control_phase) { | |
2550 | case DWC2_CONTROL_SETUP: | |
2551 | dev_vdbg(hsotg->dev, " Control setup transaction\n"); | |
2552 | chan->do_ping = 0; | |
2553 | chan->ep_is_in = 0; | |
2554 | chan->data_pid_start = DWC2_HC_PID_SETUP; | |
95832c00 | 2555 | if (hsotg->params.host_dma) |
7359d482 PZ |
2556 | chan->xfer_dma = urb->setup_dma; |
2557 | else | |
2558 | chan->xfer_buf = urb->setup_packet; | |
2559 | chan->xfer_len = 8; | |
7359d482 PZ |
2560 | break; |
2561 | ||
2562 | case DWC2_CONTROL_DATA: | |
2563 | dev_vdbg(hsotg->dev, " Control data transaction\n"); | |
2564 | chan->data_pid_start = qtd->data_toggle; | |
2565 | break; | |
2566 | ||
2567 | case DWC2_CONTROL_STATUS: | |
2568 | /* | |
2569 | * Direction is opposite of data direction or IN if no | |
2570 | * data | |
2571 | */ | |
2572 | dev_vdbg(hsotg->dev, " Control status transaction\n"); | |
2573 | if (urb->length == 0) | |
2574 | chan->ep_is_in = 1; | |
2575 | else | |
2576 | chan->ep_is_in = | |
2577 | dwc2_hcd_is_pipe_out(&urb->pipe_info); | |
2578 | if (chan->ep_is_in) | |
2579 | chan->do_ping = 0; | |
2580 | chan->data_pid_start = DWC2_HC_PID_DATA1; | |
2581 | chan->xfer_len = 0; | |
95832c00 | 2582 | if (hsotg->params.host_dma) |
7359d482 PZ |
2583 | chan->xfer_dma = hsotg->status_buf_dma; |
2584 | else | |
2585 | chan->xfer_buf = hsotg->status_buf; | |
7359d482 PZ |
2586 | break; |
2587 | } | |
2588 | break; | |
2589 | ||
2590 | case USB_ENDPOINT_XFER_BULK: | |
2591 | chan->ep_type = USB_ENDPOINT_XFER_BULK; | |
2592 | break; | |
2593 | ||
2594 | case USB_ENDPOINT_XFER_INT: | |
2595 | chan->ep_type = USB_ENDPOINT_XFER_INT; | |
2596 | break; | |
2597 | ||
2598 | case USB_ENDPOINT_XFER_ISOC: | |
2599 | chan->ep_type = USB_ENDPOINT_XFER_ISOC; | |
95832c00 | 2600 | if (hsotg->params.dma_desc_enable) |
7359d482 PZ |
2601 | break; |
2602 | ||
2603 | frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; | |
2604 | frame_desc->status = 0; | |
2605 | ||
95832c00 | 2606 | if (hsotg->params.host_dma) { |
7359d482 PZ |
2607 | chan->xfer_dma = urb->dma; |
2608 | chan->xfer_dma += frame_desc->offset + | |
2609 | qtd->isoc_split_offset; | |
2610 | } else { | |
2611 | chan->xfer_buf = urb->buf; | |
2612 | chan->xfer_buf += frame_desc->offset + | |
2613 | qtd->isoc_split_offset; | |
2614 | } | |
2615 | ||
2616 | chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; | |
2617 | ||
7359d482 PZ |
2618 | if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { |
2619 | if (chan->xfer_len <= 188) | |
2620 | chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; | |
2621 | else | |
2622 | chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; | |
2623 | } | |
2624 | break; | |
2625 | } | |
3bc04e28 DA |
2626 | } |
2627 | ||
2628 | #define DWC2_USB_DMA_ALIGN 4 | |
2629 | ||
2630 | struct dma_aligned_buffer { | |
2631 | void *kmalloc_ptr; | |
2632 | void *old_xfer_buffer; | |
2633 | u8 data[0]; | |
2634 | }; | |
2635 | ||
2636 | static void dwc2_free_dma_aligned_buffer(struct urb *urb) | |
2637 | { | |
2638 | struct dma_aligned_buffer *temp; | |
2639 | ||
2640 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
2641 | return; | |
7359d482 | 2642 | |
3bc04e28 | 2643 | temp = container_of(urb->transfer_buffer, |
9da51974 | 2644 | struct dma_aligned_buffer, data); |
3bc04e28 DA |
2645 | |
2646 | if (usb_urb_dir_in(urb)) | |
2647 | memcpy(temp->old_xfer_buffer, temp->data, | |
2648 | urb->transfer_buffer_length); | |
2649 | urb->transfer_buffer = temp->old_xfer_buffer; | |
2650 | kfree(temp->kmalloc_ptr); | |
2651 | ||
2652 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
7359d482 PZ |
2653 | } |
2654 | ||
3bc04e28 | 2655 | static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
7359d482 | 2656 | { |
3bc04e28 DA |
2657 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
2658 | size_t kmalloc_size; | |
7359d482 | 2659 | |
3bc04e28 DA |
2660 | if (urb->num_sgs || urb->sg || |
2661 | urb->transfer_buffer_length == 0 || | |
2662 | !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) | |
2663 | return 0; | |
5dce9555 | 2664 | |
3bc04e28 DA |
2665 | /* Allocate a buffer with enough padding for alignment */ |
2666 | kmalloc_size = urb->transfer_buffer_length + | |
2667 | sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; | |
7359d482 | 2668 | |
3bc04e28 DA |
2669 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); |
2670 | if (!kmalloc_ptr) | |
2671 | return -ENOMEM; | |
5dce9555 | 2672 | |
3bc04e28 DA |
2673 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
2674 | temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; | |
2675 | temp->kmalloc_ptr = kmalloc_ptr; | |
2676 | temp->old_xfer_buffer = urb->transfer_buffer; | |
2677 | if (usb_urb_dir_out(urb)) | |
2678 | memcpy(temp->data, urb->transfer_buffer, | |
2679 | urb->transfer_buffer_length); | |
2680 | urb->transfer_buffer = temp->data; | |
7359d482 | 2681 | |
3bc04e28 | 2682 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; |
db62b9a8 | 2683 | |
7359d482 PZ |
2684 | return 0; |
2685 | } | |
2686 | ||
3bc04e28 | 2687 | static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, |
9da51974 | 2688 | gfp_t mem_flags) |
3bc04e28 DA |
2689 | { |
2690 | int ret; | |
2691 | ||
2692 | /* We assume setup_dma is always aligned; warn if not */ | |
2693 | WARN_ON_ONCE(urb->setup_dma && | |
2694 | (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); | |
2695 | ||
2696 | ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); | |
2697 | if (ret) | |
2698 | return ret; | |
2699 | ||
2700 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
2701 | if (ret) | |
2702 | dwc2_free_dma_aligned_buffer(urb); | |
2703 | ||
2704 | return ret; | |
2705 | } | |
2706 | ||
2707 | static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
2708 | { | |
2709 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
2710 | dwc2_free_dma_aligned_buffer(urb); | |
2711 | } | |
2712 | ||
7359d482 PZ |
2713 | /** |
2714 | * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host | |
2715 | * channel and initializes the host channel to perform the transactions. The | |
2716 | * host channel is removed from the free list. | |
2717 | * | |
2718 | * @hsotg: The HCD state structure | |
2719 | * @qh: Transactions from the first QTD for this QH are selected and assigned | |
2720 | * to a free host channel | |
2721 | */ | |
20f2eb9c | 2722 | static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) |
7359d482 PZ |
2723 | { |
2724 | struct dwc2_host_chan *chan; | |
2725 | struct dwc2_hcd_urb *urb; | |
2726 | struct dwc2_qtd *qtd; | |
7359d482 | 2727 | |
b49977a6 MK |
2728 | if (dbg_qh(qh)) |
2729 | dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); | |
7359d482 PZ |
2730 | |
2731 | if (list_empty(&qh->qtd_list)) { | |
2732 | dev_dbg(hsotg->dev, "No QTDs in QH list\n"); | |
20f2eb9c | 2733 | return -ENOMEM; |
7359d482 PZ |
2734 | } |
2735 | ||
2736 | if (list_empty(&hsotg->free_hc_list)) { | |
2737 | dev_dbg(hsotg->dev, "No free channel to assign\n"); | |
20f2eb9c | 2738 | return -ENOMEM; |
7359d482 PZ |
2739 | } |
2740 | ||
2741 | chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, | |
2742 | hc_list_entry); | |
2743 | ||
20f2eb9c | 2744 | /* Remove host channel from free list */ |
7359d482 PZ |
2745 | list_del_init(&chan->hc_list_entry); |
2746 | ||
2747 | qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); | |
2748 | urb = qtd->urb; | |
2749 | qh->channel = chan; | |
2750 | qtd->in_process = 1; | |
2751 | ||
2752 | /* | |
2753 | * Use usb_pipedevice to determine device address. This address is | |
2754 | * 0 before the SET_ADDRESS command and the correct address afterward. | |
2755 | */ | |
2756 | chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); | |
2757 | chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); | |
2758 | chan->speed = qh->dev_speed; | |
2759 | chan->max_packet = dwc2_max_packet(qh->maxp); | |
2760 | ||
2761 | chan->xfer_started = 0; | |
2762 | chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; | |
2763 | chan->error_state = (qtd->error_count > 0); | |
2764 | chan->halt_on_queue = 0; | |
2765 | chan->halt_pending = 0; | |
2766 | chan->requests = 0; | |
2767 | ||
2768 | /* | |
2769 | * The following values may be modified in the transfer type section | |
2770 | * below. The xfer_len value may be reduced when the transfer is | |
2771 | * started to accommodate the max widths of the XferSize and PktCnt | |
2772 | * fields in the HCTSIZn register. | |
2773 | */ | |
2774 | ||
2775 | chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); | |
2776 | if (chan->ep_is_in) | |
2777 | chan->do_ping = 0; | |
2778 | else | |
2779 | chan->do_ping = qh->ping_state; | |
2780 | ||
2781 | chan->data_pid_start = qh->data_toggle; | |
2782 | chan->multi_count = 1; | |
2783 | ||
bb6c3422 | 2784 | if (urb->actual_length > urb->length && |
9da51974 | 2785 | !dwc2_hcd_is_pipe_in(&urb->pipe_info)) |
84181086 PZ |
2786 | urb->actual_length = urb->length; |
2787 | ||
95832c00 | 2788 | if (hsotg->params.host_dma) |
7359d482 | 2789 | chan->xfer_dma = urb->dma + urb->actual_length; |
3bc04e28 | 2790 | else |
7359d482 | 2791 | chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; |
7359d482 PZ |
2792 | |
2793 | chan->xfer_len = urb->length - urb->actual_length; | |
2794 | chan->xfer_count = 0; | |
2795 | ||
2796 | /* Set the split attributes if required */ | |
2797 | if (qh->do_split) | |
2798 | dwc2_hc_init_split(hsotg, chan, qtd, urb); | |
2799 | else | |
2800 | chan->do_split = 0; | |
2801 | ||
2802 | /* Set the transfer attributes */ | |
3bc04e28 | 2803 | dwc2_hc_init_xfer(hsotg, chan, qtd); |
7359d482 PZ |
2804 | |
2805 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || | |
2806 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) | |
2807 | /* | |
2808 | * This value may be modified when the transfer is started | |
2809 | * to reflect the actual transfer length | |
2810 | */ | |
2811 | chan->multi_count = dwc2_hb_mult(qh->maxp); | |
2812 | ||
95832c00 | 2813 | if (hsotg->params.dma_desc_enable) { |
7359d482 | 2814 | chan->desc_list_addr = qh->desc_list_dma; |
95105a99 GH |
2815 | chan->desc_list_sz = qh->desc_list_sz; |
2816 | } | |
7359d482 PZ |
2817 | |
2818 | dwc2_hc_init(hsotg, chan); | |
2819 | chan->qh = qh; | |
20f2eb9c DC |
2820 | |
2821 | return 0; | |
7359d482 PZ |
2822 | } |
2823 | ||
2824 | /** | |
2825 | * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer | |
2826 | * schedule and assigns them to available host channels. Called from the HCD | |
2827 | * interrupt handler functions. | |
2828 | * | |
2829 | * @hsotg: The HCD state structure | |
2830 | * | |
2831 | * Return: The types of new transactions that were assigned to host channels | |
2832 | */ | |
2833 | enum dwc2_transaction_type dwc2_hcd_select_transactions( | |
2834 | struct dwc2_hsotg *hsotg) | |
2835 | { | |
2836 | enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; | |
2837 | struct list_head *qh_ptr; | |
2838 | struct dwc2_qh *qh; | |
2839 | int num_channels; | |
2840 | ||
2841 | #ifdef DWC2_DEBUG_SOF | |
2842 | dev_vdbg(hsotg->dev, " Select Transactions\n"); | |
2843 | #endif | |
2844 | ||
2845 | /* Process entries in the periodic ready list */ | |
2846 | qh_ptr = hsotg->periodic_sched_ready.next; | |
2847 | while (qh_ptr != &hsotg->periodic_sched_ready) { | |
2848 | if (list_empty(&hsotg->free_hc_list)) | |
2849 | break; | |
95832c00 | 2850 | if (hsotg->params.uframe_sched) { |
20f2eb9c DC |
2851 | if (hsotg->available_host_channels <= 1) |
2852 | break; | |
2853 | hsotg->available_host_channels--; | |
2854 | } | |
7359d482 | 2855 | qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); |
20f2eb9c DC |
2856 | if (dwc2_assign_and_init_hc(hsotg, qh)) |
2857 | break; | |
7359d482 PZ |
2858 | |
2859 | /* | |
2860 | * Move the QH from the periodic ready schedule to the | |
2861 | * periodic assigned schedule | |
2862 | */ | |
2863 | qh_ptr = qh_ptr->next; | |
94ef7aee DA |
2864 | list_move_tail(&qh->qh_list_entry, |
2865 | &hsotg->periodic_sched_assigned); | |
7359d482 PZ |
2866 | ret_val = DWC2_TRANSACTION_PERIODIC; |
2867 | } | |
2868 | ||
2869 | /* | |
2870 | * Process entries in the inactive portion of the non-periodic | |
2871 | * schedule. Some free host channels may not be used if they are | |
2872 | * reserved for periodic transfers. | |
2873 | */ | |
bea8e86c | 2874 | num_channels = hsotg->params.host_channels; |
7359d482 PZ |
2875 | qh_ptr = hsotg->non_periodic_sched_inactive.next; |
2876 | while (qh_ptr != &hsotg->non_periodic_sched_inactive) { | |
95832c00 | 2877 | if (!hsotg->params.uframe_sched && |
20f2eb9c | 2878 | hsotg->non_periodic_channels >= num_channels - |
7359d482 PZ |
2879 | hsotg->periodic_channels) |
2880 | break; | |
2881 | if (list_empty(&hsotg->free_hc_list)) | |
2882 | break; | |
2883 | qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); | |
95832c00 | 2884 | if (hsotg->params.uframe_sched) { |
20f2eb9c DC |
2885 | if (hsotg->available_host_channels < 1) |
2886 | break; | |
2887 | hsotg->available_host_channels--; | |
2888 | } | |
2889 | ||
2890 | if (dwc2_assign_and_init_hc(hsotg, qh)) | |
2891 | break; | |
7359d482 PZ |
2892 | |
2893 | /* | |
2894 | * Move the QH from the non-periodic inactive schedule to the | |
2895 | * non-periodic active schedule | |
2896 | */ | |
2897 | qh_ptr = qh_ptr->next; | |
94ef7aee DA |
2898 | list_move_tail(&qh->qh_list_entry, |
2899 | &hsotg->non_periodic_sched_active); | |
7359d482 PZ |
2900 | |
2901 | if (ret_val == DWC2_TRANSACTION_NONE) | |
2902 | ret_val = DWC2_TRANSACTION_NON_PERIODIC; | |
2903 | else | |
2904 | ret_val = DWC2_TRANSACTION_ALL; | |
2905 | ||
95832c00 | 2906 | if (!hsotg->params.uframe_sched) |
20f2eb9c | 2907 | hsotg->non_periodic_channels++; |
7359d482 PZ |
2908 | } |
2909 | ||
2910 | return ret_val; | |
2911 | } | |
2912 | ||
2913 | /** | |
2914 | * dwc2_queue_transaction() - Attempts to queue a single transaction request for | |
2915 | * a host channel associated with either a periodic or non-periodic transfer | |
2916 | * | |
2917 | * @hsotg: The HCD state structure | |
2918 | * @chan: Host channel descriptor associated with either a periodic or | |
2919 | * non-periodic transfer | |
2920 | * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO | |
2921 | * for periodic transfers or the non-periodic Tx FIFO | |
2922 | * for non-periodic transfers | |
2923 | * | |
2924 | * Return: 1 if a request is queued and more requests may be needed to | |
2925 | * complete the transfer, 0 if no more requests are required for this | |
2926 | * transfer, -1 if there is insufficient space in the Tx FIFO | |
2927 | * | |
2928 | * This function assumes that there is space available in the appropriate | |
2929 | * request queue. For an OUT transfer or SETUP transaction in Slave mode, | |
2930 | * it checks whether space is available in the appropriate Tx FIFO. | |
2931 | * | |
2932 | * Must be called with interrupt disabled and spinlock held | |
2933 | */ | |
2934 | static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, | |
2935 | struct dwc2_host_chan *chan, | |
2936 | u16 fifo_dwords_avail) | |
2937 | { | |
2938 | int retval = 0; | |
2939 | ||
c9c8ac01 DA |
2940 | if (chan->do_split) |
2941 | /* Put ourselves on the list to keep order straight */ | |
2942 | list_move_tail(&chan->split_order_list_entry, | |
2943 | &hsotg->split_order); | |
2944 | ||
95832c00 JY |
2945 | if (hsotg->params.host_dma) { |
2946 | if (hsotg->params.dma_desc_enable) { | |
7359d482 PZ |
2947 | if (!chan->xfer_started || |
2948 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { | |
2949 | dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); | |
2950 | chan->qh->ping_state = 0; | |
2951 | } | |
2952 | } else if (!chan->xfer_started) { | |
2953 | dwc2_hc_start_transfer(hsotg, chan); | |
2954 | chan->qh->ping_state = 0; | |
2955 | } | |
2956 | } else if (chan->halt_pending) { | |
2957 | /* Don't queue a request if the channel has been halted */ | |
2958 | } else if (chan->halt_on_queue) { | |
2959 | dwc2_hc_halt(hsotg, chan, chan->halt_status); | |
2960 | } else if (chan->do_ping) { | |
2961 | if (!chan->xfer_started) | |
2962 | dwc2_hc_start_transfer(hsotg, chan); | |
2963 | } else if (!chan->ep_is_in || | |
2964 | chan->data_pid_start == DWC2_HC_PID_SETUP) { | |
2965 | if ((fifo_dwords_avail * 4) >= chan->max_packet) { | |
2966 | if (!chan->xfer_started) { | |
2967 | dwc2_hc_start_transfer(hsotg, chan); | |
2968 | retval = 1; | |
2969 | } else { | |
2970 | retval = dwc2_hc_continue_transfer(hsotg, chan); | |
2971 | } | |
2972 | } else { | |
2973 | retval = -1; | |
2974 | } | |
2975 | } else { | |
2976 | if (!chan->xfer_started) { | |
2977 | dwc2_hc_start_transfer(hsotg, chan); | |
2978 | retval = 1; | |
2979 | } else { | |
2980 | retval = dwc2_hc_continue_transfer(hsotg, chan); | |
2981 | } | |
2982 | } | |
2983 | ||
2984 | return retval; | |
2985 | } | |
2986 | ||
2987 | /* | |
2988 | * Processes periodic channels for the next frame and queues transactions for | |
2989 | * these channels to the DWC_otg controller. After queueing transactions, the | |
2990 | * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions | |
2991 | * to queue as Periodic Tx FIFO or request queue space becomes available. | |
2992 | * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. | |
2993 | * | |
2994 | * Must be called with interrupt disabled and spinlock held | |
2995 | */ | |
2996 | static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) | |
2997 | { | |
2998 | struct list_head *qh_ptr; | |
2999 | struct dwc2_qh *qh; | |
3000 | u32 tx_status; | |
3001 | u32 fspcavail; | |
3002 | u32 gintmsk; | |
3003 | int status; | |
4e50e011 DA |
3004 | bool no_queue_space = false; |
3005 | bool no_fifo_space = false; | |
7359d482 PZ |
3006 | u32 qspcavail; |
3007 | ||
4e50e011 DA |
3008 | /* If empty list then just adjust interrupt enables */ |
3009 | if (list_empty(&hsotg->periodic_sched_assigned)) | |
3010 | goto exit; | |
3011 | ||
b49977a6 MK |
3012 | if (dbg_perio()) |
3013 | dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); | |
7359d482 | 3014 | |
95c8bc36 | 3015 | tx_status = dwc2_readl(hsotg->regs + HPTXSTS); |
d6ec53e0 MK |
3016 | qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> |
3017 | TXSTS_QSPCAVAIL_SHIFT; | |
3018 | fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> | |
3019 | TXSTS_FSPCAVAIL_SHIFT; | |
b49977a6 MK |
3020 | |
3021 | if (dbg_perio()) { | |
3022 | dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", | |
3023 | qspcavail); | |
3024 | dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", | |
3025 | fspcavail); | |
3026 | } | |
7359d482 PZ |
3027 | |
3028 | qh_ptr = hsotg->periodic_sched_assigned.next; | |
3029 | while (qh_ptr != &hsotg->periodic_sched_assigned) { | |
95c8bc36 | 3030 | tx_status = dwc2_readl(hsotg->regs + HPTXSTS); |
acdb9046 MK |
3031 | qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> |
3032 | TXSTS_QSPCAVAIL_SHIFT; | |
3033 | if (qspcavail == 0) { | |
fdb09b3e | 3034 | no_queue_space = true; |
7359d482 PZ |
3035 | break; |
3036 | } | |
3037 | ||
3038 | qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); | |
3039 | if (!qh->channel) { | |
3040 | qh_ptr = qh_ptr->next; | |
3041 | continue; | |
3042 | } | |
3043 | ||
3044 | /* Make sure EP's TT buffer is clean before queueing qtds */ | |
3045 | if (qh->tt_buffer_dirty) { | |
3046 | qh_ptr = qh_ptr->next; | |
3047 | continue; | |
3048 | } | |
3049 | ||
3050 | /* | |
3051 | * Set a flag if we're queuing high-bandwidth in slave mode. | |
3052 | * The flag prevents any halts to get into the request queue in | |
3053 | * the middle of multiple high-bandwidth packets getting queued. | |
3054 | */ | |
95832c00 | 3055 | if (!hsotg->params.host_dma && |
9da51974 | 3056 | qh->channel->multi_count > 1) |
7359d482 PZ |
3057 | hsotg->queuing_high_bandwidth = 1; |
3058 | ||
d6ec53e0 MK |
3059 | fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> |
3060 | TXSTS_FSPCAVAIL_SHIFT; | |
7359d482 PZ |
3061 | status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); |
3062 | if (status < 0) { | |
fdb09b3e | 3063 | no_fifo_space = true; |
7359d482 PZ |
3064 | break; |
3065 | } | |
3066 | ||
3067 | /* | |
3068 | * In Slave mode, stay on the current transfer until there is | |
3069 | * nothing more to do or the high-bandwidth request count is | |
3070 | * reached. In DMA mode, only need to queue one request. The | |
3071 | * controller automatically handles multiple packets for | |
3072 | * high-bandwidth transfers. | |
3073 | */ | |
95832c00 | 3074 | if (hsotg->params.host_dma || status == 0 || |
7359d482 PZ |
3075 | qh->channel->requests == qh->channel->multi_count) { |
3076 | qh_ptr = qh_ptr->next; | |
3077 | /* | |
3078 | * Move the QH from the periodic assigned schedule to | |
3079 | * the periodic queued schedule | |
3080 | */ | |
94ef7aee DA |
3081 | list_move_tail(&qh->qh_list_entry, |
3082 | &hsotg->periodic_sched_queued); | |
7359d482 PZ |
3083 | |
3084 | /* done queuing high bandwidth */ | |
3085 | hsotg->queuing_high_bandwidth = 0; | |
3086 | } | |
3087 | } | |
3088 | ||
4e50e011 DA |
3089 | exit: |
3090 | if (no_queue_space || no_fifo_space || | |
95832c00 | 3091 | (!hsotg->params.host_dma && |
4e50e011 DA |
3092 | !list_empty(&hsotg->periodic_sched_assigned))) { |
3093 | /* | |
3094 | * May need to queue more transactions as the request | |
3095 | * queue or Tx FIFO empties. Enable the periodic Tx | |
3096 | * FIFO empty interrupt. (Always use the half-empty | |
3097 | * level to ensure that new requests are loaded as | |
3098 | * soon as possible.) | |
3099 | */ | |
3100 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3101 | if (!(gintmsk & GINTSTS_PTXFEMP)) { | |
7359d482 | 3102 | gintmsk |= GINTSTS_PTXFEMP; |
95c8bc36 | 3103 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
4e50e011 DA |
3104 | } |
3105 | } else { | |
3106 | /* | |
3107 | * Disable the Tx FIFO empty interrupt since there are | |
3108 | * no more transactions that need to be queued right | |
3109 | * now. This function is called from interrupt | |
3110 | * handlers to queue more transactions as transfer | |
3111 | * states change. | |
38beaec6 | 3112 | */ |
4e50e011 DA |
3113 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
3114 | if (gintmsk & GINTSTS_PTXFEMP) { | |
7359d482 | 3115 | gintmsk &= ~GINTSTS_PTXFEMP; |
95c8bc36 | 3116 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
3117 | } |
3118 | } | |
3119 | } | |
3120 | ||
3121 | /* | |
3122 | * Processes active non-periodic channels and queues transactions for these | |
3123 | * channels to the DWC_otg controller. After queueing transactions, the NP Tx | |
3124 | * FIFO Empty interrupt is enabled if there are more transactions to queue as | |
3125 | * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx | |
3126 | * FIFO Empty interrupt is disabled. | |
3127 | * | |
3128 | * Must be called with interrupt disabled and spinlock held | |
3129 | */ | |
3130 | static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) | |
3131 | { | |
3132 | struct list_head *orig_qh_ptr; | |
3133 | struct dwc2_qh *qh; | |
3134 | u32 tx_status; | |
3135 | u32 qspcavail; | |
3136 | u32 fspcavail; | |
3137 | u32 gintmsk; | |
3138 | int status; | |
3139 | int no_queue_space = 0; | |
3140 | int no_fifo_space = 0; | |
3141 | int more_to_do = 0; | |
3142 | ||
3143 | dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); | |
3144 | ||
95c8bc36 | 3145 | tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); |
d6ec53e0 MK |
3146 | qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> |
3147 | TXSTS_QSPCAVAIL_SHIFT; | |
3148 | fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> | |
3149 | TXSTS_FSPCAVAIL_SHIFT; | |
7359d482 PZ |
3150 | dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", |
3151 | qspcavail); | |
3152 | dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", | |
3153 | fspcavail); | |
3154 | ||
3155 | /* | |
3156 | * Keep track of the starting point. Skip over the start-of-list | |
3157 | * entry. | |
3158 | */ | |
3159 | if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) | |
3160 | hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; | |
3161 | orig_qh_ptr = hsotg->non_periodic_qh_ptr; | |
3162 | ||
3163 | /* | |
3164 | * Process once through the active list or until no more space is | |
3165 | * available in the request queue or the Tx FIFO | |
3166 | */ | |
3167 | do { | |
95c8bc36 | 3168 | tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); |
d6ec53e0 MK |
3169 | qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> |
3170 | TXSTS_QSPCAVAIL_SHIFT; | |
95832c00 | 3171 | if (!hsotg->params.host_dma && qspcavail == 0) { |
7359d482 PZ |
3172 | no_queue_space = 1; |
3173 | break; | |
3174 | } | |
3175 | ||
3176 | qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, | |
3177 | qh_list_entry); | |
3178 | if (!qh->channel) | |
3179 | goto next; | |
3180 | ||
3181 | /* Make sure EP's TT buffer is clean before queueing qtds */ | |
3182 | if (qh->tt_buffer_dirty) | |
3183 | goto next; | |
3184 | ||
d6ec53e0 MK |
3185 | fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> |
3186 | TXSTS_FSPCAVAIL_SHIFT; | |
7359d482 PZ |
3187 | status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); |
3188 | ||
3189 | if (status > 0) { | |
3190 | more_to_do = 1; | |
3191 | } else if (status < 0) { | |
3192 | no_fifo_space = 1; | |
3193 | break; | |
3194 | } | |
3195 | next: | |
3196 | /* Advance to next QH, skipping start-of-list entry */ | |
3197 | hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; | |
3198 | if (hsotg->non_periodic_qh_ptr == | |
3199 | &hsotg->non_periodic_sched_active) | |
3200 | hsotg->non_periodic_qh_ptr = | |
3201 | hsotg->non_periodic_qh_ptr->next; | |
3202 | } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); | |
3203 | ||
95832c00 | 3204 | if (!hsotg->params.host_dma) { |
95c8bc36 | 3205 | tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); |
d6ec53e0 MK |
3206 | qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> |
3207 | TXSTS_QSPCAVAIL_SHIFT; | |
3208 | fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> | |
3209 | TXSTS_FSPCAVAIL_SHIFT; | |
7359d482 PZ |
3210 | dev_vdbg(hsotg->dev, |
3211 | " NP Tx Req Queue Space Avail (after queue): %d\n", | |
3212 | qspcavail); | |
3213 | dev_vdbg(hsotg->dev, | |
3214 | " NP Tx FIFO Space Avail (after queue): %d\n", | |
3215 | fspcavail); | |
3216 | ||
3217 | if (more_to_do || no_queue_space || no_fifo_space) { | |
3218 | /* | |
3219 | * May need to queue more transactions as the request | |
3220 | * queue or Tx FIFO empties. Enable the non-periodic | |
3221 | * Tx FIFO empty interrupt. (Always use the half-empty | |
3222 | * level to ensure that new requests are loaded as | |
3223 | * soon as possible.) | |
3224 | */ | |
95c8bc36 | 3225 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 | 3226 | gintmsk |= GINTSTS_NPTXFEMP; |
95c8bc36 | 3227 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
3228 | } else { |
3229 | /* | |
3230 | * Disable the Tx FIFO empty interrupt since there are | |
3231 | * no more transactions that need to be queued right | |
3232 | * now. This function is called from interrupt | |
3233 | * handlers to queue more transactions as transfer | |
3234 | * states change. | |
3235 | */ | |
95c8bc36 | 3236 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 | 3237 | gintmsk &= ~GINTSTS_NPTXFEMP; |
95c8bc36 | 3238 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
3239 | } |
3240 | } | |
3241 | } | |
3242 | ||
3243 | /** | |
3244 | * dwc2_hcd_queue_transactions() - Processes the currently active host channels | |
3245 | * and queues transactions for these channels to the DWC_otg controller. Called | |
3246 | * from the HCD interrupt handler functions. | |
3247 | * | |
3248 | * @hsotg: The HCD state structure | |
3249 | * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, | |
3250 | * or both) | |
3251 | * | |
3252 | * Must be called with interrupt disabled and spinlock held | |
3253 | */ | |
3254 | void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, | |
3255 | enum dwc2_transaction_type tr_type) | |
3256 | { | |
3257 | #ifdef DWC2_DEBUG_SOF | |
3258 | dev_vdbg(hsotg->dev, "Queue Transactions\n"); | |
3259 | #endif | |
3260 | /* Process host channels associated with periodic transfers */ | |
4e50e011 DA |
3261 | if (tr_type == DWC2_TRANSACTION_PERIODIC || |
3262 | tr_type == DWC2_TRANSACTION_ALL) | |
7359d482 PZ |
3263 | dwc2_process_periodic_channels(hsotg); |
3264 | ||
3265 | /* Process host channels associated with non-periodic transfers */ | |
3266 | if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || | |
3267 | tr_type == DWC2_TRANSACTION_ALL) { | |
3268 | if (!list_empty(&hsotg->non_periodic_sched_active)) { | |
3269 | dwc2_process_non_periodic_channels(hsotg); | |
3270 | } else { | |
3271 | /* | |
3272 | * Ensure NP Tx FIFO empty interrupt is disabled when | |
3273 | * there are no non-periodic transfers to process | |
3274 | */ | |
95c8bc36 | 3275 | u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
7359d482 PZ |
3276 | |
3277 | gintmsk &= ~GINTSTS_NPTXFEMP; | |
95c8bc36 | 3278 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); |
7359d482 PZ |
3279 | } |
3280 | } | |
3281 | } | |
3282 | ||
3283 | static void dwc2_conn_id_status_change(struct work_struct *work) | |
3284 | { | |
3285 | struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, | |
3286 | wf_otg); | |
3287 | u32 count = 0; | |
3288 | u32 gotgctl; | |
5390d438 | 3289 | unsigned long flags; |
7359d482 PZ |
3290 | |
3291 | dev_dbg(hsotg->dev, "%s()\n", __func__); | |
3292 | ||
95c8bc36 | 3293 | gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); |
7359d482 PZ |
3294 | dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); |
3295 | dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", | |
3296 | !!(gotgctl & GOTGCTL_CONID_B)); | |
3297 | ||
3298 | /* B-Device connector (Device Mode) */ | |
3299 | if (gotgctl & GOTGCTL_CONID_B) { | |
531ef5eb | 3300 | dwc2_vbus_supply_exit(hsotg); |
7359d482 PZ |
3301 | /* Wait for switch to device mode */ |
3302 | dev_dbg(hsotg->dev, "connId B\n"); | |
9156a7ef CY |
3303 | if (hsotg->bus_suspended) { |
3304 | dev_info(hsotg->dev, | |
3305 | "Do port resume before switching to device mode\n"); | |
3306 | dwc2_port_resume(hsotg); | |
3307 | } | |
7359d482 PZ |
3308 | while (!dwc2_is_device_mode(hsotg)) { |
3309 | dev_info(hsotg->dev, | |
3310 | "Waiting for Peripheral Mode, Mode=%s\n", | |
3311 | dwc2_is_host_mode(hsotg) ? "Host" : | |
3312 | "Peripheral"); | |
04a9db79 | 3313 | msleep(20); |
fc30c4bb JS |
3314 | /* |
3315 | * Sometimes the initial GOTGCTRL read is wrong, so | |
3316 | * check it again and jump to host mode if that was | |
3317 | * the case. | |
3318 | */ | |
3319 | gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); | |
3320 | if (!(gotgctl & GOTGCTL_CONID_B)) | |
3321 | goto host; | |
7359d482 PZ |
3322 | if (++count > 250) |
3323 | break; | |
3324 | } | |
3325 | if (count > 250) | |
3326 | dev_err(hsotg->dev, | |
de9169a1 | 3327 | "Connection id status change timed out\n"); |
7359d482 | 3328 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
0fe239bc | 3329 | dwc2_core_init(hsotg, false); |
7359d482 | 3330 | dwc2_enable_global_interrupts(hsotg); |
5390d438 | 3331 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3332 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
5390d438 | 3333 | spin_unlock_irqrestore(&hsotg->lock, flags); |
66e77a24 RK |
3334 | /* Enable ACG feature in device mode,if supported */ |
3335 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 3336 | dwc2_hsotg_core_connect(hsotg); |
7359d482 | 3337 | } else { |
fc30c4bb | 3338 | host: |
7359d482 PZ |
3339 | /* A-Device connector (Host Mode) */ |
3340 | dev_dbg(hsotg->dev, "connId A\n"); | |
3341 | while (!dwc2_is_host_mode(hsotg)) { | |
3342 | dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", | |
3343 | dwc2_is_host_mode(hsotg) ? | |
3344 | "Host" : "Peripheral"); | |
04a9db79 | 3345 | msleep(20); |
7359d482 PZ |
3346 | if (++count > 250) |
3347 | break; | |
3348 | } | |
3349 | if (count > 250) | |
3350 | dev_err(hsotg->dev, | |
de9169a1 | 3351 | "Connection id status change timed out\n"); |
7359d482 | 3352 | |
d2471d4a JS |
3353 | spin_lock_irqsave(&hsotg->lock, flags); |
3354 | dwc2_hsotg_disconnect(hsotg); | |
3355 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3356 | ||
3357 | hsotg->op_state = OTG_STATE_A_HOST; | |
7359d482 | 3358 | /* Initialize the Core for Host mode */ |
0fe239bc | 3359 | dwc2_core_init(hsotg, false); |
7359d482 PZ |
3360 | dwc2_enable_global_interrupts(hsotg); |
3361 | dwc2_hcd_start(hsotg); | |
3362 | } | |
3363 | } | |
3364 | ||
e99e88a9 | 3365 | static void dwc2_wakeup_detected(struct timer_list *t) |
7359d482 | 3366 | { |
e99e88a9 | 3367 | struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); |
7359d482 PZ |
3368 | u32 hprt0; |
3369 | ||
3370 | dev_dbg(hsotg->dev, "%s()\n", __func__); | |
3371 | ||
3372 | /* | |
3373 | * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms | |
3374 | * so that OPT tests pass with all PHYs.) | |
3375 | */ | |
3376 | hprt0 = dwc2_read_hprt0(hsotg); | |
3377 | dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); | |
3378 | hprt0 &= ~HPRT0_RES; | |
95c8bc36 | 3379 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 | 3380 | dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", |
95c8bc36 | 3381 | dwc2_readl(hsotg->regs + HPRT0)); |
7359d482 PZ |
3382 | |
3383 | dwc2_hcd_rem_wakeup(hsotg); | |
fdb09b3e | 3384 | hsotg->bus_suspended = false; |
7359d482 PZ |
3385 | |
3386 | /* Change to L0 state */ | |
3387 | hsotg->lx_state = DWC2_L0; | |
3388 | } | |
3389 | ||
3390 | static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) | |
3391 | { | |
3392 | struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); | |
3393 | ||
3394 | return hcd->self.b_hnp_enable; | |
3395 | } | |
3396 | ||
3397 | /* Must NOT be called with interrupt disabled or spinlock held */ | |
3398 | static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) | |
3399 | { | |
3400 | unsigned long flags; | |
3401 | u32 hprt0; | |
3402 | u32 pcgctl; | |
3403 | u32 gotgctl; | |
3404 | ||
3405 | dev_dbg(hsotg->dev, "%s()\n", __func__); | |
3406 | ||
3407 | spin_lock_irqsave(&hsotg->lock, flags); | |
3408 | ||
3409 | if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { | |
95c8bc36 | 3410 | gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); |
7359d482 | 3411 | gotgctl |= GOTGCTL_HSTSETHNPEN; |
95c8bc36 | 3412 | dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); |
7359d482 PZ |
3413 | hsotg->op_state = OTG_STATE_A_SUSPEND; |
3414 | } | |
3415 | ||
3416 | hprt0 = dwc2_read_hprt0(hsotg); | |
3417 | hprt0 |= HPRT0_SUSP; | |
95c8bc36 | 3418 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 | 3419 | |
fdb09b3e | 3420 | hsotg->bus_suspended = true; |
7359d482 | 3421 | |
a2a23d3f | 3422 | /* |
41ba9b9b | 3423 | * If power_down is supported, Phy clock will be suspended |
a2a23d3f GH |
3424 | * after registers are backuped. |
3425 | */ | |
41ba9b9b | 3426 | if (!hsotg->params.power_down) { |
a2a23d3f GH |
3427 | /* Suspend the Phy Clock */ |
3428 | pcgctl = dwc2_readl(hsotg->regs + PCGCTL); | |
3429 | pcgctl |= PCGCTL_STOPPCLK; | |
3430 | dwc2_writel(pcgctl, hsotg->regs + PCGCTL); | |
3431 | udelay(10); | |
3432 | } | |
7359d482 PZ |
3433 | |
3434 | /* For HNP the bus must be suspended for at least 200ms */ | |
3435 | if (dwc2_host_is_b_hnp_enabled(hsotg)) { | |
95c8bc36 | 3436 | pcgctl = dwc2_readl(hsotg->regs + PCGCTL); |
7359d482 | 3437 | pcgctl &= ~PCGCTL_STOPPCLK; |
95c8bc36 | 3438 | dwc2_writel(pcgctl, hsotg->regs + PCGCTL); |
7359d482 PZ |
3439 | |
3440 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3441 | ||
04a9db79 | 3442 | msleep(200); |
7359d482 PZ |
3443 | } else { |
3444 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3445 | } | |
3446 | } | |
3447 | ||
30db103c GH |
3448 | /* Must NOT be called with interrupt disabled or spinlock held */ |
3449 | static void dwc2_port_resume(struct dwc2_hsotg *hsotg) | |
3450 | { | |
3451 | unsigned long flags; | |
3452 | u32 hprt0; | |
3453 | u32 pcgctl; | |
3454 | ||
4d273c2a DA |
3455 | spin_lock_irqsave(&hsotg->lock, flags); |
3456 | ||
a2a23d3f | 3457 | /* |
41ba9b9b | 3458 | * If power_down is supported, Phy clock is already resumed |
a2a23d3f GH |
3459 | * after registers restore. |
3460 | */ | |
41ba9b9b | 3461 | if (!hsotg->params.power_down) { |
a2a23d3f GH |
3462 | pcgctl = dwc2_readl(hsotg->regs + PCGCTL); |
3463 | pcgctl &= ~PCGCTL_STOPPCLK; | |
3464 | dwc2_writel(pcgctl, hsotg->regs + PCGCTL); | |
4d273c2a | 3465 | spin_unlock_irqrestore(&hsotg->lock, flags); |
04a9db79 | 3466 | msleep(20); |
4d273c2a | 3467 | spin_lock_irqsave(&hsotg->lock, flags); |
a2a23d3f | 3468 | } |
30db103c | 3469 | |
30db103c GH |
3470 | hprt0 = dwc2_read_hprt0(hsotg); |
3471 | hprt0 |= HPRT0_RES; | |
3472 | hprt0 &= ~HPRT0_SUSP; | |
3473 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
3474 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3475 | ||
3476 | msleep(USB_RESUME_TIMEOUT); | |
3477 | ||
3478 | spin_lock_irqsave(&hsotg->lock, flags); | |
3479 | hprt0 = dwc2_read_hprt0(hsotg); | |
3480 | hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); | |
3481 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
fdb09b3e | 3482 | hsotg->bus_suspended = false; |
30db103c GH |
3483 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3484 | } | |
3485 | ||
7359d482 PZ |
3486 | /* Handles hub class-specific requests */ |
3487 | static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, | |
3488 | u16 wvalue, u16 windex, char *buf, u16 wlength) | |
3489 | { | |
3490 | struct usb_hub_descriptor *hub_desc; | |
3491 | int retval = 0; | |
3492 | u32 hprt0; | |
3493 | u32 port_status; | |
3494 | u32 speed; | |
3495 | u32 pcgctl; | |
3496 | ||
3497 | switch (typereq) { | |
3498 | case ClearHubFeature: | |
3499 | dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); | |
3500 | ||
3501 | switch (wvalue) { | |
3502 | case C_HUB_LOCAL_POWER: | |
3503 | case C_HUB_OVER_CURRENT: | |
3504 | /* Nothing required here */ | |
3505 | break; | |
3506 | ||
3507 | default: | |
3508 | retval = -EINVAL; | |
3509 | dev_err(hsotg->dev, | |
3510 | "ClearHubFeature request %1xh unknown\n", | |
3511 | wvalue); | |
3512 | } | |
3513 | break; | |
3514 | ||
3515 | case ClearPortFeature: | |
3516 | if (wvalue != USB_PORT_FEAT_L1) | |
3517 | if (!windex || windex > 1) | |
3518 | goto error; | |
3519 | switch (wvalue) { | |
3520 | case USB_PORT_FEAT_ENABLE: | |
3521 | dev_dbg(hsotg->dev, | |
3522 | "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); | |
3523 | hprt0 = dwc2_read_hprt0(hsotg); | |
3524 | hprt0 |= HPRT0_ENA; | |
95c8bc36 | 3525 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
3526 | break; |
3527 | ||
3528 | case USB_PORT_FEAT_SUSPEND: | |
3529 | dev_dbg(hsotg->dev, | |
3530 | "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); | |
b0bb9bb6 | 3531 | |
f260b250 VM |
3532 | if (hsotg->bus_suspended) { |
3533 | if (hsotg->hibernated) | |
3534 | dwc2_exit_hibernation(hsotg, 0, 0, 1); | |
3535 | else | |
3536 | dwc2_port_resume(hsotg); | |
3537 | } | |
7359d482 PZ |
3538 | break; |
3539 | ||
3540 | case USB_PORT_FEAT_POWER: | |
3541 | dev_dbg(hsotg->dev, | |
3542 | "ClearPortFeature USB_PORT_FEAT_POWER\n"); | |
3543 | hprt0 = dwc2_read_hprt0(hsotg); | |
3544 | hprt0 &= ~HPRT0_PWR; | |
95c8bc36 | 3545 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
3546 | break; |
3547 | ||
3548 | case USB_PORT_FEAT_INDICATOR: | |
3549 | dev_dbg(hsotg->dev, | |
3550 | "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); | |
3551 | /* Port indicator not supported */ | |
3552 | break; | |
3553 | ||
3554 | case USB_PORT_FEAT_C_CONNECTION: | |
3555 | /* | |
3556 | * Clears driver's internal Connect Status Change flag | |
3557 | */ | |
3558 | dev_dbg(hsotg->dev, | |
3559 | "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); | |
3560 | hsotg->flags.b.port_connect_status_change = 0; | |
3561 | break; | |
3562 | ||
3563 | case USB_PORT_FEAT_C_RESET: | |
3564 | /* Clears driver's internal Port Reset Change flag */ | |
3565 | dev_dbg(hsotg->dev, | |
3566 | "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); | |
3567 | hsotg->flags.b.port_reset_change = 0; | |
3568 | break; | |
3569 | ||
3570 | case USB_PORT_FEAT_C_ENABLE: | |
3571 | /* | |
3572 | * Clears the driver's internal Port Enable/Disable | |
3573 | * Change flag | |
3574 | */ | |
3575 | dev_dbg(hsotg->dev, | |
3576 | "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); | |
3577 | hsotg->flags.b.port_enable_change = 0; | |
3578 | break; | |
3579 | ||
3580 | case USB_PORT_FEAT_C_SUSPEND: | |
3581 | /* | |
3582 | * Clears the driver's internal Port Suspend Change | |
3583 | * flag, which is set when resume signaling on the host | |
3584 | * port is complete | |
3585 | */ | |
3586 | dev_dbg(hsotg->dev, | |
3587 | "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); | |
3588 | hsotg->flags.b.port_suspend_change = 0; | |
3589 | break; | |
3590 | ||
3591 | case USB_PORT_FEAT_C_PORT_L1: | |
3592 | dev_dbg(hsotg->dev, | |
3593 | "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); | |
3594 | hsotg->flags.b.port_l1_change = 0; | |
3595 | break; | |
3596 | ||
3597 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
3598 | dev_dbg(hsotg->dev, | |
3599 | "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); | |
3600 | hsotg->flags.b.port_over_current_change = 0; | |
3601 | break; | |
3602 | ||
3603 | default: | |
3604 | retval = -EINVAL; | |
3605 | dev_err(hsotg->dev, | |
3606 | "ClearPortFeature request %1xh unknown or unsupported\n", | |
3607 | wvalue); | |
3608 | } | |
3609 | break; | |
3610 | ||
3611 | case GetHubDescriptor: | |
3612 | dev_dbg(hsotg->dev, "GetHubDescriptor\n"); | |
3613 | hub_desc = (struct usb_hub_descriptor *)buf; | |
3614 | hub_desc->bDescLength = 9; | |
a5dd0395 | 3615 | hub_desc->bDescriptorType = USB_DT_HUB; |
7359d482 | 3616 | hub_desc->bNbrPorts = 1; |
3d040de8 SS |
3617 | hub_desc->wHubCharacteristics = |
3618 | cpu_to_le16(HUB_CHAR_COMMON_LPSM | | |
3619 | HUB_CHAR_INDV_PORT_OCPM); | |
7359d482 PZ |
3620 | hub_desc->bPwrOn2PwrGood = 1; |
3621 | hub_desc->bHubContrCurrent = 0; | |
3622 | hub_desc->u.hs.DeviceRemovable[0] = 0; | |
3623 | hub_desc->u.hs.DeviceRemovable[1] = 0xff; | |
3624 | break; | |
3625 | ||
3626 | case GetHubStatus: | |
3627 | dev_dbg(hsotg->dev, "GetHubStatus\n"); | |
3628 | memset(buf, 0, 4); | |
3629 | break; | |
3630 | ||
3631 | case GetPortStatus: | |
b8313417 PZ |
3632 | dev_vdbg(hsotg->dev, |
3633 | "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, | |
3634 | hsotg->flags.d32); | |
7359d482 PZ |
3635 | if (!windex || windex > 1) |
3636 | goto error; | |
3637 | ||
3638 | port_status = 0; | |
3639 | if (hsotg->flags.b.port_connect_status_change) | |
3640 | port_status |= USB_PORT_STAT_C_CONNECTION << 16; | |
3641 | if (hsotg->flags.b.port_enable_change) | |
3642 | port_status |= USB_PORT_STAT_C_ENABLE << 16; | |
3643 | if (hsotg->flags.b.port_suspend_change) | |
3644 | port_status |= USB_PORT_STAT_C_SUSPEND << 16; | |
3645 | if (hsotg->flags.b.port_l1_change) | |
3646 | port_status |= USB_PORT_STAT_C_L1 << 16; | |
3647 | if (hsotg->flags.b.port_reset_change) | |
3648 | port_status |= USB_PORT_STAT_C_RESET << 16; | |
3649 | if (hsotg->flags.b.port_over_current_change) { | |
3650 | dev_warn(hsotg->dev, "Overcurrent change detected\n"); | |
3651 | port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
3652 | } | |
3653 | ||
3654 | if (!hsotg->flags.b.port_connect_status) { | |
3655 | /* | |
3656 | * The port is disconnected, which means the core is | |
3657 | * either in device mode or it soon will be. Just | |
3658 | * return 0's for the remainder of the port status | |
3659 | * since the port register can't be read if the core | |
3660 | * is in device mode. | |
3661 | */ | |
3662 | *(__le32 *)buf = cpu_to_le32(port_status); | |
3663 | break; | |
3664 | } | |
3665 | ||
95c8bc36 | 3666 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); |
b8313417 | 3667 | dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); |
7359d482 PZ |
3668 | |
3669 | if (hprt0 & HPRT0_CONNSTS) | |
3670 | port_status |= USB_PORT_STAT_CONNECTION; | |
3671 | if (hprt0 & HPRT0_ENA) | |
3672 | port_status |= USB_PORT_STAT_ENABLE; | |
3673 | if (hprt0 & HPRT0_SUSP) | |
3674 | port_status |= USB_PORT_STAT_SUSPEND; | |
3675 | if (hprt0 & HPRT0_OVRCURRACT) | |
3676 | port_status |= USB_PORT_STAT_OVERCURRENT; | |
3677 | if (hprt0 & HPRT0_RST) | |
3678 | port_status |= USB_PORT_STAT_RESET; | |
3679 | if (hprt0 & HPRT0_PWR) | |
3680 | port_status |= USB_PORT_STAT_POWER; | |
3681 | ||
f9234633 | 3682 | speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; |
7359d482 PZ |
3683 | if (speed == HPRT0_SPD_HIGH_SPEED) |
3684 | port_status |= USB_PORT_STAT_HIGH_SPEED; | |
3685 | else if (speed == HPRT0_SPD_LOW_SPEED) | |
3686 | port_status |= USB_PORT_STAT_LOW_SPEED; | |
3687 | ||
3688 | if (hprt0 & HPRT0_TSTCTL_MASK) | |
3689 | port_status |= USB_PORT_STAT_TEST; | |
3690 | /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ | |
3691 | ||
bea8e86c | 3692 | if (hsotg->params.dma_desc_fs_enable) { |
fbb9e22b MYK |
3693 | /* |
3694 | * Enable descriptor DMA only if a full speed | |
3695 | * device is connected. | |
3696 | */ | |
3697 | if (hsotg->new_connection && | |
3698 | ((port_status & | |
3699 | (USB_PORT_STAT_CONNECTION | | |
3700 | USB_PORT_STAT_HIGH_SPEED | | |
3701 | USB_PORT_STAT_LOW_SPEED)) == | |
3702 | USB_PORT_STAT_CONNECTION)) { | |
3703 | u32 hcfg; | |
3704 | ||
3705 | dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); | |
95832c00 | 3706 | hsotg->params.dma_desc_enable = true; |
fbb9e22b MYK |
3707 | hcfg = dwc2_readl(hsotg->regs + HCFG); |
3708 | hcfg |= HCFG_DESCDMA; | |
3709 | dwc2_writel(hcfg, hsotg->regs + HCFG); | |
3710 | hsotg->new_connection = false; | |
3711 | } | |
3712 | } | |
3713 | ||
b8313417 | 3714 | dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); |
7359d482 PZ |
3715 | *(__le32 *)buf = cpu_to_le32(port_status); |
3716 | break; | |
3717 | ||
3718 | case SetHubFeature: | |
3719 | dev_dbg(hsotg->dev, "SetHubFeature\n"); | |
3720 | /* No HUB features supported */ | |
3721 | break; | |
3722 | ||
3723 | case SetPortFeature: | |
3724 | dev_dbg(hsotg->dev, "SetPortFeature\n"); | |
3725 | if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) | |
3726 | goto error; | |
3727 | ||
3728 | if (!hsotg->flags.b.port_connect_status) { | |
3729 | /* | |
3730 | * The port is disconnected, which means the core is | |
3731 | * either in device mode or it soon will be. Just | |
3732 | * return without doing anything since the port | |
3733 | * register can't be written if the core is in device | |
3734 | * mode. | |
3735 | */ | |
3736 | break; | |
3737 | } | |
3738 | ||
3739 | switch (wvalue) { | |
3740 | case USB_PORT_FEAT_SUSPEND: | |
3741 | dev_dbg(hsotg->dev, | |
3742 | "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); | |
3743 | if (windex != hsotg->otg_port) | |
3744 | goto error; | |
f260b250 VM |
3745 | if (hsotg->params.power_down == 2) |
3746 | dwc2_enter_hibernation(hsotg, 1); | |
3747 | else | |
3748 | dwc2_port_suspend(hsotg, windex); | |
7359d482 PZ |
3749 | break; |
3750 | ||
3751 | case USB_PORT_FEAT_POWER: | |
3752 | dev_dbg(hsotg->dev, | |
3753 | "SetPortFeature - USB_PORT_FEAT_POWER\n"); | |
3754 | hprt0 = dwc2_read_hprt0(hsotg); | |
3755 | hprt0 |= HPRT0_PWR; | |
95c8bc36 | 3756 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
3757 | break; |
3758 | ||
3759 | case USB_PORT_FEAT_RESET: | |
f260b250 VM |
3760 | if (hsotg->params.power_down == 2 && |
3761 | hsotg->hibernated) | |
3762 | dwc2_exit_hibernation(hsotg, 0, 1, 1); | |
7359d482 PZ |
3763 | hprt0 = dwc2_read_hprt0(hsotg); |
3764 | dev_dbg(hsotg->dev, | |
3765 | "SetPortFeature - USB_PORT_FEAT_RESET\n"); | |
95c8bc36 | 3766 | pcgctl = dwc2_readl(hsotg->regs + PCGCTL); |
7359d482 | 3767 | pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); |
95c8bc36 | 3768 | dwc2_writel(pcgctl, hsotg->regs + PCGCTL); |
7359d482 | 3769 | /* ??? Original driver does this */ |
95c8bc36 | 3770 | dwc2_writel(0, hsotg->regs + PCGCTL); |
7359d482 PZ |
3771 | |
3772 | hprt0 = dwc2_read_hprt0(hsotg); | |
3773 | /* Clear suspend bit if resetting from suspend state */ | |
3774 | hprt0 &= ~HPRT0_SUSP; | |
3775 | ||
3776 | /* | |
3777 | * When B-Host the Port reset bit is set in the Start | |
3778 | * HCD Callback function, so that the reset is started | |
3779 | * within 1ms of the HNP success interrupt | |
3780 | */ | |
3781 | if (!dwc2_hcd_is_b_host(hsotg)) { | |
3782 | hprt0 |= HPRT0_PWR | HPRT0_RST; | |
3783 | dev_dbg(hsotg->dev, | |
3784 | "In host mode, hprt0=%08x\n", hprt0); | |
95c8bc36 | 3785 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
3786 | } |
3787 | ||
3788 | /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ | |
04a9db79 | 3789 | msleep(50); |
7359d482 | 3790 | hprt0 &= ~HPRT0_RST; |
95c8bc36 | 3791 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 PZ |
3792 | hsotg->lx_state = DWC2_L0; /* Now back to On state */ |
3793 | break; | |
3794 | ||
3795 | case USB_PORT_FEAT_INDICATOR: | |
3796 | dev_dbg(hsotg->dev, | |
3797 | "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); | |
3798 | /* Not supported */ | |
3799 | break; | |
3800 | ||
96d480e6 JL |
3801 | case USB_PORT_FEAT_TEST: |
3802 | hprt0 = dwc2_read_hprt0(hsotg); | |
3803 | dev_dbg(hsotg->dev, | |
3804 | "SetPortFeature - USB_PORT_FEAT_TEST\n"); | |
3805 | hprt0 &= ~HPRT0_TSTCTL_MASK; | |
3806 | hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; | |
95c8bc36 | 3807 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
96d480e6 JL |
3808 | break; |
3809 | ||
7359d482 PZ |
3810 | default: |
3811 | retval = -EINVAL; | |
3812 | dev_err(hsotg->dev, | |
3813 | "SetPortFeature %1xh unknown or unsupported\n", | |
3814 | wvalue); | |
3815 | break; | |
3816 | } | |
3817 | break; | |
3818 | ||
3819 | default: | |
3820 | error: | |
3821 | retval = -EINVAL; | |
3822 | dev_dbg(hsotg->dev, | |
3823 | "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", | |
3824 | typereq, windex, wvalue); | |
3825 | break; | |
3826 | } | |
3827 | ||
3828 | return retval; | |
3829 | } | |
3830 | ||
3831 | static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) | |
3832 | { | |
3833 | int retval; | |
3834 | ||
7359d482 PZ |
3835 | if (port != 1) |
3836 | return -EINVAL; | |
3837 | ||
3838 | retval = (hsotg->flags.b.port_connect_status_change || | |
3839 | hsotg->flags.b.port_reset_change || | |
3840 | hsotg->flags.b.port_enable_change || | |
3841 | hsotg->flags.b.port_suspend_change || | |
3842 | hsotg->flags.b.port_over_current_change); | |
3843 | ||
3844 | if (retval) { | |
3845 | dev_dbg(hsotg->dev, | |
3846 | "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); | |
3847 | dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", | |
3848 | hsotg->flags.b.port_connect_status_change); | |
3849 | dev_dbg(hsotg->dev, " port_reset_change: %d\n", | |
3850 | hsotg->flags.b.port_reset_change); | |
3851 | dev_dbg(hsotg->dev, " port_enable_change: %d\n", | |
3852 | hsotg->flags.b.port_enable_change); | |
3853 | dev_dbg(hsotg->dev, " port_suspend_change: %d\n", | |
3854 | hsotg->flags.b.port_suspend_change); | |
3855 | dev_dbg(hsotg->dev, " port_over_current_change: %d\n", | |
3856 | hsotg->flags.b.port_over_current_change); | |
3857 | } | |
3858 | ||
3859 | return retval; | |
3860 | } | |
3861 | ||
3862 | int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) | |
3863 | { | |
95c8bc36 | 3864 | u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); |
7359d482 PZ |
3865 | |
3866 | #ifdef DWC2_DEBUG_SOF | |
3867 | dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", | |
d6ec53e0 | 3868 | (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); |
7359d482 | 3869 | #endif |
d6ec53e0 | 3870 | return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; |
7359d482 PZ |
3871 | } |
3872 | ||
fae4e826 DA |
3873 | int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) |
3874 | { | |
3875 | u32 hprt = dwc2_readl(hsotg->regs + HPRT0); | |
3876 | u32 hfir = dwc2_readl(hsotg->regs + HFIR); | |
3877 | u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); | |
3878 | unsigned int us_per_frame; | |
3879 | unsigned int frame_number; | |
3880 | unsigned int remaining; | |
3881 | unsigned int interval; | |
3882 | unsigned int phy_clks; | |
3883 | ||
3884 | /* High speed has 125 us per (micro) frame; others are 1 ms per */ | |
3885 | us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; | |
3886 | ||
3887 | /* Extract fields */ | |
3888 | frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; | |
3889 | remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; | |
3890 | interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; | |
3891 | ||
3892 | /* | |
3893 | * Number of phy clocks since the last tick of the frame number after | |
3894 | * "us" has passed. | |
3895 | */ | |
3896 | phy_clks = (interval - remaining) + | |
3897 | DIV_ROUND_UP(interval * us, us_per_frame); | |
3898 | ||
3899 | return dwc2_frame_num_inc(frame_number, phy_clks / interval); | |
3900 | } | |
3901 | ||
7359d482 PZ |
3902 | int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) |
3903 | { | |
6bf2e2a5 | 3904 | return hsotg->op_state == OTG_STATE_B_HOST; |
7359d482 PZ |
3905 | } |
3906 | ||
3907 | static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, | |
3908 | int iso_desc_count, | |
3909 | gfp_t mem_flags) | |
3910 | { | |
3911 | struct dwc2_hcd_urb *urb; | |
3912 | u32 size = sizeof(*urb) + iso_desc_count * | |
3913 | sizeof(struct dwc2_hcd_iso_packet_desc); | |
3914 | ||
3915 | urb = kzalloc(size, mem_flags); | |
3916 | if (urb) | |
3917 | urb->packet_count = iso_desc_count; | |
3918 | return urb; | |
3919 | } | |
3920 | ||
3921 | static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, | |
3922 | struct dwc2_hcd_urb *urb, u8 dev_addr, | |
3923 | u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) | |
3924 | { | |
b49977a6 MK |
3925 | if (dbg_perio() || |
3926 | ep_type == USB_ENDPOINT_XFER_BULK || | |
3927 | ep_type == USB_ENDPOINT_XFER_CONTROL) | |
3928 | dev_vdbg(hsotg->dev, | |
3929 | "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", | |
3930 | dev_addr, ep_num, ep_dir, ep_type, mps); | |
7359d482 PZ |
3931 | urb->pipe_info.dev_addr = dev_addr; |
3932 | urb->pipe_info.ep_num = ep_num; | |
3933 | urb->pipe_info.pipe_type = ep_type; | |
3934 | urb->pipe_info.pipe_dir = ep_dir; | |
3935 | urb->pipe_info.mps = mps; | |
3936 | } | |
3937 | ||
3938 | /* | |
3939 | * NOTE: This function will be removed once the peripheral controller code | |
3940 | * is integrated and the driver is stable | |
3941 | */ | |
3942 | void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) | |
3943 | { | |
3944 | #ifdef DEBUG | |
3945 | struct dwc2_host_chan *chan; | |
3946 | struct dwc2_hcd_urb *urb; | |
3947 | struct dwc2_qtd *qtd; | |
3948 | int num_channels; | |
3949 | u32 np_tx_status; | |
3950 | u32 p_tx_status; | |
3951 | int i; | |
3952 | ||
bea8e86c | 3953 | num_channels = hsotg->params.host_channels; |
7359d482 PZ |
3954 | dev_dbg(hsotg->dev, "\n"); |
3955 | dev_dbg(hsotg->dev, | |
3956 | "************************************************************\n"); | |
3957 | dev_dbg(hsotg->dev, "HCD State:\n"); | |
3958 | dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); | |
3959 | ||
3960 | for (i = 0; i < num_channels; i++) { | |
3961 | chan = hsotg->hc_ptr_array[i]; | |
3962 | dev_dbg(hsotg->dev, " Channel %d:\n", i); | |
3963 | dev_dbg(hsotg->dev, | |
3964 | " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", | |
3965 | chan->dev_addr, chan->ep_num, chan->ep_is_in); | |
3966 | dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); | |
3967 | dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); | |
3968 | dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); | |
3969 | dev_dbg(hsotg->dev, " data_pid_start: %d\n", | |
3970 | chan->data_pid_start); | |
3971 | dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); | |
3972 | dev_dbg(hsotg->dev, " xfer_started: %d\n", | |
3973 | chan->xfer_started); | |
3974 | dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); | |
3975 | dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", | |
3976 | (unsigned long)chan->xfer_dma); | |
3977 | dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); | |
3978 | dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); | |
3979 | dev_dbg(hsotg->dev, " halt_on_queue: %d\n", | |
3980 | chan->halt_on_queue); | |
3981 | dev_dbg(hsotg->dev, " halt_pending: %d\n", | |
3982 | chan->halt_pending); | |
3983 | dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); | |
3984 | dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); | |
3985 | dev_dbg(hsotg->dev, " complete_split: %d\n", | |
3986 | chan->complete_split); | |
3987 | dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); | |
3988 | dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); | |
3989 | dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); | |
3990 | dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); | |
3991 | dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); | |
3992 | ||
3993 | if (chan->xfer_started) { | |
3994 | u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; | |
3995 | ||
95c8bc36 AS |
3996 | hfnum = dwc2_readl(hsotg->regs + HFNUM); |
3997 | hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); | |
3998 | hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); | |
3999 | hcint = dwc2_readl(hsotg->regs + HCINT(i)); | |
4000 | hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); | |
7359d482 PZ |
4001 | dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); |
4002 | dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); | |
4003 | dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); | |
4004 | dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); | |
4005 | dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); | |
4006 | } | |
4007 | ||
4008 | if (!(chan->xfer_started && chan->qh)) | |
4009 | continue; | |
4010 | ||
4011 | list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { | |
4012 | if (!qtd->in_process) | |
4013 | break; | |
4014 | urb = qtd->urb; | |
4015 | dev_dbg(hsotg->dev, " URB Info:\n"); | |
4016 | dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", | |
4017 | qtd, urb); | |
4018 | if (urb) { | |
4019 | dev_dbg(hsotg->dev, | |
4020 | " Dev: %d, EP: %d %s\n", | |
4021 | dwc2_hcd_get_dev_addr(&urb->pipe_info), | |
4022 | dwc2_hcd_get_ep_num(&urb->pipe_info), | |
4023 | dwc2_hcd_is_pipe_in(&urb->pipe_info) ? | |
4024 | "IN" : "OUT"); | |
4025 | dev_dbg(hsotg->dev, | |
4026 | " Max packet size: %d\n", | |
4027 | dwc2_hcd_get_mps(&urb->pipe_info)); | |
4028 | dev_dbg(hsotg->dev, | |
4029 | " transfer_buffer: %p\n", | |
4030 | urb->buf); | |
157dfaac PZ |
4031 | dev_dbg(hsotg->dev, |
4032 | " transfer_dma: %08lx\n", | |
4033 | (unsigned long)urb->dma); | |
7359d482 PZ |
4034 | dev_dbg(hsotg->dev, |
4035 | " transfer_buffer_length: %d\n", | |
4036 | urb->length); | |
4037 | dev_dbg(hsotg->dev, " actual_length: %d\n", | |
4038 | urb->actual_length); | |
4039 | } | |
4040 | } | |
4041 | } | |
4042 | ||
4043 | dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", | |
4044 | hsotg->non_periodic_channels); | |
4045 | dev_dbg(hsotg->dev, " periodic_channels: %d\n", | |
4046 | hsotg->periodic_channels); | |
4047 | dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); | |
95c8bc36 | 4048 | np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); |
7359d482 | 4049 | dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", |
d6ec53e0 | 4050 | (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); |
7359d482 | 4051 | dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", |
d6ec53e0 | 4052 | (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); |
95c8bc36 | 4053 | p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); |
7359d482 | 4054 | dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", |
d6ec53e0 | 4055 | (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); |
7359d482 | 4056 | dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", |
d6ec53e0 | 4057 | (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); |
7359d482 PZ |
4058 | dwc2_dump_global_registers(hsotg); |
4059 | dwc2_dump_host_registers(hsotg); | |
4060 | dev_dbg(hsotg->dev, | |
4061 | "************************************************************\n"); | |
4062 | dev_dbg(hsotg->dev, "\n"); | |
4063 | #endif | |
4064 | } | |
4065 | ||
7359d482 PZ |
4066 | struct wrapper_priv_data { |
4067 | struct dwc2_hsotg *hsotg; | |
4068 | }; | |
4069 | ||
4070 | /* Gets the dwc2_hsotg from a usb_hcd */ | |
4071 | static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) | |
4072 | { | |
4073 | struct wrapper_priv_data *p; | |
4074 | ||
9da51974 | 4075 | p = (struct wrapper_priv_data *)&hcd->hcd_priv; |
7359d482 PZ |
4076 | return p->hsotg; |
4077 | } | |
4078 | ||
9f9f09b0 DA |
4079 | /** |
4080 | * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context | |
4081 | * | |
4082 | * This will get the dwc2_tt structure (and ttport) associated with the given | |
4083 | * context (which is really just a struct urb pointer). | |
4084 | * | |
4085 | * The first time this is called for a given TT we allocate memory for our | |
4086 | * structure. When everyone is done and has called dwc2_host_put_tt_info() | |
4087 | * then the refcount for the structure will go to 0 and we'll free it. | |
4088 | * | |
4089 | * @hsotg: The HCD state structure for the DWC OTG controller. | |
9f9f09b0 DA |
4090 | * @context: The priv pointer from a struct dwc2_hcd_urb. |
4091 | * @mem_flags: Flags for allocating memory. | |
4092 | * @ttport: We'll return this device's port number here. That's used to | |
4093 | * reference into the bitmap if we're on a multi_tt hub. | |
4094 | * | |
4095 | * Return: a pointer to a struct dwc2_tt. Don't forget to call | |
4096 | * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. | |
4097 | */ | |
4098 | ||
4099 | struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, | |
4100 | gfp_t mem_flags, int *ttport) | |
4101 | { | |
4102 | struct urb *urb = context; | |
4103 | struct dwc2_tt *dwc_tt = NULL; | |
4104 | ||
4105 | if (urb->dev->tt) { | |
4106 | *ttport = urb->dev->ttport; | |
4107 | ||
4108 | dwc_tt = urb->dev->tt->hcpriv; | |
9da51974 | 4109 | if (!dwc_tt) { |
9f9f09b0 DA |
4110 | size_t bitmap_size; |
4111 | ||
4112 | /* | |
4113 | * For single_tt we need one schedule. For multi_tt | |
4114 | * we need one per port. | |
4115 | */ | |
4116 | bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * | |
4117 | sizeof(dwc_tt->periodic_bitmaps[0]); | |
4118 | if (urb->dev->tt->multi) | |
4119 | bitmap_size *= urb->dev->tt->hub->maxchild; | |
4120 | ||
4121 | dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, | |
4122 | mem_flags); | |
9da51974 | 4123 | if (!dwc_tt) |
9f9f09b0 DA |
4124 | return NULL; |
4125 | ||
4126 | dwc_tt->usb_tt = urb->dev->tt; | |
4127 | dwc_tt->usb_tt->hcpriv = dwc_tt; | |
4128 | } | |
4129 | ||
4130 | dwc_tt->refcount++; | |
4131 | } | |
4132 | ||
4133 | return dwc_tt; | |
4134 | } | |
4135 | ||
4136 | /** | |
4137 | * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() | |
4138 | * | |
4139 | * Frees resources allocated by dwc2_host_get_tt_info() if all current holders | |
4140 | * of the structure are done. | |
4141 | * | |
4142 | * It's OK to call this with NULL. | |
4143 | * | |
4144 | * @hsotg: The HCD state structure for the DWC OTG controller. | |
4145 | * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. | |
4146 | */ | |
4147 | void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) | |
4148 | { | |
4149 | /* Model kfree and make put of NULL a no-op */ | |
9da51974 | 4150 | if (!dwc_tt) |
9f9f09b0 DA |
4151 | return; |
4152 | ||
4153 | WARN_ON(dwc_tt->refcount < 1); | |
4154 | ||
4155 | dwc_tt->refcount--; | |
4156 | if (!dwc_tt->refcount) { | |
4157 | dwc_tt->usb_tt->hcpriv = NULL; | |
4158 | kfree(dwc_tt); | |
4159 | } | |
4160 | } | |
4161 | ||
7359d482 PZ |
4162 | int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) |
4163 | { | |
4164 | struct urb *urb = context; | |
4165 | ||
4166 | return urb->dev->speed; | |
4167 | } | |
4168 | ||
4169 | static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, | |
4170 | struct urb *urb) | |
4171 | { | |
4172 | struct usb_bus *bus = hcd_to_bus(hcd); | |
4173 | ||
4174 | if (urb->interval) | |
4175 | bus->bandwidth_allocated += bw / urb->interval; | |
4176 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
4177 | bus->bandwidth_isoc_reqs++; | |
4178 | else | |
4179 | bus->bandwidth_int_reqs++; | |
4180 | } | |
4181 | ||
4182 | static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, | |
4183 | struct urb *urb) | |
4184 | { | |
4185 | struct usb_bus *bus = hcd_to_bus(hcd); | |
4186 | ||
4187 | if (urb->interval) | |
4188 | bus->bandwidth_allocated -= bw / urb->interval; | |
4189 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
4190 | bus->bandwidth_isoc_reqs--; | |
4191 | else | |
4192 | bus->bandwidth_int_reqs--; | |
4193 | } | |
4194 | ||
4195 | /* | |
4196 | * Sets the final status of an URB and returns it to the upper layer. Any | |
4197 | * required cleanup of the URB is performed. | |
4198 | * | |
4199 | * Must be called with interrupt disabled and spinlock held | |
4200 | */ | |
0d012b98 PZ |
4201 | void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, |
4202 | int status) | |
7359d482 | 4203 | { |
0d012b98 | 4204 | struct urb *urb; |
7359d482 PZ |
4205 | int i; |
4206 | ||
0d012b98 PZ |
4207 | if (!qtd) { |
4208 | dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); | |
7359d482 PZ |
4209 | return; |
4210 | } | |
4211 | ||
0d012b98 PZ |
4212 | if (!qtd->urb) { |
4213 | dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); | |
7359d482 PZ |
4214 | return; |
4215 | } | |
4216 | ||
0d012b98 PZ |
4217 | urb = qtd->urb->priv; |
4218 | if (!urb) { | |
4219 | dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); | |
4220 | return; | |
4221 | } | |
4222 | ||
4223 | urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); | |
7359d482 | 4224 | |
b49977a6 MK |
4225 | if (dbg_urb(urb)) |
4226 | dev_vdbg(hsotg->dev, | |
4227 | "%s: urb %p device %d ep %d-%s status %d actual %d\n", | |
4228 | __func__, urb, usb_pipedevice(urb->pipe), | |
4229 | usb_pipeendpoint(urb->pipe), | |
4230 | usb_pipein(urb->pipe) ? "IN" : "OUT", status, | |
4231 | urb->actual_length); | |
7359d482 | 4232 | |
7359d482 | 4233 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
0d012b98 | 4234 | urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); |
7359d482 PZ |
4235 | for (i = 0; i < urb->number_of_packets; ++i) { |
4236 | urb->iso_frame_desc[i].actual_length = | |
4237 | dwc2_hcd_urb_get_iso_desc_actual_length( | |
0d012b98 | 4238 | qtd->urb, i); |
7359d482 | 4239 | urb->iso_frame_desc[i].status = |
0d012b98 | 4240 | dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); |
7359d482 PZ |
4241 | } |
4242 | } | |
4243 | ||
fe9b1773 GH |
4244 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { |
4245 | for (i = 0; i < urb->number_of_packets; i++) | |
4246 | dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", | |
4247 | i, urb->iso_frame_desc[i].status); | |
4248 | } | |
4249 | ||
7359d482 | 4250 | urb->status = status; |
7359d482 PZ |
4251 | if (!status) { |
4252 | if ((urb->transfer_flags & URB_SHORT_NOT_OK) && | |
4253 | urb->actual_length < urb->transfer_buffer_length) | |
4254 | urb->status = -EREMOTEIO; | |
4255 | } | |
4256 | ||
4257 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || | |
4258 | usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { | |
4259 | struct usb_host_endpoint *ep = urb->ep; | |
4260 | ||
4261 | if (ep) | |
4262 | dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), | |
4263 | dwc2_hcd_get_ep_bandwidth(hsotg, ep), | |
4264 | urb); | |
4265 | } | |
4266 | ||
c9e1c907 | 4267 | usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); |
0d012b98 PZ |
4268 | urb->hcpriv = NULL; |
4269 | kfree(qtd->urb); | |
4270 | qtd->urb = NULL; | |
7359d482 | 4271 | |
7359d482 | 4272 | usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); |
7359d482 PZ |
4273 | } |
4274 | ||
4275 | /* | |
4276 | * Work queue function for starting the HCD when A-Cable is connected | |
4277 | */ | |
4278 | static void dwc2_hcd_start_func(struct work_struct *work) | |
4279 | { | |
4280 | struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, | |
4281 | start_work.work); | |
4282 | ||
4283 | dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); | |
4284 | dwc2_host_start(hsotg); | |
4285 | } | |
4286 | ||
4287 | /* | |
4288 | * Reset work queue function | |
4289 | */ | |
4290 | static void dwc2_hcd_reset_func(struct work_struct *work) | |
4291 | { | |
4292 | struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, | |
4293 | reset_work.work); | |
4a065c7b | 4294 | unsigned long flags; |
7359d482 PZ |
4295 | u32 hprt0; |
4296 | ||
4297 | dev_dbg(hsotg->dev, "USB RESET function called\n"); | |
4a065c7b DA |
4298 | |
4299 | spin_lock_irqsave(&hsotg->lock, flags); | |
4300 | ||
7359d482 PZ |
4301 | hprt0 = dwc2_read_hprt0(hsotg); |
4302 | hprt0 &= ~HPRT0_RST; | |
95c8bc36 | 4303 | dwc2_writel(hprt0, hsotg->regs + HPRT0); |
7359d482 | 4304 | hsotg->flags.b.port_reset_change = 1; |
4a065c7b DA |
4305 | |
4306 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7359d482 PZ |
4307 | } |
4308 | ||
4309 | /* | |
4310 | * ========================================================================= | |
4311 | * Linux HC Driver Functions | |
4312 | * ========================================================================= | |
4313 | */ | |
4314 | ||
4315 | /* | |
4316 | * Initializes the DWC_otg controller and its root hub and prepares it for host | |
4317 | * mode operation. Activates the root port. Returns 0 on success and a negative | |
4318 | * error code on failure. | |
4319 | */ | |
4320 | static int _dwc2_hcd_start(struct usb_hcd *hcd) | |
4321 | { | |
4322 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4323 | struct usb_bus *bus = hcd_to_bus(hcd); | |
4324 | unsigned long flags; | |
4325 | ||
4326 | dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); | |
4327 | ||
4328 | spin_lock_irqsave(&hsotg->lock, flags); | |
31927b6b | 4329 | hsotg->lx_state = DWC2_L0; |
7359d482 | 4330 | hcd->state = HC_STATE_RUNNING; |
31927b6b | 4331 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
7359d482 PZ |
4332 | |
4333 | if (dwc2_is_device_mode(hsotg)) { | |
4334 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4335 | return 0; /* why 0 ?? */ | |
4336 | } | |
4337 | ||
4338 | dwc2_hcd_reinit(hsotg); | |
4339 | ||
4340 | /* Initialize and connect root hub if one is not already attached */ | |
4341 | if (bus->root_hub) { | |
4342 | dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); | |
4343 | /* Inform the HUB driver to resume */ | |
4344 | usb_hcd_resume_root_hub(hcd); | |
4345 | } | |
4346 | ||
4347 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
531ef5eb | 4348 | |
a7ef2074 | 4349 | return dwc2_vbus_supply_init(hsotg); |
7359d482 PZ |
4350 | } |
4351 | ||
4352 | /* | |
4353 | * Halts the DWC_otg host mode operations in a clean manner. USB transfers are | |
4354 | * stopped. | |
4355 | */ | |
4356 | static void _dwc2_hcd_stop(struct usb_hcd *hcd) | |
4357 | { | |
4358 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4359 | unsigned long flags; | |
4360 | ||
5bbf6ce0 GH |
4361 | /* Turn off all host-specific interrupts */ |
4362 | dwc2_disable_host_interrupts(hsotg); | |
4363 | ||
091473ad GH |
4364 | /* Wait for interrupt processing to finish */ |
4365 | synchronize_irq(hcd->irq); | |
4366 | ||
7359d482 | 4367 | spin_lock_irqsave(&hsotg->lock, flags); |
091473ad | 4368 | /* Ensure hcd is disconnected */ |
6a659531 | 4369 | dwc2_hcd_disconnect(hsotg, true); |
7359d482 | 4370 | dwc2_hcd_stop(hsotg); |
31927b6b GH |
4371 | hsotg->lx_state = DWC2_L3; |
4372 | hcd->state = HC_STATE_HALT; | |
4373 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
7359d482 PZ |
4374 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4375 | ||
531ef5eb AD |
4376 | dwc2_vbus_supply_exit(hsotg); |
4377 | ||
7359d482 PZ |
4378 | usleep_range(1000, 3000); |
4379 | } | |
4380 | ||
99a65798 GH |
4381 | static int _dwc2_hcd_suspend(struct usb_hcd *hcd) |
4382 | { | |
4383 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
a2a23d3f GH |
4384 | unsigned long flags; |
4385 | int ret = 0; | |
4386 | u32 hprt0; | |
4387 | ||
4388 | spin_lock_irqsave(&hsotg->lock, flags); | |
4389 | ||
f367b72c MD |
4390 | if (dwc2_is_device_mode(hsotg)) |
4391 | goto unlock; | |
4392 | ||
a2a23d3f GH |
4393 | if (hsotg->lx_state != DWC2_L0) |
4394 | goto unlock; | |
4395 | ||
4396 | if (!HCD_HW_ACCESSIBLE(hcd)) | |
4397 | goto unlock; | |
4398 | ||
866932e2 JS |
4399 | if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) |
4400 | goto unlock; | |
4401 | ||
631a2310 | 4402 | if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) |
a2a23d3f GH |
4403 | goto skip_power_saving; |
4404 | ||
4405 | /* | |
4406 | * Drive USB suspend and disable port Power | |
4407 | * if usb bus is not suspended. | |
4408 | */ | |
4409 | if (!hsotg->bus_suspended) { | |
4410 | hprt0 = dwc2_read_hprt0(hsotg); | |
4411 | hprt0 |= HPRT0_SUSP; | |
4412 | hprt0 &= ~HPRT0_PWR; | |
4413 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
531ef5eb | 4414 | dwc2_vbus_supply_exit(hsotg); |
a2a23d3f GH |
4415 | } |
4416 | ||
41ba9b9b VM |
4417 | /* Enter partial_power_down */ |
4418 | ret = dwc2_enter_partial_power_down(hsotg); | |
a2a23d3f GH |
4419 | if (ret) { |
4420 | if (ret != -ENOTSUPP) | |
4421 | dev_err(hsotg->dev, | |
41ba9b9b | 4422 | "enter partial_power_down failed\n"); |
a2a23d3f GH |
4423 | goto skip_power_saving; |
4424 | } | |
4425 | ||
4426 | /* Ask phy to be suspended */ | |
4427 | if (!IS_ERR_OR_NULL(hsotg->uphy)) { | |
4428 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4429 | usb_phy_set_suspend(hsotg->uphy, true); | |
4430 | spin_lock_irqsave(&hsotg->lock, flags); | |
4431 | } | |
4432 | ||
41ba9b9b | 4433 | /* After entering partial_power_down, hardware is no more accessible */ |
a2a23d3f | 4434 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
99a65798 | 4435 | |
a2a23d3f | 4436 | skip_power_saving: |
99a65798 | 4437 | hsotg->lx_state = DWC2_L2; |
a2a23d3f GH |
4438 | unlock: |
4439 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4440 | ||
4441 | return ret; | |
99a65798 GH |
4442 | } |
4443 | ||
4444 | static int _dwc2_hcd_resume(struct usb_hcd *hcd) | |
4445 | { | |
4446 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
a2a23d3f GH |
4447 | unsigned long flags; |
4448 | int ret = 0; | |
4449 | ||
4450 | spin_lock_irqsave(&hsotg->lock, flags); | |
4451 | ||
f367b72c MD |
4452 | if (dwc2_is_device_mode(hsotg)) |
4453 | goto unlock; | |
4454 | ||
a2a23d3f GH |
4455 | if (hsotg->lx_state != DWC2_L2) |
4456 | goto unlock; | |
4457 | ||
631a2310 | 4458 | if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) { |
a2a23d3f GH |
4459 | hsotg->lx_state = DWC2_L0; |
4460 | goto unlock; | |
4461 | } | |
4462 | ||
4463 | /* | |
4464 | * Set HW accessible bit before powering on the controller | |
4465 | * since an interrupt may rise. | |
4466 | */ | |
4467 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
4468 | ||
4469 | /* | |
4470 | * Enable power if not already done. | |
4471 | * This must not be spinlocked since duration | |
4472 | * of this call is unknown. | |
4473 | */ | |
4474 | if (!IS_ERR_OR_NULL(hsotg->uphy)) { | |
4475 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4476 | usb_phy_set_suspend(hsotg->uphy, false); | |
4477 | spin_lock_irqsave(&hsotg->lock, flags); | |
4478 | } | |
4479 | ||
41ba9b9b VM |
4480 | /* Exit partial_power_down */ |
4481 | ret = dwc2_exit_partial_power_down(hsotg, true); | |
a2a23d3f | 4482 | if (ret && (ret != -ENOTSUPP)) |
41ba9b9b | 4483 | dev_err(hsotg->dev, "exit partial_power_down failed\n"); |
99a65798 GH |
4484 | |
4485 | hsotg->lx_state = DWC2_L0; | |
a2a23d3f GH |
4486 | |
4487 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4488 | ||
4489 | if (hsotg->bus_suspended) { | |
4490 | spin_lock_irqsave(&hsotg->lock, flags); | |
4491 | hsotg->flags.b.port_suspend_change = 1; | |
4492 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4493 | dwc2_port_resume(hsotg); | |
4494 | } else { | |
531ef5eb AD |
4495 | dwc2_vbus_supply_init(hsotg); |
4496 | ||
5634e016 GH |
4497 | /* Wait for controller to correctly update D+/D- level */ |
4498 | usleep_range(3000, 5000); | |
4499 | ||
a2a23d3f GH |
4500 | /* |
4501 | * Clear Port Enable and Port Status changes. | |
4502 | * Enable Port Power. | |
4503 | */ | |
4504 | dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | | |
4505 | HPRT0_ENACHG, hsotg->regs + HPRT0); | |
4506 | /* Wait for controller to detect Port Connect */ | |
5634e016 | 4507 | usleep_range(5000, 7000); |
a2a23d3f GH |
4508 | } |
4509 | ||
4510 | return ret; | |
4511 | unlock: | |
4512 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4513 | ||
4514 | return ret; | |
99a65798 GH |
4515 | } |
4516 | ||
7359d482 PZ |
4517 | /* Returns the current frame number */ |
4518 | static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) | |
4519 | { | |
4520 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4521 | ||
4522 | return dwc2_hcd_get_frame_number(hsotg); | |
4523 | } | |
4524 | ||
4525 | static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, | |
4526 | char *fn_name) | |
4527 | { | |
4528 | #ifdef VERBOSE_DEBUG | |
4529 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
efe357f4 NMG |
4530 | char *pipetype = NULL; |
4531 | char *speed = NULL; | |
7359d482 PZ |
4532 | |
4533 | dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); | |
4534 | dev_vdbg(hsotg->dev, " Device address: %d\n", | |
4535 | usb_pipedevice(urb->pipe)); | |
4536 | dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", | |
4537 | usb_pipeendpoint(urb->pipe), | |
4538 | usb_pipein(urb->pipe) ? "IN" : "OUT"); | |
4539 | ||
4540 | switch (usb_pipetype(urb->pipe)) { | |
4541 | case PIPE_CONTROL: | |
4542 | pipetype = "CONTROL"; | |
4543 | break; | |
4544 | case PIPE_BULK: | |
4545 | pipetype = "BULK"; | |
4546 | break; | |
4547 | case PIPE_INTERRUPT: | |
4548 | pipetype = "INTERRUPT"; | |
4549 | break; | |
4550 | case PIPE_ISOCHRONOUS: | |
4551 | pipetype = "ISOCHRONOUS"; | |
4552 | break; | |
7359d482 PZ |
4553 | } |
4554 | ||
4555 | dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, | |
4556 | usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? | |
4557 | "IN" : "OUT"); | |
4558 | ||
4559 | switch (urb->dev->speed) { | |
4560 | case USB_SPEED_HIGH: | |
4561 | speed = "HIGH"; | |
4562 | break; | |
4563 | case USB_SPEED_FULL: | |
4564 | speed = "FULL"; | |
4565 | break; | |
4566 | case USB_SPEED_LOW: | |
4567 | speed = "LOW"; | |
4568 | break; | |
4569 | default: | |
4570 | speed = "UNKNOWN"; | |
4571 | break; | |
4572 | } | |
4573 | ||
4574 | dev_vdbg(hsotg->dev, " Speed: %s\n", speed); | |
4575 | dev_vdbg(hsotg->dev, " Max packet size: %d\n", | |
4576 | usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); | |
4577 | dev_vdbg(hsotg->dev, " Data buffer length: %d\n", | |
4578 | urb->transfer_buffer_length); | |
157dfaac PZ |
4579 | dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", |
4580 | urb->transfer_buffer, (unsigned long)urb->transfer_dma); | |
4581 | dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", | |
4582 | urb->setup_packet, (unsigned long)urb->setup_dma); | |
7359d482 PZ |
4583 | dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); |
4584 | ||
4585 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
4586 | int i; | |
4587 | ||
4588 | for (i = 0; i < urb->number_of_packets; i++) { | |
4589 | dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); | |
4590 | dev_vdbg(hsotg->dev, " offset: %d, length %d\n", | |
4591 | urb->iso_frame_desc[i].offset, | |
4592 | urb->iso_frame_desc[i].length); | |
4593 | } | |
4594 | } | |
4595 | #endif | |
4596 | } | |
4597 | ||
4598 | /* | |
4599 | * Starts processing a USB transfer request specified by a USB Request Block | |
4600 | * (URB). mem_flags indicates the type of memory allocation to use while | |
4601 | * processing this URB. | |
4602 | */ | |
4603 | static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |
4604 | gfp_t mem_flags) | |
4605 | { | |
4606 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4607 | struct usb_host_endpoint *ep = urb->ep; | |
4608 | struct dwc2_hcd_urb *dwc2_urb; | |
4609 | int i; | |
c9e1c907 | 4610 | int retval; |
7359d482 | 4611 | int alloc_bandwidth = 0; |
7359d482 PZ |
4612 | u8 ep_type = 0; |
4613 | u32 tflags = 0; | |
4614 | void *buf; | |
4615 | unsigned long flags; | |
b58e6cee MYK |
4616 | struct dwc2_qh *qh; |
4617 | bool qh_allocated = false; | |
b5a468a6 | 4618 | struct dwc2_qtd *qtd; |
7359d482 | 4619 | |
b49977a6 MK |
4620 | if (dbg_urb(urb)) { |
4621 | dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); | |
4622 | dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); | |
4623 | } | |
7359d482 | 4624 | |
9da51974 | 4625 | if (!ep) |
7359d482 PZ |
4626 | return -EINVAL; |
4627 | ||
4628 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || | |
4629 | usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { | |
4630 | spin_lock_irqsave(&hsotg->lock, flags); | |
4631 | if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) | |
4632 | alloc_bandwidth = 1; | |
4633 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4634 | } | |
4635 | ||
4636 | switch (usb_pipetype(urb->pipe)) { | |
4637 | case PIPE_CONTROL: | |
4638 | ep_type = USB_ENDPOINT_XFER_CONTROL; | |
4639 | break; | |
4640 | case PIPE_ISOCHRONOUS: | |
4641 | ep_type = USB_ENDPOINT_XFER_ISOC; | |
4642 | break; | |
4643 | case PIPE_BULK: | |
4644 | ep_type = USB_ENDPOINT_XFER_BULK; | |
4645 | break; | |
4646 | case PIPE_INTERRUPT: | |
4647 | ep_type = USB_ENDPOINT_XFER_INT; | |
4648 | break; | |
7359d482 PZ |
4649 | } |
4650 | ||
4651 | dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, | |
4652 | mem_flags); | |
4653 | if (!dwc2_urb) | |
4654 | return -ENOMEM; | |
4655 | ||
4656 | dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), | |
4657 | usb_pipeendpoint(urb->pipe), ep_type, | |
4658 | usb_pipein(urb->pipe), | |
4659 | usb_maxpacket(urb->dev, urb->pipe, | |
4660 | !(usb_pipein(urb->pipe)))); | |
4661 | ||
4662 | buf = urb->transfer_buffer; | |
25a49445 | 4663 | |
7359d482 | 4664 | if (hcd->self.uses_dma) { |
25a49445 PZ |
4665 | if (!buf && (urb->transfer_dma & 3)) { |
4666 | dev_err(hsotg->dev, | |
4667 | "%s: unaligned transfer with no transfer_buffer", | |
4668 | __func__); | |
4669 | retval = -EINVAL; | |
33ad261a | 4670 | goto fail0; |
25a49445 | 4671 | } |
7359d482 PZ |
4672 | } |
4673 | ||
4674 | if (!(urb->transfer_flags & URB_NO_INTERRUPT)) | |
4675 | tflags |= URB_GIVEBACK_ASAP; | |
4676 | if (urb->transfer_flags & URB_ZERO_PACKET) | |
4677 | tflags |= URB_SEND_ZERO_PACKET; | |
4678 | ||
4679 | dwc2_urb->priv = urb; | |
4680 | dwc2_urb->buf = buf; | |
4681 | dwc2_urb->dma = urb->transfer_dma; | |
4682 | dwc2_urb->length = urb->transfer_buffer_length; | |
4683 | dwc2_urb->setup_packet = urb->setup_packet; | |
4684 | dwc2_urb->setup_dma = urb->setup_dma; | |
4685 | dwc2_urb->flags = tflags; | |
4686 | dwc2_urb->interval = urb->interval; | |
4687 | dwc2_urb->status = -EINPROGRESS; | |
4688 | ||
4689 | for (i = 0; i < urb->number_of_packets; ++i) | |
4690 | dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, | |
4691 | urb->iso_frame_desc[i].offset, | |
4692 | urb->iso_frame_desc[i].length); | |
4693 | ||
4694 | urb->hcpriv = dwc2_urb; | |
9da51974 | 4695 | qh = (struct dwc2_qh *)ep->hcpriv; |
b58e6cee MYK |
4696 | /* Create QH for the endpoint if it doesn't exist */ |
4697 | if (!qh) { | |
4698 | qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); | |
4699 | if (!qh) { | |
4700 | retval = -ENOMEM; | |
4701 | goto fail0; | |
4702 | } | |
4703 | ep->hcpriv = qh; | |
4704 | qh_allocated = true; | |
4705 | } | |
c9e1c907 | 4706 | |
b5a468a6 MYK |
4707 | qtd = kzalloc(sizeof(*qtd), mem_flags); |
4708 | if (!qtd) { | |
4709 | retval = -ENOMEM; | |
4710 | goto fail1; | |
4711 | } | |
4712 | ||
c9e1c907 PZ |
4713 | spin_lock_irqsave(&hsotg->lock, flags); |
4714 | retval = usb_hcd_link_urb_to_ep(hcd, urb); | |
c9e1c907 | 4715 | if (retval) |
b5a468a6 | 4716 | goto fail2; |
c9e1c907 | 4717 | |
b5a468a6 | 4718 | retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); |
c9e1c907 | 4719 | if (retval) |
b5a468a6 | 4720 | goto fail3; |
c9e1c907 PZ |
4721 | |
4722 | if (alloc_bandwidth) { | |
c9e1c907 PZ |
4723 | dwc2_allocate_bus_bandwidth(hcd, |
4724 | dwc2_hcd_get_ep_bandwidth(hsotg, ep), | |
4725 | urb); | |
7359d482 PZ |
4726 | } |
4727 | ||
33ad261a GH |
4728 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4729 | ||
c9e1c907 PZ |
4730 | return 0; |
4731 | ||
b5a468a6 | 4732 | fail3: |
c9e1c907 PZ |
4733 | dwc2_urb->priv = NULL; |
4734 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
16e80218 DA |
4735 | if (qh_allocated && qh->channel && qh->channel->qh == qh) |
4736 | qh->channel->qh = NULL; | |
b5a468a6 | 4737 | fail2: |
33ad261a | 4738 | spin_unlock_irqrestore(&hsotg->lock, flags); |
c9e1c907 | 4739 | urb->hcpriv = NULL; |
b5a468a6 | 4740 | kfree(qtd); |
b0d65902 | 4741 | qtd = NULL; |
b5a468a6 | 4742 | fail1: |
b58e6cee MYK |
4743 | if (qh_allocated) { |
4744 | struct dwc2_qtd *qtd2, *qtd2_tmp; | |
4745 | ||
4746 | ep->hcpriv = NULL; | |
4747 | dwc2_hcd_qh_unlink(hsotg, qh); | |
4748 | /* Free each QTD in the QH's QTD list */ | |
4749 | list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, | |
9da51974 | 4750 | qtd_list_entry) |
b58e6cee MYK |
4751 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); |
4752 | dwc2_hcd_qh_free(hsotg, qh); | |
4753 | } | |
33ad261a | 4754 | fail0: |
c9e1c907 PZ |
4755 | kfree(dwc2_urb); |
4756 | ||
7359d482 PZ |
4757 | return retval; |
4758 | } | |
4759 | ||
4760 | /* | |
4761 | * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. | |
4762 | */ | |
4763 | static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | |
4764 | int status) | |
4765 | { | |
4766 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
c9e1c907 | 4767 | int rc; |
7359d482 PZ |
4768 | unsigned long flags; |
4769 | ||
4770 | dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); | |
4771 | dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); | |
4772 | ||
4773 | spin_lock_irqsave(&hsotg->lock, flags); | |
4774 | ||
c9e1c907 PZ |
4775 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
4776 | if (rc) | |
4777 | goto out; | |
4778 | ||
7359d482 PZ |
4779 | if (!urb->hcpriv) { |
4780 | dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); | |
4781 | goto out; | |
4782 | } | |
4783 | ||
4784 | rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); | |
4785 | ||
c9e1c907 PZ |
4786 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
4787 | ||
7359d482 PZ |
4788 | kfree(urb->hcpriv); |
4789 | urb->hcpriv = NULL; | |
4790 | ||
4791 | /* Higher layer software sets URB status */ | |
4792 | spin_unlock(&hsotg->lock); | |
4793 | usb_hcd_giveback_urb(hcd, urb, status); | |
4794 | spin_lock(&hsotg->lock); | |
4795 | ||
4796 | dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); | |
4797 | dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); | |
4798 | out: | |
4799 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4800 | ||
4801 | return rc; | |
4802 | } | |
4803 | ||
4804 | /* | |
4805 | * Frees resources in the DWC_otg controller related to a given endpoint. Also | |
4806 | * clears state in the HCD related to the endpoint. Any URBs for the endpoint | |
4807 | * must already be dequeued. | |
4808 | */ | |
4809 | static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, | |
4810 | struct usb_host_endpoint *ep) | |
4811 | { | |
4812 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4813 | ||
4814 | dev_dbg(hsotg->dev, | |
4815 | "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", | |
4816 | ep->desc.bEndpointAddress, ep->hcpriv); | |
4817 | dwc2_hcd_endpoint_disable(hsotg, ep, 250); | |
4818 | } | |
4819 | ||
4820 | /* | |
4821 | * Resets endpoint specific parameter values, in current version used to reset | |
4822 | * the data toggle (as a WA). This function can be called from usb_clear_halt | |
4823 | * routine. | |
4824 | */ | |
4825 | static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, | |
4826 | struct usb_host_endpoint *ep) | |
4827 | { | |
4828 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
7359d482 PZ |
4829 | unsigned long flags; |
4830 | ||
4831 | dev_dbg(hsotg->dev, | |
4832 | "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", | |
4833 | ep->desc.bEndpointAddress); | |
4834 | ||
7359d482 | 4835 | spin_lock_irqsave(&hsotg->lock, flags); |
7359d482 | 4836 | dwc2_hcd_endpoint_reset(hsotg, ep); |
7359d482 PZ |
4837 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4838 | } | |
4839 | ||
4840 | /* | |
4841 | * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if | |
4842 | * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid | |
4843 | * interrupt. | |
4844 | * | |
4845 | * This function is called by the USB core when an interrupt occurs | |
4846 | */ | |
4847 | static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) | |
4848 | { | |
4849 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
7359d482 | 4850 | |
ca18f4a6 | 4851 | return dwc2_handle_hcd_intr(hsotg); |
7359d482 PZ |
4852 | } |
4853 | ||
4854 | /* | |
4855 | * Creates Status Change bitmap for the root hub and root port. The bitmap is | |
4856 | * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 | |
4857 | * is the status change indicator for the single root port. Returns 1 if either | |
4858 | * change indicator is 1, otherwise returns 0. | |
4859 | */ | |
4860 | static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) | |
4861 | { | |
4862 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4863 | ||
4864 | buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; | |
4865 | return buf[0] != 0; | |
4866 | } | |
4867 | ||
4868 | /* Handles hub class-specific requests */ | |
4869 | static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, | |
4870 | u16 windex, char *buf, u16 wlength) | |
4871 | { | |
4872 | int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, | |
4873 | wvalue, windex, buf, wlength); | |
4874 | return retval; | |
4875 | } | |
4876 | ||
4877 | /* Handles hub TT buffer clear completions */ | |
4878 | static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, | |
4879 | struct usb_host_endpoint *ep) | |
4880 | { | |
4881 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4882 | struct dwc2_qh *qh; | |
4883 | unsigned long flags; | |
4884 | ||
4885 | qh = ep->hcpriv; | |
4886 | if (!qh) | |
4887 | return; | |
4888 | ||
4889 | spin_lock_irqsave(&hsotg->lock, flags); | |
4890 | qh->tt_buffer_dirty = 0; | |
4891 | ||
4892 | if (hsotg->flags.b.port_connect_status) | |
4893 | dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); | |
4894 | ||
4895 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4896 | } | |
4897 | ||
ca8b0332 CY |
4898 | /* |
4899 | * HPRT0_SPD_HIGH_SPEED: high speed | |
4900 | * HPRT0_SPD_FULL_SPEED: full speed | |
4901 | */ | |
4902 | static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) | |
4903 | { | |
4904 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4905 | ||
4906 | if (hsotg->params.speed == speed) | |
4907 | return; | |
4908 | ||
4909 | hsotg->params.speed = speed; | |
4910 | queue_work(hsotg->wq_otg, &hsotg->wf_otg); | |
4911 | } | |
4912 | ||
4913 | static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
4914 | { | |
4915 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4916 | ||
4917 | if (!hsotg->params.change_speed_quirk) | |
4918 | return; | |
4919 | ||
4920 | /* | |
4921 | * On removal, set speed to default high-speed. | |
4922 | */ | |
4923 | if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && | |
4924 | udev->parent->speed < USB_SPEED_HIGH) { | |
4925 | dev_info(hsotg->dev, "Set speed to default high-speed\n"); | |
4926 | dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); | |
4927 | } | |
4928 | } | |
4929 | ||
4930 | static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) | |
4931 | { | |
4932 | struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); | |
4933 | ||
4934 | if (!hsotg->params.change_speed_quirk) | |
4935 | return 0; | |
4936 | ||
4937 | if (udev->speed == USB_SPEED_HIGH) { | |
4938 | dev_info(hsotg->dev, "Set speed to high-speed\n"); | |
4939 | dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); | |
4940 | } else if ((udev->speed == USB_SPEED_FULL || | |
4941 | udev->speed == USB_SPEED_LOW)) { | |
4942 | /* | |
4943 | * Change speed setting to full-speed if there's | |
4944 | * a full-speed or low-speed device plugged in. | |
4945 | */ | |
4946 | dev_info(hsotg->dev, "Set speed to full-speed\n"); | |
4947 | dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); | |
4948 | } | |
4949 | ||
4950 | return 0; | |
4951 | } | |
4952 | ||
7359d482 PZ |
4953 | static struct hc_driver dwc2_hc_driver = { |
4954 | .description = "dwc2_hsotg", | |
4955 | .product_desc = "DWC OTG Controller", | |
4956 | .hcd_priv_size = sizeof(struct wrapper_priv_data), | |
4957 | ||
4958 | .irq = _dwc2_hcd_irq, | |
8add17cf | 4959 | .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, |
7359d482 PZ |
4960 | |
4961 | .start = _dwc2_hcd_start, | |
4962 | .stop = _dwc2_hcd_stop, | |
4963 | .urb_enqueue = _dwc2_hcd_urb_enqueue, | |
4964 | .urb_dequeue = _dwc2_hcd_urb_dequeue, | |
4965 | .endpoint_disable = _dwc2_hcd_endpoint_disable, | |
4966 | .endpoint_reset = _dwc2_hcd_endpoint_reset, | |
4967 | .get_frame_number = _dwc2_hcd_get_frame_number, | |
4968 | ||
4969 | .hub_status_data = _dwc2_hcd_hub_status_data, | |
4970 | .hub_control = _dwc2_hcd_hub_control, | |
4971 | .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, | |
99a65798 GH |
4972 | |
4973 | .bus_suspend = _dwc2_hcd_suspend, | |
4974 | .bus_resume = _dwc2_hcd_resume, | |
3bc04e28 DA |
4975 | |
4976 | .map_urb_for_dma = dwc2_map_urb_for_dma, | |
4977 | .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, | |
7359d482 PZ |
4978 | }; |
4979 | ||
4980 | /* | |
4981 | * Frees secondary storage associated with the dwc2_hsotg structure contained | |
4982 | * in the struct usb_hcd field | |
4983 | */ | |
4984 | static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) | |
4985 | { | |
4986 | u32 ahbcfg; | |
4987 | u32 dctl; | |
4988 | int i; | |
4989 | ||
4990 | dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); | |
4991 | ||
4992 | /* Free memory for QH/QTD lists */ | |
4993 | dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); | |
38d2b5fb | 4994 | dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); |
7359d482 PZ |
4995 | dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); |
4996 | dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); | |
4997 | dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); | |
4998 | dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); | |
4999 | dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); | |
5000 | ||
5001 | /* Free memory for the host channels */ | |
5002 | for (i = 0; i < MAX_EPS_CHANNELS; i++) { | |
5003 | struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; | |
5004 | ||
9da51974 | 5005 | if (chan) { |
7359d482 PZ |
5006 | dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", |
5007 | i, chan); | |
5008 | hsotg->hc_ptr_array[i] = NULL; | |
5009 | kfree(chan); | |
5010 | } | |
5011 | } | |
5012 | ||
95832c00 | 5013 | if (hsotg->params.host_dma) { |
7359d482 PZ |
5014 | if (hsotg->status_buf) { |
5015 | dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, | |
5016 | hsotg->status_buf, | |
5017 | hsotg->status_buf_dma); | |
5018 | hsotg->status_buf = NULL; | |
5019 | } | |
5020 | } else { | |
5021 | kfree(hsotg->status_buf); | |
5022 | hsotg->status_buf = NULL; | |
5023 | } | |
5024 | ||
95c8bc36 | 5025 | ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); |
7359d482 PZ |
5026 | |
5027 | /* Disable all interrupts */ | |
5028 | ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; | |
95c8bc36 AS |
5029 | dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); |
5030 | dwc2_writel(0, hsotg->regs + GINTMSK); | |
7359d482 | 5031 | |
9badec2f | 5032 | if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { |
95c8bc36 | 5033 | dctl = dwc2_readl(hsotg->regs + DCTL); |
7359d482 | 5034 | dctl |= DCTL_SFTDISCON; |
95c8bc36 | 5035 | dwc2_writel(dctl, hsotg->regs + DCTL); |
7359d482 PZ |
5036 | } |
5037 | ||
5038 | if (hsotg->wq_otg) { | |
5039 | if (!cancel_work_sync(&hsotg->wf_otg)) | |
5040 | flush_workqueue(hsotg->wq_otg); | |
5041 | destroy_workqueue(hsotg->wq_otg); | |
5042 | } | |
5043 | ||
7359d482 PZ |
5044 | del_timer(&hsotg->wkp_timer); |
5045 | } | |
5046 | ||
5047 | static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) | |
5048 | { | |
5049 | /* Turn off all host-specific interrupts */ | |
5050 | dwc2_disable_host_interrupts(hsotg); | |
5051 | ||
5052 | dwc2_hcd_free(hsotg); | |
5053 | } | |
5054 | ||
7359d482 PZ |
5055 | /* |
5056 | * Initializes the HCD. This function allocates memory for and initializes the | |
5057 | * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the | |
5058 | * USB bus with the core and calls the hc_driver->start() function. It returns | |
5059 | * a negative error on failure. | |
5060 | */ | |
4fe160d5 | 5061 | int dwc2_hcd_init(struct dwc2_hsotg *hsotg) |
7359d482 | 5062 | { |
348becdc HK |
5063 | struct platform_device *pdev = to_platform_device(hsotg->dev); |
5064 | struct resource *res; | |
7359d482 PZ |
5065 | struct usb_hcd *hcd; |
5066 | struct dwc2_host_chan *channel; | |
9badec2f | 5067 | u32 hcfg; |
7359d482 | 5068 | int i, num_channels; |
9badec2f | 5069 | int retval; |
7359d482 | 5070 | |
f5500ecc DN |
5071 | if (usb_disabled()) |
5072 | return -ENODEV; | |
5073 | ||
e62662c7 | 5074 | dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); |
7359d482 | 5075 | |
9badec2f | 5076 | retval = -ENOMEM; |
7359d482 | 5077 | |
95c8bc36 | 5078 | hcfg = dwc2_readl(hsotg->regs + HCFG); |
7359d482 | 5079 | dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); |
7359d482 PZ |
5080 | |
5081 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS | |
6396bb22 KC |
5082 | hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE, |
5083 | sizeof(*hsotg->frame_num_array), | |
5084 | GFP_KERNEL); | |
7359d482 | 5085 | if (!hsotg->frame_num_array) |
ba0e60d1 | 5086 | goto error1; |
6396bb22 KC |
5087 | hsotg->last_frame_num_array = |
5088 | kcalloc(FRAME_NUM_ARRAY_SIZE, | |
5089 | sizeof(*hsotg->last_frame_num_array), GFP_KERNEL); | |
7359d482 | 5090 | if (!hsotg->last_frame_num_array) |
ba0e60d1 | 5091 | goto error1; |
7359d482 | 5092 | #endif |
483bb254 | 5093 | hsotg->last_frame_num = HFNUM_MAX_FRNUM; |
7359d482 | 5094 | |
a0112f48 | 5095 | /* Check if the bus driver or platform code has setup a dma_mask */ |
95832c00 | 5096 | if (hsotg->params.host_dma && |
9da51974 | 5097 | !hsotg->dev->dma_mask) { |
a0112f48 MK |
5098 | dev_warn(hsotg->dev, |
5099 | "dma_mask not set, disabling DMA\n"); | |
fdb09b3e | 5100 | hsotg->params.host_dma = false; |
95832c00 | 5101 | hsotg->params.dma_desc_enable = false; |
a0112f48 MK |
5102 | } |
5103 | ||
ba0e60d1 | 5104 | /* Set device flags indicating whether the HCD supports DMA */ |
95832c00 | 5105 | if (hsotg->params.host_dma) { |
30885313 PZ |
5106 | if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) |
5107 | dev_warn(hsotg->dev, "can't set DMA mask\n"); | |
25a49445 PZ |
5108 | if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) |
5109 | dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); | |
ba0e60d1 PZ |
5110 | } |
5111 | ||
ca8b0332 CY |
5112 | if (hsotg->params.change_speed_quirk) { |
5113 | dwc2_hc_driver.free_dev = dwc2_free_dev; | |
5114 | dwc2_hc_driver.reset_device = dwc2_reset_device; | |
5115 | } | |
5116 | ||
ba0e60d1 PZ |
5117 | hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); |
5118 | if (!hcd) | |
5119 | goto error1; | |
5120 | ||
95832c00 | 5121 | if (!hsotg->params.host_dma) |
7de76ee1 MK |
5122 | hcd->self.uses_dma = 0; |
5123 | ||
ba0e60d1 PZ |
5124 | hcd->has_tt = 1; |
5125 | ||
348becdc HK |
5126 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
5127 | hcd->rsrc_start = res->start; | |
5128 | hcd->rsrc_len = resource_size(res); | |
5129 | ||
9da51974 | 5130 | ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; |
ba0e60d1 PZ |
5131 | hsotg->priv = hcd; |
5132 | ||
7359d482 PZ |
5133 | /* |
5134 | * Disable the global interrupt until all the interrupt handlers are | |
5135 | * installed | |
5136 | */ | |
5137 | dwc2_disable_global_interrupts(hsotg); | |
5138 | ||
6706c721 | 5139 | /* Initialize the DWC_otg core, and select the Phy type */ |
0fe239bc | 5140 | retval = dwc2_core_init(hsotg, true); |
6706c721 MK |
5141 | if (retval) |
5142 | goto error2; | |
5143 | ||
7359d482 | 5144 | /* Create new workqueue and init work */ |
53510352 | 5145 | retval = -ENOMEM; |
ec7b1268 | 5146 | hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); |
7359d482 PZ |
5147 | if (!hsotg->wq_otg) { |
5148 | dev_err(hsotg->dev, "Failed to create workqueue\n"); | |
5149 | goto error2; | |
5150 | } | |
5151 | INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); | |
5152 | ||
e99e88a9 | 5153 | timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); |
7359d482 PZ |
5154 | |
5155 | /* Initialize the non-periodic schedule */ | |
5156 | INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); | |
38d2b5fb | 5157 | INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); |
7359d482 PZ |
5158 | INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); |
5159 | ||
5160 | /* Initialize the periodic schedule */ | |
5161 | INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); | |
5162 | INIT_LIST_HEAD(&hsotg->periodic_sched_ready); | |
5163 | INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); | |
5164 | INIT_LIST_HEAD(&hsotg->periodic_sched_queued); | |
5165 | ||
c9c8ac01 DA |
5166 | INIT_LIST_HEAD(&hsotg->split_order); |
5167 | ||
7359d482 PZ |
5168 | /* |
5169 | * Create a host channel descriptor for each host channel implemented | |
5170 | * in the controller. Initialize the channel descriptor array. | |
5171 | */ | |
5172 | INIT_LIST_HEAD(&hsotg->free_hc_list); | |
bea8e86c | 5173 | num_channels = hsotg->params.host_channels; |
7359d482 PZ |
5174 | memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); |
5175 | ||
5176 | for (i = 0; i < num_channels; i++) { | |
5177 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
9da51974 | 5178 | if (!channel) |
7359d482 PZ |
5179 | goto error3; |
5180 | channel->hc_num = i; | |
c9c8ac01 | 5181 | INIT_LIST_HEAD(&channel->split_order_list_entry); |
7359d482 PZ |
5182 | hsotg->hc_ptr_array[i] = channel; |
5183 | } | |
5184 | ||
5185 | /* Initialize hsotg start work */ | |
5186 | INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); | |
5187 | ||
5188 | /* Initialize port reset work */ | |
5189 | INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); | |
5190 | ||
5191 | /* | |
5192 | * Allocate space for storing data on status transactions. Normally no | |
5193 | * data is sent, but this space acts as a bit bucket. This must be | |
5194 | * done after usb_add_hcd since that function allocates the DMA buffer | |
5195 | * pool. | |
5196 | */ | |
95832c00 | 5197 | if (hsotg->params.host_dma) |
7359d482 PZ |
5198 | hsotg->status_buf = dma_alloc_coherent(hsotg->dev, |
5199 | DWC2_HCD_STATUS_BUF_SIZE, | |
5200 | &hsotg->status_buf_dma, GFP_KERNEL); | |
5201 | else | |
5202 | hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, | |
5203 | GFP_KERNEL); | |
5204 | ||
5205 | if (!hsotg->status_buf) | |
5206 | goto error3; | |
5207 | ||
3b5fcc9a GH |
5208 | /* |
5209 | * Create kmem caches to handle descriptor buffers in descriptor | |
5210 | * DMA mode. | |
5211 | * Alignment must be set to 512 bytes. | |
5212 | */ | |
bea8e86c JY |
5213 | if (hsotg->params.dma_desc_enable || |
5214 | hsotg->params.dma_desc_fs_enable) { | |
3b5fcc9a | 5215 | hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", |
ec703251 | 5216 | sizeof(struct dwc2_dma_desc) * |
3b5fcc9a GH |
5217 | MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, |
5218 | NULL); | |
5219 | if (!hsotg->desc_gen_cache) { | |
5220 | dev_err(hsotg->dev, | |
5221 | "unable to create dwc2 generic desc cache\n"); | |
5222 | ||
5223 | /* | |
5224 | * Disable descriptor dma mode since it will not be | |
5225 | * usable. | |
5226 | */ | |
95832c00 JY |
5227 | hsotg->params.dma_desc_enable = false; |
5228 | hsotg->params.dma_desc_fs_enable = false; | |
3b5fcc9a GH |
5229 | } |
5230 | ||
5231 | hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", | |
ec703251 | 5232 | sizeof(struct dwc2_dma_desc) * |
3b5fcc9a GH |
5233 | MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); |
5234 | if (!hsotg->desc_hsisoc_cache) { | |
5235 | dev_err(hsotg->dev, | |
5236 | "unable to create dwc2 hs isoc desc cache\n"); | |
5237 | ||
5238 | kmem_cache_destroy(hsotg->desc_gen_cache); | |
5239 | ||
5240 | /* | |
5241 | * Disable descriptor dma mode since it will not be | |
5242 | * usable. | |
5243 | */ | |
95832c00 JY |
5244 | hsotg->params.dma_desc_enable = false; |
5245 | hsotg->params.dma_desc_fs_enable = false; | |
3b5fcc9a GH |
5246 | } |
5247 | } | |
5248 | ||
7359d482 PZ |
5249 | hsotg->otg_port = 1; |
5250 | hsotg->frame_list = NULL; | |
5251 | hsotg->frame_list_dma = 0; | |
5252 | hsotg->periodic_qh_count = 0; | |
5253 | ||
5254 | /* Initiate lx_state to L3 disconnected state */ | |
5255 | hsotg->lx_state = DWC2_L3; | |
5256 | ||
5257 | hcd->self.otg_port = hsotg->otg_port; | |
5258 | ||
5259 | /* Don't support SG list at this point */ | |
5260 | hcd->self.sg_tablesize = 0; | |
5261 | ||
9df4ceac MYK |
5262 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
5263 | otg_set_host(hsotg->uphy->otg, &hcd->self); | |
5264 | ||
7359d482 PZ |
5265 | /* |
5266 | * Finish generic HCD initialization and start the HCD. This function | |
5267 | * allocates the DMA buffer pool, registers the USB bus, requests the | |
5268 | * IRQ line, and calls hcd_start method. | |
5269 | */ | |
4fe160d5 | 5270 | retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); |
7359d482 | 5271 | if (retval < 0) |
3b5fcc9a | 5272 | goto error4; |
7359d482 | 5273 | |
3c9740a1 PC |
5274 | device_wakeup_enable(hcd->self.controller); |
5275 | ||
7359d482 PZ |
5276 | dwc2_hcd_dump_state(hsotg); |
5277 | ||
5278 | dwc2_enable_global_interrupts(hsotg); | |
5279 | ||
5280 | return 0; | |
5281 | ||
3b5fcc9a GH |
5282 | error4: |
5283 | kmem_cache_destroy(hsotg->desc_gen_cache); | |
5284 | kmem_cache_destroy(hsotg->desc_hsisoc_cache); | |
7359d482 PZ |
5285 | error3: |
5286 | dwc2_hcd_release(hsotg); | |
5287 | error2: | |
ba0e60d1 PZ |
5288 | usb_put_hcd(hcd); |
5289 | error1: | |
7359d482 PZ |
5290 | |
5291 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS | |
5292 | kfree(hsotg->last_frame_num_array); | |
5293 | kfree(hsotg->frame_num_array); | |
5294 | #endif | |
5295 | ||
e62662c7 | 5296 | dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); |
7359d482 PZ |
5297 | return retval; |
5298 | } | |
7359d482 PZ |
5299 | |
5300 | /* | |
5301 | * Removes the HCD. | |
5302 | * Frees memory and resources associated with the HCD and deregisters the bus. | |
5303 | */ | |
e62662c7 | 5304 | void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) |
7359d482 PZ |
5305 | { |
5306 | struct usb_hcd *hcd; | |
5307 | ||
e62662c7 | 5308 | dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); |
7359d482 PZ |
5309 | |
5310 | hcd = dwc2_hsotg_to_hcd(hsotg); | |
e62662c7 | 5311 | dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); |
7359d482 PZ |
5312 | |
5313 | if (!hcd) { | |
e62662c7 | 5314 | dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", |
7359d482 PZ |
5315 | __func__); |
5316 | return; | |
5317 | } | |
5318 | ||
9df4ceac MYK |
5319 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
5320 | otg_set_host(hsotg->uphy->otg, NULL); | |
5321 | ||
7359d482 PZ |
5322 | usb_remove_hcd(hcd); |
5323 | hsotg->priv = NULL; | |
3b5fcc9a GH |
5324 | |
5325 | kmem_cache_destroy(hsotg->desc_gen_cache); | |
5326 | kmem_cache_destroy(hsotg->desc_hsisoc_cache); | |
5327 | ||
7359d482 | 5328 | dwc2_hcd_release(hsotg); |
ba0e60d1 | 5329 | usb_put_hcd(hcd); |
7359d482 PZ |
5330 | |
5331 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS | |
5332 | kfree(hsotg->last_frame_num_array); | |
5333 | kfree(hsotg->frame_num_array); | |
5334 | #endif | |
7359d482 | 5335 | } |
58e52ff6 JY |
5336 | |
5337 | /** | |
5338 | * dwc2_backup_host_registers() - Backup controller host registers. | |
5339 | * When suspending usb bus, registers needs to be backuped | |
5340 | * if controller power is disabled once suspended. | |
5341 | * | |
5342 | * @hsotg: Programming view of the DWC_otg controller | |
5343 | */ | |
5344 | int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) | |
5345 | { | |
5346 | struct dwc2_hregs_backup *hr; | |
5347 | int i; | |
5348 | ||
5349 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5350 | ||
5351 | /* Backup Host regs */ | |
5352 | hr = &hsotg->hr_backup; | |
5353 | hr->hcfg = dwc2_readl(hsotg->regs + HCFG); | |
5354 | hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); | |
bea8e86c | 5355 | for (i = 0; i < hsotg->params.host_channels; ++i) |
58e52ff6 JY |
5356 | hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); |
5357 | ||
5358 | hr->hprt0 = dwc2_read_hprt0(hsotg); | |
5359 | hr->hfir = dwc2_readl(hsotg->regs + HFIR); | |
66a36096 | 5360 | hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); |
58e52ff6 JY |
5361 | hr->valid = true; |
5362 | ||
5363 | return 0; | |
5364 | } | |
5365 | ||
5366 | /** | |
5367 | * dwc2_restore_host_registers() - Restore controller host registers. | |
5368 | * When resuming usb bus, device registers needs to be restored | |
5369 | * if controller power were disabled. | |
5370 | * | |
5371 | * @hsotg: Programming view of the DWC_otg controller | |
5372 | */ | |
5373 | int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) | |
5374 | { | |
5375 | struct dwc2_hregs_backup *hr; | |
5376 | int i; | |
5377 | ||
5378 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5379 | ||
5380 | /* Restore host regs */ | |
5381 | hr = &hsotg->hr_backup; | |
5382 | if (!hr->valid) { | |
5383 | dev_err(hsotg->dev, "%s: no host registers to restore\n", | |
5384 | __func__); | |
5385 | return -EINVAL; | |
5386 | } | |
5387 | hr->valid = false; | |
5388 | ||
5389 | dwc2_writel(hr->hcfg, hsotg->regs + HCFG); | |
5390 | dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); | |
5391 | ||
bea8e86c | 5392 | for (i = 0; i < hsotg->params.host_channels; ++i) |
58e52ff6 JY |
5393 | dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); |
5394 | ||
5395 | dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); | |
5396 | dwc2_writel(hr->hfir, hsotg->regs + HFIR); | |
66a36096 | 5397 | dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ); |
58e52ff6 JY |
5398 | hsotg->frame_number = 0; |
5399 | ||
5400 | return 0; | |
5401 | } | |
c5c403dc VM |
5402 | |
5403 | /** | |
5404 | * dwc2_host_enter_hibernation() - Put controller in Hibernation. | |
5405 | * | |
5406 | * @hsotg: Programming view of the DWC_otg controller | |
5407 | */ | |
5408 | int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5409 | { | |
5410 | unsigned long flags; | |
5411 | int ret = 0; | |
5412 | u32 hprt0; | |
5413 | u32 pcgcctl; | |
5414 | u32 gusbcfg; | |
5415 | u32 gpwrdn; | |
5416 | ||
5417 | dev_dbg(hsotg->dev, "Preparing host for hibernation\n"); | |
5418 | ret = dwc2_backup_global_registers(hsotg); | |
5419 | if (ret) { | |
5420 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5421 | __func__); | |
5422 | return ret; | |
5423 | } | |
5424 | ret = dwc2_backup_host_registers(hsotg); | |
5425 | if (ret) { | |
5426 | dev_err(hsotg->dev, "%s: failed to backup host registers\n", | |
5427 | __func__); | |
5428 | return ret; | |
5429 | } | |
5430 | ||
5431 | /* Enter USB Suspend Mode */ | |
5432 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); | |
5433 | hprt0 |= HPRT0_SUSP; | |
5434 | hprt0 &= ~HPRT0_ENA; | |
5435 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5436 | ||
5437 | /* Wait for the HPRT0.PrtSusp register field to be set */ | |
5438 | if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 300)) | |
07b8dc55 | 5439 | dev_warn(hsotg->dev, "Suspend wasn't generated\n"); |
c5c403dc VM |
5440 | |
5441 | /* | |
5442 | * We need to disable interrupts to prevent servicing of any IRQ | |
5443 | * during going to hibernation | |
5444 | */ | |
5445 | spin_lock_irqsave(&hsotg->lock, flags); | |
5446 | hsotg->lx_state = DWC2_L2; | |
5447 | ||
5448 | gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
5449 | if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { | |
5450 | /* ULPI interface */ | |
5451 | /* Suspend the Phy Clock */ | |
5452 | pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); | |
5453 | pcgcctl |= PCGCTL_STOPPCLK; | |
5454 | dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); | |
5455 | udelay(10); | |
5456 | ||
5457 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5458 | gpwrdn |= GPWRDN_PMUACTV; | |
5459 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5460 | udelay(10); | |
5461 | } else { | |
5462 | /* UTMI+ Interface */ | |
5463 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5464 | gpwrdn |= GPWRDN_PMUACTV; | |
5465 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5466 | udelay(10); | |
5467 | ||
5468 | pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); | |
5469 | pcgcctl |= PCGCTL_STOPPCLK; | |
5470 | dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); | |
5471 | udelay(10); | |
5472 | } | |
5473 | ||
5474 | /* Enable interrupts from wake up logic */ | |
5475 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5476 | gpwrdn |= GPWRDN_PMUINTSEL; | |
5477 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5478 | udelay(10); | |
5479 | ||
5480 | /* Unmask host mode interrupts in GPWRDN */ | |
5481 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5482 | gpwrdn |= GPWRDN_DISCONN_DET_MSK; | |
5483 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5484 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
5485 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5486 | udelay(10); | |
5487 | ||
5488 | /* Enable Power Down Clamp */ | |
5489 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5490 | gpwrdn |= GPWRDN_PWRDNCLMP; | |
5491 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5492 | udelay(10); | |
5493 | ||
5494 | /* Switch off VDD */ | |
5495 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5496 | gpwrdn |= GPWRDN_PWRDNSWTCH; | |
5497 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5498 | ||
5499 | hsotg->hibernated = 1; | |
5500 | hsotg->bus_suspended = 1; | |
5501 | dev_dbg(hsotg->dev, "Host hibernation completed\n"); | |
5502 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
5503 | return ret; | |
5504 | } | |
5505 | ||
5506 | /* | |
5507 | * dwc2_host_exit_hibernation() | |
5508 | * | |
5509 | * @hsotg: Programming view of the DWC_otg controller | |
5510 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
5511 | * @param reset: indicates whether resume is initiated by Reset. | |
5512 | * | |
5513 | * Return: non-zero if failed to enter to hibernation. | |
5514 | * | |
5515 | * This function is for exiting from Host mode hibernation by | |
5516 | * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. | |
5517 | */ | |
5518 | int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, | |
5519 | int reset) | |
5520 | { | |
5521 | u32 gpwrdn; | |
5522 | u32 hprt0; | |
5523 | int ret = 0; | |
5524 | struct dwc2_gregs_backup *gr; | |
5525 | struct dwc2_hregs_backup *hr; | |
5526 | ||
5527 | gr = &hsotg->gr_backup; | |
5528 | hr = &hsotg->hr_backup; | |
5529 | ||
5530 | dev_dbg(hsotg->dev, | |
5531 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5532 | __func__, rem_wakeup, reset); | |
5533 | ||
5534 | dwc2_hib_restore_common(hsotg, rem_wakeup, 1); | |
5535 | hsotg->hibernated = 0; | |
5536 | ||
5537 | /* | |
5538 | * This step is not described in functional spec but if not wait for | |
5539 | * this delay, mismatch interrupts occurred because just after restore | |
5540 | * core is in Device mode(gintsts.curmode == 0) | |
5541 | */ | |
5542 | mdelay(100); | |
5543 | ||
5544 | /* Clear all pending interupts */ | |
5545 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5546 | ||
5547 | /* De-assert Restore */ | |
5548 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5549 | gpwrdn &= ~GPWRDN_RESTORE; | |
5550 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5551 | udelay(10); | |
5552 | ||
5553 | /* Restore GUSBCFG, HCFG */ | |
5554 | dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); | |
5555 | dwc2_writel(hr->hcfg, hsotg->regs + HCFG); | |
5556 | ||
5557 | /* De-assert Wakeup Logic */ | |
5558 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5559 | gpwrdn &= ~GPWRDN_PMUACTV; | |
5560 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5561 | udelay(10); | |
5562 | ||
5563 | hprt0 = hr->hprt0; | |
5564 | hprt0 |= HPRT0_PWR; | |
5565 | hprt0 &= ~HPRT0_ENA; | |
5566 | hprt0 &= ~HPRT0_SUSP; | |
5567 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5568 | ||
5569 | hprt0 = hr->hprt0; | |
5570 | hprt0 |= HPRT0_PWR; | |
5571 | hprt0 &= ~HPRT0_ENA; | |
5572 | hprt0 &= ~HPRT0_SUSP; | |
5573 | ||
5574 | if (reset) { | |
5575 | hprt0 |= HPRT0_RST; | |
5576 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5577 | ||
5578 | /* Wait for Resume time and then program HPRT again */ | |
5579 | mdelay(60); | |
5580 | hprt0 &= ~HPRT0_RST; | |
5581 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5582 | } else { | |
5583 | hprt0 |= HPRT0_RES; | |
5584 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5585 | ||
5586 | /* Wait for Resume time and then program HPRT again */ | |
5587 | mdelay(100); | |
5588 | hprt0 &= ~HPRT0_RES; | |
5589 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5590 | } | |
5591 | /* Clear all interrupt status */ | |
5592 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); | |
5593 | hprt0 |= HPRT0_CONNDET; | |
5594 | hprt0 |= HPRT0_ENACHG; | |
5595 | hprt0 &= ~HPRT0_ENA; | |
5596 | dwc2_writel(hprt0, hsotg->regs + HPRT0); | |
5597 | ||
5598 | hprt0 = dwc2_readl(hsotg->regs + HPRT0); | |
5599 | ||
5600 | /* Clear all pending interupts */ | |
5601 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5602 | ||
5603 | /* Restore global registers */ | |
5604 | ret = dwc2_restore_global_registers(hsotg); | |
5605 | if (ret) { | |
5606 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5607 | __func__); | |
5608 | return ret; | |
5609 | } | |
5610 | ||
5611 | /* Restore host registers */ | |
5612 | ret = dwc2_restore_host_registers(hsotg); | |
5613 | if (ret) { | |
5614 | dev_err(hsotg->dev, "%s: failed to restore host registers\n", | |
5615 | __func__); | |
5616 | return ret; | |
5617 | } | |
5618 | ||
5619 | hsotg->hibernated = 0; | |
5620 | hsotg->bus_suspended = 0; | |
5621 | hsotg->lx_state = DWC2_L0; | |
5622 | dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); | |
5623 | return ret; | |
5624 | } |