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1/*
2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the interrupt handlers for Host mode
39 */
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/spinlock.h>
43#include <linux/interrupt.h>
44#include <linux/dma-mapping.h>
45#include <linux/io.h>
46#include <linux/slab.h>
47#include <linux/usb.h>
48
49#include <linux/usb/hcd.h>
50#include <linux/usb/ch11.h>
51
52#include "core.h"
53#include "hcd.h"
54
55/* This function is for debug only */
56static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
57{
58#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
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59 u16 curr_frame_number = hsotg->frame_number;
60
61 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
62 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
63 curr_frame_number) {
64 hsotg->frame_num_array[hsotg->frame_num_idx] =
65 curr_frame_number;
66 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
67 hsotg->last_frame_num;
68 hsotg->frame_num_idx++;
69 }
70 } else if (!hsotg->dumped_frame_num_array) {
71 int i;
72
73 dev_info(hsotg->dev, "Frame Last Frame\n");
74 dev_info(hsotg->dev, "----- ----------\n");
75 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
76 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
77 hsotg->frame_num_array[i],
78 hsotg->last_frame_num_array[i]);
79 }
80 hsotg->dumped_frame_num_array = 1;
81 }
82 hsotg->last_frame_num = curr_frame_number;
83#endif
84}
85
86static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
87 struct dwc2_host_chan *chan,
88 struct dwc2_qtd *qtd)
89{
90 struct urb *usb_urb;
91
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92 if (!chan->qh)
93 return;
94
95 if (chan->qh->dev_speed == USB_SPEED_HIGH)
96 return;
97
98 if (!qtd->urb)
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99 return;
100
101 usb_urb = qtd->urb->priv;
399fdf9e 102 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
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103 return;
104
399fdf9e 105 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
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106 chan->qh->tt_buffer_dirty = 1;
107 if (usb_hub_clear_tt_buffer(usb_urb))
108 /* Clear failed; let's hope things work anyway */
109 chan->qh->tt_buffer_dirty = 0;
110 }
111}
112
113/*
114 * Handles the start-of-frame interrupt in host mode. Non-periodic
115 * transactions may be queued to the DWC_otg controller for the current
116 * (micro)frame. Periodic transactions may be queued to the controller
117 * for the next (micro)frame.
118 */
119static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
120{
121 struct list_head *qh_entry;
122 struct dwc2_qh *qh;
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123 enum dwc2_transaction_type tr_type;
124
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125 /* Clear interrupt */
126 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
127
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128#ifdef DEBUG_SOF
129 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
130#endif
131
37e1dcc2 132 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
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133
134 dwc2_track_missed_sofs(hsotg);
135
136 /* Determine whether any periodic QHs should be executed */
137 qh_entry = hsotg->periodic_sched_inactive.next;
138 while (qh_entry != &hsotg->periodic_sched_inactive) {
139 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
140 qh_entry = qh_entry->next;
141 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
142 /*
143 * Move QH to the ready list to be executed next
144 * (micro)frame
145 */
146 list_move(&qh->qh_list_entry,
147 &hsotg->periodic_sched_ready);
148 }
149 tr_type = dwc2_hcd_select_transactions(hsotg);
150 if (tr_type != DWC2_TRANSACTION_NONE)
151 dwc2_hcd_queue_transactions(hsotg, tr_type);
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152}
153
154/*
155 * Handles the Rx FIFO Level Interrupt, which indicates that there is
156 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
157 * memory if the DWC_otg controller is operating in Slave mode.
158 */
159static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
160{
161 u32 grxsts, chnum, bcnt, dpid, pktsts;
162 struct dwc2_host_chan *chan;
163
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164 if (dbg_perio())
165 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
7359d482 166
95c8bc36 167 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
d6ec53e0 168 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
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169 chan = hsotg->hc_ptr_array[chnum];
170 if (!chan) {
171 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
172 return;
173 }
174
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175 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
176 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
f9234633 177 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
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178
179 /* Packet Status */
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180 if (dbg_perio()) {
181 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
182 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
183 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
184 chan->data_pid_start);
f9234633 185 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
b49977a6 186 }
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187
188 switch (pktsts) {
189 case GRXSTS_PKTSTS_HCHIN:
190 /* Read the data into the host buffer */
191 if (bcnt > 0) {
192 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
193
194 /* Update the HC fields for the next packet received */
195 chan->xfer_count += bcnt;
196 chan->xfer_buf += bcnt;
197 }
198 break;
199 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
200 case GRXSTS_PKTSTS_DATATOGGLEERR:
201 case GRXSTS_PKTSTS_HCHHALTED:
202 /* Handled in interrupt, just ignore data */
203 break;
204 default:
205 dev_err(hsotg->dev,
206 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
207 break;
208 }
209}
210
211/*
212 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
213 * data packets may be written to the FIFO for OUT transfers. More requests
214 * may be written to the non-periodic request queue for IN transfers. This
215 * interrupt is enabled only in Slave mode.
216 */
217static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
218{
219 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
220 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
221}
222
223/*
224 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
225 * packets may be written to the FIFO for OUT transfers. More requests may be
226 * written to the periodic request queue for IN transfers. This interrupt is
227 * enabled only in Slave mode.
228 */
229static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
230{
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231 if (dbg_perio())
232 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
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233 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
234}
235
236static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
237 u32 *hprt0_modify)
238{
239 struct dwc2_core_params *params = hsotg->core_params;
240 int do_reset = 0;
241 u32 usbcfg;
242 u32 prtspd;
243 u32 hcfg;
bcc5defa 244 u32 fslspclksel;
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245 u32 hfir;
246
247 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
248
249 /* Every time when port enables calculate HFIR.FrInterval */
95c8bc36 250 hfir = dwc2_readl(hsotg->regs + HFIR);
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251 hfir &= ~HFIR_FRINT_MASK;
252 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
253 HFIR_FRINT_MASK;
95c8bc36 254 dwc2_writel(hfir, hsotg->regs + HFIR);
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255
256 /* Check if we need to adjust the PHY clock speed for low power */
257 if (!params->host_support_fs_ls_low_power) {
258 /* Port has been enabled, set the reset change flag */
259 hsotg->flags.b.port_reset_change = 1;
260 return;
261 }
262
95c8bc36 263 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
f9234633 264 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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265
266 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
267 /* Low power */
268 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
269 /* Set PHY low power clock select for FS/LS devices */
270 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
95c8bc36 271 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
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272 do_reset = 1;
273 }
274
95c8bc36 275 hcfg = dwc2_readl(hsotg->regs + HCFG);
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276 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
277 HCFG_FSLSPCLKSEL_SHIFT;
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278
279 if (prtspd == HPRT0_SPD_LOW_SPEED &&
280 params->host_ls_low_power_phy_clk ==
281 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
282 /* 6 MHZ */
283 dev_vdbg(hsotg->dev,
284 "FS_PHY programming HCFG to 6 MHz\n");
bcc5defa 285 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
f9234633 286 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
7359d482 287 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
f9234633 288 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
95c8bc36 289 dwc2_writel(hcfg, hsotg->regs + HCFG);
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290 do_reset = 1;
291 }
292 } else {
293 /* 48 MHZ */
294 dev_vdbg(hsotg->dev,
295 "FS_PHY programming HCFG to 48 MHz\n");
bcc5defa 296 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
f9234633 297 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
7359d482 298 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
f9234633 299 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
95c8bc36 300 dwc2_writel(hcfg, hsotg->regs + HCFG);
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301 do_reset = 1;
302 }
303 }
304 } else {
305 /* Not low power */
306 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
307 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
95c8bc36 308 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
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309 do_reset = 1;
310 }
311 }
312
313 if (do_reset) {
314 *hprt0_modify |= HPRT0_RST;
29539019 315 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
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316 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
317 msecs_to_jiffies(60));
318 } else {
319 /* Port has been enabled, set the reset change flag */
320 hsotg->flags.b.port_reset_change = 1;
321 }
322}
323
324/*
325 * There are multiple conditions that can cause a port interrupt. This function
326 * determines which interrupt conditions have occurred and handles them
327 * appropriately.
328 */
329static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
330{
331 u32 hprt0;
332 u32 hprt0_modify;
333
334 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
335
95c8bc36 336 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
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337 hprt0_modify = hprt0;
338
339 /*
340 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
341 * GINTSTS
342 */
343 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
344 HPRT0_OVRCURRCHG);
345
346 /*
347 * Port Connect Detected
348 * Set flag and clear if detected
349 */
350 if (hprt0 & HPRT0_CONNDET) {
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351 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
352
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353 dev_vdbg(hsotg->dev,
354 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
355 hprt0);
6a659531 356 dwc2_hcd_connect(hsotg);
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357
358 /*
359 * The Hub driver asserts a reset when it sees port connect
360 * status change flag
361 */
362 }
363
364 /*
365 * Port Enable Changed
366 * Clear if detected - Set internal flag if disabled
367 */
368 if (hprt0 & HPRT0_ENACHG) {
29539019 369 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
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370 dev_vdbg(hsotg->dev,
371 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
372 hprt0, !!(hprt0 & HPRT0_ENA));
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373 if (hprt0 & HPRT0_ENA) {
374 hsotg->new_connection = true;
7359d482 375 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
fbb9e22b 376 } else {
7359d482 377 hsotg->flags.b.port_enable_change = 1;
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378 if (hsotg->core_params->dma_desc_fs_enable) {
379 u32 hcfg;
380
381 hsotg->core_params->dma_desc_enable = 0;
382 hsotg->new_connection = false;
383 hcfg = dwc2_readl(hsotg->regs + HCFG);
384 hcfg &= ~HCFG_DESCDMA;
385 dwc2_writel(hcfg, hsotg->regs + HCFG);
386 }
387 }
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388 }
389
390 /* Overcurrent Change Interrupt */
391 if (hprt0 & HPRT0_OVRCURRCHG) {
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392 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
393 hsotg->regs + HPRT0);
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394 dev_vdbg(hsotg->dev,
395 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
396 hprt0);
397 hsotg->flags.b.port_over_current_change = 1;
7359d482 398 }
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399}
400
401/*
402 * Gets the actual length of a transfer after the transfer halts. halt_status
403 * holds the reason for the halt.
404 *
405 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
406 * is set to 1 upon return if less than the requested number of bytes were
407 * transferred. short_read may also be NULL on entry, in which case it remains
408 * unchanged.
409 */
410static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
411 struct dwc2_host_chan *chan, int chnum,
412 struct dwc2_qtd *qtd,
413 enum dwc2_halt_status halt_status,
414 int *short_read)
415{
416 u32 hctsiz, count, length;
417
95c8bc36 418 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
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419
420 if (halt_status == DWC2_HC_XFER_COMPLETE) {
421 if (chan->ep_is_in) {
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422 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
423 TSIZ_XFERSIZE_SHIFT;
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424 length = chan->xfer_len - count;
425 if (short_read != NULL)
426 *short_read = (count != 0);
427 } else if (chan->qh->do_split) {
428 length = qtd->ssplit_out_xfer_count;
429 } else {
430 length = chan->xfer_len;
431 }
432 } else {
433 /*
434 * Must use the hctsiz.pktcnt field to determine how much data
435 * has been transferred. This field reflects the number of
436 * packets that have been transferred via the USB. This is
437 * always an integral number of packets if the transfer was
438 * halted before its normal completion. (Can't use the
439 * hctsiz.xfersize field because that reflects the number of
440 * bytes transferred via the AHB, not the USB).
441 */
d6ec53e0 442 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
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443 length = (chan->start_pkt_count - count) * chan->max_packet;
444 }
445
446 return length;
447}
448
449/**
450 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
451 * Complete interrupt on the host channel. Updates the actual_length field
452 * of the URB based on the number of bytes transferred via the host channel.
453 * Sets the URB status if the data transfer is finished.
454 *
455 * Return: 1 if the data transfer specified by the URB is completely finished,
456 * 0 otherwise
457 */
458static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
459 struct dwc2_host_chan *chan, int chnum,
460 struct dwc2_hcd_urb *urb,
461 struct dwc2_qtd *qtd)
462{
463 u32 hctsiz;
464 int xfer_done = 0;
465 int short_read = 0;
466 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
467 DWC2_HC_XFER_COMPLETE,
468 &short_read);
469
470 if (urb->actual_length + xfer_length > urb->length) {
471 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
472 xfer_length = urb->length - urb->actual_length;
473 }
474
475 /* Non DWORD-aligned buffer case handling */
db62b9a8 476 if (chan->align_buf && xfer_length) {
0cf31f86 477 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
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478 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
479 chan->qh->dw_align_buf_size,
480 chan->ep_is_in ?
481 DMA_FROM_DEVICE : DMA_TO_DEVICE);
482 if (chan->ep_is_in)
483 memcpy(urb->buf + urb->actual_length,
484 chan->qh->dw_align_buf, xfer_length);
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485 }
486
487 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
488 urb->actual_length, xfer_length);
489 urb->actual_length += xfer_length;
490
491 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
492 (urb->flags & URB_SEND_ZERO_PACKET) &&
493 urb->actual_length >= urb->length &&
494 !(urb->length % chan->max_packet)) {
495 xfer_done = 0;
496 } else if (short_read || urb->actual_length >= urb->length) {
497 xfer_done = 1;
498 urb->status = 0;
499 }
500
95c8bc36 501 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
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502 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
503 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
504 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
505 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
d6ec53e0 506 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
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507 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
508 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
509 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
510 xfer_done);
511
512 return xfer_done;
513}
514
515/*
516 * Save the starting data toggle for the next transfer. The data toggle is
517 * saved in the QH for non-control transfers and it's saved in the QTD for
518 * control transfers.
519 */
520void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
521 struct dwc2_host_chan *chan, int chnum,
522 struct dwc2_qtd *qtd)
523{
95c8bc36 524 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
f9234633 525 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
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526
527 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
62943b7d
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528 if (WARN(!chan || !chan->qh,
529 "chan->qh must be specified for non-control eps\n"))
530 return;
531
7359d482
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532 if (pid == TSIZ_SC_MC_PID_DATA0)
533 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
534 else
535 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
536 } else {
62943b7d
TJ
537 if (WARN(!qtd,
538 "qtd must be specified for control eps\n"))
539 return;
540
7359d482
PZ
541 if (pid == TSIZ_SC_MC_PID_DATA0)
542 qtd->data_toggle = DWC2_HC_PID_DATA0;
543 else
544 qtd->data_toggle = DWC2_HC_PID_DATA1;
545 }
546}
547
548/**
549 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
550 * the transfer is stopped for any reason. The fields of the current entry in
551 * the frame descriptor array are set based on the transfer state and the input
552 * halt_status. Completes the Isochronous URB if all the URB frames have been
553 * completed.
554 *
555 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
556 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
557 */
558static enum dwc2_halt_status dwc2_update_isoc_urb_state(
559 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
560 int chnum, struct dwc2_qtd *qtd,
561 enum dwc2_halt_status halt_status)
562{
563 struct dwc2_hcd_iso_packet_desc *frame_desc;
564 struct dwc2_hcd_urb *urb = qtd->urb;
565
566 if (!urb)
567 return DWC2_HC_XFER_NO_HALT_STATUS;
568
569 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
570
571 switch (halt_status) {
572 case DWC2_HC_XFER_COMPLETE:
573 frame_desc->status = 0;
574 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
575 chan, chnum, qtd, halt_status, NULL);
576
577 /* Non DWORD-aligned buffer case handling */
db62b9a8 578 if (chan->align_buf && frame_desc->actual_length) {
0cf31f86
PZ
579 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
580 __func__);
db62b9a8
GH
581 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
582 chan->qh->dw_align_buf_size,
583 chan->ep_is_in ?
584 DMA_FROM_DEVICE : DMA_TO_DEVICE);
585 if (chan->ep_is_in)
586 memcpy(urb->buf + frame_desc->offset +
587 qtd->isoc_split_offset,
588 chan->qh->dw_align_buf,
589 frame_desc->actual_length);
7359d482
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590 }
591 break;
592 case DWC2_HC_XFER_FRAME_OVERRUN:
593 urb->error_count++;
594 if (chan->ep_is_in)
595 frame_desc->status = -ENOSR;
596 else
597 frame_desc->status = -ECOMM;
598 frame_desc->actual_length = 0;
599 break;
600 case DWC2_HC_XFER_BABBLE_ERR:
601 urb->error_count++;
602 frame_desc->status = -EOVERFLOW;
603 /* Don't need to update actual_length in this case */
604 break;
605 case DWC2_HC_XFER_XACT_ERR:
606 urb->error_count++;
607 frame_desc->status = -EPROTO;
608 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
609 chan, chnum, qtd, halt_status, NULL);
610
611 /* Non DWORD-aligned buffer case handling */
db62b9a8 612 if (chan->align_buf && frame_desc->actual_length) {
0cf31f86
PZ
613 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
614 __func__);
db62b9a8
GH
615 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
616 chan->qh->dw_align_buf_size,
617 chan->ep_is_in ?
618 DMA_FROM_DEVICE : DMA_TO_DEVICE);
619 if (chan->ep_is_in)
620 memcpy(urb->buf + frame_desc->offset +
621 qtd->isoc_split_offset,
622 chan->qh->dw_align_buf,
623 frame_desc->actual_length);
7359d482
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624 }
625
626 /* Skip whole frame */
627 if (chan->qh->do_split &&
628 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
629 hsotg->core_params->dma_enable > 0) {
630 qtd->complete_split = 0;
631 qtd->isoc_split_offset = 0;
632 }
633
634 break;
635 default:
636 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
637 halt_status);
638 break;
639 }
640
641 if (++qtd->isoc_frame_index == urb->packet_count) {
642 /*
643 * urb->status is not used for isoc transfers. The individual
644 * frame_desc statuses are used instead.
645 */
0d012b98 646 dwc2_host_complete(hsotg, qtd, 0);
7359d482
PZ
647 halt_status = DWC2_HC_XFER_URB_COMPLETE;
648 } else {
649 halt_status = DWC2_HC_XFER_COMPLETE;
650 }
651
652 return halt_status;
653}
654
655/*
656 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
657 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
658 * still linked to the QH, the QH is added to the end of the inactive
659 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
660 * schedule if no more QTDs are linked to the QH.
661 */
662static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
663 int free_qtd)
664{
665 int continue_split = 0;
666 struct dwc2_qtd *qtd;
667
b49977a6
MK
668 if (dbg_qh(qh))
669 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
670 hsotg, qh, free_qtd);
7359d482
PZ
671
672 if (list_empty(&qh->qtd_list)) {
673 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
674 goto no_qtd;
675 }
676
677 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
678
679 if (qtd->complete_split)
680 continue_split = 1;
681 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
682 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
683 continue_split = 1;
684
685 if (free_qtd) {
686 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
687 continue_split = 0;
688 }
689
690no_qtd:
691 if (qh->channel)
692 qh->channel->align_buf = 0;
693 qh->channel = NULL;
694 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
695}
696
697/**
698 * dwc2_release_channel() - Releases a host channel for use by other transfers
699 *
700 * @hsotg: The HCD state structure
701 * @chan: The host channel to release
702 * @qtd: The QTD associated with the host channel. This QTD may be
703 * freed if the transfer is complete or an error has occurred.
704 * @halt_status: Reason the channel is being released. This status
705 * determines the actions taken by this function.
706 *
707 * Also attempts to select and queue more transactions since at least one host
708 * channel is available.
709 */
710static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
711 struct dwc2_host_chan *chan,
712 struct dwc2_qtd *qtd,
713 enum dwc2_halt_status halt_status)
714{
715 enum dwc2_transaction_type tr_type;
716 u32 haintmsk;
717 int free_qtd = 0;
718
b49977a6
MK
719 if (dbg_hc(chan))
720 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
721 __func__, chan->hc_num, halt_status);
7359d482
PZ
722
723 switch (halt_status) {
724 case DWC2_HC_XFER_URB_COMPLETE:
725 free_qtd = 1;
726 break;
727 case DWC2_HC_XFER_AHB_ERR:
728 case DWC2_HC_XFER_STALL:
729 case DWC2_HC_XFER_BABBLE_ERR:
730 free_qtd = 1;
731 break;
732 case DWC2_HC_XFER_XACT_ERR:
8509f2f4 733 if (qtd && qtd->error_count >= 3) {
7359d482
PZ
734 dev_vdbg(hsotg->dev,
735 " Complete URB with transaction error\n");
736 free_qtd = 1;
0d012b98 737 dwc2_host_complete(hsotg, qtd, -EPROTO);
7359d482
PZ
738 }
739 break;
740 case DWC2_HC_XFER_URB_DEQUEUE:
741 /*
742 * The QTD has already been removed and the QH has been
743 * deactivated. Don't want to do anything except release the
744 * host channel and try to queue more transfers.
745 */
746 goto cleanup;
747 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
748 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
749 free_qtd = 1;
0d012b98 750 dwc2_host_complete(hsotg, qtd, -EIO);
7359d482
PZ
751 break;
752 case DWC2_HC_XFER_NO_HALT_STATUS:
753 default:
754 break;
755 }
756
757 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
758
759cleanup:
760 /*
761 * Release the host channel for use by other transfers. The cleanup
762 * function clears the channel interrupt enables and conditions, so
763 * there's no need to clear the Channel Halted interrupt separately.
764 */
765 if (!list_empty(&chan->hc_list_entry))
766 list_del(&chan->hc_list_entry);
767 dwc2_hc_cleanup(hsotg, chan);
768 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
769
20f2eb9c
DC
770 if (hsotg->core_params->uframe_sched > 0) {
771 hsotg->available_host_channels++;
772 } else {
773 switch (chan->ep_type) {
774 case USB_ENDPOINT_XFER_CONTROL:
775 case USB_ENDPOINT_XFER_BULK:
776 hsotg->non_periodic_channels--;
777 break;
778 default:
779 /*
780 * Don't release reservations for periodic channels
781 * here. That's done when a periodic transfer is
782 * descheduled (i.e. when the QH is removed from the
783 * periodic schedule).
784 */
785 break;
786 }
7359d482
PZ
787 }
788
95c8bc36 789 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
7359d482 790 haintmsk &= ~(1 << chan->hc_num);
95c8bc36 791 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
7359d482
PZ
792
793 /* Try to queue more transfers now that there's a free channel */
794 tr_type = dwc2_hcd_select_transactions(hsotg);
795 if (tr_type != DWC2_TRANSACTION_NONE)
796 dwc2_hcd_queue_transactions(hsotg, tr_type);
797}
798
799/*
800 * Halts a host channel. If the channel cannot be halted immediately because
801 * the request queue is full, this function ensures that the FIFO empty
802 * interrupt for the appropriate queue is enabled so that the halt request can
803 * be queued when there is space in the request queue.
804 *
805 * This function may also be called in DMA mode. In that case, the channel is
806 * simply released since the core always halts the channel automatically in
807 * DMA mode.
808 */
809static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
810 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
811 enum dwc2_halt_status halt_status)
812{
b49977a6
MK
813 if (dbg_hc(chan))
814 dev_vdbg(hsotg->dev, "%s()\n", __func__);
7359d482
PZ
815
816 if (hsotg->core_params->dma_enable > 0) {
b49977a6
MK
817 if (dbg_hc(chan))
818 dev_vdbg(hsotg->dev, "DMA enabled\n");
7359d482
PZ
819 dwc2_release_channel(hsotg, chan, qtd, halt_status);
820 return;
821 }
822
823 /* Slave mode processing */
824 dwc2_hc_halt(hsotg, chan, halt_status);
825
826 if (chan->halt_on_queue) {
827 u32 gintmsk;
828
829 dev_vdbg(hsotg->dev, "Halt on queue\n");
830 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
831 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
832 dev_vdbg(hsotg->dev, "control/bulk\n");
833 /*
834 * Make sure the Non-periodic Tx FIFO empty interrupt
835 * is enabled so that the non-periodic schedule will
836 * be processed
837 */
95c8bc36 838 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 839 gintmsk |= GINTSTS_NPTXFEMP;
95c8bc36 840 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ
841 } else {
842 dev_vdbg(hsotg->dev, "isoc/intr\n");
843 /*
844 * Move the QH from the periodic queued schedule to
845 * the periodic assigned schedule. This allows the
846 * halt to be queued when the periodic schedule is
847 * processed.
848 */
849 list_move(&chan->qh->qh_list_entry,
850 &hsotg->periodic_sched_assigned);
851
852 /*
853 * Make sure the Periodic Tx FIFO Empty interrupt is
854 * enabled so that the periodic schedule will be
855 * processed
856 */
95c8bc36 857 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 858 gintmsk |= GINTSTS_PTXFEMP;
95c8bc36 859 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ
860 }
861 }
862}
863
864/*
865 * Performs common cleanup for non-periodic transfers after a Transfer
866 * Complete interrupt. This function should be called after any endpoint type
867 * specific handling is finished to release the host channel.
868 */
869static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
870 struct dwc2_host_chan *chan,
871 int chnum, struct dwc2_qtd *qtd,
872 enum dwc2_halt_status halt_status)
873{
874 dev_vdbg(hsotg->dev, "%s()\n", __func__);
875
876 qtd->error_count = 0;
877
878 if (chan->hcint & HCINTMSK_NYET) {
879 /*
880 * Got a NYET on the last transaction of the transfer. This
881 * means that the endpoint should be in the PING state at the
882 * beginning of the next transfer.
883 */
884 dev_vdbg(hsotg->dev, "got NYET\n");
885 chan->qh->ping_state = 1;
886 }
887
888 /*
889 * Always halt and release the host channel to make it available for
890 * more transfers. There may still be more phases for a control
891 * transfer or more data packets for a bulk transfer at this point,
892 * but the host channel is still halted. A channel will be reassigned
893 * to the transfer when the non-periodic schedule is processed after
894 * the channel is released. This allows transactions to be queued
895 * properly via dwc2_hcd_queue_transactions, which also enables the
896 * Tx FIFO Empty interrupt if necessary.
897 */
898 if (chan->ep_is_in) {
899 /*
900 * IN transfers in Slave mode require an explicit disable to
901 * halt the channel. (In DMA mode, this call simply releases
902 * the channel.)
903 */
904 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
905 } else {
906 /*
907 * The channel is automatically disabled by the core for OUT
908 * transfers in Slave mode
909 */
910 dwc2_release_channel(hsotg, chan, qtd, halt_status);
911 }
912}
913
914/*
915 * Performs common cleanup for periodic transfers after a Transfer Complete
916 * interrupt. This function should be called after any endpoint type specific
917 * handling is finished to release the host channel.
918 */
919static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
920 struct dwc2_host_chan *chan, int chnum,
921 struct dwc2_qtd *qtd,
922 enum dwc2_halt_status halt_status)
923{
95c8bc36 924 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
7359d482
PZ
925
926 qtd->error_count = 0;
927
928 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
929 /* Core halts channel in these cases */
930 dwc2_release_channel(hsotg, chan, qtd, halt_status);
931 else
932 /* Flush any outstanding requests from the Tx queue */
933 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
934}
935
936static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
937 struct dwc2_host_chan *chan, int chnum,
938 struct dwc2_qtd *qtd)
939{
940 struct dwc2_hcd_iso_packet_desc *frame_desc;
941 u32 len;
942
943 if (!qtd->urb)
944 return 0;
945
946 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
947 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
948 DWC2_HC_XFER_COMPLETE, NULL);
949 if (!len) {
950 qtd->complete_split = 0;
951 qtd->isoc_split_offset = 0;
952 return 0;
953 }
954
955 frame_desc->actual_length += len;
956
e7e59e11 957 if (chan->align_buf) {
0cf31f86 958 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
db62b9a8
GH
959 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
960 chan->qh->dw_align_buf_size, DMA_FROM_DEVICE);
7359d482
PZ
961 memcpy(qtd->urb->buf + frame_desc->offset +
962 qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
7359d482
PZ
963 }
964
965 qtd->isoc_split_offset += len;
966
967 if (frame_desc->actual_length >= frame_desc->length) {
968 frame_desc->status = 0;
969 qtd->isoc_frame_index++;
970 qtd->complete_split = 0;
971 qtd->isoc_split_offset = 0;
972 }
973
974 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
0d012b98 975 dwc2_host_complete(hsotg, qtd, 0);
7359d482
PZ
976 dwc2_release_channel(hsotg, chan, qtd,
977 DWC2_HC_XFER_URB_COMPLETE);
978 } else {
979 dwc2_release_channel(hsotg, chan, qtd,
980 DWC2_HC_XFER_NO_HALT_STATUS);
981 }
982
983 return 1; /* Indicates that channel released */
984}
985
986/*
987 * Handles a host channel Transfer Complete interrupt. This handler may be
988 * called in either DMA mode or Slave mode.
989 */
990static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
991 struct dwc2_host_chan *chan, int chnum,
992 struct dwc2_qtd *qtd)
993{
994 struct dwc2_hcd_urb *urb = qtd->urb;
7359d482 995 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
2b54fa6b 996 int pipe_type;
7359d482
PZ
997 int urb_xfer_done;
998
b49977a6
MK
999 if (dbg_hc(chan))
1000 dev_vdbg(hsotg->dev,
1001 "--Host Channel %d Interrupt: Transfer Complete--\n",
1002 chnum);
7359d482 1003
2b54fa6b
PZ
1004 if (!urb)
1005 goto handle_xfercomp_done;
1006
1007 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1008
7359d482
PZ
1009 if (hsotg->core_params->dma_desc_enable > 0) {
1010 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1011 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
1012 /* Do not disable the interrupt, just clear it */
1013 return;
1014 goto handle_xfercomp_done;
1015 }
1016
1017 /* Handle xfer complete on CSPLIT */
1018 if (chan->qh->do_split) {
1019 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1020 hsotg->core_params->dma_enable > 0) {
1021 if (qtd->complete_split &&
1022 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1023 qtd))
1024 goto handle_xfercomp_done;
1025 } else {
1026 qtd->complete_split = 0;
1027 }
1028 }
1029
7359d482
PZ
1030 /* Update the QTD and URB states */
1031 switch (pipe_type) {
1032 case USB_ENDPOINT_XFER_CONTROL:
1033 switch (qtd->control_phase) {
1034 case DWC2_CONTROL_SETUP:
1035 if (urb->length > 0)
1036 qtd->control_phase = DWC2_CONTROL_DATA;
1037 else
1038 qtd->control_phase = DWC2_CONTROL_STATUS;
1039 dev_vdbg(hsotg->dev,
1040 " Control setup transaction done\n");
1041 halt_status = DWC2_HC_XFER_COMPLETE;
1042 break;
1043 case DWC2_CONTROL_DATA:
1044 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1045 chnum, urb, qtd);
1046 if (urb_xfer_done) {
1047 qtd->control_phase = DWC2_CONTROL_STATUS;
1048 dev_vdbg(hsotg->dev,
1049 " Control data transfer done\n");
1050 } else {
1051 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1052 qtd);
1053 }
1054 halt_status = DWC2_HC_XFER_COMPLETE;
1055 break;
1056 case DWC2_CONTROL_STATUS:
1057 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1058 if (urb->status == -EINPROGRESS)
1059 urb->status = 0;
0d012b98 1060 dwc2_host_complete(hsotg, qtd, urb->status);
7359d482
PZ
1061 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1062 break;
1063 }
1064
1065 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1066 halt_status);
1067 break;
1068 case USB_ENDPOINT_XFER_BULK:
1069 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1070 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1071 qtd);
1072 if (urb_xfer_done) {
0d012b98 1073 dwc2_host_complete(hsotg, qtd, urb->status);
7359d482
PZ
1074 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1075 } else {
1076 halt_status = DWC2_HC_XFER_COMPLETE;
1077 }
1078
1079 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1080 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1081 halt_status);
1082 break;
1083 case USB_ENDPOINT_XFER_INT:
1084 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1085 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1086 qtd);
1087
1088 /*
1089 * Interrupt URB is done on the first transfer complete
1090 * interrupt
1091 */
1092 if (urb_xfer_done) {
0d012b98
PZ
1093 dwc2_host_complete(hsotg, qtd, urb->status);
1094 halt_status = DWC2_HC_XFER_URB_COMPLETE;
7359d482 1095 } else {
0d012b98 1096 halt_status = DWC2_HC_XFER_COMPLETE;
7359d482
PZ
1097 }
1098
1099 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1100 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1101 halt_status);
1102 break;
1103 case USB_ENDPOINT_XFER_ISOC:
b49977a6
MK
1104 if (dbg_perio())
1105 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
7359d482
PZ
1106 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1107 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1108 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1109 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1110 halt_status);
1111 break;
1112 }
1113
1114handle_xfercomp_done:
1115 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1116}
1117
1118/*
1119 * Handles a host channel STALL interrupt. This handler may be called in
1120 * either DMA mode or Slave mode.
1121 */
1122static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1123 struct dwc2_host_chan *chan, int chnum,
1124 struct dwc2_qtd *qtd)
1125{
1126 struct dwc2_hcd_urb *urb = qtd->urb;
2b54fa6b 1127 int pipe_type;
7359d482
PZ
1128
1129 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1130 chnum);
1131
1132 if (hsotg->core_params->dma_desc_enable > 0) {
1133 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1134 DWC2_HC_XFER_STALL);
1135 goto handle_stall_done;
1136 }
1137
1138 if (!urb)
1139 goto handle_stall_halt;
1140
2b54fa6b
PZ
1141 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1142
7359d482 1143 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
0d012b98 1144 dwc2_host_complete(hsotg, qtd, -EPIPE);
7359d482
PZ
1145
1146 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1147 pipe_type == USB_ENDPOINT_XFER_INT) {
0d012b98 1148 dwc2_host_complete(hsotg, qtd, -EPIPE);
7359d482
PZ
1149 /*
1150 * USB protocol requires resetting the data toggle for bulk
1151 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1152 * setup command is issued to the endpoint. Anticipate the
1153 * CLEAR_FEATURE command since a STALL has occurred and reset
1154 * the data toggle now.
1155 */
1156 chan->qh->data_toggle = 0;
1157 }
1158
1159handle_stall_halt:
1160 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1161
1162handle_stall_done:
1163 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1164}
1165
1166/*
1167 * Updates the state of the URB when a transfer has been stopped due to an
1168 * abnormal condition before the transfer completes. Modifies the
1169 * actual_length field of the URB to reflect the number of bytes that have
1170 * actually been transferred via the host channel.
1171 */
1172static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1173 struct dwc2_host_chan *chan, int chnum,
1174 struct dwc2_hcd_urb *urb,
1175 struct dwc2_qtd *qtd,
1176 enum dwc2_halt_status halt_status)
1177{
1178 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1179 qtd, halt_status, NULL);
1180 u32 hctsiz;
1181
1182 if (urb->actual_length + xfer_length > urb->length) {
1183 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1184 xfer_length = urb->length - urb->actual_length;
1185 }
1186
1187 /* Non DWORD-aligned buffer case handling */
1188 if (chan->align_buf && xfer_length && chan->ep_is_in) {
0cf31f86 1189 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
db62b9a8
GH
1190 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
1191 chan->qh->dw_align_buf_size,
1192 chan->ep_is_in ?
1193 DMA_FROM_DEVICE : DMA_TO_DEVICE);
1194 if (chan->ep_is_in)
1195 memcpy(urb->buf + urb->actual_length,
1196 chan->qh->dw_align_buf,
1197 xfer_length);
7359d482
PZ
1198 }
1199
1200 urb->actual_length += xfer_length;
1201
95c8bc36 1202 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
7359d482
PZ
1203 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1204 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1205 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1206 chan->start_pkt_count);
1207 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
d6ec53e0 1208 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
7359d482
PZ
1209 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1210 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1211 xfer_length);
1212 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1213 urb->actual_length);
1214 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1215 urb->length);
1216}
1217
1218/*
1219 * Handles a host channel NAK interrupt. This handler may be called in either
1220 * DMA mode or Slave mode.
1221 */
1222static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1223 struct dwc2_host_chan *chan, int chnum,
1224 struct dwc2_qtd *qtd)
1225{
e499123e
GH
1226 if (!qtd) {
1227 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1228 return;
1229 }
1230
1231 if (!qtd->urb) {
1232 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1233 return;
1234 }
1235
b49977a6
MK
1236 if (dbg_hc(chan))
1237 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1238 chnum);
7359d482
PZ
1239
1240 /*
1241 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1242 * interrupt. Re-start the SSPLIT transfer.
1243 */
1244 if (chan->do_split) {
1245 if (chan->complete_split)
1246 qtd->error_count = 0;
1247 qtd->complete_split = 0;
1248 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1249 goto handle_nak_done;
1250 }
1251
1252 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1253 case USB_ENDPOINT_XFER_CONTROL:
1254 case USB_ENDPOINT_XFER_BULK:
1255 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1256 /*
1257 * NAK interrupts are enabled on bulk/control IN
1258 * transfers in DMA mode for the sole purpose of
1259 * resetting the error count after a transaction error
1260 * occurs. The core will continue transferring data.
1261 */
1262 qtd->error_count = 0;
1263 break;
1264 }
1265
1266 /*
1267 * NAK interrupts normally occur during OUT transfers in DMA
1268 * or Slave mode. For IN transfers, more requests will be
1269 * queued as request queue space is available.
1270 */
1271 qtd->error_count = 0;
1272
1273 if (!chan->qh->ping_state) {
1274 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1275 qtd, DWC2_HC_XFER_NAK);
1276 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1277
1278 if (chan->speed == USB_SPEED_HIGH)
1279 chan->qh->ping_state = 1;
1280 }
1281
1282 /*
1283 * Halt the channel so the transfer can be re-started from
1284 * the appropriate point or the PING protocol will
1285 * start/continue
1286 */
1287 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1288 break;
1289 case USB_ENDPOINT_XFER_INT:
1290 qtd->error_count = 0;
1291 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1292 break;
1293 case USB_ENDPOINT_XFER_ISOC:
1294 /* Should never get called for isochronous transfers */
1295 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1296 break;
1297 }
1298
1299handle_nak_done:
1300 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1301}
1302
1303/*
1304 * Handles a host channel ACK interrupt. This interrupt is enabled when
1305 * performing the PING protocol in Slave mode, when errors occur during
1306 * either Slave mode or DMA mode, and during Start Split transactions.
1307 */
1308static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1309 struct dwc2_host_chan *chan, int chnum,
1310 struct dwc2_qtd *qtd)
1311{
1312 struct dwc2_hcd_iso_packet_desc *frame_desc;
1313
b49977a6
MK
1314 if (dbg_hc(chan))
1315 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1316 chnum);
7359d482
PZ
1317
1318 if (chan->do_split) {
1319 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1320 if (!chan->ep_is_in &&
1321 chan->data_pid_start != DWC2_HC_PID_SETUP)
1322 qtd->ssplit_out_xfer_count = chan->xfer_len;
1323
1324 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1325 qtd->complete_split = 1;
1326 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1327 } else {
1328 /* ISOC OUT */
1329 switch (chan->xact_pos) {
1330 case DWC2_HCSPLT_XACTPOS_ALL:
1331 break;
1332 case DWC2_HCSPLT_XACTPOS_END:
1333 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1334 qtd->isoc_split_offset = 0;
1335 break;
1336 case DWC2_HCSPLT_XACTPOS_BEGIN:
1337 case DWC2_HCSPLT_XACTPOS_MID:
1338 /*
1339 * For BEGIN or MID, calculate the length for
1340 * the next microframe to determine the correct
1341 * SSPLIT token, either MID or END
1342 */
1343 frame_desc = &qtd->urb->iso_descs[
1344 qtd->isoc_frame_index];
1345 qtd->isoc_split_offset += 188;
1346
1347 if (frame_desc->length - qtd->isoc_split_offset
1348 <= 188)
1349 qtd->isoc_split_pos =
1350 DWC2_HCSPLT_XACTPOS_END;
1351 else
1352 qtd->isoc_split_pos =
1353 DWC2_HCSPLT_XACTPOS_MID;
1354 break;
1355 }
1356 }
1357 } else {
1358 qtd->error_count = 0;
1359
1360 if (chan->qh->ping_state) {
1361 chan->qh->ping_state = 0;
1362 /*
1363 * Halt the channel so the transfer can be re-started
1364 * from the appropriate point. This only happens in
1365 * Slave mode. In DMA mode, the ping_state is cleared
1366 * when the transfer is started because the core
1367 * automatically executes the PING, then the transfer.
1368 */
1369 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1370 }
1371 }
1372
1373 /*
1374 * If the ACK occurred when _not_ in the PING state, let the channel
1375 * continue transferring data after clearing the error count
1376 */
1377 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1378}
1379
1380/*
1381 * Handles a host channel NYET interrupt. This interrupt should only occur on
1382 * Bulk and Control OUT endpoints and for complete split transactions. If a
1383 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1384 * handled in the xfercomp interrupt handler, not here. This handler may be
1385 * called in either DMA mode or Slave mode.
1386 */
1387static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1388 struct dwc2_host_chan *chan, int chnum,
1389 struct dwc2_qtd *qtd)
1390{
b49977a6
MK
1391 if (dbg_hc(chan))
1392 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1393 chnum);
7359d482
PZ
1394
1395 /*
1396 * NYET on CSPLIT
1397 * re-do the CSPLIT immediately on non-periodic
1398 */
1399 if (chan->do_split && chan->complete_split) {
1400 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1401 hsotg->core_params->dma_enable > 0) {
1402 qtd->complete_split = 0;
1403 qtd->isoc_split_offset = 0;
0d012b98 1404 qtd->isoc_frame_index++;
7902c16b 1405 if (qtd->urb &&
0d012b98
PZ
1406 qtd->isoc_frame_index == qtd->urb->packet_count) {
1407 dwc2_host_complete(hsotg, qtd, 0);
7359d482 1408 dwc2_release_channel(hsotg, chan, qtd,
7902c16b 1409 DWC2_HC_XFER_URB_COMPLETE);
7359d482
PZ
1410 } else {
1411 dwc2_release_channel(hsotg, chan, qtd,
1412 DWC2_HC_XFER_NO_HALT_STATUS);
1413 }
1414 goto handle_nyet_done;
1415 }
1416
1417 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1418 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1419 int frnum = dwc2_hcd_get_frame_number(hsotg);
1420
1421 if (dwc2_full_frame_num(frnum) !=
1422 dwc2_full_frame_num(chan->qh->sched_frame)) {
1423 /*
1424 * No longer in the same full speed frame.
1425 * Treat this as a transaction error.
1426 */
1427#if 0
1428 /*
1429 * Todo: Fix system performance so this can
1430 * be treated as an error. Right now complete
1431 * splits cannot be scheduled precisely enough
1432 * due to other system activity, so this error
1433 * occurs regularly in Slave mode.
1434 */
1435 qtd->error_count++;
1436#endif
1437 qtd->complete_split = 0;
1438 dwc2_halt_channel(hsotg, chan, qtd,
1439 DWC2_HC_XFER_XACT_ERR);
1440 /* Todo: add support for isoc release */
1441 goto handle_nyet_done;
1442 }
1443 }
1444
1445 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1446 goto handle_nyet_done;
1447 }
1448
1449 chan->qh->ping_state = 1;
1450 qtd->error_count = 0;
1451
1452 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1453 DWC2_HC_XFER_NYET);
1454 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1455
1456 /*
1457 * Halt the channel and re-start the transfer so the PING protocol
1458 * will start
1459 */
1460 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1461
1462handle_nyet_done:
1463 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1464}
1465
1466/*
1467 * Handles a host channel babble interrupt. This handler may be called in
1468 * either DMA mode or Slave mode.
1469 */
1470static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1471 struct dwc2_host_chan *chan, int chnum,
1472 struct dwc2_qtd *qtd)
1473{
1474 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1475 chnum);
1476
0d012b98
PZ
1477 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1478
7359d482
PZ
1479 if (hsotg->core_params->dma_desc_enable > 0) {
1480 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1481 DWC2_HC_XFER_BABBLE_ERR);
0d012b98 1482 goto disable_int;
7359d482
PZ
1483 }
1484
1485 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
0d012b98 1486 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
7359d482
PZ
1487 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1488 } else {
1489 enum dwc2_halt_status halt_status;
1490
1491 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1492 qtd, DWC2_HC_XFER_BABBLE_ERR);
1493 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1494 }
1495
0d012b98 1496disable_int:
7359d482
PZ
1497 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1498}
1499
1500/*
1501 * Handles a host channel AHB error interrupt. This handler is only called in
1502 * DMA mode.
1503 */
1504static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1505 struct dwc2_host_chan *chan, int chnum,
1506 struct dwc2_qtd *qtd)
1507{
1508 struct dwc2_hcd_urb *urb = qtd->urb;
1509 char *pipetype, *speed;
1510 u32 hcchar;
1511 u32 hcsplt;
1512 u32 hctsiz;
1513 u32 hc_dma;
1514
1515 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1516 chnum);
1517
1518 if (!urb)
1519 goto handle_ahberr_halt;
1520
0d012b98
PZ
1521 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1522
95c8bc36
AS
1523 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1524 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1525 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1526 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
7359d482
PZ
1527
1528 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1529 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1530 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1531 dev_err(hsotg->dev, " Device address: %d\n",
1532 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1533 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1534 dwc2_hcd_get_ep_num(&urb->pipe_info),
1535 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1536
1537 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1538 case USB_ENDPOINT_XFER_CONTROL:
1539 pipetype = "CONTROL";
1540 break;
1541 case USB_ENDPOINT_XFER_BULK:
1542 pipetype = "BULK";
1543 break;
1544 case USB_ENDPOINT_XFER_INT:
1545 pipetype = "INTERRUPT";
1546 break;
1547 case USB_ENDPOINT_XFER_ISOC:
1548 pipetype = "ISOCHRONOUS";
1549 break;
1550 default:
1551 pipetype = "UNKNOWN";
1552 break;
1553 }
1554
1555 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1556
1557 switch (chan->speed) {
1558 case USB_SPEED_HIGH:
1559 speed = "HIGH";
1560 break;
1561 case USB_SPEED_FULL:
1562 speed = "FULL";
1563 break;
1564 case USB_SPEED_LOW:
1565 speed = "LOW";
1566 break;
1567 default:
1568 speed = "UNKNOWN";
1569 break;
1570 }
1571
1572 dev_err(hsotg->dev, " Speed: %s\n", speed);
1573
1574 dev_err(hsotg->dev, " Max packet size: %d\n",
1575 dwc2_hcd_get_mps(&urb->pipe_info));
1576 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
157dfaac
PZ
1577 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1578 urb->buf, (unsigned long)urb->dma);
1579 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1580 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ
1581 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1582
1583 /* Core halts the channel for Descriptor DMA mode */
1584 if (hsotg->core_params->dma_desc_enable > 0) {
1585 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1586 DWC2_HC_XFER_AHB_ERR);
1587 goto handle_ahberr_done;
1588 }
1589
0d012b98 1590 dwc2_host_complete(hsotg, qtd, -EIO);
7359d482
PZ
1591
1592handle_ahberr_halt:
1593 /*
1594 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1595 * write to the HCCHARn register in DMA mode to force the halt.
1596 */
1597 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1598
1599handle_ahberr_done:
7359d482
PZ
1600 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1601}
1602
1603/*
1604 * Handles a host channel transaction error interrupt. This handler may be
1605 * called in either DMA mode or Slave mode.
1606 */
1607static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1608 struct dwc2_host_chan *chan, int chnum,
1609 struct dwc2_qtd *qtd)
1610{
1611 dev_dbg(hsotg->dev,
1612 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1613
0d012b98
PZ
1614 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1615
7359d482
PZ
1616 if (hsotg->core_params->dma_desc_enable > 0) {
1617 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1618 DWC2_HC_XFER_XACT_ERR);
1619 goto handle_xacterr_done;
1620 }
1621
1622 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1623 case USB_ENDPOINT_XFER_CONTROL:
1624 case USB_ENDPOINT_XFER_BULK:
1625 qtd->error_count++;
1626 if (!chan->qh->ping_state) {
1627
1628 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1629 qtd, DWC2_HC_XFER_XACT_ERR);
1630 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1631 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1632 chan->qh->ping_state = 1;
1633 }
1634
1635 /*
1636 * Halt the channel so the transfer can be re-started from
1637 * the appropriate point or the PING protocol will start
1638 */
1639 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1640 break;
1641 case USB_ENDPOINT_XFER_INT:
1642 qtd->error_count++;
1643 if (chan->do_split && chan->complete_split)
1644 qtd->complete_split = 0;
1645 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1646 break;
1647 case USB_ENDPOINT_XFER_ISOC:
1648 {
1649 enum dwc2_halt_status halt_status;
1650
1651 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1652 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1653 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1654 }
1655 break;
1656 }
1657
1658handle_xacterr_done:
7359d482
PZ
1659 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1660}
1661
1662/*
1663 * Handles a host channel frame overrun interrupt. This handler may be called
1664 * in either DMA mode or Slave mode.
1665 */
1666static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1667 struct dwc2_host_chan *chan, int chnum,
1668 struct dwc2_qtd *qtd)
1669{
1670 enum dwc2_halt_status halt_status;
1671
b49977a6
MK
1672 if (dbg_hc(chan))
1673 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1674 chnum);
7359d482 1675
0d012b98
PZ
1676 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1677
7359d482
PZ
1678 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1679 case USB_ENDPOINT_XFER_CONTROL:
1680 case USB_ENDPOINT_XFER_BULK:
1681 break;
1682 case USB_ENDPOINT_XFER_INT:
1683 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1684 break;
1685 case USB_ENDPOINT_XFER_ISOC:
1686 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1687 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1688 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1689 break;
1690 }
1691
7359d482
PZ
1692 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1693}
1694
1695/*
1696 * Handles a host channel data toggle error interrupt. This handler may be
1697 * called in either DMA mode or Slave mode.
1698 */
1699static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1700 struct dwc2_host_chan *chan, int chnum,
1701 struct dwc2_qtd *qtd)
1702{
1703 dev_dbg(hsotg->dev,
1704 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1705
1706 if (chan->ep_is_in)
1707 qtd->error_count = 0;
1708 else
1709 dev_err(hsotg->dev,
1710 "Data Toggle Error on OUT transfer, channel %d\n",
1711 chnum);
1712
1713 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1714 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1715}
1716
1717/*
1718 * For debug only. It checks that a valid halt status is set and that
1719 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1720 * taken and a warning is issued.
1721 *
1722 * Return: true if halt status is ok, false otherwise
1723 */
1724static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1725 struct dwc2_host_chan *chan, int chnum,
1726 struct dwc2_qtd *qtd)
1727{
1728#ifdef DEBUG
1729 u32 hcchar;
1730 u32 hctsiz;
1731 u32 hcintmsk;
1732 u32 hcsplt;
1733
1734 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1735 /*
1736 * This code is here only as a check. This condition should
1737 * never happen. Ignore the halt if it does occur.
1738 */
95c8bc36
AS
1739 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1740 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1741 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1742 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
7359d482
PZ
1743 dev_dbg(hsotg->dev,
1744 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1745 __func__);
1746 dev_dbg(hsotg->dev,
1747 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1748 chnum, hcchar, hctsiz);
1749 dev_dbg(hsotg->dev,
1750 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1751 chan->hcint, hcintmsk, hcsplt);
8509f2f4
MK
1752 if (qtd)
1753 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1754 qtd->complete_split);
7359d482
PZ
1755 dev_warn(hsotg->dev,
1756 "%s: no halt status, channel %d, ignoring interrupt\n",
1757 __func__, chnum);
1758 return false;
1759 }
1760
1761 /*
1762 * This code is here only as a check. hcchar.chdis should never be set
1763 * when the halt interrupt occurs. Halt the channel again if it does
1764 * occur.
1765 */
95c8bc36 1766 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
7359d482
PZ
1767 if (hcchar & HCCHAR_CHDIS) {
1768 dev_warn(hsotg->dev,
1769 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1770 __func__, hcchar);
1771 chan->halt_pending = 0;
1772 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1773 return false;
1774 }
1775#endif
1776
1777 return true;
1778}
1779
1780/*
1781 * Handles a host Channel Halted interrupt in DMA mode. This handler
1782 * determines the reason the channel halted and proceeds accordingly.
1783 */
1784static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1785 struct dwc2_host_chan *chan, int chnum,
1786 struct dwc2_qtd *qtd)
1787{
1788 u32 hcintmsk;
1789 int out_nak_enh = 0;
1790
b49977a6
MK
1791 if (dbg_hc(chan))
1792 dev_vdbg(hsotg->dev,
1793 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1794 chnum);
7359d482
PZ
1795
1796 /*
1797 * For core with OUT NAK enhancement, the flow for high-speed
1798 * CONTROL/BULK OUT is handled a little differently
1799 */
9badec2f 1800 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
7359d482
PZ
1801 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1802 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1803 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1804 out_nak_enh = 1;
1805 }
1806 }
1807
1808 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1809 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1810 hsotg->core_params->dma_desc_enable <= 0)) {
1811 if (hsotg->core_params->dma_desc_enable > 0)
1812 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1813 chan->halt_status);
1814 else
1815 /*
1816 * Just release the channel. A dequeue can happen on a
1817 * transfer timeout. In the case of an AHB Error, the
1818 * channel was forced to halt because there's no way to
1819 * gracefully recover.
1820 */
1821 dwc2_release_channel(hsotg, chan, qtd,
1822 chan->halt_status);
1823 return;
1824 }
1825
95c8bc36 1826 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
7359d482
PZ
1827
1828 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1829 /*
1830 * Todo: This is here because of a possible hardware bug. Spec
1831 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1832 * interrupt w/ACK bit set should occur, but I only see the
1833 * XFERCOMP bit, even with it masked out. This is a workaround
1834 * for that behavior. Should fix this when hardware is fixed.
1835 */
1836 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1837 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1838 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1839 } else if (chan->hcint & HCINTMSK_STALL) {
1840 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1841 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1842 hsotg->core_params->dma_desc_enable <= 0) {
1843 if (out_nak_enh) {
1844 if (chan->hcint &
1845 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1846 dev_vdbg(hsotg->dev,
1847 "XactErr with NYET/NAK/ACK\n");
1848 qtd->error_count = 0;
1849 } else {
1850 dev_vdbg(hsotg->dev,
1851 "XactErr without NYET/NAK/ACK\n");
1852 }
1853 }
1854
1855 /*
1856 * Must handle xacterr before nak or ack. Could get a xacterr
1857 * at the same time as either of these on a BULK/CONTROL OUT
1858 * that started with a PING. The xacterr takes precedence.
1859 */
1860 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1861 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1862 hsotg->core_params->dma_desc_enable > 0) {
1863 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1864 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1865 hsotg->core_params->dma_desc_enable > 0) {
1866 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1867 } else if (chan->hcint & HCINTMSK_BBLERR) {
1868 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1869 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1870 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1871 } else if (!out_nak_enh) {
1872 if (chan->hcint & HCINTMSK_NYET) {
1873 /*
1874 * Must handle nyet before nak or ack. Could get a nyet
1875 * at the same time as either of those on a BULK/CONTROL
1876 * OUT that started with a PING. The nyet takes
1877 * precedence.
1878 */
1879 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1880 } else if ((chan->hcint & HCINTMSK_NAK) &&
1881 !(hcintmsk & HCINTMSK_NAK)) {
1882 /*
1883 * If nak is not masked, it's because a non-split IN
1884 * transfer is in an error state. In that case, the nak
1885 * is handled by the nak interrupt handler, not here.
1886 * Handle nak here for BULK/CONTROL OUT transfers, which
1887 * halt on a NAK to allow rewinding the buffer pointer.
1888 */
1889 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1890 } else if ((chan->hcint & HCINTMSK_ACK) &&
1891 !(hcintmsk & HCINTMSK_ACK)) {
1892 /*
1893 * If ack is not masked, it's because a non-split IN
1894 * transfer is in an error state. In that case, the ack
1895 * is handled by the ack interrupt handler, not here.
1896 * Handle ack here for split transfers. Start splits
1897 * halt on ACK.
1898 */
1899 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1900 } else {
1901 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1902 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1903 /*
1904 * A periodic transfer halted with no other
1905 * channel interrupts set. Assume it was halted
1906 * by the core because it could not be completed
1907 * in its scheduled (micro)frame.
1908 */
1909 dev_dbg(hsotg->dev,
1910 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1911 __func__, chnum);
1912 dwc2_halt_channel(hsotg, chan, qtd,
1913 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1914 } else {
1915 dev_err(hsotg->dev,
1916 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1917 __func__, chnum);
1918 dev_err(hsotg->dev,
1919 "hcint 0x%08x, intsts 0x%08x\n",
1920 chan->hcint,
95c8bc36 1921 dwc2_readl(hsotg->regs + GINTSTS));
151d0cbd 1922 goto error;
7359d482
PZ
1923 }
1924 }
1925 } else {
1926 dev_info(hsotg->dev,
1927 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1928 chan->hcint);
151d0cbd
NH
1929error:
1930 /* Failthrough: use 3-strikes rule */
1931 qtd->error_count++;
1932 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1933 qtd, DWC2_HC_XFER_XACT_ERR);
1934 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1935 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
7359d482
PZ
1936 }
1937}
1938
1939/*
1940 * Handles a host channel Channel Halted interrupt
1941 *
1942 * In slave mode, this handler is called only when the driver specifically
1943 * requests a halt. This occurs during handling other host channel interrupts
1944 * (e.g. nak, xacterr, stall, nyet, etc.).
1945 *
1946 * In DMA mode, this is the interrupt that occurs when the core has finished
1947 * processing a transfer on a channel. Other host channel interrupts (except
1948 * ahberr) are disabled in DMA mode.
1949 */
1950static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1951 struct dwc2_host_chan *chan, int chnum,
1952 struct dwc2_qtd *qtd)
1953{
b49977a6
MK
1954 if (dbg_hc(chan))
1955 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1956 chnum);
7359d482
PZ
1957
1958 if (hsotg->core_params->dma_enable > 0) {
1959 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1960 } else {
1961 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1962 return;
1963 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1964 }
1965}
1966
dc873084
DA
1967/*
1968 * Check if the given qtd is still the top of the list (and thus valid).
1969 *
1970 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1971 * the qtd from the top of the list, this will return false (otherwise true).
1972 */
1973static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1974{
1975 struct dwc2_qtd *cur_head;
1976
1977 if (qh == NULL)
1978 return false;
1979
1980 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1981 qtd_list_entry);
1982 return (cur_head == qtd);
1983}
1984
7359d482
PZ
1985/* Handles interrupt for a specific Host Channel */
1986static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1987{
1988 struct dwc2_qtd *qtd;
1989 struct dwc2_host_chan *chan;
1990 u32 hcint, hcintmsk;
1991
b49977a6
MK
1992 chan = hsotg->hc_ptr_array[chnum];
1993
95c8bc36
AS
1994 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1995 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
7359d482
PZ
1996 if (!chan) {
1997 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
95c8bc36 1998 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
7359d482
PZ
1999 return;
2000 }
2001
723a2311
RK
2002 if (dbg_hc(chan)) {
2003 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2004 chnum);
2005 dev_vdbg(hsotg->dev,
2006 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2007 hcint, hcintmsk, hcint & hcintmsk);
2008 }
2009
95c8bc36 2010 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
7359d482
PZ
2011 chan->hcint = hcint;
2012 hcint &= hcintmsk;
2013
8509f2f4
MK
2014 /*
2015 * If the channel was halted due to a dequeue, the qtd list might
2016 * be empty or at least the first entry will not be the active qtd.
2017 * In this case, take a shortcut and just release the channel.
2018 */
2019 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2020 /*
2021 * If the channel was halted, this should be the only
2022 * interrupt unmasked
2023 */
2024 WARN_ON(hcint != HCINTMSK_CHHLTD);
2025 if (hsotg->core_params->dma_desc_enable > 0)
2026 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2027 chan->halt_status);
2028 else
2029 dwc2_release_channel(hsotg, chan, NULL,
2030 chan->halt_status);
2031 return;
2032 }
2033
7359d482 2034 if (list_empty(&chan->qh->qtd_list)) {
8509f2f4
MK
2035 /*
2036 * TODO: Will this ever happen with the
2037 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2038 */
7359d482
PZ
2039 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2040 chnum);
2041 dev_dbg(hsotg->dev,
2042 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2043 chan->hcint, hcintmsk, hcint);
2044 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2045 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2046 chan->hcint = 0;
2047 return;
2048 }
2049
2050 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2051 qtd_list_entry);
2052
2053 if (hsotg->core_params->dma_enable <= 0) {
2054 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2055 hcint &= ~HCINTMSK_CHHLTD;
2056 }
2057
2058 if (hcint & HCINTMSK_XFERCOMPL) {
2059 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2060 /*
2061 * If NYET occurred at same time as Xfer Complete, the NYET is
2062 * handled by the Xfer Complete interrupt handler. Don't want
2063 * to call the NYET interrupt handler in this case.
2064 */
2065 hcint &= ~HCINTMSK_NYET;
2066 }
dc873084
DA
2067
2068 if (hcint & HCINTMSK_CHHLTD) {
7359d482 2069 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2070 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2071 goto exit;
2072 }
2073 if (hcint & HCINTMSK_AHBERR) {
7359d482 2074 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2075 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2076 goto exit;
2077 }
2078 if (hcint & HCINTMSK_STALL) {
7359d482 2079 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2080 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2081 goto exit;
2082 }
2083 if (hcint & HCINTMSK_NAK) {
7359d482 2084 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2085 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2086 goto exit;
2087 }
2088 if (hcint & HCINTMSK_ACK) {
7359d482 2089 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2090 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2091 goto exit;
2092 }
2093 if (hcint & HCINTMSK_NYET) {
7359d482 2094 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2095 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2096 goto exit;
2097 }
2098 if (hcint & HCINTMSK_XACTERR) {
7359d482 2099 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2100 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2101 goto exit;
2102 }
2103 if (hcint & HCINTMSK_BBLERR) {
7359d482 2104 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2105 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2106 goto exit;
2107 }
2108 if (hcint & HCINTMSK_FRMOVRUN) {
7359d482 2109 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2110 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2111 goto exit;
2112 }
2113 if (hcint & HCINTMSK_DATATGLERR) {
7359d482 2114 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
dc873084
DA
2115 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2116 goto exit;
2117 }
7359d482 2118
dc873084 2119exit:
7359d482
PZ
2120 chan->hcint = 0;
2121}
2122
2123/*
2124 * This interrupt indicates that one or more host channels has a pending
2125 * interrupt. There are multiple conditions that can cause each host channel
2126 * interrupt. This function determines which conditions have occurred for each
2127 * host channel interrupt and handles them appropriately.
2128 */
2129static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2130{
2131 u32 haint;
2132 int i;
2133
95c8bc36 2134 haint = dwc2_readl(hsotg->regs + HAINT);
b49977a6
MK
2135 if (dbg_perio()) {
2136 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2137
2138 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2139 }
7359d482
PZ
2140
2141 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2142 if (haint & (1 << i))
2143 dwc2_hc_n_intr(hsotg, i);
2144 }
2145}
2146
2147/* This function handles interrupts for the HCD */
ca18f4a6 2148irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
7359d482 2149{
b49977a6 2150 u32 gintsts, dbg_gintsts;
6aafb003 2151 irqreturn_t retval = IRQ_NONE;
7359d482 2152
54216ace 2153 if (!dwc2_is_controller_alive(hsotg)) {
057715f2 2154 dev_warn(hsotg->dev, "Controller is dead\n");
6aafb003 2155 return retval;
7359d482
PZ
2156 }
2157
2158 spin_lock(&hsotg->lock);
2159
2160 /* Check if HOST Mode */
2161 if (dwc2_is_host_mode(hsotg)) {
2162 gintsts = dwc2_read_core_intr(hsotg);
2163 if (!gintsts) {
2164 spin_unlock(&hsotg->lock);
6aafb003 2165 return retval;
7359d482
PZ
2166 }
2167
6aafb003 2168 retval = IRQ_HANDLED;
7359d482 2169
b49977a6 2170 dbg_gintsts = gintsts;
7359d482 2171#ifndef DEBUG_SOF
b49977a6 2172 dbg_gintsts &= ~GINTSTS_SOF;
7359d482 2173#endif
b49977a6
MK
2174 if (!dbg_perio())
2175 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2176 GINTSTS_PTXFEMP);
2177
2178 /* Only print if there are any non-suppressed interrupts left */
2179 if (dbg_gintsts)
7359d482
PZ
2180 dev_vdbg(hsotg->dev,
2181 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2182 gintsts);
2183
2184 if (gintsts & GINTSTS_SOF)
2185 dwc2_sof_intr(hsotg);
2186 if (gintsts & GINTSTS_RXFLVL)
2187 dwc2_rx_fifo_level_intr(hsotg);
2188 if (gintsts & GINTSTS_NPTXFEMP)
2189 dwc2_np_tx_fifo_empty_intr(hsotg);
7359d482
PZ
2190 if (gintsts & GINTSTS_PRTINT)
2191 dwc2_port_intr(hsotg);
2192 if (gintsts & GINTSTS_HCHINT)
2193 dwc2_hc_intr(hsotg);
2194 if (gintsts & GINTSTS_PTXFEMP)
2195 dwc2_perio_tx_fifo_empty_intr(hsotg);
2196
b49977a6 2197 if (dbg_gintsts) {
7359d482
PZ
2198 dev_vdbg(hsotg->dev,
2199 "DWC OTG HCD Finished Servicing Interrupts\n");
2200 dev_vdbg(hsotg->dev,
2201 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
95c8bc36
AS
2202 dwc2_readl(hsotg->regs + GINTSTS),
2203 dwc2_readl(hsotg->regs + GINTMSK));
7359d482 2204 }
7359d482
PZ
2205 }
2206
2207 spin_unlock(&hsotg->lock);
2208
2209 return retval;
2210}