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usb: dwc2: Add params.c file
[mirror_ubuntu-hirsute-kernel.git] / drivers / usb / dwc2 / params.c
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323230ef
JY		 1/*
2 * Copyright (C) 2004-2016 Synopsys, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions, and the following disclaimer,
9 * without modification.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The names of the above-listed copyright holders may not be used
14 * to endorse or promote products derived from this software without
15 * specific prior written permission.
16 *
17 * ALTERNATIVELY, this software may be distributed under the terms of the
18 * GNU General Public License ("GPL") as published by the Free Software
19 * Foundation; either version 2 of the License, or (at your option) any
20 * later version.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/of_device.h>
38
39#include "core.h"
40
41static const struct dwc2_core_params params_hi6220 = {
42 .otg_cap = 2, /* No HNP/SRP capable */
43 .otg_ver = 0, /* 1.3 */
44 .dma_enable = 1,
45 .dma_desc_enable = 0,
46 .dma_desc_fs_enable = 0,
47 .speed = 0, /* High Speed */
48 .enable_dynamic_fifo = 1,
49 .en_multiple_tx_fifo = 1,
50 .host_rx_fifo_size = 512,
51 .host_nperio_tx_fifo_size = 512,
52 .host_perio_tx_fifo_size = 512,
53 .max_transfer_size = 65535,
54 .max_packet_count = 511,
55 .host_channels = 16,
56 .phy_type = 1, /* UTMI */
57 .phy_utmi_width = 8,
58 .phy_ulpi_ddr = 0, /* Single */
59 .phy_ulpi_ext_vbus = 0,
60 .i2c_enable = 0,
61 .ulpi_fs_ls = 0,
62 .host_support_fs_ls_low_power = 0,
63 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
64 .ts_dline = 0,
65 .reload_ctl = 0,
66 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
67 GAHBCFG_HBSTLEN_SHIFT,
68 .uframe_sched = 0,
69 .external_id_pin_ctl = -1,
70 .hibernation = -1,
71};
72
73static const struct dwc2_core_params params_bcm2835 = {
74 .otg_cap = 0, /* HNP/SRP capable */
75 .otg_ver = 0, /* 1.3 */
76 .dma_enable = 1,
77 .dma_desc_enable = 0,
78 .dma_desc_fs_enable = 0,
79 .speed = 0, /* High Speed */
80 .enable_dynamic_fifo = 1,
81 .en_multiple_tx_fifo = 1,
82 .host_rx_fifo_size = 774, /* 774 DWORDs */
83 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
84 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
85 .max_transfer_size = 65535,
86 .max_packet_count = 511,
87 .host_channels = 8,
88 .phy_type = 1, /* UTMI */
89 .phy_utmi_width = 8, /* 8 bits */
90 .phy_ulpi_ddr = 0, /* Single */
91 .phy_ulpi_ext_vbus = 0,
92 .i2c_enable = 0,
93 .ulpi_fs_ls = 0,
94 .host_support_fs_ls_low_power = 0,
95 .host_ls_low_power_phy_clk = 0, /* 48 MHz */
96 .ts_dline = 0,
97 .reload_ctl = 0,
98 .ahbcfg = 0x10,
99 .uframe_sched = 0,
100 .external_id_pin_ctl = -1,
101 .hibernation = -1,
102};
103
104static const struct dwc2_core_params params_rk3066 = {
105 .otg_cap = 2, /* non-HNP/non-SRP */
106 .otg_ver = -1,
107 .dma_enable = -1,
108 .dma_desc_enable = 0,
109 .dma_desc_fs_enable = 0,
110 .speed = -1,
111 .enable_dynamic_fifo = 1,
112 .en_multiple_tx_fifo = -1,
113 .host_rx_fifo_size = 525, /* 525 DWORDs */
114 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
115 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
116 .max_transfer_size = -1,
117 .max_packet_count = -1,
118 .host_channels = -1,
119 .phy_type = -1,
120 .phy_utmi_width = -1,
121 .phy_ulpi_ddr = -1,
122 .phy_ulpi_ext_vbus = -1,
123 .i2c_enable = -1,
124 .ulpi_fs_ls = -1,
125 .host_support_fs_ls_low_power = -1,
126 .host_ls_low_power_phy_clk = -1,
127 .ts_dline = -1,
128 .reload_ctl = -1,
129 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
130 GAHBCFG_HBSTLEN_SHIFT,
131 .uframe_sched = -1,
132 .external_id_pin_ctl = -1,
133 .hibernation = -1,
134};
135
136static const struct dwc2_core_params params_ltq = {
137 .otg_cap = 2, /* non-HNP/non-SRP */
138 .otg_ver = -1,
139 .dma_enable = -1,
140 .dma_desc_enable = -1,
141 .dma_desc_fs_enable = -1,
142 .speed = -1,
143 .enable_dynamic_fifo = -1,
144 .en_multiple_tx_fifo = -1,
145 .host_rx_fifo_size = 288, /* 288 DWORDs */
146 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
147 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
148 .max_transfer_size = 65535,
149 .max_packet_count = 511,
150 .host_channels = -1,
151 .phy_type = -1,
152 .phy_utmi_width = -1,
153 .phy_ulpi_ddr = -1,
154 .phy_ulpi_ext_vbus = -1,
155 .i2c_enable = -1,
156 .ulpi_fs_ls = -1,
157 .host_support_fs_ls_low_power = -1,
158 .host_ls_low_power_phy_clk = -1,
159 .ts_dline = -1,
160 .reload_ctl = -1,
161 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
162 GAHBCFG_HBSTLEN_SHIFT,
163 .uframe_sched = -1,
164 .external_id_pin_ctl = -1,
165 .hibernation = -1,
166};
167
168static const struct dwc2_core_params params_amlogic = {
169 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
170 .otg_ver = -1,
171 .dma_enable = 1,
172 .dma_desc_enable = 0,
173 .dma_desc_fs_enable = 0,
174 .speed = DWC2_SPEED_PARAM_HIGH,
175 .enable_dynamic_fifo = 1,
176 .en_multiple_tx_fifo = -1,
177 .host_rx_fifo_size = 512,
178 .host_nperio_tx_fifo_size = 500,
179 .host_perio_tx_fifo_size = 500,
180 .max_transfer_size = -1,
181 .max_packet_count = -1,
182 .host_channels = 16,
183 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
184 .phy_utmi_width = -1,
185 .phy_ulpi_ddr = -1,
186 .phy_ulpi_ext_vbus = -1,
187 .i2c_enable = -1,
188 .ulpi_fs_ls = -1,
189 .host_support_fs_ls_low_power = -1,
190 .host_ls_low_power_phy_clk = -1,
191 .ts_dline = -1,
192 .reload_ctl = 1,
193 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
194 GAHBCFG_HBSTLEN_SHIFT,
195 .uframe_sched = 0,
196 .external_id_pin_ctl = -1,
197 .hibernation = -1,
198};
199
200const struct of_device_id dwc2_of_match_table[] = {
201 { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
202 { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
203 { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
204 { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
205 { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
206 { .compatible = "snps,dwc2", .data = NULL },
207 { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
208 { .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
209 { .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
210 {},
211};
212MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
213
214#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
215
216/* Parameter access functions */
217void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
218{
219 int valid = 1;
220
221 switch (val) {
222 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
223 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
224 valid = 0;
225 break;
226 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
227 switch (hsotg->hw_params.op_mode) {
228 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
229 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
230 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
231 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
232 break;
233 default:
234 valid = 0;
235 break;
236 }
237 break;
238 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
239 /* always valid */
240 break;
241 default:
242 valid = 0;
243 break;
244 }
245
246 if (!valid) {
247 if (val >= 0)
248 dev_err(hsotg->dev,
249 "%d invalid for otg_cap parameter. Check HW configuration.\n",
250 val);
251 switch (hsotg->hw_params.op_mode) {
252 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
253 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
254 break;
255 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
256 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
257 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
258 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
259 break;
260 default:
261 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
262 break;
263 }
264 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
265 }
266
267 hsotg->core_params->otg_cap = val;
268}
269
270void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
271{
272 int valid = 1;
273
274 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
275 valid = 0;
276 if (val < 0)
277 valid = 0;
278
279 if (!valid) {
280 if (val >= 0)
281 dev_err(hsotg->dev,
282 "%d invalid for dma_enable parameter. Check HW configuration.\n",
283 val);
284 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
285 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
286 }
287
288 hsotg->core_params->dma_enable = val;
289}
290
291void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
292{
293 int valid = 1;
294
295 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
296 !hsotg->hw_params.dma_desc_enable))
297 valid = 0;
298 if (val < 0)
299 valid = 0;
300
301 if (!valid) {
302 if (val >= 0)
303 dev_err(hsotg->dev,
304 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
305 val);
306 val = (hsotg->core_params->dma_enable > 0 &&
307 hsotg->hw_params.dma_desc_enable);
308 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
309 }
310
311 hsotg->core_params->dma_desc_enable = val;
312}
313
314void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
315{
316 int valid = 1;
317
318 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
319 !hsotg->hw_params.dma_desc_enable))
320 valid = 0;
321 if (val < 0)
322 valid = 0;
323
324 if (!valid) {
325 if (val >= 0)
326 dev_err(hsotg->dev,
327 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
328 val);
329 val = (hsotg->core_params->dma_enable > 0 &&
330 hsotg->hw_params.dma_desc_enable);
331 }
332
333 hsotg->core_params->dma_desc_fs_enable = val;
334 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
335}
336
337void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
338 int val)
339{
340 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
341 if (val >= 0) {
342 dev_err(hsotg->dev,
343 "Wrong value for host_support_fs_low_power\n");
344 dev_err(hsotg->dev,
345 "host_support_fs_low_power must be 0 or 1\n");
346 }
347 val = 0;
348 dev_dbg(hsotg->dev,
349 "Setting host_support_fs_low_power to %d\n", val);
350 }
351
352 hsotg->core_params->host_support_fs_ls_low_power = val;
353}
354
355void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
356{
357 int valid = 1;
358
359 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
360 valid = 0;
361 if (val < 0)
362 valid = 0;
363
364 if (!valid) {
365 if (val >= 0)
366 dev_err(hsotg->dev,
367 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
368 val);
369 val = hsotg->hw_params.enable_dynamic_fifo;
370 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
371 }
372
373 hsotg->core_params->enable_dynamic_fifo = val;
374}
375
376void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
377{
378 int valid = 1;
379
380 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
381 valid = 0;
382
383 if (!valid) {
384 if (val >= 0)
385 dev_err(hsotg->dev,
386 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
387 val);
388 val = hsotg->hw_params.host_rx_fifo_size;
389 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
390 }
391
392 hsotg->core_params->host_rx_fifo_size = val;
393}
394
395void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
396{
397 int valid = 1;
398
399 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
400 valid = 0;
401
402 if (!valid) {
403 if (val >= 0)
404 dev_err(hsotg->dev,
405 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
406 val);
407 val = hsotg->hw_params.host_nperio_tx_fifo_size;
408 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
409 val);
410 }
411
412 hsotg->core_params->host_nperio_tx_fifo_size = val;
413}
414
415void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
416{
417 int valid = 1;
418
419 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
420 valid = 0;
421
422 if (!valid) {
423 if (val >= 0)
424 dev_err(hsotg->dev,
425 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
426 val);
427 val = hsotg->hw_params.host_perio_tx_fifo_size;
428 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
429 val);
430 }
431
432 hsotg->core_params->host_perio_tx_fifo_size = val;
433}
434
435void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
436{
437 int valid = 1;
438
439 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
440 valid = 0;
441
442 if (!valid) {
443 if (val >= 0)
444 dev_err(hsotg->dev,
445 "%d invalid for max_transfer_size. Check HW configuration.\n",
446 val);
447 val = hsotg->hw_params.max_transfer_size;
448 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
449 }
450
451 hsotg->core_params->max_transfer_size = val;
452}
453
454void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
455{
456 int valid = 1;
457
458 if (val < 15 || val > hsotg->hw_params.max_packet_count)
459 valid = 0;
460
461 if (!valid) {
462 if (val >= 0)
463 dev_err(hsotg->dev,
464 "%d invalid for max_packet_count. Check HW configuration.\n",
465 val);
466 val = hsotg->hw_params.max_packet_count;
467 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
468 }
469
470 hsotg->core_params->max_packet_count = val;
471}
472
473void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
474{
475 int valid = 1;
476
477 if (val < 1 || val > hsotg->hw_params.host_channels)
478 valid = 0;
479
480 if (!valid) {
481 if (val >= 0)
482 dev_err(hsotg->dev,
483 "%d invalid for host_channels. Check HW configuration.\n",
484 val);
485 val = hsotg->hw_params.host_channels;
486 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
487 }
488
489 hsotg->core_params->host_channels = val;
490}
491
492void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
493{
494 int valid = 0;
495 u32 hs_phy_type, fs_phy_type;
496
497 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
498 DWC2_PHY_TYPE_PARAM_ULPI)) {
499 if (val >= 0) {
500 dev_err(hsotg->dev, "Wrong value for phy_type\n");
501 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
502 }
503
504 valid = 0;
505 }
506
507 hs_phy_type = hsotg->hw_params.hs_phy_type;
508 fs_phy_type = hsotg->hw_params.fs_phy_type;
509 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
510 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
511 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
512 valid = 1;
513 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
514 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
515 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
516 valid = 1;
517 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
518 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
519 valid = 1;
520
521 if (!valid) {
522 if (val >= 0)
523 dev_err(hsotg->dev,
524 "%d invalid for phy_type. Check HW configuration.\n",
525 val);
526 val = DWC2_PHY_TYPE_PARAM_FS;
527 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
528 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
529 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
530 val = DWC2_PHY_TYPE_PARAM_UTMI;
531 else
532 val = DWC2_PHY_TYPE_PARAM_ULPI;
533 }
534 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
535 }
536
537 hsotg->core_params->phy_type = val;
538}
539
540static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
541{
542 return hsotg->core_params->phy_type;
543}
544
545void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
546{
547 int valid = 1;
548
549 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
550 if (val >= 0) {
551 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
552 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
553 }
554 valid = 0;
555 }
556
557 if (val == DWC2_SPEED_PARAM_HIGH &&
558 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
559 valid = 0;
560
561 if (!valid) {
562 if (val >= 0)
563 dev_err(hsotg->dev,
564 "%d invalid for speed parameter. Check HW configuration.\n",
565 val);
566 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
567 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
568 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
569 }
570
571 hsotg->core_params->speed = val;
572}
573
574void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
575{
576 int valid = 1;
577
578 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
579 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
580 if (val >= 0) {
581 dev_err(hsotg->dev,
582 "Wrong value for host_ls_low_power_phy_clk parameter\n");
583 dev_err(hsotg->dev,
584 "host_ls_low_power_phy_clk must be 0 or 1\n");
585 }
586 valid = 0;
587 }
588
589 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
590 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
591 valid = 0;
592
593 if (!valid) {
594 if (val >= 0)
595 dev_err(hsotg->dev,
596 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
597 val);
598 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
599 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
600 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
601 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
602 val);
603 }
604
605 hsotg->core_params->host_ls_low_power_phy_clk = val;
606}
607
608void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
609{
610 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
611 if (val >= 0) {
612 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
613 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
614 }
615 val = 0;
616 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
617 }
618
619 hsotg->core_params->phy_ulpi_ddr = val;
620}
621
622void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
623{
624 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
625 if (val >= 0) {
626 dev_err(hsotg->dev,
627 "Wrong value for phy_ulpi_ext_vbus\n");
628 dev_err(hsotg->dev,
629 "phy_ulpi_ext_vbus must be 0 or 1\n");
630 }
631 val = 0;
632 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
633 }
634
635 hsotg->core_params->phy_ulpi_ext_vbus = val;
636}
637
638void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
639{
640 int valid = 0;
641
642 switch (hsotg->hw_params.utmi_phy_data_width) {
643 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
644 valid = (val == 8);
645 break;
646 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
647 valid = (val == 16);
648 break;
649 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
650 valid = (val == 8 || val == 16);
651 break;
652 }
653
654 if (!valid) {
655 if (val >= 0) {
656 dev_err(hsotg->dev,
657 "%d invalid for phy_utmi_width. Check HW configuration.\n",
658 val);
659 }
660 val = (hsotg->hw_params.utmi_phy_data_width ==
661 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
662 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
663 }
664
665 hsotg->core_params->phy_utmi_width = val;
666}
667
668void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
669{
670 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
671 if (val >= 0) {
672 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
673 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
674 }
675 val = 0;
676 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
677 }
678
679 hsotg->core_params->ulpi_fs_ls = val;
680}
681
682void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
683{
684 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
685 if (val >= 0) {
686 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
687 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
688 }
689 val = 0;
690 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
691 }
692
693 hsotg->core_params->ts_dline = val;
694}
695
696void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
697{
698 int valid = 1;
699
700 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
701 if (val >= 0) {
702 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
703 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
704 }
705
706 valid = 0;
707 }
708
709 if (val == 1 && !(hsotg->hw_params.i2c_enable))
710 valid = 0;
711
712 if (!valid) {
713 if (val >= 0)
714 dev_err(hsotg->dev,
715 "%d invalid for i2c_enable. Check HW configuration.\n",
716 val);
717 val = hsotg->hw_params.i2c_enable;
718 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
719 }
720
721 hsotg->core_params->i2c_enable = val;
722}
723
724void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
725{
726 int valid = 1;
727
728 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
729 if (val >= 0) {
730 dev_err(hsotg->dev,
731 "Wrong value for en_multiple_tx_fifo,\n");
732 dev_err(hsotg->dev,
733 "en_multiple_tx_fifo must be 0 or 1\n");
734 }
735 valid = 0;
736 }
737
738 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
739 valid = 0;
740
741 if (!valid) {
742 if (val >= 0)
743 dev_err(hsotg->dev,
744 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
745 val);
746 val = hsotg->hw_params.en_multiple_tx_fifo;
747 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
748 }
749
750 hsotg->core_params->en_multiple_tx_fifo = val;
751}
752
753void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
754{
755 int valid = 1;
756
757 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
758 if (val >= 0) {
759 dev_err(hsotg->dev,
760 "'%d' invalid for parameter reload_ctl\n", val);
761 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
762 }
763 valid = 0;
764 }
765
766 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
767 valid = 0;
768
769 if (!valid) {
770 if (val >= 0)
771 dev_err(hsotg->dev,
772 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
773 val);
774 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
775 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
776 }
777
778 hsotg->core_params->reload_ctl = val;
779}
780
781void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
782{
783 if (val != -1)
784 hsotg->core_params->ahbcfg = val;
785 else
786 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
787 GAHBCFG_HBSTLEN_SHIFT;
788}
789
790void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
791{
792 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
793 if (val >= 0) {
794 dev_err(hsotg->dev,
795 "'%d' invalid for parameter otg_ver\n", val);
796 dev_err(hsotg->dev,
797 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
798 }
799 val = 0;
800 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
801 }
802
803 hsotg->core_params->otg_ver = val;
804}
805
806static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
807{
808 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
809 if (val >= 0) {
810 dev_err(hsotg->dev,
811 "'%d' invalid for parameter uframe_sched\n",
812 val);
813 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
814 }
815 val = 1;
816 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
817 }
818
819 hsotg->core_params->uframe_sched = val;
820}
821
822static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
823 int val)
824{
825 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
826 if (val >= 0) {
827 dev_err(hsotg->dev,
828 "'%d' invalid for parameter external_id_pin_ctl\n",
829 val);
830 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
831 }
832 val = 0;
833 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
834 }
835
836 hsotg->core_params->external_id_pin_ctl = val;
837}
838
839static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
840 int val)
841{
842 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
843 if (val >= 0) {
844 dev_err(hsotg->dev,
845 "'%d' invalid for parameter hibernation\n",
846 val);
847 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
848 }
849 val = 0;
850 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
851 }
852
853 hsotg->core_params->hibernation = val;
854}
855
856/*
857 * This function is called during module intialization to pass module parameters
858 * for the DWC_otg core.
859 */
860void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
861 const struct dwc2_core_params *params)
862{
863 dev_dbg(hsotg->dev, "%s()\n", __func__);
864
865 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
866 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
867 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
868 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
869 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
870 params->host_support_fs_ls_low_power);
871 dwc2_set_param_enable_dynamic_fifo(hsotg,
872 params->enable_dynamic_fifo);
873 dwc2_set_param_host_rx_fifo_size(hsotg,
874 params->host_rx_fifo_size);
875 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
876 params->host_nperio_tx_fifo_size);
877 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
878 params->host_perio_tx_fifo_size);
879 dwc2_set_param_max_transfer_size(hsotg,
880 params->max_transfer_size);
881 dwc2_set_param_max_packet_count(hsotg,
882 params->max_packet_count);
883 dwc2_set_param_host_channels(hsotg, params->host_channels);
884 dwc2_set_param_phy_type(hsotg, params->phy_type);
885 dwc2_set_param_speed(hsotg, params->speed);
886 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
887 params->host_ls_low_power_phy_clk);
888 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
889 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
890 params->phy_ulpi_ext_vbus);
891 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
892 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
893 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
894 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
895 dwc2_set_param_en_multiple_tx_fifo(hsotg,
896 params->en_multiple_tx_fifo);
897 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
898 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
899 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
900 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
901 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
902 dwc2_set_param_hibernation(hsotg, params->hibernation);
903}
904
905/*
906 * Gets host hardware parameters. Forces host mode if not currently in
907 * host mode. Should be called immediately after a core soft reset in
908 * order to get the reset values.
909 */
910static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
911{
912 struct dwc2_hw_params *hw = &hsotg->hw_params;
913 u32 gnptxfsiz;
914 u32 hptxfsiz;
915 bool forced;
916
917 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
918 return;
919
920 forced = dwc2_force_mode_if_needed(hsotg, true);
921
922 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
923 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
924 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
925 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
926
927 if (forced)
928 dwc2_clear_force_mode(hsotg);
929
930 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
931 FIFOSIZE_DEPTH_SHIFT;
932 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
933 FIFOSIZE_DEPTH_SHIFT;
934}
935
936/*
937 * Gets device hardware parameters. Forces device mode if not
938 * currently in device mode. Should be called immediately after a core
939 * soft reset in order to get the reset values.
940 */
941static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
942{
943 struct dwc2_hw_params *hw = &hsotg->hw_params;
944 bool forced;
945 u32 gnptxfsiz;
946
947 if (hsotg->dr_mode == USB_DR_MODE_HOST)
948 return;
949
950 forced = dwc2_force_mode_if_needed(hsotg, false);
951
952 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
953 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
954
955 if (forced)
956 dwc2_clear_force_mode(hsotg);
957
958 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
959 FIFOSIZE_DEPTH_SHIFT;
960}
961
962/**
963 * During device initialization, read various hardware configuration
964 * registers and interpret the contents.
965 */
966int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
967{
968 struct dwc2_hw_params *hw = &hsotg->hw_params;
969 unsigned int width;
970 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
971 u32 grxfsiz;
972
973 /*
974 * Attempt to ensure this device is really a DWC_otg Controller.
975 * Read and verify the GSNPSID register contents. The value should be
976 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
977 * as in "OTG version 2.xx" or "OTG version 3.xx".
978 */
979 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
980 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
981 (hw->snpsid & 0xfffff000) != 0x4f543000) {
982 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
983 hw->snpsid);
984 return -ENODEV;
985 }
986
987 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
988 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
989 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
990
991 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
992 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
993 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
994 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
995 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
996
997 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
998 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
999 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
1000 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
1001 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
1002
1003 /*
1004 * Host specific hardware parameters. Reading these parameters
1005 * requires the controller to be in host mode. The mode will
1006 * be forced, if necessary, to read these values.
1007 */
1008 dwc2_get_host_hwparams(hsotg);
1009 dwc2_get_dev_hwparams(hsotg);
1010
1011 /* hwcfg1 */
1012 hw->dev_ep_dirs = hwcfg1;
1013
1014 /* hwcfg2 */
1015 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
1016 GHWCFG2_OP_MODE_SHIFT;
1017 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
1018 GHWCFG2_ARCHITECTURE_SHIFT;
1019 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
1020 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
1021 GHWCFG2_NUM_HOST_CHAN_SHIFT);
1022 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
1023 GHWCFG2_HS_PHY_TYPE_SHIFT;
1024 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
1025 GHWCFG2_FS_PHY_TYPE_SHIFT;
1026 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
1027 GHWCFG2_NUM_DEV_EP_SHIFT;
1028 hw->nperio_tx_q_depth =
1029 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
1030 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
1031 hw->host_perio_tx_q_depth =
1032 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
1033 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
1034 hw->dev_token_q_depth =
1035 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
1036 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
1037
1038 /* hwcfg3 */
1039 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
1040 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
1041 hw->max_transfer_size = (1 << (width + 11)) - 1;
1042 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
1043 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
1044 hw->max_packet_count = (1 << (width + 4)) - 1;
1045 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
1046 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1047 GHWCFG3_DFIFO_DEPTH_SHIFT;
1048
1049 /* hwcfg4 */
1050 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1051 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1052 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1053 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1054 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1055 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1056 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1057
1058 /* fifo sizes */
1059 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1060 GRXFSIZ_DEPTH_SHIFT;
1061
1062 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
1063 dev_dbg(hsotg->dev, " op_mode=%d\n",
1064 hw->op_mode);
1065 dev_dbg(hsotg->dev, " arch=%d\n",
1066 hw->arch);
1067 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
1068 hw->dma_desc_enable);
1069 dev_dbg(hsotg->dev, " power_optimized=%d\n",
1070 hw->power_optimized);
1071 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
1072 hw->i2c_enable);
1073 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
1074 hw->hs_phy_type);
1075 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
1076 hw->fs_phy_type);
1077 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
1078 hw->utmi_phy_data_width);
1079 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
1080 hw->num_dev_ep);
1081 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
1082 hw->num_dev_perio_in_ep);
1083 dev_dbg(hsotg->dev, " host_channels=%d\n",
1084 hw->host_channels);
1085 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
1086 hw->max_transfer_size);
1087 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
1088 hw->max_packet_count);
1089 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
1090 hw->nperio_tx_q_depth);
1091 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
1092 hw->host_perio_tx_q_depth);
1093 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
1094 hw->dev_token_q_depth);
1095 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
1096 hw->enable_dynamic_fifo);
1097 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
1098 hw->en_multiple_tx_fifo);
1099 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
1100 hw->total_fifo_size);
1101 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
1102 hw->host_rx_fifo_size);
1103 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
1104 hw->host_nperio_tx_fifo_size);
1105 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
1106 hw->host_perio_tx_fifo_size);
1107 dev_dbg(hsotg->dev, "\n");
1108
1109 return 0;
1110}
1111
1112/*
1113 * Sets all parameters to the given value.
1114 *
1115 * Assumes that the dwc2_core_params struct contains only integers.
1116 */
1117void dwc2_set_all_params(struct dwc2_core_params *params, int value)
1118{
1119 int *p = (int *)params;
1120 size_t size = sizeof(*params) / sizeof(*p);
1121 int i;
1122
1123 for (i = 0; i < size; i++)
1124 p[i] = value;
1125}
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