]>
Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
323230ef JY |
2 | /* |
3 | * Copyright (C) 2004-2016 Synopsys, Inc. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions | |
7 | * are met: | |
8 | * 1. Redistributions of source code must retain the above copyright | |
9 | * notice, this list of conditions, and the following disclaimer, | |
10 | * without modification. | |
11 | * 2. Redistributions in binary form must reproduce the above copyright | |
12 | * notice, this list of conditions and the following disclaimer in the | |
13 | * documentation and/or other materials provided with the distribution. | |
14 | * 3. The names of the above-listed copyright holders may not be used | |
15 | * to endorse or promote products derived from this software without | |
16 | * specific prior written permission. | |
17 | * | |
18 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
19 | * GNU General Public License ("GPL") as published by the Free Software | |
20 | * Foundation; either version 2 of the License, or (at your option) any | |
21 | * later version. | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
24 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
25 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
26 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
27 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
28 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
29 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
30 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
31 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
32 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/module.h> | |
38 | #include <linux/of_device.h> | |
39 | ||
40 | #include "core.h" | |
41 | ||
7de1debc JY |
42 | static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) |
43 | { | |
44 | struct dwc2_core_params *p = &hsotg->params; | |
323230ef | 45 | |
7de1debc | 46 | p->host_rx_fifo_size = 774; |
7de1debc JY |
47 | p->max_transfer_size = 65535; |
48 | p->max_packet_count = 511; | |
7de1debc JY |
49 | p->ahbcfg = 0x10; |
50 | p->uframe_sched = false; | |
51 | } | |
323230ef | 52 | |
7de1debc JY |
53 | static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) |
54 | { | |
55 | struct dwc2_core_params *p = &hsotg->params; | |
323230ef | 56 | |
7de1debc JY |
57 | p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; |
58 | p->speed = DWC2_SPEED_PARAM_HIGH; | |
59 | p->host_rx_fifo_size = 512; | |
60 | p->host_nperio_tx_fifo_size = 512; | |
61 | p->host_perio_tx_fifo_size = 512; | |
62 | p->max_transfer_size = 65535; | |
63 | p->max_packet_count = 511; | |
64 | p->host_channels = 16; | |
65 | p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; | |
66 | p->phy_utmi_width = 8; | |
67 | p->i2c_enable = false; | |
7de1debc JY |
68 | p->reload_ctl = false; |
69 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
70 | GAHBCFG_HBSTLEN_SHIFT; | |
71 | p->uframe_sched = false; | |
ca8b0332 | 72 | p->change_speed_quirk = true; |
7de1debc | 73 | } |
323230ef | 74 | |
7de1debc JY |
75 | static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) |
76 | { | |
77 | struct dwc2_core_params *p = &hsotg->params; | |
78 | ||
79 | p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; | |
80 | p->host_rx_fifo_size = 525; | |
81 | p->host_nperio_tx_fifo_size = 128; | |
82 | p->host_perio_tx_fifo_size = 256; | |
83 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
84 | GAHBCFG_HBSTLEN_SHIFT; | |
85 | } | |
86 | ||
87 | static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) | |
88 | { | |
89 | struct dwc2_core_params *p = &hsotg->params; | |
90 | ||
91 | p->otg_cap = 2; | |
92 | p->host_rx_fifo_size = 288; | |
93 | p->host_nperio_tx_fifo_size = 128; | |
94 | p->host_perio_tx_fifo_size = 96; | |
95 | p->max_transfer_size = 65535; | |
96 | p->max_packet_count = 511; | |
97 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << | |
98 | GAHBCFG_HBSTLEN_SHIFT; | |
99 | } | |
100 | ||
101 | static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) | |
102 | { | |
103 | struct dwc2_core_params *p = &hsotg->params; | |
104 | ||
105 | p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; | |
106 | p->speed = DWC2_SPEED_PARAM_HIGH; | |
107 | p->host_rx_fifo_size = 512; | |
108 | p->host_nperio_tx_fifo_size = 500; | |
109 | p->host_perio_tx_fifo_size = 500; | |
110 | p->host_channels = 16; | |
111 | p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; | |
112 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << | |
113 | GAHBCFG_HBSTLEN_SHIFT; | |
114 | p->uframe_sched = false; | |
115 | } | |
116 | ||
117 | static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) | |
118 | { | |
119 | struct dwc2_core_params *p = &hsotg->params; | |
120 | ||
121 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; | |
122 | } | |
323230ef | 123 | |
e35b1350 BH |
124 | static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) |
125 | { | |
126 | struct dwc2_core_params *p = &hsotg->params; | |
127 | ||
128 | p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; | |
129 | p->speed = DWC2_SPEED_PARAM_FULL; | |
130 | p->host_rx_fifo_size = 128; | |
131 | p->host_nperio_tx_fifo_size = 96; | |
132 | p->host_perio_tx_fifo_size = 96; | |
133 | p->max_packet_count = 256; | |
134 | p->phy_type = DWC2_PHY_TYPE_PARAM_FS; | |
135 | p->i2c_enable = false; | |
136 | p->uframe_sched = false; | |
137 | p->activate_stm_fs_transceiver = true; | |
138 | } | |
139 | ||
1a149e35 | 140 | static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) |
d8fae8b9 AD |
141 | { |
142 | struct dwc2_core_params *p = &hsotg->params; | |
143 | ||
144 | p->host_rx_fifo_size = 622; | |
145 | p->host_nperio_tx_fifo_size = 128; | |
146 | p->host_perio_tx_fifo_size = 256; | |
147 | } | |
148 | ||
323230ef | 149 | const struct of_device_id dwc2_of_match_table[] = { |
7de1debc JY |
150 | { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, |
151 | { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, | |
152 | { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, | |
153 | { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, | |
154 | { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, | |
155 | { .compatible = "snps,dwc2" }, | |
156 | { .compatible = "samsung,s3c6400-hsotg" }, | |
55b644fd MB |
157 | { .compatible = "amlogic,meson8-usb", |
158 | .data = dwc2_set_amlogic_params }, | |
7de1debc JY |
159 | { .compatible = "amlogic,meson8b-usb", |
160 | .data = dwc2_set_amlogic_params }, | |
161 | { .compatible = "amlogic,meson-gxbb-usb", | |
162 | .data = dwc2_set_amlogic_params }, | |
163 | { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, | |
e35b1350 BH |
164 | { .compatible = "st,stm32f4x9-fsotg", |
165 | .data = dwc2_set_stm32f4x9_fsotg_params }, | |
166 | { .compatible = "st,stm32f4x9-hsotg" }, | |
1a149e35 AD |
167 | { .compatible = "st,stm32f7-hsotg", |
168 | .data = dwc2_set_stm32f7_hsotg_params }, | |
323230ef JY |
169 | {}, |
170 | }; | |
171 | MODULE_DEVICE_TABLE(of, dwc2_of_match_table); | |
172 | ||
245977c9 | 173 | static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) |
05ee799f | 174 | { |
245977c9 | 175 | u8 val; |
05ee799f | 176 | |
245977c9 JY |
177 | switch (hsotg->hw_params.op_mode) { |
178 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: | |
179 | val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; | |
05ee799f | 180 | break; |
245977c9 JY |
181 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
182 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: | |
183 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: | |
184 | val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; | |
05ee799f JY |
185 | break; |
186 | default: | |
245977c9 | 187 | val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; |
05ee799f | 188 | break; |
323230ef JY |
189 | } |
190 | ||
bea8e86c | 191 | hsotg->params.otg_cap = val; |
323230ef JY |
192 | } |
193 | ||
245977c9 | 194 | static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) |
323230ef | 195 | { |
245977c9 JY |
196 | int val; |
197 | u32 hs_phy_type = hsotg->hw_params.hs_phy_type; | |
323230ef | 198 | |
245977c9 JY |
199 | val = DWC2_PHY_TYPE_PARAM_FS; |
200 | if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { | |
201 | if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || | |
202 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) | |
203 | val = DWC2_PHY_TYPE_PARAM_UTMI; | |
204 | else | |
205 | val = DWC2_PHY_TYPE_PARAM_ULPI; | |
323230ef JY |
206 | } |
207 | ||
245977c9 JY |
208 | if (dwc2_is_fs_iot(hsotg)) |
209 | hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; | |
323230ef | 210 | |
bea8e86c | 211 | hsotg->params.phy_type = val; |
323230ef JY |
212 | } |
213 | ||
245977c9 | 214 | static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) |
323230ef | 215 | { |
245977c9 | 216 | int val; |
323230ef | 217 | |
245977c9 JY |
218 | val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? |
219 | DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; | |
323230ef | 220 | |
245977c9 JY |
221 | if (dwc2_is_fs_iot(hsotg)) |
222 | val = DWC2_SPEED_PARAM_FULL; | |
38e9002b | 223 | |
245977c9 JY |
224 | if (dwc2_is_hs_iot(hsotg)) |
225 | val = DWC2_SPEED_PARAM_HIGH; | |
323230ef | 226 | |
bea8e86c | 227 | hsotg->params.speed = val; |
323230ef JY |
228 | } |
229 | ||
245977c9 | 230 | static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) |
323230ef | 231 | { |
245977c9 | 232 | int val; |
323230ef | 233 | |
245977c9 JY |
234 | val = (hsotg->hw_params.utmi_phy_data_width == |
235 | GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; | |
323230ef | 236 | |
bea8e86c | 237 | hsotg->params.phy_utmi_width = val; |
323230ef JY |
238 | } |
239 | ||
05ee799f JY |
240 | static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) |
241 | { | |
05ee799f | 242 | struct dwc2_core_params *p = &hsotg->params; |
c138ecfa SA |
243 | int depth_average; |
244 | int fifo_count; | |
245 | int i; | |
246 | ||
247 | fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
05ee799f JY |
248 | |
249 | memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); | |
c138ecfa SA |
250 | depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); |
251 | for (i = 1; i <= fifo_count; i++) | |
252 | p->g_tx_fifo_size[i] = depth_average; | |
9962b62f JY |
253 | } |
254 | ||
05ee799f | 255 | /** |
245977c9 JY |
256 | * dwc2_set_default_params() - Set all core parameters to their |
257 | * auto-detected default values. | |
323230ef | 258 | */ |
245977c9 | 259 | static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) |
323230ef | 260 | { |
05ee799f JY |
261 | struct dwc2_hw_params *hw = &hsotg->hw_params; |
262 | struct dwc2_core_params *p = &hsotg->params; | |
6b66ce51 | 263 | bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); |
323230ef | 264 | |
245977c9 JY |
265 | dwc2_set_param_otg_cap(hsotg); |
266 | dwc2_set_param_phy_type(hsotg); | |
267 | dwc2_set_param_speed(hsotg); | |
268 | dwc2_set_param_phy_utmi_width(hsotg); | |
269 | p->phy_ulpi_ddr = false; | |
270 | p->phy_ulpi_ext_vbus = false; | |
271 | ||
272 | p->enable_dynamic_fifo = hw->enable_dynamic_fifo; | |
273 | p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; | |
274 | p->i2c_enable = hw->i2c_enable; | |
275 | p->ulpi_fs_ls = false; | |
276 | p->ts_dline = false; | |
277 | p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); | |
278 | p->uframe_sched = true; | |
279 | p->external_id_pin_ctl = false; | |
280 | p->hibernation = false; | |
281 | p->max_packet_count = hw->max_packet_count; | |
282 | p->max_transfer_size = hw->max_transfer_size; | |
283 | p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; | |
284 | ||
6b66ce51 JY |
285 | if ((hsotg->dr_mode == USB_DR_MODE_HOST) || |
286 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
245977c9 JY |
287 | p->host_dma = dma_capable; |
288 | p->dma_desc_enable = false; | |
289 | p->dma_desc_fs_enable = false; | |
290 | p->host_support_fs_ls_low_power = false; | |
291 | p->host_ls_low_power_phy_clk = false; | |
292 | p->host_channels = hw->host_channels; | |
293 | p->host_rx_fifo_size = hw->rx_fifo_size; | |
294 | p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; | |
295 | p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; | |
6b66ce51 JY |
296 | } |
297 | ||
05ee799f JY |
298 | if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || |
299 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
245977c9 JY |
300 | p->g_dma = dma_capable; |
301 | p->g_dma_desc = hw->dma_desc_enable; | |
05ee799f JY |
302 | |
303 | /* | |
304 | * The values for g_rx_fifo_size (2048) and | |
305 | * g_np_tx_fifo_size (1024) come from the legacy s3c | |
306 | * gadget driver. These defaults have been hard-coded | |
307 | * for some time so many platforms depend on these | |
308 | * values. Leave them as defaults for now and only | |
309 | * auto-detect if the hardware does not support the | |
310 | * default. | |
311 | */ | |
245977c9 JY |
312 | p->g_rx_fifo_size = 2048; |
313 | p->g_np_tx_fifo_size = 1024; | |
05ee799f JY |
314 | dwc2_set_param_tx_fifo_sizes(hsotg); |
315 | } | |
323230ef JY |
316 | } |
317 | ||
f9f93cbb JY |
318 | /** |
319 | * dwc2_get_device_properties() - Read in device properties. | |
320 | * | |
321 | * Read in the device properties and adjust core parameters if needed. | |
322 | */ | |
323 | static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) | |
324 | { | |
325 | struct dwc2_core_params *p = &hsotg->params; | |
326 | int num; | |
327 | ||
328 | if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || | |
329 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
330 | device_property_read_u32(hsotg->dev, "g-rx-fifo-size", | |
331 | &p->g_rx_fifo_size); | |
332 | ||
333 | device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", | |
334 | &p->g_np_tx_fifo_size); | |
335 | ||
336 | num = device_property_read_u32_array(hsotg->dev, | |
337 | "g-tx-fifo-size", | |
338 | NULL, 0); | |
339 | ||
340 | if (num > 0) { | |
341 | num = min(num, 15); | |
342 | memset(p->g_tx_fifo_size, 0, | |
343 | sizeof(p->g_tx_fifo_size)); | |
344 | device_property_read_u32_array(hsotg->dev, | |
345 | "g-tx-fifo-size", | |
346 | &p->g_tx_fifo_size[1], | |
347 | num); | |
348 | } | |
349 | } | |
b11633c4 DN |
350 | |
351 | if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) | |
352 | p->oc_disable = true; | |
f9f93cbb JY |
353 | } |
354 | ||
d936e666 JY |
355 | static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) |
356 | { | |
357 | int valid = 1; | |
358 | ||
359 | switch (hsotg->params.otg_cap) { | |
360 | case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: | |
361 | if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) | |
362 | valid = 0; | |
363 | break; | |
364 | case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: | |
365 | switch (hsotg->hw_params.op_mode) { | |
366 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: | |
367 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: | |
368 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: | |
369 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: | |
370 | break; | |
371 | default: | |
372 | valid = 0; | |
373 | break; | |
374 | } | |
375 | break; | |
376 | case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: | |
377 | /* always valid */ | |
378 | break; | |
379 | default: | |
380 | valid = 0; | |
381 | break; | |
382 | } | |
383 | ||
384 | if (!valid) | |
385 | dwc2_set_param_otg_cap(hsotg); | |
386 | } | |
387 | ||
388 | static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) | |
389 | { | |
390 | int valid = 0; | |
391 | u32 hs_phy_type; | |
392 | u32 fs_phy_type; | |
393 | ||
394 | hs_phy_type = hsotg->hw_params.hs_phy_type; | |
395 | fs_phy_type = hsotg->hw_params.fs_phy_type; | |
396 | ||
397 | switch (hsotg->params.phy_type) { | |
398 | case DWC2_PHY_TYPE_PARAM_FS: | |
399 | if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) | |
400 | valid = 1; | |
401 | break; | |
402 | case DWC2_PHY_TYPE_PARAM_UTMI: | |
403 | if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || | |
404 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) | |
405 | valid = 1; | |
406 | break; | |
407 | case DWC2_PHY_TYPE_PARAM_ULPI: | |
408 | if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || | |
409 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) | |
410 | valid = 1; | |
411 | break; | |
412 | default: | |
413 | break; | |
414 | } | |
415 | ||
416 | if (!valid) | |
417 | dwc2_set_param_phy_type(hsotg); | |
418 | } | |
419 | ||
420 | static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) | |
421 | { | |
422 | int valid = 1; | |
423 | int phy_type = hsotg->params.phy_type; | |
424 | int speed = hsotg->params.speed; | |
425 | ||
426 | switch (speed) { | |
427 | case DWC2_SPEED_PARAM_HIGH: | |
428 | if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && | |
429 | (phy_type == DWC2_PHY_TYPE_PARAM_FS)) | |
430 | valid = 0; | |
431 | break; | |
432 | case DWC2_SPEED_PARAM_FULL: | |
433 | case DWC2_SPEED_PARAM_LOW: | |
434 | break; | |
435 | default: | |
436 | valid = 0; | |
437 | break; | |
438 | } | |
439 | ||
440 | if (!valid) | |
441 | dwc2_set_param_speed(hsotg); | |
442 | } | |
443 | ||
444 | static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) | |
445 | { | |
446 | int valid = 0; | |
447 | int param = hsotg->params.phy_utmi_width; | |
448 | int width = hsotg->hw_params.utmi_phy_data_width; | |
449 | ||
450 | switch (width) { | |
451 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: | |
452 | valid = (param == 8); | |
453 | break; | |
454 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: | |
455 | valid = (param == 16); | |
456 | break; | |
457 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: | |
458 | valid = (param == 8 || param == 16); | |
459 | break; | |
460 | } | |
461 | ||
462 | if (!valid) | |
463 | dwc2_set_param_phy_utmi_width(hsotg); | |
464 | } | |
465 | ||
3c6aea73 SA |
466 | static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) |
467 | { | |
468 | int fifo_count; | |
469 | int fifo; | |
470 | int min; | |
471 | u32 total = 0; | |
472 | u32 dptxfszn; | |
473 | ||
474 | fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
475 | min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; | |
476 | ||
477 | for (fifo = 1; fifo <= fifo_count; fifo++) | |
478 | total += hsotg->params.g_tx_fifo_size[fifo]; | |
479 | ||
480 | if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { | |
481 | dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", | |
482 | __func__); | |
483 | dwc2_set_param_tx_fifo_sizes(hsotg); | |
484 | } | |
485 | ||
486 | for (fifo = 1; fifo <= fifo_count; fifo++) { | |
9273083a | 487 | dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; |
3c6aea73 SA |
488 | |
489 | if (hsotg->params.g_tx_fifo_size[fifo] < min || | |
490 | hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { | |
491 | dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", | |
492 | __func__, fifo, | |
493 | hsotg->params.g_tx_fifo_size[fifo]); | |
494 | hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; | |
495 | } | |
496 | } | |
497 | } | |
498 | ||
d936e666 JY |
499 | #define CHECK_RANGE(_param, _min, _max, _def) do { \ |
500 | if ((hsotg->params._param) < (_min) || \ | |
501 | (hsotg->params._param) > (_max)) { \ | |
502 | dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ | |
503 | __func__, #_param, hsotg->params._param); \ | |
504 | hsotg->params._param = (_def); \ | |
505 | } \ | |
506 | } while (0) | |
507 | ||
508 | #define CHECK_BOOL(_param, _check) do { \ | |
509 | if (hsotg->params._param && !(_check)) { \ | |
510 | dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ | |
511 | __func__, #_param, hsotg->params._param); \ | |
512 | hsotg->params._param = false; \ | |
513 | } \ | |
514 | } while (0) | |
515 | ||
516 | static void dwc2_check_params(struct dwc2_hsotg *hsotg) | |
517 | { | |
518 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
519 | struct dwc2_core_params *p = &hsotg->params; | |
520 | bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); | |
521 | ||
522 | dwc2_check_param_otg_cap(hsotg); | |
523 | dwc2_check_param_phy_type(hsotg); | |
524 | dwc2_check_param_speed(hsotg); | |
525 | dwc2_check_param_phy_utmi_width(hsotg); | |
526 | CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); | |
527 | CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); | |
528 | CHECK_BOOL(i2c_enable, hw->i2c_enable); | |
529 | CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); | |
530 | CHECK_RANGE(max_packet_count, | |
531 | 15, hw->max_packet_count, | |
532 | hw->max_packet_count); | |
533 | CHECK_RANGE(max_transfer_size, | |
534 | 2047, hw->max_transfer_size, | |
535 | hw->max_transfer_size); | |
536 | ||
537 | if ((hsotg->dr_mode == USB_DR_MODE_HOST) || | |
538 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
539 | CHECK_BOOL(host_dma, dma_capable); | |
540 | CHECK_BOOL(dma_desc_enable, p->host_dma); | |
541 | CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); | |
542 | CHECK_BOOL(host_ls_low_power_phy_clk, | |
543 | p->phy_type == DWC2_PHY_TYPE_PARAM_FS); | |
544 | CHECK_RANGE(host_channels, | |
545 | 1, hw->host_channels, | |
546 | hw->host_channels); | |
547 | CHECK_RANGE(host_rx_fifo_size, | |
548 | 16, hw->rx_fifo_size, | |
549 | hw->rx_fifo_size); | |
550 | CHECK_RANGE(host_nperio_tx_fifo_size, | |
551 | 16, hw->host_nperio_tx_fifo_size, | |
552 | hw->host_nperio_tx_fifo_size); | |
553 | CHECK_RANGE(host_perio_tx_fifo_size, | |
554 | 16, hw->host_perio_tx_fifo_size, | |
555 | hw->host_perio_tx_fifo_size); | |
556 | } | |
557 | ||
558 | if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || | |
559 | (hsotg->dr_mode == USB_DR_MODE_OTG)) { | |
560 | CHECK_BOOL(g_dma, dma_capable); | |
561 | CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); | |
562 | CHECK_RANGE(g_rx_fifo_size, | |
563 | 16, hw->rx_fifo_size, | |
564 | hw->rx_fifo_size); | |
565 | CHECK_RANGE(g_np_tx_fifo_size, | |
566 | 16, hw->dev_nperio_tx_fifo_size, | |
567 | hw->dev_nperio_tx_fifo_size); | |
3c6aea73 | 568 | dwc2_check_param_tx_fifo_sizes(hsotg); |
d936e666 JY |
569 | } |
570 | } | |
571 | ||
323230ef JY |
572 | /* |
573 | * Gets host hardware parameters. Forces host mode if not currently in | |
574 | * host mode. Should be called immediately after a core soft reset in | |
575 | * order to get the reset values. | |
576 | */ | |
577 | static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) | |
578 | { | |
579 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
580 | u32 gnptxfsiz; | |
581 | u32 hptxfsiz; | |
582 | bool forced; | |
583 | ||
584 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) | |
585 | return; | |
586 | ||
587 | forced = dwc2_force_mode_if_needed(hsotg, true); | |
588 | ||
589 | gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); | |
590 | hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); | |
323230ef JY |
591 | |
592 | if (forced) | |
593 | dwc2_clear_force_mode(hsotg); | |
594 | ||
595 | hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
596 | FIFOSIZE_DEPTH_SHIFT; | |
597 | hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
598 | FIFOSIZE_DEPTH_SHIFT; | |
599 | } | |
600 | ||
601 | /* | |
602 | * Gets device hardware parameters. Forces device mode if not | |
603 | * currently in device mode. Should be called immediately after a core | |
604 | * soft reset in order to get the reset values. | |
605 | */ | |
606 | static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) | |
607 | { | |
608 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
609 | bool forced; | |
610 | u32 gnptxfsiz; | |
9273083a | 611 | int fifo, fifo_count; |
323230ef JY |
612 | |
613 | if (hsotg->dr_mode == USB_DR_MODE_HOST) | |
614 | return; | |
615 | ||
616 | forced = dwc2_force_mode_if_needed(hsotg, false); | |
617 | ||
618 | gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); | |
323230ef | 619 | |
9273083a MH |
620 | fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
621 | ||
622 | for (fifo = 1; fifo <= fifo_count; fifo++) { | |
623 | hw->g_tx_fifo_size[fifo] = | |
624 | (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & | |
625 | FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; | |
626 | } | |
627 | ||
323230ef JY |
628 | if (forced) |
629 | dwc2_clear_force_mode(hsotg); | |
630 | ||
631 | hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> | |
632 | FIFOSIZE_DEPTH_SHIFT; | |
633 | } | |
634 | ||
635 | /** | |
636 | * During device initialization, read various hardware configuration | |
637 | * registers and interpret the contents. | |
638 | */ | |
639 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) | |
640 | { | |
641 | struct dwc2_hw_params *hw = &hsotg->hw_params; | |
642 | unsigned int width; | |
643 | u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; | |
644 | u32 grxfsiz; | |
645 | ||
646 | /* | |
647 | * Attempt to ensure this device is really a DWC_otg Controller. | |
648 | * Read and verify the GSNPSID register contents. The value should be | |
649 | * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", | |
650 | * as in "OTG version 2.xx" or "OTG version 3.xx". | |
651 | */ | |
652 | hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); | |
653 | if ((hw->snpsid & 0xfffff000) != 0x4f542000 && | |
1e6b98eb VM |
654 | (hw->snpsid & 0xfffff000) != 0x4f543000 && |
655 | (hw->snpsid & 0xffff0000) != 0x55310000 && | |
656 | (hw->snpsid & 0xffff0000) != 0x55320000) { | |
323230ef JY |
657 | dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", |
658 | hw->snpsid); | |
659 | return -ENODEV; | |
660 | } | |
661 | ||
662 | dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", | |
663 | hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, | |
664 | hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); | |
665 | ||
666 | hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); | |
667 | hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); | |
668 | hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); | |
669 | hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); | |
670 | grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); | |
671 | ||
323230ef JY |
672 | /* hwcfg1 */ |
673 | hw->dev_ep_dirs = hwcfg1; | |
674 | ||
675 | /* hwcfg2 */ | |
676 | hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> | |
677 | GHWCFG2_OP_MODE_SHIFT; | |
678 | hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> | |
679 | GHWCFG2_ARCHITECTURE_SHIFT; | |
680 | hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); | |
681 | hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> | |
682 | GHWCFG2_NUM_HOST_CHAN_SHIFT); | |
683 | hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> | |
684 | GHWCFG2_HS_PHY_TYPE_SHIFT; | |
685 | hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> | |
686 | GHWCFG2_FS_PHY_TYPE_SHIFT; | |
687 | hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> | |
688 | GHWCFG2_NUM_DEV_EP_SHIFT; | |
689 | hw->nperio_tx_q_depth = | |
690 | (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> | |
691 | GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; | |
692 | hw->host_perio_tx_q_depth = | |
693 | (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> | |
694 | GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; | |
695 | hw->dev_token_q_depth = | |
696 | (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> | |
697 | GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; | |
698 | ||
699 | /* hwcfg3 */ | |
700 | width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> | |
701 | GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; | |
702 | hw->max_transfer_size = (1 << (width + 11)) - 1; | |
703 | width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> | |
704 | GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; | |
705 | hw->max_packet_count = (1 << (width + 4)) - 1; | |
706 | hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); | |
707 | hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> | |
708 | GHWCFG3_DFIFO_DEPTH_SHIFT; | |
709 | ||
710 | /* hwcfg4 */ | |
711 | hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); | |
712 | hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> | |
713 | GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; | |
9273083a MH |
714 | hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> |
715 | GHWCFG4_NUM_IN_EPS_SHIFT; | |
323230ef JY |
716 | hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); |
717 | hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); | |
718 | hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> | |
719 | GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; | |
720 | ||
721 | /* fifo sizes */ | |
d1531319 | 722 | hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> |
323230ef | 723 | GRXFSIZ_DEPTH_SHIFT; |
9273083a MH |
724 | /* |
725 | * Host specific hardware parameters. Reading these parameters | |
726 | * requires the controller to be in host mode. The mode will | |
727 | * be forced, if necessary, to read these values. | |
728 | */ | |
729 | dwc2_get_host_hwparams(hsotg); | |
730 | dwc2_get_dev_hwparams(hsotg); | |
323230ef | 731 | |
323230ef JY |
732 | return 0; |
733 | } | |
734 | ||
334bbd4e JY |
735 | int dwc2_init_params(struct dwc2_hsotg *hsotg) |
736 | { | |
7de1debc JY |
737 | const struct of_device_id *match; |
738 | void (*set_params)(void *data); | |
739 | ||
245977c9 | 740 | dwc2_set_default_params(hsotg); |
f9f93cbb | 741 | dwc2_get_device_properties(hsotg); |
334bbd4e | 742 | |
7de1debc JY |
743 | match = of_match_device(dwc2_of_match_table, hsotg->dev); |
744 | if (match && match->data) { | |
745 | set_params = match->data; | |
746 | set_params(hsotg); | |
747 | } | |
748 | ||
d936e666 JY |
749 | dwc2_check_params(hsotg); |
750 | ||
334bbd4e JY |
751 | return 0; |
752 | } |