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72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
a72e658b | 22 | #include <linux/module.h> |
72246da4 FB |
23 | #include <linux/kernel.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
457e84b6 | 34 | #include <linux/of.h> |
72246da4 FB |
35 | |
36 | #include <linux/usb/ch9.h> | |
37 | #include <linux/usb/gadget.h> | |
f7e846f0 | 38 | #include <linux/usb/of.h> |
a45c82b8 | 39 | #include <linux/usb/otg.h> |
72246da4 | 40 | |
6462cbd5 | 41 | #include "platform_data.h" |
72246da4 FB |
42 | #include "core.h" |
43 | #include "gadget.h" | |
44 | #include "io.h" | |
45 | ||
46 | #include "debug.h" | |
47 | ||
8300dd23 FB |
48 | /* -------------------------------------------------------------------------- */ |
49 | ||
3140e8cb SAS |
50 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
51 | { | |
52 | u32 reg; | |
53 | ||
54 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
55 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
56 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
57 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
58 | } | |
8300dd23 | 59 | |
72246da4 FB |
60 | /** |
61 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
62 | * @dwc: pointer to our context structure | |
63 | */ | |
57303488 | 64 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
65 | { |
66 | u32 reg; | |
57303488 | 67 | int ret; |
72246da4 FB |
68 | |
69 | /* Before Resetting PHY, put Core in Reset */ | |
70 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
71 | reg |= DWC3_GCTL_CORESOFTRESET; | |
72 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
73 | ||
74 | /* Assert USB3 PHY reset */ | |
75 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
76 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
77 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
78 | ||
79 | /* Assert USB2 PHY reset */ | |
80 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
81 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
82 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
83 | ||
51e1e7bc FB |
84 | usb_phy_init(dwc->usb2_phy); |
85 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
86 | ret = phy_init(dwc->usb2_generic_phy); |
87 | if (ret < 0) | |
88 | return ret; | |
89 | ||
90 | ret = phy_init(dwc->usb3_generic_phy); | |
91 | if (ret < 0) { | |
92 | phy_exit(dwc->usb2_generic_phy); | |
93 | return ret; | |
94 | } | |
72246da4 FB |
95 | mdelay(100); |
96 | ||
97 | /* Clear USB3 PHY reset */ | |
98 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
99 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
100 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
101 | ||
102 | /* Clear USB2 PHY reset */ | |
103 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
104 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
105 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
106 | ||
45627ac6 PA |
107 | mdelay(100); |
108 | ||
72246da4 FB |
109 | /* After PHYs are stable we can take Core out of reset state */ |
110 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
111 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
112 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
57303488 KVA |
113 | |
114 | return 0; | |
72246da4 FB |
115 | } |
116 | ||
117 | /** | |
118 | * dwc3_free_one_event_buffer - Frees one event buffer | |
119 | * @dwc: Pointer to our controller context structure | |
120 | * @evt: Pointer to event buffer to be freed | |
121 | */ | |
122 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
123 | struct dwc3_event_buffer *evt) | |
124 | { | |
125 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
126 | } |
127 | ||
128 | /** | |
1d046793 | 129 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
130 | * @dwc: Pointer to our controller context structure |
131 | * @length: size of the event buffer | |
132 | * | |
1d046793 | 133 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
134 | * otherwise ERR_PTR(errno). |
135 | */ | |
67d0b500 FB |
136 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
137 | unsigned length) | |
72246da4 FB |
138 | { |
139 | struct dwc3_event_buffer *evt; | |
140 | ||
380f0d28 | 141 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
142 | if (!evt) |
143 | return ERR_PTR(-ENOMEM); | |
144 | ||
145 | evt->dwc = dwc; | |
146 | evt->length = length; | |
147 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
148 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 149 | if (!evt->buf) |
72246da4 | 150 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
151 | |
152 | return evt; | |
153 | } | |
154 | ||
155 | /** | |
156 | * dwc3_free_event_buffers - frees all allocated event buffers | |
157 | * @dwc: Pointer to our controller context structure | |
158 | */ | |
159 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
160 | { | |
161 | struct dwc3_event_buffer *evt; | |
162 | int i; | |
163 | ||
9f622b2a | 164 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 165 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 166 | if (evt) |
72246da4 | 167 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
168 | } |
169 | } | |
170 | ||
171 | /** | |
172 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 173 | * @dwc: pointer to our controller context structure |
72246da4 FB |
174 | * @length: size of event buffer |
175 | * | |
1d046793 | 176 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
177 | * may contain some buffers allocated but not all which were requested. |
178 | */ | |
41ac7b3a | 179 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 180 | { |
9f622b2a | 181 | int num; |
72246da4 FB |
182 | int i; |
183 | ||
9f622b2a FB |
184 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
185 | dwc->num_event_buffers = num; | |
186 | ||
380f0d28 FB |
187 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
188 | GFP_KERNEL); | |
734d5a53 | 189 | if (!dwc->ev_buffs) |
457d3f21 | 190 | return -ENOMEM; |
457d3f21 | 191 | |
72246da4 FB |
192 | for (i = 0; i < num; i++) { |
193 | struct dwc3_event_buffer *evt; | |
194 | ||
195 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
196 | if (IS_ERR(evt)) { | |
197 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
198 | return PTR_ERR(evt); | |
199 | } | |
200 | dwc->ev_buffs[i] = evt; | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | /** | |
207 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 208 | * @dwc: pointer to our controller context structure |
72246da4 FB |
209 | * |
210 | * Returns 0 on success otherwise negative errno. | |
211 | */ | |
7acd85e0 | 212 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
213 | { |
214 | struct dwc3_event_buffer *evt; | |
215 | int n; | |
216 | ||
9f622b2a | 217 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
218 | evt = dwc->ev_buffs[n]; |
219 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
220 | evt->buf, (unsigned long long) evt->dma, | |
221 | evt->length); | |
222 | ||
7acd85e0 PZ |
223 | evt->lpos = 0; |
224 | ||
72246da4 FB |
225 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
226 | lower_32_bits(evt->dma)); | |
227 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
228 | upper_32_bits(evt->dma)); | |
229 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 230 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
231 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
232 | } | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
238 | { | |
239 | struct dwc3_event_buffer *evt; | |
240 | int n; | |
241 | ||
9f622b2a | 242 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 243 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
244 | |
245 | evt->lpos = 0; | |
246 | ||
72246da4 FB |
247 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
248 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
249 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
250 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
251 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
252 | } | |
253 | } | |
254 | ||
0ffcaf37 FB |
255 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
256 | { | |
257 | if (!dwc->has_hibernation) | |
258 | return 0; | |
259 | ||
260 | if (!dwc->nr_scratch) | |
261 | return 0; | |
262 | ||
263 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
264 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
265 | if (!dwc->scratchbuf) | |
266 | return -ENOMEM; | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
272 | { | |
273 | dma_addr_t scratch_addr; | |
274 | u32 param; | |
275 | int ret; | |
276 | ||
277 | if (!dwc->has_hibernation) | |
278 | return 0; | |
279 | ||
280 | if (!dwc->nr_scratch) | |
281 | return 0; | |
282 | ||
283 | /* should never fall here */ | |
284 | if (!WARN_ON(dwc->scratchbuf)) | |
285 | return 0; | |
286 | ||
287 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
288 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
289 | DMA_BIDIRECTIONAL); | |
290 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
291 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
292 | ret = -EFAULT; | |
293 | goto err0; | |
294 | } | |
295 | ||
296 | dwc->scratch_addr = scratch_addr; | |
297 | ||
298 | param = lower_32_bits(scratch_addr); | |
299 | ||
300 | ret = dwc3_send_gadget_generic_command(dwc, | |
301 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
302 | if (ret < 0) | |
303 | goto err1; | |
304 | ||
305 | param = upper_32_bits(scratch_addr); | |
306 | ||
307 | ret = dwc3_send_gadget_generic_command(dwc, | |
308 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
309 | if (ret < 0) | |
310 | goto err1; | |
311 | ||
312 | return 0; | |
313 | ||
314 | err1: | |
315 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
316 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
317 | ||
318 | err0: | |
319 | return ret; | |
320 | } | |
321 | ||
322 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
323 | { | |
324 | if (!dwc->has_hibernation) | |
325 | return; | |
326 | ||
327 | if (!dwc->nr_scratch) | |
328 | return; | |
329 | ||
330 | /* should never fall here */ | |
331 | if (!WARN_ON(dwc->scratchbuf)) | |
332 | return; | |
333 | ||
334 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
335 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
336 | kfree(dwc->scratchbuf); | |
337 | } | |
338 | ||
789451f6 FB |
339 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
340 | { | |
341 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
342 | ||
343 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
344 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
345 | ||
346 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
347 | dwc->num_in_eps, dwc->num_out_eps); | |
348 | } | |
349 | ||
41ac7b3a | 350 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
351 | { |
352 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
353 | ||
354 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
355 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
356 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
357 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
358 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
359 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
360 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
361 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
362 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
363 | } | |
364 | ||
72246da4 FB |
365 | /** |
366 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
367 | * @dwc: Pointer to our controller context structure | |
368 | * | |
369 | * Returns 0 on success otherwise negative errno. | |
370 | */ | |
41ac7b3a | 371 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
372 | { |
373 | unsigned long timeout; | |
0ffcaf37 | 374 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
375 | u32 reg; |
376 | int ret; | |
377 | ||
7650bd74 SAS |
378 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
379 | /* This should read as U3 followed by revision number */ | |
380 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
381 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
382 | ret = -ENODEV; | |
383 | goto err0; | |
384 | } | |
248b122b | 385 | dwc->revision = reg; |
7650bd74 | 386 | |
0e1e5c47 PZ |
387 | /* Handle USB2.0-only core configuration */ |
388 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
389 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
390 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
391 | dwc->maximum_speed = USB_SPEED_HIGH; | |
392 | } | |
393 | ||
72246da4 FB |
394 | /* issue device SoftReset too */ |
395 | timeout = jiffies + msecs_to_jiffies(500); | |
396 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
397 | do { | |
398 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
399 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
400 | break; | |
401 | ||
402 | if (time_after(jiffies, timeout)) { | |
403 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
404 | ret = -ETIMEDOUT; | |
405 | goto err0; | |
406 | } | |
407 | ||
408 | cpu_relax(); | |
409 | } while (true); | |
410 | ||
57303488 KVA |
411 | ret = dwc3_core_soft_reset(dwc); |
412 | if (ret) | |
413 | goto err0; | |
58a0f23f | 414 | |
4878a028 | 415 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 416 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
417 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
418 | ||
164d7731 | 419 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 420 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
421 | /** |
422 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
423 | * issue which would cause xHCI compliance tests to fail. | |
424 | * | |
425 | * Because of that we cannot enable clock gating on such | |
426 | * configurations. | |
427 | * | |
428 | * Refers to: | |
429 | * | |
430 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
431 | * SOF/ITP Mode Used | |
432 | */ | |
433 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
434 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
435 | (dwc->revision >= DWC3_REVISION_210A && | |
436 | dwc->revision <= DWC3_REVISION_250A)) | |
437 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
438 | else | |
439 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 440 | break; |
0ffcaf37 FB |
441 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
442 | /* enable hibernation here */ | |
443 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
444 | break; | |
4878a028 SAS |
445 | default: |
446 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
447 | } | |
448 | ||
449 | /* | |
450 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 451 | * where the device can fail to connect at SuperSpeed |
4878a028 | 452 | * and falls back to high-speed mode which causes |
1d046793 | 453 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
454 | */ |
455 | if (dwc->revision < DWC3_REVISION_190A) | |
456 | reg |= DWC3_GCTL_U2RSTECN; | |
457 | ||
789451f6 FB |
458 | dwc3_core_num_eps(dwc); |
459 | ||
4878a028 SAS |
460 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
461 | ||
0ffcaf37 FB |
462 | ret = dwc3_alloc_scratch_buffers(dwc); |
463 | if (ret) | |
464 | goto err1; | |
465 | ||
466 | ret = dwc3_setup_scratch_buffers(dwc); | |
467 | if (ret) | |
468 | goto err2; | |
469 | ||
72246da4 FB |
470 | return 0; |
471 | ||
0ffcaf37 FB |
472 | err2: |
473 | dwc3_free_scratch_buffers(dwc); | |
474 | ||
475 | err1: | |
476 | usb_phy_shutdown(dwc->usb2_phy); | |
477 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
478 | phy_exit(dwc->usb2_generic_phy); |
479 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 480 | |
72246da4 FB |
481 | err0: |
482 | return ret; | |
483 | } | |
484 | ||
485 | static void dwc3_core_exit(struct dwc3 *dwc) | |
486 | { | |
0ffcaf37 | 487 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
488 | usb_phy_shutdown(dwc->usb2_phy); |
489 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
490 | phy_exit(dwc->usb2_generic_phy); |
491 | phy_exit(dwc->usb3_generic_phy); | |
72246da4 FB |
492 | } |
493 | ||
3c9f94ac | 494 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 495 | { |
3c9f94ac | 496 | struct device *dev = dwc->dev; |
941ea361 | 497 | struct device_node *node = dev->of_node; |
3c9f94ac | 498 | int ret; |
72246da4 | 499 | |
5088b6f5 KVA |
500 | if (node) { |
501 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
502 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
503 | } else { |
504 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
505 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
506 | } |
507 | ||
d105e7f8 FB |
508 | if (IS_ERR(dwc->usb2_phy)) { |
509 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
510 | if (ret == -ENXIO || ret == -ENODEV) { |
511 | dwc->usb2_phy = NULL; | |
512 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 513 | return ret; |
122f06e6 KVA |
514 | } else { |
515 | dev_err(dev, "no usb2 phy configured\n"); | |
516 | return ret; | |
517 | } | |
51e1e7bc FB |
518 | } |
519 | ||
d105e7f8 | 520 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 521 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
522 | if (ret == -ENXIO || ret == -ENODEV) { |
523 | dwc->usb3_phy = NULL; | |
524 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 525 | return ret; |
122f06e6 KVA |
526 | } else { |
527 | dev_err(dev, "no usb3 phy configured\n"); | |
528 | return ret; | |
529 | } | |
51e1e7bc FB |
530 | } |
531 | ||
57303488 KVA |
532 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
533 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
534 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
535 | if (ret == -ENOSYS || ret == -ENODEV) { | |
536 | dwc->usb2_generic_phy = NULL; | |
537 | } else if (ret == -EPROBE_DEFER) { | |
538 | return ret; | |
539 | } else { | |
540 | dev_err(dev, "no usb2 phy configured\n"); | |
541 | return ret; | |
542 | } | |
543 | } | |
544 | ||
545 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
546 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
547 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
548 | if (ret == -ENOSYS || ret == -ENODEV) { | |
549 | dwc->usb3_generic_phy = NULL; | |
550 | } else if (ret == -EPROBE_DEFER) { | |
551 | return ret; | |
552 | } else { | |
553 | dev_err(dev, "no usb3 phy configured\n"); | |
554 | return ret; | |
555 | } | |
556 | } | |
557 | ||
3c9f94ac FB |
558 | return 0; |
559 | } | |
560 | ||
5f94adfe FB |
561 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
562 | { | |
563 | struct device *dev = dwc->dev; | |
564 | int ret; | |
565 | ||
566 | switch (dwc->dr_mode) { | |
567 | case USB_DR_MODE_PERIPHERAL: | |
568 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
569 | ret = dwc3_gadget_init(dwc); | |
570 | if (ret) { | |
571 | dev_err(dev, "failed to initialize gadget\n"); | |
572 | return ret; | |
573 | } | |
574 | break; | |
575 | case USB_DR_MODE_HOST: | |
576 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
577 | ret = dwc3_host_init(dwc); | |
578 | if (ret) { | |
579 | dev_err(dev, "failed to initialize host\n"); | |
580 | return ret; | |
581 | } | |
582 | break; | |
583 | case USB_DR_MODE_OTG: | |
584 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
585 | ret = dwc3_host_init(dwc); | |
586 | if (ret) { | |
587 | dev_err(dev, "failed to initialize host\n"); | |
588 | return ret; | |
589 | } | |
590 | ||
591 | ret = dwc3_gadget_init(dwc); | |
592 | if (ret) { | |
593 | dev_err(dev, "failed to initialize gadget\n"); | |
594 | return ret; | |
595 | } | |
596 | break; | |
597 | default: | |
598 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
599 | return -EINVAL; | |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
606 | { | |
607 | switch (dwc->dr_mode) { | |
608 | case USB_DR_MODE_PERIPHERAL: | |
609 | dwc3_gadget_exit(dwc); | |
610 | break; | |
611 | case USB_DR_MODE_HOST: | |
612 | dwc3_host_exit(dwc); | |
613 | break; | |
614 | case USB_DR_MODE_OTG: | |
615 | dwc3_host_exit(dwc); | |
616 | dwc3_gadget_exit(dwc); | |
617 | break; | |
618 | default: | |
619 | /* do nothing */ | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
3c9f94ac FB |
624 | #define DWC3_ALIGN_MASK (16 - 1) |
625 | ||
626 | static int dwc3_probe(struct platform_device *pdev) | |
627 | { | |
628 | struct device *dev = &pdev->dev; | |
629 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
630 | struct device_node *node = dev->of_node; | |
631 | struct resource *res; | |
632 | struct dwc3 *dwc; | |
633 | ||
b09e99ee | 634 | int ret; |
3c9f94ac FB |
635 | |
636 | void __iomem *regs; | |
637 | void *mem; | |
638 | ||
639 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 640 | if (!mem) |
3c9f94ac | 641 | return -ENOMEM; |
734d5a53 | 642 | |
3c9f94ac FB |
643 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
644 | dwc->mem = mem; | |
645 | dwc->dev = dev; | |
646 | ||
647 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
648 | if (!res) { | |
649 | dev_err(dev, "missing IRQ\n"); | |
650 | return -ENODEV; | |
651 | } | |
652 | dwc->xhci_resources[1].start = res->start; | |
653 | dwc->xhci_resources[1].end = res->end; | |
654 | dwc->xhci_resources[1].flags = res->flags; | |
655 | dwc->xhci_resources[1].name = res->name; | |
656 | ||
657 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
658 | if (!res) { | |
659 | dev_err(dev, "missing memory resource\n"); | |
660 | return -ENODEV; | |
661 | } | |
662 | ||
f32a5e23 VG |
663 | dwc->xhci_resources[0].start = res->start; |
664 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
665 | DWC3_XHCI_REGS_END; | |
666 | dwc->xhci_resources[0].flags = res->flags; | |
667 | dwc->xhci_resources[0].name = res->name; | |
668 | ||
669 | res->start += DWC3_GLOBALS_REGS_START; | |
670 | ||
671 | /* | |
672 | * Request memory region but exclude xHCI regs, | |
673 | * since it will be requested by the xhci-plat driver. | |
674 | */ | |
675 | regs = devm_ioremap_resource(dev, res); | |
676 | if (IS_ERR(regs)) | |
677 | return PTR_ERR(regs); | |
678 | ||
679 | dwc->regs = regs; | |
680 | dwc->regs_size = resource_size(res); | |
681 | /* | |
682 | * restore res->start back to its original value so that, | |
683 | * in case the probe is deferred, we don't end up getting error in | |
684 | * request the memory region the next time probe is called. | |
685 | */ | |
686 | res->start -= DWC3_GLOBALS_REGS_START; | |
687 | ||
3c9f94ac FB |
688 | if (node) { |
689 | dwc->maximum_speed = of_usb_get_maximum_speed(node); | |
690 | ||
691 | dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize"); | |
692 | dwc->dr_mode = of_usb_get_dr_mode(node); | |
693 | } else if (pdata) { | |
694 | dwc->maximum_speed = pdata->maximum_speed; | |
695 | ||
696 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
697 | dwc->dr_mode = pdata->dr_mode; | |
698 | } | |
699 | ||
700 | /* default to superspeed if no maximum_speed passed */ | |
701 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
702 | dwc->maximum_speed = USB_SPEED_SUPER; | |
703 | ||
704 | ret = dwc3_core_get_phy(dwc); | |
705 | if (ret) | |
706 | return ret; | |
707 | ||
72246da4 FB |
708 | spin_lock_init(&dwc->lock); |
709 | platform_set_drvdata(pdev, dwc); | |
710 | ||
ddff14f1 KVA |
711 | dev->dma_mask = dev->parent->dma_mask; |
712 | dev->dma_parms = dev->parent->dma_parms; | |
713 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
714 | ||
802ca850 CP |
715 | pm_runtime_enable(dev); |
716 | pm_runtime_get_sync(dev); | |
717 | pm_runtime_forbid(dev); | |
72246da4 | 718 | |
4fd24483 KVA |
719 | dwc3_cache_hwparams(dwc); |
720 | ||
3921426b FB |
721 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
722 | if (ret) { | |
723 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
724 | ret = -ENOMEM; | |
725 | goto err0; | |
726 | } | |
727 | ||
32a4a135 FB |
728 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
729 | dwc->dr_mode = USB_DR_MODE_HOST; | |
730 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
731 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
732 | ||
733 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
734 | dwc->dr_mode = USB_DR_MODE_OTG; | |
735 | ||
72246da4 FB |
736 | ret = dwc3_core_init(dwc); |
737 | if (ret) { | |
802ca850 | 738 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 739 | goto err0; |
72246da4 FB |
740 | } |
741 | ||
3088f108 KVA |
742 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
743 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
57303488 KVA |
744 | ret = phy_power_on(dwc->usb2_generic_phy); |
745 | if (ret < 0) | |
746 | goto err1; | |
747 | ||
748 | ret = phy_power_on(dwc->usb3_generic_phy); | |
749 | if (ret < 0) | |
750 | goto err_usb2phy_power; | |
3088f108 | 751 | |
f122d33e FB |
752 | ret = dwc3_event_buffers_setup(dwc); |
753 | if (ret) { | |
754 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
57303488 | 755 | goto err_usb3phy_power; |
f122d33e FB |
756 | } |
757 | ||
5f94adfe FB |
758 | ret = dwc3_core_init_mode(dwc); |
759 | if (ret) | |
f122d33e | 760 | goto err2; |
72246da4 FB |
761 | |
762 | ret = dwc3_debugfs_init(dwc); | |
763 | if (ret) { | |
802ca850 | 764 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 765 | goto err3; |
72246da4 FB |
766 | } |
767 | ||
802ca850 | 768 | pm_runtime_allow(dev); |
72246da4 FB |
769 | |
770 | return 0; | |
771 | ||
f122d33e | 772 | err3: |
5f94adfe | 773 | dwc3_core_exit_mode(dwc); |
72246da4 | 774 | |
f122d33e FB |
775 | err2: |
776 | dwc3_event_buffers_cleanup(dwc); | |
777 | ||
57303488 KVA |
778 | err_usb3phy_power: |
779 | phy_power_off(dwc->usb3_generic_phy); | |
780 | ||
781 | err_usb2phy_power: | |
782 | phy_power_off(dwc->usb2_generic_phy); | |
783 | ||
72246da4 | 784 | err1: |
501fae51 KVA |
785 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
786 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 787 | dwc3_core_exit(dwc); |
72246da4 | 788 | |
3921426b FB |
789 | err0: |
790 | dwc3_free_event_buffers(dwc); | |
791 | ||
72246da4 FB |
792 | return ret; |
793 | } | |
794 | ||
fb4e98ab | 795 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 796 | { |
72246da4 | 797 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 798 | |
dc99f16f FB |
799 | dwc3_debugfs_exit(dwc); |
800 | dwc3_core_exit_mode(dwc); | |
801 | dwc3_event_buffers_cleanup(dwc); | |
802 | dwc3_free_event_buffers(dwc); | |
803 | ||
8ba007a9 KVA |
804 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
805 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
57303488 KVA |
806 | phy_power_off(dwc->usb2_generic_phy); |
807 | phy_power_off(dwc->usb3_generic_phy); | |
8ba007a9 | 808 | |
72246da4 | 809 | dwc3_core_exit(dwc); |
72246da4 | 810 | |
16b972a5 | 811 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
812 | pm_runtime_disable(&pdev->dev); |
813 | ||
72246da4 FB |
814 | return 0; |
815 | } | |
816 | ||
19fda7cd | 817 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
818 | static int dwc3_prepare(struct device *dev) |
819 | { | |
820 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
821 | unsigned long flags; | |
822 | ||
823 | spin_lock_irqsave(&dwc->lock, flags); | |
824 | ||
a45c82b8 RK |
825 | switch (dwc->dr_mode) { |
826 | case USB_DR_MODE_PERIPHERAL: | |
827 | case USB_DR_MODE_OTG: | |
7415f17c FB |
828 | dwc3_gadget_prepare(dwc); |
829 | /* FALLTHROUGH */ | |
a45c82b8 | 830 | case USB_DR_MODE_HOST: |
7415f17c FB |
831 | default: |
832 | dwc3_event_buffers_cleanup(dwc); | |
833 | break; | |
834 | } | |
835 | ||
836 | spin_unlock_irqrestore(&dwc->lock, flags); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | static void dwc3_complete(struct device *dev) | |
842 | { | |
843 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
844 | unsigned long flags; | |
845 | ||
846 | spin_lock_irqsave(&dwc->lock, flags); | |
847 | ||
f45e5f00 | 848 | dwc3_event_buffers_setup(dwc); |
a45c82b8 RK |
849 | switch (dwc->dr_mode) { |
850 | case USB_DR_MODE_PERIPHERAL: | |
851 | case USB_DR_MODE_OTG: | |
7415f17c FB |
852 | dwc3_gadget_complete(dwc); |
853 | /* FALLTHROUGH */ | |
a45c82b8 | 854 | case USB_DR_MODE_HOST: |
7415f17c | 855 | default: |
7415f17c FB |
856 | break; |
857 | } | |
858 | ||
859 | spin_unlock_irqrestore(&dwc->lock, flags); | |
860 | } | |
861 | ||
862 | static int dwc3_suspend(struct device *dev) | |
863 | { | |
864 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
865 | unsigned long flags; | |
866 | ||
867 | spin_lock_irqsave(&dwc->lock, flags); | |
868 | ||
a45c82b8 RK |
869 | switch (dwc->dr_mode) { |
870 | case USB_DR_MODE_PERIPHERAL: | |
871 | case USB_DR_MODE_OTG: | |
7415f17c FB |
872 | dwc3_gadget_suspend(dwc); |
873 | /* FALLTHROUGH */ | |
a45c82b8 | 874 | case USB_DR_MODE_HOST: |
7415f17c FB |
875 | default: |
876 | /* do nothing */ | |
877 | break; | |
878 | } | |
879 | ||
880 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
881 | spin_unlock_irqrestore(&dwc->lock, flags); | |
882 | ||
883 | usb_phy_shutdown(dwc->usb3_phy); | |
884 | usb_phy_shutdown(dwc->usb2_phy); | |
57303488 KVA |
885 | phy_exit(dwc->usb2_generic_phy); |
886 | phy_exit(dwc->usb3_generic_phy); | |
7415f17c FB |
887 | |
888 | return 0; | |
889 | } | |
890 | ||
891 | static int dwc3_resume(struct device *dev) | |
892 | { | |
893 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
894 | unsigned long flags; | |
57303488 | 895 | int ret; |
7415f17c FB |
896 | |
897 | usb_phy_init(dwc->usb3_phy); | |
898 | usb_phy_init(dwc->usb2_phy); | |
57303488 KVA |
899 | ret = phy_init(dwc->usb2_generic_phy); |
900 | if (ret < 0) | |
901 | return ret; | |
902 | ||
903 | ret = phy_init(dwc->usb3_generic_phy); | |
904 | if (ret < 0) | |
905 | goto err_usb2phy_init; | |
7415f17c FB |
906 | |
907 | spin_lock_irqsave(&dwc->lock, flags); | |
908 | ||
909 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); | |
910 | ||
a45c82b8 RK |
911 | switch (dwc->dr_mode) { |
912 | case USB_DR_MODE_PERIPHERAL: | |
913 | case USB_DR_MODE_OTG: | |
7415f17c FB |
914 | dwc3_gadget_resume(dwc); |
915 | /* FALLTHROUGH */ | |
a45c82b8 | 916 | case USB_DR_MODE_HOST: |
7415f17c FB |
917 | default: |
918 | /* do nothing */ | |
919 | break; | |
920 | } | |
921 | ||
922 | spin_unlock_irqrestore(&dwc->lock, flags); | |
923 | ||
924 | pm_runtime_disable(dev); | |
925 | pm_runtime_set_active(dev); | |
926 | pm_runtime_enable(dev); | |
927 | ||
928 | return 0; | |
57303488 KVA |
929 | |
930 | err_usb2phy_init: | |
931 | phy_exit(dwc->usb2_generic_phy); | |
932 | ||
933 | return ret; | |
7415f17c FB |
934 | } |
935 | ||
936 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
937 | .prepare = dwc3_prepare, | |
938 | .complete = dwc3_complete, | |
939 | ||
940 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) | |
941 | }; | |
942 | ||
943 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
944 | #else | |
945 | #define DWC3_PM_OPS NULL | |
946 | #endif | |
947 | ||
5088b6f5 KVA |
948 | #ifdef CONFIG_OF |
949 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
950 | { |
951 | .compatible = "snps,dwc3" | |
952 | }, | |
5088b6f5 KVA |
953 | { |
954 | .compatible = "synopsys,dwc3" | |
955 | }, | |
956 | { }, | |
957 | }; | |
958 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
959 | #endif | |
960 | ||
72246da4 FB |
961 | static struct platform_driver dwc3_driver = { |
962 | .probe = dwc3_probe, | |
7690417d | 963 | .remove = dwc3_remove, |
72246da4 FB |
964 | .driver = { |
965 | .name = "dwc3", | |
5088b6f5 | 966 | .of_match_table = of_match_ptr(of_dwc3_match), |
7415f17c | 967 | .pm = DWC3_PM_OPS, |
72246da4 | 968 | }, |
72246da4 FB |
969 | }; |
970 | ||
b1116dcc TK |
971 | module_platform_driver(dwc3_driver); |
972 | ||
7ae4fc4d | 973 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 974 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 975 | MODULE_LICENSE("GPL v2"); |
72246da4 | 976 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |