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72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
a72e658b | 39 | #include <linux/module.h> |
72246da4 FB |
40 | #include <linux/kernel.h> |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/platform_device.h> | |
44 | #include <linux/pm_runtime.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/io.h> | |
48 | #include <linux/list.h> | |
49 | #include <linux/delay.h> | |
50 | #include <linux/dma-mapping.h> | |
457e84b6 | 51 | #include <linux/of.h> |
72246da4 | 52 | |
51e1e7bc | 53 | #include <linux/usb/otg.h> |
72246da4 FB |
54 | #include <linux/usb/ch9.h> |
55 | #include <linux/usb/gadget.h> | |
56 | ||
57 | #include "core.h" | |
58 | #include "gadget.h" | |
59 | #include "io.h" | |
60 | ||
61 | #include "debug.h" | |
62 | ||
6c167fc9 FB |
63 | static char *maximum_speed = "super"; |
64 | module_param(maximum_speed, charp, 0); | |
65 | MODULE_PARM_DESC(maximum_speed, "Maximum supported speed."); | |
66 | ||
8300dd23 FB |
67 | /* -------------------------------------------------------------------------- */ |
68 | ||
3140e8cb SAS |
69 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
70 | { | |
71 | u32 reg; | |
72 | ||
73 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
74 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
75 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
76 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
77 | } | |
8300dd23 | 78 | |
72246da4 FB |
79 | /** |
80 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
81 | * @dwc: pointer to our context structure | |
82 | */ | |
83 | static void dwc3_core_soft_reset(struct dwc3 *dwc) | |
84 | { | |
85 | u32 reg; | |
86 | ||
87 | /* Before Resetting PHY, put Core in Reset */ | |
88 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
89 | reg |= DWC3_GCTL_CORESOFTRESET; | |
90 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
91 | ||
92 | /* Assert USB3 PHY reset */ | |
93 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
94 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
95 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
96 | ||
97 | /* Assert USB2 PHY reset */ | |
98 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
99 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
100 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
101 | ||
51e1e7bc FB |
102 | usb_phy_init(dwc->usb2_phy); |
103 | usb_phy_init(dwc->usb3_phy); | |
72246da4 FB |
104 | mdelay(100); |
105 | ||
106 | /* Clear USB3 PHY reset */ | |
107 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
108 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
109 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
110 | ||
111 | /* Clear USB2 PHY reset */ | |
112 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
113 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
114 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
115 | ||
45627ac6 PA |
116 | mdelay(100); |
117 | ||
72246da4 FB |
118 | /* After PHYs are stable we can take Core out of reset state */ |
119 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
120 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
121 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
122 | } | |
123 | ||
124 | /** | |
125 | * dwc3_free_one_event_buffer - Frees one event buffer | |
126 | * @dwc: Pointer to our controller context structure | |
127 | * @evt: Pointer to event buffer to be freed | |
128 | */ | |
129 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
130 | struct dwc3_event_buffer *evt) | |
131 | { | |
132 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
133 | } |
134 | ||
135 | /** | |
1d046793 | 136 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
137 | * @dwc: Pointer to our controller context structure |
138 | * @length: size of the event buffer | |
139 | * | |
1d046793 | 140 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
141 | * otherwise ERR_PTR(errno). |
142 | */ | |
143 | static struct dwc3_event_buffer *__devinit | |
144 | dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length) | |
145 | { | |
146 | struct dwc3_event_buffer *evt; | |
147 | ||
380f0d28 | 148 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
149 | if (!evt) |
150 | return ERR_PTR(-ENOMEM); | |
151 | ||
152 | evt->dwc = dwc; | |
153 | evt->length = length; | |
154 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
155 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 156 | if (!evt->buf) |
72246da4 | 157 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
158 | |
159 | return evt; | |
160 | } | |
161 | ||
162 | /** | |
163 | * dwc3_free_event_buffers - frees all allocated event buffers | |
164 | * @dwc: Pointer to our controller context structure | |
165 | */ | |
166 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
167 | { | |
168 | struct dwc3_event_buffer *evt; | |
169 | int i; | |
170 | ||
9f622b2a | 171 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 172 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 173 | if (evt) |
72246da4 | 174 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
175 | } |
176 | } | |
177 | ||
178 | /** | |
179 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 180 | * @dwc: pointer to our controller context structure |
72246da4 FB |
181 | * @length: size of event buffer |
182 | * | |
1d046793 | 183 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
184 | * may contain some buffers allocated but not all which were requested. |
185 | */ | |
9f622b2a | 186 | static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 187 | { |
9f622b2a | 188 | int num; |
72246da4 FB |
189 | int i; |
190 | ||
9f622b2a FB |
191 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
192 | dwc->num_event_buffers = num; | |
193 | ||
380f0d28 FB |
194 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
195 | GFP_KERNEL); | |
457d3f21 FB |
196 | if (!dwc->ev_buffs) { |
197 | dev_err(dwc->dev, "can't allocate event buffers array\n"); | |
198 | return -ENOMEM; | |
199 | } | |
200 | ||
72246da4 FB |
201 | for (i = 0; i < num; i++) { |
202 | struct dwc3_event_buffer *evt; | |
203 | ||
204 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
205 | if (IS_ERR(evt)) { | |
206 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
207 | return PTR_ERR(evt); | |
208 | } | |
209 | dwc->ev_buffs[i] = evt; | |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | /** | |
216 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 217 | * @dwc: pointer to our controller context structure |
72246da4 FB |
218 | * |
219 | * Returns 0 on success otherwise negative errno. | |
220 | */ | |
7acd85e0 | 221 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
222 | { |
223 | struct dwc3_event_buffer *evt; | |
224 | int n; | |
225 | ||
9f622b2a | 226 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
227 | evt = dwc->ev_buffs[n]; |
228 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
229 | evt->buf, (unsigned long long) evt->dma, | |
230 | evt->length); | |
231 | ||
7acd85e0 PZ |
232 | evt->lpos = 0; |
233 | ||
72246da4 FB |
234 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
235 | lower_32_bits(evt->dma)); | |
236 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
237 | upper_32_bits(evt->dma)); | |
238 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
239 | evt->length & 0xffff); | |
240 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
247 | { | |
248 | struct dwc3_event_buffer *evt; | |
249 | int n; | |
250 | ||
9f622b2a | 251 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 252 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
253 | |
254 | evt->lpos = 0; | |
255 | ||
72246da4 FB |
256 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
257 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
258 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0); | |
259 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
260 | } | |
261 | } | |
262 | ||
26ceca97 FB |
263 | static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc) |
264 | { | |
265 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
266 | ||
267 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
268 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
269 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
270 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
271 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
272 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
273 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
274 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
275 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
276 | } | |
277 | ||
72246da4 FB |
278 | /** |
279 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
280 | * @dwc: Pointer to our controller context structure | |
281 | * | |
282 | * Returns 0 on success otherwise negative errno. | |
283 | */ | |
284 | static int __devinit dwc3_core_init(struct dwc3 *dwc) | |
285 | { | |
286 | unsigned long timeout; | |
287 | u32 reg; | |
288 | int ret; | |
289 | ||
7650bd74 SAS |
290 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
291 | /* This should read as U3 followed by revision number */ | |
292 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
293 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
294 | ret = -ENODEV; | |
295 | goto err0; | |
296 | } | |
248b122b | 297 | dwc->revision = reg; |
7650bd74 | 298 | |
72246da4 FB |
299 | /* issue device SoftReset too */ |
300 | timeout = jiffies + msecs_to_jiffies(500); | |
301 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
302 | do { | |
303 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
304 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
305 | break; | |
306 | ||
307 | if (time_after(jiffies, timeout)) { | |
308 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
309 | ret = -ETIMEDOUT; | |
310 | goto err0; | |
311 | } | |
312 | ||
313 | cpu_relax(); | |
314 | } while (true); | |
315 | ||
58a0f23f PA |
316 | dwc3_core_soft_reset(dwc); |
317 | ||
9f622b2a FB |
318 | dwc3_cache_hwparams(dwc); |
319 | ||
4878a028 | 320 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 321 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
322 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
323 | ||
164d7731 | 324 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 SAS |
325 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
326 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
327 | break; | |
328 | default: | |
329 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
330 | } | |
331 | ||
332 | /* | |
333 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 334 | * where the device can fail to connect at SuperSpeed |
4878a028 | 335 | * and falls back to high-speed mode which causes |
1d046793 | 336 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
337 | */ |
338 | if (dwc->revision < DWC3_REVISION_190A) | |
339 | reg |= DWC3_GCTL_U2RSTECN; | |
340 | ||
341 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
342 | ||
72246da4 FB |
343 | ret = dwc3_event_buffers_setup(dwc); |
344 | if (ret) { | |
345 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
3921426b | 346 | goto err0; |
72246da4 FB |
347 | } |
348 | ||
349 | return 0; | |
350 | ||
72246da4 FB |
351 | err0: |
352 | return ret; | |
353 | } | |
354 | ||
355 | static void dwc3_core_exit(struct dwc3 *dwc) | |
356 | { | |
357 | dwc3_event_buffers_cleanup(dwc); | |
01b8daf7 VG |
358 | |
359 | usb_phy_shutdown(dwc->usb2_phy); | |
360 | usb_phy_shutdown(dwc->usb3_phy); | |
72246da4 FB |
361 | } |
362 | ||
363 | #define DWC3_ALIGN_MASK (16 - 1) | |
364 | ||
365 | static int __devinit dwc3_probe(struct platform_device *pdev) | |
366 | { | |
457e84b6 | 367 | struct device_node *node = pdev->dev.of_node; |
72246da4 FB |
368 | struct resource *res; |
369 | struct dwc3 *dwc; | |
802ca850 | 370 | struct device *dev = &pdev->dev; |
0949e99b | 371 | |
72246da4 | 372 | int ret = -ENOMEM; |
0949e99b FB |
373 | |
374 | void __iomem *regs; | |
72246da4 FB |
375 | void *mem; |
376 | ||
0949e99b FB |
377 | u8 mode; |
378 | ||
802ca850 | 379 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
72246da4 | 380 | if (!mem) { |
802ca850 CP |
381 | dev_err(dev, "not enough memory\n"); |
382 | return -ENOMEM; | |
72246da4 FB |
383 | } |
384 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
385 | dwc->mem = mem; | |
386 | ||
51249dca | 387 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
72246da4 | 388 | if (!res) { |
51249dca | 389 | dev_err(dev, "missing IRQ\n"); |
802ca850 | 390 | return -ENODEV; |
72246da4 | 391 | } |
066618bc KVA |
392 | dwc->xhci_resources[1].start = res->start; |
393 | dwc->xhci_resources[1].end = res->end; | |
394 | dwc->xhci_resources[1].flags = res->flags; | |
395 | dwc->xhci_resources[1].name = res->name; | |
72246da4 | 396 | |
51249dca IS |
397 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
398 | if (!res) { | |
399 | dev_err(dev, "missing memory resource\n"); | |
400 | return -ENODEV; | |
401 | } | |
066618bc | 402 | dwc->xhci_resources[0].start = res->start; |
51249dca IS |
403 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + |
404 | DWC3_XHCI_REGS_END; | |
066618bc KVA |
405 | dwc->xhci_resources[0].flags = res->flags; |
406 | dwc->xhci_resources[0].name = res->name; | |
51249dca IS |
407 | |
408 | /* | |
409 | * Request memory region but exclude xHCI regs, | |
410 | * since it will be requested by the xhci-plat driver. | |
411 | */ | |
412 | res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START, | |
413 | resource_size(res) - DWC3_GLOBALS_REGS_START, | |
802ca850 | 414 | dev_name(dev)); |
72246da4 | 415 | if (!res) { |
802ca850 CP |
416 | dev_err(dev, "can't request mem region\n"); |
417 | return -ENOMEM; | |
72246da4 FB |
418 | } |
419 | ||
b7e38aa6 | 420 | regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
72246da4 | 421 | if (!regs) { |
802ca850 CP |
422 | dev_err(dev, "ioremap failed\n"); |
423 | return -ENOMEM; | |
72246da4 FB |
424 | } |
425 | ||
51e1e7bc FB |
426 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
427 | if (IS_ERR_OR_NULL(dwc->usb2_phy)) { | |
428 | dev_err(dev, "no usb2 phy configured\n"); | |
429 | return -EPROBE_DEFER; | |
430 | } | |
431 | ||
432 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
433 | if (IS_ERR_OR_NULL(dwc->usb3_phy)) { | |
434 | dev_err(dev, "no usb3 phy configured\n"); | |
435 | return -EPROBE_DEFER; | |
436 | } | |
437 | ||
72246da4 FB |
438 | spin_lock_init(&dwc->lock); |
439 | platform_set_drvdata(pdev, dwc); | |
440 | ||
441 | dwc->regs = regs; | |
442 | dwc->regs_size = resource_size(res); | |
802ca850 | 443 | dwc->dev = dev; |
72246da4 | 444 | |
6c167fc9 FB |
445 | if (!strncmp("super", maximum_speed, 5)) |
446 | dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; | |
447 | else if (!strncmp("high", maximum_speed, 4)) | |
448 | dwc->maximum_speed = DWC3_DCFG_HIGHSPEED; | |
449 | else if (!strncmp("full", maximum_speed, 4)) | |
450 | dwc->maximum_speed = DWC3_DCFG_FULLSPEED1; | |
451 | else if (!strncmp("low", maximum_speed, 3)) | |
452 | dwc->maximum_speed = DWC3_DCFG_LOWSPEED; | |
453 | else | |
454 | dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; | |
455 | ||
457e84b6 FB |
456 | if (of_get_property(node, "tx-fifo-resize", NULL)) |
457 | dwc->needs_fifo_resize = true; | |
458 | ||
802ca850 CP |
459 | pm_runtime_enable(dev); |
460 | pm_runtime_get_sync(dev); | |
461 | pm_runtime_forbid(dev); | |
72246da4 | 462 | |
3921426b FB |
463 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
464 | if (ret) { | |
465 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
466 | ret = -ENOMEM; | |
467 | goto err0; | |
468 | } | |
469 | ||
72246da4 FB |
470 | ret = dwc3_core_init(dwc); |
471 | if (ret) { | |
802ca850 | 472 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 473 | goto err0; |
72246da4 FB |
474 | } |
475 | ||
0949e99b FB |
476 | mode = DWC3_MODE(dwc->hwparams.hwparams0); |
477 | ||
478 | switch (mode) { | |
0949e99b | 479 | case DWC3_MODE_DEVICE: |
3140e8cb | 480 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
72246da4 FB |
481 | ret = dwc3_gadget_init(dwc); |
482 | if (ret) { | |
802ca850 CP |
483 | dev_err(dev, "failed to initialize gadget\n"); |
484 | goto err1; | |
72246da4 | 485 | } |
d07e8819 FB |
486 | break; |
487 | case DWC3_MODE_HOST: | |
3140e8cb | 488 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
d07e8819 FB |
489 | ret = dwc3_host_init(dwc); |
490 | if (ret) { | |
802ca850 CP |
491 | dev_err(dev, "failed to initialize host\n"); |
492 | goto err1; | |
d07e8819 FB |
493 | } |
494 | break; | |
495 | case DWC3_MODE_DRD: | |
3140e8cb | 496 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); |
d07e8819 FB |
497 | ret = dwc3_host_init(dwc); |
498 | if (ret) { | |
802ca850 CP |
499 | dev_err(dev, "failed to initialize host\n"); |
500 | goto err1; | |
d07e8819 FB |
501 | } |
502 | ||
72246da4 FB |
503 | ret = dwc3_gadget_init(dwc); |
504 | if (ret) { | |
802ca850 CP |
505 | dev_err(dev, "failed to initialize gadget\n"); |
506 | goto err1; | |
72246da4 | 507 | } |
0949e99b FB |
508 | break; |
509 | default: | |
802ca850 CP |
510 | dev_err(dev, "Unsupported mode of operation %d\n", mode); |
511 | goto err1; | |
72246da4 | 512 | } |
0949e99b | 513 | dwc->mode = mode; |
72246da4 FB |
514 | |
515 | ret = dwc3_debugfs_init(dwc); | |
516 | if (ret) { | |
802ca850 CP |
517 | dev_err(dev, "failed to initialize debugfs\n"); |
518 | goto err2; | |
72246da4 FB |
519 | } |
520 | ||
802ca850 | 521 | pm_runtime_allow(dev); |
72246da4 FB |
522 | |
523 | return 0; | |
524 | ||
802ca850 | 525 | err2: |
0949e99b | 526 | switch (mode) { |
0949e99b | 527 | case DWC3_MODE_DEVICE: |
72246da4 | 528 | dwc3_gadget_exit(dwc); |
0949e99b | 529 | break; |
d07e8819 FB |
530 | case DWC3_MODE_HOST: |
531 | dwc3_host_exit(dwc); | |
532 | break; | |
533 | case DWC3_MODE_DRD: | |
534 | dwc3_host_exit(dwc); | |
72246da4 | 535 | dwc3_gadget_exit(dwc); |
d07e8819 | 536 | break; |
0949e99b FB |
537 | default: |
538 | /* do nothing */ | |
539 | break; | |
540 | } | |
72246da4 | 541 | |
72246da4 | 542 | err1: |
802ca850 | 543 | dwc3_core_exit(dwc); |
72246da4 | 544 | |
3921426b FB |
545 | err0: |
546 | dwc3_free_event_buffers(dwc); | |
547 | ||
72246da4 FB |
548 | return ret; |
549 | } | |
550 | ||
551 | static int __devexit dwc3_remove(struct platform_device *pdev) | |
552 | { | |
72246da4 FB |
553 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
554 | struct resource *res; | |
72246da4 FB |
555 | |
556 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
557 | ||
558 | pm_runtime_put(&pdev->dev); | |
559 | pm_runtime_disable(&pdev->dev); | |
560 | ||
561 | dwc3_debugfs_exit(dwc); | |
562 | ||
0949e99b | 563 | switch (dwc->mode) { |
0949e99b | 564 | case DWC3_MODE_DEVICE: |
72246da4 | 565 | dwc3_gadget_exit(dwc); |
0949e99b | 566 | break; |
d07e8819 FB |
567 | case DWC3_MODE_HOST: |
568 | dwc3_host_exit(dwc); | |
569 | break; | |
570 | case DWC3_MODE_DRD: | |
571 | dwc3_host_exit(dwc); | |
72246da4 | 572 | dwc3_gadget_exit(dwc); |
d07e8819 | 573 | break; |
0949e99b FB |
574 | default: |
575 | /* do nothing */ | |
576 | break; | |
577 | } | |
72246da4 FB |
578 | |
579 | dwc3_core_exit(dwc); | |
72246da4 FB |
580 | |
581 | return 0; | |
582 | } | |
583 | ||
72246da4 FB |
584 | static struct platform_driver dwc3_driver = { |
585 | .probe = dwc3_probe, | |
586 | .remove = __devexit_p(dwc3_remove), | |
587 | .driver = { | |
588 | .name = "dwc3", | |
589 | }, | |
72246da4 FB |
590 | }; |
591 | ||
b1116dcc TK |
592 | module_platform_driver(dwc3_driver); |
593 | ||
7ae4fc4d | 594 | MODULE_ALIAS("platform:dwc3"); |
72246da4 FB |
595 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
596 | MODULE_LICENSE("Dual BSD/GPL"); | |
597 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |