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72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
6344475f | 37 | #include <linux/pinctrl/consumer.h> |
72246da4 FB |
38 | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
f7e846f0 | 41 | #include <linux/usb/of.h> |
a45c82b8 | 42 | #include <linux/usb/otg.h> |
72246da4 | 43 | |
6462cbd5 | 44 | #include "platform_data.h" |
72246da4 FB |
45 | #include "core.h" |
46 | #include "gadget.h" | |
47 | #include "io.h" | |
48 | ||
49 | #include "debug.h" | |
50 | ||
8300dd23 FB |
51 | /* -------------------------------------------------------------------------- */ |
52 | ||
3140e8cb SAS |
53 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
54 | { | |
55 | u32 reg; | |
56 | ||
57 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
58 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
59 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
60 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
61 | } | |
8300dd23 | 62 | |
72246da4 FB |
63 | /** |
64 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
65 | * @dwc: pointer to our context structure | |
66 | */ | |
57303488 | 67 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
68 | { |
69 | u32 reg; | |
57303488 | 70 | int ret; |
72246da4 FB |
71 | |
72 | /* Before Resetting PHY, put Core in Reset */ | |
73 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
74 | reg |= DWC3_GCTL_CORESOFTRESET; | |
75 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
76 | ||
77 | /* Assert USB3 PHY reset */ | |
78 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
79 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
80 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
81 | ||
82 | /* Assert USB2 PHY reset */ | |
83 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
84 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
85 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
86 | ||
51e1e7bc FB |
87 | usb_phy_init(dwc->usb2_phy); |
88 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
89 | ret = phy_init(dwc->usb2_generic_phy); |
90 | if (ret < 0) | |
91 | return ret; | |
92 | ||
93 | ret = phy_init(dwc->usb3_generic_phy); | |
94 | if (ret < 0) { | |
95 | phy_exit(dwc->usb2_generic_phy); | |
96 | return ret; | |
97 | } | |
72246da4 FB |
98 | mdelay(100); |
99 | ||
100 | /* Clear USB3 PHY reset */ | |
101 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
102 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
103 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
104 | ||
105 | /* Clear USB2 PHY reset */ | |
106 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
107 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
108 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
109 | ||
45627ac6 PA |
110 | mdelay(100); |
111 | ||
72246da4 FB |
112 | /* After PHYs are stable we can take Core out of reset state */ |
113 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
114 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
115 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
57303488 KVA |
116 | |
117 | return 0; | |
72246da4 FB |
118 | } |
119 | ||
c5cc74e8 HK |
120 | /** |
121 | * dwc3_soft_reset - Issue soft reset | |
122 | * @dwc: Pointer to our controller context structure | |
123 | */ | |
124 | static int dwc3_soft_reset(struct dwc3 *dwc) | |
125 | { | |
126 | unsigned long timeout; | |
127 | u32 reg; | |
128 | ||
129 | timeout = jiffies + msecs_to_jiffies(500); | |
130 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
131 | do { | |
132 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
133 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
134 | break; | |
135 | ||
136 | if (time_after(jiffies, timeout)) { | |
137 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
138 | return -ETIMEDOUT; | |
139 | } | |
140 | ||
141 | cpu_relax(); | |
142 | } while (true); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
db2be4e9 NB |
147 | /* |
148 | * dwc3_frame_length_adjustment - Adjusts frame length if required | |
149 | * @dwc3: Pointer to our controller context structure | |
150 | * @fladj: Value of GFLADJ_30MHZ to adjust frame length | |
151 | */ | |
152 | static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj) | |
153 | { | |
154 | u32 reg; | |
155 | u32 dft; | |
156 | ||
157 | if (dwc->revision < DWC3_REVISION_250A) | |
158 | return; | |
159 | ||
160 | if (fladj == 0) | |
161 | return; | |
162 | ||
163 | reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); | |
164 | dft = reg & DWC3_GFLADJ_30MHZ_MASK; | |
165 | if (!dev_WARN_ONCE(dwc->dev, dft == fladj, | |
166 | "request value same as default, ignoring\n")) { | |
167 | reg &= ~DWC3_GFLADJ_30MHZ_MASK; | |
168 | reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj; | |
169 | dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); | |
170 | } | |
171 | } | |
172 | ||
72246da4 FB |
173 | /** |
174 | * dwc3_free_one_event_buffer - Frees one event buffer | |
175 | * @dwc: Pointer to our controller context structure | |
176 | * @evt: Pointer to event buffer to be freed | |
177 | */ | |
178 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
179 | struct dwc3_event_buffer *evt) | |
180 | { | |
181 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
182 | } |
183 | ||
184 | /** | |
1d046793 | 185 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
186 | * @dwc: Pointer to our controller context structure |
187 | * @length: size of the event buffer | |
188 | * | |
1d046793 | 189 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
190 | * otherwise ERR_PTR(errno). |
191 | */ | |
67d0b500 FB |
192 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
193 | unsigned length) | |
72246da4 FB |
194 | { |
195 | struct dwc3_event_buffer *evt; | |
196 | ||
380f0d28 | 197 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
198 | if (!evt) |
199 | return ERR_PTR(-ENOMEM); | |
200 | ||
201 | evt->dwc = dwc; | |
202 | evt->length = length; | |
203 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
204 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 205 | if (!evt->buf) |
72246da4 | 206 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
207 | |
208 | return evt; | |
209 | } | |
210 | ||
211 | /** | |
212 | * dwc3_free_event_buffers - frees all allocated event buffers | |
213 | * @dwc: Pointer to our controller context structure | |
214 | */ | |
215 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
216 | { | |
217 | struct dwc3_event_buffer *evt; | |
218 | int i; | |
219 | ||
9f622b2a | 220 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 221 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 222 | if (evt) |
72246da4 | 223 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
224 | } |
225 | } | |
226 | ||
227 | /** | |
228 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 229 | * @dwc: pointer to our controller context structure |
72246da4 FB |
230 | * @length: size of event buffer |
231 | * | |
1d046793 | 232 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
233 | * may contain some buffers allocated but not all which were requested. |
234 | */ | |
41ac7b3a | 235 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 236 | { |
9f622b2a | 237 | int num; |
72246da4 FB |
238 | int i; |
239 | ||
9f622b2a FB |
240 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
241 | dwc->num_event_buffers = num; | |
242 | ||
380f0d28 FB |
243 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
244 | GFP_KERNEL); | |
734d5a53 | 245 | if (!dwc->ev_buffs) |
457d3f21 | 246 | return -ENOMEM; |
457d3f21 | 247 | |
72246da4 FB |
248 | for (i = 0; i < num; i++) { |
249 | struct dwc3_event_buffer *evt; | |
250 | ||
251 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
252 | if (IS_ERR(evt)) { | |
253 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
254 | return PTR_ERR(evt); | |
255 | } | |
256 | dwc->ev_buffs[i] = evt; | |
257 | } | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | /** | |
263 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 264 | * @dwc: pointer to our controller context structure |
72246da4 FB |
265 | * |
266 | * Returns 0 on success otherwise negative errno. | |
267 | */ | |
7acd85e0 | 268 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
269 | { |
270 | struct dwc3_event_buffer *evt; | |
271 | int n; | |
272 | ||
9f622b2a | 273 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
274 | evt = dwc->ev_buffs[n]; |
275 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
276 | evt->buf, (unsigned long long) evt->dma, | |
277 | evt->length); | |
278 | ||
7acd85e0 PZ |
279 | evt->lpos = 0; |
280 | ||
72246da4 FB |
281 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
282 | lower_32_bits(evt->dma)); | |
283 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
284 | upper_32_bits(evt->dma)); | |
285 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 286 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
287 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
294 | { | |
295 | struct dwc3_event_buffer *evt; | |
296 | int n; | |
297 | ||
9f622b2a | 298 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 299 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
300 | |
301 | evt->lpos = 0; | |
302 | ||
72246da4 FB |
303 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
304 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
305 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
306 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
307 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
308 | } | |
309 | } | |
310 | ||
0ffcaf37 FB |
311 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
312 | { | |
313 | if (!dwc->has_hibernation) | |
314 | return 0; | |
315 | ||
316 | if (!dwc->nr_scratch) | |
317 | return 0; | |
318 | ||
319 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
320 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
321 | if (!dwc->scratchbuf) | |
322 | return -ENOMEM; | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
328 | { | |
329 | dma_addr_t scratch_addr; | |
330 | u32 param; | |
331 | int ret; | |
332 | ||
333 | if (!dwc->has_hibernation) | |
334 | return 0; | |
335 | ||
336 | if (!dwc->nr_scratch) | |
337 | return 0; | |
338 | ||
339 | /* should never fall here */ | |
340 | if (!WARN_ON(dwc->scratchbuf)) | |
341 | return 0; | |
342 | ||
343 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
344 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
345 | DMA_BIDIRECTIONAL); | |
346 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
347 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
348 | ret = -EFAULT; | |
349 | goto err0; | |
350 | } | |
351 | ||
352 | dwc->scratch_addr = scratch_addr; | |
353 | ||
354 | param = lower_32_bits(scratch_addr); | |
355 | ||
356 | ret = dwc3_send_gadget_generic_command(dwc, | |
357 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
358 | if (ret < 0) | |
359 | goto err1; | |
360 | ||
361 | param = upper_32_bits(scratch_addr); | |
362 | ||
363 | ret = dwc3_send_gadget_generic_command(dwc, | |
364 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
365 | if (ret < 0) | |
366 | goto err1; | |
367 | ||
368 | return 0; | |
369 | ||
370 | err1: | |
371 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
372 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
373 | ||
374 | err0: | |
375 | return ret; | |
376 | } | |
377 | ||
378 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
379 | { | |
380 | if (!dwc->has_hibernation) | |
381 | return; | |
382 | ||
383 | if (!dwc->nr_scratch) | |
384 | return; | |
385 | ||
386 | /* should never fall here */ | |
387 | if (!WARN_ON(dwc->scratchbuf)) | |
388 | return; | |
389 | ||
390 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
391 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
392 | kfree(dwc->scratchbuf); | |
393 | } | |
394 | ||
789451f6 FB |
395 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
396 | { | |
397 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
398 | ||
399 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
400 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
401 | ||
73815280 | 402 | dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", |
789451f6 FB |
403 | dwc->num_in_eps, dwc->num_out_eps); |
404 | } | |
405 | ||
41ac7b3a | 406 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
407 | { |
408 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
409 | ||
410 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
411 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
412 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
413 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
414 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
415 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
416 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
417 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
418 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
419 | } | |
420 | ||
b5a65c40 HR |
421 | /** |
422 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
423 | * @dwc: Pointer to our controller context structure | |
88bc9d19 HK |
424 | * |
425 | * Returns 0 on success. The USB PHY interfaces are configured but not | |
426 | * initialized. The PHY interfaces and the PHYs get initialized together with | |
427 | * the core in dwc3_core_init. | |
b5a65c40 | 428 | */ |
88bc9d19 | 429 | static int dwc3_phy_setup(struct dwc3 *dwc) |
b5a65c40 HR |
430 | { |
431 | u32 reg; | |
88bc9d19 | 432 | int ret; |
b5a65c40 HR |
433 | |
434 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
435 | ||
2164a476 HR |
436 | /* |
437 | * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY | |
438 | * to '0' during coreConsultant configuration. So default value | |
439 | * will be '0' when the core is reset. Application needs to set it | |
440 | * to '1' after the core initialization is completed. | |
441 | */ | |
442 | if (dwc->revision > DWC3_REVISION_194A) | |
443 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
444 | ||
b5a65c40 HR |
445 | if (dwc->u2ss_inp3_quirk) |
446 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
447 | ||
df31f5b3 HR |
448 | if (dwc->req_p1p2p3_quirk) |
449 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
450 | ||
a2a1d0f5 HR |
451 | if (dwc->del_p1p2p3_quirk) |
452 | reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; | |
453 | ||
41c06ffd HR |
454 | if (dwc->del_phy_power_chg_quirk) |
455 | reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; | |
456 | ||
fb67afca HR |
457 | if (dwc->lfps_filter_quirk) |
458 | reg |= DWC3_GUSB3PIPECTL_LFPSFILT; | |
459 | ||
14f4ac53 HR |
460 | if (dwc->rx_detect_poll_quirk) |
461 | reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; | |
462 | ||
6b6a0c9a HR |
463 | if (dwc->tx_de_emphasis_quirk) |
464 | reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); | |
465 | ||
cd72f890 | 466 | if (dwc->dis_u3_susphy_quirk) |
59acfa20 HR |
467 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; |
468 | ||
b5a65c40 HR |
469 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
470 | ||
2164a476 HR |
471 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
472 | ||
3e10a2ce HK |
473 | /* Select the HS PHY interface */ |
474 | switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { | |
475 | case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: | |
43cacb03 FB |
476 | if (dwc->hsphy_interface && |
477 | !strncmp(dwc->hsphy_interface, "utmi", 4)) { | |
3e10a2ce | 478 | reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 479 | break; |
43cacb03 FB |
480 | } else if (dwc->hsphy_interface && |
481 | !strncmp(dwc->hsphy_interface, "ulpi", 4)) { | |
3e10a2ce | 482 | reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; |
88bc9d19 | 483 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
3e10a2ce | 484 | } else { |
88bc9d19 HK |
485 | /* Relying on default value. */ |
486 | if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) | |
487 | break; | |
3e10a2ce HK |
488 | } |
489 | /* FALLTHROUGH */ | |
88bc9d19 HK |
490 | case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: |
491 | /* Making sure the interface and PHY are operational */ | |
492 | ret = dwc3_soft_reset(dwc); | |
493 | if (ret) | |
494 | return ret; | |
495 | ||
496 | udelay(1); | |
497 | ||
498 | ret = dwc3_ulpi_init(dwc); | |
499 | if (ret) | |
500 | return ret; | |
501 | /* FALLTHROUGH */ | |
3e10a2ce HK |
502 | default: |
503 | break; | |
504 | } | |
505 | ||
2164a476 HR |
506 | /* |
507 | * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to | |
508 | * '0' during coreConsultant configuration. So default value will | |
509 | * be '0' when the core is reset. Application needs to set it to | |
510 | * '1' after the core initialization is completed. | |
511 | */ | |
512 | if (dwc->revision > DWC3_REVISION_194A) | |
513 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
514 | ||
cd72f890 | 515 | if (dwc->dis_u2_susphy_quirk) |
0effe0a3 HR |
516 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
517 | ||
2164a476 | 518 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
88bc9d19 HK |
519 | |
520 | return 0; | |
b5a65c40 HR |
521 | } |
522 | ||
72246da4 FB |
523 | /** |
524 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
525 | * @dwc: Pointer to our controller context structure | |
526 | * | |
527 | * Returns 0 on success otherwise negative errno. | |
528 | */ | |
41ac7b3a | 529 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 | 530 | { |
0ffcaf37 | 531 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
532 | u32 reg; |
533 | int ret; | |
534 | ||
7650bd74 SAS |
535 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
536 | /* This should read as U3 followed by revision number */ | |
537 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
538 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
539 | ret = -ENODEV; | |
540 | goto err0; | |
541 | } | |
248b122b | 542 | dwc->revision = reg; |
7650bd74 | 543 | |
fa0ea13e FB |
544 | /* |
545 | * Write Linux Version Code to our GUID register so it's easy to figure | |
546 | * out which kernel version a bug was found. | |
547 | */ | |
548 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
549 | ||
0e1e5c47 PZ |
550 | /* Handle USB2.0-only core configuration */ |
551 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
552 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
553 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
554 | dwc->maximum_speed = USB_SPEED_HIGH; | |
555 | } | |
556 | ||
72246da4 | 557 | /* issue device SoftReset too */ |
c5cc74e8 HK |
558 | ret = dwc3_soft_reset(dwc); |
559 | if (ret) | |
560 | goto err0; | |
72246da4 | 561 | |
57303488 KVA |
562 | ret = dwc3_core_soft_reset(dwc); |
563 | if (ret) | |
564 | goto err0; | |
58a0f23f | 565 | |
4878a028 | 566 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 567 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 568 | |
164d7731 | 569 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 570 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
571 | /** |
572 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
573 | * issue which would cause xHCI compliance tests to fail. | |
574 | * | |
575 | * Because of that we cannot enable clock gating on such | |
576 | * configurations. | |
577 | * | |
578 | * Refers to: | |
579 | * | |
580 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
581 | * SOF/ITP Mode Used | |
582 | */ | |
583 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
584 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
585 | (dwc->revision >= DWC3_REVISION_210A && | |
586 | dwc->revision <= DWC3_REVISION_250A)) | |
587 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
588 | else | |
589 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 590 | break; |
0ffcaf37 FB |
591 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
592 | /* enable hibernation here */ | |
593 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
594 | |
595 | /* | |
596 | * REVISIT Enabling this bit so that host-mode hibernation | |
597 | * will work. Device-mode hibernation is not yet implemented. | |
598 | */ | |
599 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 600 | break; |
4878a028 SAS |
601 | default: |
602 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
603 | } | |
604 | ||
946bd579 HR |
605 | /* check if current dwc3 is on simulation board */ |
606 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
607 | dev_dbg(dwc->dev, "it is on FPGA board\n"); | |
608 | dwc->is_fpga = true; | |
609 | } | |
610 | ||
3b81221a HR |
611 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
612 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
613 | ||
614 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
615 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
616 | else | |
617 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
618 | ||
9a5b2f31 HR |
619 | if (dwc->u2exit_lfps_quirk) |
620 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
621 | ||
4878a028 SAS |
622 | /* |
623 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 624 | * where the device can fail to connect at SuperSpeed |
4878a028 | 625 | * and falls back to high-speed mode which causes |
1d046793 | 626 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
627 | */ |
628 | if (dwc->revision < DWC3_REVISION_190A) | |
629 | reg |= DWC3_GCTL_U2RSTECN; | |
630 | ||
789451f6 FB |
631 | dwc3_core_num_eps(dwc); |
632 | ||
4878a028 SAS |
633 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
634 | ||
0ffcaf37 FB |
635 | ret = dwc3_alloc_scratch_buffers(dwc); |
636 | if (ret) | |
637 | goto err1; | |
638 | ||
639 | ret = dwc3_setup_scratch_buffers(dwc); | |
640 | if (ret) | |
641 | goto err2; | |
642 | ||
72246da4 FB |
643 | return 0; |
644 | ||
0ffcaf37 FB |
645 | err2: |
646 | dwc3_free_scratch_buffers(dwc); | |
647 | ||
648 | err1: | |
649 | usb_phy_shutdown(dwc->usb2_phy); | |
650 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
651 | phy_exit(dwc->usb2_generic_phy); |
652 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 653 | |
72246da4 FB |
654 | err0: |
655 | return ret; | |
656 | } | |
657 | ||
658 | static void dwc3_core_exit(struct dwc3 *dwc) | |
659 | { | |
0ffcaf37 | 660 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
661 | usb_phy_shutdown(dwc->usb2_phy); |
662 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
663 | phy_exit(dwc->usb2_generic_phy); |
664 | phy_exit(dwc->usb3_generic_phy); | |
72246da4 FB |
665 | } |
666 | ||
3c9f94ac | 667 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 668 | { |
3c9f94ac | 669 | struct device *dev = dwc->dev; |
941ea361 | 670 | struct device_node *node = dev->of_node; |
3c9f94ac | 671 | int ret; |
72246da4 | 672 | |
5088b6f5 KVA |
673 | if (node) { |
674 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
675 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
676 | } else { |
677 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
678 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
679 | } |
680 | ||
d105e7f8 FB |
681 | if (IS_ERR(dwc->usb2_phy)) { |
682 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
683 | if (ret == -ENXIO || ret == -ENODEV) { |
684 | dwc->usb2_phy = NULL; | |
685 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 686 | return ret; |
122f06e6 KVA |
687 | } else { |
688 | dev_err(dev, "no usb2 phy configured\n"); | |
689 | return ret; | |
690 | } | |
51e1e7bc FB |
691 | } |
692 | ||
d105e7f8 | 693 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 694 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
695 | if (ret == -ENXIO || ret == -ENODEV) { |
696 | dwc->usb3_phy = NULL; | |
697 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 698 | return ret; |
122f06e6 KVA |
699 | } else { |
700 | dev_err(dev, "no usb3 phy configured\n"); | |
701 | return ret; | |
702 | } | |
51e1e7bc FB |
703 | } |
704 | ||
57303488 KVA |
705 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
706 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
707 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
708 | if (ret == -ENOSYS || ret == -ENODEV) { | |
709 | dwc->usb2_generic_phy = NULL; | |
710 | } else if (ret == -EPROBE_DEFER) { | |
711 | return ret; | |
712 | } else { | |
713 | dev_err(dev, "no usb2 phy configured\n"); | |
714 | return ret; | |
715 | } | |
716 | } | |
717 | ||
718 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
719 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
720 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
721 | if (ret == -ENOSYS || ret == -ENODEV) { | |
722 | dwc->usb3_generic_phy = NULL; | |
723 | } else if (ret == -EPROBE_DEFER) { | |
724 | return ret; | |
725 | } else { | |
726 | dev_err(dev, "no usb3 phy configured\n"); | |
727 | return ret; | |
728 | } | |
729 | } | |
730 | ||
3c9f94ac FB |
731 | return 0; |
732 | } | |
733 | ||
5f94adfe FB |
734 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
735 | { | |
736 | struct device *dev = dwc->dev; | |
737 | int ret; | |
738 | ||
739 | switch (dwc->dr_mode) { | |
740 | case USB_DR_MODE_PERIPHERAL: | |
741 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
742 | ret = dwc3_gadget_init(dwc); | |
743 | if (ret) { | |
744 | dev_err(dev, "failed to initialize gadget\n"); | |
745 | return ret; | |
746 | } | |
747 | break; | |
748 | case USB_DR_MODE_HOST: | |
749 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
750 | ret = dwc3_host_init(dwc); | |
751 | if (ret) { | |
752 | dev_err(dev, "failed to initialize host\n"); | |
753 | return ret; | |
754 | } | |
755 | break; | |
756 | case USB_DR_MODE_OTG: | |
757 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
758 | ret = dwc3_host_init(dwc); | |
759 | if (ret) { | |
760 | dev_err(dev, "failed to initialize host\n"); | |
761 | return ret; | |
762 | } | |
763 | ||
764 | ret = dwc3_gadget_init(dwc); | |
765 | if (ret) { | |
766 | dev_err(dev, "failed to initialize gadget\n"); | |
767 | return ret; | |
768 | } | |
769 | break; | |
770 | default: | |
771 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
779 | { | |
780 | switch (dwc->dr_mode) { | |
781 | case USB_DR_MODE_PERIPHERAL: | |
782 | dwc3_gadget_exit(dwc); | |
783 | break; | |
784 | case USB_DR_MODE_HOST: | |
785 | dwc3_host_exit(dwc); | |
786 | break; | |
787 | case USB_DR_MODE_OTG: | |
788 | dwc3_host_exit(dwc); | |
789 | dwc3_gadget_exit(dwc); | |
790 | break; | |
791 | default: | |
792 | /* do nothing */ | |
793 | break; | |
794 | } | |
795 | } | |
796 | ||
3c9f94ac FB |
797 | #define DWC3_ALIGN_MASK (16 - 1) |
798 | ||
799 | static int dwc3_probe(struct platform_device *pdev) | |
800 | { | |
801 | struct device *dev = &pdev->dev; | |
802 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
3c9f94ac FB |
803 | struct resource *res; |
804 | struct dwc3 *dwc; | |
80caf7d2 | 805 | u8 lpm_nyet_threshold; |
6b6a0c9a | 806 | u8 tx_de_emphasis; |
460d098c | 807 | u8 hird_threshold; |
db2be4e9 | 808 | u32 fladj = 0; |
3c9f94ac | 809 | |
b09e99ee | 810 | int ret; |
3c9f94ac FB |
811 | |
812 | void __iomem *regs; | |
813 | void *mem; | |
814 | ||
815 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 816 | if (!mem) |
3c9f94ac | 817 | return -ENOMEM; |
734d5a53 | 818 | |
3c9f94ac FB |
819 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
820 | dwc->mem = mem; | |
821 | dwc->dev = dev; | |
822 | ||
823 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
824 | if (!res) { | |
825 | dev_err(dev, "missing IRQ\n"); | |
826 | return -ENODEV; | |
827 | } | |
828 | dwc->xhci_resources[1].start = res->start; | |
829 | dwc->xhci_resources[1].end = res->end; | |
830 | dwc->xhci_resources[1].flags = res->flags; | |
831 | dwc->xhci_resources[1].name = res->name; | |
832 | ||
833 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
834 | if (!res) { | |
835 | dev_err(dev, "missing memory resource\n"); | |
836 | return -ENODEV; | |
837 | } | |
838 | ||
f32a5e23 VG |
839 | dwc->xhci_resources[0].start = res->start; |
840 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
841 | DWC3_XHCI_REGS_END; | |
842 | dwc->xhci_resources[0].flags = res->flags; | |
843 | dwc->xhci_resources[0].name = res->name; | |
844 | ||
845 | res->start += DWC3_GLOBALS_REGS_START; | |
846 | ||
847 | /* | |
848 | * Request memory region but exclude xHCI regs, | |
849 | * since it will be requested by the xhci-plat driver. | |
850 | */ | |
851 | regs = devm_ioremap_resource(dev, res); | |
3da1f6ee FB |
852 | if (IS_ERR(regs)) { |
853 | ret = PTR_ERR(regs); | |
854 | goto err0; | |
855 | } | |
f32a5e23 VG |
856 | |
857 | dwc->regs = regs; | |
858 | dwc->regs_size = resource_size(res); | |
f32a5e23 | 859 | |
80caf7d2 HR |
860 | /* default to highest possible threshold */ |
861 | lpm_nyet_threshold = 0xff; | |
862 | ||
6b6a0c9a HR |
863 | /* default to -3.5dB de-emphasis */ |
864 | tx_de_emphasis = 1; | |
865 | ||
460d098c HR |
866 | /* |
867 | * default to assert utmi_sleep_n and use maximum allowed HIRD | |
868 | * threshold value of 0b1100 | |
869 | */ | |
870 | hird_threshold = 12; | |
871 | ||
63863b98 | 872 | dwc->maximum_speed = usb_get_maximum_speed(dev); |
06e7114f | 873 | dwc->dr_mode = usb_get_dr_mode(dev); |
63863b98 | 874 | |
3d128919 | 875 | dwc->has_lpm_erratum = device_property_read_bool(dev, |
80caf7d2 | 876 | "snps,has-lpm-erratum"); |
3d128919 | 877 | device_property_read_u8(dev, "snps,lpm-nyet-threshold", |
80caf7d2 | 878 | &lpm_nyet_threshold); |
3d128919 | 879 | dwc->is_utmi_l1_suspend = device_property_read_bool(dev, |
460d098c | 880 | "snps,is-utmi-l1-suspend"); |
3d128919 | 881 | device_property_read_u8(dev, "snps,hird-threshold", |
460d098c | 882 | &hird_threshold); |
3d128919 | 883 | dwc->usb3_lpm_capable = device_property_read_bool(dev, |
eac68e8f | 884 | "snps,usb3_lpm_capable"); |
3c9f94ac | 885 | |
3d128919 | 886 | dwc->needs_fifo_resize = device_property_read_bool(dev, |
80caf7d2 | 887 | "tx-fifo-resize"); |
3b81221a | 888 | |
3d128919 | 889 | dwc->disable_scramble_quirk = device_property_read_bool(dev, |
3b81221a | 890 | "snps,disable_scramble_quirk"); |
3d128919 | 891 | dwc->u2exit_lfps_quirk = device_property_read_bool(dev, |
9a5b2f31 | 892 | "snps,u2exit_lfps_quirk"); |
3d128919 | 893 | dwc->u2ss_inp3_quirk = device_property_read_bool(dev, |
b5a65c40 | 894 | "snps,u2ss_inp3_quirk"); |
3d128919 | 895 | dwc->req_p1p2p3_quirk = device_property_read_bool(dev, |
df31f5b3 | 896 | "snps,req_p1p2p3_quirk"); |
3d128919 | 897 | dwc->del_p1p2p3_quirk = device_property_read_bool(dev, |
a2a1d0f5 | 898 | "snps,del_p1p2p3_quirk"); |
3d128919 | 899 | dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, |
41c06ffd | 900 | "snps,del_phy_power_chg_quirk"); |
3d128919 | 901 | dwc->lfps_filter_quirk = device_property_read_bool(dev, |
fb67afca | 902 | "snps,lfps_filter_quirk"); |
3d128919 | 903 | dwc->rx_detect_poll_quirk = device_property_read_bool(dev, |
14f4ac53 | 904 | "snps,rx_detect_poll_quirk"); |
3d128919 | 905 | dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, |
59acfa20 | 906 | "snps,dis_u3_susphy_quirk"); |
3d128919 | 907 | dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, |
0effe0a3 | 908 | "snps,dis_u2_susphy_quirk"); |
6b6a0c9a | 909 | |
3d128919 | 910 | dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, |
6b6a0c9a | 911 | "snps,tx_de_emphasis_quirk"); |
3d128919 | 912 | device_property_read_u8(dev, "snps,tx_de_emphasis", |
6b6a0c9a | 913 | &tx_de_emphasis); |
3d128919 HK |
914 | device_property_read_string(dev, "snps,hsphy_interface", |
915 | &dwc->hsphy_interface); | |
916 | device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", | |
917 | &fladj); | |
918 | ||
919 | if (pdata) { | |
3c9f94ac | 920 | dwc->maximum_speed = pdata->maximum_speed; |
80caf7d2 HR |
921 | dwc->has_lpm_erratum = pdata->has_lpm_erratum; |
922 | if (pdata->lpm_nyet_threshold) | |
923 | lpm_nyet_threshold = pdata->lpm_nyet_threshold; | |
460d098c HR |
924 | dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; |
925 | if (pdata->hird_threshold) | |
926 | hird_threshold = pdata->hird_threshold; | |
3c9f94ac FB |
927 | |
928 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
eac68e8f | 929 | dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; |
3c9f94ac | 930 | dwc->dr_mode = pdata->dr_mode; |
3b81221a HR |
931 | |
932 | dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; | |
9a5b2f31 | 933 | dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; |
b5a65c40 | 934 | dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; |
df31f5b3 | 935 | dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; |
a2a1d0f5 | 936 | dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; |
41c06ffd | 937 | dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; |
fb67afca | 938 | dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; |
14f4ac53 | 939 | dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; |
59acfa20 | 940 | dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; |
0effe0a3 | 941 | dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; |
6b6a0c9a HR |
942 | |
943 | dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; | |
944 | if (pdata->tx_de_emphasis) | |
945 | tx_de_emphasis = pdata->tx_de_emphasis; | |
3e10a2ce HK |
946 | |
947 | dwc->hsphy_interface = pdata->hsphy_interface; | |
db2be4e9 | 948 | fladj = pdata->fladj_value; |
3c9f94ac FB |
949 | } |
950 | ||
951 | /* default to superspeed if no maximum_speed passed */ | |
952 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
953 | dwc->maximum_speed = USB_SPEED_SUPER; | |
954 | ||
80caf7d2 | 955 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
6b6a0c9a | 956 | dwc->tx_de_emphasis = tx_de_emphasis; |
80caf7d2 | 957 | |
460d098c HR |
958 | dwc->hird_threshold = hird_threshold |
959 | | (dwc->is_utmi_l1_suspend << 4); | |
960 | ||
6c89cce0 | 961 | platform_set_drvdata(pdev, dwc); |
2917e718 | 962 | dwc3_cache_hwparams(dwc); |
6c89cce0 | 963 | |
88bc9d19 HK |
964 | ret = dwc3_phy_setup(dwc); |
965 | if (ret) | |
966 | goto err0; | |
45bb7de2 | 967 | |
3c9f94ac FB |
968 | ret = dwc3_core_get_phy(dwc); |
969 | if (ret) | |
3da1f6ee | 970 | goto err0; |
3c9f94ac | 971 | |
72246da4 | 972 | spin_lock_init(&dwc->lock); |
72246da4 | 973 | |
19bacdc9 HK |
974 | if (!dev->dma_mask) { |
975 | dev->dma_mask = dev->parent->dma_mask; | |
976 | dev->dma_parms = dev->parent->dma_parms; | |
977 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
978 | } | |
ddff14f1 | 979 | |
802ca850 CP |
980 | pm_runtime_enable(dev); |
981 | pm_runtime_get_sync(dev); | |
982 | pm_runtime_forbid(dev); | |
72246da4 | 983 | |
3921426b FB |
984 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
985 | if (ret) { | |
986 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
987 | ret = -ENOMEM; | |
3da1f6ee | 988 | goto err1; |
3921426b FB |
989 | } |
990 | ||
32a4a135 FB |
991 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
992 | dwc->dr_mode = USB_DR_MODE_HOST; | |
993 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
994 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
995 | ||
996 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
997 | dwc->dr_mode = USB_DR_MODE_OTG; | |
998 | ||
72246da4 FB |
999 | ret = dwc3_core_init(dwc); |
1000 | if (ret) { | |
802ca850 | 1001 | dev_err(dev, "failed to initialize core\n"); |
3da1f6ee | 1002 | goto err1; |
72246da4 FB |
1003 | } |
1004 | ||
db2be4e9 NB |
1005 | /* Adjust Frame Length */ |
1006 | dwc3_frame_length_adjustment(dwc, fladj); | |
1007 | ||
3088f108 KVA |
1008 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
1009 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
57303488 KVA |
1010 | ret = phy_power_on(dwc->usb2_generic_phy); |
1011 | if (ret < 0) | |
3da1f6ee | 1012 | goto err2; |
57303488 KVA |
1013 | |
1014 | ret = phy_power_on(dwc->usb3_generic_phy); | |
1015 | if (ret < 0) | |
3da1f6ee | 1016 | goto err3; |
3088f108 | 1017 | |
f122d33e FB |
1018 | ret = dwc3_event_buffers_setup(dwc); |
1019 | if (ret) { | |
1020 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
3da1f6ee | 1021 | goto err4; |
f122d33e FB |
1022 | } |
1023 | ||
5f94adfe FB |
1024 | ret = dwc3_core_init_mode(dwc); |
1025 | if (ret) | |
3da1f6ee | 1026 | goto err5; |
72246da4 FB |
1027 | |
1028 | ret = dwc3_debugfs_init(dwc); | |
1029 | if (ret) { | |
802ca850 | 1030 | dev_err(dev, "failed to initialize debugfs\n"); |
3da1f6ee | 1031 | goto err6; |
72246da4 FB |
1032 | } |
1033 | ||
802ca850 | 1034 | pm_runtime_allow(dev); |
72246da4 FB |
1035 | |
1036 | return 0; | |
1037 | ||
3da1f6ee | 1038 | err6: |
5f94adfe | 1039 | dwc3_core_exit_mode(dwc); |
72246da4 | 1040 | |
3da1f6ee | 1041 | err5: |
f122d33e FB |
1042 | dwc3_event_buffers_cleanup(dwc); |
1043 | ||
3da1f6ee | 1044 | err4: |
57303488 KVA |
1045 | phy_power_off(dwc->usb3_generic_phy); |
1046 | ||
3da1f6ee | 1047 | err3: |
57303488 KVA |
1048 | phy_power_off(dwc->usb2_generic_phy); |
1049 | ||
3da1f6ee | 1050 | err2: |
501fae51 KVA |
1051 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1052 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 1053 | dwc3_core_exit(dwc); |
72246da4 | 1054 | |
3da1f6ee | 1055 | err1: |
3921426b | 1056 | dwc3_free_event_buffers(dwc); |
88bc9d19 | 1057 | dwc3_ulpi_exit(dwc); |
3921426b | 1058 | |
3da1f6ee FB |
1059 | err0: |
1060 | /* | |
1061 | * restore res->start back to its original value so that, in case the | |
1062 | * probe is deferred, we don't end up getting error in request the | |
1063 | * memory region the next time probe is called. | |
1064 | */ | |
1065 | res->start -= DWC3_GLOBALS_REGS_START; | |
1066 | ||
72246da4 FB |
1067 | return ret; |
1068 | } | |
1069 | ||
fb4e98ab | 1070 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 1071 | { |
72246da4 | 1072 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
3da1f6ee FB |
1073 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1074 | ||
1075 | /* | |
1076 | * restore res->start back to its original value so that, in case the | |
1077 | * probe is deferred, we don't end up getting error in request the | |
1078 | * memory region the next time probe is called. | |
1079 | */ | |
1080 | res->start -= DWC3_GLOBALS_REGS_START; | |
72246da4 | 1081 | |
dc99f16f FB |
1082 | dwc3_debugfs_exit(dwc); |
1083 | dwc3_core_exit_mode(dwc); | |
1084 | dwc3_event_buffers_cleanup(dwc); | |
1085 | dwc3_free_event_buffers(dwc); | |
1086 | ||
8ba007a9 KVA |
1087 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
1088 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
57303488 KVA |
1089 | phy_power_off(dwc->usb2_generic_phy); |
1090 | phy_power_off(dwc->usb3_generic_phy); | |
8ba007a9 | 1091 | |
72246da4 | 1092 | dwc3_core_exit(dwc); |
88bc9d19 | 1093 | dwc3_ulpi_exit(dwc); |
72246da4 | 1094 | |
16b972a5 | 1095 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
1096 | pm_runtime_disable(&pdev->dev); |
1097 | ||
72246da4 FB |
1098 | return 0; |
1099 | } | |
1100 | ||
19fda7cd | 1101 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
1102 | static int dwc3_suspend(struct device *dev) |
1103 | { | |
1104 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1105 | unsigned long flags; | |
1106 | ||
1107 | spin_lock_irqsave(&dwc->lock, flags); | |
1108 | ||
a45c82b8 RK |
1109 | switch (dwc->dr_mode) { |
1110 | case USB_DR_MODE_PERIPHERAL: | |
1111 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1112 | dwc3_gadget_suspend(dwc); |
1113 | /* FALLTHROUGH */ | |
a45c82b8 | 1114 | case USB_DR_MODE_HOST: |
7415f17c | 1115 | default: |
0b0231aa | 1116 | dwc3_event_buffers_cleanup(dwc); |
7415f17c FB |
1117 | break; |
1118 | } | |
1119 | ||
1120 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
1121 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1122 | ||
1123 | usb_phy_shutdown(dwc->usb3_phy); | |
1124 | usb_phy_shutdown(dwc->usb2_phy); | |
57303488 KVA |
1125 | phy_exit(dwc->usb2_generic_phy); |
1126 | phy_exit(dwc->usb3_generic_phy); | |
7415f17c | 1127 | |
6344475f SN |
1128 | pinctrl_pm_select_sleep_state(dev); |
1129 | ||
7415f17c FB |
1130 | return 0; |
1131 | } | |
1132 | ||
1133 | static int dwc3_resume(struct device *dev) | |
1134 | { | |
1135 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
1136 | unsigned long flags; | |
57303488 | 1137 | int ret; |
7415f17c | 1138 | |
6344475f SN |
1139 | pinctrl_pm_select_default_state(dev); |
1140 | ||
7415f17c FB |
1141 | usb_phy_init(dwc->usb3_phy); |
1142 | usb_phy_init(dwc->usb2_phy); | |
57303488 KVA |
1143 | ret = phy_init(dwc->usb2_generic_phy); |
1144 | if (ret < 0) | |
1145 | return ret; | |
1146 | ||
1147 | ret = phy_init(dwc->usb3_generic_phy); | |
1148 | if (ret < 0) | |
1149 | goto err_usb2phy_init; | |
7415f17c FB |
1150 | |
1151 | spin_lock_irqsave(&dwc->lock, flags); | |
1152 | ||
0b0231aa | 1153 | dwc3_event_buffers_setup(dwc); |
7415f17c FB |
1154 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); |
1155 | ||
a45c82b8 RK |
1156 | switch (dwc->dr_mode) { |
1157 | case USB_DR_MODE_PERIPHERAL: | |
1158 | case USB_DR_MODE_OTG: | |
7415f17c FB |
1159 | dwc3_gadget_resume(dwc); |
1160 | /* FALLTHROUGH */ | |
a45c82b8 | 1161 | case USB_DR_MODE_HOST: |
7415f17c FB |
1162 | default: |
1163 | /* do nothing */ | |
1164 | break; | |
1165 | } | |
1166 | ||
1167 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1168 | ||
1169 | pm_runtime_disable(dev); | |
1170 | pm_runtime_set_active(dev); | |
1171 | pm_runtime_enable(dev); | |
1172 | ||
1173 | return 0; | |
57303488 KVA |
1174 | |
1175 | err_usb2phy_init: | |
1176 | phy_exit(dwc->usb2_generic_phy); | |
1177 | ||
1178 | return ret; | |
7415f17c FB |
1179 | } |
1180 | ||
1181 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c FB |
1182 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
1183 | }; | |
1184 | ||
1185 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
1186 | #else | |
1187 | #define DWC3_PM_OPS NULL | |
1188 | #endif | |
1189 | ||
5088b6f5 KVA |
1190 | #ifdef CONFIG_OF |
1191 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
1192 | { |
1193 | .compatible = "snps,dwc3" | |
1194 | }, | |
5088b6f5 KVA |
1195 | { |
1196 | .compatible = "synopsys,dwc3" | |
1197 | }, | |
1198 | { }, | |
1199 | }; | |
1200 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
1201 | #endif | |
1202 | ||
404905a6 HK |
1203 | #ifdef CONFIG_ACPI |
1204 | ||
1205 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1206 | ||
1207 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1208 | { ACPI_ID_INTEL_BSW, 0 }, | |
1209 | { }, | |
1210 | }; | |
1211 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1212 | #endif | |
1213 | ||
72246da4 FB |
1214 | static struct platform_driver dwc3_driver = { |
1215 | .probe = dwc3_probe, | |
7690417d | 1216 | .remove = dwc3_remove, |
72246da4 FB |
1217 | .driver = { |
1218 | .name = "dwc3", | |
5088b6f5 | 1219 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1220 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7415f17c | 1221 | .pm = DWC3_PM_OPS, |
72246da4 | 1222 | }, |
72246da4 FB |
1223 | }; |
1224 | ||
b1116dcc TK |
1225 | module_platform_driver(dwc3_driver); |
1226 | ||
7ae4fc4d | 1227 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1228 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1229 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1230 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |