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72246da4 FB |
1 | /** |
2 | * core.h - DesignWare USB3 DRD Core Header | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #ifndef __DRIVERS_USB_DWC3_CORE_H | |
20 | #define __DRIVERS_USB_DWC3_CORE_H | |
21 | ||
22 | #include <linux/device.h> | |
23 | #include <linux/spinlock.h> | |
d07e8819 | 24 | #include <linux/ioport.h> |
72246da4 FB |
25 | #include <linux/list.h> |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/mm.h> | |
28 | #include <linux/debugfs.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
a45c82b8 | 32 | #include <linux/usb/otg.h> |
72246da4 FB |
33 | |
34 | /* Global constants */ | |
3ef35faf | 35 | #define DWC3_EP0_BOUNCE_SIZE 512 |
72246da4 | 36 | #define DWC3_ENDPOINTS_NUM 32 |
51249dca | 37 | #define DWC3_XHCI_RESOURCES_NUM 2 |
72246da4 | 38 | |
5da93478 FB |
39 | #define DWC3_EVENT_SIZE 4 /* bytes */ |
40 | #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ | |
41 | #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) | |
72246da4 FB |
42 | #define DWC3_EVENT_TYPE_MASK 0xfe |
43 | ||
44 | #define DWC3_EVENT_TYPE_DEV 0 | |
45 | #define DWC3_EVENT_TYPE_CARKIT 3 | |
46 | #define DWC3_EVENT_TYPE_I2C 4 | |
47 | ||
48 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 | |
49 | #define DWC3_DEVICE_EVENT_RESET 1 | |
50 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 | |
51 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 | |
52 | #define DWC3_DEVICE_EVENT_WAKEUP 4 | |
2c61a8ef | 53 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
72246da4 FB |
54 | #define DWC3_DEVICE_EVENT_EOPF 6 |
55 | #define DWC3_DEVICE_EVENT_SOF 7 | |
56 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 | |
57 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 | |
58 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 | |
59 | ||
60 | #define DWC3_GEVNTCOUNT_MASK 0xfffc | |
61 | #define DWC3_GSNPSID_MASK 0xffff0000 | |
62 | #define DWC3_GSNPSREV_MASK 0xffff | |
63 | ||
51249dca IS |
64 | /* DWC3 registers memory space boundries */ |
65 | #define DWC3_XHCI_REGS_START 0x0 | |
66 | #define DWC3_XHCI_REGS_END 0x7fff | |
67 | #define DWC3_GLOBALS_REGS_START 0xc100 | |
68 | #define DWC3_GLOBALS_REGS_END 0xc6ff | |
69 | #define DWC3_DEVICE_REGS_START 0xc700 | |
70 | #define DWC3_DEVICE_REGS_END 0xcbff | |
71 | #define DWC3_OTG_REGS_START 0xcc00 | |
72 | #define DWC3_OTG_REGS_END 0xccff | |
73 | ||
72246da4 FB |
74 | /* Global Registers */ |
75 | #define DWC3_GSBUSCFG0 0xc100 | |
76 | #define DWC3_GSBUSCFG1 0xc104 | |
77 | #define DWC3_GTXTHRCFG 0xc108 | |
78 | #define DWC3_GRXTHRCFG 0xc10c | |
79 | #define DWC3_GCTL 0xc110 | |
80 | #define DWC3_GEVTEN 0xc114 | |
81 | #define DWC3_GSTS 0xc118 | |
82 | #define DWC3_GSNPSID 0xc120 | |
83 | #define DWC3_GGPIO 0xc124 | |
84 | #define DWC3_GUID 0xc128 | |
85 | #define DWC3_GUCTL 0xc12c | |
86 | #define DWC3_GBUSERRADDR0 0xc130 | |
87 | #define DWC3_GBUSERRADDR1 0xc134 | |
88 | #define DWC3_GPRTBIMAP0 0xc138 | |
89 | #define DWC3_GPRTBIMAP1 0xc13c | |
90 | #define DWC3_GHWPARAMS0 0xc140 | |
91 | #define DWC3_GHWPARAMS1 0xc144 | |
92 | #define DWC3_GHWPARAMS2 0xc148 | |
93 | #define DWC3_GHWPARAMS3 0xc14c | |
94 | #define DWC3_GHWPARAMS4 0xc150 | |
95 | #define DWC3_GHWPARAMS5 0xc154 | |
96 | #define DWC3_GHWPARAMS6 0xc158 | |
97 | #define DWC3_GHWPARAMS7 0xc15c | |
98 | #define DWC3_GDBGFIFOSPACE 0xc160 | |
99 | #define DWC3_GDBGLTSSM 0xc164 | |
100 | #define DWC3_GPRTBIMAP_HS0 0xc180 | |
101 | #define DWC3_GPRTBIMAP_HS1 0xc184 | |
102 | #define DWC3_GPRTBIMAP_FS0 0xc188 | |
103 | #define DWC3_GPRTBIMAP_FS1 0xc18c | |
104 | ||
105 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) | |
106 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) | |
107 | ||
108 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) | |
109 | ||
110 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) | |
111 | ||
112 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) | |
113 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) | |
114 | ||
115 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) | |
116 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) | |
117 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) | |
118 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) | |
119 | ||
120 | #define DWC3_GHWPARAMS8 0xc600 | |
121 | ||
122 | /* Device Registers */ | |
123 | #define DWC3_DCFG 0xc700 | |
124 | #define DWC3_DCTL 0xc704 | |
125 | #define DWC3_DEVTEN 0xc708 | |
126 | #define DWC3_DSTS 0xc70c | |
127 | #define DWC3_DGCMDPAR 0xc710 | |
128 | #define DWC3_DGCMD 0xc714 | |
129 | #define DWC3_DALEPENA 0xc720 | |
130 | #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) | |
131 | #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) | |
132 | #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) | |
133 | #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) | |
134 | ||
135 | /* OTG Registers */ | |
136 | #define DWC3_OCFG 0xcc00 | |
137 | #define DWC3_OCTL 0xcc04 | |
d4436c3a GC |
138 | #define DWC3_OEVT 0xcc08 |
139 | #define DWC3_OEVTEN 0xcc0C | |
140 | #define DWC3_OSTS 0xcc10 | |
72246da4 FB |
141 | |
142 | /* Bit fields */ | |
143 | ||
144 | /* Global Configuration Register */ | |
1d046793 | 145 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
f4aadbe4 | 146 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
1d046793 | 147 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
72246da4 FB |
148 | #define DWC3_GCTL_CLK_BUS (0) |
149 | #define DWC3_GCTL_CLK_PIPE (1) | |
150 | #define DWC3_GCTL_CLK_PIPEHALF (2) | |
151 | #define DWC3_GCTL_CLK_MASK (3) | |
152 | ||
0b9fe32d | 153 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
1d046793 | 154 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
72246da4 FB |
155 | #define DWC3_GCTL_PRTCAP_HOST 1 |
156 | #define DWC3_GCTL_PRTCAP_DEVICE 2 | |
157 | #define DWC3_GCTL_PRTCAP_OTG 3 | |
158 | ||
2c61a8ef | 159 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
183ca111 | 160 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
2c61a8ef PZ |
161 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
162 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) | |
163 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) | |
164 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) | |
165 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) | |
72246da4 FB |
166 | |
167 | /* Global USB2 PHY Configuration Register */ | |
2c61a8ef PZ |
168 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
169 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) | |
72246da4 FB |
170 | |
171 | /* Global USB3 PIPE Control Register */ | |
2c61a8ef PZ |
172 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
173 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) | |
72246da4 | 174 | |
457e84b6 | 175 | /* Global TX Fifo Size Register */ |
2c61a8ef PZ |
176 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
177 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) | |
457e84b6 | 178 | |
68d6a01b FB |
179 | /* Global Event Size Registers */ |
180 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) | |
181 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) | |
182 | ||
aabb7075 | 183 | /* Global HWPARAMS1 Register */ |
1d046793 | 184 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
aabb7075 FB |
185 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
186 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 | |
2c61a8ef PZ |
187 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
188 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) | |
189 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) | |
190 | ||
191 | /* Global HWPARAMS4 Register */ | |
192 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) | |
193 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 | |
aabb7075 | 194 | |
72246da4 FB |
195 | /* Device Configuration Register */ |
196 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) | |
197 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) | |
198 | ||
199 | #define DWC3_DCFG_SPEED_MASK (7 << 0) | |
200 | #define DWC3_DCFG_SUPERSPEED (4 << 0) | |
201 | #define DWC3_DCFG_HIGHSPEED (0 << 0) | |
202 | #define DWC3_DCFG_FULLSPEED2 (1 << 0) | |
203 | #define DWC3_DCFG_LOWSPEED (2 << 0) | |
204 | #define DWC3_DCFG_FULLSPEED1 (3 << 0) | |
205 | ||
2c61a8ef PZ |
206 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
207 | ||
72246da4 FB |
208 | /* Device Control Register */ |
209 | #define DWC3_DCTL_RUN_STOP (1 << 31) | |
210 | #define DWC3_DCTL_CSFTRST (1 << 30) | |
211 | #define DWC3_DCTL_LSFTRST (1 << 29) | |
212 | ||
213 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) | |
7e39b817 | 214 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
72246da4 FB |
215 | |
216 | #define DWC3_DCTL_APPL1RES (1 << 23) | |
217 | ||
2c61a8ef PZ |
218 | /* These apply for core versions 1.87a and earlier */ |
219 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) | |
220 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) | |
221 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) | |
222 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) | |
223 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) | |
224 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) | |
225 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) | |
226 | ||
227 | /* These apply for core versions 1.94a and later */ | |
228 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) | |
229 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) | |
230 | #define DWC3_DCTL_CRS (1 << 17) | |
231 | #define DWC3_DCTL_CSS (1 << 16) | |
8db7ed15 | 232 | |
72246da4 FB |
233 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
234 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) | |
235 | #define DWC3_DCTL_INITU1ENA (1 << 10) | |
236 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) | |
237 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) | |
238 | ||
239 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) | |
240 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) | |
241 | ||
242 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) | |
243 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) | |
244 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) | |
245 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) | |
246 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) | |
247 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) | |
248 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) | |
249 | ||
250 | /* Device Event Enable Register */ | |
251 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) | |
252 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) | |
253 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) | |
254 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) | |
255 | #define DWC3_DEVTEN_SOFEN (1 << 7) | |
256 | #define DWC3_DEVTEN_EOPFEN (1 << 6) | |
2c61a8ef | 257 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
72246da4 FB |
258 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
259 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) | |
260 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) | |
261 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) | |
262 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) | |
263 | ||
264 | /* Device Status Register */ | |
2c61a8ef PZ |
265 | #define DWC3_DSTS_DCNRD (1 << 29) |
266 | ||
267 | /* This applies for core versions 1.87a and earlier */ | |
72246da4 | 268 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
2c61a8ef PZ |
269 | |
270 | /* These apply for core versions 1.94a and later */ | |
271 | #define DWC3_DSTS_RSS (1 << 25) | |
272 | #define DWC3_DSTS_SSS (1 << 24) | |
273 | ||
72246da4 FB |
274 | #define DWC3_DSTS_COREIDLE (1 << 23) |
275 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) | |
276 | ||
277 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) | |
278 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) | |
279 | ||
280 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) | |
281 | ||
d05b8182 | 282 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
72246da4 FB |
283 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
284 | ||
285 | #define DWC3_DSTS_CONNECTSPD (7 << 0) | |
286 | ||
287 | #define DWC3_DSTS_SUPERSPEED (4 << 0) | |
288 | #define DWC3_DSTS_HIGHSPEED (0 << 0) | |
289 | #define DWC3_DSTS_FULLSPEED2 (1 << 0) | |
290 | #define DWC3_DSTS_LOWSPEED (2 << 0) | |
291 | #define DWC3_DSTS_FULLSPEED1 (3 << 0) | |
292 | ||
293 | /* Device Generic Command Register */ | |
294 | #define DWC3_DGCMD_SET_LMP 0x01 | |
295 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 | |
296 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 | |
2c61a8ef PZ |
297 | |
298 | /* These apply for core versions 1.94a and later */ | |
299 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 | |
300 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 | |
301 | ||
72246da4 FB |
302 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
303 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a | |
304 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c | |
305 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 | |
306 | ||
b09bb642 FB |
307 | #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) |
308 | #define DWC3_DGCMD_CMDACT (1 << 10) | |
2c61a8ef PZ |
309 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
310 | ||
311 | /* Device Generic Command Parameter Register */ | |
312 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) | |
313 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) | |
314 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) | |
315 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) | |
316 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) | |
317 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) | |
b09bb642 | 318 | |
72246da4 FB |
319 | /* Device Endpoint Command Register */ |
320 | #define DWC3_DEPCMD_PARAM_SHIFT 16 | |
1d046793 PZ |
321 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
322 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) | |
b09bb642 | 323 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) |
72246da4 FB |
324 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
325 | #define DWC3_DEPCMD_CMDACT (1 << 10) | |
326 | #define DWC3_DEPCMD_CMDIOC (1 << 8) | |
327 | ||
328 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) | |
329 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) | |
330 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) | |
331 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) | |
332 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) | |
333 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) | |
2c61a8ef | 334 | /* This applies for core versions 1.90a and earlier */ |
72246da4 | 335 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
2c61a8ef PZ |
336 | /* This applies for core versions 1.94a and later */ |
337 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) | |
72246da4 FB |
338 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
339 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) | |
340 | ||
341 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ | |
342 | #define DWC3_DALEPENA_EP(n) (1 << n) | |
343 | ||
344 | #define DWC3_DEPCMD_TYPE_CONTROL 0 | |
345 | #define DWC3_DEPCMD_TYPE_ISOC 1 | |
346 | #define DWC3_DEPCMD_TYPE_BULK 2 | |
347 | #define DWC3_DEPCMD_TYPE_INTR 3 | |
348 | ||
349 | /* Structures */ | |
350 | ||
f6bafc6a | 351 | struct dwc3_trb; |
72246da4 FB |
352 | |
353 | /** | |
354 | * struct dwc3_event_buffer - Software event buffer representation | |
72246da4 FB |
355 | * @buf: _THE_ buffer |
356 | * @length: size of this buffer | |
abed4118 | 357 | * @lpos: event offset |
60d04bbe | 358 | * @count: cache of last read event count register |
abed4118 | 359 | * @flags: flags related to this event buffer |
72246da4 FB |
360 | * @dma: dma_addr_t |
361 | * @dwc: pointer to DWC controller | |
362 | */ | |
363 | struct dwc3_event_buffer { | |
364 | void *buf; | |
365 | unsigned length; | |
366 | unsigned int lpos; | |
60d04bbe | 367 | unsigned int count; |
abed4118 FB |
368 | unsigned int flags; |
369 | ||
370 | #define DWC3_EVENT_PENDING BIT(0) | |
72246da4 FB |
371 | |
372 | dma_addr_t dma; | |
373 | ||
374 | struct dwc3 *dwc; | |
375 | }; | |
376 | ||
377 | #define DWC3_EP_FLAG_STALLED (1 << 0) | |
378 | #define DWC3_EP_FLAG_WEDGED (1 << 1) | |
379 | ||
380 | #define DWC3_EP_DIRECTION_TX true | |
381 | #define DWC3_EP_DIRECTION_RX false | |
382 | ||
383 | #define DWC3_TRB_NUM 32 | |
384 | #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) | |
385 | ||
386 | /** | |
387 | * struct dwc3_ep - device side endpoint representation | |
388 | * @endpoint: usb endpoint | |
389 | * @request_list: list of requests for this endpoint | |
390 | * @req_queued: list of requests on this ep which have TRBs setup | |
391 | * @trb_pool: array of transaction buffers | |
392 | * @trb_pool_dma: dma address of @trb_pool | |
393 | * @free_slot: next slot which is going to be used | |
394 | * @busy_slot: first slot which is owned by HW | |
395 | * @desc: usb_endpoint_descriptor pointer | |
396 | * @dwc: pointer to DWC controller | |
4cfcf876 | 397 | * @saved_state: ep state saved during hibernation |
72246da4 FB |
398 | * @flags: endpoint flags (wedged, stalled, ...) |
399 | * @current_trb: index of current used trb | |
400 | * @number: endpoint number (1 - 15) | |
401 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK | |
b4996a86 | 402 | * @resource_index: Resource transfer index |
c75f52fb | 403 | * @interval: the interval on which the ISOC transfer is started |
72246da4 FB |
404 | * @name: a human readable name e.g. ep1out-bulk |
405 | * @direction: true for TX, false for RX | |
879631aa | 406 | * @stream_capable: true when streams are enabled |
72246da4 FB |
407 | */ |
408 | struct dwc3_ep { | |
409 | struct usb_ep endpoint; | |
410 | struct list_head request_list; | |
411 | struct list_head req_queued; | |
412 | ||
f6bafc6a | 413 | struct dwc3_trb *trb_pool; |
72246da4 FB |
414 | dma_addr_t trb_pool_dma; |
415 | u32 free_slot; | |
416 | u32 busy_slot; | |
c90bfaec | 417 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
72246da4 FB |
418 | struct dwc3 *dwc; |
419 | ||
4cfcf876 | 420 | u32 saved_state; |
72246da4 FB |
421 | unsigned flags; |
422 | #define DWC3_EP_ENABLED (1 << 0) | |
423 | #define DWC3_EP_STALL (1 << 1) | |
424 | #define DWC3_EP_WEDGE (1 << 2) | |
425 | #define DWC3_EP_BUSY (1 << 4) | |
426 | #define DWC3_EP_PENDING_REQUEST (1 << 5) | |
d6d6ec7b | 427 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
72246da4 | 428 | |
984f66a6 FB |
429 | /* This last one is specific to EP0 */ |
430 | #define DWC3_EP0_DIR_IN (1 << 31) | |
431 | ||
72246da4 FB |
432 | unsigned current_trb; |
433 | ||
434 | u8 number; | |
435 | u8 type; | |
b4996a86 | 436 | u8 resource_index; |
72246da4 FB |
437 | u32 interval; |
438 | ||
439 | char name[20]; | |
440 | ||
441 | unsigned direction:1; | |
879631aa | 442 | unsigned stream_capable:1; |
72246da4 FB |
443 | }; |
444 | ||
445 | enum dwc3_phy { | |
446 | DWC3_PHY_UNKNOWN = 0, | |
447 | DWC3_PHY_USB3, | |
448 | DWC3_PHY_USB2, | |
449 | }; | |
450 | ||
b53c772d FB |
451 | enum dwc3_ep0_next { |
452 | DWC3_EP0_UNKNOWN = 0, | |
453 | DWC3_EP0_COMPLETE, | |
b53c772d FB |
454 | DWC3_EP0_NRDY_DATA, |
455 | DWC3_EP0_NRDY_STATUS, | |
456 | }; | |
457 | ||
72246da4 FB |
458 | enum dwc3_ep0_state { |
459 | EP0_UNCONNECTED = 0, | |
c7fcdeb2 FB |
460 | EP0_SETUP_PHASE, |
461 | EP0_DATA_PHASE, | |
462 | EP0_STATUS_PHASE, | |
72246da4 FB |
463 | }; |
464 | ||
465 | enum dwc3_link_state { | |
466 | /* In SuperSpeed */ | |
467 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ | |
468 | DWC3_LINK_STATE_U1 = 0x01, | |
469 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ | |
470 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ | |
471 | DWC3_LINK_STATE_SS_DIS = 0x04, | |
472 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ | |
473 | DWC3_LINK_STATE_SS_INACT = 0x06, | |
474 | DWC3_LINK_STATE_POLL = 0x07, | |
475 | DWC3_LINK_STATE_RECOV = 0x08, | |
476 | DWC3_LINK_STATE_HRESET = 0x09, | |
477 | DWC3_LINK_STATE_CMPLY = 0x0a, | |
478 | DWC3_LINK_STATE_LPBK = 0x0b, | |
2c61a8ef PZ |
479 | DWC3_LINK_STATE_RESET = 0x0e, |
480 | DWC3_LINK_STATE_RESUME = 0x0f, | |
72246da4 FB |
481 | DWC3_LINK_STATE_MASK = 0x0f, |
482 | }; | |
483 | ||
f6bafc6a FB |
484 | /* TRB Length, PCM and Status */ |
485 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) | |
486 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) | |
487 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) | |
389f2828 | 488 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
f6bafc6a FB |
489 | |
490 | #define DWC3_TRBSTS_OK 0 | |
491 | #define DWC3_TRBSTS_MISSED_ISOC 1 | |
492 | #define DWC3_TRBSTS_SETUP_PENDING 2 | |
2c61a8ef | 493 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
f6bafc6a FB |
494 | |
495 | /* TRB Control */ | |
496 | #define DWC3_TRB_CTRL_HWO (1 << 0) | |
497 | #define DWC3_TRB_CTRL_LST (1 << 1) | |
498 | #define DWC3_TRB_CTRL_CHN (1 << 2) | |
499 | #define DWC3_TRB_CTRL_CSP (1 << 3) | |
500 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) | |
501 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) | |
502 | #define DWC3_TRB_CTRL_IOC (1 << 11) | |
503 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) | |
504 | ||
505 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) | |
506 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) | |
507 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) | |
508 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) | |
509 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) | |
510 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) | |
511 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) | |
512 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) | |
72246da4 FB |
513 | |
514 | /** | |
f6bafc6a | 515 | * struct dwc3_trb - transfer request block (hw format) |
72246da4 FB |
516 | * @bpl: DW0-3 |
517 | * @bph: DW4-7 | |
518 | * @size: DW8-B | |
519 | * @trl: DWC-F | |
520 | */ | |
f6bafc6a FB |
521 | struct dwc3_trb { |
522 | u32 bpl; | |
523 | u32 bph; | |
524 | u32 size; | |
525 | u32 ctrl; | |
72246da4 FB |
526 | } __packed; |
527 | ||
a3299499 FB |
528 | /** |
529 | * dwc3_hwparams - copy of HWPARAMS registers | |
530 | * @hwparams0 - GHWPARAMS0 | |
531 | * @hwparams1 - GHWPARAMS1 | |
532 | * @hwparams2 - GHWPARAMS2 | |
533 | * @hwparams3 - GHWPARAMS3 | |
534 | * @hwparams4 - GHWPARAMS4 | |
535 | * @hwparams5 - GHWPARAMS5 | |
536 | * @hwparams6 - GHWPARAMS6 | |
537 | * @hwparams7 - GHWPARAMS7 | |
538 | * @hwparams8 - GHWPARAMS8 | |
539 | */ | |
540 | struct dwc3_hwparams { | |
541 | u32 hwparams0; | |
542 | u32 hwparams1; | |
543 | u32 hwparams2; | |
544 | u32 hwparams3; | |
545 | u32 hwparams4; | |
546 | u32 hwparams5; | |
547 | u32 hwparams6; | |
548 | u32 hwparams7; | |
549 | u32 hwparams8; | |
550 | }; | |
551 | ||
0949e99b FB |
552 | /* HWPARAMS0 */ |
553 | #define DWC3_MODE(n) ((n) & 0x7) | |
554 | ||
457e84b6 FB |
555 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
556 | ||
0949e99b | 557 | /* HWPARAMS1 */ |
457e84b6 FB |
558 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
559 | ||
789451f6 FB |
560 | /* HWPARAMS3 */ |
561 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) | |
562 | #define DWC3_NUM_EPS_MASK (0x3f << 12) | |
563 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ | |
564 | (DWC3_NUM_EPS_MASK)) >> 12) | |
565 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ | |
566 | (DWC3_NUM_IN_EPS_MASK)) >> 18) | |
567 | ||
457e84b6 FB |
568 | /* HWPARAMS7 */ |
569 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) | |
9f622b2a | 570 | |
e0ce0b0a SAS |
571 | struct dwc3_request { |
572 | struct usb_request request; | |
573 | struct list_head list; | |
574 | struct dwc3_ep *dep; | |
e5ba5ec8 | 575 | u32 start_slot; |
e0ce0b0a SAS |
576 | |
577 | u8 epnum; | |
f6bafc6a | 578 | struct dwc3_trb *trb; |
e0ce0b0a SAS |
579 | dma_addr_t trb_dma; |
580 | ||
581 | unsigned direction:1; | |
582 | unsigned mapped:1; | |
583 | unsigned queued:1; | |
584 | }; | |
585 | ||
2c61a8ef PZ |
586 | /* |
587 | * struct dwc3_scratchpad_array - hibernation scratchpad array | |
588 | * (format defined by hw) | |
589 | */ | |
590 | struct dwc3_scratchpad_array { | |
591 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; | |
592 | }; | |
593 | ||
72246da4 FB |
594 | /** |
595 | * struct dwc3 - representation of our controller | |
91db07dc FB |
596 | * @ctrl_req: usb control request which is used for ep0 |
597 | * @ep0_trb: trb which is used for the ctrl_req | |
5812b1c2 | 598 | * @ep0_bounce: bounce buffer for ep0 |
91db07dc FB |
599 | * @setup_buf: used while precessing STD USB requests |
600 | * @ctrl_req_addr: dma address of ctrl_req | |
601 | * @ep0_trb: dma address of ep0_trb | |
602 | * @ep0_usb_req: dummy req used while handling STD USB requests | |
5812b1c2 | 603 | * @ep0_bounce_addr: dma address of ep0_bounce |
72246da4 FB |
604 | * @lock: for synchronizing |
605 | * @dev: pointer to our struct device | |
d07e8819 | 606 | * @xhci: pointer to our xHCI child |
72246da4 FB |
607 | * @event_buffer_list: a list of event buffers |
608 | * @gadget: device side representation of the peripheral controller | |
609 | * @gadget_driver: pointer to the gadget driver | |
610 | * @regs: base address for our registers | |
611 | * @regs_size: address space size | |
9f622b2a | 612 | * @num_event_buffers: calculated number of event buffers |
fae2b904 | 613 | * @u1u2: only used on revisions <1.83a for workaround |
6c167fc9 | 614 | * @maximum_speed: maximum speed requested (mainly for testing purposes) |
72246da4 | 615 | * @revision: revision register contents |
a45c82b8 | 616 | * @dr_mode: requested mode of operation |
51e1e7bc FB |
617 | * @usb2_phy: pointer to USB2 PHY |
618 | * @usb3_phy: pointer to USB3 PHY | |
7415f17c FB |
619 | * @dcfg: saved contents of DCFG register |
620 | * @gctl: saved contents of GCTL register | |
c12a0d86 | 621 | * @isoch_delay: wValue from Set Isochronous Delay request; |
865e09e7 FB |
622 | * @u2sel: parameter from Set SEL request. |
623 | * @u2pel: parameter from Set SEL request. | |
624 | * @u1sel: parameter from Set SEL request. | |
625 | * @u1pel: parameter from Set SEL request. | |
789451f6 FB |
626 | * @num_out_eps: number of out endpoints |
627 | * @num_in_eps: number of in endpoints | |
b53c772d | 628 | * @ep0_next_event: hold the next expected event |
72246da4 FB |
629 | * @ep0state: state of endpoint zero |
630 | * @link_state: link state | |
631 | * @speed: device speed (super, high, full, low) | |
632 | * @mem: points to start of memory which is used for this struct. | |
a3299499 | 633 | * @hwparams: copy of hwparams registers |
72246da4 | 634 | * @root: debugfs root folder pointer |
f2b685d5 FB |
635 | * @regset: debugfs pointer to regdump file |
636 | * @test_mode: true when we're entering a USB test mode | |
637 | * @test_mode_nr: test feature selector | |
638 | * @delayed_status: true when gadget driver asks for delayed status | |
639 | * @ep0_bounced: true when we used bounce buffer | |
640 | * @ep0_expect_in: true when we expect a DATA IN transfer | |
81bc5599 | 641 | * @has_hibernation: true when dwc3 was configured with Hibernation |
f2b685d5 FB |
642 | * @is_selfpowered: true when we are selfpowered |
643 | * @needs_fifo_resize: not all users might want fifo resizing, flag it | |
644 | * @pullups_connected: true when Run/Stop bit is set | |
645 | * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. | |
646 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround | |
647 | * @start_config_issued: true when StartConfig command has been issued | |
648 | * @three_stage_setup: set if we perform a three phase setup | |
72246da4 FB |
649 | */ |
650 | struct dwc3 { | |
651 | struct usb_ctrlrequest *ctrl_req; | |
f6bafc6a | 652 | struct dwc3_trb *ep0_trb; |
5812b1c2 | 653 | void *ep0_bounce; |
72246da4 FB |
654 | u8 *setup_buf; |
655 | dma_addr_t ctrl_req_addr; | |
656 | dma_addr_t ep0_trb_addr; | |
5812b1c2 | 657 | dma_addr_t ep0_bounce_addr; |
e0ce0b0a | 658 | struct dwc3_request ep0_usb_req; |
789451f6 | 659 | |
72246da4 FB |
660 | /* device lock */ |
661 | spinlock_t lock; | |
789451f6 | 662 | |
72246da4 FB |
663 | struct device *dev; |
664 | ||
d07e8819 | 665 | struct platform_device *xhci; |
51249dca | 666 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
d07e8819 | 667 | |
457d3f21 | 668 | struct dwc3_event_buffer **ev_buffs; |
72246da4 FB |
669 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
670 | ||
671 | struct usb_gadget gadget; | |
672 | struct usb_gadget_driver *gadget_driver; | |
673 | ||
51e1e7bc FB |
674 | struct usb_phy *usb2_phy; |
675 | struct usb_phy *usb3_phy; | |
676 | ||
72246da4 FB |
677 | void __iomem *regs; |
678 | size_t regs_size; | |
679 | ||
a45c82b8 RK |
680 | enum usb_dr_mode dr_mode; |
681 | ||
7415f17c FB |
682 | /* used for suspend/resume */ |
683 | u32 dcfg; | |
684 | u32 gctl; | |
685 | ||
9f622b2a | 686 | u32 num_event_buffers; |
fae2b904 | 687 | u32 u1u2; |
6c167fc9 | 688 | u32 maximum_speed; |
72246da4 FB |
689 | u32 revision; |
690 | ||
691 | #define DWC3_REVISION_173A 0x5533173a | |
692 | #define DWC3_REVISION_175A 0x5533175a | |
693 | #define DWC3_REVISION_180A 0x5533180a | |
694 | #define DWC3_REVISION_183A 0x5533183a | |
695 | #define DWC3_REVISION_185A 0x5533185a | |
2c61a8ef | 696 | #define DWC3_REVISION_187A 0x5533187a |
72246da4 FB |
697 | #define DWC3_REVISION_188A 0x5533188a |
698 | #define DWC3_REVISION_190A 0x5533190a | |
2c61a8ef | 699 | #define DWC3_REVISION_194A 0x5533194a |
1522d703 FB |
700 | #define DWC3_REVISION_200A 0x5533200a |
701 | #define DWC3_REVISION_202A 0x5533202a | |
702 | #define DWC3_REVISION_210A 0x5533210a | |
703 | #define DWC3_REVISION_220A 0x5533220a | |
7ac6a593 FB |
704 | #define DWC3_REVISION_230A 0x5533230a |
705 | #define DWC3_REVISION_240A 0x5533240a | |
706 | #define DWC3_REVISION_250A 0x5533250a | |
72246da4 | 707 | |
b53c772d | 708 | enum dwc3_ep0_next ep0_next_event; |
72246da4 FB |
709 | enum dwc3_ep0_state ep0state; |
710 | enum dwc3_link_state link_state; | |
72246da4 | 711 | |
c12a0d86 | 712 | u16 isoch_delay; |
865e09e7 FB |
713 | u16 u2sel; |
714 | u16 u2pel; | |
715 | u8 u1sel; | |
716 | u8 u1pel; | |
717 | ||
72246da4 | 718 | u8 speed; |
865e09e7 | 719 | |
789451f6 FB |
720 | u8 num_out_eps; |
721 | u8 num_in_eps; | |
722 | ||
72246da4 FB |
723 | void *mem; |
724 | ||
a3299499 | 725 | struct dwc3_hwparams hwparams; |
72246da4 | 726 | struct dentry *root; |
d7668024 | 727 | struct debugfs_regset32 *regset; |
3b637367 GC |
728 | |
729 | u8 test_mode; | |
730 | u8 test_mode_nr; | |
f2b685d5 FB |
731 | |
732 | unsigned delayed_status:1; | |
733 | unsigned ep0_bounced:1; | |
734 | unsigned ep0_expect_in:1; | |
81bc5599 | 735 | unsigned has_hibernation:1; |
f2b685d5 FB |
736 | unsigned is_selfpowered:1; |
737 | unsigned needs_fifo_resize:1; | |
738 | unsigned pullups_connected:1; | |
739 | unsigned resize_fifos:1; | |
740 | unsigned setup_packet_pending:1; | |
741 | unsigned start_config_issued:1; | |
742 | unsigned three_stage_setup:1; | |
72246da4 FB |
743 | }; |
744 | ||
745 | /* -------------------------------------------------------------------------- */ | |
746 | ||
72246da4 FB |
747 | /* -------------------------------------------------------------------------- */ |
748 | ||
749 | struct dwc3_event_type { | |
750 | u32 is_devspec:1; | |
1974d494 HR |
751 | u32 type:7; |
752 | u32 reserved8_31:24; | |
72246da4 FB |
753 | } __packed; |
754 | ||
755 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 | |
756 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 | |
757 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 | |
758 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 | |
759 | #define DWC3_DEPEVT_STREAMEVT 0x06 | |
760 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 | |
761 | ||
762 | /** | |
763 | * struct dwc3_event_depvt - Device Endpoint Events | |
764 | * @one_bit: indicates this is an endpoint event (not used) | |
765 | * @endpoint_number: number of the endpoint | |
766 | * @endpoint_event: The event we have: | |
767 | * 0x00 - Reserved | |
768 | * 0x01 - XferComplete | |
769 | * 0x02 - XferInProgress | |
770 | * 0x03 - XferNotReady | |
771 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) | |
772 | * 0x05 - Reserved | |
773 | * 0x06 - StreamEvt | |
774 | * 0x07 - EPCmdCmplt | |
775 | * @reserved11_10: Reserved, don't use. | |
776 | * @status: Indicates the status of the event. Refer to databook for | |
777 | * more information. | |
778 | * @parameters: Parameters of the current event. Refer to databook for | |
779 | * more information. | |
780 | */ | |
781 | struct dwc3_event_depevt { | |
782 | u32 one_bit:1; | |
783 | u32 endpoint_number:5; | |
784 | u32 endpoint_event:4; | |
785 | u32 reserved11_10:2; | |
786 | u32 status:4; | |
40aa41fb FB |
787 | |
788 | /* Within XferNotReady */ | |
789 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) | |
790 | ||
791 | /* Within XferComplete */ | |
1d046793 PZ |
792 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
793 | #define DEPEVT_STATUS_SHORT (1 << 1) | |
794 | #define DEPEVT_STATUS_IOC (1 << 2) | |
72246da4 | 795 | #define DEPEVT_STATUS_LST (1 << 3) |
dc137f01 | 796 | |
879631aa FB |
797 | /* Stream event only */ |
798 | #define DEPEVT_STREAMEVT_FOUND 1 | |
799 | #define DEPEVT_STREAMEVT_NOTFOUND 2 | |
800 | ||
dc137f01 | 801 | /* Control-only Status */ |
dc137f01 FB |
802 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
803 | #define DEPEVT_STATUS_CONTROL_STATUS 2 | |
804 | ||
72246da4 FB |
805 | u32 parameters:16; |
806 | } __packed; | |
807 | ||
808 | /** | |
809 | * struct dwc3_event_devt - Device Events | |
810 | * @one_bit: indicates this is a non-endpoint event (not used) | |
811 | * @device_event: indicates it's a device event. Should read as 0x00 | |
812 | * @type: indicates the type of device event. | |
813 | * 0 - DisconnEvt | |
814 | * 1 - USBRst | |
815 | * 2 - ConnectDone | |
816 | * 3 - ULStChng | |
817 | * 4 - WkUpEvt | |
818 | * 5 - Reserved | |
819 | * 6 - EOPF | |
820 | * 7 - SOF | |
821 | * 8 - Reserved | |
822 | * 9 - ErrticErr | |
823 | * 10 - CmdCmplt | |
824 | * 11 - EvntOverflow | |
825 | * 12 - VndrDevTstRcved | |
826 | * @reserved15_12: Reserved, not used | |
827 | * @event_info: Information about this event | |
06f9b6e5 | 828 | * @reserved31_25: Reserved, not used |
72246da4 FB |
829 | */ |
830 | struct dwc3_event_devt { | |
831 | u32 one_bit:1; | |
832 | u32 device_event:7; | |
833 | u32 type:4; | |
834 | u32 reserved15_12:4; | |
06f9b6e5 HR |
835 | u32 event_info:9; |
836 | u32 reserved31_25:7; | |
72246da4 FB |
837 | } __packed; |
838 | ||
839 | /** | |
840 | * struct dwc3_event_gevt - Other Core Events | |
841 | * @one_bit: indicates this is a non-endpoint event (not used) | |
842 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. | |
843 | * @phy_port_number: self-explanatory | |
844 | * @reserved31_12: Reserved, not used. | |
845 | */ | |
846 | struct dwc3_event_gevt { | |
847 | u32 one_bit:1; | |
848 | u32 device_event:7; | |
849 | u32 phy_port_number:4; | |
850 | u32 reserved31_12:20; | |
851 | } __packed; | |
852 | ||
853 | /** | |
854 | * union dwc3_event - representation of Event Buffer contents | |
855 | * @raw: raw 32-bit event | |
856 | * @type: the type of the event | |
857 | * @depevt: Device Endpoint Event | |
858 | * @devt: Device Event | |
859 | * @gevt: Global Event | |
860 | */ | |
861 | union dwc3_event { | |
862 | u32 raw; | |
863 | struct dwc3_event_type type; | |
864 | struct dwc3_event_depevt depevt; | |
865 | struct dwc3_event_devt devt; | |
866 | struct dwc3_event_gevt gevt; | |
867 | }; | |
868 | ||
869 | /* | |
870 | * DWC3 Features to be used as Driver Data | |
871 | */ | |
872 | ||
873 | #define DWC3_HAS_PERIPHERAL BIT(0) | |
874 | #define DWC3_HAS_XHCI BIT(1) | |
875 | #define DWC3_HAS_OTG BIT(3) | |
876 | ||
d07e8819 | 877 | /* prototypes */ |
3140e8cb | 878 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
457e84b6 | 879 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); |
3140e8cb | 880 | |
388e5c51 | 881 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
d07e8819 FB |
882 | int dwc3_host_init(struct dwc3 *dwc); |
883 | void dwc3_host_exit(struct dwc3 *dwc); | |
388e5c51 VG |
884 | #else |
885 | static inline int dwc3_host_init(struct dwc3 *dwc) | |
886 | { return 0; } | |
887 | static inline void dwc3_host_exit(struct dwc3 *dwc) | |
888 | { } | |
889 | #endif | |
890 | ||
891 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) | |
f80b45e7 FB |
892 | int dwc3_gadget_init(struct dwc3 *dwc); |
893 | void dwc3_gadget_exit(struct dwc3 *dwc); | |
388e5c51 VG |
894 | #else |
895 | static inline int dwc3_gadget_init(struct dwc3 *dwc) | |
896 | { return 0; } | |
897 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) | |
898 | { } | |
899 | #endif | |
f80b45e7 | 900 | |
7415f17c FB |
901 | /* power management interface */ |
902 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) | |
903 | int dwc3_gadget_prepare(struct dwc3 *dwc); | |
904 | void dwc3_gadget_complete(struct dwc3 *dwc); | |
905 | int dwc3_gadget_suspend(struct dwc3 *dwc); | |
906 | int dwc3_gadget_resume(struct dwc3 *dwc); | |
907 | #else | |
908 | static inline int dwc3_gadget_prepare(struct dwc3 *dwc) | |
909 | { | |
910 | return 0; | |
911 | } | |
912 | ||
913 | static inline void dwc3_gadget_complete(struct dwc3 *dwc) | |
914 | { | |
915 | } | |
916 | ||
917 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) | |
918 | { | |
919 | return 0; | |
920 | } | |
921 | ||
922 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) | |
923 | { | |
924 | return 0; | |
925 | } | |
926 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ | |
927 | ||
72246da4 | 928 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |