[mirror_ubuntu-jammy-kernel.git] / drivers / usb / dwc3 / dwc3-meson-g12a.c

// SPDX-License-Identifier: GPL-2.0
/*
 * USB Glue for Amlogic G12A SoCs
 *
 * Copyright (c) 2019 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

/*
 * The USB is organized with a glue around the DWC3 Controller IP as :
 * - Control registers for each USB2 Ports
 * - Control registers for the USB PHY layer
 * - SuperSpeed PHY can be enabled only if port is used
 * - Dynamic OTG switching with ID change interrupt
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
#include <linux/usb/otg.h>
#include <linux/usb/role.h>
#include <linux/regulator/consumer.h>

/* USB2 Ports Control Registers */

#define U2P_REG_SIZE						0x20

#define U2P_R0							0x0
	#define U2P_R0_HOST_DEVICE				BIT(0)
	#define U2P_R0_POWER_OK					BIT(1)
	#define U2P_R0_HAST_MODE				BIT(2)
	#define U2P_R0_POWER_ON_RESET				BIT(3)
	#define U2P_R0_ID_PULLUP				BIT(4)
	#define U2P_R0_DRV_VBUS					BIT(5)

#define U2P_R1							0x4
	#define U2P_R1_PHY_READY				BIT(0)
	#define U2P_R1_ID_DIG					BIT(1)
	#define U2P_R1_OTG_SESSION_VALID			BIT(2)
	#define U2P_R1_VBUS_VALID				BIT(3)

/* USB Glue Control Registers */

#define USB_R0							0x80
	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK			BIT(17)
	#define USB_R0_P30_LANE0_EXT_PCLK_REQ			BIT(18)
	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
	#define USB_R0_U2D_ACT					BIT(31)

#define USB_R1							0x84
	#define USB_R1_U3H_BIGENDIAN_GS				BIT(0)
	#define USB_R1_U3H_PME_ENABLE				BIT(1)
	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(4, 2)
	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(9, 7)
	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(13, 12)
	#define USB_R1_U3H_HOST_U3_PORT_DISABLE			BIT(16)
	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	BIT(17)
	#define USB_R1_U3H_HOST_MSI_ENABLE			BIT(18)
	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)

#define USB_R2							0x88
	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)

#define USB_R3							0x8c
	#define USB_R3_P30_SSC_ENABLE				BIT(0)
	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
	#define USB_R3_P30_REF_SSP_EN				BIT(13)

#define USB_R4							0x90
	#define USB_R4_P21_PORT_RESET_0				BIT(0)
	#define USB_R4_P21_SLEEP_M0				BIT(1)
	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
	#define USB_R4_P21_ONLY					BIT(4)

#define USB_R5							0x94
	#define USB_R5_ID_DIG_SYNC				BIT(0)
	#define USB_R5_ID_DIG_REG				BIT(1)
	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
	#define USB_R5_ID_DIG_EN_0				BIT(4)
	#define USB_R5_ID_DIG_EN_1				BIT(5)
	#define USB_R5_ID_DIG_CURR				BIT(6)
	#define USB_R5_ID_DIG_IRQ				BIT(7)
	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)

#define PHY_COUNT						3
#define USB2_OTG_PHY						1

static struct clk_bulk_data meson_g12a_clocks[] = {
	{ .id = NULL },
};

static struct clk_bulk_data meson_a1_clocks[] = {
	{ .id = "usb_ctrl" },
	{ .id = "usb_bus" },
	{ .id = "xtal_usb_ctrl" },
};

static const char *meson_g12a_phy_names[] = {
	"usb2-phy0", "usb2-phy1", "usb3-phy0",
};

/*
 * Amlogic A1 has a single physical PHY, in slot 1, but still has the
 * two U2 PHY controls register blocks like G12A.
 * Handling the first PHY on slot 1 would need a large amount of code
 * changes, and the current management is generic enough to handle it
 * correctly when only the "usb2-phy1" phy is specified on-par with the
 * DT bindings.
 */
static const char *meson_a1_phy_names[] = {
	"usb2-phy0", "usb2-phy1"
};

struct dwc3_meson_g12a_drvdata {
	bool otg_switch_supported;
	struct clk_bulk_data *clks;
	int num_clks;
	const char **phy_names;
	int num_phys;
};

static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
	.otg_switch_supported = true,
	.clks = meson_g12a_clocks,
	.num_clks = ARRAY_SIZE(meson_g12a_clocks),
	.phy_names = meson_g12a_phy_names,
	.num_phys = ARRAY_SIZE(meson_g12a_phy_names),
};

static struct dwc3_meson_g12a_drvdata a1_drvdata = {
	.otg_switch_supported = false,
	.clks = meson_a1_clocks,
	.num_clks = ARRAY_SIZE(meson_a1_clocks),
	.phy_names = meson_a1_phy_names,
	.num_phys = ARRAY_SIZE(meson_a1_phy_names),
};

struct dwc3_meson_g12a {
	struct device		*dev;
	struct regmap		*regmap;
	struct reset_control	*reset;
	struct phy		*phys[PHY_COUNT];
	enum usb_dr_mode	otg_mode;
	enum phy_mode		otg_phy_mode;
	unsigned int		usb2_ports;
	unsigned int		usb3_ports;
	struct regulator	*vbus;
	struct usb_role_switch_desc switch_desc;
	struct usb_role_switch	*role_switch;
	const struct dwc3_meson_g12a_drvdata *drvdata;
};

static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
					  int i, enum phy_mode mode)
{
	if (mode == PHY_MODE_USB_HOST)
		regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
				U2P_R0_HOST_DEVICE,
				U2P_R0_HOST_DEVICE);
	else
		regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
				U2P_R0_HOST_DEVICE, 0);
}

static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
{
	int i;

	if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
		priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
	else
		priv->otg_phy_mode = PHY_MODE_USB_HOST;

	for (i = 0; i < priv->drvdata->num_phys; ++i) {
		if (!priv->phys[i])
			continue;

		if (!strstr(priv->drvdata->phy_names[i], "usb2"))
			continue;

		regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
				   U2P_R0_POWER_ON_RESET,
				   U2P_R0_POWER_ON_RESET);

		if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) {
			regmap_update_bits(priv->regmap,
				U2P_R0 + (U2P_REG_SIZE * i),
				U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
				U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);

			dwc3_meson_g12a_usb2_set_mode(priv, i,
						      priv->otg_phy_mode);
		} else
			dwc3_meson_g12a_usb2_set_mode(priv, i,
						      PHY_MODE_USB_HOST);

		regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
				   U2P_R0_POWER_ON_RESET, 0);
	}

	return 0;
}

static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
{
	regmap_update_bits(priv->regmap, USB_R3,
			USB_R3_P30_SSC_RANGE_MASK |
			USB_R3_P30_REF_SSP_EN,
			USB_R3_P30_SSC_ENABLE |
			FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
			USB_R3_P30_REF_SSP_EN);
	udelay(2);

	regmap_update_bits(priv->regmap, USB_R2,
			USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
			FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));

	regmap_update_bits(priv->regmap, USB_R2,
			USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
			FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));

	udelay(2);

	regmap_update_bits(priv->regmap, USB_R1,
			USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
			USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);

	regmap_update_bits(priv->regmap, USB_R1,
			USB_R1_P30_PCS_TX_SWING_FULL_MASK,
			FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
}

static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
{
	if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) {
		regmap_update_bits(priv->regmap, USB_R0,
				USB_R0_U2D_ACT, USB_R0_U2D_ACT);
		regmap_update_bits(priv->regmap, USB_R0,
				USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
		regmap_update_bits(priv->regmap, USB_R4,
				USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
	} else {
		regmap_update_bits(priv->regmap, USB_R0,
				USB_R0_U2D_ACT, 0);
		regmap_update_bits(priv->regmap, USB_R4,
				USB_R4_P21_SLEEP_M0, 0);
	}
}

static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
{
	int ret;

	ret = dwc3_meson_g12a_usb2_init(priv);
	if (ret)
		return ret;

	regmap_update_bits(priv->regmap, USB_R1,
			USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
			FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));

	regmap_update_bits(priv->regmap, USB_R5,
			USB_R5_ID_DIG_EN_0,
			USB_R5_ID_DIG_EN_0);
	regmap_update_bits(priv->regmap, USB_R5,
			USB_R5_ID_DIG_EN_1,
			USB_R5_ID_DIG_EN_1);
	regmap_update_bits(priv->regmap, USB_R5,
			USB_R5_ID_DIG_TH_MASK,
			FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));

	/* If we have an actual SuperSpeed port, initialize it */
	if (priv->usb3_ports)
		dwc3_meson_g12a_usb3_init(priv);

	dwc3_meson_g12a_usb_otg_apply_mode(priv);

	return 0;
}

static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = {
	.reg_bits = 8,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = USB_R5,
};

static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
{
	const char *phy_name;
	int i;

	for (i = 0 ; i < priv->drvdata->num_phys ; ++i) {
		phy_name = priv->drvdata->phy_names[i];
		priv->phys[i] = devm_phy_optional_get(priv->dev, phy_name);
		if (!priv->phys[i])
			continue;

		if (IS_ERR(priv->phys[i]))
			return PTR_ERR(priv->phys[i]);

		if (strstr(phy_name, "usb3"))
			priv->usb3_ports++;
		else
			priv->usb2_ports++;
	}

	dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports);
	dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports);

	return 0;
}

static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv)
{
	u32 reg;

	regmap_read(priv->regmap, USB_R5, &reg);

	if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG))
		return PHY_MODE_USB_DEVICE;

	return PHY_MODE_USB_HOST;
}

static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
					enum phy_mode mode)
{
	int ret;

	if (!priv->drvdata->otg_switch_supported || !priv->phys[USB2_OTG_PHY])
		return -EINVAL;

	if (mode == PHY_MODE_USB_HOST)
		dev_info(priv->dev, "switching to Host Mode\n");
	else
		dev_info(priv->dev, "switching to Device Mode\n");

	if (priv->vbus) {
		if (mode == PHY_MODE_USB_DEVICE)
			ret = regulator_disable(priv->vbus);
		else
			ret = regulator_enable(priv->vbus);
		if (ret)
			return ret;
	}

	priv->otg_phy_mode = mode;

	dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);

	dwc3_meson_g12a_usb_otg_apply_mode(priv);

	return 0;
}

static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw,
				    enum usb_role role)
{
	struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
	enum phy_mode mode;

	if (role == USB_ROLE_NONE)
		return 0;

	mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST
				       : PHY_MODE_USB_DEVICE;

	if (mode == priv->otg_phy_mode)
		return 0;

	return dwc3_meson_g12a_otg_mode_set(priv, mode);
}

static enum usb_role dwc3_meson_g12a_role_get(struct usb_role_switch *sw)
{
	struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);

	return priv->otg_phy_mode == PHY_MODE_USB_HOST ?
		USB_ROLE_HOST : USB_ROLE_DEVICE;
}

static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data)
{
	struct dwc3_meson_g12a *priv = data;
	enum phy_mode otg_id;

	otg_id = dwc3_meson_g12a_get_id(priv);
	if (otg_id != priv->otg_phy_mode) {
		if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
			dev_warn(priv->dev, "Failed to switch OTG mode\n");
	}

	regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0);

	return IRQ_HANDLED;
}

static struct device *dwc3_meson_g12_find_child(struct device *dev,
						const char *compatible)
{
	struct platform_device *pdev;
	struct device_node *np;

	np = of_get_compatible_child(dev->of_node, compatible);
	if (!np)
		return NULL;

	pdev = of_find_device_by_node(np);
	of_node_put(np);
	if (!pdev)
		return NULL;

	return &pdev->dev;
}

static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
				    struct dwc3_meson_g12a *priv)
{
	enum phy_mode otg_id;
	int ret, irq;
	struct device *dev = &pdev->dev;

	if (!priv->drvdata->otg_switch_supported)
		return 0;

	if (priv->otg_mode == USB_DR_MODE_OTG) {
		/* Ack irq before registering */
		regmap_update_bits(priv->regmap, USB_R5,
				   USB_R5_ID_DIG_IRQ, 0);

		irq = platform_get_irq(pdev, 0);
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
						dwc3_meson_g12a_irq_thread,
						IRQF_ONESHOT, pdev->name, priv);
		if (ret)
			return ret;
	}

	/* Setup OTG mode corresponding to the ID pin */
	if (priv->otg_mode == USB_DR_MODE_OTG) {
		otg_id = dwc3_meson_g12a_get_id(priv);
		if (otg_id != priv->otg_phy_mode) {
			if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
				dev_warn(dev, "Failed to switch OTG mode\n");
		}
	}

	/* Setup role switcher */
	priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
								"snps,dwc3");
	priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
	priv->switch_desc.allow_userspace_control = true;
	priv->switch_desc.set = dwc3_meson_g12a_role_set;
	priv->switch_desc.get = dwc3_meson_g12a_role_get;
	priv->switch_desc.driver_data = priv;

	priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
	if (IS_ERR(priv->role_switch))
		dev_warn(dev, "Unable to register Role Switch\n");

	return 0;
}

static int dwc3_meson_g12a_probe(struct platform_device *pdev)
{
	struct dwc3_meson_g12a	*priv;
	struct device		*dev = &pdev->dev;
	struct device_node	*np = dev->of_node;
	void __iomem *base;
	int ret, i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	priv->regmap = devm_regmap_init_mmio(dev, base,
					     &phy_meson_g12a_usb3_regmap_conf);
	if (IS_ERR(priv->regmap))
		return PTR_ERR(priv->regmap);

	priv->vbus = devm_regulator_get_optional(dev, "vbus");
	if (IS_ERR(priv->vbus)) {
		if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
			return PTR_ERR(priv->vbus);
		priv->vbus = NULL;
	}

	priv->drvdata = of_device_get_match_data(&pdev->dev);

	ret = devm_clk_bulk_get(dev,
				priv->drvdata->num_clks,
				priv->drvdata->clks);
	if (ret)
		return ret;

	ret = clk_bulk_prepare_enable(priv->drvdata->num_clks,
				      priv->drvdata->clks);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, priv);
	priv->dev = dev;

	priv->reset = devm_reset_control_get(dev, NULL);
	if (IS_ERR(priv->reset)) {
		ret = PTR_ERR(priv->reset);
		dev_err(dev, "failed to get device reset, err=%d\n", ret);
		return ret;
	}

	ret = reset_control_reset(priv->reset);
	if (ret)
		goto err_disable_clks;

	ret = dwc3_meson_g12a_get_phys(priv);
	if (ret)
		goto err_disable_clks;

	if (priv->vbus) {
		ret = regulator_enable(priv->vbus);
		if (ret)
			goto err_disable_clks;
	}

	/* Get dr_mode */
	priv->otg_mode = usb_get_dr_mode(dev);

	dwc3_meson_g12a_usb_init(priv);

	/* Init PHYs */
	for (i = 0 ; i < PHY_COUNT ; ++i) {
		ret = phy_init(priv->phys[i]);
		if (ret)
			goto err_disable_clks;
	}

	/* Set PHY Power */
	for (i = 0 ; i < PHY_COUNT ; ++i) {
		ret = phy_power_on(priv->phys[i]);
		if (ret)
			goto err_phys_exit;
	}

	ret = of_platform_populate(np, NULL, NULL, dev);
	if (ret)
		goto err_phys_power;

	ret = dwc3_meson_g12a_otg_init(pdev, priv);
	if (ret)
		goto err_phys_power;

	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	return 0;

err_phys_power:
	for (i = 0 ; i < PHY_COUNT ; ++i)
		phy_power_off(priv->phys[i]);

err_phys_exit:
	for (i = 0 ; i < PHY_COUNT ; ++i)
		phy_exit(priv->phys[i]);

err_disable_clks:
	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
				   priv->drvdata->clks);

	return ret;
}

static int dwc3_meson_g12a_remove(struct platform_device *pdev)
{
	struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev);
	struct device *dev = &pdev->dev;
	int i;

	if (priv->drvdata->otg_switch_supported)
		usb_role_switch_unregister(priv->role_switch);

	of_platform_depopulate(dev);

	for (i = 0 ; i < PHY_COUNT ; ++i) {
		phy_power_off(priv->phys[i]);
		phy_exit(priv->phys[i]);
	}

	pm_runtime_disable(dev);
	pm_runtime_put_noidle(dev);
	pm_runtime_set_suspended(dev);

	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
				   priv->drvdata->clks);

	return 0;
}

static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
{
	struct dwc3_meson_g12a	*priv = dev_get_drvdata(dev);

	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
				   priv->drvdata->clks);

	return 0;
}

static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
{
	struct dwc3_meson_g12a	*priv = dev_get_drvdata(dev);

	return clk_bulk_prepare_enable(priv->drvdata->num_clks,
				       priv->drvdata->clks);
}

static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
{
	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
	int i, ret;

	if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
		ret = regulator_disable(priv->vbus);
		if (ret)
			return ret;
	}

	for (i = 0 ; i < PHY_COUNT ; ++i) {
		phy_power_off(priv->phys[i]);
		phy_exit(priv->phys[i]);
	}

	reset_control_assert(priv->reset);

	return 0;
}

static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
{
	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
	int i, ret;

	reset_control_deassert(priv->reset);

	dwc3_meson_g12a_usb_init(priv);

	/* Init PHYs */
	for (i = 0 ; i < PHY_COUNT ; ++i) {
		ret = phy_init(priv->phys[i]);
		if (ret)
			return ret;
	}

	/* Set PHY Power */
	for (i = 0 ; i < PHY_COUNT ; ++i) {
		ret = phy_power_on(priv->phys[i]);
		if (ret)
			return ret;
	}

       if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
               ret = regulator_enable(priv->vbus);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume)
	SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend,
			   dwc3_meson_g12a_runtime_resume, NULL)
};

static const struct of_device_id dwc3_meson_g12a_match[] = {
	{
		.compatible = "amlogic,meson-g12a-usb-ctrl",
		.data = &g12a_drvdata,
	},
	{
		.compatible = "amlogic,meson-a1-usb-ctrl",
		.data = &a1_drvdata,
	},
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);

static struct platform_driver dwc3_meson_g12a_driver = {
	.probe		= dwc3_meson_g12a_probe,
	.remove		= dwc3_meson_g12a_remove,
	.driver		= {
		.name	= "dwc3-meson-g12a",
		.of_match_table = dwc3_meson_g12a_match,
		.pm	= &dwc3_meson_g12a_dev_pm_ops,
	},
};

module_platform_driver(dwc3_meson_g12a_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer");
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
Commit	Line	Data
c9999337 NA	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* USB Glue for Amlogic G12A SoCs
	4	*
	5	* Copyright (c) 2019 BayLibre, SAS
	6	* Author: Neil Armstrong <narmstrong@baylibre.com>
	7	*/
	8
	9	/*
	10	* The USB is organized with a glue around the DWC3 Controller IP as :
	11	* - Control registers for each USB2 Ports
	12	* - Control registers for the USB PHY layer
	13	* - SuperSpeed PHY can be enabled only if port is used
f90db107	14	* - Dynamic OTG switching with ID change interrupt
c9999337 NA	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/clk.h>
	21	#include <linux/of.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/pm_runtime.h>
	24	#include <linux/regmap.h>
	25	#include <linux/bitfield.h>
	26	#include <linux/bitops.h>
	27	#include <linux/reset.h>
	28	#include <linux/phy/phy.h>
	29	#include <linux/usb/otg.h>
	30	#include <linux/usb/role.h>
	31	#include <linux/regulator/consumer.h>
	32
	33	/* USB2 Ports Control Registers */
	34
	35	#define U2P_REG_SIZE 0x20
	36
	37	#define U2P_R0 0x0
	38	#define U2P_R0_HOST_DEVICE BIT(0)
	39	#define U2P_R0_POWER_OK BIT(1)
	40	#define U2P_R0_HAST_MODE BIT(2)
	41	#define U2P_R0_POWER_ON_RESET BIT(3)
	42	#define U2P_R0_ID_PULLUP BIT(4)
	43	#define U2P_R0_DRV_VBUS BIT(5)
	44
	45	#define U2P_R1 0x4
	46	#define U2P_R1_PHY_READY BIT(0)
	47	#define U2P_R1_ID_DIG BIT(1)
	48	#define U2P_R1_OTG_SESSION_VALID BIT(2)
	49	#define U2P_R1_VBUS_VALID BIT(3)
	50
	51	/* USB Glue Control Registers */
	52
	53	#define USB_R0 0x80
	54	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
	55	#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
	56	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
	57	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
	58	#define USB_R0_U2D_ACT BIT(31)
	59
	60	#define USB_R1 0x84
	61	#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
	62	#define USB_R1_U3H_PME_ENABLE BIT(1)
	63	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
	64	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
	65	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
	66	#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
	67	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
	68	#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
	69	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
	70	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
	71
	72	#define USB_R2 0x88
	73	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
	74	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
	75
	76	#define USB_R3 0x8c
	77	#define USB_R3_P30_SSC_ENABLE BIT(0)
	78	#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
79	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
80	#define USB_R3_P30_REF_SSP_EN BIT(13)
81
82	#define USB_R4 0x90
83	#define USB_R4_P21_PORT_RESET_0 BIT(0)
84	#define USB_R4_P21_SLEEP_M0 BIT(1)
85	#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
86	#define USB_R4_P21_ONLY BIT(4)
87
88	#define USB_R5 0x94
89	#define USB_R5_ID_DIG_SYNC BIT(0)
90	#define USB_R5_ID_DIG_REG BIT(1)
91	#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
92	#define USB_R5_ID_DIG_EN_0 BIT(4)
93	#define USB_R5_ID_DIG_EN_1 BIT(5)
94	#define USB_R5_ID_DIG_CURR BIT(6)
95	#define USB_R5_ID_DIG_IRQ BIT(7)
96	#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
97	#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
98
5174564c NA	99	#define PHY_COUNT 3
5174564c NA	100	#define USB2_OTG_PHY 1
c9999337	101
1e355f21 HL	102	static struct clk_bulk_data meson_g12a_clocks[] = {
	103	{ .id = NULL },
	104	};
	105
	106	static struct clk_bulk_data meson_a1_clocks[] = {
	107	{ .id = "usb_ctrl" },
	108	{ .id = "usb_bus" },
	109	{ .id = "xtal_usb_ctrl" },
	110	};
	111
5174564c NA	112	static const char *meson_g12a_phy_names[] = {
	113	"usb2-phy0", "usb2-phy1", "usb3-phy0",
	114	};
	115
	116	/*
	117	* Amlogic A1 has a single physical PHY, in slot 1, but still has the
	118	* two U2 PHY controls register blocks like G12A.
	119	* Handling the first PHY on slot 1 would need a large amount of code
	120	* changes, and the current management is generic enough to handle it
	121	* correctly when only the "usb2-phy1" phy is specified on-par with the
	122	* DT bindings.
	123	*/
	124	static const char *meson_a1_phy_names[] = {
	125	"usb2-phy0", "usb2-phy1"
	126	};
	127
1e355f21 HL	128	struct dwc3_meson_g12a_drvdata {
	129	bool otg_switch_supported;
	130	struct clk_bulk_data *clks;
	131	int num_clks;
5174564c NA	132	const char **phy_names;
5174564c NA	133	int num_phys;
1e355f21 HL	134	};
	135
	136	static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
	137	.otg_switch_supported = true,
	138	.clks = meson_g12a_clocks,
	139	.num_clks = ARRAY_SIZE(meson_g12a_clocks),
5174564c NA	140	.phy_names = meson_g12a_phy_names,
5174564c NA	141	.num_phys = ARRAY_SIZE(meson_g12a_phy_names),
1e355f21 HL	142	};
	143
	144	static struct dwc3_meson_g12a_drvdata a1_drvdata = {
	145	.otg_switch_supported = false,
	146	.clks = meson_a1_clocks,
	147	.num_clks = ARRAY_SIZE(meson_a1_clocks),
5174564c NA	148	.phy_names = meson_a1_phy_names,
5174564c NA	149	.num_phys = ARRAY_SIZE(meson_a1_phy_names),
1e355f21 HL	150	};
1e355f21 HL	151
c9999337 NA	152	struct dwc3_meson_g12a {
	153	struct device *dev;
	154	struct regmap *regmap;
c9999337 NA	155	struct reset_control *reset;
	156	struct phy *phys[PHY_COUNT];
	157	enum usb_dr_mode otg_mode;
	158	enum phy_mode otg_phy_mode;
	159	unsigned int usb2_ports;
	160	unsigned int usb3_ports;
	161	struct regulator *vbus;
	162	struct usb_role_switch_desc switch_desc;
	163	struct usb_role_switch *role_switch;
1e355f21	164	const struct dwc3_meson_g12a_drvdata *drvdata;
c9999337 NA	165	};
	166
	167	static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
	168	int i, enum phy_mode mode)
	169	{
	170	if (mode == PHY_MODE_USB_HOST)
	171	regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
	172	U2P_R0_HOST_DEVICE,
	173	U2P_R0_HOST_DEVICE);
	174	else
	175	regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
	176	U2P_R0_HOST_DEVICE, 0);
	177	}
	178
	179	static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
	180	{
	181	int i;
	182
	183	if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
	184	priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
	185	else
	186	priv->otg_phy_mode = PHY_MODE_USB_HOST;
	187
5174564c	188	for (i = 0; i < priv->drvdata->num_phys; ++i) {
c9999337 NA	189	if (!priv->phys[i])
	190	continue;
	191
5174564c NA	192	if (!strstr(priv->drvdata->phy_names[i], "usb2"))
	193	continue;
	194
c9999337 NA	195	regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
	196	U2P_R0_POWER_ON_RESET,
	197	U2P_R0_POWER_ON_RESET);
	198
1e355f21	199	if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) {
c9999337 NA	200	regmap_update_bits(priv->regmap,
	201	U2P_R0 + (U2P_REG_SIZE * i),
	202	U2P_R0_ID_PULLUP \| U2P_R0_DRV_VBUS,
	203	U2P_R0_ID_PULLUP \| U2P_R0_DRV_VBUS);
	204
	205	dwc3_meson_g12a_usb2_set_mode(priv, i,
	206	priv->otg_phy_mode);
	207	} else
	208	dwc3_meson_g12a_usb2_set_mode(priv, i,
	209	PHY_MODE_USB_HOST);
	210
	211	regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
	212	U2P_R0_POWER_ON_RESET, 0);
	213	}
	214
	215	return 0;
	216	}
	217
	218	static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
	219	{
	220	regmap_update_bits(priv->regmap, USB_R3,
	221	USB_R3_P30_SSC_RANGE_MASK \|
	222	USB_R3_P30_REF_SSP_EN,
	223	USB_R3_P30_SSC_ENABLE \|
	224	FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) \|
	225	USB_R3_P30_REF_SSP_EN);
	226	udelay(2);
	227
	228	regmap_update_bits(priv->regmap, USB_R2,
	229	USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
	230	FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
	231
	232	regmap_update_bits(priv->regmap, USB_R2,
	233	USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
	234	FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
	235
	236	udelay(2);
	237
	238	regmap_update_bits(priv->regmap, USB_R1,
	239	USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
	240	USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
	241
	242	regmap_update_bits(priv->regmap, USB_R1,
	243	USB_R1_P30_PCS_TX_SWING_FULL_MASK,
	244	FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
	245	}
	246
	247	static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
	248	{
	249	if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) {
	250	regmap_update_bits(priv->regmap, USB_R0,
	251	USB_R0_U2D_ACT, USB_R0_U2D_ACT);
	252	regmap_update_bits(priv->regmap, USB_R0,
	253	USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
	254	regmap_update_bits(priv->regmap, USB_R4,
	255	USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
	256	} else {
	257	regmap_update_bits(priv->regmap, USB_R0,
	258	USB_R0_U2D_ACT, 0);
	259	regmap_update_bits(priv->regmap, USB_R4,
	260	USB_R4_P21_SLEEP_M0, 0);
	261	}
	262	}
	263
264	static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
265	{
266	int ret;
267
268	ret = dwc3_meson_g12a_usb2_init(priv);
269	if (ret)
270	return ret;
271
272	regmap_update_bits(priv->regmap, USB_R1,
273	USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
274	FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
275
276	regmap_update_bits(priv->regmap, USB_R5,
277	USB_R5_ID_DIG_EN_0,
278	USB_R5_ID_DIG_EN_0);
279	regmap_update_bits(priv->regmap, USB_R5,
280	USB_R5_ID_DIG_EN_1,
281	USB_R5_ID_DIG_EN_1);
282	regmap_update_bits(priv->regmap, USB_R5,
283	USB_R5_ID_DIG_TH_MASK,
284	FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
285
286	/* If we have an actual SuperSpeed port, initialize it */
287	if (priv->usb3_ports)
288	dwc3_meson_g12a_usb3_init(priv);
289
290	dwc3_meson_g12a_usb_otg_apply_mode(priv);
291
292	return 0;
293	}
294
295	static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = {
296	.reg_bits = 8,
297	.val_bits = 32,
298	.reg_stride = 4,
299	.max_register = USB_R5,
300	};
301
302	static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
303	{
5174564c	304	const char *phy_name;
c9999337 NA	305	int i;
c9999337 NA	306
5174564c NA	307	for (i = 0 ; i < priv->drvdata->num_phys ; ++i) {
	308	phy_name = priv->drvdata->phy_names[i];
	309	priv->phys[i] = devm_phy_optional_get(priv->dev, phy_name);
c9999337 NA	310	if (!priv->phys[i])
	311	continue;
	312
	313	if (IS_ERR(priv->phys[i]))
	314	return PTR_ERR(priv->phys[i]);
	315
5174564c	316	if (strstr(phy_name, "usb3"))
c9999337 NA	317	priv->usb3_ports++;
	318	else
	319	priv->usb2_ports++;
	320	}
	321
	322	dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports);
	323	dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports);
	324
	325	return 0;
	326	}
	327
	328	static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv)
	329	{
	330	u32 reg;
	331
	332	regmap_read(priv->regmap, USB_R5, &reg);
	333
	334	if (reg & (USB_R5_ID_DIG_SYNC \| USB_R5_ID_DIG_REG))
	335	return PHY_MODE_USB_DEVICE;
	336
	337	return PHY_MODE_USB_HOST;
	338	}
	339
	340	static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
	341	enum phy_mode mode)
	342	{
	343	int ret;
	344
1e355f21	345	if (!priv->drvdata->otg_switch_supported \|\| !priv->phys[USB2_OTG_PHY])
c9999337 NA	346	return -EINVAL;
	347
	348	if (mode == PHY_MODE_USB_HOST)
	349	dev_info(priv->dev, "switching to Host Mode\n");
	350	else
	351	dev_info(priv->dev, "switching to Device Mode\n");
	352
	353	if (priv->vbus) {
	354	if (mode == PHY_MODE_USB_DEVICE)
	355	ret = regulator_disable(priv->vbus);
	356	else
	357	ret = regulator_enable(priv->vbus);
	358	if (ret)
	359	return ret;
	360	}
	361
	362	priv->otg_phy_mode = mode;
	363
	364	dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
	365
	366	dwc3_meson_g12a_usb_otg_apply_mode(priv);
	367
	368	return 0;
	369	}
	370
bce3052f HK	371	static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw,
bce3052f HK	372	enum usb_role role)
c9999337	373	{
bce3052f	374	struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
c9999337 NA	375	enum phy_mode mode;
	376
	377	if (role == USB_ROLE_NONE)
	378	return 0;
	379
	380	mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST
	381	: PHY_MODE_USB_DEVICE;
	382
	383	if (mode == priv->otg_phy_mode)
	384	return 0;
	385
	386	return dwc3_meson_g12a_otg_mode_set(priv, mode);
	387	}
	388
bce3052f	389	static enum usb_role dwc3_meson_g12a_role_get(struct usb_role_switch *sw)
c9999337	390	{
bce3052f	391	struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
c9999337 NA	392
	393	return priv->otg_phy_mode == PHY_MODE_USB_HOST ?
	394	USB_ROLE_HOST : USB_ROLE_DEVICE;
	395	}
	396
f90db107 NA	397	static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data)
	398	{
	399	struct dwc3_meson_g12a *priv = data;
	400	enum phy_mode otg_id;
	401
	402	otg_id = dwc3_meson_g12a_get_id(priv);
	403	if (otg_id != priv->otg_phy_mode) {
	404	if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
	405	dev_warn(priv->dev, "Failed to switch OTG mode\n");
	406	}
	407
	408	regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0);
	409
	410	return IRQ_HANDLED;
	411	}
	412
c9999337 NA	413	static struct device dwc3_meson_g12_find_child(struct device dev,
	414	const char *compatible)
	415	{
	416	struct platform_device *pdev;
	417	struct device_node *np;
	418
	419	np = of_get_compatible_child(dev->of_node, compatible);
	420	if (!np)
	421	return NULL;
	422
	423	pdev = of_find_device_by_node(np);
	424	of_node_put(np);
	425	if (!pdev)
	426	return NULL;
	427
	428	return &pdev->dev;
	429	}
	430
1e355f21 HL	431	static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
	432	struct dwc3_meson_g12a *priv)
	433	{
	434	enum phy_mode otg_id;
	435	int ret, irq;
	436	struct device *dev = &pdev->dev;
	437
	438	if (!priv->drvdata->otg_switch_supported)
	439	return 0;
	440
	441	if (priv->otg_mode == USB_DR_MODE_OTG) {
	442	/* Ack irq before registering */
	443	regmap_update_bits(priv->regmap, USB_R5,
	444	USB_R5_ID_DIG_IRQ, 0);
	445
	446	irq = platform_get_irq(pdev, 0);
	447	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	448	dwc3_meson_g12a_irq_thread,
	449	IRQF_ONESHOT, pdev->name, priv);
	450	if (ret)
	451	return ret;
	452	}
	453
	454	/* Setup OTG mode corresponding to the ID pin */
	455	if (priv->otg_mode == USB_DR_MODE_OTG) {
	456	otg_id = dwc3_meson_g12a_get_id(priv);
	457	if (otg_id != priv->otg_phy_mode) {
	458	if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
	459	dev_warn(dev, "Failed to switch OTG mode\n");
	460	}
	461	}
	462
	463	/* Setup role switcher */
	464	priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
	465	"snps,dwc3");
	466	priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
	467	priv->switch_desc.allow_userspace_control = true;
	468	priv->switch_desc.set = dwc3_meson_g12a_role_set;
	469	priv->switch_desc.get = dwc3_meson_g12a_role_get;
a8ab3e76	470	priv->switch_desc.driver_data = priv;
1e355f21 HL	471
	472	priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
	473	if (IS_ERR(priv->role_switch))
	474	dev_warn(dev, "Unable to register Role Switch\n");
	475
238d7602	476	return 0;
1e355f21 HL	477	}
1e355f21 HL	478
c9999337 NA	479	static int dwc3_meson_g12a_probe(struct platform_device *pdev)
	480	{
	481	struct dwc3_meson_g12a *priv;
	482	struct device *dev = &pdev->dev;
	483	struct device_node *np = dev->of_node;
	484	void __iomem *base;
1e355f21	485	int ret, i;
c9999337 NA	486
	487	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	488	if (!priv)
	489	return -ENOMEM;
	490
c6e4999c	491	base = devm_platform_ioremap_resource(pdev, 0);
c9999337 NA	492	if (IS_ERR(base))
	493	return PTR_ERR(base);
	494
	495	priv->regmap = devm_regmap_init_mmio(dev, base,
	496	&phy_meson_g12a_usb3_regmap_conf);
	497	if (IS_ERR(priv->regmap))
	498	return PTR_ERR(priv->regmap);
	499
	500	priv->vbus = devm_regulator_get_optional(dev, "vbus");
	501	if (IS_ERR(priv->vbus)) {
	502	if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
	503	return PTR_ERR(priv->vbus);
	504	priv->vbus = NULL;
	505	}
	506
1e355f21	507	priv->drvdata = of_device_get_match_data(&pdev->dev);
c9999337	508
1e355f21 HL	509	ret = devm_clk_bulk_get(dev,
	510	priv->drvdata->num_clks,
	511	priv->drvdata->clks);
c9999337 NA	512	if (ret)
	513	return ret;
	514
1e355f21 HL	515	ret = clk_bulk_prepare_enable(priv->drvdata->num_clks,
	516	priv->drvdata->clks);
	517	if (ret)
	518	return ret;
c9999337 NA	519
	520	platform_set_drvdata(pdev, priv);
	521	priv->dev = dev;
	522
	523	priv->reset = devm_reset_control_get(dev, NULL);
	524	if (IS_ERR(priv->reset)) {
	525	ret = PTR_ERR(priv->reset);
	526	dev_err(dev, "failed to get device reset, err=%d\n", ret);
	527	return ret;
	528	}
	529
	530	ret = reset_control_reset(priv->reset);
	531	if (ret)
1e355f21	532	goto err_disable_clks;
c9999337 NA	533
	534	ret = dwc3_meson_g12a_get_phys(priv);
	535	if (ret)
1e355f21	536	goto err_disable_clks;
c9999337 NA	537
	538	if (priv->vbus) {
	539	ret = regulator_enable(priv->vbus);
	540	if (ret)
1e355f21	541	goto err_disable_clks;
c9999337 NA	542	}
	543
	544	/* Get dr_mode */
	545	priv->otg_mode = usb_get_dr_mode(dev);
	546
	547	dwc3_meson_g12a_usb_init(priv);
	548
	549	/* Init PHYs */
	550	for (i = 0 ; i < PHY_COUNT ; ++i) {
	551	ret = phy_init(priv->phys[i]);
	552	if (ret)
1e355f21	553	goto err_disable_clks;
c9999337 NA	554	}
	555
	556	/* Set PHY Power */
	557	for (i = 0 ; i < PHY_COUNT ; ++i) {
	558	ret = phy_power_on(priv->phys[i]);
	559	if (ret)
	560	goto err_phys_exit;
	561	}
	562
	563	ret = of_platform_populate(np, NULL, NULL, dev);
1e355f21	564	if (ret)
c9999337	565	goto err_phys_power;
c9999337	566
1e355f21 HL	567	ret = dwc3_meson_g12a_otg_init(pdev, priv);
	568	if (ret)
	569	goto err_phys_power;
c9999337 NA	570
	571	pm_runtime_set_active(dev);
	572	pm_runtime_enable(dev);
	573	pm_runtime_get_sync(dev);
	574
	575	return 0;
	576
	577	err_phys_power:
	578	for (i = 0 ; i < PHY_COUNT ; ++i)
	579	phy_power_off(priv->phys[i]);
	580
	581	err_phys_exit:
	582	for (i = 0 ; i < PHY_COUNT ; ++i)
	583	phy_exit(priv->phys[i]);
	584
1e355f21 HL	585	err_disable_clks:
	586	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
	587	priv->drvdata->clks);
	588
c9999337 NA	589	return ret;
	590	}
	591
	592	static int dwc3_meson_g12a_remove(struct platform_device *pdev)
	593	{
	594	struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev);
	595	struct device *dev = &pdev->dev;
	596	int i;
	597
1e355f21 HL	598	if (priv->drvdata->otg_switch_supported)
1e355f21 HL	599	usb_role_switch_unregister(priv->role_switch);
c9999337 NA	600
	601	of_platform_depopulate(dev);
	602
	603	for (i = 0 ; i < PHY_COUNT ; ++i) {
	604	phy_power_off(priv->phys[i]);
	605	phy_exit(priv->phys[i]);
	606	}
	607
	608	pm_runtime_disable(dev);
	609	pm_runtime_put_noidle(dev);
	610	pm_runtime_set_suspended(dev);
	611
1e355f21 HL	612	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
	613	priv->drvdata->clks);
	614
c9999337 NA	615	return 0;
	616	}
	617
	618	static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
	619	{
	620	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
	621
1e355f21 HL	622	clk_bulk_disable_unprepare(priv->drvdata->num_clks,
1e355f21 HL	623	priv->drvdata->clks);
c9999337 NA	624
	625	return 0;
	626	}
	627
	628	static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
	629	{
	630	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
	631
1e355f21 HL	632	return clk_bulk_prepare_enable(priv->drvdata->num_clks,
1e355f21 HL	633	priv->drvdata->clks);
c9999337 NA	634	}
	635
	636	static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
	637	{
	638	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
1cf084d1 NA	639	int i, ret;
	640
	641	if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
	642	ret = regulator_disable(priv->vbus);
	643	if (ret)
	644	return ret;
	645	}
c9999337 NA	646
	647	for (i = 0 ; i < PHY_COUNT ; ++i) {
	648	phy_power_off(priv->phys[i]);
	649	phy_exit(priv->phys[i]);
	650	}
	651
	652	reset_control_assert(priv->reset);
	653
	654	return 0;
	655	}
	656
	657	static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
	658	{
	659	struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
	660	int i, ret;
	661
	662	reset_control_deassert(priv->reset);
	663
	664	dwc3_meson_g12a_usb_init(priv);
	665
	666	/* Init PHYs */
	667	for (i = 0 ; i < PHY_COUNT ; ++i) {
	668	ret = phy_init(priv->phys[i]);
	669	if (ret)
	670	return ret;
	671	}
	672
	673	/* Set PHY Power */
	674	for (i = 0 ; i < PHY_COUNT ; ++i) {
	675	ret = phy_power_on(priv->phys[i]);
	676	if (ret)
	677	return ret;
	678	}
	679
1cf084d1 NA	680	if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
	681	ret = regulator_enable(priv->vbus);
	682	if (ret)
	683	return ret;
	684	}
	685
c9999337 NA	686	return 0;
	687	}
	688
	689	static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
	690	SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume)
	691	SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend,
	692	dwc3_meson_g12a_runtime_resume, NULL)
	693	};
	694
	695	static const struct of_device_id dwc3_meson_g12a_match[] = {
1e355f21 HL	696	{
	697	.compatible = "amlogic,meson-g12a-usb-ctrl",
	698	.data = &g12a_drvdata,
	699	},
	700	{
	701	.compatible = "amlogic,meson-a1-usb-ctrl",
	702	.data = &a1_drvdata,
	703	},
c9999337 NA	704	{ /* Sentinel */ }
	705	};
	706	MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
	707
	708	static struct platform_driver dwc3_meson_g12a_driver = {
	709	.probe = dwc3_meson_g12a_probe,
	710	.remove = dwc3_meson_g12a_remove,
	711	.driver = {
	712	.name = "dwc3-meson-g12a",
	713	.of_match_table = dwc3_meson_g12a_match,
	714	.pm = &dwc3_meson_g12a_dev_pm_ops,
	715	},
	716	};
	717
	718	module_platform_driver(dwc3_meson_g12a_driver);
	719	MODULE_LICENSE("GPL v2");
	720	MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer");
	721	MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");