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72246da4 FB |
1 | /** |
2 | * dwc3-omap.c - OMAP Specific Glue layer | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
a72e658b | 19 | #include <linux/module.h> |
72246da4 FB |
20 | #include <linux/kernel.h> |
21 | #include <linux/slab.h> | |
12a7f17f | 22 | #include <linux/irq.h> |
72246da4 | 23 | #include <linux/interrupt.h> |
72246da4 | 24 | #include <linux/platform_device.h> |
9962444f | 25 | #include <linux/platform_data/dwc3-omap.h> |
af310e96 | 26 | #include <linux/pm_runtime.h> |
72246da4 FB |
27 | #include <linux/dma-mapping.h> |
28 | #include <linux/ioport.h> | |
29 | #include <linux/io.h> | |
45b3cd4a | 30 | #include <linux/of.h> |
b4bfe6aa | 31 | #include <linux/of_platform.h> |
8061ad72 | 32 | #include <linux/extcon.h> |
8061ad72 | 33 | #include <linux/regulator/consumer.h> |
72246da4 | 34 | |
a418cc4e | 35 | #include <linux/usb/otg.h> |
a418cc4e | 36 | |
72246da4 FB |
37 | /* |
38 | * All these registers belong to OMAP's Wrapper around the | |
39 | * DesignWare USB3 Core. | |
40 | */ | |
41 | ||
42 | #define USBOTGSS_REVISION 0x0000 | |
43 | #define USBOTGSS_SYSCONFIG 0x0010 | |
44 | #define USBOTGSS_IRQ_EOI 0x0020 | |
ff7307b5 | 45 | #define USBOTGSS_EOI_OFFSET 0x0008 |
72246da4 FB |
46 | #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 |
47 | #define USBOTGSS_IRQSTATUS_0 0x0028 | |
48 | #define USBOTGSS_IRQENABLE_SET_0 0x002c | |
49 | #define USBOTGSS_IRQENABLE_CLR_0 0x0030 | |
ff7307b5 | 50 | #define USBOTGSS_IRQ0_OFFSET 0x0004 |
b1fd6cb5 GC |
51 | #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 |
52 | #define USBOTGSS_IRQSTATUS_1 0x0034 | |
53 | #define USBOTGSS_IRQENABLE_SET_1 0x0038 | |
54 | #define USBOTGSS_IRQENABLE_CLR_1 0x003c | |
55 | #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 | |
56 | #define USBOTGSS_IRQSTATUS_2 0x0044 | |
57 | #define USBOTGSS_IRQENABLE_SET_2 0x0048 | |
58 | #define USBOTGSS_IRQENABLE_CLR_2 0x004c | |
59 | #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 | |
60 | #define USBOTGSS_IRQSTATUS_3 0x0054 | |
61 | #define USBOTGSS_IRQENABLE_SET_3 0x0058 | |
62 | #define USBOTGSS_IRQENABLE_CLR_3 0x005c | |
ff7307b5 GC |
63 | #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 |
64 | #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 | |
65 | #define USBOTGSS_IRQSTATUS_MISC 0x0038 | |
66 | #define USBOTGSS_IRQENABLE_SET_MISC 0x003c | |
67 | #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 | |
68 | #define USBOTGSS_IRQMISC_OFFSET 0x03fc | |
22832190 BL |
69 | #define USBOTGSS_UTMI_OTG_STATUS 0x0080 |
70 | #define USBOTGSS_UTMI_OTG_CTRL 0x0084 | |
ff7307b5 GC |
71 | #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 |
72 | #define USBOTGSS_TXFIFO_DEPTH 0x0508 | |
73 | #define USBOTGSS_RXFIFO_DEPTH 0x050c | |
72246da4 FB |
74 | #define USBOTGSS_MMRAM_OFFSET 0x0100 |
75 | #define USBOTGSS_FLADJ 0x0104 | |
76 | #define USBOTGSS_DEBUG_CFG 0x0108 | |
77 | #define USBOTGSS_DEBUG_DATA 0x010c | |
ff7307b5 GC |
78 | #define USBOTGSS_DEV_EBC_EN 0x0110 |
79 | #define USBOTGSS_DEBUG_OFFSET 0x0600 | |
72246da4 FB |
80 | |
81 | /* SYSCONFIG REGISTER */ | |
82 | #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) | |
4b5faa7a | 83 | |
72246da4 FB |
84 | /* IRQ_EOI REGISTER */ |
85 | #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) | |
86 | ||
87 | /* IRQS0 BITS */ | |
88 | #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) | |
89 | ||
b1fd6cb5 GC |
90 | /* IRQMISC BITS */ |
91 | #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) | |
92 | #define USBOTGSS_IRQMISC_OEVT (1 << 16) | |
93 | #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) | |
94 | #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) | |
95 | #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) | |
96 | #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) | |
97 | #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) | |
98 | #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) | |
99 | #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) | |
100 | #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) | |
72246da4 | 101 | |
72246da4 | 102 | /* UTMI_OTG_STATUS REGISTER */ |
22832190 BL |
103 | #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5) |
104 | #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4) | |
105 | #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3) | |
106 | #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0) | |
107 | ||
108 | /* UTMI_OTG_CTRL REGISTER */ | |
109 | #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31) | |
110 | #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9) | |
111 | #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8) | |
112 | #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4) | |
113 | #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3) | |
114 | #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2) | |
115 | #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1) | |
72246da4 FB |
116 | |
117 | struct dwc3_omap { | |
72246da4 FB |
118 | struct device *dev; |
119 | ||
120 | int irq; | |
121 | void __iomem *base; | |
122 | ||
22832190 | 123 | u32 utmi_otg_ctrl; |
1e2a064c GC |
124 | u32 utmi_otg_offset; |
125 | u32 irqmisc_offset; | |
126 | u32 irq_eoi_offset; | |
127 | u32 debug_offset; | |
128 | u32 irq0_offset; | |
f3e117f4 | 129 | |
5960387a | 130 | struct extcon_dev *edev; |
8061ad72 KVA |
131 | struct notifier_block vbus_nb; |
132 | struct notifier_block id_nb; | |
133 | ||
134 | struct regulator *vbus_reg; | |
72246da4 FB |
135 | }; |
136 | ||
8061ad72 KVA |
137 | enum omap_dwc3_vbus_id_status { |
138 | OMAP_DWC3_ID_FLOAT, | |
139 | OMAP_DWC3_ID_GROUND, | |
140 | OMAP_DWC3_VBUS_OFF, | |
141 | OMAP_DWC3_VBUS_VALID, | |
142 | }; | |
7e41bba9 | 143 | |
ab5e59db IS |
144 | static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) |
145 | { | |
146 | return readl(base + offset); | |
147 | } | |
148 | ||
149 | static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) | |
150 | { | |
151 | writel(value, base + offset); | |
152 | } | |
153 | ||
22832190 | 154 | static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) |
b1fd6cb5 | 155 | { |
22832190 | 156 | return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + |
b1fd6cb5 GC |
157 | omap->utmi_otg_offset); |
158 | } | |
159 | ||
22832190 | 160 | static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) |
b1fd6cb5 | 161 | { |
22832190 | 162 | dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + |
b1fd6cb5 GC |
163 | omap->utmi_otg_offset, value); |
164 | ||
165 | } | |
166 | ||
167 | static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) | |
168 | { | |
3f586c92 | 169 | return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - |
b1fd6cb5 GC |
170 | omap->irq0_offset); |
171 | } | |
172 | ||
173 | static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) | |
174 | { | |
175 | dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - | |
176 | omap->irq0_offset, value); | |
177 | ||
178 | } | |
179 | ||
180 | static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) | |
181 | { | |
3f586c92 | 182 | return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + |
b1fd6cb5 GC |
183 | omap->irqmisc_offset); |
184 | } | |
185 | ||
186 | static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) | |
187 | { | |
188 | dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + | |
189 | omap->irqmisc_offset, value); | |
190 | ||
191 | } | |
192 | ||
193 | static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) | |
194 | { | |
195 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + | |
196 | omap->irqmisc_offset, value); | |
197 | ||
198 | } | |
199 | ||
200 | static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) | |
201 | { | |
202 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - | |
203 | omap->irq0_offset, value); | |
204 | } | |
205 | ||
96e5d312 GC |
206 | static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) |
207 | { | |
208 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + | |
209 | omap->irqmisc_offset, value); | |
210 | } | |
211 | ||
212 | static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) | |
213 | { | |
214 | dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - | |
215 | omap->irq0_offset, value); | |
216 | } | |
217 | ||
8061ad72 KVA |
218 | static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, |
219 | enum omap_dwc3_vbus_id_status status) | |
7e41bba9 | 220 | { |
8061ad72 KVA |
221 | int ret; |
222 | u32 val; | |
2ba7943a | 223 | |
7e41bba9 KVA |
224 | switch (status) { |
225 | case OMAP_DWC3_ID_GROUND: | |
8061ad72 KVA |
226 | if (omap->vbus_reg) { |
227 | ret = regulator_enable(omap->vbus_reg); | |
228 | if (ret) { | |
e4f75667 | 229 | dev_err(omap->dev, "regulator enable failed\n"); |
8061ad72 KVA |
230 | return; |
231 | } | |
232 | } | |
233 | ||
22832190 | 234 | val = dwc3_omap_read_utmi_ctrl(omap); |
d2728fb3 | 235 | val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG; |
22832190 | 236 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
237 | break; |
238 | ||
239 | case OMAP_DWC3_VBUS_VALID: | |
22832190 BL |
240 | val = dwc3_omap_read_utmi_ctrl(omap); |
241 | val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; | |
d2728fb3 | 242 | val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID |
9ab330bf | 243 | | USBOTGSS_UTMI_OTG_CTRL_SESSVALID; |
22832190 | 244 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
245 | break; |
246 | ||
247 | case OMAP_DWC3_ID_FLOAT: | |
8061ad72 KVA |
248 | if (omap->vbus_reg) |
249 | regulator_disable(omap->vbus_reg); | |
d2728fb3 RQ |
250 | val = dwc3_omap_read_utmi_ctrl(omap); |
251 | val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; | |
252 | dwc3_omap_write_utmi_ctrl(omap, val); | |
8061ad72 | 253 | |
7e41bba9 | 254 | case OMAP_DWC3_VBUS_OFF: |
22832190 BL |
255 | val = dwc3_omap_read_utmi_ctrl(omap); |
256 | val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID | |
9ab330bf | 257 | | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID); |
d2728fb3 | 258 | val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND; |
22832190 | 259 | dwc3_omap_write_utmi_ctrl(omap, val); |
7e41bba9 KVA |
260 | break; |
261 | ||
262 | default: | |
e4f75667 | 263 | dev_WARN(omap->dev, "invalid state\n"); |
7e41bba9 | 264 | } |
7e41bba9 | 265 | } |
7e41bba9 | 266 | |
3f586c92 RQ |
267 | static void dwc3_omap_enable_irqs(struct dwc3_omap *omap); |
268 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap); | |
269 | ||
72246da4 | 270 | static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) |
3f586c92 RQ |
271 | { |
272 | struct dwc3_omap *omap = _omap; | |
273 | ||
274 | if (dwc3_omap_read_irqmisc_status(omap) || | |
275 | dwc3_omap_read_irq0_status(omap)) { | |
276 | /* mask irqs */ | |
277 | dwc3_omap_disable_irqs(omap); | |
278 | return IRQ_WAKE_THREAD; | |
279 | } | |
280 | ||
281 | return IRQ_NONE; | |
282 | } | |
283 | ||
284 | static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap) | |
72246da4 FB |
285 | { |
286 | struct dwc3_omap *omap = _omap; | |
287 | u32 reg; | |
72246da4 | 288 | |
3f586c92 | 289 | /* clear irq status flags */ |
b1fd6cb5 | 290 | reg = dwc3_omap_read_irqmisc_status(omap); |
b1fd6cb5 GC |
291 | dwc3_omap_write_irqmisc_status(omap, reg); |
292 | ||
293 | reg = dwc3_omap_read_irq0_status(omap); | |
b1fd6cb5 | 294 | dwc3_omap_write_irq0_status(omap, reg); |
72246da4 | 295 | |
3f586c92 RQ |
296 | /* unmask irqs */ |
297 | dwc3_omap_enable_irqs(omap); | |
298 | ||
72246da4 FB |
299 | return IRQ_HANDLED; |
300 | } | |
301 | ||
9a4b5dab FB |
302 | static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) |
303 | { | |
304 | u32 reg; | |
305 | ||
306 | /* enable all IRQs */ | |
307 | reg = USBOTGSS_IRQO_COREIRQ_ST; | |
b1fd6cb5 GC |
308 | dwc3_omap_write_irq0_set(omap, reg); |
309 | ||
310 | reg = (USBOTGSS_IRQMISC_OEVT | | |
311 | USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
312 | USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
313 | USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
314 | USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
315 | USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
316 | USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
317 | USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
318 | USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
319 | ||
320 | dwc3_omap_write_irqmisc_set(omap, reg); | |
9a4b5dab FB |
321 | } |
322 | ||
323 | static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) | |
324 | { | |
96e5d312 GC |
325 | u32 reg; |
326 | ||
9a4b5dab | 327 | /* disable all IRQs */ |
96e5d312 GC |
328 | reg = USBOTGSS_IRQO_COREIRQ_ST; |
329 | dwc3_omap_write_irq0_clr(omap, reg); | |
330 | ||
331 | reg = (USBOTGSS_IRQMISC_OEVT | | |
332 | USBOTGSS_IRQMISC_DRVVBUS_RISE | | |
333 | USBOTGSS_IRQMISC_CHRGVBUS_RISE | | |
334 | USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | | |
335 | USBOTGSS_IRQMISC_IDPULLUP_RISE | | |
336 | USBOTGSS_IRQMISC_DRVVBUS_FALL | | |
337 | USBOTGSS_IRQMISC_CHRGVBUS_FALL | | |
338 | USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | | |
339 | USBOTGSS_IRQMISC_IDPULLUP_FALL); | |
340 | ||
341 | dwc3_omap_write_irqmisc_clr(omap, reg); | |
9a4b5dab FB |
342 | } |
343 | ||
8061ad72 KVA |
344 | static int dwc3_omap_id_notifier(struct notifier_block *nb, |
345 | unsigned long event, void *ptr) | |
346 | { | |
347 | struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); | |
348 | ||
349 | if (event) | |
350 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); | |
351 | else | |
352 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); | |
353 | ||
354 | return NOTIFY_DONE; | |
355 | } | |
356 | ||
357 | static int dwc3_omap_vbus_notifier(struct notifier_block *nb, | |
358 | unsigned long event, void *ptr) | |
359 | { | |
360 | struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); | |
361 | ||
362 | if (event) | |
363 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); | |
364 | else | |
365 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); | |
366 | ||
367 | return NOTIFY_DONE; | |
368 | } | |
369 | ||
30fef1a9 GC |
370 | static void dwc3_omap_map_offset(struct dwc3_omap *omap) |
371 | { | |
372 | struct device_node *node = omap->dev->of_node; | |
373 | ||
374 | /* | |
375 | * Differentiate between OMAP5 and AM437x. | |
376 | * | |
377 | * For OMAP5(ES2.0) and AM437x wrapper revision is same, even | |
378 | * though there are changes in wrapper register offsets. | |
379 | * | |
380 | * Using dt compatible to differentiate AM437x. | |
381 | */ | |
382 | if (of_device_is_compatible(node, "ti,am437x-dwc3")) { | |
383 | omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; | |
384 | omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; | |
385 | omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; | |
386 | omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; | |
387 | omap->debug_offset = USBOTGSS_DEBUG_OFFSET; | |
388 | } | |
389 | } | |
390 | ||
d2f0cf89 GC |
391 | static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) |
392 | { | |
393 | u32 reg; | |
394 | struct device_node *node = omap->dev->of_node; | |
395 | int utmi_mode = 0; | |
396 | ||
22832190 | 397 | reg = dwc3_omap_read_utmi_ctrl(omap); |
d2f0cf89 GC |
398 | |
399 | of_property_read_u32(node, "utmi-mode", &utmi_mode); | |
400 | ||
401 | switch (utmi_mode) { | |
402 | case DWC3_OMAP_UTMI_MODE_SW: | |
22832190 | 403 | reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; |
d2f0cf89 GC |
404 | break; |
405 | case DWC3_OMAP_UTMI_MODE_HW: | |
22832190 | 406 | reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; |
d2f0cf89 GC |
407 | break; |
408 | default: | |
e4f75667 | 409 | dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); |
d2f0cf89 GC |
410 | } |
411 | ||
22832190 | 412 | dwc3_omap_write_utmi_ctrl(omap, reg); |
d2f0cf89 GC |
413 | } |
414 | ||
025b431b GC |
415 | static int dwc3_omap_extcon_register(struct dwc3_omap *omap) |
416 | { | |
788b0bc4 | 417 | int ret; |
025b431b GC |
418 | struct device_node *node = omap->dev->of_node; |
419 | struct extcon_dev *edev; | |
420 | ||
421 | if (of_property_read_bool(node, "extcon")) { | |
422 | edev = extcon_get_edev_by_phandle(omap->dev, 0); | |
423 | if (IS_ERR(edev)) { | |
424 | dev_vdbg(omap->dev, "couldn't get extcon device\n"); | |
425 | return -EPROBE_DEFER; | |
426 | } | |
427 | ||
428 | omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; | |
5960387a CC |
429 | ret = extcon_register_notifier(edev, EXTCON_USB, |
430 | &omap->vbus_nb); | |
025b431b GC |
431 | if (ret < 0) |
432 | dev_vdbg(omap->dev, "failed to register notifier for USB\n"); | |
433 | ||
434 | omap->id_nb.notifier_call = dwc3_omap_id_notifier; | |
5960387a CC |
435 | ret = extcon_register_notifier(edev, EXTCON_USB_HOST, |
436 | &omap->id_nb); | |
025b431b GC |
437 | if (ret < 0) |
438 | dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); | |
439 | ||
5960387a | 440 | if (extcon_get_cable_state_(edev, EXTCON_USB) == true) |
025b431b | 441 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); |
5960387a | 442 | if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) == true) |
025b431b | 443 | dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); |
5960387a CC |
444 | |
445 | omap->edev = edev; | |
025b431b GC |
446 | } |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
41ac7b3a | 451 | static int dwc3_omap_probe(struct platform_device *pdev) |
72246da4 | 452 | { |
45b3cd4a FB |
453 | struct device_node *node = pdev->dev.of_node; |
454 | ||
72246da4 FB |
455 | struct dwc3_omap *omap; |
456 | struct resource *res; | |
802ca850 | 457 | struct device *dev = &pdev->dev; |
8061ad72 | 458 | struct regulator *vbus_reg = NULL; |
72246da4 | 459 | |
b09e99ee | 460 | int ret; |
72246da4 FB |
461 | int irq; |
462 | ||
463 | u32 reg; | |
464 | ||
465 | void __iomem *base; | |
72246da4 | 466 | |
4495afcf KVA |
467 | if (!node) { |
468 | dev_err(dev, "device node not found\n"); | |
469 | return -EINVAL; | |
470 | } | |
471 | ||
802ca850 | 472 | omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); |
734d5a53 | 473 | if (!omap) |
802ca850 | 474 | return -ENOMEM; |
72246da4 FB |
475 | |
476 | platform_set_drvdata(pdev, omap); | |
477 | ||
e36a0c87 | 478 | irq = platform_get_irq(pdev, 0); |
72246da4 | 479 | if (irq < 0) { |
802ca850 CP |
480 | dev_err(dev, "missing IRQ resource\n"); |
481 | return -EINVAL; | |
72246da4 FB |
482 | } |
483 | ||
e36a0c87 | 484 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8bbcd17d FB |
485 | base = devm_ioremap_resource(dev, res); |
486 | if (IS_ERR(base)) | |
487 | return PTR_ERR(base); | |
72246da4 | 488 | |
8061ad72 KVA |
489 | if (of_property_read_bool(node, "vbus-supply")) { |
490 | vbus_reg = devm_regulator_get(dev, "vbus"); | |
491 | if (IS_ERR(vbus_reg)) { | |
492 | dev_err(dev, "vbus init failed\n"); | |
493 | return PTR_ERR(vbus_reg); | |
494 | } | |
495 | } | |
496 | ||
802ca850 | 497 | omap->dev = dev; |
72246da4 FB |
498 | omap->irq = irq; |
499 | omap->base = base; | |
8061ad72 | 500 | omap->vbus_reg = vbus_reg; |
72246da4 | 501 | |
af310e96 KVA |
502 | pm_runtime_enable(dev); |
503 | ret = pm_runtime_get_sync(dev); | |
504 | if (ret < 0) { | |
505 | dev_err(dev, "get_sync failed with err %d\n", ret); | |
45d49cb7 | 506 | goto err1; |
af310e96 KVA |
507 | } |
508 | ||
30fef1a9 | 509 | dwc3_omap_map_offset(omap); |
d2f0cf89 | 510 | dwc3_omap_set_utmi_mode(omap); |
9962444f | 511 | |
72246da4 | 512 | /* check the DMA Status */ |
ab5e59db | 513 | reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); |
12a7f17f | 514 | irq_set_status_flags(omap->irq, IRQ_NOAUTOEN); |
3f586c92 | 515 | ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt, |
12da8eae | 516 | dwc3_omap_interrupt_thread, IRQF_SHARED, |
3f586c92 | 517 | "dwc3-omap", omap); |
72246da4 | 518 | if (ret) { |
802ca850 | 519 | dev_err(dev, "failed to request IRQ #%d --> %d\n", |
72246da4 | 520 | omap->irq, ret); |
594daba1 | 521 | goto err1; |
72246da4 FB |
522 | } |
523 | ||
025b431b GC |
524 | ret = dwc3_omap_extcon_register(omap); |
525 | if (ret < 0) | |
45d49cb7 | 526 | goto err1; |
8061ad72 | 527 | |
4495afcf KVA |
528 | ret = of_platform_populate(node, NULL, NULL, dev); |
529 | if (ret) { | |
530 | dev_err(&pdev->dev, "failed to create dwc3 core\n"); | |
45d49cb7 | 531 | goto err2; |
72246da4 FB |
532 | } |
533 | ||
e2ae0692 | 534 | dwc3_omap_enable_irqs(omap); |
12a7f17f | 535 | enable_irq(omap->irq); |
72246da4 | 536 | return 0; |
594daba1 | 537 | |
45d49cb7 | 538 | err2: |
5960387a CC |
539 | extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); |
540 | extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); | |
594daba1 KVA |
541 | |
542 | err1: | |
543 | pm_runtime_put_sync(dev); | |
594daba1 KVA |
544 | pm_runtime_disable(dev); |
545 | ||
546 | return ret; | |
72246da4 FB |
547 | } |
548 | ||
fb4e98ab | 549 | static int dwc3_omap_remove(struct platform_device *pdev) |
72246da4 | 550 | { |
9a4b5dab FB |
551 | struct dwc3_omap *omap = platform_get_drvdata(pdev); |
552 | ||
5960387a CC |
553 | extcon_unregister_notifier(omap->edev, EXTCON_USB, &omap->vbus_nb); |
554 | extcon_unregister_notifier(omap->edev, EXTCON_USB_HOST, &omap->id_nb); | |
9a4b5dab | 555 | dwc3_omap_disable_irqs(omap); |
12a7f17f | 556 | disable_irq(omap->irq); |
3d0184d0 | 557 | of_platform_depopulate(omap->dev); |
af310e96 KVA |
558 | pm_runtime_put_sync(&pdev->dev); |
559 | pm_runtime_disable(&pdev->dev); | |
94c6a436 | 560 | |
72246da4 FB |
561 | return 0; |
562 | } | |
563 | ||
2c2dc89c | 564 | static const struct of_device_id of_dwc3_match[] = { |
72246da4 | 565 | { |
e36a0c87 | 566 | .compatible = "ti,dwc3" |
72246da4 | 567 | }, |
ff7307b5 GC |
568 | { |
569 | .compatible = "ti,am437x-dwc3" | |
570 | }, | |
72246da4 FB |
571 | { }, |
572 | }; | |
2c2dc89c | 573 | MODULE_DEVICE_TABLE(of, of_dwc3_match); |
72246da4 | 574 | |
19fda7cd | 575 | #ifdef CONFIG_PM_SLEEP |
f3e117f4 FB |
576 | static int dwc3_omap_suspend(struct device *dev) |
577 | { | |
578 | struct dwc3_omap *omap = dev_get_drvdata(dev); | |
579 | ||
22832190 | 580 | omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); |
7ee2566f | 581 | dwc3_omap_disable_irqs(omap); |
f3e117f4 FB |
582 | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int dwc3_omap_resume(struct device *dev) | |
587 | { | |
588 | struct dwc3_omap *omap = dev_get_drvdata(dev); | |
589 | ||
22832190 | 590 | dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); |
7ee2566f | 591 | dwc3_omap_enable_irqs(omap); |
f3e117f4 FB |
592 | |
593 | pm_runtime_disable(dev); | |
594 | pm_runtime_set_active(dev); | |
595 | pm_runtime_enable(dev); | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { | |
f3e117f4 FB |
601 | |
602 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) | |
603 | }; | |
604 | ||
605 | #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) | |
606 | #else | |
607 | #define DEV_PM_OPS NULL | |
19fda7cd | 608 | #endif /* CONFIG_PM_SLEEP */ |
f3e117f4 | 609 | |
72246da4 FB |
610 | static struct platform_driver dwc3_omap_driver = { |
611 | .probe = dwc3_omap_probe, | |
7690417d | 612 | .remove = dwc3_omap_remove, |
72246da4 FB |
613 | .driver = { |
614 | .name = "omap-dwc3", | |
2c2dc89c | 615 | .of_match_table = of_dwc3_match, |
f3e117f4 | 616 | .pm = DEV_PM_OPS, |
72246da4 FB |
617 | }, |
618 | }; | |
619 | ||
cc27c96c AL |
620 | module_platform_driver(dwc3_omap_driver); |
621 | ||
7ae4fc4d | 622 | MODULE_ALIAS("platform:omap-dwc3"); |
72246da4 | 623 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 624 | MODULE_LICENSE("GPL v2"); |
72246da4 | 625 | MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); |