[mirror_ubuntu-artful-kernel.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2  of
 * the License as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/extcon.h>
#include <linux/regulator/consumer.h>

#include <linux/usb/otg.h>

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_EOI_OFFSET			0x0008
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQ0_OFFSET			0x0004
#define USBOTGSS_IRQSTATUS_RAW_1		0x0030
#define USBOTGSS_IRQSTATUS_1			0x0034
#define USBOTGSS_IRQENABLE_SET_1		0x0038
#define USBOTGSS_IRQENABLE_CLR_1		0x003c
#define USBOTGSS_IRQSTATUS_RAW_2		0x0040
#define USBOTGSS_IRQSTATUS_2			0x0044
#define USBOTGSS_IRQENABLE_SET_2		0x0048
#define USBOTGSS_IRQENABLE_CLR_2		0x004c
#define USBOTGSS_IRQSTATUS_RAW_3		0x0050
#define USBOTGSS_IRQSTATUS_3			0x0054
#define USBOTGSS_IRQENABLE_SET_3		0x0058
#define USBOTGSS_IRQENABLE_CLR_3		0x005c
#define USBOTGSS_IRQSTATUS_EOI_MISC		0x0030
#define USBOTGSS_IRQSTATUS_RAW_MISC		0x0034
#define USBOTGSS_IRQSTATUS_MISC			0x0038
#define USBOTGSS_IRQENABLE_SET_MISC		0x003c
#define USBOTGSS_IRQENABLE_CLR_MISC		0x0040
#define USBOTGSS_IRQMISC_OFFSET			0x03fc
#define USBOTGSS_UTMI_OTG_STATUS		0x0080
#define USBOTGSS_UTMI_OTG_CTRL			0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480
#define USBOTGSS_TXFIFO_DEPTH			0x0508
#define USBOTGSS_RXFIFO_DEPTH			0x050c
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c
#define USBOTGSS_DEV_EBC_EN			0x0110
#define USBOTGSS_DEBUG_OFFSET			0x0600

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		BIT(16)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		BIT(0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		BIT(0)

/* IRQMISC BITS */
#define USBOTGSS_IRQMISC_DMADISABLECLR		BIT(17)
#define USBOTGSS_IRQMISC_OEVT			BIT(16)
#define USBOTGSS_IRQMISC_DRVVBUS_RISE		BIT(13)
#define USBOTGSS_IRQMISC_CHRGVBUS_RISE		BIT(12)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE	BIT(11)
#define USBOTGSS_IRQMISC_IDPULLUP_RISE		BIT(8)
#define USBOTGSS_IRQMISC_DRVVBUS_FALL		BIT(5)
#define USBOTGSS_IRQMISC_CHRGVBUS_FALL		BIT(4)
#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL		BIT(3)
#define USBOTGSS_IRQMISC_IDPULLUP_FALL		BIT(0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS	BIT(5)
#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS	BIT(4)
#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS	BIT(3)
#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP	BIT(0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE		BIT(31)
#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT	BIT(9)
#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
#define USBOTGSS_UTMI_OTG_CTRL_IDDIG		BIT(4)
#define USBOTGSS_UTMI_OTG_CTRL_SESSEND		BIT(3)
#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID	BIT(2)
#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID	BIT(1)

struct dwc3_omap {
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	u32			utmi_otg_ctrl;
	u32			utmi_otg_offset;
	u32			irqmisc_offset;
	u32			irq_eoi_offset;
	u32			debug_offset;
	u32			irq0_offset;

	struct extcon_dev	*edev;
	struct notifier_block	vbus_nb;
	struct notifier_block	id_nb;

	struct regulator	*vbus_reg;
};

enum omap_dwc3_vbus_id_status {
	OMAP_DWC3_ID_FLOAT,
	OMAP_DWC3_ID_GROUND,
	OMAP_DWC3_VBUS_OFF,
	OMAP_DWC3_VBUS_VALID,
};

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
							omap->utmi_otg_offset);
}

static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
					omap->utmi_otg_offset, value);

}

static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
						omap->irq0_offset);
}

static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
						omap->irq0_offset, value);

}

static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
{
	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
						omap->irqmisc_offset);
}

static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
					omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
						omap->irqmisc_offset, value);

}

static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
						omap->irqmisc_offset, value);
}

static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
{
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
						omap->irq0_offset, value);
}

static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
	enum omap_dwc3_vbus_id_status status)
{
	int	ret;
	u32	val;

	switch (status) {
	case OMAP_DWC3_ID_GROUND:
		if (omap->vbus_reg) {
			ret = regulator_enable(omap->vbus_reg);
			if (ret) {
				dev_err(omap->dev, "regulator enable failed\n");
				return;
			}
		}

		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_VBUS_VALID:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
		val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
				| USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_ID_FLOAT:
		if (omap->vbus_reg)
			regulator_disable(omap->vbus_reg);
		val = dwc3_omap_read_utmi_ctrl(omap);
		val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	case OMAP_DWC3_VBUS_OFF:
		val = dwc3_omap_read_utmi_ctrl(omap);
		val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
				| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
		val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
		dwc3_omap_write_utmi_ctrl(omap, val);
		break;

	default:
		dev_WARN(omap->dev, "invalid state\n");
	}
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;

	if (dwc3_omap_read_irqmisc_status(omap) ||
	    dwc3_omap_read_irq0_status(omap)) {
		/* mask irqs */
		dwc3_omap_disable_irqs(omap);
		return IRQ_WAKE_THREAD;
	}

	return IRQ_NONE;
}

static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	/* clear irq status flags */
	reg = dwc3_omap_read_irqmisc_status(omap);
	dwc3_omap_write_irqmisc_status(omap, reg);

	reg = dwc3_omap_read_irq0_status(omap);
	dwc3_omap_write_irq0_status(omap, reg);

	/* unmask irqs */
	dwc3_omap_enable_irqs(omap);

	return IRQ_HANDLED;
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_set(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_set(omap, reg);
}

static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* disable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_write_irq0_clr(omap, reg);

	reg = (USBOTGSS_IRQMISC_OEVT |
			USBOTGSS_IRQMISC_DRVVBUS_RISE |
			USBOTGSS_IRQMISC_CHRGVBUS_RISE |
			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
			USBOTGSS_IRQMISC_IDPULLUP_RISE |
			USBOTGSS_IRQMISC_DRVVBUS_FALL |
			USBOTGSS_IRQMISC_CHRGVBUS_FALL |
			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
			USBOTGSS_IRQMISC_IDPULLUP_FALL);

	dwc3_omap_write_irqmisc_clr(omap, reg);
}

static int dwc3_omap_id_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);

	return NOTIFY_DONE;
}

static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	unsigned long event, void *ptr)
{
	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);

	if (event)
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	else
		dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);

	return NOTIFY_DONE;
}

static void dwc3_omap_map_offset(struct dwc3_omap *omap)
{
	struct device_node	*node = omap->dev->of_node;

	/*
	 * Differentiate between OMAP5 and AM437x.
	 *
	 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	 * though there are changes in wrapper register offsets.
	 *
	 * Using dt compatible to differentiate AM437x.
	 */
	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
		omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
		omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
		omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
		omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
		omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	}
}

static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
{
	u32			reg;
	struct device_node	*node = omap->dev->of_node;
	u32			utmi_mode = 0;

	reg = dwc3_omap_read_utmi_ctrl(omap);

	of_property_read_u32(node, "utmi-mode", &utmi_mode);

	switch (utmi_mode) {
	case DWC3_OMAP_UTMI_MODE_SW:
		reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	case DWC3_OMAP_UTMI_MODE_HW:
		reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
		break;
	default:
		dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
	}

	dwc3_omap_write_utmi_ctrl(omap, reg);
}

static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
{
	int			ret;
	struct device_node	*node = omap->dev->of_node;
	struct extcon_dev	*edev;

	if (of_property_read_bool(node, "extcon")) {
		edev = extcon_get_edev_by_phandle(omap->dev, 0);
		if (IS_ERR(edev)) {
			dev_vdbg(omap->dev, "couldn't get extcon device\n");
			return -EPROBE_DEFER;
		}

		omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
		ret = devm_extcon_register_notifier(omap->dev, edev,
						EXTCON_USB, &omap->vbus_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB\n");

		omap->id_nb.notifier_call = dwc3_omap_id_notifier;
		ret = devm_extcon_register_notifier(omap->dev, edev,
						EXTCON_USB_HOST, &omap->id_nb);
		if (ret < 0)
			dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");

		if (extcon_get_state(edev, EXTCON_USB) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
		if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
			dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);

		omap->edev = edev;
	}

	return 0;
}

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;

	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;
	struct regulator	*vbus_reg = NULL;

	int			ret;
	int			irq;

	u32			reg;

	void __iomem		*base;

	if (!node) {
		dev_err(dev, "device node not found\n");
		return -EINVAL;
	}

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap)
		return -ENOMEM;

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	if (of_property_read_bool(node, "vbus-supply")) {
		vbus_reg = devm_regulator_get(dev, "vbus");
		if (IS_ERR(vbus_reg)) {
			dev_err(dev, "vbus init failed\n");
			return PTR_ERR(vbus_reg);
		}
	}

	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->vbus_reg	= vbus_reg;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "get_sync failed with err %d\n", ret);
		goto err1;
	}

	dwc3_omap_map_offset(omap);
	dwc3_omap_set_utmi_mode(omap);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);

	ret = dwc3_omap_extcon_register(omap);
	if (ret < 0)
		goto err1;

	ret = of_platform_populate(node, NULL, NULL, dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to create dwc3 core\n");
		goto err1;
	}

	ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
					dwc3_omap_interrupt_thread, IRQF_SHARED,
					"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
			omap->irq, ret);
		goto err1;
	}
	dwc3_omap_enable_irqs(omap);
	return 0;

err1:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	dwc3_omap_disable_irqs(omap);
	disable_irq(omap->irq);
	of_platform_depopulate(omap->dev);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static const struct of_device_id of_dwc3_match[] = {
	{
		.compatible =	"ti,dwc3"
	},
	{
		.compatible =	"ti,am437x-dwc3"
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);

#ifdef CONFIG_PM_SLEEP
static int dwc3_omap_suspend(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
	dwc3_omap_disable_irqs(omap);

	return 0;
}

static int dwc3_omap_resume(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
	dwc3_omap_enable_irqs(omap);

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;
}

static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {

	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
};

#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif /* CONFIG_PM_SLEEP */

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_match,
		.pm	= DEV_PM_OPS,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
5945f789 FB	9	* This program is free software: you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 of
	11	* the License as published by the Free Software Foundation.
72246da4	12	*
5945f789 FB	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
72246da4 FB	17	*/
72246da4 FB	18
a72e658b	19	#include <linux/module.h>
72246da4 FB	20	#include <linux/kernel.h>
72246da4 FB	21	#include <linux/slab.h>
12a7f17f	22	#include <linux/irq.h>
72246da4	23	#include <linux/interrupt.h>
72246da4	24	#include <linux/platform_device.h>
9962444f	25	#include <linux/platform_data/dwc3-omap.h>
af310e96	26	#include <linux/pm_runtime.h>
72246da4 FB	27	#include <linux/dma-mapping.h>
	28	#include <linux/ioport.h>
	29	#include <linux/io.h>
45b3cd4a	30	#include <linux/of.h>
b4bfe6aa	31	#include <linux/of_platform.h>
8061ad72	32	#include <linux/extcon.h>
8061ad72	33	#include <linux/regulator/consumer.h>
72246da4	34
a418cc4e	35	#include <linux/usb/otg.h>
a418cc4e	36
72246da4 FB	37	/*
	38	* All these registers belong to OMAP's Wrapper around the
	39	* DesignWare USB3 Core.
	40	*/
	41
	42	#define USBOTGSS_REVISION 0x0000
	43	#define USBOTGSS_SYSCONFIG 0x0010
	44	#define USBOTGSS_IRQ_EOI 0x0020
ff7307b5	45	#define USBOTGSS_EOI_OFFSET 0x0008
72246da4 FB	46	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	47	#define USBOTGSS_IRQSTATUS_0 0x0028
	48	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	49	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
ff7307b5	50	#define USBOTGSS_IRQ0_OFFSET 0x0004
b1fd6cb5 GC	51	#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
	52	#define USBOTGSS_IRQSTATUS_1 0x0034
	53	#define USBOTGSS_IRQENABLE_SET_1 0x0038
	54	#define USBOTGSS_IRQENABLE_CLR_1 0x003c
	55	#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
	56	#define USBOTGSS_IRQSTATUS_2 0x0044
	57	#define USBOTGSS_IRQENABLE_SET_2 0x0048
	58	#define USBOTGSS_IRQENABLE_CLR_2 0x004c
	59	#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
	60	#define USBOTGSS_IRQSTATUS_3 0x0054
	61	#define USBOTGSS_IRQENABLE_SET_3 0x0058
	62	#define USBOTGSS_IRQENABLE_CLR_3 0x005c
ff7307b5 GC	63	#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
	64	#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
	65	#define USBOTGSS_IRQSTATUS_MISC 0x0038
	66	#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
	67	#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
	68	#define USBOTGSS_IRQMISC_OFFSET 0x03fc
22832190 BL	69	#define USBOTGSS_UTMI_OTG_STATUS 0x0080
22832190 BL	70	#define USBOTGSS_UTMI_OTG_CTRL 0x0084
ff7307b5 GC	71	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	72	#define USBOTGSS_TXFIFO_DEPTH 0x0508
	73	#define USBOTGSS_RXFIFO_DEPTH 0x050c
72246da4 FB	74	#define USBOTGSS_MMRAM_OFFSET 0x0100
	75	#define USBOTGSS_FLADJ 0x0104
	76	#define USBOTGSS_DEBUG_CFG 0x0108
	77	#define USBOTGSS_DEBUG_DATA 0x010c
ff7307b5 GC	78	#define USBOTGSS_DEV_EBC_EN 0x0110
ff7307b5 GC	79	#define USBOTGSS_DEBUG_OFFSET 0x0600
72246da4 FB	80
72246da4 FB	81	/* SYSCONFIG REGISTER */
ff3f0789	82	#define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16)
4b5faa7a	83
72246da4	84	/* IRQ_EOI REGISTER */
ff3f0789	85	#define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0)
72246da4 FB	86
72246da4 FB	87	/* IRQS0 BITS */
ff3f0789	88	#define USBOTGSS_IRQO_COREIRQ_ST BIT(0)
72246da4	89
b1fd6cb5	90	/* IRQMISC BITS */
ff3f0789 RQ	91	#define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17)
	92	#define USBOTGSS_IRQMISC_OEVT BIT(16)
	93	#define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13)
	94	#define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12)
	95	#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11)
	96	#define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8)
	97	#define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5)
	98	#define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4)
	99	#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3)
	100	#define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0)
72246da4	101
72246da4	102	/* UTMI_OTG_STATUS REGISTER */
ff3f0789 RQ	103	#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5)
	104	#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4)
	105	#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3)
	106	#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0)
22832190 BL	107
22832190 BL	108	/* UTMI_OTG_CTRL REGISTER */
ff3f0789 RQ	109	#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31)
	110	#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9)
	111	#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
	112	#define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4)
	113	#define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3)
	114	#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
	115	#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
72246da4 FB	116
72246da4 FB	117	struct dwc3_omap {
72246da4 FB	118	struct device *dev;
	119
	120	int irq;
	121	void __iomem *base;
	122
22832190	123	u32 utmi_otg_ctrl;
1e2a064c GC	124	u32 utmi_otg_offset;
	125	u32 irqmisc_offset;
	126	u32 irq_eoi_offset;
	127	u32 debug_offset;
	128	u32 irq0_offset;
f3e117f4	129
5960387a	130	struct extcon_dev *edev;
8061ad72 KVA	131	struct notifier_block vbus_nb;
	132	struct notifier_block id_nb;
	133
	134	struct regulator *vbus_reg;
72246da4 FB	135	};
72246da4 FB	136
8061ad72 KVA	137	enum omap_dwc3_vbus_id_status {
	138	OMAP_DWC3_ID_FLOAT,
	139	OMAP_DWC3_ID_GROUND,
	140	OMAP_DWC3_VBUS_OFF,
	141	OMAP_DWC3_VBUS_VALID,
	142	};
7e41bba9	143
ab5e59db IS	144	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	145	{
	146	return readl(base + offset);
	147	}
	148
	149	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	150	{
	151	writel(value, base + offset);
	152	}
	153
22832190	154	static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
b1fd6cb5	155	{
22832190	156	return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	157	omap->utmi_otg_offset);
	158	}
	159
22832190	160	static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
b1fd6cb5	161	{
22832190	162	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
b1fd6cb5 GC	163	omap->utmi_otg_offset, value);
	164
	165	}
	166
	167	static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
	168	{
3f586c92	169	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
b1fd6cb5 GC	170	omap->irq0_offset);
	171	}
	172
	173	static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
	174	{
	175	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
	176	omap->irq0_offset, value);
	177
	178	}
	179
	180	static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
	181	{
3f586c92	182	return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
b1fd6cb5 GC	183	omap->irqmisc_offset);
	184	}
	185
	186	static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
	187	{
	188	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
	189	omap->irqmisc_offset, value);
	190
	191	}
	192
	193	static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
	194	{
	195	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
	196	omap->irqmisc_offset, value);
	197
	198	}
	199
	200	static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
	201	{
	202	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
	203	omap->irq0_offset, value);
	204	}
	205
96e5d312 GC	206	static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
	207	{
	208	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
	209	omap->irqmisc_offset, value);
	210	}
	211
	212	static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
	213	{
	214	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
	215	omap->irq0_offset, value);
	216	}
	217
8061ad72 KVA	218	static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
8061ad72 KVA	219	enum omap_dwc3_vbus_id_status status)
7e41bba9	220	{
8061ad72 KVA	221	int ret;
8061ad72 KVA	222	u32 val;
2ba7943a	223
7e41bba9 KVA	224	switch (status) {
7e41bba9 KVA	225	case OMAP_DWC3_ID_GROUND:
8061ad72 KVA	226	if (omap->vbus_reg) {
	227	ret = regulator_enable(omap->vbus_reg);
	228	if (ret) {
e4f75667	229	dev_err(omap->dev, "regulator enable failed\n");
8061ad72 KVA	230	return;
	231	}
	232	}
	233
22832190	234	val = dwc3_omap_read_utmi_ctrl(omap);
d2728fb3	235	val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
22832190	236	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	237	break;
	238
	239	case OMAP_DWC3_VBUS_VALID:
22832190 BL	240	val = dwc3_omap_read_utmi_ctrl(omap);
22832190 BL	241	val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
d2728fb3	242	val \|= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
9ab330bf	243	\| USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
22832190	244	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	245	break;
	246
	247	case OMAP_DWC3_ID_FLOAT:
8061ad72 KVA	248	if (omap->vbus_reg)
8061ad72 KVA	249	regulator_disable(omap->vbus_reg);
d2728fb3 RQ	250	val = dwc3_omap_read_utmi_ctrl(omap);
	251	val \|= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
	252	dwc3_omap_write_utmi_ctrl(omap, val);
0913750f	253	break;
8061ad72	254
7e41bba9	255	case OMAP_DWC3_VBUS_OFF:
22832190 BL	256	val = dwc3_omap_read_utmi_ctrl(omap);
22832190 BL	257	val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
9ab330bf	258	\| USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
d2728fb3	259	val \|= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
22832190	260	dwc3_omap_write_utmi_ctrl(omap, val);
7e41bba9 KVA	261	break;
	262
	263	default:
e4f75667	264	dev_WARN(omap->dev, "invalid state\n");
7e41bba9	265	}
7e41bba9	266	}
7e41bba9	267
3f586c92 RQ	268	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
	269	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
	270
72246da4	271	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
3f586c92 RQ	272	{
	273	struct dwc3_omap *omap = _omap;
	274
	275	if (dwc3_omap_read_irqmisc_status(omap) \|\|
	276	dwc3_omap_read_irq0_status(omap)) {
	277	/* mask irqs */
	278	dwc3_omap_disable_irqs(omap);
	279	return IRQ_WAKE_THREAD;
	280	}
	281
	282	return IRQ_NONE;
	283	}
	284
	285	static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
72246da4 FB	286	{
	287	struct dwc3_omap *omap = _omap;
	288	u32 reg;
72246da4	289
3f586c92	290	/* clear irq status flags */
b1fd6cb5	291	reg = dwc3_omap_read_irqmisc_status(omap);
b1fd6cb5 GC	292	dwc3_omap_write_irqmisc_status(omap, reg);
	293
	294	reg = dwc3_omap_read_irq0_status(omap);
b1fd6cb5	295	dwc3_omap_write_irq0_status(omap, reg);
72246da4	296
3f586c92 RQ	297	/* unmask irqs */
	298	dwc3_omap_enable_irqs(omap);
	299
72246da4 FB	300	return IRQ_HANDLED;
	301	}
	302
9a4b5dab FB	303	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
	304	{
	305	u32 reg;
	306
	307	/* enable all IRQs */
	308	reg = USBOTGSS_IRQO_COREIRQ_ST;
b1fd6cb5 GC	309	dwc3_omap_write_irq0_set(omap, reg);
	310
	311	reg = (USBOTGSS_IRQMISC_OEVT \|
	312	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	313	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	314	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	315	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	316	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	317	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	318	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	319	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	320
	321	dwc3_omap_write_irqmisc_set(omap, reg);
9a4b5dab FB	322	}
	323
	324	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
	325	{
96e5d312 GC	326	u32 reg;
96e5d312 GC	327
9a4b5dab	328	/* disable all IRQs */
96e5d312 GC	329	reg = USBOTGSS_IRQO_COREIRQ_ST;
	330	dwc3_omap_write_irq0_clr(omap, reg);
	331
	332	reg = (USBOTGSS_IRQMISC_OEVT \|
	333	USBOTGSS_IRQMISC_DRVVBUS_RISE \|
	334	USBOTGSS_IRQMISC_CHRGVBUS_RISE \|
	335	USBOTGSS_IRQMISC_DISCHRGVBUS_RISE \|
	336	USBOTGSS_IRQMISC_IDPULLUP_RISE \|
	337	USBOTGSS_IRQMISC_DRVVBUS_FALL \|
	338	USBOTGSS_IRQMISC_CHRGVBUS_FALL \|
	339	USBOTGSS_IRQMISC_DISCHRGVBUS_FALL \|
	340	USBOTGSS_IRQMISC_IDPULLUP_FALL);
	341
	342	dwc3_omap_write_irqmisc_clr(omap, reg);
9a4b5dab FB	343	}
9a4b5dab FB	344
8061ad72 KVA	345	static int dwc3_omap_id_notifier(struct notifier_block *nb,
	346	unsigned long event, void *ptr)
	347	{
	348	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
	349
	350	if (event)
	351	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
	352	else
	353	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
	354
	355	return NOTIFY_DONE;
	356	}
	357
	358	static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
	359	unsigned long event, void *ptr)
	360	{
	361	struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
	362
	363	if (event)
	364	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
	365	else
	366	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
	367
	368	return NOTIFY_DONE;
	369	}
	370
30fef1a9 GC	371	static void dwc3_omap_map_offset(struct dwc3_omap *omap)
	372	{
	373	struct device_node *node = omap->dev->of_node;
	374
	375	/*
	376	* Differentiate between OMAP5 and AM437x.
	377	*
	378	* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
	379	* though there are changes in wrapper register offsets.
	380	*
	381	* Using dt compatible to differentiate AM437x.
	382	*/
	383	if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
	384	omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
	385	omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
	386	omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
	387	omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
	388	omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
	389	}
	390	}
	391
d2f0cf89 GC	392	static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
	393	{
	394	u32 reg;
	395	struct device_node *node = omap->dev->of_node;
73561128	396	u32 utmi_mode = 0;
d2f0cf89	397
22832190	398	reg = dwc3_omap_read_utmi_ctrl(omap);
d2f0cf89 GC	399
	400	of_property_read_u32(node, "utmi-mode", &utmi_mode);
	401
	402	switch (utmi_mode) {
	403	case DWC3_OMAP_UTMI_MODE_SW:
22832190	404	reg \|= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	405	break;
d2f0cf89 GC	406	case DWC3_OMAP_UTMI_MODE_HW:
22832190	407	reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
d2f0cf89 GC	408	break;
d2f0cf89 GC	409	default:
e4f75667	410	dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
d2f0cf89 GC	411	}
d2f0cf89 GC	412
22832190	413	dwc3_omap_write_utmi_ctrl(omap, reg);
d2f0cf89 GC	414	}
d2f0cf89 GC	415
025b431b GC	416	static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
025b431b GC	417	{
788b0bc4	418	int ret;
025b431b GC	419	struct device_node *node = omap->dev->of_node;
	420	struct extcon_dev *edev;
	421
	422	if (of_property_read_bool(node, "extcon")) {
	423	edev = extcon_get_edev_by_phandle(omap->dev, 0);
	424	if (IS_ERR(edev)) {
	425	dev_vdbg(omap->dev, "couldn't get extcon device\n");
	426	return -EPROBE_DEFER;
	427	}
	428
	429	omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
c773bb0b CC	430	ret = devm_extcon_register_notifier(omap->dev, edev,
c773bb0b CC	431	EXTCON_USB, &omap->vbus_nb);
025b431b GC	432	if (ret < 0)
	433	dev_vdbg(omap->dev, "failed to register notifier for USB\n");
	434
	435	omap->id_nb.notifier_call = dwc3_omap_id_notifier;
c773bb0b CC	436	ret = devm_extcon_register_notifier(omap->dev, edev,
c773bb0b CC	437	EXTCON_USB_HOST, &omap->id_nb);
025b431b GC	438	if (ret < 0)
	439	dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
	440
c773bb0b	441	if (extcon_get_state(edev, EXTCON_USB) == true)
025b431b	442	dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
c773bb0b	443	if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
025b431b	444	dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
5960387a CC	445
5960387a CC	446	omap->edev = edev;
025b431b GC	447	}
	448
	449	return 0;
	450	}
	451
41ac7b3a	452	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	453	{
45b3cd4a FB	454	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	455
72246da4 FB	456	struct dwc3_omap *omap;
72246da4 FB	457	struct resource *res;
802ca850	458	struct device *dev = &pdev->dev;
8061ad72	459	struct regulator *vbus_reg = NULL;
72246da4	460
b09e99ee	461	int ret;
72246da4 FB	462	int irq;
	463
	464	u32 reg;
	465
	466	void __iomem *base;
72246da4	467
4495afcf KVA	468	if (!node) {
	469	dev_err(dev, "device node not found\n");
	470	return -EINVAL;
	471	}
	472
802ca850	473	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
734d5a53	474	if (!omap)
802ca850	475	return -ENOMEM;
72246da4 FB	476
	477	platform_set_drvdata(pdev, omap);
	478
e36a0c87	479	irq = platform_get_irq(pdev, 0);
72246da4	480	if (irq < 0) {
802ca850 CP	481	dev_err(dev, "missing IRQ resource\n");
802ca850 CP	482	return -EINVAL;
72246da4 FB	483	}
72246da4 FB	484
e36a0c87	485	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8bbcd17d FB	486	base = devm_ioremap_resource(dev, res);
	487	if (IS_ERR(base))
	488	return PTR_ERR(base);
72246da4	489
8061ad72 KVA	490	if (of_property_read_bool(node, "vbus-supply")) {
	491	vbus_reg = devm_regulator_get(dev, "vbus");
	492	if (IS_ERR(vbus_reg)) {
	493	dev_err(dev, "vbus init failed\n");
	494	return PTR_ERR(vbus_reg);
	495	}
	496	}
	497
802ca850	498	omap->dev = dev;
72246da4 FB	499	omap->irq = irq;
72246da4 FB	500	omap->base = base;
8061ad72	501	omap->vbus_reg = vbus_reg;
72246da4	502
af310e96 KVA	503	pm_runtime_enable(dev);
	504	ret = pm_runtime_get_sync(dev);
	505	if (ret < 0) {
	506	dev_err(dev, "get_sync failed with err %d\n", ret);
45d49cb7	507	goto err1;
af310e96 KVA	508	}
af310e96 KVA	509
30fef1a9	510	dwc3_omap_map_offset(omap);
d2f0cf89	511	dwc3_omap_set_utmi_mode(omap);
9962444f	512
72246da4	513	/* check the DMA Status */
ab5e59db	514	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4	515
025b431b GC	516	ret = dwc3_omap_extcon_register(omap);
025b431b GC	517	if (ret < 0)
45d49cb7	518	goto err1;
8061ad72	519
4495afcf KVA	520	ret = of_platform_populate(node, NULL, NULL, dev);
	521	if (ret) {
	522	dev_err(&pdev->dev, "failed to create dwc3 core\n");
c773bb0b	523	goto err1;
72246da4 FB	524	}
72246da4 FB	525
ee249b45 V	526	ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
	527	dwc3_omap_interrupt_thread, IRQF_SHARED,
	528	"dwc3-omap", omap);
	529	if (ret) {
	530	dev_err(dev, "failed to request IRQ #%d --> %d\n",
	531	omap->irq, ret);
	532	goto err1;
	533	}
e2ae0692	534	dwc3_omap_enable_irqs(omap);
72246da4	535	return 0;
594daba1	536
594daba1 KVA	537	err1:
594daba1 KVA	538	pm_runtime_put_sync(dev);
594daba1 KVA	539	pm_runtime_disable(dev);
	540
	541	return ret;
72246da4 FB	542	}
72246da4 FB	543
fb4e98ab	544	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4	545	{
9a4b5dab FB	546	struct dwc3_omap *omap = platform_get_drvdata(pdev);
	547
	548	dwc3_omap_disable_irqs(omap);
12a7f17f	549	disable_irq(omap->irq);
3d0184d0	550	of_platform_depopulate(omap->dev);
af310e96 KVA	551	pm_runtime_put_sync(&pdev->dev);
af310e96 KVA	552	pm_runtime_disable(&pdev->dev);
94c6a436	553
72246da4 FB	554	return 0;
	555	}
	556
2c2dc89c	557	static const struct of_device_id of_dwc3_match[] = {
72246da4	558	{
e36a0c87	559	.compatible = "ti,dwc3"
72246da4	560	},
ff7307b5 GC	561	{
	562	.compatible = "ti,am437x-dwc3"
	563	},
72246da4 FB	564	{ },
72246da4 FB	565	};
2c2dc89c	566	MODULE_DEVICE_TABLE(of, of_dwc3_match);
72246da4	567
19fda7cd	568	#ifdef CONFIG_PM_SLEEP
f3e117f4 FB	569	static int dwc3_omap_suspend(struct device *dev)
	570	{
	571	struct dwc3_omap *omap = dev_get_drvdata(dev);
	572
22832190	573	omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
7ee2566f	574	dwc3_omap_disable_irqs(omap);
f3e117f4 FB	575
	576	return 0;
	577	}
	578
	579	static int dwc3_omap_resume(struct device *dev)
	580	{
	581	struct dwc3_omap *omap = dev_get_drvdata(dev);
	582
22832190	583	dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
7ee2566f	584	dwc3_omap_enable_irqs(omap);
f3e117f4 FB	585
	586	pm_runtime_disable(dev);
	587	pm_runtime_set_active(dev);
	588	pm_runtime_enable(dev);
	589
	590	return 0;
	591	}
	592
	593	static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
f3e117f4 FB	594
	595	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
	596	};
	597
	598	#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
	599	#else
	600	#define DEV_PM_OPS NULL
19fda7cd	601	#endif /* CONFIG_PM_SLEEP */
f3e117f4	602
72246da4 FB	603	static struct platform_driver dwc3_omap_driver = {
72246da4 FB	604	.probe = dwc3_omap_probe,
7690417d	605	.remove = dwc3_omap_remove,
72246da4 FB	606	.driver = {
72246da4 FB	607	.name = "omap-dwc3",
2c2dc89c	608	.of_match_table = of_dwc3_match,
f3e117f4	609	.pm = DEV_PM_OPS,
72246da4 FB	610	},
	611	};
	612
cc27c96c AL	613	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	614
7ae4fc4d	615	MODULE_ALIAS("platform:omap-dwc3");
72246da4	616	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
5945f789	617	MODULE_LICENSE("GPL v2");
72246da4	618	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");