[mirror_ubuntu-bionic-kernel.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/usb/dwc3-omap.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>

#include <linux/usb/otg.h>

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQSTATUS_RAW_1		0x0034
#define USBOTGSS_IRQSTATUS_1			0x0038
#define USBOTGSS_IRQENABLE_SET_1		0x003c
#define USBOTGSS_IRQENABLE_CLR_1		0x0040
#define USBOTGSS_UTMI_OTG_CTRL			0x0080
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)

/* IRQ1 BITS */
#define USBOTGSS_IRQ1_DMADISABLECLR		(1 << 17)
#define USBOTGSS_IRQ1_OEVT			(1 << 16)
#define USBOTGSS_IRQ1_DRVVBUS_RISE		(1 << 13)
#define USBOTGSS_IRQ1_CHRGVBUS_RISE		(1 << 12)
#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE		(1 << 11)
#define USBOTGSS_IRQ1_IDPULLUP_RISE		(1 << 8)
#define USBOTGSS_IRQ1_DRVVBUS_FALL		(1 << 5)
#define USBOTGSS_IRQ1_CHRGVBUS_FALL		(1 << 4)
#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL		(1 << 3)
#define USBOTGSS_IRQ1_IDPULLUP_FALL		(1 << 0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)
#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS	(1 << 3)
#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP		(1 << 0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	(1 << 31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	(1 << 9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		(1 << 4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	(1 << 3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	(1 << 2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	(1 << 1)

struct dwc3_omap {
	/* device lock */
	spinlock_t		lock;

	struct device		*dev;

	int			irq;
	void __iomem		*base;

	u32			utmi_otg_status;

	u32			dma_status:1;
};

static struct dwc3_omap		*_omap;

static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
{
	return readl(base + offset);
}

static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
{
	writel(value, base + offset);
}

int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
{
	u32			val;
	struct dwc3_omap	*omap = _omap;

	if (!omap)
		return -EPROBE_DEFER;

	switch (status) {
	case OMAP_DWC3_ID_GROUND:
		dev_dbg(omap->dev, "ID GND\n");

		val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
		val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
		val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
		dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
		break;

	case OMAP_DWC3_VBUS_VALID:
		dev_dbg(omap->dev, "VBUS Connect\n");

		val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
		val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
		val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
		dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
		break;

	case OMAP_DWC3_ID_FLOAT:
	case OMAP_DWC3_VBUS_OFF:
		dev_dbg(omap->dev, "VBUS Disconnect\n");

		val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
		val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
				| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
				| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
		val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
				| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
		dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
		break;

	default:
		dev_dbg(omap->dev, "ID float\n");
	}

	return 0;
}
EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	spin_lock(&omap->lock);

	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);

	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
		dev_dbg(omap->dev, "DMA Disable was Cleared\n");
		omap->dma_status = false;
	}

	if (reg & USBOTGSS_IRQ1_OEVT)
		dev_dbg(omap->dev, "OTG Event\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
		dev_dbg(omap->dev, "DRVVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
		dev_dbg(omap->dev, "CHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
		dev_dbg(omap->dev, "IDPULLUP Rise\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
		dev_dbg(omap->dev, "DRVVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
		dev_dbg(omap->dev, "CHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
		dev_dbg(omap->dev, "IDPULLUP Fall\n");

	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);

	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);

	spin_unlock(&omap->lock);

	return IRQ_HANDLED;
}

static int dwc3_omap_remove_core(struct device *dev, void *c)
{
	struct platform_device *pdev = to_platform_device(dev);

	platform_device_unregister(pdev);

	return 0;
}

static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
{
	u32			reg;

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);

	reg = (USBOTGSS_IRQ1_OEVT |
			USBOTGSS_IRQ1_DRVVBUS_RISE |
			USBOTGSS_IRQ1_CHRGVBUS_RISE |
			USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
			USBOTGSS_IRQ1_IDPULLUP_RISE |
			USBOTGSS_IRQ1_DRVVBUS_FALL |
			USBOTGSS_IRQ1_CHRGVBUS_FALL |
			USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
			USBOTGSS_IRQ1_IDPULLUP_FALL);

	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
}

static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
{
	/* disable all IRQs */
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
}

static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);

static int dwc3_omap_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;

	struct dwc3_omap	*omap;
	struct resource		*res;
	struct device		*dev = &pdev->dev;

	int			ret = -ENOMEM;
	int			irq;

	int			utmi_mode = 0;

	u32			reg;

	void __iomem		*base;

	if (!node) {
		dev_err(dev, "device node not found\n");
		return -EINVAL;
	}

	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
	if (!omap) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing memory base resource\n");
		return -EINVAL;
	}

	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!base) {
		dev_err(dev, "ioremap failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&omap->lock);

	omap->dev	= dev;
	omap->irq	= irq;
	omap->base	= base;
	dev->dma_mask	= &dwc3_omap_dma_mask;

	/*
	 * REVISIT if we ever have two instances of the wrapper, we will be
	 * in big trouble
	 */
	_omap	= omap;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "get_sync failed with err %d\n", ret);
		return ret;
	}

	reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);

	of_property_read_u32(node, "utmi-mode", &utmi_mode);

	switch (utmi_mode) {
	case DWC3_OMAP_UTMI_MODE_SW:
		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
		break;
	case DWC3_OMAP_UTMI_MODE_HW:
		reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
		break;
	default:
		dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
	}

	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);

	/* check the DMA Status */
	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
			"dwc3-omap", omap);
	if (ret) {
		dev_err(dev, "failed to request IRQ #%d --> %d\n",
				omap->irq, ret);
		return ret;
	}

	dwc3_omap_enable_irqs(omap);

	ret = of_platform_populate(node, NULL, NULL, dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to create dwc3 core\n");
		return ret;
	}

	return 0;
}

static int dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	dwc3_omap_disable_irqs(omap);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);

	return 0;
}

static const struct of_device_id of_dwc3_match[] = {
	{
		.compatible =	"ti,dwc3"
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_match);

#ifdef CONFIG_PM
static int dwc3_omap_prepare(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_disable_irqs(omap);

	return 0;
}

static void dwc3_omap_complete(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_enable_irqs(omap);
}

static int dwc3_omap_suspend(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	omap->utmi_otg_status = dwc3_omap_readl(omap->base,
			USBOTGSS_UTMI_OTG_STATUS);

	return 0;
}

static int dwc3_omap_resume(struct device *dev)
{
	struct dwc3_omap	*omap = dev_get_drvdata(dev);

	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
			omap->utmi_otg_status);

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;
}

static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
	.prepare	= dwc3_omap_prepare,
	.complete	= dwc3_omap_complete,

	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
};

#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
#else
#define DEV_PM_OPS	NULL
#endif /* CONFIG_PM */

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= dwc3_omap_remove,
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_match,
		.pm	= DEV_PM_OPS,
	},
};

module_platform_driver(dwc3_omap_driver);

MODULE_ALIAS("platform:omap-dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/spinlock.h>
	44	#include <linux/platform_device.h>
9962444f	45	#include <linux/platform_data/dwc3-omap.h>
7e41bba9	46	#include <linux/usb/dwc3-omap.h>
af310e96	47	#include <linux/pm_runtime.h>
72246da4 FB	48	#include <linux/dma-mapping.h>
	49	#include <linux/ioport.h>
	50	#include <linux/io.h>
45b3cd4a	51	#include <linux/of.h>
b4bfe6aa	52	#include <linux/of_platform.h>
72246da4	53
a418cc4e	54	#include <linux/usb/otg.h>
a418cc4e	55
72246da4 FB	56	/*
	57	* All these registers belong to OMAP's Wrapper around the
	58	* DesignWare USB3 Core.
	59	*/
	60
	61	#define USBOTGSS_REVISION 0x0000
	62	#define USBOTGSS_SYSCONFIG 0x0010
	63	#define USBOTGSS_IRQ_EOI 0x0020
	64	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	65	#define USBOTGSS_IRQSTATUS_0 0x0028
	66	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	67	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
	68	#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
	69	#define USBOTGSS_IRQSTATUS_1 0x0038
	70	#define USBOTGSS_IRQENABLE_SET_1 0x003c
	71	#define USBOTGSS_IRQENABLE_CLR_1 0x0040
	72	#define USBOTGSS_UTMI_OTG_CTRL 0x0080
	73	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
	74	#define USBOTGSS_MMRAM_OFFSET 0x0100
	75	#define USBOTGSS_FLADJ 0x0104
	76	#define USBOTGSS_DEBUG_CFG 0x0108
	77	#define USBOTGSS_DEBUG_DATA 0x010c
	78
	79	/* SYSCONFIG REGISTER */
	80	#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
4b5faa7a	81
72246da4 FB	82	/* IRQ_EOI REGISTER */
	83	#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
	84
	85	/* IRQS0 BITS */
	86	#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
	87
	88	/* IRQ1 BITS */
	89	#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
	90	#define USBOTGSS_IRQ1_OEVT (1 << 16)
	91	#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
	92	#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
	93	#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
	94	#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
	95	#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
	96	#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
	97	#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
	98	#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
	99
	100	/* UTMI_OTG_CTRL REGISTER */
	101	#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
	102	#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
	103	#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
	104	#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
	105
	106	/* UTMI_OTG_STATUS REGISTER */
	107	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
	108	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
	109	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
	110	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
	111	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
	112	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
	113	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
	114
	115	struct dwc3_omap {
	116	/* device lock */
	117	spinlock_t lock;
	118
72246da4 FB	119	struct device *dev;
	120
	121	int irq;
	122	void __iomem *base;
	123
f3e117f4 FB	124	u32 utmi_otg_status;
f3e117f4 FB	125
72246da4 FB	126	u32 dma_status:1;
	127	};
	128
a33bb212	129	static struct dwc3_omap *_omap;
7e41bba9	130
ab5e59db IS	131	static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
	132	{
	133	return readl(base + offset);
	134	}
	135
	136	static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
	137	{
	138	writel(value, base + offset);
	139	}
	140
2ba7943a	141	int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
7e41bba9 KVA	142	{
	143	u32 val;
	144	struct dwc3_omap *omap = _omap;
	145
2ba7943a KVA	146	if (!omap)
	147	return -EPROBE_DEFER;
	148
7e41bba9 KVA	149	switch (status) {
	150	case OMAP_DWC3_ID_GROUND:
	151	dev_dbg(omap->dev, "ID GND\n");
	152
	153	val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
	154	val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
	155	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	156	\| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
	157	val \|= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	158	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
	159	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
	160	break;
	161
	162	case OMAP_DWC3_VBUS_VALID:
	163	dev_dbg(omap->dev, "VBUS Connect\n");
	164
	165	val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
	166	val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
	167	val \|= USBOTGSS_UTMI_OTG_STATUS_IDDIG
	168	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	169	\| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	170	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
	171	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
	172	break;
	173
	174	case OMAP_DWC3_ID_FLOAT:
	175	case OMAP_DWC3_VBUS_OFF:
	176	dev_dbg(omap->dev, "VBUS Disconnect\n");
	177
	178	val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
	179	val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
	180	\| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
	181	\| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
	182	val \|= USBOTGSS_UTMI_OTG_STATUS_SESSEND
	183	\| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
	184	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
	185	break;
	186
	187	default:
	188	dev_dbg(omap->dev, "ID float\n");
	189	}
	190
2ba7943a	191	return 0;
7e41bba9 KVA	192	}
	193	EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
	194
72246da4 FB	195	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
	196	{
	197	struct dwc3_omap *omap = _omap;
	198	u32 reg;
72246da4 FB	199
	200	spin_lock(&omap->lock);
	201
ab5e59db	202	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
72246da4 FB	203
72246da4 FB	204	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
ccba3bca	205	dev_dbg(omap->dev, "DMA Disable was Cleared\n");
72246da4 FB	206	omap->dma_status = false;
	207	}
	208
	209	if (reg & USBOTGSS_IRQ1_OEVT)
ccba3bca	210	dev_dbg(omap->dev, "OTG Event\n");
72246da4	211
42077b0a	212	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
ccba3bca	213	dev_dbg(omap->dev, "DRVVBUS Rise\n");
72246da4	214
42077b0a	215	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
ccba3bca	216	dev_dbg(omap->dev, "CHRGVBUS Rise\n");
72246da4	217
42077b0a	218	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
ccba3bca	219	dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
72246da4	220
42077b0a	221	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
ccba3bca	222	dev_dbg(omap->dev, "IDPULLUP Rise\n");
72246da4	223
42077b0a	224	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
ccba3bca	225	dev_dbg(omap->dev, "DRVVBUS Fall\n");
72246da4	226
42077b0a	227	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
ccba3bca	228	dev_dbg(omap->dev, "CHRGVBUS Fall\n");
72246da4	229
42077b0a	230	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
ccba3bca	231	dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
72246da4	232
42077b0a	233	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
ccba3bca	234	dev_dbg(omap->dev, "IDPULLUP Fall\n");
72246da4	235
ab5e59db	236	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
42077b0a	237
ab5e59db IS	238	reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
ab5e59db IS	239	dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
72246da4 FB	240
	241	spin_unlock(&omap->lock);
	242
	243	return IRQ_HANDLED;
	244	}
	245
94c6a436 KVA	246	static int dwc3_omap_remove_core(struct device dev, void c)
	247	{
	248	struct platform_device *pdev = to_platform_device(dev);
	249
	250	platform_device_unregister(pdev);
	251
	252	return 0;
	253	}
	254
9a4b5dab FB	255	static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
	256	{
	257	u32 reg;
	258
	259	/* enable all IRQs */
	260	reg = USBOTGSS_IRQO_COREIRQ_ST;
	261	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
	262
	263	reg = (USBOTGSS_IRQ1_OEVT \|
	264	USBOTGSS_IRQ1_DRVVBUS_RISE \|
	265	USBOTGSS_IRQ1_CHRGVBUS_RISE \|
	266	USBOTGSS_IRQ1_DISCHRGVBUS_RISE \|
	267	USBOTGSS_IRQ1_IDPULLUP_RISE \|
	268	USBOTGSS_IRQ1_DRVVBUS_FALL \|
	269	USBOTGSS_IRQ1_CHRGVBUS_FALL \|
	270	USBOTGSS_IRQ1_DISCHRGVBUS_FALL \|
	271	USBOTGSS_IRQ1_IDPULLUP_FALL);
	272
	273	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
	274	}
	275
	276	static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
	277	{
	278	/* disable all IRQs */
	279	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
	280	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
	281	}
	282
ddff14f1 KVA	283	static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
ddff14f1 KVA	284
41ac7b3a	285	static int dwc3_omap_probe(struct platform_device *pdev)
72246da4	286	{
45b3cd4a FB	287	struct device_node *node = pdev->dev.of_node;
45b3cd4a FB	288
72246da4 FB	289	struct dwc3_omap *omap;
72246da4 FB	290	struct resource *res;
802ca850	291	struct device *dev = &pdev->dev;
72246da4 FB	292
	293	int ret = -ENOMEM;
	294	int irq;
	295
e36a0c87 KVA	296	int utmi_mode = 0;
e36a0c87 KVA	297
72246da4 FB	298	u32 reg;
	299
	300	void __iomem *base;
72246da4	301
4495afcf KVA	302	if (!node) {
	303	dev_err(dev, "device node not found\n");
	304	return -EINVAL;
	305	}
	306
802ca850	307	omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
72246da4	308	if (!omap) {
802ca850 CP	309	dev_err(dev, "not enough memory\n");
802ca850 CP	310	return -ENOMEM;
72246da4 FB	311	}
	312
	313	platform_set_drvdata(pdev, omap);
	314
e36a0c87	315	irq = platform_get_irq(pdev, 0);
72246da4	316	if (irq < 0) {
802ca850 CP	317	dev_err(dev, "missing IRQ resource\n");
802ca850 CP	318	return -EINVAL;
72246da4 FB	319	}
72246da4 FB	320
e36a0c87	321	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
72246da4	322	if (!res) {
802ca850 CP	323	dev_err(dev, "missing memory base resource\n");
802ca850 CP	324	return -EINVAL;
72246da4 FB	325	}
72246da4 FB	326
802ca850	327	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
72246da4	328	if (!base) {
802ca850 CP	329	dev_err(dev, "ioremap failed\n");
802ca850 CP	330	return -ENOMEM;
72246da4 FB	331	}
72246da4 FB	332
72246da4	333	spin_lock_init(&omap->lock);
72246da4	334
802ca850	335	omap->dev = dev;
72246da4 FB	336	omap->irq = irq;
72246da4 FB	337	omap->base = base;
ddff14f1	338	dev->dma_mask = &dwc3_omap_dma_mask;
72246da4	339
7e41bba9 KVA	340	/*
	341	* REVISIT if we ever have two instances of the wrapper, we will be
	342	* in big trouble
	343	*/
	344	_omap = omap;
	345
af310e96 KVA	346	pm_runtime_enable(dev);
	347	ret = pm_runtime_get_sync(dev);
	348	if (ret < 0) {
	349	dev_err(dev, "get_sync failed with err %d\n", ret);
	350	return ret;
	351	}
	352
ab5e59db	353	reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
9962444f	354
4495afcf	355	of_property_read_u32(node, "utmi-mode", &utmi_mode);
e36a0c87 KVA	356
	357	switch (utmi_mode) {
	358	case DWC3_OMAP_UTMI_MODE_SW:
	359	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	360	break;
	361	case DWC3_OMAP_UTMI_MODE_HW:
	362	reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	363	break;
	364	default:
	365	dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
9962444f FB	366	}
9962444f FB	367
ab5e59db	368	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
9962444f	369
72246da4	370	/* check the DMA Status */
ab5e59db	371	reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
72246da4 FB	372	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
72246da4 FB	373
802ca850	374	ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
dd17a6b2	375	"dwc3-omap", omap);
72246da4	376	if (ret) {
802ca850	377	dev_err(dev, "failed to request IRQ #%d --> %d\n",
72246da4	378	omap->irq, ret);
b4bfe6aa	379	return ret;
72246da4 FB	380	}
72246da4 FB	381
9a4b5dab	382	dwc3_omap_enable_irqs(omap);
72246da4	383
4495afcf KVA	384	ret = of_platform_populate(node, NULL, NULL, dev);
	385	if (ret) {
	386	dev_err(&pdev->dev, "failed to create dwc3 core\n");
	387	return ret;
72246da4 FB	388	}
	389
	390	return 0;
72246da4 FB	391	}
72246da4 FB	392
fb4e98ab	393	static int dwc3_omap_remove(struct platform_device *pdev)
72246da4	394	{
9a4b5dab FB	395	struct dwc3_omap *omap = platform_get_drvdata(pdev);
	396
	397	dwc3_omap_disable_irqs(omap);
af310e96 KVA	398	pm_runtime_put_sync(&pdev->dev);
af310e96 KVA	399	pm_runtime_disable(&pdev->dev);
94c6a436 KVA	400	device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
94c6a436 KVA	401
72246da4 FB	402	return 0;
	403	}
	404
2c2dc89c	405	static const struct of_device_id of_dwc3_match[] = {
72246da4	406	{
e36a0c87	407	.compatible = "ti,dwc3"
72246da4 FB	408	},
	409	{ },
	410	};
2c2dc89c	411	MODULE_DEVICE_TABLE(of, of_dwc3_match);
72246da4	412
f3e117f4 FB	413	#ifdef CONFIG_PM
	414	static int dwc3_omap_prepare(struct device *dev)
	415	{
	416	struct dwc3_omap *omap = dev_get_drvdata(dev);
	417
	418	dwc3_omap_disable_irqs(omap);
	419
	420	return 0;
	421	}
	422
	423	static void dwc3_omap_complete(struct device *dev)
	424	{
	425	struct dwc3_omap *omap = dev_get_drvdata(dev);
	426
	427	dwc3_omap_enable_irqs(omap);
	428	}
	429
	430	static int dwc3_omap_suspend(struct device *dev)
	431	{
	432	struct dwc3_omap *omap = dev_get_drvdata(dev);
	433
	434	omap->utmi_otg_status = dwc3_omap_readl(omap->base,
	435	USBOTGSS_UTMI_OTG_STATUS);
	436
	437	return 0;
	438	}
	439
	440	static int dwc3_omap_resume(struct device *dev)
	441	{
	442	struct dwc3_omap *omap = dev_get_drvdata(dev);
	443
	444	dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
	445	omap->utmi_otg_status);
	446
	447	pm_runtime_disable(dev);
	448	pm_runtime_set_active(dev);
	449	pm_runtime_enable(dev);
	450
	451	return 0;
	452	}
	453
	454	static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
	455	.prepare = dwc3_omap_prepare,
	456	.complete = dwc3_omap_complete,
	457
	458	SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
	459	};
	460
	461	#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
	462	#else
	463	#define DEV_PM_OPS NULL
	464	#endif /* CONFIG_PM */
	465
72246da4 FB	466	static struct platform_driver dwc3_omap_driver = {
72246da4 FB	467	.probe = dwc3_omap_probe,
7690417d	468	.remove = dwc3_omap_remove,
72246da4 FB	469	.driver = {
72246da4 FB	470	.name = "omap-dwc3",
2c2dc89c	471	.of_match_table = of_dwc3_match,
f3e117f4	472	.pm = DEV_PM_OPS,
72246da4 FB	473	},
	474	};
	475
cc27c96c AL	476	module_platform_driver(dwc3_omap_driver);
cc27c96c AL	477
7ae4fc4d	478	MODULE_ALIAS("platform:omap-dwc3");
72246da4 FB	479	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	480	MODULE_LICENSE("Dual BSD/GPL");
	481	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");