[mirror_ubuntu-bionic-kernel.git] / drivers / usb / dwc3 / dwc3-omap.c

/**
 * dwc3-omap.c - OMAP Specific Glue layer
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dwc3-omap.h>
#include <linux/dma-mapping.h>
#include <linux/ioport.h>
#include <linux/io.h>

#include "io.h"

/*
 * All these registers belong to OMAP's Wrapper around the
 * DesignWare USB3 Core.
 */

#define USBOTGSS_REVISION			0x0000
#define USBOTGSS_SYSCONFIG			0x0010
#define USBOTGSS_IRQ_EOI			0x0020
#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
#define USBOTGSS_IRQSTATUS_0			0x0028
#define USBOTGSS_IRQENABLE_SET_0		0x002c
#define USBOTGSS_IRQENABLE_CLR_0		0x0030
#define USBOTGSS_IRQSTATUS_RAW_1		0x0034
#define USBOTGSS_IRQSTATUS_1			0x0038
#define USBOTGSS_IRQENABLE_SET_1		0x003c
#define USBOTGSS_IRQENABLE_CLR_1		0x0040
#define USBOTGSS_UTMI_OTG_CTRL			0x0080
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_MMRAM_OFFSET			0x0100
#define USBOTGSS_FLADJ				0x0104
#define USBOTGSS_DEBUG_CFG			0x0108
#define USBOTGSS_DEBUG_DATA			0x010c

/* SYSCONFIG REGISTER */
#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)
#define USBOTGSS_SYSCONFIG_STANDBYMODE(x)	((x) << 4)

#define USBOTGSS_STANDBYMODE_FORCE_STANDBY	0
#define USBOTGSS_STANDBYMODE_NO_STANDBY		1
#define USBOTGSS_STANDBYMODE_SMART_STANDBY	2
#define USBOTGSS_STANDBYMODE_SMART_WAKEUP	3

#define USBOTGSS_STANDBYMODE_MASK		(0x03 << 4)

#define USBOTGSS_SYSCONFIG_IDLEMODE(x)		((x) << 2)

#define USBOTGSS_IDLEMODE_FORCE_IDLE		0
#define USBOTGSS_IDLEMODE_NO_IDLE		1
#define USBOTGSS_IDLEMODE_SMART_IDLE		2
#define USBOTGSS_IDLEMODE_SMART_WAKEUP		3

#define USBOTGSS_IDLEMODE_MASK			(0x03 << 2)

/* IRQ_EOI REGISTER */
#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)

/* IRQS0 BITS */
#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)

/* IRQ1 BITS */
#define USBOTGSS_IRQ1_DMADISABLECLR		(1 << 17)
#define USBOTGSS_IRQ1_OEVT			(1 << 16)
#define USBOTGSS_IRQ1_DRVVBUS_RISE		(1 << 13)
#define USBOTGSS_IRQ1_CHRGVBUS_RISE		(1 << 12)
#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE		(1 << 11)
#define USBOTGSS_IRQ1_IDPULLUP_RISE		(1 << 8)
#define USBOTGSS_IRQ1_DRVVBUS_FALL		(1 << 5)
#define USBOTGSS_IRQ1_CHRGVBUS_FALL		(1 << 4)
#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL		(1 << 3)
#define USBOTGSS_IRQ1_IDPULLUP_FALL		(1 << 0)

/* UTMI_OTG_CTRL REGISTER */
#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)
#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS	(1 << 3)
#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP		(1 << 0)

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	(1 << 31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	(1 << 9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		(1 << 4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	(1 << 3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	(1 << 2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	(1 << 1)

struct dwc3_omap {
	/* device lock */
	spinlock_t		lock;

	struct platform_device	*dwc3;
	struct device		*dev;

	int			irq;
	void __iomem		*base;

	void			*context;
	u32			resource_size;

	u32			dma_status:1;
};

static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
{
	struct dwc3_omap	*omap = _omap;
	u32			reg;

	spin_lock(&omap->lock);

	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);

	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
		dev_dbg(omap->dev, "DMA Disable was Cleared\n");
		omap->dma_status = false;
	}

	if (reg & USBOTGSS_IRQ1_OEVT)
		dev_dbg(omap->dev, "OTG Event\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
		dev_dbg(omap->dev, "DRVVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
		dev_dbg(omap->dev, "CHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
		dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
		dev_dbg(omap->dev, "IDPULLUP Rise\n");

	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
		dev_dbg(omap->dev, "DRVVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
		dev_dbg(omap->dev, "CHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
		dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");

	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
		dev_dbg(omap->dev, "IDPULLUP Fall\n");

	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);

	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);

	spin_unlock(&omap->lock);

	return IRQ_HANDLED;
}

static int __devinit dwc3_omap_probe(struct platform_device *pdev)
{
	struct dwc3_omap_data	*pdata = pdev->dev.platform_data;
	struct platform_device	*dwc3;
	struct dwc3_omap	*omap;
	struct resource		*res;

	int			ret = -ENOMEM;
	int			irq;

	u32			reg;

	void __iomem		*base;
	void			*context;

	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
	if (!omap) {
		dev_err(&pdev->dev, "not enough memory\n");
		goto err0;
	}

	platform_set_drvdata(pdev, omap);

	irq = platform_get_irq(pdev, 1);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ resource\n");
		ret = -EINVAL;
		goto err1;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "missing memory base resource\n");
		ret = -EINVAL;
		goto err1;
	}

	base = ioremap_nocache(res->start, resource_size(res));
	if (!base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		goto err1;
	}

	dwc3 = platform_device_alloc("dwc3-omap", -1);
	if (!dwc3) {
		dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
		goto err2;
	}

	context = kzalloc(resource_size(res), GFP_KERNEL);
	if (!context) {
		dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
		goto err3;
	}

	spin_lock_init(&omap->lock);
	dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);

	dwc3->dev.parent = &pdev->dev;
	dwc3->dev.dma_mask = pdev->dev.dma_mask;
	dwc3->dev.dma_parms = pdev->dev.dma_parms;
	omap->resource_size = resource_size(res);
	omap->context	= context;
	omap->dev	= &pdev->dev;
	omap->irq	= irq;
	omap->base	= base;
	omap->dwc3	= dwc3;

	reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);

	if (!pdata) {
		dev_dbg(&pdev->dev, "missing platform data\n");
	} else {
		switch (pdata->utmi_mode) {
		case DWC3_OMAP_UTMI_MODE_SW:
			reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
			break;
		case DWC3_OMAP_UTMI_MODE_HW:
			reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
			break;
		default:
			dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
					pdata->utmi_mode);
		}
	}

	dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);

	/* check the DMA Status */
	reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

	/* Set No-Idle and No-Standby */
	reg &= ~(USBOTGSS_STANDBYMODE_MASK
			| USBOTGSS_IDLEMODE_MASK);

	reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
		| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));

	dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);

	ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
			"dwc3-omap", omap);
	if (ret) {
		dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
				omap->irq, ret);
		goto err4;
	}

	/* enable all IRQs */
	reg = USBOTGSS_IRQO_COREIRQ_ST;
	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);

	reg = (USBOTGSS_IRQ1_OEVT |
			USBOTGSS_IRQ1_DRVVBUS_RISE |
			USBOTGSS_IRQ1_CHRGVBUS_RISE |
			USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
			USBOTGSS_IRQ1_IDPULLUP_RISE |
			USBOTGSS_IRQ1_DRVVBUS_FALL |
			USBOTGSS_IRQ1_CHRGVBUS_FALL |
			USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
			USBOTGSS_IRQ1_IDPULLUP_FALL);

	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);

	ret = platform_device_add_resources(dwc3, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
		goto err5;
	}

	ret = platform_device_add(dwc3);
	if (ret) {
		dev_err(&pdev->dev, "failed to register dwc3 device\n");
		goto err5;
	}

	return 0;

err5:
	free_irq(omap->irq, omap);

err4:
	kfree(omap->context);

err3:
	platform_device_put(dwc3);

err2:
	iounmap(base);

err1:
	kfree(omap);

err0:
	return ret;
}

static int __devexit dwc3_omap_remove(struct platform_device *pdev)
{
	struct dwc3_omap	*omap = platform_get_drvdata(pdev);

	platform_device_unregister(omap->dwc3);

	free_irq(omap->irq, omap);
	iounmap(omap->base);

	kfree(omap->context);
	kfree(omap);

	return 0;
}

static const struct of_device_id of_dwc3_matach[] = {
	{
		"ti,dwc3",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, of_dwc3_matach);

static struct platform_driver dwc3_omap_driver = {
	.probe		= dwc3_omap_probe,
	.remove		= __devexit_p(dwc3_omap_remove),
	.driver		= {
		.name	= "omap-dwc3",
		.of_match_table	= of_dwc3_matach,
	},
};

MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");

static int __devinit dwc3_omap_init(void)
{
	return platform_driver_register(&dwc3_omap_driver);
}
module_init(dwc3_omap_init);

static void __exit dwc3_omap_exit(void)
{
	platform_driver_unregister(&dwc3_omap_driver);
}
module_exit(dwc3_omap_exit);
Commit	Line	Data
72246da4 FB	1	/**
	2	* dwc3-omap.c - OMAP Specific Glue layer
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/spinlock.h>
	44	#include <linux/platform_device.h>
9962444f	45	#include <linux/platform_data/dwc3-omap.h>
72246da4 FB	46	#include <linux/dma-mapping.h>
	47	#include <linux/ioport.h>
	48	#include <linux/io.h>
	49
	50	#include "io.h"
	51
	52	/*
	53	* All these registers belong to OMAP's Wrapper around the
	54	* DesignWare USB3 Core.
	55	*/
	56
	57	#define USBOTGSS_REVISION 0x0000
	58	#define USBOTGSS_SYSCONFIG 0x0010
	59	#define USBOTGSS_IRQ_EOI 0x0020
	60	#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
	61	#define USBOTGSS_IRQSTATUS_0 0x0028
	62	#define USBOTGSS_IRQENABLE_SET_0 0x002c
	63	#define USBOTGSS_IRQENABLE_CLR_0 0x0030
	64	#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
	65	#define USBOTGSS_IRQSTATUS_1 0x0038
	66	#define USBOTGSS_IRQENABLE_SET_1 0x003c
	67	#define USBOTGSS_IRQENABLE_CLR_1 0x0040
	68	#define USBOTGSS_UTMI_OTG_CTRL 0x0080
	69	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
	70	#define USBOTGSS_MMRAM_OFFSET 0x0100
	71	#define USBOTGSS_FLADJ 0x0104
	72	#define USBOTGSS_DEBUG_CFG 0x0108
	73	#define USBOTGSS_DEBUG_DATA 0x010c
	74
	75	/* SYSCONFIG REGISTER */
	76	#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
	77	#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
4b5faa7a FB	78
	79	#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
	80	#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
	81	#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
	82	#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
	83
	84	#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
	85
72246da4 FB	86	#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
72246da4 FB	87
4b5faa7a FB	88	#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
	89	#define USBOTGSS_IDLEMODE_NO_IDLE 1
	90	#define USBOTGSS_IDLEMODE_SMART_IDLE 2
	91	#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
	92
	93	#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
	94
72246da4 FB	95	/* IRQ_EOI REGISTER */
	96	#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
	97
	98	/* IRQS0 BITS */
	99	#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
	100
	101	/* IRQ1 BITS */
	102	#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
	103	#define USBOTGSS_IRQ1_OEVT (1 << 16)
	104	#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
	105	#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
	106	#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
	107	#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
	108	#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
	109	#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
	110	#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
	111	#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
	112
	113	/* UTMI_OTG_CTRL REGISTER */
	114	#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
	115	#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
	116	#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
	117	#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
	118
	119	/* UTMI_OTG_STATUS REGISTER */
	120	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
	121	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
	122	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
	123	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
	124	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
	125	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
	126	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
	127
	128	struct dwc3_omap {
	129	/* device lock */
	130	spinlock_t lock;
	131
	132	struct platform_device *dwc3;
	133	struct device *dev;
	134
	135	int irq;
	136	void __iomem *base;
	137
	138	void *context;
	139	u32 resource_size;
	140
	141	u32 dma_status:1;
	142	};
	143
72246da4 FB	144	static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
	145	{
	146	struct dwc3_omap *omap = _omap;
	147	u32 reg;
72246da4 FB	148
	149	spin_lock(&omap->lock);
	150
	151	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
72246da4 FB	152
72246da4 FB	153	if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
ccba3bca	154	dev_dbg(omap->dev, "DMA Disable was Cleared\n");
72246da4 FB	155	omap->dma_status = false;
	156	}
	157
	158	if (reg & USBOTGSS_IRQ1_OEVT)
ccba3bca	159	dev_dbg(omap->dev, "OTG Event\n");
72246da4	160
42077b0a	161	if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
ccba3bca	162	dev_dbg(omap->dev, "DRVVBUS Rise\n");
72246da4	163
42077b0a	164	if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
ccba3bca	165	dev_dbg(omap->dev, "CHRGVBUS Rise\n");
72246da4	166
42077b0a	167	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
ccba3bca	168	dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
72246da4	169
42077b0a	170	if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
ccba3bca	171	dev_dbg(omap->dev, "IDPULLUP Rise\n");
72246da4	172
42077b0a	173	if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
ccba3bca	174	dev_dbg(omap->dev, "DRVVBUS Fall\n");
72246da4	175
42077b0a	176	if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
ccba3bca	177	dev_dbg(omap->dev, "CHRGVBUS Fall\n");
72246da4	178
42077b0a	179	if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
ccba3bca	180	dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
72246da4	181
42077b0a	182	if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
ccba3bca	183	dev_dbg(omap->dev, "IDPULLUP Fall\n");
72246da4	184
42077b0a FB	185	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
	186
	187	reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
	188	dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
72246da4 FB	189
	190	spin_unlock(&omap->lock);
	191
	192	return IRQ_HANDLED;
	193	}
	194
	195	static int __devinit dwc3_omap_probe(struct platform_device *pdev)
	196	{
9962444f	197	struct dwc3_omap_data *pdata = pdev->dev.platform_data;
72246da4 FB	198	struct platform_device *dwc3;
	199	struct dwc3_omap *omap;
	200	struct resource *res;
	201
	202	int ret = -ENOMEM;
	203	int irq;
	204
	205	u32 reg;
	206
	207	void __iomem *base;
	208	void *context;
	209
	210	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
	211	if (!omap) {
	212	dev_err(&pdev->dev, "not enough memory\n");
	213	goto err0;
	214	}
	215
	216	platform_set_drvdata(pdev, omap);
	217
	218	irq = platform_get_irq(pdev, 1);
	219	if (irq < 0) {
	220	dev_err(&pdev->dev, "missing IRQ resource\n");
	221	ret = -EINVAL;
	222	goto err1;
	223	}
	224
	225	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	226	if (!res) {
	227	dev_err(&pdev->dev, "missing memory base resource\n");
	228	ret = -EINVAL;
	229	goto err1;
	230	}
	231
	232	base = ioremap_nocache(res->start, resource_size(res));
	233	if (!base) {
	234	dev_err(&pdev->dev, "ioremap failed\n");
	235	goto err1;
	236	}
	237
	238	dwc3 = platform_device_alloc("dwc3-omap", -1);
	239	if (!dwc3) {
	240	dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
	241	goto err2;
	242	}
	243
	244	context = kzalloc(resource_size(res), GFP_KERNEL);
	245	if (!context) {
	246	dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
	247	goto err3;
	248	}
	249
	250	spin_lock_init(&omap->lock);
	251	dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
	252
	253	dwc3->dev.parent = &pdev->dev;
	254	dwc3->dev.dma_mask = pdev->dev.dma_mask;
	255	dwc3->dev.dma_parms = pdev->dev.dma_parms;
	256	omap->resource_size = resource_size(res);
	257	omap->context = context;
	258	omap->dev = &pdev->dev;
	259	omap->irq = irq;
	260	omap->base = base;
	261	omap->dwc3 = dwc3;
262
9962444f FB	263	reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
	264
	265	if (!pdata) {
	266	dev_dbg(&pdev->dev, "missing platform data\n");
	267	} else {
	268	switch (pdata->utmi_mode) {
	269	case DWC3_OMAP_UTMI_MODE_SW:
	270	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	271	break;
	272	case DWC3_OMAP_UTMI_MODE_HW:
	273	reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	274	break;
	275	default:
	276	dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
	277	pdata->utmi_mode);
	278	}
	279	}
	280
	281	dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
	282
72246da4 FB	283	/* check the DMA Status */
	284	reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
	285	omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
	286
4b5faa7a FB	287	/* Set No-Idle and No-Standby */
	288	reg &= ~(USBOTGSS_STANDBYMODE_MASK
	289	\| USBOTGSS_IDLEMODE_MASK);
	290
	291	reg \|= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
	292	\| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
	293
	294	dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
	295
72246da4	296	ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
dd17a6b2	297	"dwc3-omap", omap);
72246da4 FB	298	if (ret) {
	299	dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
	300	omap->irq, ret);
	301	goto err4;
	302	}
	303
	304	/* enable all IRQs */
df01c61e FB	305	reg = USBOTGSS_IRQO_COREIRQ_ST;
df01c61e FB	306	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
72246da4	307
324e5481	308	reg = (USBOTGSS_IRQ1_OEVT \|
72246da4 FB	309	USBOTGSS_IRQ1_DRVVBUS_RISE \|
	310	USBOTGSS_IRQ1_CHRGVBUS_RISE \|
	311	USBOTGSS_IRQ1_DISCHRGVBUS_RISE \|
	312	USBOTGSS_IRQ1_IDPULLUP_RISE \|
	313	USBOTGSS_IRQ1_DRVVBUS_FALL \|
	314	USBOTGSS_IRQ1_CHRGVBUS_FALL \|
	315	USBOTGSS_IRQ1_DISCHRGVBUS_FALL \|
	316	USBOTGSS_IRQ1_IDPULLUP_FALL);
	317
	318	dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
	319
	320	ret = platform_device_add_resources(dwc3, pdev->resource,
	321	pdev->num_resources);
	322	if (ret) {
	323	dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
	324	goto err5;
	325	}
	326
	327	ret = platform_device_add(dwc3);
	328	if (ret) {
	329	dev_err(&pdev->dev, "failed to register dwc3 device\n");
	330	goto err5;
	331	}
	332
	333	return 0;
	334
	335	err5:
	336	free_irq(omap->irq, omap);
	337
	338	err4:
	339	kfree(omap->context);
	340
	341	err3:
	342	platform_device_put(dwc3);
	343
	344	err2:
	345	iounmap(base);
	346
	347	err1:
	348	kfree(omap);
	349
	350	err0:
	351	return ret;
	352	}
	353
	354	static int __devexit dwc3_omap_remove(struct platform_device *pdev)
	355	{
	356	struct dwc3_omap *omap = platform_get_drvdata(pdev);
	357
	358	platform_device_unregister(omap->dwc3);
	359
	360	free_irq(omap->irq, omap);
	361	iounmap(omap->base);
	362
	363	kfree(omap->context);
	364	kfree(omap);
	365
	366	return 0;
	367	}
	368
	369	static const struct of_device_id of_dwc3_matach[] = {
	370	{
	371	"ti,dwc3",
	372	},
373	{ },
374	};
375	MODULE_DEVICE_TABLE(of, of_dwc3_matach);
376
377	static struct platform_driver dwc3_omap_driver = {
378	.probe = dwc3_omap_probe,
379	.remove = __devexit_p(dwc3_omap_remove),
380	.driver = {
381	.name = "omap-dwc3",
72246da4 FB	382	.of_match_table = of_dwc3_matach,
	383	},
	384	};
	385
	386	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	387	MODULE_LICENSE("Dual BSD/GPL");
	388	MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
	389
	390	static int __devinit dwc3_omap_init(void)
	391	{
	392	return platform_driver_register(&dwc3_omap_driver);
	393	}
	394	module_init(dwc3_omap_init);
	395
	396	static void __exit dwc3_omap_exit(void)
	397	{
	398	platform_driver_unregister(&dwc3_omap_driver);
	399	}
	400	module_exit(dwc3_omap_exit);