]>
Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * dwc3-omap.c - OMAP Specific Glue layer | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
5 | * All rights reserved. | |
6 | * | |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions, and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce the above copyright | |
17 | * notice, this list of conditions and the following disclaimer in the | |
18 | * documentation and/or other materials provided with the distribution. | |
19 | * 3. The names of the above-listed copyright holders may not be used | |
20 | * to endorse or promote products derived from this software without | |
21 | * specific prior written permission. | |
22 | * | |
23 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
24 | * GNU General Public License ("GPL") version 2, as published by the Free | |
25 | * Software Foundation. | |
26 | * | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
28 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
29 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
31 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
32 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
33 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
34 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
35 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
36 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
37 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
38 | */ | |
39 | ||
a72e658b | 40 | #include <linux/module.h> |
72246da4 FB |
41 | #include <linux/kernel.h> |
42 | #include <linux/slab.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/spinlock.h> | |
45 | #include <linux/platform_device.h> | |
9962444f | 46 | #include <linux/platform_data/dwc3-omap.h> |
72246da4 FB |
47 | #include <linux/dma-mapping.h> |
48 | #include <linux/ioport.h> | |
49 | #include <linux/io.h> | |
50 | ||
51 | #include "io.h" | |
52 | ||
53 | /* | |
54 | * All these registers belong to OMAP's Wrapper around the | |
55 | * DesignWare USB3 Core. | |
56 | */ | |
57 | ||
58 | #define USBOTGSS_REVISION 0x0000 | |
59 | #define USBOTGSS_SYSCONFIG 0x0010 | |
60 | #define USBOTGSS_IRQ_EOI 0x0020 | |
61 | #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 | |
62 | #define USBOTGSS_IRQSTATUS_0 0x0028 | |
63 | #define USBOTGSS_IRQENABLE_SET_0 0x002c | |
64 | #define USBOTGSS_IRQENABLE_CLR_0 0x0030 | |
65 | #define USBOTGSS_IRQSTATUS_RAW_1 0x0034 | |
66 | #define USBOTGSS_IRQSTATUS_1 0x0038 | |
67 | #define USBOTGSS_IRQENABLE_SET_1 0x003c | |
68 | #define USBOTGSS_IRQENABLE_CLR_1 0x0040 | |
69 | #define USBOTGSS_UTMI_OTG_CTRL 0x0080 | |
70 | #define USBOTGSS_UTMI_OTG_STATUS 0x0084 | |
71 | #define USBOTGSS_MMRAM_OFFSET 0x0100 | |
72 | #define USBOTGSS_FLADJ 0x0104 | |
73 | #define USBOTGSS_DEBUG_CFG 0x0108 | |
74 | #define USBOTGSS_DEBUG_DATA 0x010c | |
75 | ||
76 | /* SYSCONFIG REGISTER */ | |
77 | #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) | |
78 | #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4) | |
79 | #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2) | |
80 | ||
81 | /* IRQ_EOI REGISTER */ | |
82 | #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) | |
83 | ||
84 | /* IRQS0 BITS */ | |
85 | #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) | |
86 | ||
87 | /* IRQ1 BITS */ | |
88 | #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17) | |
89 | #define USBOTGSS_IRQ1_OEVT (1 << 16) | |
90 | #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13) | |
91 | #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12) | |
92 | #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11) | |
93 | #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8) | |
94 | #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5) | |
95 | #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4) | |
96 | #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3) | |
97 | #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0) | |
98 | ||
99 | /* UTMI_OTG_CTRL REGISTER */ | |
100 | #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) | |
101 | #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) | |
102 | #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) | |
103 | #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) | |
104 | ||
105 | /* UTMI_OTG_STATUS REGISTER */ | |
106 | #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) | |
107 | #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) | |
108 | #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) | |
109 | #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) | |
110 | #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) | |
111 | #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) | |
112 | #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) | |
113 | ||
114 | struct dwc3_omap { | |
115 | /* device lock */ | |
116 | spinlock_t lock; | |
117 | ||
118 | struct platform_device *dwc3; | |
119 | struct device *dev; | |
120 | ||
121 | int irq; | |
122 | void __iomem *base; | |
123 | ||
124 | void *context; | |
125 | u32 resource_size; | |
126 | ||
127 | u32 dma_status:1; | |
128 | }; | |
129 | ||
72246da4 FB |
130 | static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) |
131 | { | |
132 | struct dwc3_omap *omap = _omap; | |
133 | u32 reg; | |
134 | u32 ctrl; | |
135 | ||
136 | spin_lock(&omap->lock); | |
137 | ||
138 | reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1); | |
139 | ctrl = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL); | |
140 | ||
141 | if (reg & USBOTGSS_IRQ1_DMADISABLECLR) { | |
ccba3bca | 142 | dev_dbg(omap->dev, "DMA Disable was Cleared\n"); |
72246da4 FB |
143 | omap->dma_status = false; |
144 | } | |
145 | ||
146 | if (reg & USBOTGSS_IRQ1_OEVT) | |
ccba3bca | 147 | dev_dbg(omap->dev, "OTG Event\n"); |
72246da4 FB |
148 | |
149 | if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) { | |
ccba3bca | 150 | dev_dbg(omap->dev, "DRVVBUS Rise\n"); |
72246da4 FB |
151 | ctrl |= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS; |
152 | } | |
153 | ||
154 | if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) { | |
ccba3bca | 155 | dev_dbg(omap->dev, "CHRGVBUS Rise\n"); |
72246da4 FB |
156 | ctrl |= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS; |
157 | } | |
158 | ||
159 | if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) { | |
ccba3bca | 160 | dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); |
72246da4 FB |
161 | ctrl |= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS; |
162 | } | |
163 | ||
164 | if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) { | |
ccba3bca | 165 | dev_dbg(omap->dev, "IDPULLUP Rise\n"); |
72246da4 FB |
166 | ctrl |= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP; |
167 | } | |
168 | ||
169 | if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) { | |
ccba3bca | 170 | dev_dbg(omap->dev, "DRVVBUS Fall\n"); |
72246da4 FB |
171 | ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS; |
172 | } | |
173 | ||
174 | if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) { | |
ccba3bca | 175 | dev_dbg(omap->dev, "CHRGVBUS Fall\n"); |
72246da4 FB |
176 | ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS; |
177 | } | |
178 | ||
179 | if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) { | |
ccba3bca | 180 | dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); |
72246da4 FB |
181 | ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS; |
182 | } | |
183 | ||
184 | if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) { | |
ccba3bca | 185 | dev_dbg(omap->dev, "IDPULLUP Fall\n"); |
72246da4 FB |
186 | ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP; |
187 | } | |
188 | ||
189 | dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL, ctrl); | |
190 | ||
191 | spin_unlock(&omap->lock); | |
192 | ||
193 | return IRQ_HANDLED; | |
194 | } | |
195 | ||
196 | static int __devinit dwc3_omap_probe(struct platform_device *pdev) | |
197 | { | |
9962444f | 198 | struct dwc3_omap_data *pdata = pdev->dev.platform_data; |
72246da4 FB |
199 | struct platform_device *dwc3; |
200 | struct dwc3_omap *omap; | |
201 | struct resource *res; | |
202 | ||
203 | int ret = -ENOMEM; | |
204 | int irq; | |
205 | ||
206 | u32 reg; | |
207 | ||
208 | void __iomem *base; | |
209 | void *context; | |
210 | ||
211 | omap = kzalloc(sizeof(*omap), GFP_KERNEL); | |
212 | if (!omap) { | |
213 | dev_err(&pdev->dev, "not enough memory\n"); | |
214 | goto err0; | |
215 | } | |
216 | ||
217 | platform_set_drvdata(pdev, omap); | |
218 | ||
219 | irq = platform_get_irq(pdev, 1); | |
220 | if (irq < 0) { | |
221 | dev_err(&pdev->dev, "missing IRQ resource\n"); | |
222 | ret = -EINVAL; | |
223 | goto err1; | |
224 | } | |
225 | ||
226 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
227 | if (!res) { | |
228 | dev_err(&pdev->dev, "missing memory base resource\n"); | |
229 | ret = -EINVAL; | |
230 | goto err1; | |
231 | } | |
232 | ||
233 | base = ioremap_nocache(res->start, resource_size(res)); | |
234 | if (!base) { | |
235 | dev_err(&pdev->dev, "ioremap failed\n"); | |
236 | goto err1; | |
237 | } | |
238 | ||
239 | dwc3 = platform_device_alloc("dwc3-omap", -1); | |
240 | if (!dwc3) { | |
241 | dev_err(&pdev->dev, "couldn't allocate dwc3 device\n"); | |
242 | goto err2; | |
243 | } | |
244 | ||
245 | context = kzalloc(resource_size(res), GFP_KERNEL); | |
246 | if (!context) { | |
247 | dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n"); | |
248 | goto err3; | |
249 | } | |
250 | ||
251 | spin_lock_init(&omap->lock); | |
252 | dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask); | |
253 | ||
254 | dwc3->dev.parent = &pdev->dev; | |
255 | dwc3->dev.dma_mask = pdev->dev.dma_mask; | |
256 | dwc3->dev.dma_parms = pdev->dev.dma_parms; | |
257 | omap->resource_size = resource_size(res); | |
258 | omap->context = context; | |
259 | omap->dev = &pdev->dev; | |
260 | omap->irq = irq; | |
261 | omap->base = base; | |
262 | omap->dwc3 = dwc3; | |
263 | ||
9962444f FB |
264 | reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS); |
265 | ||
266 | if (!pdata) { | |
267 | dev_dbg(&pdev->dev, "missing platform data\n"); | |
268 | } else { | |
269 | switch (pdata->utmi_mode) { | |
270 | case DWC3_OMAP_UTMI_MODE_SW: | |
271 | reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; | |
272 | break; | |
273 | case DWC3_OMAP_UTMI_MODE_HW: | |
274 | reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; | |
275 | break; | |
276 | default: | |
277 | dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n", | |
278 | pdata->utmi_mode); | |
279 | } | |
280 | } | |
281 | ||
282 | dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg); | |
283 | ||
72246da4 FB |
284 | /* check the DMA Status */ |
285 | reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG); | |
286 | omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); | |
287 | ||
288 | ret = request_irq(omap->irq, dwc3_omap_interrupt, 0, | |
dd17a6b2 | 289 | "dwc3-omap", omap); |
72246da4 FB |
290 | if (ret) { |
291 | dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n", | |
292 | omap->irq, ret); | |
293 | goto err4; | |
294 | } | |
295 | ||
296 | /* enable all IRQs */ | |
df01c61e FB |
297 | reg = USBOTGSS_IRQO_COREIRQ_ST; |
298 | dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg); | |
72246da4 | 299 | |
324e5481 | 300 | reg = (USBOTGSS_IRQ1_OEVT | |
72246da4 FB |
301 | USBOTGSS_IRQ1_DRVVBUS_RISE | |
302 | USBOTGSS_IRQ1_CHRGVBUS_RISE | | |
303 | USBOTGSS_IRQ1_DISCHRGVBUS_RISE | | |
304 | USBOTGSS_IRQ1_IDPULLUP_RISE | | |
305 | USBOTGSS_IRQ1_DRVVBUS_FALL | | |
306 | USBOTGSS_IRQ1_CHRGVBUS_FALL | | |
307 | USBOTGSS_IRQ1_DISCHRGVBUS_FALL | | |
308 | USBOTGSS_IRQ1_IDPULLUP_FALL); | |
309 | ||
310 | dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg); | |
311 | ||
312 | ret = platform_device_add_resources(dwc3, pdev->resource, | |
313 | pdev->num_resources); | |
314 | if (ret) { | |
315 | dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n"); | |
316 | goto err5; | |
317 | } | |
318 | ||
319 | ret = platform_device_add(dwc3); | |
320 | if (ret) { | |
321 | dev_err(&pdev->dev, "failed to register dwc3 device\n"); | |
322 | goto err5; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | ||
327 | err5: | |
328 | free_irq(omap->irq, omap); | |
329 | ||
330 | err4: | |
331 | kfree(omap->context); | |
332 | ||
333 | err3: | |
334 | platform_device_put(dwc3); | |
335 | ||
336 | err2: | |
337 | iounmap(base); | |
338 | ||
339 | err1: | |
340 | kfree(omap); | |
341 | ||
342 | err0: | |
343 | return ret; | |
344 | } | |
345 | ||
346 | static int __devexit dwc3_omap_remove(struct platform_device *pdev) | |
347 | { | |
348 | struct dwc3_omap *omap = platform_get_drvdata(pdev); | |
349 | ||
350 | platform_device_unregister(omap->dwc3); | |
351 | ||
352 | free_irq(omap->irq, omap); | |
353 | iounmap(omap->base); | |
354 | ||
355 | kfree(omap->context); | |
356 | kfree(omap); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static const struct of_device_id of_dwc3_matach[] = { | |
362 | { | |
363 | "ti,dwc3", | |
364 | }, | |
365 | { }, | |
366 | }; | |
367 | MODULE_DEVICE_TABLE(of, of_dwc3_matach); | |
368 | ||
369 | static struct platform_driver dwc3_omap_driver = { | |
370 | .probe = dwc3_omap_probe, | |
371 | .remove = __devexit_p(dwc3_omap_remove), | |
372 | .driver = { | |
373 | .name = "omap-dwc3", | |
72246da4 FB |
374 | .of_match_table = of_dwc3_matach, |
375 | }, | |
376 | }; | |
377 | ||
378 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
379 | MODULE_LICENSE("Dual BSD/GPL"); | |
380 | MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); | |
381 | ||
382 | static int __devinit dwc3_omap_init(void) | |
383 | { | |
384 | return platform_driver_register(&dwc3_omap_driver); | |
385 | } | |
386 | module_init(dwc3_omap_init); | |
387 | ||
388 | static void __exit dwc3_omap_exit(void) | |
389 | { | |
390 | platform_driver_unregister(&dwc3_omap_driver); | |
391 | } | |
392 | module_exit(dwc3_omap_exit); |