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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
73815280 FB |
142 | dwc3_trace(trace_dwc3_gadget, |
143 | "link state change request timed out"); | |
8598bde7 FB |
144 | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
dca0119c JY |
148 | /** |
149 | * dwc3_ep_inc_trb() - Increment a TRB index. | |
150 | * @index - Pointer to the TRB index to increment. | |
151 | * | |
152 | * The index should never point to the link TRB. After incrementing, | |
153 | * if it is point to the link TRB, wrap around to the beginning. The | |
154 | * link TRB is always at the last TRB entry. | |
155 | */ | |
156 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 157 | { |
dca0119c JY |
158 | (*index)++; |
159 | if (*index == (DWC3_TRB_NUM - 1)) | |
160 | *index = 0; | |
ef966b9d | 161 | } |
457e84b6 | 162 | |
dca0119c | 163 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 164 | { |
dca0119c | 165 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 166 | } |
457e84b6 | 167 | |
dca0119c | 168 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 169 | { |
dca0119c | 170 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
171 | } |
172 | ||
72246da4 FB |
173 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
174 | int status) | |
175 | { | |
176 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 177 | int i; |
72246da4 | 178 | |
aa3342c8 | 179 | if (req->started) { |
e5ba5ec8 PA |
180 | i = 0; |
181 | do { | |
ef966b9d | 182 | dwc3_ep_inc_deq(dep); |
e5ba5ec8 | 183 | } while(++i < req->request.num_mapped_sgs); |
aa3342c8 | 184 | req->started = false; |
72246da4 FB |
185 | } |
186 | list_del(&req->list); | |
eeb720fb | 187 | req->trb = NULL; |
72246da4 FB |
188 | |
189 | if (req->request.status == -EINPROGRESS) | |
190 | req->request.status = status; | |
191 | ||
0416e494 PA |
192 | if (dwc->ep0_bounced && dep->number == 0) |
193 | dwc->ep0_bounced = false; | |
194 | else | |
195 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
196 | req->direction); | |
72246da4 | 197 | |
2c4cbe6e | 198 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
199 | |
200 | spin_unlock(&dwc->lock); | |
304f7e5e | 201 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 | 202 | spin_lock(&dwc->lock); |
fc8bb91b FB |
203 | |
204 | if (dep->number > 1) | |
205 | pm_runtime_put(dwc->dev); | |
72246da4 FB |
206 | } |
207 | ||
3ece0ec4 | 208 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
209 | { |
210 | u32 timeout = 500; | |
71f7e702 | 211 | int status = 0; |
0fe886cd | 212 | int ret = 0; |
b09bb642 FB |
213 | u32 reg; |
214 | ||
215 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
216 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
217 | ||
218 | do { | |
219 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
220 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
221 | status = DWC3_DGCMD_STATUS(reg); |
222 | if (status) | |
0fe886cd FB |
223 | ret = -EINVAL; |
224 | break; | |
b09bb642 | 225 | } |
0fe886cd FB |
226 | } while (timeout--); |
227 | ||
228 | if (!timeout) { | |
0fe886cd | 229 | ret = -ETIMEDOUT; |
71f7e702 | 230 | status = -ETIMEDOUT; |
0fe886cd FB |
231 | } |
232 | ||
71f7e702 FB |
233 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
234 | ||
0fe886cd | 235 | return ret; |
b09bb642 FB |
236 | } |
237 | ||
c36d8e94 FB |
238 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
239 | ||
2cd4718d FB |
240 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
241 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 242 | { |
2cd4718d | 243 | struct dwc3 *dwc = dep->dwc; |
61d58242 | 244 | u32 timeout = 500; |
72246da4 FB |
245 | u32 reg; |
246 | ||
0933df15 | 247 | int cmd_status = 0; |
2b0f11df | 248 | int susphy = false; |
c0ca324d | 249 | int ret = -EINVAL; |
72246da4 | 250 | |
2b0f11df FB |
251 | /* |
252 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
253 | * we're issuing an endpoint command, we must check if | |
254 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
255 | * | |
256 | * We will also set SUSPHY bit to what it was before returning as stated | |
257 | * by the same section on Synopsys databook. | |
258 | */ | |
ab2a92e7 FB |
259 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
260 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
261 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
262 | susphy = true; | |
263 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
264 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
265 | } | |
2b0f11df FB |
266 | } |
267 | ||
c36d8e94 FB |
268 | if (cmd == DWC3_DEPCMD_STARTTRANSFER) { |
269 | int needs_wakeup; | |
270 | ||
271 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
272 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
273 | dwc->link_state == DWC3_LINK_STATE_U3); | |
274 | ||
275 | if (unlikely(needs_wakeup)) { | |
276 | ret = __dwc3_gadget_wakeup(dwc); | |
277 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
278 | ret); | |
279 | } | |
280 | } | |
281 | ||
2eb88016 FB |
282 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
283 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
284 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 285 | |
2eb88016 | 286 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT); |
72246da4 | 287 | do { |
2eb88016 | 288 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 289 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 290 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 291 | |
73815280 FB |
292 | dwc3_trace(trace_dwc3_gadget, |
293 | "Command Complete --> %d", | |
7b9cc7a2 KL |
294 | cmd_status); |
295 | ||
296 | switch (cmd_status) { | |
297 | case 0: | |
298 | ret = 0; | |
299 | break; | |
300 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
ba159841 | 301 | dwc3_trace(trace_dwc3_gadget, "no resource available"); |
7b9cc7a2 | 302 | ret = -EINVAL; |
c0ca324d | 303 | break; |
7b9cc7a2 KL |
304 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
305 | /* | |
306 | * SW issues START TRANSFER command to | |
307 | * isochronous ep with future frame interval. If | |
308 | * future interval time has already passed when | |
309 | * core receives the command, it will respond | |
310 | * with an error status of 'Bus Expiry'. | |
311 | * | |
312 | * Instead of always returning -EINVAL, let's | |
313 | * give a hint to the gadget driver that this is | |
314 | * the case by returning -EAGAIN. | |
315 | */ | |
ba159841 | 316 | dwc3_trace(trace_dwc3_gadget, "bus expiry"); |
7b9cc7a2 KL |
317 | ret = -EAGAIN; |
318 | break; | |
319 | default: | |
320 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
321 | } | |
322 | ||
c0ca324d | 323 | break; |
72246da4 | 324 | } |
f6bb225b | 325 | } while (--timeout); |
72246da4 | 326 | |
f6bb225b FB |
327 | if (timeout == 0) { |
328 | dwc3_trace(trace_dwc3_gadget, | |
329 | "Command Timed Out"); | |
330 | ret = -ETIMEDOUT; | |
0933df15 | 331 | cmd_status = -ETIMEDOUT; |
f6bb225b | 332 | } |
c0ca324d | 333 | |
0933df15 FB |
334 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
335 | ||
2b0f11df FB |
336 | if (unlikely(susphy)) { |
337 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
338 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
339 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
340 | } | |
341 | ||
c0ca324d | 342 | return ret; |
72246da4 FB |
343 | } |
344 | ||
50c763f8 JY |
345 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
346 | { | |
347 | struct dwc3 *dwc = dep->dwc; | |
348 | struct dwc3_gadget_ep_cmd_params params; | |
349 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
350 | ||
351 | /* | |
352 | * As of core revision 2.60a the recommended programming model | |
353 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
354 | * command for IN endpoints. This is to prevent an issue where | |
355 | * some (non-compliant) hosts may not send ACK TPs for pending | |
356 | * IN transfers due to a mishandled error condition. Synopsys | |
357 | * STAR 9000614252. | |
358 | */ | |
359 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A)) | |
360 | cmd |= DWC3_DEPCMD_CLEARPENDIN; | |
361 | ||
362 | memset(¶ms, 0, sizeof(params)); | |
363 | ||
2cd4718d | 364 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
365 | } |
366 | ||
72246da4 | 367 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 368 | struct dwc3_trb *trb) |
72246da4 | 369 | { |
c439ef87 | 370 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
371 | |
372 | return dep->trb_pool_dma + offset; | |
373 | } | |
374 | ||
375 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
376 | { | |
377 | struct dwc3 *dwc = dep->dwc; | |
378 | ||
379 | if (dep->trb_pool) | |
380 | return 0; | |
381 | ||
72246da4 FB |
382 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
383 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
384 | &dep->trb_pool_dma, GFP_KERNEL); | |
385 | if (!dep->trb_pool) { | |
386 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
387 | dep->name); | |
388 | return -ENOMEM; | |
389 | } | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
395 | { | |
396 | struct dwc3 *dwc = dep->dwc; | |
397 | ||
398 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
399 | dep->trb_pool, dep->trb_pool_dma); | |
400 | ||
401 | dep->trb_pool = NULL; | |
402 | dep->trb_pool_dma = 0; | |
403 | } | |
404 | ||
c4509601 JY |
405 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
406 | ||
407 | /** | |
408 | * dwc3_gadget_start_config - Configure EP resources | |
409 | * @dwc: pointer to our controller context structure | |
410 | * @dep: endpoint that is being enabled | |
411 | * | |
412 | * The assignment of transfer resources cannot perfectly follow the | |
413 | * data book due to the fact that the controller driver does not have | |
414 | * all knowledge of the configuration in advance. It is given this | |
415 | * information piecemeal by the composite gadget framework after every | |
416 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
417 | * programming model in this scenario can cause errors. For two | |
418 | * reasons: | |
419 | * | |
420 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
421 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
422 | * multiple interfaces. | |
423 | * | |
424 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
425 | * endpoint on alt setting (8.1.6). | |
426 | * | |
427 | * The following simplified method is used instead: | |
428 | * | |
429 | * All hardware endpoints can be assigned a transfer resource and this | |
430 | * setting will stay persistent until either a core reset or | |
431 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
432 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
433 | * guaranteed that there are as many transfer resources as endpoints. | |
434 | * | |
435 | * This function is called for each endpoint when it is being enabled | |
436 | * but is triggered only when called for EP0-out, which always happens | |
437 | * first, and which should only happen in one of the above conditions. | |
438 | */ | |
72246da4 FB |
439 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
440 | { | |
441 | struct dwc3_gadget_ep_cmd_params params; | |
442 | u32 cmd; | |
c4509601 JY |
443 | int i; |
444 | int ret; | |
445 | ||
446 | if (dep->number) | |
447 | return 0; | |
72246da4 FB |
448 | |
449 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 450 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 451 | |
2cd4718d | 452 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
453 | if (ret) |
454 | return ret; | |
455 | ||
456 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
457 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 458 | |
c4509601 JY |
459 | if (!dep) |
460 | continue; | |
461 | ||
462 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
463 | if (ret) | |
464 | return ret; | |
72246da4 FB |
465 | } |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 471 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 472 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 473 | bool ignore, bool restore) |
72246da4 FB |
474 | { |
475 | struct dwc3_gadget_ep_cmd_params params; | |
476 | ||
477 | memset(¶ms, 0x00, sizeof(params)); | |
478 | ||
dc1c70a7 | 479 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
480 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
481 | ||
482 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 483 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 484 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 485 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 486 | } |
72246da4 | 487 | |
4b345c9a FB |
488 | if (ignore) |
489 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
490 | ||
265b70a7 PZ |
491 | if (restore) { |
492 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
493 | params.param2 |= dep->saved_state; | |
494 | } | |
495 | ||
dc1c70a7 FB |
496 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
497 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 498 | |
18b7ede5 | 499 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
500 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
501 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
502 | dep->stream_capable = true; |
503 | } | |
504 | ||
0b93a4c8 | 505 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 506 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
507 | |
508 | /* | |
509 | * We are doing 1:1 mapping for endpoints, meaning | |
510 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
511 | * so on. We consider the direction bit as part of the physical | |
512 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
513 | */ | |
dc1c70a7 | 514 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
515 | |
516 | /* | |
517 | * We must use the lower 16 TX FIFOs even though | |
518 | * HW might have more | |
519 | */ | |
520 | if (dep->direction) | |
dc1c70a7 | 521 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
522 | |
523 | if (desc->bInterval) { | |
dc1c70a7 | 524 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
525 | dep->interval = 1 << (desc->bInterval - 1); |
526 | } | |
527 | ||
2cd4718d | 528 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
529 | } |
530 | ||
531 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
532 | { | |
533 | struct dwc3_gadget_ep_cmd_params params; | |
534 | ||
535 | memset(¶ms, 0x00, sizeof(params)); | |
536 | ||
dc1c70a7 | 537 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 | 538 | |
2cd4718d FB |
539 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, |
540 | ¶ms); | |
72246da4 FB |
541 | } |
542 | ||
543 | /** | |
544 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
545 | * @dep: endpoint to be initialized | |
546 | * @desc: USB Endpoint Descriptor | |
547 | * | |
548 | * Caller should take care of locking | |
549 | */ | |
550 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 551 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 552 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 553 | bool ignore, bool restore) |
72246da4 FB |
554 | { |
555 | struct dwc3 *dwc = dep->dwc; | |
556 | u32 reg; | |
b09e99ee | 557 | int ret; |
72246da4 | 558 | |
73815280 | 559 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); |
ff62d6b6 | 560 | |
72246da4 FB |
561 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
562 | ret = dwc3_gadget_start_config(dwc, dep); | |
563 | if (ret) | |
564 | return ret; | |
565 | } | |
566 | ||
265b70a7 PZ |
567 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
568 | restore); | |
72246da4 FB |
569 | if (ret) |
570 | return ret; | |
571 | ||
572 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
573 | struct dwc3_trb *trb_st_hw; |
574 | struct dwc3_trb *trb_link; | |
72246da4 | 575 | |
16e78db7 | 576 | dep->endpoint.desc = desc; |
c90bfaec | 577 | dep->comp_desc = comp_desc; |
72246da4 FB |
578 | dep->type = usb_endpoint_type(desc); |
579 | dep->flags |= DWC3_EP_ENABLED; | |
580 | ||
581 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
582 | reg |= DWC3_DALEPENA_EP(dep->number); | |
583 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
584 | ||
36b68aae | 585 | if (usb_endpoint_xfer_control(desc)) |
7ab373aa | 586 | return 0; |
72246da4 | 587 | |
0d25744a JY |
588 | /* Initialize the TRB ring */ |
589 | dep->trb_dequeue = 0; | |
590 | dep->trb_enqueue = 0; | |
591 | memset(dep->trb_pool, 0, | |
592 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
593 | ||
36b68aae | 594 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
595 | trb_st_hw = &dep->trb_pool[0]; |
596 | ||
f6bafc6a | 597 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
598 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
599 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
600 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
601 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
602 | } |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
b992e681 | 607 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 608 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
609 | { |
610 | struct dwc3_request *req; | |
611 | ||
aa3342c8 | 612 | if (!list_empty(&dep->started_list)) { |
b992e681 | 613 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 614 | |
57911504 | 615 | /* - giveback all requests to gadget driver */ |
aa3342c8 FB |
616 | while (!list_empty(&dep->started_list)) { |
617 | req = next_request(&dep->started_list); | |
1591633e PA |
618 | |
619 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
620 | } | |
ea53b882 FB |
621 | } |
622 | ||
aa3342c8 FB |
623 | while (!list_empty(&dep->pending_list)) { |
624 | req = next_request(&dep->pending_list); | |
72246da4 | 625 | |
624407f9 | 626 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 627 | } |
72246da4 FB |
628 | } |
629 | ||
630 | /** | |
631 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
632 | * @dep: the endpoint to disable | |
633 | * | |
624407f9 SAS |
634 | * This function also removes requests which are currently processed ny the |
635 | * hardware and those which are not yet scheduled. | |
636 | * Caller should take care of locking. | |
72246da4 | 637 | */ |
72246da4 FB |
638 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
639 | { | |
640 | struct dwc3 *dwc = dep->dwc; | |
641 | u32 reg; | |
642 | ||
7eaeac5c FB |
643 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); |
644 | ||
624407f9 | 645 | dwc3_remove_requests(dwc, dep); |
72246da4 | 646 | |
687ef981 FB |
647 | /* make sure HW endpoint isn't stalled */ |
648 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 649 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 650 | |
72246da4 FB |
651 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
652 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
653 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
654 | ||
879631aa | 655 | dep->stream_capable = false; |
f9c56cdd | 656 | dep->endpoint.desc = NULL; |
c90bfaec | 657 | dep->comp_desc = NULL; |
72246da4 | 658 | dep->type = 0; |
879631aa | 659 | dep->flags = 0; |
72246da4 FB |
660 | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* -------------------------------------------------------------------------- */ | |
665 | ||
666 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
667 | const struct usb_endpoint_descriptor *desc) | |
668 | { | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
673 | { | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | /* -------------------------------------------------------------------------- */ | |
678 | ||
679 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
680 | const struct usb_endpoint_descriptor *desc) | |
681 | { | |
682 | struct dwc3_ep *dep; | |
683 | struct dwc3 *dwc; | |
684 | unsigned long flags; | |
685 | int ret; | |
686 | ||
687 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
688 | pr_debug("dwc3: invalid parameters\n"); | |
689 | return -EINVAL; | |
690 | } | |
691 | ||
692 | if (!desc->wMaxPacketSize) { | |
693 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
694 | return -EINVAL; | |
695 | } | |
696 | ||
697 | dep = to_dwc3_ep(ep); | |
698 | dwc = dep->dwc; | |
699 | ||
95ca961c FB |
700 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
701 | "%s is already enabled\n", | |
702 | dep->name)) | |
c6f83f38 | 703 | return 0; |
c6f83f38 | 704 | |
72246da4 | 705 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 706 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
707 | spin_unlock_irqrestore(&dwc->lock, flags); |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
712 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
713 | { | |
714 | struct dwc3_ep *dep; | |
715 | struct dwc3 *dwc; | |
716 | unsigned long flags; | |
717 | int ret; | |
718 | ||
719 | if (!ep) { | |
720 | pr_debug("dwc3: invalid parameters\n"); | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | dep = to_dwc3_ep(ep); | |
725 | dwc = dep->dwc; | |
726 | ||
95ca961c FB |
727 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
728 | "%s is already disabled\n", | |
729 | dep->name)) | |
72246da4 | 730 | return 0; |
72246da4 | 731 | |
72246da4 FB |
732 | spin_lock_irqsave(&dwc->lock, flags); |
733 | ret = __dwc3_gadget_ep_disable(dep); | |
734 | spin_unlock_irqrestore(&dwc->lock, flags); | |
735 | ||
736 | return ret; | |
737 | } | |
738 | ||
739 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
740 | gfp_t gfp_flags) | |
741 | { | |
742 | struct dwc3_request *req; | |
743 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
744 | |
745 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 746 | if (!req) |
72246da4 | 747 | return NULL; |
72246da4 FB |
748 | |
749 | req->epnum = dep->number; | |
750 | req->dep = dep; | |
72246da4 | 751 | |
2c4cbe6e FB |
752 | trace_dwc3_alloc_request(req); |
753 | ||
72246da4 FB |
754 | return &req->request; |
755 | } | |
756 | ||
757 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
758 | struct usb_request *request) | |
759 | { | |
760 | struct dwc3_request *req = to_dwc3_request(request); | |
761 | ||
2c4cbe6e | 762 | trace_dwc3_free_request(req); |
72246da4 FB |
763 | kfree(req); |
764 | } | |
765 | ||
c71fc37c FB |
766 | /** |
767 | * dwc3_prepare_one_trb - setup one TRB from one request | |
768 | * @dep: endpoint for which this request is prepared | |
769 | * @req: dwc3_request pointer | |
770 | */ | |
68e823e2 | 771 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 772 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 773 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 774 | { |
f6bafc6a | 775 | struct dwc3_trb *trb; |
c71fc37c | 776 | |
73815280 | 777 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s", |
eeb720fb FB |
778 | dep->name, req, (unsigned long long) dma, |
779 | length, last ? " last" : "", | |
780 | chain ? " chain" : ""); | |
781 | ||
915e202a | 782 | |
4faf7550 | 783 | trb = &dep->trb_pool[dep->trb_enqueue]; |
c71fc37c | 784 | |
eeb720fb | 785 | if (!req->trb) { |
aa3342c8 | 786 | dwc3_gadget_move_started_request(req); |
f6bafc6a FB |
787 | req->trb = trb; |
788 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
4faf7550 | 789 | req->first_trb_index = dep->trb_enqueue; |
eeb720fb | 790 | } |
c71fc37c | 791 | |
ef966b9d | 792 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 793 | |
f6bafc6a FB |
794 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
795 | trb->bpl = lower_32_bits(dma); | |
796 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 797 | |
16e78db7 | 798 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 799 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 800 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
801 | break; |
802 | ||
803 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
804 | if (!node) |
805 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
806 | else | |
807 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
ca4d44ea FB |
808 | |
809 | /* always enable Interrupt on Missed ISOC */ | |
810 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
811 | break; |
812 | ||
813 | case USB_ENDPOINT_XFER_BULK: | |
814 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 815 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
816 | break; |
817 | default: | |
818 | /* | |
819 | * This is only possible with faulty memory because we | |
820 | * checked it already :) | |
821 | */ | |
822 | BUG(); | |
823 | } | |
824 | ||
ca4d44ea FB |
825 | /* always enable Continue on Short Packet */ |
826 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 827 | |
f3af3651 | 828 | if (!req->request.no_interrupt && !chain) |
ca4d44ea | 829 | trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI; |
f3af3651 | 830 | |
ca4d44ea | 831 | if (last) |
e5ba5ec8 | 832 | trb->ctrl |= DWC3_TRB_CTRL_LST; |
c71fc37c | 833 | |
e5ba5ec8 PA |
834 | if (chain) |
835 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
836 | ||
16e78db7 | 837 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 838 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 839 | |
f6bafc6a | 840 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
841 | |
842 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
843 | } |
844 | ||
c4233573 FB |
845 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) |
846 | { | |
847 | struct dwc3_trb *tmp; | |
848 | ||
849 | /* | |
850 | * If enqueue & dequeue are equal than it is either full or empty. | |
851 | * | |
852 | * One way to know for sure is if the TRB right before us has HWO bit | |
853 | * set or not. If it has, then we're definitely full and can't fit any | |
854 | * more transfers in our ring. | |
855 | */ | |
856 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
857 | /* If we're full, enqueue/dequeue are > 0 */ | |
858 | if (dep->trb_enqueue) { | |
859 | tmp = &dep->trb_pool[dep->trb_enqueue - 1]; | |
860 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
861 | return 0; | |
862 | } | |
863 | ||
864 | return DWC3_TRB_NUM - 1; | |
865 | } | |
866 | ||
867 | return dep->trb_dequeue - dep->trb_enqueue; | |
868 | } | |
869 | ||
5ee85d89 FB |
870 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
871 | struct dwc3_request *req, unsigned int trbs_left) | |
872 | { | |
873 | struct usb_request *request = &req->request; | |
874 | struct scatterlist *sg = request->sg; | |
875 | struct scatterlist *s; | |
876 | unsigned int last = false; | |
877 | unsigned int length; | |
878 | dma_addr_t dma; | |
879 | int i; | |
880 | ||
881 | for_each_sg(sg, s, request->num_mapped_sgs, i) { | |
882 | unsigned chain = true; | |
883 | ||
884 | length = sg_dma_len(s); | |
885 | dma = sg_dma_address(s); | |
886 | ||
887 | if (sg_is_last(s)) { | |
888 | if (list_is_last(&req->list, &dep->pending_list)) | |
889 | last = true; | |
890 | ||
891 | chain = false; | |
892 | } | |
893 | ||
894 | if (!trbs_left) | |
895 | last = true; | |
896 | ||
897 | if (last) | |
898 | chain = false; | |
899 | ||
900 | dwc3_prepare_one_trb(dep, req, dma, length, | |
901 | last, chain, i); | |
902 | ||
903 | if (last) | |
904 | break; | |
905 | } | |
906 | } | |
907 | ||
908 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
909 | struct dwc3_request *req, unsigned int trbs_left) | |
910 | { | |
911 | unsigned int last = false; | |
912 | unsigned int length; | |
913 | dma_addr_t dma; | |
914 | ||
915 | dma = req->request.dma; | |
916 | length = req->request.length; | |
917 | ||
918 | if (!trbs_left) | |
919 | last = true; | |
920 | ||
921 | /* Is this the last request? */ | |
922 | if (list_is_last(&req->list, &dep->pending_list)) | |
923 | last = true; | |
924 | ||
925 | dwc3_prepare_one_trb(dep, req, dma, length, | |
926 | last, false, 0); | |
927 | } | |
928 | ||
72246da4 FB |
929 | /* |
930 | * dwc3_prepare_trbs - setup TRBs from requests | |
931 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 932 | * |
1d046793 PZ |
933 | * The function goes through the requests list and sets up TRBs for the |
934 | * transfers. The function returns once there are no more TRBs available or | |
935 | * it runs out of requests. | |
72246da4 | 936 | */ |
c4233573 | 937 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 938 | { |
68e823e2 | 939 | struct dwc3_request *req, *n; |
72246da4 FB |
940 | u32 trbs_left; |
941 | ||
942 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
943 | ||
c4233573 | 944 | trbs_left = dwc3_calc_trbs_left(dep); |
72246da4 | 945 | |
aa3342c8 | 946 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
5ee85d89 FB |
947 | if (req->request.num_mapped_sgs > 0) |
948 | dwc3_prepare_one_trb_sg(dep, req, trbs_left--); | |
949 | else | |
950 | dwc3_prepare_one_trb_linear(dep, req, trbs_left--); | |
72246da4 | 951 | |
5ee85d89 FB |
952 | if (!trbs_left) |
953 | return; | |
72246da4 | 954 | } |
72246da4 FB |
955 | } |
956 | ||
4fae2e3e | 957 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) |
72246da4 FB |
958 | { |
959 | struct dwc3_gadget_ep_cmd_params params; | |
960 | struct dwc3_request *req; | |
961 | struct dwc3 *dwc = dep->dwc; | |
4fae2e3e | 962 | int starting; |
72246da4 FB |
963 | int ret; |
964 | u32 cmd; | |
965 | ||
4fae2e3e | 966 | starting = !(dep->flags & DWC3_EP_BUSY); |
72246da4 | 967 | |
4fae2e3e FB |
968 | dwc3_prepare_trbs(dep); |
969 | req = next_request(&dep->started_list); | |
72246da4 FB |
970 | if (!req) { |
971 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
972 | return 0; | |
973 | } | |
974 | ||
975 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 976 | |
4fae2e3e | 977 | if (starting) { |
1877d6c9 PA |
978 | params.param0 = upper_32_bits(req->trb_dma); |
979 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 980 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 981 | } else { |
72246da4 | 982 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 983 | } |
72246da4 FB |
984 | |
985 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
2cd4718d | 986 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 987 | if (ret < 0) { |
72246da4 FB |
988 | /* |
989 | * FIXME we need to iterate over the list of requests | |
990 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 991 | * requests instead of what we do now. |
72246da4 | 992 | */ |
0fc9a1be FB |
993 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
994 | req->direction); | |
72246da4 FB |
995 | list_del(&req->list); |
996 | return ret; | |
997 | } | |
998 | ||
999 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1000 | |
4fae2e3e | 1001 | if (starting) { |
2eb88016 | 1002 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
b4996a86 | 1003 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1004 | } |
25b8ff68 | 1005 | |
72246da4 FB |
1006 | return 0; |
1007 | } | |
1008 | ||
d6d6ec7b PA |
1009 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1010 | struct dwc3_ep *dep, u32 cur_uf) | |
1011 | { | |
1012 | u32 uf; | |
1013 | ||
aa3342c8 | 1014 | if (list_empty(&dep->pending_list)) { |
73815280 FB |
1015 | dwc3_trace(trace_dwc3_gadget, |
1016 | "ISOC ep %s run out for requests", | |
1017 | dep->name); | |
f4a53c55 | 1018 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1019 | return; |
1020 | } | |
1021 | ||
1022 | /* 4 micro frames in the future */ | |
1023 | uf = cur_uf + dep->interval * 4; | |
1024 | ||
4fae2e3e | 1025 | __dwc3_gadget_kick_transfer(dep, uf); |
d6d6ec7b PA |
1026 | } |
1027 | ||
1028 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1029 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1030 | { | |
1031 | u32 cur_uf, mask; | |
1032 | ||
1033 | mask = ~(dep->interval - 1); | |
1034 | cur_uf = event->parameters & mask; | |
1035 | ||
1036 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1037 | } | |
1038 | ||
72246da4 FB |
1039 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1040 | { | |
0fc9a1be FB |
1041 | struct dwc3 *dwc = dep->dwc; |
1042 | int ret; | |
1043 | ||
bb423984 | 1044 | if (!dep->endpoint.desc) { |
ec5e795c FB |
1045 | dwc3_trace(trace_dwc3_gadget, |
1046 | "trying to queue request %p to disabled %s\n", | |
bb423984 FB |
1047 | &req->request, dep->endpoint.name); |
1048 | return -ESHUTDOWN; | |
1049 | } | |
1050 | ||
1051 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1052 | &req->request, req->dep->name)) { | |
ec5e795c FB |
1053 | dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n", |
1054 | &req->request, req->dep->name); | |
bb423984 FB |
1055 | return -EINVAL; |
1056 | } | |
1057 | ||
fc8bb91b FB |
1058 | pm_runtime_get(dwc->dev); |
1059 | ||
72246da4 FB |
1060 | req->request.actual = 0; |
1061 | req->request.status = -EINPROGRESS; | |
1062 | req->direction = dep->direction; | |
1063 | req->epnum = dep->number; | |
1064 | ||
fe84f522 FB |
1065 | trace_dwc3_ep_queue(req); |
1066 | ||
72246da4 FB |
1067 | /* |
1068 | * We only add to our list of requests now and | |
1069 | * start consuming the list once we get XferNotReady | |
1070 | * IRQ. | |
1071 | * | |
1072 | * That way, we avoid doing anything that we don't need | |
1073 | * to do now and defer it until the point we receive a | |
1074 | * particular token from the Host side. | |
1075 | * | |
1076 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1077 | * many NAKs. |
72246da4 | 1078 | */ |
0fc9a1be FB |
1079 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1080 | dep->direction); | |
1081 | if (ret) | |
1082 | return ret; | |
1083 | ||
aa3342c8 | 1084 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1085 | |
1d6a3918 FB |
1086 | /* |
1087 | * If there are no pending requests and the endpoint isn't already | |
1088 | * busy, we will just start the request straight away. | |
1089 | * | |
1090 | * This will save one IRQ (XFER_NOT_READY) and possibly make it a | |
1091 | * little bit faster. | |
1092 | */ | |
1093 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
62e345ae | 1094 | !usb_endpoint_xfer_int(dep->endpoint.desc) && |
1d6a3918 | 1095 | !(dep->flags & DWC3_EP_BUSY)) { |
4fae2e3e | 1096 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
a8f32817 | 1097 | goto out; |
1d6a3918 FB |
1098 | } |
1099 | ||
72246da4 | 1100 | /* |
b511e5e7 | 1101 | * There are a few special cases: |
72246da4 | 1102 | * |
f898ae09 PZ |
1103 | * 1. XferNotReady with empty list of requests. We need to kick the |
1104 | * transfer here in that situation, otherwise we will be NAKing | |
1105 | * forever. If we get XferNotReady before gadget driver has a | |
1106 | * chance to queue a request, we will ACK the IRQ but won't be | |
1107 | * able to receive the data until the next request is queued. | |
1108 | * The following code is handling exactly that. | |
72246da4 | 1109 | * |
72246da4 FB |
1110 | */ |
1111 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1112 | /* |
1113 | * If xfernotready is already elapsed and it is a case | |
1114 | * of isoc transfer, then issue END TRANSFER, so that | |
1115 | * you can receive xfernotready again and can have | |
1116 | * notion of current microframe. | |
1117 | */ | |
1118 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
aa3342c8 | 1119 | if (list_empty(&dep->started_list)) { |
b992e681 | 1120 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1121 | dep->flags = DWC3_EP_ENABLED; |
1122 | } | |
f4a53c55 PA |
1123 | return 0; |
1124 | } | |
1125 | ||
4fae2e3e | 1126 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
89185916 FB |
1127 | if (!ret) |
1128 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1129 | ||
a8f32817 | 1130 | goto out; |
b511e5e7 | 1131 | } |
72246da4 | 1132 | |
b511e5e7 FB |
1133 | /* |
1134 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1135 | * kick the transfer here after queuing a request, otherwise the | |
1136 | * core may not see the modified TRB(s). | |
1137 | */ | |
1138 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1139 | (dep->flags & DWC3_EP_BUSY) && |
1140 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 | 1141 | WARN_ON_ONCE(!dep->resource_index); |
4fae2e3e | 1142 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index); |
a8f32817 | 1143 | goto out; |
a0925324 | 1144 | } |
72246da4 | 1145 | |
b997ada5 FB |
1146 | /* |
1147 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1148 | * right away, otherwise host will not know we have streams to be | |
1149 | * handled. | |
1150 | */ | |
a8f32817 | 1151 | if (dep->stream_capable) |
4fae2e3e | 1152 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
b997ada5 | 1153 | |
a8f32817 FB |
1154 | out: |
1155 | if (ret && ret != -EBUSY) | |
ec5e795c FB |
1156 | dwc3_trace(trace_dwc3_gadget, |
1157 | "%s: failed to kick transfers\n", | |
a8f32817 FB |
1158 | dep->name); |
1159 | if (ret == -EBUSY) | |
1160 | ret = 0; | |
1161 | ||
1162 | return ret; | |
72246da4 FB |
1163 | } |
1164 | ||
04c03d10 FB |
1165 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, |
1166 | struct usb_request *request) | |
1167 | { | |
1168 | dwc3_gadget_ep_free_request(ep, request); | |
1169 | } | |
1170 | ||
1171 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1172 | { | |
1173 | struct dwc3_request *req; | |
1174 | struct usb_request *request; | |
1175 | struct usb_ep *ep = &dep->endpoint; | |
1176 | ||
1177 | dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n"); | |
1178 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); | |
1179 | if (!request) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | request->length = 0; | |
1183 | request->buf = dwc->zlp_buf; | |
1184 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1185 | ||
1186 | req = to_dwc3_request(request); | |
1187 | ||
1188 | return __dwc3_gadget_ep_queue(dep, req); | |
1189 | } | |
1190 | ||
72246da4 FB |
1191 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, |
1192 | gfp_t gfp_flags) | |
1193 | { | |
1194 | struct dwc3_request *req = to_dwc3_request(request); | |
1195 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1196 | struct dwc3 *dwc = dep->dwc; | |
1197 | ||
1198 | unsigned long flags; | |
1199 | ||
1200 | int ret; | |
1201 | ||
fdee4eba | 1202 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1203 | ret = __dwc3_gadget_ep_queue(dep, req); |
04c03d10 FB |
1204 | |
1205 | /* | |
1206 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1207 | * setting request->zero, instead of doing magic, we will just queue an | |
1208 | * extra usb_request ourselves so that it gets handled the same way as | |
1209 | * any other request. | |
1210 | */ | |
d9261898 JY |
1211 | if (ret == 0 && request->zero && request->length && |
1212 | (request->length % ep->maxpacket == 0)) | |
04c03d10 FB |
1213 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); |
1214 | ||
72246da4 FB |
1215 | spin_unlock_irqrestore(&dwc->lock, flags); |
1216 | ||
1217 | return ret; | |
1218 | } | |
1219 | ||
1220 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1221 | struct usb_request *request) | |
1222 | { | |
1223 | struct dwc3_request *req = to_dwc3_request(request); | |
1224 | struct dwc3_request *r = NULL; | |
1225 | ||
1226 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1227 | struct dwc3 *dwc = dep->dwc; | |
1228 | ||
1229 | unsigned long flags; | |
1230 | int ret = 0; | |
1231 | ||
2c4cbe6e FB |
1232 | trace_dwc3_ep_dequeue(req); |
1233 | ||
72246da4 FB |
1234 | spin_lock_irqsave(&dwc->lock, flags); |
1235 | ||
aa3342c8 | 1236 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1237 | if (r == req) |
1238 | break; | |
1239 | } | |
1240 | ||
1241 | if (r != req) { | |
aa3342c8 | 1242 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1243 | if (r == req) |
1244 | break; | |
1245 | } | |
1246 | if (r == req) { | |
1247 | /* wait until it is processed */ | |
b992e681 | 1248 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1249 | goto out1; |
72246da4 FB |
1250 | } |
1251 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1252 | request, ep->name); | |
1253 | ret = -EINVAL; | |
1254 | goto out0; | |
1255 | } | |
1256 | ||
e8d4e8be | 1257 | out1: |
72246da4 FB |
1258 | /* giveback the request */ |
1259 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1260 | ||
1261 | out0: | |
1262 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1263 | ||
1264 | return ret; | |
1265 | } | |
1266 | ||
7a608559 | 1267 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1268 | { |
1269 | struct dwc3_gadget_ep_cmd_params params; | |
1270 | struct dwc3 *dwc = dep->dwc; | |
1271 | int ret; | |
1272 | ||
5ad02fb8 FB |
1273 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1274 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1275 | return -EINVAL; | |
1276 | } | |
1277 | ||
72246da4 FB |
1278 | memset(¶ms, 0x00, sizeof(params)); |
1279 | ||
1280 | if (value) { | |
7a608559 | 1281 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
aa3342c8 FB |
1282 | (!list_empty(&dep->started_list) || |
1283 | !list_empty(&dep->pending_list)))) { | |
ec5e795c | 1284 | dwc3_trace(trace_dwc3_gadget, |
052ba52e | 1285 | "%s: pending request, cannot halt", |
7a608559 FB |
1286 | dep->name); |
1287 | return -EAGAIN; | |
1288 | } | |
1289 | ||
2cd4718d FB |
1290 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1291 | ¶ms); | |
72246da4 | 1292 | if (ret) |
3f89204b | 1293 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1294 | dep->name); |
1295 | else | |
1296 | dep->flags |= DWC3_EP_STALL; | |
1297 | } else { | |
2cd4718d | 1298 | |
50c763f8 | 1299 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1300 | if (ret) |
3f89204b | 1301 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1302 | dep->name); |
1303 | else | |
a535d81c | 1304 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1305 | } |
5275455a | 1306 | |
72246da4 FB |
1307 | return ret; |
1308 | } | |
1309 | ||
1310 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1311 | { | |
1312 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1313 | struct dwc3 *dwc = dep->dwc; | |
1314 | ||
1315 | unsigned long flags; | |
1316 | ||
1317 | int ret; | |
1318 | ||
1319 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1320 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1321 | spin_unlock_irqrestore(&dwc->lock, flags); |
1322 | ||
1323 | return ret; | |
1324 | } | |
1325 | ||
1326 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1327 | { | |
1328 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1329 | struct dwc3 *dwc = dep->dwc; |
1330 | unsigned long flags; | |
95aa4e8d | 1331 | int ret; |
72246da4 | 1332 | |
249a4569 | 1333 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1334 | dep->flags |= DWC3_EP_WEDGE; |
1335 | ||
08f0d966 | 1336 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1337 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1338 | else |
7a608559 | 1339 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1340 | spin_unlock_irqrestore(&dwc->lock, flags); |
1341 | ||
1342 | return ret; | |
72246da4 FB |
1343 | } |
1344 | ||
1345 | /* -------------------------------------------------------------------------- */ | |
1346 | ||
1347 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1348 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1349 | .bDescriptorType = USB_DT_ENDPOINT, | |
1350 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1351 | }; | |
1352 | ||
1353 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1354 | .enable = dwc3_gadget_ep0_enable, | |
1355 | .disable = dwc3_gadget_ep0_disable, | |
1356 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1357 | .free_request = dwc3_gadget_ep_free_request, | |
1358 | .queue = dwc3_gadget_ep0_queue, | |
1359 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1360 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1361 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1362 | }; | |
1363 | ||
1364 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1365 | .enable = dwc3_gadget_ep_enable, | |
1366 | .disable = dwc3_gadget_ep_disable, | |
1367 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1368 | .free_request = dwc3_gadget_ep_free_request, | |
1369 | .queue = dwc3_gadget_ep_queue, | |
1370 | .dequeue = dwc3_gadget_ep_dequeue, | |
1371 | .set_halt = dwc3_gadget_ep_set_halt, | |
1372 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1373 | }; | |
1374 | ||
1375 | /* -------------------------------------------------------------------------- */ | |
1376 | ||
1377 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1378 | { | |
1379 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1380 | u32 reg; | |
1381 | ||
1382 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1383 | return DWC3_DSTS_SOFFN(reg); | |
1384 | } | |
1385 | ||
218ef7b6 | 1386 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1387 | { |
72246da4 | 1388 | unsigned long timeout; |
72246da4 | 1389 | |
218ef7b6 | 1390 | int ret; |
72246da4 FB |
1391 | u32 reg; |
1392 | ||
72246da4 FB |
1393 | u8 link_state; |
1394 | u8 speed; | |
1395 | ||
72246da4 FB |
1396 | /* |
1397 | * According to the Databook Remote wakeup request should | |
1398 | * be issued only when the device is in early suspend state. | |
1399 | * | |
1400 | * We can check that via USB Link State bits in DSTS register. | |
1401 | */ | |
1402 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1403 | ||
1404 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c JY |
1405 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
1406 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
ec5e795c | 1407 | dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n"); |
6b742899 | 1408 | return 0; |
72246da4 FB |
1409 | } |
1410 | ||
1411 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1412 | ||
1413 | switch (link_state) { | |
1414 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1415 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1416 | break; | |
1417 | default: | |
ec5e795c FB |
1418 | dwc3_trace(trace_dwc3_gadget, |
1419 | "can't wakeup from '%s'\n", | |
1420 | dwc3_gadget_link_string(link_state)); | |
218ef7b6 | 1421 | return -EINVAL; |
72246da4 FB |
1422 | } |
1423 | ||
8598bde7 FB |
1424 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1425 | if (ret < 0) { | |
1426 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1427 | return ret; |
8598bde7 | 1428 | } |
72246da4 | 1429 | |
802fde98 PZ |
1430 | /* Recent versions do this automatically */ |
1431 | if (dwc->revision < DWC3_REVISION_194A) { | |
1432 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1433 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1434 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1435 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1436 | } | |
72246da4 | 1437 | |
1d046793 | 1438 | /* poll until Link State changes to ON */ |
72246da4 FB |
1439 | timeout = jiffies + msecs_to_jiffies(100); |
1440 | ||
1d046793 | 1441 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1442 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1443 | ||
1444 | /* in HS, means ON */ | |
1445 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1446 | break; | |
1447 | } | |
1448 | ||
1449 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1450 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1451 | return -EINVAL; |
72246da4 FB |
1452 | } |
1453 | ||
218ef7b6 FB |
1454 | return 0; |
1455 | } | |
1456 | ||
1457 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1458 | { | |
1459 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1460 | unsigned long flags; | |
1461 | int ret; | |
1462 | ||
1463 | spin_lock_irqsave(&dwc->lock, flags); | |
1464 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1465 | spin_unlock_irqrestore(&dwc->lock, flags); |
1466 | ||
1467 | return ret; | |
1468 | } | |
1469 | ||
1470 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1471 | int is_selfpowered) | |
1472 | { | |
1473 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1474 | unsigned long flags; |
72246da4 | 1475 | |
249a4569 | 1476 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1477 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1478 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1479 | |
1480 | return 0; | |
1481 | } | |
1482 | ||
7b2a0368 | 1483 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1484 | { |
1485 | u32 reg; | |
61d58242 | 1486 | u32 timeout = 500; |
72246da4 | 1487 | |
fc8bb91b FB |
1488 | if (pm_runtime_suspended(dwc->dev)) |
1489 | return 0; | |
1490 | ||
72246da4 | 1491 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1492 | if (is_on) { |
802fde98 PZ |
1493 | if (dwc->revision <= DWC3_REVISION_187A) { |
1494 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1495 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1496 | } | |
1497 | ||
1498 | if (dwc->revision >= DWC3_REVISION_194A) | |
1499 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1500 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1501 | |
1502 | if (dwc->has_hibernation) | |
1503 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1504 | ||
9fcb3bd8 | 1505 | dwc->pullups_connected = true; |
8db7ed15 | 1506 | } else { |
72246da4 | 1507 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1508 | |
1509 | if (dwc->has_hibernation && !suspend) | |
1510 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1511 | ||
9fcb3bd8 | 1512 | dwc->pullups_connected = false; |
8db7ed15 | 1513 | } |
72246da4 FB |
1514 | |
1515 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1516 | ||
1517 | do { | |
1518 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1519 | if (is_on) { | |
1520 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1521 | break; | |
1522 | } else { | |
1523 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1524 | break; | |
1525 | } | |
72246da4 FB |
1526 | timeout--; |
1527 | if (!timeout) | |
6f17f74b | 1528 | return -ETIMEDOUT; |
61d58242 | 1529 | udelay(1); |
72246da4 FB |
1530 | } while (1); |
1531 | ||
73815280 | 1532 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", |
72246da4 FB |
1533 | dwc->gadget_driver |
1534 | ? dwc->gadget_driver->function : "no-function", | |
1535 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1536 | |
1537 | return 0; | |
72246da4 FB |
1538 | } |
1539 | ||
1540 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1541 | { | |
1542 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1543 | unsigned long flags; | |
6f17f74b | 1544 | int ret; |
72246da4 FB |
1545 | |
1546 | is_on = !!is_on; | |
1547 | ||
1548 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1549 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1550 | spin_unlock_irqrestore(&dwc->lock, flags); |
1551 | ||
6f17f74b | 1552 | return ret; |
72246da4 FB |
1553 | } |
1554 | ||
8698e2ac FB |
1555 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1556 | { | |
1557 | u32 reg; | |
1558 | ||
1559 | /* Enable all but Start and End of Frame IRQs */ | |
1560 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1561 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1562 | DWC3_DEVTEN_CMDCMPLTEN | | |
1563 | DWC3_DEVTEN_ERRTICERREN | | |
1564 | DWC3_DEVTEN_WKUPEVTEN | | |
1565 | DWC3_DEVTEN_ULSTCNGEN | | |
1566 | DWC3_DEVTEN_CONNECTDONEEN | | |
1567 | DWC3_DEVTEN_USBRSTEN | | |
1568 | DWC3_DEVTEN_DISCONNEVTEN); | |
1569 | ||
1570 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1571 | } | |
1572 | ||
1573 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1574 | { | |
1575 | /* mask all interrupts */ | |
1576 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1577 | } | |
1578 | ||
1579 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1580 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1581 | |
4e99472b FB |
1582 | /** |
1583 | * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG | |
1584 | * dwc: pointer to our context structure | |
1585 | * | |
1586 | * The following looks like complex but it's actually very simple. In order to | |
1587 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1588 | * gonna use RxFIFO size. | |
1589 | * | |
1590 | * To calculate RxFIFO size we need two numbers: | |
1591 | * MDWIDTH = size, in bits, of the internal memory bus | |
1592 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1593 | * | |
1594 | * Given these two numbers, the formula is simple: | |
1595 | * | |
1596 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1597 | * | |
1598 | * 24 bytes is for 3x SETUP packets | |
1599 | * 16 bytes is a clock domain crossing tolerance | |
1600 | * | |
1601 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1602 | */ | |
1603 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1604 | { | |
1605 | u32 ram2_depth; | |
1606 | u32 mdwidth; | |
1607 | u32 nump; | |
1608 | u32 reg; | |
1609 | ||
1610 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1611 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1612 | ||
1613 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1614 | nump = min_t(u32, nump, 16); | |
1615 | ||
1616 | /* update NumP */ | |
1617 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1618 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1619 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1620 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1621 | } | |
1622 | ||
d7be2952 | 1623 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1624 | { |
72246da4 | 1625 | struct dwc3_ep *dep; |
72246da4 FB |
1626 | int ret = 0; |
1627 | u32 reg; | |
1628 | ||
72246da4 FB |
1629 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1630 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1631 | |
1632 | /** | |
1633 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1634 | * which would cause metastability state on Run/Stop | |
1635 | * bit if we try to force the IP to USB2-only mode. | |
1636 | * | |
1637 | * Because of that, we cannot configure the IP to any | |
1638 | * speed other than the SuperSpeed | |
1639 | * | |
1640 | * Refers to: | |
1641 | * | |
1642 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1643 | * USB 2.0 Mode | |
1644 | */ | |
f7e846f0 | 1645 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1646 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1647 | } else { |
1648 | switch (dwc->maximum_speed) { | |
1649 | case USB_SPEED_LOW: | |
1650 | reg |= DWC3_DSTS_LOWSPEED; | |
1651 | break; | |
1652 | case USB_SPEED_FULL: | |
1653 | reg |= DWC3_DSTS_FULLSPEED1; | |
1654 | break; | |
1655 | case USB_SPEED_HIGH: | |
1656 | reg |= DWC3_DSTS_HIGHSPEED; | |
1657 | break; | |
7580862b JY |
1658 | case USB_SPEED_SUPER_PLUS: |
1659 | reg |= DWC3_DSTS_SUPERSPEED_PLUS; | |
1660 | break; | |
f7e846f0 | 1661 | default: |
77966eb8 JY |
1662 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1663 | dwc->maximum_speed); | |
1664 | /* fall through */ | |
1665 | case USB_SPEED_SUPER: | |
1666 | reg |= DWC3_DCFG_SUPERSPEED; | |
1667 | break; | |
f7e846f0 FB |
1668 | } |
1669 | } | |
72246da4 FB |
1670 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1671 | ||
2a58f9c1 FB |
1672 | /* |
1673 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1674 | * field instead of letting dwc3 itself calculate that automatically. | |
1675 | * | |
1676 | * This way, we maximize the chances that we'll be able to get several | |
1677 | * bursts of data without going through any sort of endpoint throttling. | |
1678 | */ | |
1679 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1680 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1681 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1682 | ||
4e99472b FB |
1683 | dwc3_gadget_setup_nump(dwc); |
1684 | ||
72246da4 FB |
1685 | /* Start with SuperSpeed Default */ |
1686 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1687 | ||
1688 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1689 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1690 | false); | |
72246da4 FB |
1691 | if (ret) { |
1692 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1693 | goto err0; |
72246da4 FB |
1694 | } |
1695 | ||
1696 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1697 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1698 | false); | |
72246da4 FB |
1699 | if (ret) { |
1700 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1701 | goto err1; |
72246da4 FB |
1702 | } |
1703 | ||
1704 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1705 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1706 | dwc3_ep0_out_start(dwc); |
1707 | ||
8698e2ac FB |
1708 | dwc3_gadget_enable_irq(dwc); |
1709 | ||
72246da4 FB |
1710 | return 0; |
1711 | ||
b0d7ffd4 | 1712 | err1: |
d7be2952 | 1713 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1714 | |
1715 | err0: | |
72246da4 FB |
1716 | return ret; |
1717 | } | |
1718 | ||
d7be2952 FB |
1719 | static int dwc3_gadget_start(struct usb_gadget *g, |
1720 | struct usb_gadget_driver *driver) | |
72246da4 FB |
1721 | { |
1722 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1723 | unsigned long flags; | |
d7be2952 | 1724 | int ret = 0; |
8698e2ac | 1725 | int irq; |
72246da4 | 1726 | |
d7be2952 FB |
1727 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1728 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
1729 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1730 | if (ret) { | |
1731 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1732 | irq, ret); | |
1733 | goto err0; | |
1734 | } | |
3f308d17 | 1735 | dwc->irq_gadget = irq; |
d7be2952 | 1736 | |
72246da4 | 1737 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
1738 | if (dwc->gadget_driver) { |
1739 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1740 | dwc->gadget.name, | |
1741 | dwc->gadget_driver->driver.name); | |
1742 | ret = -EBUSY; | |
1743 | goto err1; | |
1744 | } | |
1745 | ||
1746 | dwc->gadget_driver = driver; | |
1747 | ||
fc8bb91b FB |
1748 | if (pm_runtime_active(dwc->dev)) |
1749 | __dwc3_gadget_start(dwc); | |
1750 | ||
d7be2952 FB |
1751 | spin_unlock_irqrestore(&dwc->lock, flags); |
1752 | ||
1753 | return 0; | |
1754 | ||
1755 | err1: | |
1756 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1757 | free_irq(irq, dwc); | |
1758 | ||
1759 | err0: | |
1760 | return ret; | |
1761 | } | |
72246da4 | 1762 | |
d7be2952 FB |
1763 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
1764 | { | |
8698e2ac | 1765 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1766 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1767 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 1768 | } |
72246da4 | 1769 | |
d7be2952 FB |
1770 | static int dwc3_gadget_stop(struct usb_gadget *g) |
1771 | { | |
1772 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1773 | unsigned long flags; | |
72246da4 | 1774 | |
d7be2952 FB |
1775 | spin_lock_irqsave(&dwc->lock, flags); |
1776 | __dwc3_gadget_stop(dwc); | |
1777 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1778 | spin_unlock_irqrestore(&dwc->lock, flags); |
1779 | ||
3f308d17 | 1780 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 1781 | |
72246da4 FB |
1782 | return 0; |
1783 | } | |
802fde98 | 1784 | |
72246da4 FB |
1785 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1786 | .get_frame = dwc3_gadget_get_frame, | |
1787 | .wakeup = dwc3_gadget_wakeup, | |
1788 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1789 | .pullup = dwc3_gadget_pullup, | |
1790 | .udc_start = dwc3_gadget_start, | |
1791 | .udc_stop = dwc3_gadget_stop, | |
1792 | }; | |
1793 | ||
1794 | /* -------------------------------------------------------------------------- */ | |
1795 | ||
6a1e3ef4 FB |
1796 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1797 | u8 num, u32 direction) | |
72246da4 FB |
1798 | { |
1799 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1800 | u8 i; |
72246da4 | 1801 | |
6a1e3ef4 | 1802 | for (i = 0; i < num; i++) { |
d07fa665 | 1803 | u8 epnum = (i << 1) | (direction ? 1 : 0); |
72246da4 | 1804 | |
72246da4 | 1805 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1806 | if (!dep) |
72246da4 | 1807 | return -ENOMEM; |
72246da4 FB |
1808 | |
1809 | dep->dwc = dwc; | |
1810 | dep->number = epnum; | |
9aa62ae4 | 1811 | dep->direction = !!direction; |
2eb88016 | 1812 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); |
72246da4 FB |
1813 | dwc->eps[epnum] = dep; |
1814 | ||
1815 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1816 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1817 | |
72246da4 | 1818 | dep->endpoint.name = dep->name; |
74674cbf | 1819 | spin_lock_init(&dep->lock); |
72246da4 | 1820 | |
73815280 | 1821 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); |
653df35e | 1822 | |
72246da4 | 1823 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1824 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1825 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1826 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1827 | if (!epnum) | |
1828 | dwc->gadget.ep0 = &dep->endpoint; | |
1829 | } else { | |
1830 | int ret; | |
1831 | ||
e117e742 | 1832 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1833 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1834 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1835 | list_add_tail(&dep->endpoint.ep_list, | |
1836 | &dwc->gadget.ep_list); | |
1837 | ||
1838 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1839 | if (ret) |
72246da4 | 1840 | return ret; |
72246da4 | 1841 | } |
25b8ff68 | 1842 | |
a474d3b7 RB |
1843 | if (epnum == 0 || epnum == 1) { |
1844 | dep->endpoint.caps.type_control = true; | |
1845 | } else { | |
1846 | dep->endpoint.caps.type_iso = true; | |
1847 | dep->endpoint.caps.type_bulk = true; | |
1848 | dep->endpoint.caps.type_int = true; | |
1849 | } | |
1850 | ||
1851 | dep->endpoint.caps.dir_in = !!direction; | |
1852 | dep->endpoint.caps.dir_out = !direction; | |
1853 | ||
aa3342c8 FB |
1854 | INIT_LIST_HEAD(&dep->pending_list); |
1855 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
1856 | } |
1857 | ||
1858 | return 0; | |
1859 | } | |
1860 | ||
6a1e3ef4 FB |
1861 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1862 | { | |
1863 | int ret; | |
1864 | ||
1865 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1866 | ||
1867 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1868 | if (ret < 0) { | |
73815280 FB |
1869 | dwc3_trace(trace_dwc3_gadget, |
1870 | "failed to allocate OUT endpoints"); | |
6a1e3ef4 FB |
1871 | return ret; |
1872 | } | |
1873 | ||
1874 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1875 | if (ret < 0) { | |
73815280 FB |
1876 | dwc3_trace(trace_dwc3_gadget, |
1877 | "failed to allocate IN endpoints"); | |
6a1e3ef4 FB |
1878 | return ret; |
1879 | } | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | ||
72246da4 FB |
1884 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1885 | { | |
1886 | struct dwc3_ep *dep; | |
1887 | u8 epnum; | |
1888 | ||
1889 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1890 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1891 | if (!dep) |
1892 | continue; | |
5bf8fae3 GC |
1893 | /* |
1894 | * Physical endpoints 0 and 1 are special; they form the | |
1895 | * bi-directional USB endpoint 0. | |
1896 | * | |
1897 | * For those two physical endpoints, we don't allocate a TRB | |
1898 | * pool nor do we add them the endpoints list. Due to that, we | |
1899 | * shouldn't do these two operations otherwise we would end up | |
1900 | * with all sorts of bugs when removing dwc3.ko. | |
1901 | */ | |
1902 | if (epnum != 0 && epnum != 1) { | |
1903 | dwc3_free_trb_pool(dep); | |
72246da4 | 1904 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1905 | } |
72246da4 FB |
1906 | |
1907 | kfree(dep); | |
1908 | } | |
1909 | } | |
1910 | ||
72246da4 | 1911 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1912 | |
e5ba5ec8 PA |
1913 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1914 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1915 | const struct dwc3_event_depevt *event, int status) |
1916 | { | |
72246da4 FB |
1917 | unsigned int count; |
1918 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1919 | unsigned int trb_status; |
72246da4 | 1920 | |
2c4cbe6e FB |
1921 | trace_dwc3_complete_trb(dep, trb); |
1922 | ||
e5ba5ec8 PA |
1923 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1924 | /* | |
1925 | * We continue despite the error. There is not much we | |
1926 | * can do. If we don't clean it up we loop forever. If | |
1927 | * we skip the TRB then it gets overwritten after a | |
1928 | * while since we use them in a ring buffer. A BUG() | |
1929 | * would help. Lets hope that if this occurs, someone | |
1930 | * fixes the root cause instead of looking away :) | |
1931 | */ | |
1932 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1933 | dep->name, trb); | |
1934 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1935 | ||
1936 | if (dep->direction) { | |
1937 | if (count) { | |
1938 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1939 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
ec5e795c FB |
1940 | dwc3_trace(trace_dwc3_gadget, |
1941 | "%s: incomplete IN transfer\n", | |
e5ba5ec8 PA |
1942 | dep->name); |
1943 | /* | |
1944 | * If missed isoc occurred and there is | |
1945 | * no request queued then issue END | |
1946 | * TRANSFER, so that core generates | |
1947 | * next xfernotready and we will issue | |
1948 | * a fresh START TRANSFER. | |
1949 | * If there are still queued request | |
1950 | * then wait, do not issue either END | |
1951 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 1952 | * request in pending_list during |
e5ba5ec8 PA |
1953 | * giveback.If any future queued request |
1954 | * is successfully transferred then we | |
1955 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 1956 | * request in the pending_list. |
e5ba5ec8 PA |
1957 | */ |
1958 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1959 | } else { | |
1960 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1961 | dep->name); | |
1962 | status = -ECONNRESET; | |
1963 | } | |
1964 | } else { | |
1965 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1966 | } | |
1967 | } else { | |
1968 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1969 | s_pkt = 1; | |
1970 | } | |
1971 | ||
1972 | /* | |
1973 | * We assume here we will always receive the entire data block | |
1974 | * which we should receive. Meaning, if we program RX to | |
1975 | * receive 4K but we receive only 2K, we assume that's all we | |
1976 | * should receive and we simply bounce the request back to the | |
1977 | * gadget driver for further processing. | |
1978 | */ | |
1979 | req->request.actual += req->request.length - count; | |
1980 | if (s_pkt) | |
1981 | return 1; | |
1982 | if ((event->status & DEPEVT_STATUS_LST) && | |
1983 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1984 | DWC3_TRB_CTRL_HWO))) | |
1985 | return 1; | |
1986 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1987 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1988 | return 1; | |
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1993 | const struct dwc3_event_depevt *event, int status) | |
1994 | { | |
1995 | struct dwc3_request *req; | |
1996 | struct dwc3_trb *trb; | |
1997 | unsigned int slot; | |
1998 | unsigned int i; | |
1999 | int ret; | |
2000 | ||
72246da4 | 2001 | do { |
aa3342c8 | 2002 | req = next_request(&dep->started_list); |
ac7bdcc1 | 2003 | if (WARN_ON_ONCE(!req)) |
d115d705 | 2004 | return 1; |
ac7bdcc1 | 2005 | |
d115d705 VS |
2006 | i = 0; |
2007 | do { | |
53fd8818 | 2008 | slot = req->first_trb_index + i; |
36b68aae | 2009 | if (slot == DWC3_TRB_NUM - 1) |
d115d705 VS |
2010 | slot++; |
2011 | slot %= DWC3_TRB_NUM; | |
2012 | trb = &dep->trb_pool[slot]; | |
2013 | ||
2014 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
2015 | event, status); | |
2016 | if (ret) | |
2017 | break; | |
2018 | } while (++i < req->request.num_mapped_sgs); | |
2019 | ||
2020 | dwc3_gadget_giveback(dep, req, status); | |
e5ba5ec8 PA |
2021 | |
2022 | if (ret) | |
72246da4 | 2023 | break; |
d115d705 | 2024 | } while (1); |
72246da4 | 2025 | |
4cb42217 FB |
2026 | /* |
2027 | * Our endpoint might get disabled by another thread during | |
2028 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2029 | * early on so DWC3_EP_BUSY flag gets cleared | |
2030 | */ | |
2031 | if (!dep->endpoint.desc) | |
2032 | return 1; | |
2033 | ||
cdc359dd | 2034 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
2035 | list_empty(&dep->started_list)) { |
2036 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
2037 | /* |
2038 | * If there is no entry in request list then do | |
2039 | * not issue END TRANSFER now. Just set PENDING | |
2040 | * flag, so that END TRANSFER is issued when an | |
2041 | * entry is added into request list. | |
2042 | */ | |
2043 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2044 | } else { | |
b992e681 | 2045 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
2046 | dep->flags = DWC3_EP_ENABLED; |
2047 | } | |
7efea86c PA |
2048 | return 1; |
2049 | } | |
2050 | ||
9cad39fe KL |
2051 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
2052 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2053 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2054 | return 0; | |
72246da4 FB |
2055 | return 1; |
2056 | } | |
2057 | ||
2058 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 2059 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
2060 | { |
2061 | unsigned status = 0; | |
2062 | int clean_busy; | |
e18b7975 FB |
2063 | u32 is_xfer_complete; |
2064 | ||
2065 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
2066 | |
2067 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2068 | status = -ECONNRESET; | |
2069 | ||
1d046793 | 2070 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
4cb42217 | 2071 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || |
e18b7975 | 2072 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) |
72246da4 | 2073 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2074 | |
2075 | /* | |
2076 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2077 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2078 | */ | |
2079 | if (dwc->revision < DWC3_REVISION_183A) { | |
2080 | u32 reg; | |
2081 | int i; | |
2082 | ||
2083 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2084 | dep = dwc->eps[i]; |
fae2b904 FB |
2085 | |
2086 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2087 | continue; | |
2088 | ||
aa3342c8 | 2089 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2090 | return; |
2091 | } | |
2092 | ||
2093 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2094 | reg |= dwc->u1u2; | |
2095 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2096 | ||
2097 | dwc->u1u2 = 0; | |
2098 | } | |
8a1a9c9e | 2099 | |
4cb42217 FB |
2100 | /* |
2101 | * Our endpoint might get disabled by another thread during | |
2102 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2103 | * early on so DWC3_EP_BUSY flag gets cleared | |
2104 | */ | |
2105 | if (!dep->endpoint.desc) | |
2106 | return; | |
2107 | ||
e6e709b7 | 2108 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2109 | int ret; |
2110 | ||
4fae2e3e | 2111 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
8a1a9c9e FB |
2112 | if (!ret || ret == -EBUSY) |
2113 | return; | |
2114 | } | |
72246da4 FB |
2115 | } |
2116 | ||
72246da4 FB |
2117 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2118 | const struct dwc3_event_depevt *event) | |
2119 | { | |
2120 | struct dwc3_ep *dep; | |
2121 | u8 epnum = event->endpoint_number; | |
2122 | ||
2123 | dep = dwc->eps[epnum]; | |
2124 | ||
3336abb5 FB |
2125 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2126 | return; | |
2127 | ||
72246da4 FB |
2128 | if (epnum == 0 || epnum == 1) { |
2129 | dwc3_ep0_interrupt(dwc, event); | |
2130 | return; | |
2131 | } | |
2132 | ||
2133 | switch (event->endpoint_event) { | |
2134 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2135 | dep->resource_index = 0; |
c2df85ca | 2136 | |
16e78db7 | 2137 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
ec5e795c FB |
2138 | dwc3_trace(trace_dwc3_gadget, |
2139 | "%s is an Isochronous endpoint\n", | |
72246da4 FB |
2140 | dep->name); |
2141 | return; | |
2142 | } | |
2143 | ||
029d97ff | 2144 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2145 | break; |
2146 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2147 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2148 | break; |
2149 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2150 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2151 | dwc3_gadget_start_isoc(dwc, dep, event); |
2152 | } else { | |
6bb4fe12 | 2153 | int active; |
72246da4 FB |
2154 | int ret; |
2155 | ||
6bb4fe12 FB |
2156 | active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE; |
2157 | ||
73815280 | 2158 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", |
6bb4fe12 | 2159 | dep->name, active ? "Transfer Active" |
72246da4 FB |
2160 | : "Transfer Not Active"); |
2161 | ||
4fae2e3e | 2162 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
72246da4 FB |
2163 | if (!ret || ret == -EBUSY) |
2164 | return; | |
2165 | ||
ec5e795c FB |
2166 | dwc3_trace(trace_dwc3_gadget, |
2167 | "%s: failed to kick transfers\n", | |
72246da4 FB |
2168 | dep->name); |
2169 | } | |
2170 | ||
879631aa FB |
2171 | break; |
2172 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2173 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2174 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2175 | dep->name); | |
2176 | return; | |
2177 | } | |
2178 | ||
2179 | switch (event->status) { | |
2180 | case DEPEVT_STREAMEVT_FOUND: | |
73815280 FB |
2181 | dwc3_trace(trace_dwc3_gadget, |
2182 | "Stream %d found and started", | |
879631aa FB |
2183 | event->parameters); |
2184 | ||
2185 | break; | |
2186 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2187 | /* FALLTHROUGH */ | |
2188 | default: | |
ec5e795c FB |
2189 | dwc3_trace(trace_dwc3_gadget, |
2190 | "unable to find suitable stream\n"); | |
879631aa | 2191 | } |
72246da4 FB |
2192 | break; |
2193 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
ec5e795c | 2194 | dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name); |
72246da4 | 2195 | break; |
72246da4 | 2196 | case DWC3_DEPEVT_EPCMDCMPLT: |
73815280 | 2197 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); |
72246da4 FB |
2198 | break; |
2199 | } | |
2200 | } | |
2201 | ||
2202 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2203 | { | |
2204 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2205 | spin_unlock(&dwc->lock); | |
2206 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2207 | spin_lock(&dwc->lock); | |
2208 | } | |
2209 | } | |
2210 | ||
bc5ba2e0 FB |
2211 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2212 | { | |
73a30bfc | 2213 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2214 | spin_unlock(&dwc->lock); |
2215 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2216 | spin_lock(&dwc->lock); | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2221 | { | |
73a30bfc | 2222 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2223 | spin_unlock(&dwc->lock); |
2224 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2225 | spin_lock(&dwc->lock); |
8e74475b FB |
2226 | } |
2227 | } | |
2228 | ||
2229 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2230 | { | |
2231 | if (!dwc->gadget_driver) | |
2232 | return; | |
2233 | ||
2234 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2235 | spin_unlock(&dwc->lock); | |
2236 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2237 | spin_lock(&dwc->lock); |
2238 | } | |
2239 | } | |
2240 | ||
b992e681 | 2241 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2242 | { |
2243 | struct dwc3_ep *dep; | |
2244 | struct dwc3_gadget_ep_cmd_params params; | |
2245 | u32 cmd; | |
2246 | int ret; | |
2247 | ||
2248 | dep = dwc->eps[epnum]; | |
2249 | ||
b4996a86 | 2250 | if (!dep->resource_index) |
3daf74d7 PA |
2251 | return; |
2252 | ||
57911504 PA |
2253 | /* |
2254 | * NOTICE: We are violating what the Databook says about the | |
2255 | * EndTransfer command. Ideally we would _always_ wait for the | |
2256 | * EndTransfer Command Completion IRQ, but that's causing too | |
2257 | * much trouble synchronizing between us and gadget driver. | |
2258 | * | |
2259 | * We have discussed this with the IP Provider and it was | |
2260 | * suggested to giveback all requests here, but give HW some | |
2261 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2262 | * an arbitrary 100us delay for that. |
57911504 PA |
2263 | * |
2264 | * Note also that a similar handling was tested by Synopsys | |
2265 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2266 | * In short, what we're doing is: | |
2267 | * | |
2268 | * - Issue EndTransfer WITH CMDIOC bit set | |
2269 | * - Wait 100us | |
2270 | */ | |
2271 | ||
3daf74d7 | 2272 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2273 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2274 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2275 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2276 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2277 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2278 | WARN_ON_ONCE(ret); |
b4996a86 | 2279 | dep->resource_index = 0; |
041d81f4 | 2280 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2281 | udelay(100); |
72246da4 FB |
2282 | } |
2283 | ||
2284 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2285 | { | |
2286 | u32 epnum; | |
2287 | ||
2288 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2289 | struct dwc3_ep *dep; | |
2290 | ||
2291 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2292 | if (!dep) |
2293 | continue; | |
2294 | ||
72246da4 FB |
2295 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2296 | continue; | |
2297 | ||
624407f9 | 2298 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2299 | } |
2300 | } | |
2301 | ||
2302 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2303 | { | |
2304 | u32 epnum; | |
2305 | ||
2306 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2307 | struct dwc3_ep *dep; | |
72246da4 FB |
2308 | int ret; |
2309 | ||
2310 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2311 | if (!dep) |
2312 | continue; | |
72246da4 FB |
2313 | |
2314 | if (!(dep->flags & DWC3_EP_STALL)) | |
2315 | continue; | |
2316 | ||
2317 | dep->flags &= ~DWC3_EP_STALL; | |
2318 | ||
50c763f8 | 2319 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2320 | WARN_ON_ONCE(ret); |
2321 | } | |
2322 | } | |
2323 | ||
2324 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2325 | { | |
c4430a26 FB |
2326 | int reg; |
2327 | ||
72246da4 FB |
2328 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2329 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2330 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2331 | ||
2332 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2333 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2334 | |
72246da4 FB |
2335 | dwc3_disconnect_gadget(dwc); |
2336 | ||
2337 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2338 | dwc->setup_packet_pending = false; |
06a374ed | 2339 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2340 | |
2341 | dwc->connected = false; | |
72246da4 FB |
2342 | } |
2343 | ||
72246da4 FB |
2344 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2345 | { | |
2346 | u32 reg; | |
2347 | ||
fc8bb91b FB |
2348 | dwc->connected = true; |
2349 | ||
df62df56 FB |
2350 | /* |
2351 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2352 | * would cause a missing Disconnect Event if there's a | |
2353 | * pending Setup Packet in the FIFO. | |
2354 | * | |
2355 | * There's no suggested workaround on the official Bug | |
2356 | * report, which states that "unless the driver/application | |
2357 | * is doing any special handling of a disconnect event, | |
2358 | * there is no functional issue". | |
2359 | * | |
2360 | * Unfortunately, it turns out that we _do_ some special | |
2361 | * handling of a disconnect event, namely complete all | |
2362 | * pending transfers, notify gadget driver of the | |
2363 | * disconnection, and so on. | |
2364 | * | |
2365 | * Our suggested workaround is to follow the Disconnect | |
2366 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2367 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2368 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2369 | * same endpoint. |
2370 | * | |
2371 | * Refers to: | |
2372 | * | |
2373 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2374 | * generated if setup packet pending in FIFO | |
2375 | */ | |
2376 | if (dwc->revision < DWC3_REVISION_188A) { | |
2377 | if (dwc->setup_packet_pending) | |
2378 | dwc3_gadget_disconnect_interrupt(dwc); | |
2379 | } | |
2380 | ||
8e74475b | 2381 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2382 | |
2383 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2384 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2385 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2386 | dwc->test_mode = false; |
72246da4 FB |
2387 | |
2388 | dwc3_stop_active_transfers(dwc); | |
2389 | dwc3_clear_stall_all_ep(dwc); | |
2390 | ||
2391 | /* Reset device address to zero */ | |
2392 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2393 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2394 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2395 | } |
2396 | ||
2397 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2398 | { | |
2399 | u32 reg; | |
2400 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2401 | ||
2402 | /* | |
2403 | * We change the clock only at SS but I dunno why I would want to do | |
2404 | * this. Maybe it becomes part of the power saving plan. | |
2405 | */ | |
2406 | ||
ee5cd41c JY |
2407 | if ((speed != DWC3_DSTS_SUPERSPEED) && |
2408 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
72246da4 FB |
2409 | return; |
2410 | ||
2411 | /* | |
2412 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2413 | * each time on Connect Done. | |
2414 | */ | |
2415 | if (!usb30_clock) | |
2416 | return; | |
2417 | ||
2418 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2419 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2420 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2421 | } | |
2422 | ||
72246da4 FB |
2423 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2424 | { | |
72246da4 FB |
2425 | struct dwc3_ep *dep; |
2426 | int ret; | |
2427 | u32 reg; | |
2428 | u8 speed; | |
2429 | ||
72246da4 FB |
2430 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2431 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2432 | dwc->speed = speed; | |
2433 | ||
2434 | dwc3_update_ram_clk_sel(dwc, speed); | |
2435 | ||
2436 | switch (speed) { | |
7580862b JY |
2437 | case DWC3_DCFG_SUPERSPEED_PLUS: |
2438 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2439 | dwc->gadget.ep0->maxpacket = 512; | |
2440 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2441 | break; | |
72246da4 | 2442 | case DWC3_DCFG_SUPERSPEED: |
05870c5b FB |
2443 | /* |
2444 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2445 | * would cause a missing USB3 Reset event. | |
2446 | * | |
2447 | * In such situations, we should force a USB3 Reset | |
2448 | * event by calling our dwc3_gadget_reset_interrupt() | |
2449 | * routine. | |
2450 | * | |
2451 | * Refers to: | |
2452 | * | |
2453 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2454 | * not be generated always when the link enters poll | |
2455 | */ | |
2456 | if (dwc->revision < DWC3_REVISION_190A) | |
2457 | dwc3_gadget_reset_interrupt(dwc); | |
2458 | ||
72246da4 FB |
2459 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2460 | dwc->gadget.ep0->maxpacket = 512; | |
2461 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2462 | break; | |
2463 | case DWC3_DCFG_HIGHSPEED: | |
2464 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2465 | dwc->gadget.ep0->maxpacket = 64; | |
2466 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2467 | break; | |
2468 | case DWC3_DCFG_FULLSPEED2: | |
2469 | case DWC3_DCFG_FULLSPEED1: | |
2470 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2471 | dwc->gadget.ep0->maxpacket = 64; | |
2472 | dwc->gadget.speed = USB_SPEED_FULL; | |
2473 | break; | |
2474 | case DWC3_DCFG_LOWSPEED: | |
2475 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2476 | dwc->gadget.ep0->maxpacket = 8; | |
2477 | dwc->gadget.speed = USB_SPEED_LOW; | |
2478 | break; | |
2479 | } | |
2480 | ||
2b758350 PA |
2481 | /* Enable USB2 LPM Capability */ |
2482 | ||
ee5cd41c JY |
2483 | if ((dwc->revision > DWC3_REVISION_194A) && |
2484 | (speed != DWC3_DCFG_SUPERSPEED) && | |
2485 | (speed != DWC3_DCFG_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2486 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2487 | reg |= DWC3_DCFG_LPM_CAP; | |
2488 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2489 | ||
2490 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2491 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2492 | ||
460d098c | 2493 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2494 | |
80caf7d2 HR |
2495 | /* |
2496 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2497 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2498 | * BESL value in the LPM token is less than or equal to LPM | |
2499 | * NYET threshold. | |
2500 | */ | |
2501 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2502 | && dwc->has_lpm_erratum, | |
2503 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2504 | ||
2505 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2506 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2507 | ||
356363bf FB |
2508 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2509 | } else { | |
2510 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2511 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2512 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2513 | } | |
2514 | ||
72246da4 | 2515 | dep = dwc->eps[0]; |
265b70a7 PZ |
2516 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2517 | false); | |
72246da4 FB |
2518 | if (ret) { |
2519 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2520 | return; | |
2521 | } | |
2522 | ||
2523 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2524 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2525 | false); | |
72246da4 FB |
2526 | if (ret) { |
2527 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2528 | return; | |
2529 | } | |
2530 | ||
2531 | /* | |
2532 | * Configure PHY via GUSB3PIPECTLn if required. | |
2533 | * | |
2534 | * Update GTXFIFOSIZn | |
2535 | * | |
2536 | * In both cases reset values should be sufficient. | |
2537 | */ | |
2538 | } | |
2539 | ||
2540 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2541 | { | |
72246da4 FB |
2542 | /* |
2543 | * TODO take core out of low power mode when that's | |
2544 | * implemented. | |
2545 | */ | |
2546 | ||
ad14d4e0 JL |
2547 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2548 | spin_unlock(&dwc->lock); | |
2549 | dwc->gadget_driver->resume(&dwc->gadget); | |
2550 | spin_lock(&dwc->lock); | |
2551 | } | |
72246da4 FB |
2552 | } |
2553 | ||
2554 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2555 | unsigned int evtinfo) | |
2556 | { | |
fae2b904 | 2557 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2558 | unsigned int pwropt; |
2559 | ||
2560 | /* | |
2561 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2562 | * Hibernation mode enabled which would show up when device detects | |
2563 | * host-initiated U3 exit. | |
2564 | * | |
2565 | * In that case, device will generate a Link State Change Interrupt | |
2566 | * from U3 to RESUME which is only necessary if Hibernation is | |
2567 | * configured in. | |
2568 | * | |
2569 | * There are no functional changes due to such spurious event and we | |
2570 | * just need to ignore it. | |
2571 | * | |
2572 | * Refers to: | |
2573 | * | |
2574 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2575 | * operational mode | |
2576 | */ | |
2577 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2578 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2579 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2580 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2581 | (next == DWC3_LINK_STATE_RESUME)) { | |
73815280 FB |
2582 | dwc3_trace(trace_dwc3_gadget, |
2583 | "ignoring transition U3 -> Resume"); | |
0b0cc1cd FB |
2584 | return; |
2585 | } | |
2586 | } | |
fae2b904 FB |
2587 | |
2588 | /* | |
2589 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2590 | * on the link partner, the USB session might do multiple entry/exit | |
2591 | * of low power states before a transfer takes place. | |
2592 | * | |
2593 | * Due to this problem, we might experience lower throughput. The | |
2594 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2595 | * transitioning from U1/U2 to U0 and enable those bits again | |
2596 | * after a transfer completes and there are no pending transfers | |
2597 | * on any of the enabled endpoints. | |
2598 | * | |
2599 | * This is the first half of that workaround. | |
2600 | * | |
2601 | * Refers to: | |
2602 | * | |
2603 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2604 | * core send LGO_Ux entering U0 | |
2605 | */ | |
2606 | if (dwc->revision < DWC3_REVISION_183A) { | |
2607 | if (next == DWC3_LINK_STATE_U0) { | |
2608 | u32 u1u2; | |
2609 | u32 reg; | |
2610 | ||
2611 | switch (dwc->link_state) { | |
2612 | case DWC3_LINK_STATE_U1: | |
2613 | case DWC3_LINK_STATE_U2: | |
2614 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2615 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2616 | | DWC3_DCTL_ACCEPTU2ENA | |
2617 | | DWC3_DCTL_INITU1ENA | |
2618 | | DWC3_DCTL_ACCEPTU1ENA); | |
2619 | ||
2620 | if (!dwc->u1u2) | |
2621 | dwc->u1u2 = reg & u1u2; | |
2622 | ||
2623 | reg &= ~u1u2; | |
2624 | ||
2625 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2626 | break; | |
2627 | default: | |
2628 | /* do nothing */ | |
2629 | break; | |
2630 | } | |
2631 | } | |
2632 | } | |
2633 | ||
bc5ba2e0 FB |
2634 | switch (next) { |
2635 | case DWC3_LINK_STATE_U1: | |
2636 | if (dwc->speed == USB_SPEED_SUPER) | |
2637 | dwc3_suspend_gadget(dwc); | |
2638 | break; | |
2639 | case DWC3_LINK_STATE_U2: | |
2640 | case DWC3_LINK_STATE_U3: | |
2641 | dwc3_suspend_gadget(dwc); | |
2642 | break; | |
2643 | case DWC3_LINK_STATE_RESUME: | |
2644 | dwc3_resume_gadget(dwc); | |
2645 | break; | |
2646 | default: | |
2647 | /* do nothing */ | |
2648 | break; | |
2649 | } | |
2650 | ||
e57ebc1d | 2651 | dwc->link_state = next; |
72246da4 FB |
2652 | } |
2653 | ||
e1dadd3b FB |
2654 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2655 | unsigned int evtinfo) | |
2656 | { | |
2657 | unsigned int is_ss = evtinfo & BIT(4); | |
2658 | ||
2659 | /** | |
2660 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2661 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2662 | * randomly. | |
2663 | * | |
2664 | * Because of this issue, core could generate bogus hibernation | |
2665 | * events which SW needs to ignore. | |
2666 | * | |
2667 | * Refers to: | |
2668 | * | |
2669 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2670 | * Device Fallback from SuperSpeed | |
2671 | */ | |
2672 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2673 | return; | |
2674 | ||
2675 | /* enter hibernation here */ | |
2676 | } | |
2677 | ||
72246da4 FB |
2678 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2679 | const struct dwc3_event_devt *event) | |
2680 | { | |
2681 | switch (event->type) { | |
2682 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2683 | dwc3_gadget_disconnect_interrupt(dwc); | |
2684 | break; | |
2685 | case DWC3_DEVICE_EVENT_RESET: | |
2686 | dwc3_gadget_reset_interrupt(dwc); | |
2687 | break; | |
2688 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2689 | dwc3_gadget_conndone_interrupt(dwc); | |
2690 | break; | |
2691 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2692 | dwc3_gadget_wakeup_interrupt(dwc); | |
2693 | break; | |
e1dadd3b FB |
2694 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2695 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2696 | "unexpected hibernation event\n")) | |
2697 | break; | |
2698 | ||
2699 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2700 | break; | |
72246da4 FB |
2701 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2702 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2703 | break; | |
2704 | case DWC3_DEVICE_EVENT_EOPF: | |
73815280 | 2705 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); |
72246da4 FB |
2706 | break; |
2707 | case DWC3_DEVICE_EVENT_SOF: | |
73815280 | 2708 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); |
72246da4 FB |
2709 | break; |
2710 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
73815280 | 2711 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); |
72246da4 FB |
2712 | break; |
2713 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
73815280 | 2714 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); |
72246da4 FB |
2715 | break; |
2716 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
73815280 | 2717 | dwc3_trace(trace_dwc3_gadget, "Overflow"); |
72246da4 FB |
2718 | break; |
2719 | default: | |
e9f2aa87 | 2720 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2721 | } |
2722 | } | |
2723 | ||
2724 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2725 | const union dwc3_event *event) | |
2726 | { | |
2c4cbe6e FB |
2727 | trace_dwc3_event(event->raw); |
2728 | ||
72246da4 FB |
2729 | /* Endpoint IRQ, handle it and return early */ |
2730 | if (event->type.is_devspec == 0) { | |
2731 | /* depevt */ | |
2732 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2733 | } | |
2734 | ||
2735 | switch (event->type.type) { | |
2736 | case DWC3_EVENT_TYPE_DEV: | |
2737 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2738 | break; | |
2739 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2740 | default: | |
2741 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2742 | } | |
2743 | } | |
2744 | ||
dea520a4 | 2745 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2746 | { |
dea520a4 | 2747 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2748 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2749 | int left; |
e8adfc30 | 2750 | u32 reg; |
b15a762f | 2751 | |
f42f2447 | 2752 | left = evt->count; |
b15a762f | 2753 | |
f42f2447 FB |
2754 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2755 | return IRQ_NONE; | |
b15a762f | 2756 | |
f42f2447 FB |
2757 | while (left > 0) { |
2758 | union dwc3_event event; | |
b15a762f | 2759 | |
f42f2447 | 2760 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2761 | |
f42f2447 | 2762 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2763 | |
f42f2447 FB |
2764 | /* |
2765 | * FIXME we wrap around correctly to the next entry as | |
2766 | * almost all entries are 4 bytes in size. There is one | |
2767 | * entry which has 12 bytes which is a regular entry | |
2768 | * followed by 8 bytes data. ATM I don't know how | |
2769 | * things are organized if we get next to the a | |
2770 | * boundary so I worry about that once we try to handle | |
2771 | * that. | |
2772 | */ | |
2773 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2774 | left -= 4; | |
b15a762f | 2775 | |
660e9bde | 2776 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); |
f42f2447 | 2777 | } |
b15a762f | 2778 | |
f42f2447 FB |
2779 | evt->count = 0; |
2780 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2781 | ret = IRQ_HANDLED; | |
b15a762f | 2782 | |
f42f2447 | 2783 | /* Unmask interrupt */ |
660e9bde | 2784 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 2785 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2786 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 2787 | |
f42f2447 FB |
2788 | return ret; |
2789 | } | |
e8adfc30 | 2790 | |
dea520a4 | 2791 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 2792 | { |
dea520a4 FB |
2793 | struct dwc3_event_buffer *evt = _evt; |
2794 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 2795 | unsigned long flags; |
f42f2447 | 2796 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2797 | |
e5f68b4a | 2798 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 2799 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 2800 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2801 | |
2802 | return ret; | |
2803 | } | |
2804 | ||
dea520a4 | 2805 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 2806 | { |
dea520a4 | 2807 | struct dwc3 *dwc = evt->dwc; |
72246da4 | 2808 | u32 count; |
e8adfc30 | 2809 | u32 reg; |
72246da4 | 2810 | |
fc8bb91b FB |
2811 | if (pm_runtime_suspended(dwc->dev)) { |
2812 | pm_runtime_get(dwc->dev); | |
2813 | disable_irq_nosync(dwc->irq_gadget); | |
2814 | dwc->pending_events = true; | |
2815 | return IRQ_HANDLED; | |
2816 | } | |
2817 | ||
660e9bde | 2818 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
2819 | count &= DWC3_GEVNTCOUNT_MASK; |
2820 | if (!count) | |
2821 | return IRQ_NONE; | |
2822 | ||
b15a762f FB |
2823 | evt->count = count; |
2824 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2825 | |
e8adfc30 | 2826 | /* Mask interrupt */ |
660e9bde | 2827 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 2828 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2829 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 2830 | |
b15a762f | 2831 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2832 | } |
2833 | ||
dea520a4 | 2834 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 2835 | { |
dea520a4 | 2836 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 2837 | |
dea520a4 | 2838 | return dwc3_check_event_buf(evt); |
72246da4 FB |
2839 | } |
2840 | ||
2841 | /** | |
2842 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2843 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2844 | * |
2845 | * Returns 0 on success otherwise negative errno. | |
2846 | */ | |
41ac7b3a | 2847 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2848 | { |
72246da4 | 2849 | int ret; |
72246da4 FB |
2850 | |
2851 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2852 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2853 | if (!dwc->ctrl_req) { | |
2854 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2855 | ret = -ENOMEM; | |
2856 | goto err0; | |
2857 | } | |
2858 | ||
2abd9d5f | 2859 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2860 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2861 | if (!dwc->ep0_trb) { | |
2862 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2863 | ret = -ENOMEM; | |
2864 | goto err1; | |
2865 | } | |
2866 | ||
3ef35faf | 2867 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2868 | if (!dwc->setup_buf) { |
72246da4 FB |
2869 | ret = -ENOMEM; |
2870 | goto err2; | |
2871 | } | |
2872 | ||
5812b1c2 | 2873 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2874 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2875 | GFP_KERNEL); | |
5812b1c2 FB |
2876 | if (!dwc->ep0_bounce) { |
2877 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2878 | ret = -ENOMEM; | |
2879 | goto err3; | |
2880 | } | |
2881 | ||
04c03d10 FB |
2882 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); |
2883 | if (!dwc->zlp_buf) { | |
2884 | ret = -ENOMEM; | |
2885 | goto err4; | |
2886 | } | |
2887 | ||
72246da4 | 2888 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 2889 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2890 | dwc->gadget.sg_supported = true; |
72246da4 | 2891 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 2892 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 2893 | |
b9e51b2b BM |
2894 | /* |
2895 | * FIXME We might be setting max_speed to <SUPER, however versions | |
2896 | * <2.20a of dwc3 have an issue with metastability (documented | |
2897 | * elsewhere in this driver) which tells us we can't set max speed to | |
2898 | * anything lower than SUPER. | |
2899 | * | |
2900 | * Because gadget.max_speed is only used by composite.c and function | |
2901 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
2902 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
2903 | * together with our BOS descriptor as that could confuse host into | |
2904 | * thinking we can handle super speed. | |
2905 | * | |
2906 | * Note that, in fact, we won't even support GetBOS requests when speed | |
2907 | * is less than super speed because we don't have means, yet, to tell | |
2908 | * composite.c that we are USB 2.0 + LPM ECN. | |
2909 | */ | |
2910 | if (dwc->revision < DWC3_REVISION_220A) | |
2911 | dwc3_trace(trace_dwc3_gadget, | |
2912 | "Changing max_speed on rev %08x\n", | |
2913 | dwc->revision); | |
2914 | ||
2915 | dwc->gadget.max_speed = dwc->maximum_speed; | |
2916 | ||
a4b9d94b DC |
2917 | /* |
2918 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2919 | * on ep out. | |
2920 | */ | |
2921 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2922 | ||
72246da4 FB |
2923 | /* |
2924 | * REVISIT: Here we should clear all pending IRQs to be | |
2925 | * sure we're starting from a well known location. | |
2926 | */ | |
2927 | ||
2928 | ret = dwc3_gadget_init_endpoints(dwc); | |
2929 | if (ret) | |
04c03d10 | 2930 | goto err5; |
72246da4 | 2931 | |
72246da4 FB |
2932 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2933 | if (ret) { | |
2934 | dev_err(dwc->dev, "failed to register udc\n"); | |
04c03d10 | 2935 | goto err5; |
72246da4 FB |
2936 | } |
2937 | ||
2938 | return 0; | |
2939 | ||
04c03d10 FB |
2940 | err5: |
2941 | kfree(dwc->zlp_buf); | |
2942 | ||
5812b1c2 | 2943 | err4: |
e1f80467 | 2944 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2945 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2946 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2947 | |
72246da4 | 2948 | err3: |
0fc9a1be | 2949 | kfree(dwc->setup_buf); |
72246da4 FB |
2950 | |
2951 | err2: | |
2952 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2953 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2954 | ||
2955 | err1: | |
2956 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2957 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2958 | ||
2959 | err0: | |
2960 | return ret; | |
2961 | } | |
2962 | ||
7415f17c FB |
2963 | /* -------------------------------------------------------------------------- */ |
2964 | ||
72246da4 FB |
2965 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2966 | { | |
72246da4 | 2967 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2968 | |
72246da4 FB |
2969 | dwc3_gadget_free_endpoints(dwc); |
2970 | ||
3ef35faf FB |
2971 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2972 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2973 | |
0fc9a1be | 2974 | kfree(dwc->setup_buf); |
04c03d10 | 2975 | kfree(dwc->zlp_buf); |
72246da4 FB |
2976 | |
2977 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2978 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2979 | ||
2980 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2981 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2982 | } |
7415f17c | 2983 | |
0b0231aa | 2984 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 2985 | { |
9f8a67b6 FB |
2986 | int ret; |
2987 | ||
9772b47a RQ |
2988 | if (!dwc->gadget_driver) |
2989 | return 0; | |
2990 | ||
9f8a67b6 FB |
2991 | ret = dwc3_gadget_run_stop(dwc, false, false); |
2992 | if (ret < 0) | |
2993 | return ret; | |
7415f17c | 2994 | |
9f8a67b6 FB |
2995 | dwc3_disconnect_gadget(dwc); |
2996 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
2997 | |
2998 | return 0; | |
2999 | } | |
3000 | ||
3001 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3002 | { | |
7415f17c FB |
3003 | int ret; |
3004 | ||
9772b47a RQ |
3005 | if (!dwc->gadget_driver) |
3006 | return 0; | |
3007 | ||
9f8a67b6 FB |
3008 | ret = __dwc3_gadget_start(dwc); |
3009 | if (ret < 0) | |
7415f17c FB |
3010 | goto err0; |
3011 | ||
9f8a67b6 FB |
3012 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3013 | if (ret < 0) | |
7415f17c FB |
3014 | goto err1; |
3015 | ||
7415f17c FB |
3016 | return 0; |
3017 | ||
3018 | err1: | |
9f8a67b6 | 3019 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3020 | |
3021 | err0: | |
3022 | return ret; | |
3023 | } | |
fc8bb91b FB |
3024 | |
3025 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3026 | { | |
3027 | if (dwc->pending_events) { | |
3028 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3029 | dwc->pending_events = false; | |
3030 | enable_irq(dwc->irq_gadget); | |
3031 | } | |
3032 | } |