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usb: dwc3: ep0: avoid empty-body warning
[mirror_ubuntu-artful-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
0416e494
PA		 183 if (dwc->ep0_bounced && dep->number == 0)
184 dwc->ep0_bounced = false;
185 else
186 usb_gadget_unmap_request(&dwc->gadget, &req->request,
187 req->direction);
72246da4 188
2c4cbe6e 189 trace_dwc3_gadget_giveback(req);
72246da4
FB		 190
191 spin_unlock(&dwc->lock);
304f7e5e 192 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 193 spin_lock(&dwc->lock);
fc8bb91b
FB		 194
195 if (dep->number > 1)
196 pm_runtime_put(dwc->dev);
72246da4
FB		 197}
198
3ece0ec4 199int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 200{
201 u32 timeout = 500;
71f7e702 202 int status = 0;
0fe886cd 203 int ret = 0;
b09bb642
FB		 204 u32 reg;
205
206 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
207 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
208
209 do {
210 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
211 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 212 status = DWC3_DGCMD_STATUS(reg);
213 if (status)
0fe886cd
FB		 214 ret = -EINVAL;
215 break;
b09bb642 216 }
e3aee486 217 } while (--timeout);
0fe886cd
FB		 218
219 if (!timeout) {
0fe886cd 220 ret = -ETIMEDOUT;
71f7e702 221 status = -ETIMEDOUT;
0fe886cd
FB		 222 }
223
71f7e702
FB		 224 trace_dwc3_gadget_generic_cmd(cmd, param, status);
225
0fe886cd 226 return ret;
b09bb642
FB		 227}
228
c36d8e94
FB		 229static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
230
2cd4718d
FB		 231int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
232 struct dwc3_gadget_ep_cmd_params *params)
72246da4 233{
8897a761 234 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 235 struct dwc3 *dwc = dep->dwc;
61d58242 236 u32 timeout = 500;
72246da4
FB		 237 u32 reg;
238
0933df15 239 int cmd_status = 0;
2b0f11df 240 int susphy = false;
c0ca324d 241 int ret = -EINVAL;
72246da4 242
2b0f11df
FB		 243 /*
244 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245 * we're issuing an endpoint command, we must check if
246 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
247 *
248 * We will also set SUSPHY bit to what it was before returning as stated
249 * by the same section on Synopsys databook.
250 */
ab2a92e7
FB		 251 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
252 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
253 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
254 susphy = true;
255 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
256 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
257 }
2b0f11df
FB		 258 }
259
5999914f 260 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 261 int needs_wakeup;
262
263 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
264 dwc->link_state == DWC3_LINK_STATE_U2 ||
265 dwc->link_state == DWC3_LINK_STATE_U3);
266
267 if (unlikely(needs_wakeup)) {
268 ret = __dwc3_gadget_wakeup(dwc);
269 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
270 ret);
271 }
272 }
273
2eb88016
FB		 274 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
275 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
276 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 277
8897a761
FB		 278 /*
279 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280 * not relying on XferNotReady, we can make use of a special "No
281 * Response Update Transfer" command where we should clear both CmdAct
282 * and CmdIOC bits.
283 *
284 * With this, we don't need to wait for command completion and can
285 * straight away issue further commands to the endpoint.
286 *
287 * NOTICE: We're making an assumption that control endpoints will never
288 * make use of Update Transfer command. This is a safe assumption
289 * because we can never have more than one request at a time with
290 * Control Endpoints. If anybody changes that assumption, this chunk
291 * needs to be updated accordingly.
292 */
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
294 !usb_endpoint_xfer_isoc(desc))
295 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
296 else
297 cmd |= DWC3_DEPCMD_CMDACT;
298
299 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 300 do {
2eb88016 301 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 302 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 303 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 304
7b9cc7a2
KL		 305 switch (cmd_status) {
306 case 0:
307 ret = 0;
308 break;
309 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 310 ret = -EINVAL;
c0ca324d 311 break;
7b9cc7a2
KL		 312 case DEPEVT_TRANSFER_BUS_EXPIRY:
313 /*
314 * SW issues START TRANSFER command to
315 * isochronous ep with future frame interval. If
316 * future interval time has already passed when
317 * core receives the command, it will respond
318 * with an error status of 'Bus Expiry'.
319 *
320 * Instead of always returning -EINVAL, let's
321 * give a hint to the gadget driver that this is
322 * the case by returning -EAGAIN.
323 */
7b9cc7a2
KL		 324 ret = -EAGAIN;
325 break;
326 default:
327 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
328 }
329
c0ca324d 330 break;
72246da4 331 }
f6bb225b 332 } while (--timeout);
72246da4 333
f6bb225b 334 if (timeout == 0) {
f6bb225b 335 ret = -ETIMEDOUT;
0933df15 336 cmd_status = -ETIMEDOUT;
f6bb225b 337 }
c0ca324d 338
0933df15
FB		 339 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
340
6cb2e4e3
FB		 341 if (ret == 0) {
342 switch (DWC3_DEPCMD_CMD(cmd)) {
343 case DWC3_DEPCMD_STARTTRANSFER:
344 dep->flags |= DWC3_EP_TRANSFER_STARTED;
345 break;
346 case DWC3_DEPCMD_ENDTRANSFER:
347 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
348 break;
349 default:
350 /* nothing */
351 break;
352 }
353 }
354
2b0f11df
FB		 355 if (unlikely(susphy)) {
356 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
357 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
358 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
359 }
360
c0ca324d 361 return ret;
72246da4
FB		 362}
363
50c763f8
JY		 364static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
365{
366 struct dwc3 *dwc = dep->dwc;
367 struct dwc3_gadget_ep_cmd_params params;
368 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
369
370 /*
371 * As of core revision 2.60a the recommended programming model
372 * is to set the ClearPendIN bit when issuing a Clear Stall EP
373 * command for IN endpoints. This is to prevent an issue where
374 * some (non-compliant) hosts may not send ACK TPs for pending
375 * IN transfers due to a mishandled error condition. Synopsys
376 * STAR 9000614252.
377 */
5e6c88d2
LB		 378 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
379 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 380 cmd |= DWC3_DEPCMD_CLEARPENDIN;
381
382 memset(&params, 0, sizeof(params));
383
2cd4718d 384 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 385}
386
72246da4 387static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 388 struct dwc3_trb *trb)
72246da4 389{
c439ef87 390 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 391
392 return dep->trb_pool_dma + offset;
393}
394
395static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398
399 if (dep->trb_pool)
400 return 0;
401
72246da4
FB		 402 dep->trb_pool = dma_alloc_coherent(dwc->dev,
403 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
404 &dep->trb_pool_dma, GFP_KERNEL);
405 if (!dep->trb_pool) {
406 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
407 dep->name);
408 return -ENOMEM;
409 }
410
411 return 0;
412}
413
414static void dwc3_free_trb_pool(struct dwc3_ep *dep)
415{
416 struct dwc3 *dwc = dep->dwc;
417
418 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
419 dep->trb_pool, dep->trb_pool_dma);
420
421 dep->trb_pool = NULL;
422 dep->trb_pool_dma = 0;
423}
424
c4509601
JY		 425static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
426
427/**
428 * dwc3_gadget_start_config - Configure EP resources
429 * @dwc: pointer to our controller context structure
430 * @dep: endpoint that is being enabled
431 *
432 * The assignment of transfer resources cannot perfectly follow the
433 * data book due to the fact that the controller driver does not have
434 * all knowledge of the configuration in advance. It is given this
435 * information piecemeal by the composite gadget framework after every
436 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437 * programming model in this scenario can cause errors. For two
438 * reasons:
439 *
440 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442 * multiple interfaces.
443 *
444 * 2) The databook does not mention doing more DEPXFERCFG for new
445 * endpoint on alt setting (8.1.6).
446 *
447 * The following simplified method is used instead:
448 *
449 * All hardware endpoints can be assigned a transfer resource and this
450 * setting will stay persistent until either a core reset or
451 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452 * do DEPXFERCFG for every hardware endpoint as well. We are
453 * guaranteed that there are as many transfer resources as endpoints.
454 *
455 * This function is called for each endpoint when it is being enabled
456 * but is triggered only when called for EP0-out, which always happens
457 * first, and which should only happen in one of the above conditions.
458 */
72246da4
FB		 459static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
460{
461 struct dwc3_gadget_ep_cmd_params params;
462 u32 cmd;
c4509601
JY		 463 int i;
464 int ret;
465
466 if (dep->number)
467 return 0;
72246da4
FB		 468
469 memset(&params, 0x00, sizeof(params));
c4509601 470 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 471
2cd4718d 472 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 473 if (ret)
474 return ret;
475
476 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
477 struct dwc3_ep *dep = dwc->eps[i];
72246da4 478
c4509601
JY		 479 if (!dep)
480 continue;
481
482 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
483 if (ret)
484 return ret;
72246da4
FB		 485 }
486
487 return 0;
488}
489
490static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 491 bool modify, bool restore)
72246da4 492{
39ebb05c
JY		 493 const struct usb_ss_ep_comp_descriptor *comp_desc;
494 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 495 struct dwc3_gadget_ep_cmd_params params;
496
21e64bf2
FB		 497 if (dev_WARN_ONCE(dwc->dev, modify && restore,
498 "Can't modify and restore\n"))
499 return -EINVAL;
500
39ebb05c
JY		 501 comp_desc = dep->endpoint.comp_desc;
502 desc = dep->endpoint.desc;
503
72246da4
FB		 504 memset(&params, 0x00, sizeof(params));
505
dc1c70a7 506 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 507 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
508
509 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 510 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 511 u32 burst = dep->endpoint.maxburst;
676e3497 512 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 513 }
72246da4 514
21e64bf2
FB		 515 if (modify) {
516 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
517 } else if (restore) {
265b70a7
PZ		 518 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
519 params.param2 |= dep->saved_state;
21e64bf2
FB		 520 } else {
521 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 522 }
523
4bc48c97
FB		 524 if (usb_endpoint_xfer_control(desc))
525 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 526
527 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
528 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 529
18b7ede5 530 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 531 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
532 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 533 dep->stream_capable = true;
534 }
535
0b93a4c8 536 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 537 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 538
539 /*
540 * We are doing 1:1 mapping for endpoints, meaning
541 * Physical Endpoints 2 maps to Logical Endpoint 2 and
542 * so on. We consider the direction bit as part of the physical
543 * endpoint number. So USB endpoint 0x81 is 0x03.
544 */
dc1c70a7 545 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 546
547 /*
548 * We must use the lower 16 TX FIFOs even though
549 * HW might have more
550 */
551 if (dep->direction)
dc1c70a7 552 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 553
554 if (desc->bInterval) {
dc1c70a7 555 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 556 dep->interval = 1 << (desc->bInterval - 1);
557 }
558
2cd4718d 559 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 560}
561
562static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
563{
564 struct dwc3_gadget_ep_cmd_params params;
565
566 memset(&params, 0x00, sizeof(params));
567
dc1c70a7 568 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 569
2cd4718d
FB		 570 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
571 &params);
72246da4
FB		 572}
573
574/**
575 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
576 * @dep: endpoint to be initialized
577 * @desc: USB Endpoint Descriptor
578 *
579 * Caller should take care of locking
580 */
581static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 582 bool modify, bool restore)
72246da4 583{
39ebb05c 584 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 585 struct dwc3 *dwc = dep->dwc;
39ebb05c 586
72246da4 587 u32 reg;
b09e99ee 588 int ret;
72246da4
FB		 589
590 if (!(dep->flags & DWC3_EP_ENABLED)) {
591 ret = dwc3_gadget_start_config(dwc, dep);
592 if (ret)
593 return ret;
594 }
595
39ebb05c 596 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 597 if (ret)
598 return ret;
599
600 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 601 struct dwc3_trb *trb_st_hw;
602 struct dwc3_trb *trb_link;
72246da4 603
72246da4
FB		 604 dep->type = usb_endpoint_type(desc);
605 dep->flags |= DWC3_EP_ENABLED;
76a638f8 606 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 607
608 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
609 reg |= DWC3_DALEPENA_EP(dep->number);
610 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611
76a638f8
BW		 612 init_waitqueue_head(&dep->wait_end_transfer);
613
36b68aae 614 if (usb_endpoint_xfer_control(desc))
2870e501 615 goto out;
72246da4 616
0d25744a
JY		 617 /* Initialize the TRB ring */
618 dep->trb_dequeue = 0;
619 dep->trb_enqueue = 0;
620 memset(dep->trb_pool, 0,
621 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
622
36b68aae 623 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 624 trb_st_hw = &dep->trb_pool[0];
625
f6bafc6a 626 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 627 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
628 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
629 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
630 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 631 }
632
a97ea994
FB		 633 /*
634 * Issue StartTransfer here with no-op TRB so we can always rely on No
635 * Response Update Transfer command.
636 */
637 if (usb_endpoint_xfer_bulk(desc)) {
638 struct dwc3_gadget_ep_cmd_params params;
639 struct dwc3_trb *trb;
640 dma_addr_t trb_dma;
641 u32 cmd;
642
643 memset(&params, 0, sizeof(params));
644 trb = &dep->trb_pool[0];
645 trb_dma = dwc3_trb_dma_offset(dep, trb);
646
647 params.param0 = upper_32_bits(trb_dma);
648 params.param1 = lower_32_bits(trb_dma);
649
650 cmd = DWC3_DEPCMD_STARTTRANSFER;
651
652 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
653 if (ret < 0)
654 return ret;
655
656 dep->flags |= DWC3_EP_BUSY;
657
658 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
659 WARN_ON_ONCE(!dep->resource_index);
660 }
661
2870e501
FB		 662
663out:
664 trace_dwc3_gadget_ep_enable(dep);
665
72246da4
FB		 666 return 0;
667}
668
b992e681 669static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 670static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 671{
672 struct dwc3_request *req;
673
0e146028 674 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 675
0e146028
FB		 676 /* - giveback all requests to gadget driver */
677 while (!list_empty(&dep->started_list)) {
678 req = next_request(&dep->started_list);
1591633e 679
0e146028 680 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 681 }
682
aa3342c8
FB		 683 while (!list_empty(&dep->pending_list)) {
684 req = next_request(&dep->pending_list);
72246da4 685
624407f9 686 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 687 }
72246da4
FB		 688}
689
690/**
691 * __dwc3_gadget_ep_disable - Disables a HW endpoint
692 * @dep: the endpoint to disable
693 *
624407f9
SAS		 694 * This function also removes requests which are currently processed ny the
695 * hardware and those which are not yet scheduled.
696 * Caller should take care of locking.
72246da4 697 */
72246da4
FB		 698static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
699{
700 struct dwc3 *dwc = dep->dwc;
701 u32 reg;
702
2870e501 703 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 704
624407f9 705 dwc3_remove_requests(dwc, dep);
72246da4 706
687ef981
FB		 707 /* make sure HW endpoint isn't stalled */
708 if (dep->flags & DWC3_EP_STALL)
7a608559 709 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 710
72246da4
FB		 711 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
712 reg &= ~DWC3_DALEPENA_EP(dep->number);
713 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
714
879631aa 715 dep->stream_capable = false;
72246da4 716 dep->type = 0;
76a638f8 717 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 718
39ebb05c
JY		 719 /* Clear out the ep descriptors for non-ep0 */
720 if (dep->number > 1) {
721 dep->endpoint.comp_desc = NULL;
722 dep->endpoint.desc = NULL;
723 }
724
72246da4
FB		 725 return 0;
726}
727
728/* -------------------------------------------------------------------------- */
729
730static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
731 const struct usb_endpoint_descriptor *desc)
732{
733 return -EINVAL;
734}
735
736static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
737{
738 return -EINVAL;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 struct dwc3_ep *dep;
747 struct dwc3 *dwc;
748 unsigned long flags;
749 int ret;
750
751 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
752 pr_debug("dwc3: invalid parameters\n");
753 return -EINVAL;
754 }
755
756 if (!desc->wMaxPacketSize) {
757 pr_debug("dwc3: missing wMaxPacketSize\n");
758 return -EINVAL;
759 }
760
761 dep = to_dwc3_ep(ep);
762 dwc = dep->dwc;
763
95ca961c
FB		 764 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
765 "%s is already enabled\n",
766 dep->name))
c6f83f38 767 return 0;
c6f83f38 768
72246da4 769 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 770 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 771 spin_unlock_irqrestore(&dwc->lock, flags);
772
773 return ret;
774}
775
776static int dwc3_gadget_ep_disable(struct usb_ep *ep)
777{
778 struct dwc3_ep *dep;
779 struct dwc3 *dwc;
780 unsigned long flags;
781 int ret;
782
783 if (!ep) {
784 pr_debug("dwc3: invalid parameters\n");
785 return -EINVAL;
786 }
787
788 dep = to_dwc3_ep(ep);
789 dwc = dep->dwc;
790
95ca961c
FB		 791 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
792 "%s is already disabled\n",
793 dep->name))
72246da4 794 return 0;
72246da4 795
72246da4
FB		 796 spin_lock_irqsave(&dwc->lock, flags);
797 ret = __dwc3_gadget_ep_disable(dep);
798 spin_unlock_irqrestore(&dwc->lock, flags);
799
800 return ret;
801}
802
803static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
804 gfp_t gfp_flags)
805{
806 struct dwc3_request *req;
807 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 808
809 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 810 if (!req)
72246da4 811 return NULL;
72246da4
FB		 812
813 req->epnum = dep->number;
814 req->dep = dep;
72246da4 815
68d34c8a
FB		 816 dep->allocated_requests++;
817
2c4cbe6e
FB		 818 trace_dwc3_alloc_request(req);
819
72246da4
FB		 820 return &req->request;
821}
822
823static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
824 struct usb_request *request)
825{
826 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 827 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 828
68d34c8a 829 dep->allocated_requests--;
2c4cbe6e 830 trace_dwc3_free_request(req);
72246da4
FB		 831 kfree(req);
832}
833
2c78c029
FB		 834static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
835
c71fc37c
FB		 836/**
837 * dwc3_prepare_one_trb - setup one TRB from one request
838 * @dep: endpoint for which this request is prepared
839 * @req: dwc3_request pointer
840 */
68e823e2 841static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 842 struct dwc3_request *req, dma_addr_t dma,
4bc48c97 843 unsigned length, unsigned chain, unsigned node)
c71fc37c 844{
f6bafc6a 845 struct dwc3_trb *trb;
6b9018d4
FB		 846 struct dwc3 *dwc = dep->dwc;
847 struct usb_gadget *gadget = &dwc->gadget;
848 enum usb_device_speed speed = gadget->speed;
c71fc37c 849
4faf7550 850 trb = &dep->trb_pool[dep->trb_enqueue];
c71fc37c 851
eeb720fb 852 if (!req->trb) {
aa3342c8 853 dwc3_gadget_move_started_request(req);
f6bafc6a
FB		 854 req->trb = trb;
855 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
a9c3ca5f 856 dep->queued_requests++;
eeb720fb 857 }
c71fc37c 858
ef966b9d 859 dwc3_ep_inc_enq(dep);
e5ba5ec8 860
f6bafc6a
FB		 861 trb->size = DWC3_TRB_SIZE_LENGTH(length);
862 trb->bpl = lower_32_bits(dma);
863 trb->bph = upper_32_bits(dma);
c71fc37c 864
16e78db7 865 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 866 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 867 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 868 break;
869
870 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 871 if (!node) {
e5ba5ec8 872 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 873
874 if (speed == USB_SPEED_HIGH) {
875 struct usb_ep *ep = &dep->endpoint;
876 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
877 }
878 } else {
e5ba5ec8 879 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 880 }
ca4d44ea
FB		 881
882 /* always enable Interrupt on Missed ISOC */
883 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 884 break;
885
886 case USB_ENDPOINT_XFER_BULK:
887 case USB_ENDPOINT_XFER_INT:
f6bafc6a 888 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 889 break;
890 default:
891 /*
892 * This is only possible with faulty memory because we
893 * checked it already :)
894 */
0a695d4c
FB		 895 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
896 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 897 }
898
ca4d44ea 899 /* always enable Continue on Short Packet */
c9508c8c 900 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 901 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 902
c9508c8c
FB		 903 if (req->request.short_not_ok)
904 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
905 }
906
2c78c029
FB		 907 if ((!req->request.no_interrupt && !chain) ||
908 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 909 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 910
e5ba5ec8
PA		 911 if (chain)
912 trb->ctrl |= DWC3_TRB_CTRL_CHN;
913
16e78db7 914 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 915 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 916
f6bafc6a 917 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 918
919 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 920}
921
361572b5
JY		 922/**
923 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
924 * @dep: The endpoint with the TRB ring
925 * @index: The index of the current TRB in the ring
926 *
927 * Returns the TRB prior to the one pointed to by the index. If the
928 * index is 0, we will wrap backwards, skip the link TRB, and return
929 * the one just before that.
930 */
931static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
932{
45438a0c 933 u8 tmp = index;
361572b5 934
45438a0c
FB		 935 if (!tmp)
936 tmp = DWC3_TRB_NUM - 1;
361572b5 937
45438a0c 938 return &dep->trb_pool[tmp - 1];
361572b5
JY		 939}
940
c4233573
FB		 941static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
942{
943 struct dwc3_trb *tmp;
f2694a93 944 struct dwc3 *dwc = dep->dwc;
32db3d94 945 u8 trbs_left;
c4233573
FB		 946
947 /*
948 * If enqueue & dequeue are equal than it is either full or empty.
949 *
950 * One way to know for sure is if the TRB right before us has HWO bit
951 * set or not. If it has, then we're definitely full and can't fit any
952 * more transfers in our ring.
953 */
954 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 955 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 956 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
957 "%s No TRBS left\n", dep->name))
361572b5 958 return 0;
c4233573
FB		 959
960 return DWC3_TRB_NUM - 1;
961 }
962
9d7aba77 963 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 964 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 965
9d7aba77
JY		 966 if (dep->trb_dequeue < dep->trb_enqueue)
967 trbs_left--;
968
32db3d94 969 return trbs_left;
c4233573
FB		 970}
971
5ee85d89 972static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 973 struct dwc3_request *req)
5ee85d89 974{
1f512119 975 struct scatterlist *sg = req->sg;
5ee85d89 976 struct scatterlist *s;
5ee85d89
FB		 977 unsigned int length;
978 dma_addr_t dma;
979 int i;
980
1f512119 981 for_each_sg(sg, s, req->num_pending_sgs, i) {
5ee85d89
FB		 982 unsigned chain = true;
983
984 length = sg_dma_len(s);
985 dma = sg_dma_address(s);
986
4bc48c97 987 if (sg_is_last(s))
5ee85d89
FB		 988 chain = false;
989
990 dwc3_prepare_one_trb(dep, req, dma, length,
4bc48c97 991 chain, i);
5ee85d89 992
7ae7df49 993 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 994 break;
995 }
996}
997
998static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 999 struct dwc3_request *req)
5ee85d89 1000{
5ee85d89
FB		 1001 unsigned int length;
1002 dma_addr_t dma;
1003
1004 dma = req->request.dma;
1005 length = req->request.length;
1006
5ee85d89 1007 dwc3_prepare_one_trb(dep, req, dma, length,
4bc48c97 1008 false, 0);
5ee85d89
FB		 1009}
1010
72246da4
FB		 1011/*
1012 * dwc3_prepare_trbs - setup TRBs from requests
1013 * @dep: endpoint for which requests are being prepared
72246da4 1014 *
1d046793
PZ		 1015 * The function goes through the requests list and sets up TRBs for the
1016 * transfers. The function returns once there are no more TRBs available or
1017 * it runs out of requests.
72246da4 1018 */
c4233573 1019static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1020{
68e823e2 1021 struct dwc3_request *req, *n;
72246da4
FB		 1022
1023 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1024
7ae7df49 1025 if (!dwc3_calc_trbs_left(dep))
89bc856e 1026 return;
72246da4 1027
d86c5a67
FB		 1028 /*
1029 * We can get in a situation where there's a request in the started list
1030 * but there weren't enough TRBs to fully kick it in the first time
1031 * around, so it has been waiting for more TRBs to be freed up.
1032 *
1033 * In that case, we should check if we have a request with pending_sgs
1034 * in the started list and prepare TRBs for that request first,
1035 * otherwise we will prepare TRBs completely out of order and that will
1036 * break things.
1037 */
1038 list_for_each_entry(req, &dep->started_list, list) {
1039 if (req->num_pending_sgs > 0)
1040 dwc3_prepare_one_trb_sg(dep, req);
1041
1042 if (!dwc3_calc_trbs_left(dep))
1043 return;
1044 }
1045
aa3342c8 1046 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1047 if (req->num_pending_sgs > 0)
7ae7df49 1048 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1049 else
7ae7df49 1050 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1051
7ae7df49 1052 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1053 return;
72246da4 1054 }
72246da4
FB		 1055}
1056
4fae2e3e 1057static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1058{
1059 struct dwc3_gadget_ep_cmd_params params;
1060 struct dwc3_request *req;
4fae2e3e 1061 int starting;
72246da4
FB		 1062 int ret;
1063 u32 cmd;
1064
4fae2e3e 1065 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1066
4fae2e3e
FB		 1067 dwc3_prepare_trbs(dep);
1068 req = next_request(&dep->started_list);
72246da4
FB		 1069 if (!req) {
1070 dep->flags |= DWC3_EP_PENDING_REQUEST;
1071 return 0;
1072 }
1073
1074 memset(&params, 0, sizeof(params));
72246da4 1075
4fae2e3e 1076 if (starting) {
1877d6c9
PA		 1077 params.param0 = upper_32_bits(req->trb_dma);
1078 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1079 cmd = DWC3_DEPCMD_STARTTRANSFER |
1080 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1081 } else {
b6b1c6db
FB		 1082 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1083 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1084 }
72246da4 1085
2cd4718d 1086 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1087 if (ret < 0) {
72246da4
FB		 1088 /*
1089 * FIXME we need to iterate over the list of requests
1090 * here and stop, unmap, free and del each of the linked
1d046793 1091 * requests instead of what we do now.
72246da4 1092 */
ce3fc8b3
JD		 1093 if (req->trb)
1094 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1095 dep->queued_requests--;
15b8d933 1096 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1097 return ret;
1098 }
1099
1100 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1101
4fae2e3e 1102 if (starting) {
2eb88016 1103 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1104 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1105 }
25b8ff68 1106
72246da4
FB		 1107 return 0;
1108}
1109
6cb2e4e3
FB		 1110static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1111{
1112 u32 reg;
1113
1114 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1115 return DWC3_DSTS_SOFFN(reg);
1116}
1117
d6d6ec7b
PA		 1118static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1119 struct dwc3_ep *dep, u32 cur_uf)
1120{
1121 u32 uf;
1122
aa3342c8 1123 if (list_empty(&dep->pending_list)) {
5eb30ced 1124 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1125 dep->name);
f4a53c55 1126 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1127 return;
1128 }
1129
1130 /* 4 micro frames in the future */
1131 uf = cur_uf + dep->interval * 4;
1132
4fae2e3e 1133 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1134}
1135
1136static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1137 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1138{
1139 u32 cur_uf, mask;
1140
1141 mask = ~(dep->interval - 1);
1142 cur_uf = event->parameters & mask;
1143
1144 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1145}
1146
72246da4
FB		 1147static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1148{
0fc9a1be
FB		 1149 struct dwc3 *dwc = dep->dwc;
1150 int ret;
1151
bb423984 1152 if (!dep->endpoint.desc) {
5eb30ced
FB		 1153 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1154 dep->name);
bb423984
FB		 1155 return -ESHUTDOWN;
1156 }
1157
1158 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1159 &req->request, req->dep->name)) {
5eb30ced
FB		 1160 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1161 dep->name, &req->request, req->dep->name);
bb423984
FB		 1162 return -EINVAL;
1163 }
1164
fc8bb91b
FB		 1165 pm_runtime_get(dwc->dev);
1166
72246da4
FB		 1167 req->request.actual = 0;
1168 req->request.status = -EINPROGRESS;
1169 req->direction = dep->direction;
1170 req->epnum = dep->number;
1171
fe84f522
FB		 1172 trace_dwc3_ep_queue(req);
1173
0fc9a1be
FB		 1174 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1175 dep->direction);
1176 if (ret)
1177 return ret;
1178
1f512119
FB		 1179 req->sg = req->request.sg;
1180 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1181
aa3342c8 1182 list_add_tail(&req->list, &dep->pending_list);
72246da4 1183
d889c23c
FB		 1184 /*
1185 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1186 * wait for a XferNotReady event so we will know what's the current
1187 * (micro-)frame number.
1188 *
1189 * Without this trick, we are very, very likely gonna get Bus Expiry
1190 * errors which will force us issue EndTransfer command.
1191 */
1192 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1193 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1194 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1195 dwc3_stop_active_transfer(dwc, dep->number, true);
1196 dep->flags = DWC3_EP_ENABLED;
1197 } else {
1198 u32 cur_uf;
1199
1200 cur_uf = __dwc3_gadget_get_frame(dwc);
1201 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1202 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1203 }
08a36b54
FB		 1204 }
1205 return 0;
a0925324 1206 }
72246da4 1207
594e121f
FB		 1208 if (!dwc3_calc_trbs_left(dep))
1209 return 0;
b997ada5 1210
08a36b54 1211 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1212 if (ret == -EBUSY)
1213 ret = 0;
1214
1215 return ret;
72246da4
FB		 1216}
1217
04c03d10
FB		 1218static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1219 struct usb_request *request)
1220{
1221 dwc3_gadget_ep_free_request(ep, request);
1222}
1223
1224static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1225{
1226 struct dwc3_request *req;
1227 struct usb_request *request;
1228 struct usb_ep *ep = &dep->endpoint;
1229
04c03d10
FB		 1230 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1231 if (!request)
1232 return -ENOMEM;
1233
1234 request->length = 0;
1235 request->buf = dwc->zlp_buf;
1236 request->complete = __dwc3_gadget_ep_zlp_complete;
1237
1238 req = to_dwc3_request(request);
1239
1240 return __dwc3_gadget_ep_queue(dep, req);
1241}
1242
72246da4
FB		 1243static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1244 gfp_t gfp_flags)
1245{
1246 struct dwc3_request *req = to_dwc3_request(request);
1247 struct dwc3_ep *dep = to_dwc3_ep(ep);
1248 struct dwc3 *dwc = dep->dwc;
1249
1250 unsigned long flags;
1251
1252 int ret;
1253
fdee4eba 1254 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1255 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1256
1257 /*
1258 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1259 * setting request->zero, instead of doing magic, we will just queue an
1260 * extra usb_request ourselves so that it gets handled the same way as
1261 * any other request.
1262 */
d9261898
JY		 1263 if (ret == 0 && request->zero && request->length &&
1264 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1265 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1266
72246da4
FB		 1267 spin_unlock_irqrestore(&dwc->lock, flags);
1268
1269 return ret;
1270}
1271
1272static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1273 struct usb_request *request)
1274{
1275 struct dwc3_request *req = to_dwc3_request(request);
1276 struct dwc3_request *r = NULL;
1277
1278 struct dwc3_ep *dep = to_dwc3_ep(ep);
1279 struct dwc3 *dwc = dep->dwc;
1280
1281 unsigned long flags;
1282 int ret = 0;
1283
2c4cbe6e
FB		 1284 trace_dwc3_ep_dequeue(req);
1285
72246da4
FB		 1286 spin_lock_irqsave(&dwc->lock, flags);
1287
aa3342c8 1288 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1289 if (r == req)
1290 break;
1291 }
1292
1293 if (r != req) {
aa3342c8 1294 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1295 if (r == req)
1296 break;
1297 }
1298 if (r == req) {
1299 /* wait until it is processed */
b992e681 1300 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1301 goto out1;
72246da4
FB		 1302 }
1303 dev_err(dwc->dev, "request %p was not queued to %s\n",
1304 request, ep->name);
1305 ret = -EINVAL;
1306 goto out0;
1307 }
1308
e8d4e8be 1309out1:
72246da4
FB		 1310 /* giveback the request */
1311 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1312
1313out0:
1314 spin_unlock_irqrestore(&dwc->lock, flags);
1315
1316 return ret;
1317}
1318
7a608559 1319int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1320{
1321 struct dwc3_gadget_ep_cmd_params params;
1322 struct dwc3 *dwc = dep->dwc;
1323 int ret;
1324
5ad02fb8
FB		 1325 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1326 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1327 return -EINVAL;
1328 }
1329
72246da4
FB		 1330 memset(&params, 0x00, sizeof(params));
1331
1332 if (value) {
69450c4d
FB		 1333 struct dwc3_trb *trb;
1334
1335 unsigned transfer_in_flight;
1336 unsigned started;
1337
1338 if (dep->number > 1)
1339 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1340 else
1341 trb = &dwc->ep0_trb[dep->trb_enqueue];
1342
1343 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1344 started = !list_empty(&dep->started_list);
1345
1346 if (!protocol && ((dep->direction && transfer_in_flight) ||
1347 (!dep->direction && started))) {
7a608559
FB		 1348 return -EAGAIN;
1349 }
1350
2cd4718d
FB		 1351 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1352 &params);
72246da4 1353 if (ret)
3f89204b 1354 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1355 dep->name);
1356 else
1357 dep->flags |= DWC3_EP_STALL;
1358 } else {
2cd4718d 1359
50c763f8 1360 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1361 if (ret)
3f89204b 1362 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1363 dep->name);
1364 else
a535d81c 1365 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1366 }
5275455a 1367
72246da4
FB		 1368 return ret;
1369}
1370
1371static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1372{
1373 struct dwc3_ep *dep = to_dwc3_ep(ep);
1374 struct dwc3 *dwc = dep->dwc;
1375
1376 unsigned long flags;
1377
1378 int ret;
1379
1380 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1381 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1382 spin_unlock_irqrestore(&dwc->lock, flags);
1383
1384 return ret;
1385}
1386
1387static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1388{
1389 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1390 struct dwc3 *dwc = dep->dwc;
1391 unsigned long flags;
95aa4e8d 1392 int ret;
72246da4 1393
249a4569 1394 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1395 dep->flags |= DWC3_EP_WEDGE;
1396
08f0d966 1397 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1398 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1399 else
7a608559 1400 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1401 spin_unlock_irqrestore(&dwc->lock, flags);
1402
1403 return ret;
72246da4
FB		 1404}
1405
1406/* -------------------------------------------------------------------------- */
1407
1408static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1409 .bLength = USB_DT_ENDPOINT_SIZE,
1410 .bDescriptorType = USB_DT_ENDPOINT,
1411 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1412};
1413
1414static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1415 .enable = dwc3_gadget_ep0_enable,
1416 .disable = dwc3_gadget_ep0_disable,
1417 .alloc_request = dwc3_gadget_ep_alloc_request,
1418 .free_request = dwc3_gadget_ep_free_request,
1419 .queue = dwc3_gadget_ep0_queue,
1420 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1421 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1422 .set_wedge = dwc3_gadget_ep_set_wedge,
1423};
1424
1425static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1426 .enable = dwc3_gadget_ep_enable,
1427 .disable = dwc3_gadget_ep_disable,
1428 .alloc_request = dwc3_gadget_ep_alloc_request,
1429 .free_request = dwc3_gadget_ep_free_request,
1430 .queue = dwc3_gadget_ep_queue,
1431 .dequeue = dwc3_gadget_ep_dequeue,
1432 .set_halt = dwc3_gadget_ep_set_halt,
1433 .set_wedge = dwc3_gadget_ep_set_wedge,
1434};
1435
1436/* -------------------------------------------------------------------------- */
1437
1438static int dwc3_gadget_get_frame(struct usb_gadget *g)
1439{
1440 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1441
6cb2e4e3 1442 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1443}
1444
218ef7b6 1445static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1446{
d6011f6f 1447 int retries;
72246da4 1448
218ef7b6 1449 int ret;
72246da4
FB		 1450 u32 reg;
1451
72246da4
FB		 1452 u8 link_state;
1453 u8 speed;
1454
72246da4
FB		 1455 /*
1456 * According to the Databook Remote wakeup request should
1457 * be issued only when the device is in early suspend state.
1458 *
1459 * We can check that via USB Link State bits in DSTS register.
1460 */
1461 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1462
1463 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1464 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1465 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1466 return 0;
72246da4
FB		 1467
1468 link_state = DWC3_DSTS_USBLNKST(reg);
1469
1470 switch (link_state) {
1471 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1472 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1473 break;
1474 default:
218ef7b6 1475 return -EINVAL;
72246da4
FB		 1476 }
1477
8598bde7
FB		 1478 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1479 if (ret < 0) {
1480 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1481 return ret;
8598bde7 1482 }
72246da4 1483
802fde98
PZ		 1484 /* Recent versions do this automatically */
1485 if (dwc->revision < DWC3_REVISION_194A) {
1486 /* write zeroes to Link Change Request */
fcc023c7 1487 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1488 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1489 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1490 }
72246da4 1491
1d046793 1492 /* poll until Link State changes to ON */
d6011f6f 1493 retries = 20000;
72246da4 1494
d6011f6f 1495 while (retries--) {
72246da4
FB		 1496 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1497
1498 /* in HS, means ON */
1499 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1500 break;
1501 }
1502
1503 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1504 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1505 return -EINVAL;
72246da4
FB		 1506 }
1507
218ef7b6
FB		 1508 return 0;
1509}
1510
1511static int dwc3_gadget_wakeup(struct usb_gadget *g)
1512{
1513 struct dwc3 *dwc = gadget_to_dwc(g);
1514 unsigned long flags;
1515 int ret;
1516
1517 spin_lock_irqsave(&dwc->lock, flags);
1518 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1519 spin_unlock_irqrestore(&dwc->lock, flags);
1520
1521 return ret;
1522}
1523
1524static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1525 int is_selfpowered)
1526{
1527 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1528 unsigned long flags;
72246da4 1529
249a4569 1530 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1531 g->is_selfpowered = !!is_selfpowered;
249a4569 1532 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1533
1534 return 0;
1535}
1536
7b2a0368 1537static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1538{
1539 u32 reg;
61d58242 1540 u32 timeout = 500;
72246da4 1541
fc8bb91b
FB		 1542 if (pm_runtime_suspended(dwc->dev))
1543 return 0;
1544
72246da4 1545 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1546 if (is_on) {
802fde98
PZ		 1547 if (dwc->revision <= DWC3_REVISION_187A) {
1548 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1549 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1550 }
1551
1552 if (dwc->revision >= DWC3_REVISION_194A)
1553 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1554 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1555
1556 if (dwc->has_hibernation)
1557 reg |= DWC3_DCTL_KEEP_CONNECT;
1558
9fcb3bd8 1559 dwc->pullups_connected = true;
8db7ed15 1560 } else {
72246da4 1561 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1562
1563 if (dwc->has_hibernation && !suspend)
1564 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1565
9fcb3bd8 1566 dwc->pullups_connected = false;
8db7ed15 1567 }
72246da4
FB		 1568
1569 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1570
1571 do {
1572 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1573 reg &= DWC3_DSTS_DEVCTRLHLT;
1574 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1575
1576 if (!timeout)
1577 return -ETIMEDOUT;
72246da4 1578
6f17f74b 1579 return 0;
72246da4
FB		 1580}
1581
1582static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1583{
1584 struct dwc3 *dwc = gadget_to_dwc(g);
1585 unsigned long flags;
6f17f74b 1586 int ret;
72246da4
FB		 1587
1588 is_on = !!is_on;
1589
bb014736
BW		 1590 /*
1591 * Per databook, when we want to stop the gadget, if a control transfer
1592 * is still in process, complete it and get the core into setup phase.
1593 */
1594 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1595 reinit_completion(&dwc->ep0_in_setup);
1596
1597 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1598 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1599 if (ret == 0) {
1600 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1601 return -ETIMEDOUT;
1602 }
1603 }
1604
72246da4 1605 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1606 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1607 spin_unlock_irqrestore(&dwc->lock, flags);
1608
6f17f74b 1609 return ret;
72246da4
FB		 1610}
1611
8698e2ac
FB		 1612static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1613{
1614 u32 reg;
1615
1616 /* Enable all but Start and End of Frame IRQs */
1617 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1618 DWC3_DEVTEN_EVNTOVERFLOWEN |
1619 DWC3_DEVTEN_CMDCMPLTEN |
1620 DWC3_DEVTEN_ERRTICERREN |
1621 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1622 DWC3_DEVTEN_CONNECTDONEEN |
1623 DWC3_DEVTEN_USBRSTEN |
1624 DWC3_DEVTEN_DISCONNEVTEN);
1625
799e9dc8
FB		 1626 if (dwc->revision < DWC3_REVISION_250A)
1627 reg |= DWC3_DEVTEN_ULSTCNGEN;
1628
8698e2ac
FB		 1629 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1630}
1631
1632static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1633{
1634 /* mask all interrupts */
1635 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1636}
1637
1638static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1639static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1640
4e99472b
FB		 1641/**
1642 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1643 * dwc: pointer to our context structure
1644 *
1645 * The following looks like complex but it's actually very simple. In order to
1646 * calculate the number of packets we can burst at once on OUT transfers, we're
1647 * gonna use RxFIFO size.
1648 *
1649 * To calculate RxFIFO size we need two numbers:
1650 * MDWIDTH = size, in bits, of the internal memory bus
1651 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1652 *
1653 * Given these two numbers, the formula is simple:
1654 *
1655 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1656 *
1657 * 24 bytes is for 3x SETUP packets
1658 * 16 bytes is a clock domain crossing tolerance
1659 *
1660 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1661 */
1662static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1663{
1664 u32 ram2_depth;
1665 u32 mdwidth;
1666 u32 nump;
1667 u32 reg;
1668
1669 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1670 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1671
1672 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1673 nump = min_t(u32, nump, 16);
1674
1675 /* update NumP */
1676 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1677 reg &= ~DWC3_DCFG_NUMP_MASK;
1678 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1679 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1680}
1681
d7be2952 1682static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1683{
72246da4 1684 struct dwc3_ep *dep;
72246da4
FB		 1685 int ret = 0;
1686 u32 reg;
1687
cf40b86b
JY		 1688 /*
1689 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1690 * the core supports IMOD, disable it.
1691 */
1692 if (dwc->imod_interval) {
1693 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1694 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1695 } else if (dwc3_has_imod(dwc)) {
1696 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1697 }
1698
72246da4
FB		 1699 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1700 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1701
1702 /**
1703 * WORKAROUND: DWC3 revision < 2.20a have an issue
1704 * which would cause metastability state on Run/Stop
1705 * bit if we try to force the IP to USB2-only mode.
1706 *
1707 * Because of that, we cannot configure the IP to any
1708 * speed other than the SuperSpeed
1709 *
1710 * Refers to:
1711 *
1712 * STAR#9000525659: Clock Domain Crossing on DCTL in
1713 * USB 2.0 Mode
1714 */
f7e846f0 1715 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1716 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1717 } else {
1718 switch (dwc->maximum_speed) {
1719 case USB_SPEED_LOW:
2da9ad76 1720 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1721 break;
1722 case USB_SPEED_FULL:
2da9ad76 1723 reg |= DWC3_DCFG_FULLSPEED1;
f7e846f0
FB		 1724 break;
1725 case USB_SPEED_HIGH:
2da9ad76 1726 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1727 break;
7580862b 1728 case USB_SPEED_SUPER_PLUS:
2da9ad76 1729 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1730 break;
f7e846f0 1731 default:
77966eb8
JY		 1732 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1733 dwc->maximum_speed);
1734 /* fall through */
1735 case USB_SPEED_SUPER:
1736 reg |= DWC3_DCFG_SUPERSPEED;
1737 break;
f7e846f0
FB		 1738 }
1739 }
72246da4
FB		 1740 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1741
2a58f9c1
FB		 1742 /*
1743 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1744 * field instead of letting dwc3 itself calculate that automatically.
1745 *
1746 * This way, we maximize the chances that we'll be able to get several
1747 * bursts of data without going through any sort of endpoint throttling.
1748 */
1749 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1750 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1751 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1752
4e99472b
FB		 1753 dwc3_gadget_setup_nump(dwc);
1754
72246da4
FB		 1755 /* Start with SuperSpeed Default */
1756 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1757
1758 dep = dwc->eps[0];
39ebb05c 1759 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1760 if (ret) {
1761 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1762 goto err0;
72246da4
FB		 1763 }
1764
1765 dep = dwc->eps[1];
39ebb05c 1766 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1767 if (ret) {
1768 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1769 goto err1;
72246da4
FB		 1770 }
1771
1772 /* begin to receive SETUP packets */
c7fcdeb2 1773 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1774 dwc3_ep0_out_start(dwc);
1775
8698e2ac
FB		 1776 dwc3_gadget_enable_irq(dwc);
1777
72246da4
FB		 1778 return 0;
1779
b0d7ffd4 1780err1:
d7be2952 1781 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1782
1783err0:
72246da4
FB		 1784 return ret;
1785}
1786
d7be2952
FB		 1787static int dwc3_gadget_start(struct usb_gadget *g,
1788 struct usb_gadget_driver *driver)
72246da4
FB		 1789{
1790 struct dwc3 *dwc = gadget_to_dwc(g);
1791 unsigned long flags;
d7be2952 1792 int ret = 0;
8698e2ac 1793 int irq;
72246da4 1794
9522def4 1795 irq = dwc->irq_gadget;
d7be2952
FB		 1796 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1797 IRQF_SHARED, "dwc3", dwc->ev_buf);
1798 if (ret) {
1799 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1800 irq, ret);
1801 goto err0;
1802 }
1803
72246da4 1804 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1805 if (dwc->gadget_driver) {
1806 dev_err(dwc->dev, "%s is already bound to %s\n",
1807 dwc->gadget.name,
1808 dwc->gadget_driver->driver.name);
1809 ret = -EBUSY;
1810 goto err1;
1811 }
1812
1813 dwc->gadget_driver = driver;
1814
fc8bb91b
FB		 1815 if (pm_runtime_active(dwc->dev))
1816 __dwc3_gadget_start(dwc);
1817
d7be2952
FB		 1818 spin_unlock_irqrestore(&dwc->lock, flags);
1819
1820 return 0;
1821
1822err1:
1823 spin_unlock_irqrestore(&dwc->lock, flags);
1824 free_irq(irq, dwc);
1825
1826err0:
1827 return ret;
1828}
72246da4 1829
d7be2952
FB		 1830static void __dwc3_gadget_stop(struct dwc3 *dwc)
1831{
8698e2ac 1832 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1833 __dwc3_gadget_ep_disable(dwc->eps[0]);
1834 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1835}
72246da4 1836
d7be2952
FB		 1837static int dwc3_gadget_stop(struct usb_gadget *g)
1838{
1839 struct dwc3 *dwc = gadget_to_dwc(g);
1840 unsigned long flags;
76a638f8 1841 int epnum;
72246da4 1842
d7be2952 1843 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1844
1845 if (pm_runtime_suspended(dwc->dev))
1846 goto out;
1847
d7be2952 1848 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1849
1850 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1851 struct dwc3_ep *dep = dwc->eps[epnum];
1852
1853 if (!dep)
1854 continue;
1855
1856 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1857 continue;
1858
1859 wait_event_lock_irq(dep->wait_end_transfer,
1860 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1861 dwc->lock);
1862 }
1863
1864out:
d7be2952 1865 dwc->gadget_driver = NULL;
72246da4
FB		 1866 spin_unlock_irqrestore(&dwc->lock, flags);
1867
3f308d17 1868 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1869
72246da4
FB		 1870 return 0;
1871}
802fde98 1872
72246da4
FB		 1873static const struct usb_gadget_ops dwc3_gadget_ops = {
1874 .get_frame = dwc3_gadget_get_frame,
1875 .wakeup = dwc3_gadget_wakeup,
1876 .set_selfpowered = dwc3_gadget_set_selfpowered,
1877 .pullup = dwc3_gadget_pullup,
1878 .udc_start = dwc3_gadget_start,
1879 .udc_stop = dwc3_gadget_stop,
1880};
1881
1882/* -------------------------------------------------------------------------- */
1883
6a1e3ef4
FB		 1884static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1885 u8 num, u32 direction)
72246da4
FB		 1886{
1887 struct dwc3_ep *dep;
6a1e3ef4 1888 u8 i;
72246da4 1889
6a1e3ef4 1890 for (i = 0; i < num; i++) {
d07fa665 1891 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1892
72246da4 1893 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1894 if (!dep)
72246da4 1895 return -ENOMEM;
72246da4
FB		 1896
1897 dep->dwc = dwc;
1898 dep->number = epnum;
9aa62ae4 1899 dep->direction = !!direction;
2eb88016 1900 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1901 dwc->eps[epnum] = dep;
1902
1903 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1904 (epnum & 1) ? "in" : "out");
6a1e3ef4 1905
72246da4 1906 dep->endpoint.name = dep->name;
39ebb05c
JY		 1907
1908 if (!(dep->number > 1)) {
1909 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
1910 dep->endpoint.comp_desc = NULL;
1911 }
1912
74674cbf 1913 spin_lock_init(&dep->lock);
72246da4
FB		 1914
1915 if (epnum == 0 || epnum == 1) {
e117e742 1916 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1917 dep->endpoint.maxburst = 1;
72246da4
FB		 1918 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1919 if (!epnum)
1920 dwc->gadget.ep0 = &dep->endpoint;
1921 } else {
1922 int ret;
1923
e117e742 1924 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1925 dep->endpoint.max_streams = 15;
72246da4
FB		 1926 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1927 list_add_tail(&dep->endpoint.ep_list,
1928 &dwc->gadget.ep_list);
1929
1930 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1931 if (ret)
72246da4 1932 return ret;
72246da4 1933 }
25b8ff68 1934
a474d3b7
RB		 1935 if (epnum == 0 || epnum == 1) {
1936 dep->endpoint.caps.type_control = true;
1937 } else {
1938 dep->endpoint.caps.type_iso = true;
1939 dep->endpoint.caps.type_bulk = true;
1940 dep->endpoint.caps.type_int = true;
1941 }
1942
1943 dep->endpoint.caps.dir_in = !!direction;
1944 dep->endpoint.caps.dir_out = !direction;
1945
aa3342c8
FB		 1946 INIT_LIST_HEAD(&dep->pending_list);
1947 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1948 }
1949
1950 return 0;
1951}
1952
6a1e3ef4
FB		 1953static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1954{
1955 int ret;
1956
1957 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1958
1959 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1960 if (ret < 0) {
5eb30ced 1961 dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
6a1e3ef4
FB		 1962 return ret;
1963 }
1964
1965 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1966 if (ret < 0) {
5eb30ced 1967 dev_err(dwc->dev, "failed to initialize IN endpoints\n");
6a1e3ef4
FB		 1968 return ret;
1969 }
1970
1971 return 0;
1972}
1973
72246da4
FB		 1974static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1975{
1976 struct dwc3_ep *dep;
1977 u8 epnum;
1978
1979 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1980 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1981 if (!dep)
1982 continue;
5bf8fae3
GC		 1983 /*
1984 * Physical endpoints 0 and 1 are special; they form the
1985 * bi-directional USB endpoint 0.
1986 *
1987 * For those two physical endpoints, we don't allocate a TRB
1988 * pool nor do we add them the endpoints list. Due to that, we
1989 * shouldn't do these two operations otherwise we would end up
1990 * with all sorts of bugs when removing dwc3.ko.
1991 */
1992 if (epnum != 0 && epnum != 1) {
1993 dwc3_free_trb_pool(dep);
72246da4 1994 list_del(&dep->endpoint.ep_list);
5bf8fae3 1995 }
72246da4
FB		 1996
1997 kfree(dep);
1998 }
1999}
2000
72246da4 2001/* -------------------------------------------------------------------------- */
e5caff68 2002
e5ba5ec8
PA		 2003static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2004 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2005 const struct dwc3_event_depevt *event, int status,
2006 int chain)
72246da4 2007{
72246da4
FB		 2008 unsigned int count;
2009 unsigned int s_pkt = 0;
d6d6ec7b 2010 unsigned int trb_status;
72246da4 2011
dc55c67e 2012 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2013
2014 if (req->trb == trb)
2015 dep->queued_requests--;
2016
2c4cbe6e
FB		 2017 trace_dwc3_complete_trb(dep, trb);
2018
e5b36ae2
FB		 2019 /*
2020 * If we're in the middle of series of chained TRBs and we
2021 * receive a short transfer along the way, DWC3 will skip
2022 * through all TRBs including the last TRB in the chain (the
2023 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2024 * bit and SW has to do it manually.
2025 *
2026 * We're going to do that here to avoid problems of HW trying
2027 * to use bogus TRBs for transfers.
2028 */
2029 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2030 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2031
e5ba5ec8 2032 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
a0ad85ae 2033 return 1;
e5b36ae2 2034
e5ba5ec8 2035 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2036 req->remaining += count;
e5ba5ec8
PA		 2037
2038 if (dep->direction) {
2039 if (count) {
2040 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2041 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2042 /*
2043 * If missed isoc occurred and there is
2044 * no request queued then issue END
2045 * TRANSFER, so that core generates
2046 * next xfernotready and we will issue
2047 * a fresh START TRANSFER.
2048 * If there are still queued request
2049 * then wait, do not issue either END
2050 * or UPDATE TRANSFER, just attach next
aa3342c8 2051 * request in pending_list during
e5ba5ec8
PA		 2052 * giveback.If any future queued request
2053 * is successfully transferred then we
2054 * will issue UPDATE TRANSFER for all
aa3342c8 2055 * request in the pending_list.
e5ba5ec8
PA		 2056 */
2057 dep->flags |= DWC3_EP_MISSED_ISOC;
2058 } else {
2059 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2060 dep->name);
2061 status = -ECONNRESET;
2062 }
2063 } else {
2064 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2065 }
2066 } else {
2067 if (count && (event->status & DEPEVT_STATUS_SHORT))
2068 s_pkt = 1;
2069 }
2070
7c705dfe 2071 if (s_pkt && !chain)
e5ba5ec8 2072 return 1;
f99f53f2 2073
e5ba5ec8
PA		 2074 if ((event->status & DEPEVT_STATUS_IOC) &&
2075 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2076 return 1;
f99f53f2 2077
e5ba5ec8
PA		 2078 return 0;
2079}
2080
2081static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2082 const struct dwc3_event_depevt *event, int status)
2083{
31162af4 2084 struct dwc3_request *req, *n;
e5ba5ec8 2085 struct dwc3_trb *trb;
d6e10bf2 2086 bool ioc = false;
e62c5bc5 2087 int ret = 0;
e5ba5ec8 2088
31162af4 2089 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2090 unsigned length;
e5b36ae2
FB		 2091 int chain;
2092
1f512119
FB		 2093 length = req->request.length;
2094 chain = req->num_pending_sgs > 0;
31162af4 2095 if (chain) {
1f512119 2096 struct scatterlist *sg = req->sg;
31162af4 2097 struct scatterlist *s;
1f512119 2098 unsigned int pending = req->num_pending_sgs;
31162af4 2099 unsigned int i;
c7de5734 2100
1f512119 2101 for_each_sg(sg, s, pending, i) {
31162af4 2102 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2103
7282c4ef
FB		 2104 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2105 break;
2106
1f512119
FB		 2107 req->sg = sg_next(s);
2108 req->num_pending_sgs--;
2109
31162af4
FB		 2110 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2111 event, status, chain);
1f512119
FB		 2112 if (ret)
2113 break;
31162af4
FB		 2114 }
2115 } else {
737f1ae2 2116 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2117 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2118 event, status, chain);
31162af4 2119 }
d115d705 2120
e62c5bc5 2121 req->request.actual = length - req->remaining;
1f512119 2122
ff377ae4 2123 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2124 return __dwc3_gadget_kick_transfer(dep, 0);
2125
d115d705 2126 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2127
d6e10bf2
AB		 2128 if (ret) {
2129 if ((event->status & DEPEVT_STATUS_IOC) &&
2130 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2131 ioc = true;
72246da4 2132 break;
d6e10bf2 2133 }
31162af4 2134 }
72246da4 2135
4cb42217
FB		 2136 /*
2137 * Our endpoint might get disabled by another thread during
2138 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2139 * early on so DWC3_EP_BUSY flag gets cleared
2140 */
2141 if (!dep->endpoint.desc)
2142 return 1;
2143
cdc359dd 2144 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2145 list_empty(&dep->started_list)) {
2146 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2147 /*
2148 * If there is no entry in request list then do
2149 * not issue END TRANSFER now. Just set PENDING
2150 * flag, so that END TRANSFER is issued when an
2151 * entry is added into request list.
2152 */
2153 dep->flags = DWC3_EP_PENDING_REQUEST;
2154 } else {
b992e681 2155 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2156 dep->flags = DWC3_EP_ENABLED;
2157 }
7efea86c
PA		 2158 return 1;
2159 }
2160
d6e10bf2
AB		 2161 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2162 return 0;
2163
72246da4
FB		 2164 return 1;
2165}
2166
2167static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2168 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2169{
2170 unsigned status = 0;
2171 int clean_busy;
e18b7975
FB		 2172 u32 is_xfer_complete;
2173
2174 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2175
2176 if (event->status & DEPEVT_STATUS_BUSERR)
2177 status = -ECONNRESET;
2178
1d046793 2179 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2180 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2181 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2182 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2183
2184 /*
2185 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2186 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2187 */
2188 if (dwc->revision < DWC3_REVISION_183A) {
2189 u32 reg;
2190 int i;
2191
2192 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2193 dep = dwc->eps[i];
fae2b904
FB		 2194
2195 if (!(dep->flags & DWC3_EP_ENABLED))
2196 continue;
2197
aa3342c8 2198 if (!list_empty(&dep->started_list))
fae2b904
FB		 2199 return;
2200 }
2201
2202 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2203 reg |= dwc->u1u2;
2204 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2205
2206 dwc->u1u2 = 0;
2207 }
8a1a9c9e 2208
4cb42217
FB		 2209 /*
2210 * Our endpoint might get disabled by another thread during
2211 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2212 * early on so DWC3_EP_BUSY flag gets cleared
2213 */
2214 if (!dep->endpoint.desc)
2215 return;
2216
e6e709b7 2217 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2218 int ret;
2219
4fae2e3e 2220 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2221 if (!ret || ret == -EBUSY)
2222 return;
2223 }
72246da4
FB		 2224}
2225
72246da4
FB		 2226static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2227 const struct dwc3_event_depevt *event)
2228{
2229 struct dwc3_ep *dep;
2230 u8 epnum = event->endpoint_number;
76a638f8 2231 u8 cmd;
72246da4
FB		 2232
2233 dep = dwc->eps[epnum];
2234
76a638f8
BW		 2235 if (!(dep->flags & DWC3_EP_ENABLED) &&
2236 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3336abb5
FB		 2237 return;
2238
72246da4
FB		 2239 if (epnum == 0 || epnum == 1) {
2240 dwc3_ep0_interrupt(dwc, event);
2241 return;
2242 }
2243
2244 switch (event->endpoint_event) {
2245 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2246 dep->resource_index = 0;
c2df85ca 2247
16e78db7 2248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2249 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2250 return;
2251 }
2252
029d97ff 2253 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2254 break;
2255 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2256 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2257 break;
2258 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2259 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2260 dwc3_gadget_start_isoc(dwc, dep, event);
2261 } else {
2262 int ret;
2263
4fae2e3e 2264 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2265 if (!ret || ret == -EBUSY)
2266 return;
72246da4
FB		 2267 }
2268
879631aa
FB		 2269 break;
2270 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2271 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2272 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2273 dep->name);
2274 return;
2275 }
72246da4 2276 break;
72246da4 2277 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2278 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2279
2280 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2281 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2282 wake_up(&dep->wait_end_transfer);
2283 }
2284 break;
2285 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2286 break;
2287 }
2288}
2289
2290static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2291{
2292 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2293 spin_unlock(&dwc->lock);
2294 dwc->gadget_driver->disconnect(&dwc->gadget);
2295 spin_lock(&dwc->lock);
2296 }
2297}
2298
bc5ba2e0
FB		 2299static void dwc3_suspend_gadget(struct dwc3 *dwc)
2300{
73a30bfc 2301 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2302 spin_unlock(&dwc->lock);
2303 dwc->gadget_driver->suspend(&dwc->gadget);
2304 spin_lock(&dwc->lock);
2305 }
2306}
2307
2308static void dwc3_resume_gadget(struct dwc3 *dwc)
2309{
73a30bfc 2310 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2311 spin_unlock(&dwc->lock);
2312 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2313 spin_lock(&dwc->lock);
8e74475b
FB		 2314 }
2315}
2316
2317static void dwc3_reset_gadget(struct dwc3 *dwc)
2318{
2319 if (!dwc->gadget_driver)
2320 return;
2321
2322 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2323 spin_unlock(&dwc->lock);
2324 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2325 spin_lock(&dwc->lock);
2326 }
2327}
2328
b992e681 2329static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2330{
2331 struct dwc3_ep *dep;
2332 struct dwc3_gadget_ep_cmd_params params;
2333 u32 cmd;
2334 int ret;
2335
2336 dep = dwc->eps[epnum];
2337
76a638f8
BW		 2338 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2339 !dep->resource_index)
3daf74d7
PA		 2340 return;
2341
57911504
PA		 2342 /*
2343 * NOTICE: We are violating what the Databook says about the
2344 * EndTransfer command. Ideally we would _always_ wait for the
2345 * EndTransfer Command Completion IRQ, but that's causing too
2346 * much trouble synchronizing between us and gadget driver.
2347 *
2348 * We have discussed this with the IP Provider and it was
2349 * suggested to giveback all requests here, but give HW some
2350 * extra time to synchronize with the interconnect. We're using
dc93b41a 2351 * an arbitrary 100us delay for that.
57911504
PA		 2352 *
2353 * Note also that a similar handling was tested by Synopsys
2354 * (thanks a lot Paul) and nothing bad has come out of it.
2355 * In short, what we're doing is:
2356 *
2357 * - Issue EndTransfer WITH CMDIOC bit set
2358 * - Wait 100us
06281d46
JY		 2359 *
2360 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2361 * supports a mode to work around the above limitation. The
2362 * software can poll the CMDACT bit in the DEPCMD register
2363 * after issuing a EndTransfer command. This mode is enabled
2364 * by writing GUCTL2[14]. This polling is already done in the
2365 * dwc3_send_gadget_ep_cmd() function so if the mode is
2366 * enabled, the EndTransfer command will have completed upon
2367 * returning from this function and we don't need to delay for
2368 * 100us.
2369 *
2370 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2371 */
2372
3daf74d7 2373 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2374 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2375 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2376 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2377 memset(&params, 0, sizeof(params));
2cd4718d 2378 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2379 WARN_ON_ONCE(ret);
b4996a86 2380 dep->resource_index = 0;
041d81f4 2381 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2382
76a638f8
BW		 2383 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2384 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2385 udelay(100);
76a638f8 2386 }
72246da4
FB		 2387}
2388
72246da4
FB		 2389static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2390{
2391 u32 epnum;
2392
2393 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2394 struct dwc3_ep *dep;
72246da4
FB		 2395 int ret;
2396
2397 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2398 if (!dep)
2399 continue;
72246da4
FB		 2400
2401 if (!(dep->flags & DWC3_EP_STALL))
2402 continue;
2403
2404 dep->flags &= ~DWC3_EP_STALL;
2405
50c763f8 2406 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2407 WARN_ON_ONCE(ret);
2408 }
2409}
2410
2411static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2412{
c4430a26
FB		 2413 int reg;
2414
72246da4
FB		 2415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2416 reg &= ~DWC3_DCTL_INITU1ENA;
2417 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2418
2419 reg &= ~DWC3_DCTL_INITU2ENA;
2420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2421
72246da4
FB		 2422 dwc3_disconnect_gadget(dwc);
2423
2424 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2425 dwc->setup_packet_pending = false;
06a374ed 2426 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2427
2428 dwc->connected = false;
72246da4
FB		 2429}
2430
72246da4
FB		 2431static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2432{
2433 u32 reg;
2434
fc8bb91b
FB		 2435 dwc->connected = true;
2436
df62df56
FB		 2437 /*
2438 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2439 * would cause a missing Disconnect Event if there's a
2440 * pending Setup Packet in the FIFO.
2441 *
2442 * There's no suggested workaround on the official Bug
2443 * report, which states that "unless the driver/application
2444 * is doing any special handling of a disconnect event,
2445 * there is no functional issue".
2446 *
2447 * Unfortunately, it turns out that we _do_ some special
2448 * handling of a disconnect event, namely complete all
2449 * pending transfers, notify gadget driver of the
2450 * disconnection, and so on.
2451 *
2452 * Our suggested workaround is to follow the Disconnect
2453 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2454 * flag. Such flag gets set whenever we have a SETUP_PENDING
2455 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2456 * same endpoint.
2457 *
2458 * Refers to:
2459 *
2460 * STAR#9000466709: RTL: Device : Disconnect event not
2461 * generated if setup packet pending in FIFO
2462 */
2463 if (dwc->revision < DWC3_REVISION_188A) {
2464 if (dwc->setup_packet_pending)
2465 dwc3_gadget_disconnect_interrupt(dwc);
2466 }
2467
8e74475b 2468 dwc3_reset_gadget(dwc);
72246da4
FB		 2469
2470 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2471 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2472 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2473 dwc->test_mode = false;
72246da4
FB		 2474 dwc3_clear_stall_all_ep(dwc);
2475
2476 /* Reset device address to zero */
2477 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2478 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2479 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2480}
2481
72246da4
FB		 2482static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2483{
72246da4
FB		 2484 struct dwc3_ep *dep;
2485 int ret;
2486 u32 reg;
2487 u8 speed;
2488
72246da4
FB		 2489 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2490 speed = reg & DWC3_DSTS_CONNECTSPD;
2491 dwc->speed = speed;
2492
5fb6fdaf
JY		 2493 /*
2494 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2495 * each time on Connect Done.
2496 *
2497 * Currently we always use the reset value. If any platform
2498 * wants to set this to a different value, we need to add a
2499 * setting and update GCTL.RAMCLKSEL here.
2500 */
72246da4
FB		 2501
2502 switch (speed) {
2da9ad76 2503 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2504 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2505 dwc->gadget.ep0->maxpacket = 512;
2506 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2507 break;
2da9ad76 2508 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2509 /*
2510 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2511 * would cause a missing USB3 Reset event.
2512 *
2513 * In such situations, we should force a USB3 Reset
2514 * event by calling our dwc3_gadget_reset_interrupt()
2515 * routine.
2516 *
2517 * Refers to:
2518 *
2519 * STAR#9000483510: RTL: SS : USB3 reset event may
2520 * not be generated always when the link enters poll
2521 */
2522 if (dwc->revision < DWC3_REVISION_190A)
2523 dwc3_gadget_reset_interrupt(dwc);
2524
72246da4
FB		 2525 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2526 dwc->gadget.ep0->maxpacket = 512;
2527 dwc->gadget.speed = USB_SPEED_SUPER;
2528 break;
2da9ad76 2529 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2530 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2531 dwc->gadget.ep0->maxpacket = 64;
2532 dwc->gadget.speed = USB_SPEED_HIGH;
2533 break;
2da9ad76
JY		 2534 case DWC3_DSTS_FULLSPEED2:
2535 case DWC3_DSTS_FULLSPEED1:
72246da4
FB		 2536 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2537 dwc->gadget.ep0->maxpacket = 64;
2538 dwc->gadget.speed = USB_SPEED_FULL;
2539 break;
2da9ad76 2540 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2541 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2542 dwc->gadget.ep0->maxpacket = 8;
2543 dwc->gadget.speed = USB_SPEED_LOW;
2544 break;
2545 }
2546
2b758350
PA		 2547 /* Enable USB2 LPM Capability */
2548
ee5cd41c 2549 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2550 (speed != DWC3_DSTS_SUPERSPEED) &&
2551 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2552 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2553 reg |= DWC3_DCFG_LPM_CAP;
2554 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2555
2556 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2557 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2558
460d098c 2559 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2560
80caf7d2
HR		 2561 /*
2562 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2563 * DCFG.LPMCap is set, core responses with an ACK and the
2564 * BESL value in the LPM token is less than or equal to LPM
2565 * NYET threshold.
2566 */
2567 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2568 && dwc->has_lpm_erratum,
2569 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2570
2571 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2572 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2573
356363bf
FB		 2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575 } else {
2576 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2577 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2578 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2579 }
2580
72246da4 2581 dep = dwc->eps[0];
39ebb05c 2582 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2583 if (ret) {
2584 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2585 return;
2586 }
2587
2588 dep = dwc->eps[1];
39ebb05c 2589 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2590 if (ret) {
2591 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2592 return;
2593 }
2594
2595 /*
2596 * Configure PHY via GUSB3PIPECTLn if required.
2597 *
2598 * Update GTXFIFOSIZn
2599 *
2600 * In both cases reset values should be sufficient.
2601 */
2602}
2603
2604static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2605{
72246da4
FB		 2606 /*
2607 * TODO take core out of low power mode when that's
2608 * implemented.
2609 */
2610
ad14d4e0
JL		 2611 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2612 spin_unlock(&dwc->lock);
2613 dwc->gadget_driver->resume(&dwc->gadget);
2614 spin_lock(&dwc->lock);
2615 }
72246da4
FB		 2616}
2617
2618static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2619 unsigned int evtinfo)
2620{
fae2b904 2621 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2622 unsigned int pwropt;
2623
2624 /*
2625 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2626 * Hibernation mode enabled which would show up when device detects
2627 * host-initiated U3 exit.
2628 *
2629 * In that case, device will generate a Link State Change Interrupt
2630 * from U3 to RESUME which is only necessary if Hibernation is
2631 * configured in.
2632 *
2633 * There are no functional changes due to such spurious event and we
2634 * just need to ignore it.
2635 *
2636 * Refers to:
2637 *
2638 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2639 * operational mode
2640 */
2641 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2642 if ((dwc->revision < DWC3_REVISION_250A) &&
2643 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2644 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2645 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2646 return;
2647 }
2648 }
fae2b904
FB		 2649
2650 /*
2651 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2652 * on the link partner, the USB session might do multiple entry/exit
2653 * of low power states before a transfer takes place.
2654 *
2655 * Due to this problem, we might experience lower throughput. The
2656 * suggested workaround is to disable DCTL[12:9] bits if we're
2657 * transitioning from U1/U2 to U0 and enable those bits again
2658 * after a transfer completes and there are no pending transfers
2659 * on any of the enabled endpoints.
2660 *
2661 * This is the first half of that workaround.
2662 *
2663 * Refers to:
2664 *
2665 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2666 * core send LGO_Ux entering U0
2667 */
2668 if (dwc->revision < DWC3_REVISION_183A) {
2669 if (next == DWC3_LINK_STATE_U0) {
2670 u32 u1u2;
2671 u32 reg;
2672
2673 switch (dwc->link_state) {
2674 case DWC3_LINK_STATE_U1:
2675 case DWC3_LINK_STATE_U2:
2676 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2677 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2678 | DWC3_DCTL_ACCEPTU2ENA
2679 | DWC3_DCTL_INITU1ENA
2680 | DWC3_DCTL_ACCEPTU1ENA);
2681
2682 if (!dwc->u1u2)
2683 dwc->u1u2 = reg & u1u2;
2684
2685 reg &= ~u1u2;
2686
2687 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2688 break;
2689 default:
2690 /* do nothing */
2691 break;
2692 }
2693 }
2694 }
2695
bc5ba2e0
FB		 2696 switch (next) {
2697 case DWC3_LINK_STATE_U1:
2698 if (dwc->speed == USB_SPEED_SUPER)
2699 dwc3_suspend_gadget(dwc);
2700 break;
2701 case DWC3_LINK_STATE_U2:
2702 case DWC3_LINK_STATE_U3:
2703 dwc3_suspend_gadget(dwc);
2704 break;
2705 case DWC3_LINK_STATE_RESUME:
2706 dwc3_resume_gadget(dwc);
2707 break;
2708 default:
2709 /* do nothing */
2710 break;
2711 }
2712
e57ebc1d 2713 dwc->link_state = next;
72246da4
FB		 2714}
2715
72704f87
BW		 2716static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2717 unsigned int evtinfo)
2718{
2719 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2720
2721 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2722 dwc3_suspend_gadget(dwc);
2723
2724 dwc->link_state = next;
2725}
2726
e1dadd3b
FB		 2727static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2728 unsigned int evtinfo)
2729{
2730 unsigned int is_ss = evtinfo & BIT(4);
2731
2732 /**
2733 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2734 * have a known issue which can cause USB CV TD.9.23 to fail
2735 * randomly.
2736 *
2737 * Because of this issue, core could generate bogus hibernation
2738 * events which SW needs to ignore.
2739 *
2740 * Refers to:
2741 *
2742 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2743 * Device Fallback from SuperSpeed
2744 */
2745 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2746 return;
2747
2748 /* enter hibernation here */
2749}
2750
72246da4
FB		 2751static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2752 const struct dwc3_event_devt *event)
2753{
2754 switch (event->type) {
2755 case DWC3_DEVICE_EVENT_DISCONNECT:
2756 dwc3_gadget_disconnect_interrupt(dwc);
2757 break;
2758 case DWC3_DEVICE_EVENT_RESET:
2759 dwc3_gadget_reset_interrupt(dwc);
2760 break;
2761 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2762 dwc3_gadget_conndone_interrupt(dwc);
2763 break;
2764 case DWC3_DEVICE_EVENT_WAKEUP:
2765 dwc3_gadget_wakeup_interrupt(dwc);
2766 break;
e1dadd3b
FB		 2767 case DWC3_DEVICE_EVENT_HIBER_REQ:
2768 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2769 "unexpected hibernation event\n"))
2770 break;
2771
2772 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2773 break;
72246da4
FB		 2774 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2775 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2776 break;
2777 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2778 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2779 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2780 /*
2781 * Ignore suspend event until the gadget enters into
2782 * USB_STATE_CONFIGURED state.
2783 */
2784 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2785 dwc3_gadget_suspend_interrupt(dwc,
2786 event->event_info);
2787 }
72246da4
FB		 2788 break;
2789 case DWC3_DEVICE_EVENT_SOF:
72246da4 2790 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2791 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2792 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2793 break;
2794 default:
e9f2aa87 2795 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2796 }
2797}
2798
2799static void dwc3_process_event_entry(struct dwc3 *dwc,
2800 const union dwc3_event *event)
2801{
43c96be1 2802 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2803
72246da4
FB		 2804 /* Endpoint IRQ, handle it and return early */
2805 if (event->type.is_devspec == 0) {
2806 /* depevt */
2807 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2808 }
2809
2810 switch (event->type.type) {
2811 case DWC3_EVENT_TYPE_DEV:
2812 dwc3_gadget_interrupt(dwc, &event->devt);
2813 break;
2814 /* REVISIT what to do with Carkit and I2C events ? */
2815 default:
2816 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2817 }
2818}
2819
dea520a4 2820static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2821{
dea520a4 2822 struct dwc3 *dwc = evt->dwc;
b15a762f 2823 irqreturn_t ret = IRQ_NONE;
f42f2447 2824 int left;
e8adfc30 2825 u32 reg;
b15a762f 2826
f42f2447 2827 left = evt->count;
b15a762f 2828
f42f2447
FB		 2829 if (!(evt->flags & DWC3_EVENT_PENDING))
2830 return IRQ_NONE;
b15a762f 2831
f42f2447
FB		 2832 while (left > 0) {
2833 union dwc3_event event;
b15a762f 2834
ebbb2d59 2835 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2836
f42f2447 2837 dwc3_process_event_entry(dwc, &event);
b15a762f 2838
f42f2447
FB		 2839 /*
2840 * FIXME we wrap around correctly to the next entry as
2841 * almost all entries are 4 bytes in size. There is one
2842 * entry which has 12 bytes which is a regular entry
2843 * followed by 8 bytes data. ATM I don't know how
2844 * things are organized if we get next to the a
2845 * boundary so I worry about that once we try to handle
2846 * that.
2847 */
caefe6c7 2848 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2849 left -= 4;
f42f2447 2850 }
b15a762f 2851
f42f2447
FB		 2852 evt->count = 0;
2853 evt->flags &= ~DWC3_EVENT_PENDING;
2854 ret = IRQ_HANDLED;
b15a762f 2855
f42f2447 2856 /* Unmask interrupt */
660e9bde 2857 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2858 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2859 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2860
cf40b86b
JY		 2861 if (dwc->imod_interval) {
2862 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2863 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2864 }
2865
f42f2447
FB		 2866 return ret;
2867}
e8adfc30 2868
dea520a4 2869static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2870{
dea520a4
FB		 2871 struct dwc3_event_buffer *evt = _evt;
2872 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2873 unsigned long flags;
f42f2447 2874 irqreturn_t ret = IRQ_NONE;
f42f2447 2875
e5f68b4a 2876 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2877 ret = dwc3_process_event_buf(evt);
e5f68b4a 2878 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2879
2880 return ret;
2881}
2882
dea520a4 2883static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2884{
dea520a4 2885 struct dwc3 *dwc = evt->dwc;
ebbb2d59 2886 u32 amount;
72246da4 2887 u32 count;
e8adfc30 2888 u32 reg;
72246da4 2889
fc8bb91b
FB		 2890 if (pm_runtime_suspended(dwc->dev)) {
2891 pm_runtime_get(dwc->dev);
2892 disable_irq_nosync(dwc->irq_gadget);
2893 dwc->pending_events = true;
2894 return IRQ_HANDLED;
2895 }
2896
660e9bde 2897 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2898 count &= DWC3_GEVNTCOUNT_MASK;
2899 if (!count)
2900 return IRQ_NONE;
2901
b15a762f
FB		 2902 evt->count = count;
2903 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2904
e8adfc30 2905 /* Mask interrupt */
660e9bde 2906 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2907 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2908 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2909
ebbb2d59
JY		 2910 amount = min(count, evt->length - evt->lpos);
2911 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
2912
2913 if (amount < count)
2914 memcpy(evt->cache, evt->buf, count - amount);
2915
65aca320
JY		 2916 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2917
b15a762f 2918 return IRQ_WAKE_THREAD;
72246da4
FB		 2919}
2920
dea520a4 2921static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2922{
dea520a4 2923 struct dwc3_event_buffer *evt = _evt;
72246da4 2924
dea520a4 2925 return dwc3_check_event_buf(evt);
72246da4
FB		 2926}
2927
6db3812e
FB		 2928static int dwc3_gadget_get_irq(struct dwc3 *dwc)
2929{
2930 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2931 int irq;
2932
2933 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2934 if (irq > 0)
2935 goto out;
2936
2937 if (irq == -EPROBE_DEFER)
2938 goto out;
2939
2940 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2941 if (irq > 0)
2942 goto out;
2943
2944 if (irq == -EPROBE_DEFER)
2945 goto out;
2946
2947 irq = platform_get_irq(dwc3_pdev, 0);
2948 if (irq > 0)
2949 goto out;
2950
2951 if (irq != -EPROBE_DEFER)
2952 dev_err(dwc->dev, "missing peripheral IRQ\n");
2953
2954 if (!irq)
2955 irq = -EINVAL;
2956
2957out:
2958 return irq;
2959}
2960
72246da4
FB		 2961/**
2962 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2963 * @dwc: pointer to our controller context structure
72246da4
FB		 2964 *
2965 * Returns 0 on success otherwise negative errno.
2966 */
41ac7b3a 2967int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2968{
6db3812e
FB		 2969 int ret;
2970 int irq;
9522def4 2971
6db3812e
FB		 2972 irq = dwc3_gadget_get_irq(dwc);
2973 if (irq < 0) {
2974 ret = irq;
2975 goto err0;
9522def4
RQ		 2976 }
2977
2978 dwc->irq_gadget = irq;
72246da4
FB		 2979
2980 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2981 &dwc->ctrl_req_addr, GFP_KERNEL);
2982 if (!dwc->ctrl_req) {
2983 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2984 ret = -ENOMEM;
2985 goto err0;
2986 }
2987
2abd9d5f 2988 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2989 &dwc->ep0_trb_addr, GFP_KERNEL);
2990 if (!dwc->ep0_trb) {
2991 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2992 ret = -ENOMEM;
2993 goto err1;
2994 }
2995
3ef35faf 2996 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2997 if (!dwc->setup_buf) {
72246da4
FB		 2998 ret = -ENOMEM;
2999 goto err2;
3000 }
3001
5812b1c2 3002 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 3003 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3004 GFP_KERNEL);
5812b1c2
FB		 3005 if (!dwc->ep0_bounce) {
3006 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3007 ret = -ENOMEM;
3008 goto err3;
3009 }
3010
04c03d10
FB		 3011 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3012 if (!dwc->zlp_buf) {
3013 ret = -ENOMEM;
3014 goto err4;
3015 }
3016
bb014736
BW		 3017 init_completion(&dwc->ep0_in_setup);
3018
72246da4 3019 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3020 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3021 dwc->gadget.sg_supported = true;
72246da4 3022 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3023 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3024
b9e51b2b
BM		 3025 /*
3026 * FIXME We might be setting max_speed to <SUPER, however versions
3027 * <2.20a of dwc3 have an issue with metastability (documented
3028 * elsewhere in this driver) which tells us we can't set max speed to
3029 * anything lower than SUPER.
3030 *
3031 * Because gadget.max_speed is only used by composite.c and function
3032 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3033 * to happen so we avoid sending SuperSpeed Capability descriptor
3034 * together with our BOS descriptor as that could confuse host into
3035 * thinking we can handle super speed.
3036 *
3037 * Note that, in fact, we won't even support GetBOS requests when speed
3038 * is less than super speed because we don't have means, yet, to tell
3039 * composite.c that we are USB 2.0 + LPM ECN.
3040 */
3041 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3042 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3043 dwc->revision);
3044
3045 dwc->gadget.max_speed = dwc->maximum_speed;
3046
a4b9d94b
DC		 3047 /*
3048 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3049 * on ep out.
3050 */
3051 dwc->gadget.quirk_ep_out_aligned_size = true;
3052
72246da4
FB		 3053 /*
3054 * REVISIT: Here we should clear all pending IRQs to be
3055 * sure we're starting from a well known location.
3056 */
3057
3058 ret = dwc3_gadget_init_endpoints(dwc);
3059 if (ret)
04c03d10 3060 goto err5;
72246da4 3061
72246da4
FB		 3062 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3063 if (ret) {
3064 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 3065 goto err5;
72246da4
FB		 3066 }
3067
3068 return 0;
3069
04c03d10
FB		 3070err5:
3071 kfree(dwc->zlp_buf);
3072
5812b1c2 3073err4:
e1f80467 3074 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 3075 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3076 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3077
72246da4 3078err3:
0fc9a1be 3079 kfree(dwc->setup_buf);
72246da4
FB		 3080
3081err2:
51fbc7c0 3082 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3083 dwc->ep0_trb, dwc->ep0_trb_addr);
3084
3085err1:
3086 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3087 dwc->ctrl_req, dwc->ctrl_req_addr);
3088
3089err0:
3090 return ret;
3091}
3092
7415f17c
FB		 3093/* -------------------------------------------------------------------------- */
3094
72246da4
FB		 3095void dwc3_gadget_exit(struct dwc3 *dwc)
3096{
72246da4 3097 usb_del_gadget_udc(&dwc->gadget);
72246da4 3098
72246da4
FB		 3099 dwc3_gadget_free_endpoints(dwc);
3100
3ef35faf
FB		 3101 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3102 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3103
0fc9a1be 3104 kfree(dwc->setup_buf);
04c03d10 3105 kfree(dwc->zlp_buf);
72246da4 3106
51fbc7c0 3107 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3108 dwc->ep0_trb, dwc->ep0_trb_addr);
3109
3110 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3111 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3112}
7415f17c 3113
0b0231aa 3114int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3115{
9f8a67b6
FB		 3116 int ret;
3117
9772b47a
RQ		 3118 if (!dwc->gadget_driver)
3119 return 0;
3120
9f8a67b6
FB		 3121 ret = dwc3_gadget_run_stop(dwc, false, false);
3122 if (ret < 0)
3123 return ret;
7415f17c 3124
9f8a67b6
FB		 3125 dwc3_disconnect_gadget(dwc);
3126 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3127
3128 return 0;
3129}
3130
3131int dwc3_gadget_resume(struct dwc3 *dwc)
3132{
7415f17c
FB		 3133 int ret;
3134
9772b47a
RQ		 3135 if (!dwc->gadget_driver)
3136 return 0;
3137
9f8a67b6
FB		 3138 ret = __dwc3_gadget_start(dwc);
3139 if (ret < 0)
7415f17c
FB		 3140 goto err0;
3141
9f8a67b6
FB		 3142 ret = dwc3_gadget_run_stop(dwc, true, false);
3143 if (ret < 0)
7415f17c
FB		 3144 goto err1;
3145
7415f17c
FB		 3146 return 0;
3147
3148err1:
9f8a67b6 3149 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3150
3151err0:
3152 return ret;
3153}
fc8bb91b
FB		 3154
3155void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3156{
3157 if (dwc->pending_events) {
3158 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3159 dwc->pending_events = false;
3160 enable_irq(dwc->irq_gadget);
3161 }
3162}
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