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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
73815280 FB |
142 | dwc3_trace(trace_dwc3_gadget, |
143 | "link state change request timed out"); | |
8598bde7 FB |
144 | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
457e84b6 FB |
148 | /** |
149 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
150 | * @dwc: pointer to our context structure | |
151 | * | |
152 | * This function will a best effort FIFO allocation in order | |
153 | * to improve FIFO usage and throughput, while still allowing | |
154 | * us to enable as many endpoints as possible. | |
155 | * | |
156 | * Keep in mind that this operation will be highly dependent | |
157 | * on the configured size for RAM1 - which contains TxFifo -, | |
158 | * the amount of endpoints enabled on coreConsultant tool, and | |
159 | * the width of the Master Bus. | |
160 | * | |
161 | * In the ideal world, we would always be able to satisfy the | |
162 | * following equation: | |
163 | * | |
164 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
165 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
166 | * | |
167 | * Unfortunately, due to many variables that's not always the case. | |
168 | */ | |
169 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
170 | { | |
171 | int last_fifo_depth = 0; | |
172 | int ram1_depth; | |
173 | int fifo_size; | |
174 | int mdwidth; | |
175 | int num; | |
176 | ||
177 | if (!dwc->needs_fifo_resize) | |
178 | return 0; | |
179 | ||
180 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
181 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
182 | ||
183 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
184 | mdwidth >>= 3; | |
185 | ||
186 | /* | |
187 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
188 | * for each enabled endpoint, later patches will come to | |
189 | * improve this algorithm so that we better use the internal | |
190 | * FIFO space | |
191 | */ | |
32702e96 JP |
192 | for (num = 0; num < dwc->num_in_eps; num++) { |
193 | /* bit0 indicates direction; 1 means IN ep */ | |
194 | struct dwc3_ep *dep = dwc->eps[(num << 1) | 1]; | |
2e81c36a | 195 | int mult = 1; |
457e84b6 FB |
196 | int tmp; |
197 | ||
457e84b6 FB |
198 | if (!(dep->flags & DWC3_EP_ENABLED)) |
199 | continue; | |
200 | ||
16e78db7 IS |
201 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
202 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
203 | mult = 3; |
204 | ||
205 | /* | |
206 | * REVISIT: the following assumes we will always have enough | |
207 | * space available on the FIFO RAM for all possible use cases. | |
208 | * Make sure that's true somehow and change FIFO allocation | |
209 | * accordingly. | |
210 | * | |
211 | * If we have Bulk or Isochronous endpoints, we want | |
212 | * them to be able to be very, very fast. So we're giving | |
213 | * those endpoints a fifo_size which is enough for 3 full | |
214 | * packets | |
215 | */ | |
216 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
217 | tmp += mdwidth; |
218 | ||
219 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 220 | |
457e84b6 FB |
221 | fifo_size |= (last_fifo_depth << 16); |
222 | ||
73815280 | 223 | dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d", |
457e84b6 FB |
224 | dep->name, last_fifo_depth, fifo_size & 0xffff); |
225 | ||
32702e96 | 226 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size); |
457e84b6 FB |
227 | |
228 | last_fifo_depth += (fifo_size & 0xffff); | |
229 | } | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
72246da4 FB |
234 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
235 | int status) | |
236 | { | |
237 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 238 | int i; |
72246da4 FB |
239 | |
240 | if (req->queued) { | |
e5ba5ec8 PA |
241 | i = 0; |
242 | do { | |
eeb720fb | 243 | dep->busy_slot++; |
e5ba5ec8 PA |
244 | /* |
245 | * Skip LINK TRB. We can't use req->trb and check for | |
246 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
247 | * just completed (not the LINK TRB). | |
248 | */ | |
249 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
250 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 251 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
252 | dep->busy_slot++; |
253 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 254 | req->queued = false; |
72246da4 FB |
255 | } |
256 | list_del(&req->list); | |
eeb720fb | 257 | req->trb = NULL; |
72246da4 FB |
258 | |
259 | if (req->request.status == -EINPROGRESS) | |
260 | req->request.status = status; | |
261 | ||
0416e494 PA |
262 | if (dwc->ep0_bounced && dep->number == 0) |
263 | dwc->ep0_bounced = false; | |
264 | else | |
265 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
266 | req->direction); | |
72246da4 FB |
267 | |
268 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
269 | req, dep->name, req->request.actual, | |
270 | req->request.length, status); | |
2c4cbe6e | 271 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
272 | |
273 | spin_unlock(&dwc->lock); | |
304f7e5e | 274 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
275 | spin_lock(&dwc->lock); |
276 | } | |
277 | ||
3ece0ec4 | 278 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
279 | { |
280 | u32 timeout = 500; | |
281 | u32 reg; | |
282 | ||
2c4cbe6e | 283 | trace_dwc3_gadget_generic_cmd(cmd, param); |
427c3df6 | 284 | |
b09bb642 FB |
285 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); |
286 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
287 | ||
288 | do { | |
289 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
290 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
73815280 FB |
291 | dwc3_trace(trace_dwc3_gadget, |
292 | "Command Complete --> %d", | |
b09bb642 | 293 | DWC3_DGCMD_STATUS(reg)); |
891b1dc0 SSB |
294 | if (DWC3_DGCMD_STATUS(reg)) |
295 | return -EINVAL; | |
b09bb642 FB |
296 | return 0; |
297 | } | |
298 | ||
299 | /* | |
300 | * We can't sleep here, because it's also called from | |
301 | * interrupt context. | |
302 | */ | |
303 | timeout--; | |
73815280 FB |
304 | if (!timeout) { |
305 | dwc3_trace(trace_dwc3_gadget, | |
306 | "Command Timed Out"); | |
b09bb642 | 307 | return -ETIMEDOUT; |
73815280 | 308 | } |
b09bb642 FB |
309 | udelay(1); |
310 | } while (1); | |
311 | } | |
312 | ||
72246da4 FB |
313 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
314 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
315 | { | |
316 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 317 | u32 timeout = 500; |
72246da4 FB |
318 | u32 reg; |
319 | ||
2c4cbe6e | 320 | trace_dwc3_gadget_ep_cmd(dep, cmd, params); |
72246da4 | 321 | |
dc1c70a7 FB |
322 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
323 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
324 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
325 | |
326 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
327 | do { | |
328 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
329 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
73815280 FB |
330 | dwc3_trace(trace_dwc3_gadget, |
331 | "Command Complete --> %d", | |
164f6e14 | 332 | DWC3_DEPCMD_STATUS(reg)); |
76e838c9 SSB |
333 | if (DWC3_DEPCMD_STATUS(reg)) |
334 | return -EINVAL; | |
72246da4 FB |
335 | return 0; |
336 | } | |
337 | ||
338 | /* | |
72246da4 FB |
339 | * We can't sleep here, because it is also called from |
340 | * interrupt context. | |
341 | */ | |
342 | timeout--; | |
73815280 FB |
343 | if (!timeout) { |
344 | dwc3_trace(trace_dwc3_gadget, | |
345 | "Command Timed Out"); | |
72246da4 | 346 | return -ETIMEDOUT; |
73815280 | 347 | } |
72246da4 | 348 | |
61d58242 | 349 | udelay(1); |
72246da4 FB |
350 | } while (1); |
351 | } | |
352 | ||
353 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 354 | struct dwc3_trb *trb) |
72246da4 | 355 | { |
c439ef87 | 356 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
357 | |
358 | return dep->trb_pool_dma + offset; | |
359 | } | |
360 | ||
361 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
362 | { | |
363 | struct dwc3 *dwc = dep->dwc; | |
364 | ||
365 | if (dep->trb_pool) | |
366 | return 0; | |
367 | ||
72246da4 FB |
368 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
369 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
370 | &dep->trb_pool_dma, GFP_KERNEL); | |
371 | if (!dep->trb_pool) { | |
372 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
373 | dep->name); | |
374 | return -ENOMEM; | |
375 | } | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
381 | { | |
382 | struct dwc3 *dwc = dep->dwc; | |
383 | ||
384 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
385 | dep->trb_pool, dep->trb_pool_dma); | |
386 | ||
387 | dep->trb_pool = NULL; | |
388 | dep->trb_pool_dma = 0; | |
389 | } | |
390 | ||
391 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
392 | { | |
393 | struct dwc3_gadget_ep_cmd_params params; | |
394 | u32 cmd; | |
395 | ||
396 | memset(¶ms, 0x00, sizeof(params)); | |
397 | ||
398 | if (dep->number != 1) { | |
399 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
400 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
401 | if (dep->number > 1) { |
402 | if (dwc->start_config_issued) | |
403 | return 0; | |
404 | dwc->start_config_issued = true; | |
72246da4 | 405 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 406 | } |
72246da4 FB |
407 | |
408 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 415 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 416 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 417 | bool ignore, bool restore) |
72246da4 FB |
418 | { |
419 | struct dwc3_gadget_ep_cmd_params params; | |
420 | ||
421 | memset(¶ms, 0x00, sizeof(params)); | |
422 | ||
dc1c70a7 | 423 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
424 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
425 | ||
426 | /* Burst size is only needed in SuperSpeed mode */ | |
427 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
428 | u32 burst = dep->endpoint.maxburst - 1; | |
429 | ||
430 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
431 | } | |
72246da4 | 432 | |
4b345c9a FB |
433 | if (ignore) |
434 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
435 | ||
265b70a7 PZ |
436 | if (restore) { |
437 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
438 | params.param2 |= dep->saved_state; | |
439 | } | |
440 | ||
dc1c70a7 FB |
441 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
442 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 443 | |
18b7ede5 | 444 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
445 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
446 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
447 | dep->stream_capable = true; |
448 | } | |
449 | ||
0b93a4c8 | 450 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 451 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
452 | |
453 | /* | |
454 | * We are doing 1:1 mapping for endpoints, meaning | |
455 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
456 | * so on. We consider the direction bit as part of the physical | |
457 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
458 | */ | |
dc1c70a7 | 459 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
460 | |
461 | /* | |
462 | * We must use the lower 16 TX FIFOs even though | |
463 | * HW might have more | |
464 | */ | |
465 | if (dep->direction) | |
dc1c70a7 | 466 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
467 | |
468 | if (desc->bInterval) { | |
dc1c70a7 | 469 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
470 | dep->interval = 1 << (desc->bInterval - 1); |
471 | } | |
472 | ||
473 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
474 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
475 | } | |
476 | ||
477 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
478 | { | |
479 | struct dwc3_gadget_ep_cmd_params params; | |
480 | ||
481 | memset(¶ms, 0x00, sizeof(params)); | |
482 | ||
dc1c70a7 | 483 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
484 | |
485 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
486 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
487 | } | |
488 | ||
489 | /** | |
490 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
491 | * @dep: endpoint to be initialized | |
492 | * @desc: USB Endpoint Descriptor | |
493 | * | |
494 | * Caller should take care of locking | |
495 | */ | |
496 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 497 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 498 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 499 | bool ignore, bool restore) |
72246da4 FB |
500 | { |
501 | struct dwc3 *dwc = dep->dwc; | |
502 | u32 reg; | |
b09e99ee | 503 | int ret; |
72246da4 | 504 | |
73815280 | 505 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); |
ff62d6b6 | 506 | |
72246da4 FB |
507 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
508 | ret = dwc3_gadget_start_config(dwc, dep); | |
509 | if (ret) | |
510 | return ret; | |
511 | } | |
512 | ||
265b70a7 PZ |
513 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
514 | restore); | |
72246da4 FB |
515 | if (ret) |
516 | return ret; | |
517 | ||
518 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
519 | struct dwc3_trb *trb_st_hw; |
520 | struct dwc3_trb *trb_link; | |
72246da4 FB |
521 | |
522 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
523 | if (ret) | |
524 | return ret; | |
525 | ||
16e78db7 | 526 | dep->endpoint.desc = desc; |
c90bfaec | 527 | dep->comp_desc = comp_desc; |
72246da4 FB |
528 | dep->type = usb_endpoint_type(desc); |
529 | dep->flags |= DWC3_EP_ENABLED; | |
530 | ||
531 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
532 | reg |= DWC3_DALEPENA_EP(dep->number); | |
533 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
534 | ||
535 | if (!usb_endpoint_xfer_isoc(desc)) | |
536 | return 0; | |
537 | ||
1d046793 | 538 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
539 | trb_st_hw = &dep->trb_pool[0]; |
540 | ||
f6bafc6a | 541 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
1200a82a | 542 | memset(trb_link, 0, sizeof(*trb_link)); |
72246da4 | 543 | |
f6bafc6a FB |
544 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
545 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
546 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
547 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
548 | } |
549 | ||
aa739974 FB |
550 | switch (usb_endpoint_type(desc)) { |
551 | case USB_ENDPOINT_XFER_CONTROL: | |
552 | strlcat(dep->name, "-control", sizeof(dep->name)); | |
553 | break; | |
554 | case USB_ENDPOINT_XFER_ISOC: | |
555 | strlcat(dep->name, "-isoc", sizeof(dep->name)); | |
556 | break; | |
557 | case USB_ENDPOINT_XFER_BULK: | |
558 | strlcat(dep->name, "-bulk", sizeof(dep->name)); | |
559 | break; | |
560 | case USB_ENDPOINT_XFER_INT: | |
561 | strlcat(dep->name, "-int", sizeof(dep->name)); | |
562 | break; | |
563 | default: | |
564 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
565 | } | |
566 | ||
72246da4 FB |
567 | return 0; |
568 | } | |
569 | ||
b992e681 | 570 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 571 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
572 | { |
573 | struct dwc3_request *req; | |
574 | ||
ea53b882 | 575 | if (!list_empty(&dep->req_queued)) { |
b992e681 | 576 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 577 | |
57911504 | 578 | /* - giveback all requests to gadget driver */ |
1591633e PA |
579 | while (!list_empty(&dep->req_queued)) { |
580 | req = next_request(&dep->req_queued); | |
581 | ||
582 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
583 | } | |
ea53b882 FB |
584 | } |
585 | ||
72246da4 FB |
586 | while (!list_empty(&dep->request_list)) { |
587 | req = next_request(&dep->request_list); | |
588 | ||
624407f9 | 589 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 590 | } |
72246da4 FB |
591 | } |
592 | ||
593 | /** | |
594 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
595 | * @dep: the endpoint to disable | |
596 | * | |
624407f9 SAS |
597 | * This function also removes requests which are currently processed ny the |
598 | * hardware and those which are not yet scheduled. | |
599 | * Caller should take care of locking. | |
72246da4 | 600 | */ |
72246da4 FB |
601 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
602 | { | |
603 | struct dwc3 *dwc = dep->dwc; | |
604 | u32 reg; | |
605 | ||
7eaeac5c FB |
606 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); |
607 | ||
624407f9 | 608 | dwc3_remove_requests(dwc, dep); |
72246da4 | 609 | |
687ef981 FB |
610 | /* make sure HW endpoint isn't stalled */ |
611 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 612 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 613 | |
72246da4 FB |
614 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
615 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
616 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
617 | ||
879631aa | 618 | dep->stream_capable = false; |
f9c56cdd | 619 | dep->endpoint.desc = NULL; |
c90bfaec | 620 | dep->comp_desc = NULL; |
72246da4 | 621 | dep->type = 0; |
879631aa | 622 | dep->flags = 0; |
72246da4 | 623 | |
aa739974 FB |
624 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", |
625 | dep->number >> 1, | |
626 | (dep->number & 1) ? "in" : "out"); | |
627 | ||
72246da4 FB |
628 | return 0; |
629 | } | |
630 | ||
631 | /* -------------------------------------------------------------------------- */ | |
632 | ||
633 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
634 | const struct usb_endpoint_descriptor *desc) | |
635 | { | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
639 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
640 | { | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
644 | /* -------------------------------------------------------------------------- */ | |
645 | ||
646 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
647 | const struct usb_endpoint_descriptor *desc) | |
648 | { | |
649 | struct dwc3_ep *dep; | |
650 | struct dwc3 *dwc; | |
651 | unsigned long flags; | |
652 | int ret; | |
653 | ||
654 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
655 | pr_debug("dwc3: invalid parameters\n"); | |
656 | return -EINVAL; | |
657 | } | |
658 | ||
659 | if (!desc->wMaxPacketSize) { | |
660 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
661 | return -EINVAL; | |
662 | } | |
663 | ||
664 | dep = to_dwc3_ep(ep); | |
665 | dwc = dep->dwc; | |
666 | ||
c6f83f38 FB |
667 | if (dep->flags & DWC3_EP_ENABLED) { |
668 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
669 | dep->name); | |
670 | return 0; | |
671 | } | |
672 | ||
72246da4 | 673 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 674 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
675 | spin_unlock_irqrestore(&dwc->lock, flags); |
676 | ||
677 | return ret; | |
678 | } | |
679 | ||
680 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
681 | { | |
682 | struct dwc3_ep *dep; | |
683 | struct dwc3 *dwc; | |
684 | unsigned long flags; | |
685 | int ret; | |
686 | ||
687 | if (!ep) { | |
688 | pr_debug("dwc3: invalid parameters\n"); | |
689 | return -EINVAL; | |
690 | } | |
691 | ||
692 | dep = to_dwc3_ep(ep); | |
693 | dwc = dep->dwc; | |
694 | ||
695 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
696 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
697 | dep->name); | |
698 | return 0; | |
699 | } | |
700 | ||
72246da4 FB |
701 | spin_lock_irqsave(&dwc->lock, flags); |
702 | ret = __dwc3_gadget_ep_disable(dep); | |
703 | spin_unlock_irqrestore(&dwc->lock, flags); | |
704 | ||
705 | return ret; | |
706 | } | |
707 | ||
708 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
709 | gfp_t gfp_flags) | |
710 | { | |
711 | struct dwc3_request *req; | |
712 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
713 | |
714 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 715 | if (!req) |
72246da4 | 716 | return NULL; |
72246da4 FB |
717 | |
718 | req->epnum = dep->number; | |
719 | req->dep = dep; | |
72246da4 | 720 | |
2c4cbe6e FB |
721 | trace_dwc3_alloc_request(req); |
722 | ||
72246da4 FB |
723 | return &req->request; |
724 | } | |
725 | ||
726 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
727 | struct usb_request *request) | |
728 | { | |
729 | struct dwc3_request *req = to_dwc3_request(request); | |
730 | ||
2c4cbe6e | 731 | trace_dwc3_free_request(req); |
72246da4 FB |
732 | kfree(req); |
733 | } | |
734 | ||
c71fc37c FB |
735 | /** |
736 | * dwc3_prepare_one_trb - setup one TRB from one request | |
737 | * @dep: endpoint for which this request is prepared | |
738 | * @req: dwc3_request pointer | |
739 | */ | |
68e823e2 | 740 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 741 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 742 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 743 | { |
f6bafc6a | 744 | struct dwc3_trb *trb; |
c71fc37c | 745 | |
73815280 | 746 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s", |
eeb720fb FB |
747 | dep->name, req, (unsigned long long) dma, |
748 | length, last ? " last" : "", | |
749 | chain ? " chain" : ""); | |
750 | ||
915e202a PA |
751 | |
752 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 753 | |
eeb720fb FB |
754 | if (!req->trb) { |
755 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
756 | req->trb = trb; |
757 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 758 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 759 | } |
c71fc37c | 760 | |
e5ba5ec8 | 761 | dep->free_slot++; |
5cd8c48d ZJC |
762 | /* Skip the LINK-TRB on ISOC */ |
763 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
764 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
765 | dep->free_slot++; | |
e5ba5ec8 | 766 | |
f6bafc6a FB |
767 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
768 | trb->bpl = lower_32_bits(dma); | |
769 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 770 | |
16e78db7 | 771 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 772 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 773 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
774 | break; |
775 | ||
776 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
777 | if (!node) |
778 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
779 | else | |
780 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c FB |
781 | break; |
782 | ||
783 | case USB_ENDPOINT_XFER_BULK: | |
784 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 785 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
786 | break; |
787 | default: | |
788 | /* | |
789 | * This is only possible with faulty memory because we | |
790 | * checked it already :) | |
791 | */ | |
792 | BUG(); | |
793 | } | |
794 | ||
f3af3651 FB |
795 | if (!req->request.no_interrupt && !chain) |
796 | trb->ctrl |= DWC3_TRB_CTRL_IOC; | |
797 | ||
16e78db7 | 798 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
799 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
800 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
801 | } else if (last) { |
802 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 803 | } |
c71fc37c | 804 | |
e5ba5ec8 PA |
805 | if (chain) |
806 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
807 | ||
16e78db7 | 808 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 809 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 810 | |
f6bafc6a | 811 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
812 | |
813 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
814 | } |
815 | ||
72246da4 FB |
816 | /* |
817 | * dwc3_prepare_trbs - setup TRBs from requests | |
818 | * @dep: endpoint for which requests are being prepared | |
819 | * @starting: true if the endpoint is idle and no requests are queued. | |
820 | * | |
1d046793 PZ |
821 | * The function goes through the requests list and sets up TRBs for the |
822 | * transfers. The function returns once there are no more TRBs available or | |
823 | * it runs out of requests. | |
72246da4 | 824 | */ |
68e823e2 | 825 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 826 | { |
68e823e2 | 827 | struct dwc3_request *req, *n; |
72246da4 | 828 | u32 trbs_left; |
8d62cd65 | 829 | u32 max; |
c71fc37c | 830 | unsigned int last_one = 0; |
72246da4 FB |
831 | |
832 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
833 | ||
834 | /* the first request must not be queued */ | |
835 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 836 | |
8d62cd65 | 837 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 838 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
839 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
840 | if (trbs_left > max) | |
841 | trbs_left = max; | |
842 | } | |
843 | ||
72246da4 | 844 | /* |
1d046793 PZ |
845 | * If busy & slot are equal than it is either full or empty. If we are |
846 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
847 | * full and don't do anything |
848 | */ | |
849 | if (!trbs_left) { | |
850 | if (!starting) | |
68e823e2 | 851 | return; |
72246da4 FB |
852 | trbs_left = DWC3_TRB_NUM; |
853 | /* | |
854 | * In case we start from scratch, we queue the ISOC requests | |
855 | * starting from slot 1. This is done because we use ring | |
856 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 857 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
858 | * after the first request so we start at slot 1 and have |
859 | * 7 requests proceed before we hit the first IOC. | |
860 | * Other transfer types don't use the ring buffer and are | |
861 | * processed from the first TRB until the last one. Since we | |
862 | * don't wrap around we have to start at the beginning. | |
863 | */ | |
16e78db7 | 864 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
865 | dep->busy_slot = 1; |
866 | dep->free_slot = 1; | |
867 | } else { | |
868 | dep->busy_slot = 0; | |
869 | dep->free_slot = 0; | |
870 | } | |
871 | } | |
872 | ||
873 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 874 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 875 | return; |
72246da4 FB |
876 | |
877 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
878 | unsigned length; |
879 | dma_addr_t dma; | |
e5ba5ec8 | 880 | last_one = false; |
72246da4 | 881 | |
eeb720fb FB |
882 | if (req->request.num_mapped_sgs > 0) { |
883 | struct usb_request *request = &req->request; | |
884 | struct scatterlist *sg = request->sg; | |
885 | struct scatterlist *s; | |
886 | int i; | |
72246da4 | 887 | |
eeb720fb FB |
888 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
889 | unsigned chain = true; | |
72246da4 | 890 | |
eeb720fb FB |
891 | length = sg_dma_len(s); |
892 | dma = sg_dma_address(s); | |
72246da4 | 893 | |
1d046793 PZ |
894 | if (i == (request->num_mapped_sgs - 1) || |
895 | sg_is_last(s)) { | |
ec512fb8 | 896 | if (list_empty(&dep->request_list)) |
e5ba5ec8 | 897 | last_one = true; |
eeb720fb FB |
898 | chain = false; |
899 | } | |
72246da4 | 900 | |
eeb720fb FB |
901 | trbs_left--; |
902 | if (!trbs_left) | |
903 | last_one = true; | |
72246da4 | 904 | |
eeb720fb FB |
905 | if (last_one) |
906 | chain = false; | |
72246da4 | 907 | |
eeb720fb | 908 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 909 | last_one, chain, i); |
72246da4 | 910 | |
eeb720fb FB |
911 | if (last_one) |
912 | break; | |
913 | } | |
39e60635 AV |
914 | |
915 | if (last_one) | |
916 | break; | |
72246da4 | 917 | } else { |
eeb720fb FB |
918 | dma = req->request.dma; |
919 | length = req->request.length; | |
920 | trbs_left--; | |
72246da4 | 921 | |
eeb720fb FB |
922 | if (!trbs_left) |
923 | last_one = 1; | |
879631aa | 924 | |
eeb720fb FB |
925 | /* Is this the last request? */ |
926 | if (list_is_last(&req->list, &dep->request_list)) | |
927 | last_one = 1; | |
72246da4 | 928 | |
eeb720fb | 929 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 930 | last_one, false, 0); |
72246da4 | 931 | |
eeb720fb FB |
932 | if (last_one) |
933 | break; | |
72246da4 | 934 | } |
72246da4 | 935 | } |
72246da4 FB |
936 | } |
937 | ||
938 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
939 | int start_new) | |
940 | { | |
941 | struct dwc3_gadget_ep_cmd_params params; | |
942 | struct dwc3_request *req; | |
943 | struct dwc3 *dwc = dep->dwc; | |
944 | int ret; | |
945 | u32 cmd; | |
946 | ||
947 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
73815280 | 948 | dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name); |
72246da4 FB |
949 | return -EBUSY; |
950 | } | |
951 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
952 | ||
953 | /* | |
954 | * If we are getting here after a short-out-packet we don't enqueue any | |
955 | * new requests as we try to set the IOC bit only on the last request. | |
956 | */ | |
957 | if (start_new) { | |
958 | if (list_empty(&dep->req_queued)) | |
959 | dwc3_prepare_trbs(dep, start_new); | |
960 | ||
961 | /* req points to the first request which will be sent */ | |
962 | req = next_request(&dep->req_queued); | |
963 | } else { | |
68e823e2 FB |
964 | dwc3_prepare_trbs(dep, start_new); |
965 | ||
72246da4 | 966 | /* |
1d046793 | 967 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 968 | */ |
68e823e2 | 969 | req = next_request(&dep->req_queued); |
72246da4 FB |
970 | } |
971 | if (!req) { | |
972 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
973 | return 0; | |
974 | } | |
975 | ||
976 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 977 | |
1877d6c9 PA |
978 | if (start_new) { |
979 | params.param0 = upper_32_bits(req->trb_dma); | |
980 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 981 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 982 | } else { |
72246da4 | 983 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 984 | } |
72246da4 FB |
985 | |
986 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
987 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
988 | if (ret < 0) { | |
989 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
990 | ||
991 | /* | |
992 | * FIXME we need to iterate over the list of requests | |
993 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 994 | * requests instead of what we do now. |
72246da4 | 995 | */ |
0fc9a1be FB |
996 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
997 | req->direction); | |
72246da4 FB |
998 | list_del(&req->list); |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1003 | |
f898ae09 | 1004 | if (start_new) { |
b4996a86 | 1005 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1006 | dep->number); |
b4996a86 | 1007 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1008 | } |
25b8ff68 | 1009 | |
72246da4 FB |
1010 | return 0; |
1011 | } | |
1012 | ||
d6d6ec7b PA |
1013 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1014 | struct dwc3_ep *dep, u32 cur_uf) | |
1015 | { | |
1016 | u32 uf; | |
1017 | ||
1018 | if (list_empty(&dep->request_list)) { | |
73815280 FB |
1019 | dwc3_trace(trace_dwc3_gadget, |
1020 | "ISOC ep %s run out for requests", | |
1021 | dep->name); | |
f4a53c55 | 1022 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1023 | return; |
1024 | } | |
1025 | ||
1026 | /* 4 micro frames in the future */ | |
1027 | uf = cur_uf + dep->interval * 4; | |
1028 | ||
1029 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1030 | } | |
1031 | ||
1032 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1033 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1034 | { | |
1035 | u32 cur_uf, mask; | |
1036 | ||
1037 | mask = ~(dep->interval - 1); | |
1038 | cur_uf = event->parameters & mask; | |
1039 | ||
1040 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1041 | } | |
1042 | ||
72246da4 FB |
1043 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1044 | { | |
0fc9a1be FB |
1045 | struct dwc3 *dwc = dep->dwc; |
1046 | int ret; | |
1047 | ||
72246da4 FB |
1048 | req->request.actual = 0; |
1049 | req->request.status = -EINPROGRESS; | |
1050 | req->direction = dep->direction; | |
1051 | req->epnum = dep->number; | |
1052 | ||
fe84f522 FB |
1053 | trace_dwc3_ep_queue(req); |
1054 | ||
72246da4 FB |
1055 | /* |
1056 | * We only add to our list of requests now and | |
1057 | * start consuming the list once we get XferNotReady | |
1058 | * IRQ. | |
1059 | * | |
1060 | * That way, we avoid doing anything that we don't need | |
1061 | * to do now and defer it until the point we receive a | |
1062 | * particular token from the Host side. | |
1063 | * | |
1064 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1065 | * many NAKs. |
72246da4 | 1066 | */ |
0fc9a1be FB |
1067 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1068 | dep->direction); | |
1069 | if (ret) | |
1070 | return ret; | |
1071 | ||
72246da4 FB |
1072 | list_add_tail(&req->list, &dep->request_list); |
1073 | ||
1d6a3918 FB |
1074 | /* |
1075 | * If there are no pending requests and the endpoint isn't already | |
1076 | * busy, we will just start the request straight away. | |
1077 | * | |
1078 | * This will save one IRQ (XFER_NOT_READY) and possibly make it a | |
1079 | * little bit faster. | |
1080 | */ | |
1081 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
1082 | !(dep->flags & DWC3_EP_BUSY)) { | |
1083 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); | |
1084 | if (ret && ret != -EBUSY) | |
1085 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1086 | dep->name); | |
1087 | return ret; | |
1088 | } | |
1089 | ||
72246da4 | 1090 | /* |
b511e5e7 | 1091 | * There are a few special cases: |
72246da4 | 1092 | * |
f898ae09 PZ |
1093 | * 1. XferNotReady with empty list of requests. We need to kick the |
1094 | * transfer here in that situation, otherwise we will be NAKing | |
1095 | * forever. If we get XferNotReady before gadget driver has a | |
1096 | * chance to queue a request, we will ACK the IRQ but won't be | |
1097 | * able to receive the data until the next request is queued. | |
1098 | * The following code is handling exactly that. | |
72246da4 | 1099 | * |
72246da4 FB |
1100 | */ |
1101 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1102 | /* |
1103 | * If xfernotready is already elapsed and it is a case | |
1104 | * of isoc transfer, then issue END TRANSFER, so that | |
1105 | * you can receive xfernotready again and can have | |
1106 | * notion of current microframe. | |
1107 | */ | |
1108 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd | 1109 | if (list_empty(&dep->req_queued)) { |
b992e681 | 1110 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1111 | dep->flags = DWC3_EP_ENABLED; |
1112 | } | |
f4a53c55 PA |
1113 | return 0; |
1114 | } | |
1115 | ||
b511e5e7 | 1116 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
348e026f | 1117 | if (ret && ret != -EBUSY) |
b511e5e7 FB |
1118 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1119 | dep->name); | |
15f86bde | 1120 | return ret; |
b511e5e7 | 1121 | } |
72246da4 | 1122 | |
b511e5e7 FB |
1123 | /* |
1124 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1125 | * kick the transfer here after queuing a request, otherwise the | |
1126 | * core may not see the modified TRB(s). | |
1127 | */ | |
1128 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1129 | (dep->flags & DWC3_EP_BUSY) && |
1130 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1131 | WARN_ON_ONCE(!dep->resource_index); |
1132 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1133 | false); |
348e026f | 1134 | if (ret && ret != -EBUSY) |
72246da4 FB |
1135 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1136 | dep->name); | |
15f86bde | 1137 | return ret; |
a0925324 | 1138 | } |
72246da4 | 1139 | |
b997ada5 FB |
1140 | /* |
1141 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1142 | * right away, otherwise host will not know we have streams to be | |
1143 | * handled. | |
1144 | */ | |
1145 | if (dep->stream_capable) { | |
b997ada5 | 1146 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
4cd8f6d0 | 1147 | if (ret && ret != -EBUSY) |
b997ada5 FB |
1148 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1149 | dep->name); | |
b997ada5 FB |
1150 | } |
1151 | ||
72246da4 FB |
1152 | return 0; |
1153 | } | |
1154 | ||
1155 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1156 | gfp_t gfp_flags) | |
1157 | { | |
1158 | struct dwc3_request *req = to_dwc3_request(request); | |
1159 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1160 | struct dwc3 *dwc = dep->dwc; | |
1161 | ||
1162 | unsigned long flags; | |
1163 | ||
1164 | int ret; | |
1165 | ||
fdee4eba | 1166 | spin_lock_irqsave(&dwc->lock, flags); |
16e78db7 | 1167 | if (!dep->endpoint.desc) { |
72246da4 FB |
1168 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1169 | request, ep->name); | |
73359cef FB |
1170 | ret = -ESHUTDOWN; |
1171 | goto out; | |
1172 | } | |
1173 | ||
1174 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1175 | request, req->dep->name)) { | |
1176 | ret = -EINVAL; | |
1177 | goto out; | |
72246da4 FB |
1178 | } |
1179 | ||
72246da4 | 1180 | ret = __dwc3_gadget_ep_queue(dep, req); |
73359cef FB |
1181 | |
1182 | out: | |
72246da4 FB |
1183 | spin_unlock_irqrestore(&dwc->lock, flags); |
1184 | ||
1185 | return ret; | |
1186 | } | |
1187 | ||
1188 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1189 | struct usb_request *request) | |
1190 | { | |
1191 | struct dwc3_request *req = to_dwc3_request(request); | |
1192 | struct dwc3_request *r = NULL; | |
1193 | ||
1194 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1195 | struct dwc3 *dwc = dep->dwc; | |
1196 | ||
1197 | unsigned long flags; | |
1198 | int ret = 0; | |
1199 | ||
2c4cbe6e FB |
1200 | trace_dwc3_ep_dequeue(req); |
1201 | ||
72246da4 FB |
1202 | spin_lock_irqsave(&dwc->lock, flags); |
1203 | ||
1204 | list_for_each_entry(r, &dep->request_list, list) { | |
1205 | if (r == req) | |
1206 | break; | |
1207 | } | |
1208 | ||
1209 | if (r != req) { | |
1210 | list_for_each_entry(r, &dep->req_queued, list) { | |
1211 | if (r == req) | |
1212 | break; | |
1213 | } | |
1214 | if (r == req) { | |
1215 | /* wait until it is processed */ | |
b992e681 | 1216 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1217 | goto out1; |
72246da4 FB |
1218 | } |
1219 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1220 | request, ep->name); | |
1221 | ret = -EINVAL; | |
1222 | goto out0; | |
1223 | } | |
1224 | ||
e8d4e8be | 1225 | out1: |
72246da4 FB |
1226 | /* giveback the request */ |
1227 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1228 | ||
1229 | out0: | |
1230 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1231 | ||
1232 | return ret; | |
1233 | } | |
1234 | ||
7a608559 | 1235 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1236 | { |
1237 | struct dwc3_gadget_ep_cmd_params params; | |
1238 | struct dwc3 *dwc = dep->dwc; | |
1239 | int ret; | |
1240 | ||
5ad02fb8 FB |
1241 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1242 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1243 | return -EINVAL; | |
1244 | } | |
1245 | ||
72246da4 FB |
1246 | memset(¶ms, 0x00, sizeof(params)); |
1247 | ||
1248 | if (value) { | |
7a608559 FB |
1249 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
1250 | (!list_empty(&dep->req_queued) || | |
1251 | !list_empty(&dep->request_list)))) { | |
1252 | dev_dbg(dwc->dev, "%s: pending request, cannot halt\n", | |
1253 | dep->name); | |
1254 | return -EAGAIN; | |
1255 | } | |
1256 | ||
72246da4 FB |
1257 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1258 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1259 | if (ret) | |
3f89204b | 1260 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1261 | dep->name); |
1262 | else | |
1263 | dep->flags |= DWC3_EP_STALL; | |
1264 | } else { | |
1265 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1266 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1267 | if (ret) | |
3f89204b | 1268 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1269 | dep->name); |
1270 | else | |
a535d81c | 1271 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1272 | } |
5275455a | 1273 | |
72246da4 FB |
1274 | return ret; |
1275 | } | |
1276 | ||
1277 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1278 | { | |
1279 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1280 | struct dwc3 *dwc = dep->dwc; | |
1281 | ||
1282 | unsigned long flags; | |
1283 | ||
1284 | int ret; | |
1285 | ||
1286 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1287 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1288 | spin_unlock_irqrestore(&dwc->lock, flags); |
1289 | ||
1290 | return ret; | |
1291 | } | |
1292 | ||
1293 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1294 | { | |
1295 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1296 | struct dwc3 *dwc = dep->dwc; |
1297 | unsigned long flags; | |
95aa4e8d | 1298 | int ret; |
72246da4 | 1299 | |
249a4569 | 1300 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1301 | dep->flags |= DWC3_EP_WEDGE; |
1302 | ||
08f0d966 | 1303 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1304 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1305 | else |
7a608559 | 1306 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1307 | spin_unlock_irqrestore(&dwc->lock, flags); |
1308 | ||
1309 | return ret; | |
72246da4 FB |
1310 | } |
1311 | ||
1312 | /* -------------------------------------------------------------------------- */ | |
1313 | ||
1314 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1315 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1316 | .bDescriptorType = USB_DT_ENDPOINT, | |
1317 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1318 | }; | |
1319 | ||
1320 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1321 | .enable = dwc3_gadget_ep0_enable, | |
1322 | .disable = dwc3_gadget_ep0_disable, | |
1323 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1324 | .free_request = dwc3_gadget_ep_free_request, | |
1325 | .queue = dwc3_gadget_ep0_queue, | |
1326 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1327 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1328 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1329 | }; | |
1330 | ||
1331 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1332 | .enable = dwc3_gadget_ep_enable, | |
1333 | .disable = dwc3_gadget_ep_disable, | |
1334 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1335 | .free_request = dwc3_gadget_ep_free_request, | |
1336 | .queue = dwc3_gadget_ep_queue, | |
1337 | .dequeue = dwc3_gadget_ep_dequeue, | |
1338 | .set_halt = dwc3_gadget_ep_set_halt, | |
1339 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1340 | }; | |
1341 | ||
1342 | /* -------------------------------------------------------------------------- */ | |
1343 | ||
1344 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1345 | { | |
1346 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1347 | u32 reg; | |
1348 | ||
1349 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1350 | return DWC3_DSTS_SOFFN(reg); | |
1351 | } | |
1352 | ||
1353 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1354 | { | |
1355 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1356 | ||
1357 | unsigned long timeout; | |
1358 | unsigned long flags; | |
1359 | ||
1360 | u32 reg; | |
1361 | ||
1362 | int ret = 0; | |
1363 | ||
1364 | u8 link_state; | |
1365 | u8 speed; | |
1366 | ||
1367 | spin_lock_irqsave(&dwc->lock, flags); | |
1368 | ||
1369 | /* | |
1370 | * According to the Databook Remote wakeup request should | |
1371 | * be issued only when the device is in early suspend state. | |
1372 | * | |
1373 | * We can check that via USB Link State bits in DSTS register. | |
1374 | */ | |
1375 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1376 | ||
1377 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1378 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1379 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1380 | ret = -EINVAL; | |
1381 | goto out; | |
1382 | } | |
1383 | ||
1384 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1385 | ||
1386 | switch (link_state) { | |
1387 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1388 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1389 | break; | |
1390 | default: | |
1391 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1392 | link_state); | |
1393 | ret = -EINVAL; | |
1394 | goto out; | |
1395 | } | |
1396 | ||
8598bde7 FB |
1397 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1398 | if (ret < 0) { | |
1399 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1400 | goto out; | |
1401 | } | |
72246da4 | 1402 | |
802fde98 PZ |
1403 | /* Recent versions do this automatically */ |
1404 | if (dwc->revision < DWC3_REVISION_194A) { | |
1405 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1406 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1407 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1408 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1409 | } | |
72246da4 | 1410 | |
1d046793 | 1411 | /* poll until Link State changes to ON */ |
72246da4 FB |
1412 | timeout = jiffies + msecs_to_jiffies(100); |
1413 | ||
1d046793 | 1414 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1415 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1416 | ||
1417 | /* in HS, means ON */ | |
1418 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1419 | break; | |
1420 | } | |
1421 | ||
1422 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1423 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1424 | ret = -EINVAL; | |
1425 | } | |
1426 | ||
1427 | out: | |
1428 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1429 | ||
1430 | return ret; | |
1431 | } | |
1432 | ||
1433 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1434 | int is_selfpowered) | |
1435 | { | |
1436 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1437 | unsigned long flags; |
72246da4 | 1438 | |
249a4569 | 1439 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1440 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1441 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
7b2a0368 | 1446 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1447 | { |
1448 | u32 reg; | |
61d58242 | 1449 | u32 timeout = 500; |
72246da4 FB |
1450 | |
1451 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1452 | if (is_on) { |
802fde98 PZ |
1453 | if (dwc->revision <= DWC3_REVISION_187A) { |
1454 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1455 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1456 | } | |
1457 | ||
1458 | if (dwc->revision >= DWC3_REVISION_194A) | |
1459 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1460 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1461 | |
1462 | if (dwc->has_hibernation) | |
1463 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1464 | ||
9fcb3bd8 | 1465 | dwc->pullups_connected = true; |
8db7ed15 | 1466 | } else { |
72246da4 | 1467 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1468 | |
1469 | if (dwc->has_hibernation && !suspend) | |
1470 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1471 | ||
9fcb3bd8 | 1472 | dwc->pullups_connected = false; |
8db7ed15 | 1473 | } |
72246da4 FB |
1474 | |
1475 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1476 | ||
1477 | do { | |
1478 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1479 | if (is_on) { | |
1480 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1481 | break; | |
1482 | } else { | |
1483 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1484 | break; | |
1485 | } | |
72246da4 FB |
1486 | timeout--; |
1487 | if (!timeout) | |
6f17f74b | 1488 | return -ETIMEDOUT; |
61d58242 | 1489 | udelay(1); |
72246da4 FB |
1490 | } while (1); |
1491 | ||
73815280 | 1492 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", |
72246da4 FB |
1493 | dwc->gadget_driver |
1494 | ? dwc->gadget_driver->function : "no-function", | |
1495 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1496 | |
1497 | return 0; | |
72246da4 FB |
1498 | } |
1499 | ||
1500 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1501 | { | |
1502 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1503 | unsigned long flags; | |
6f17f74b | 1504 | int ret; |
72246da4 FB |
1505 | |
1506 | is_on = !!is_on; | |
1507 | ||
1508 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1509 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1510 | spin_unlock_irqrestore(&dwc->lock, flags); |
1511 | ||
6f17f74b | 1512 | return ret; |
72246da4 FB |
1513 | } |
1514 | ||
8698e2ac FB |
1515 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1516 | { | |
1517 | u32 reg; | |
1518 | ||
1519 | /* Enable all but Start and End of Frame IRQs */ | |
1520 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1521 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1522 | DWC3_DEVTEN_CMDCMPLTEN | | |
1523 | DWC3_DEVTEN_ERRTICERREN | | |
1524 | DWC3_DEVTEN_WKUPEVTEN | | |
1525 | DWC3_DEVTEN_ULSTCNGEN | | |
1526 | DWC3_DEVTEN_CONNECTDONEEN | | |
1527 | DWC3_DEVTEN_USBRSTEN | | |
1528 | DWC3_DEVTEN_DISCONNEVTEN); | |
1529 | ||
1530 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1531 | } | |
1532 | ||
1533 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1534 | { | |
1535 | /* mask all interrupts */ | |
1536 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1537 | } | |
1538 | ||
1539 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1540 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1541 | |
72246da4 FB |
1542 | static int dwc3_gadget_start(struct usb_gadget *g, |
1543 | struct usb_gadget_driver *driver) | |
1544 | { | |
1545 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1546 | struct dwc3_ep *dep; | |
1547 | unsigned long flags; | |
1548 | int ret = 0; | |
8698e2ac | 1549 | int irq; |
72246da4 FB |
1550 | u32 reg; |
1551 | ||
b0d7ffd4 FB |
1552 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1553 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1554 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1555 | if (ret) { |
1556 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1557 | irq, ret); | |
1558 | goto err0; | |
1559 | } | |
1560 | ||
72246da4 FB |
1561 | spin_lock_irqsave(&dwc->lock, flags); |
1562 | ||
1563 | if (dwc->gadget_driver) { | |
1564 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1565 | dwc->gadget.name, | |
1566 | dwc->gadget_driver->driver.name); | |
1567 | ret = -EBUSY; | |
b0d7ffd4 | 1568 | goto err1; |
72246da4 FB |
1569 | } |
1570 | ||
1571 | dwc->gadget_driver = driver; | |
72246da4 | 1572 | |
72246da4 FB |
1573 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1574 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1575 | |
1576 | /** | |
1577 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1578 | * which would cause metastability state on Run/Stop | |
1579 | * bit if we try to force the IP to USB2-only mode. | |
1580 | * | |
1581 | * Because of that, we cannot configure the IP to any | |
1582 | * speed other than the SuperSpeed | |
1583 | * | |
1584 | * Refers to: | |
1585 | * | |
1586 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1587 | * USB 2.0 Mode | |
1588 | */ | |
f7e846f0 | 1589 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1590 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1591 | } else { |
1592 | switch (dwc->maximum_speed) { | |
1593 | case USB_SPEED_LOW: | |
1594 | reg |= DWC3_DSTS_LOWSPEED; | |
1595 | break; | |
1596 | case USB_SPEED_FULL: | |
1597 | reg |= DWC3_DSTS_FULLSPEED1; | |
1598 | break; | |
1599 | case USB_SPEED_HIGH: | |
1600 | reg |= DWC3_DSTS_HIGHSPEED; | |
1601 | break; | |
1602 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1603 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1604 | default: | |
1605 | reg |= DWC3_DSTS_SUPERSPEED; | |
1606 | } | |
1607 | } | |
72246da4 FB |
1608 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1609 | ||
b23c8439 PZ |
1610 | dwc->start_config_issued = false; |
1611 | ||
72246da4 FB |
1612 | /* Start with SuperSpeed Default */ |
1613 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1614 | ||
1615 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1616 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1617 | false); | |
72246da4 FB |
1618 | if (ret) { |
1619 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1620 | goto err2; |
72246da4 FB |
1621 | } |
1622 | ||
1623 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1624 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1625 | false); | |
72246da4 FB |
1626 | if (ret) { |
1627 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1628 | goto err3; |
72246da4 FB |
1629 | } |
1630 | ||
1631 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1632 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1633 | dwc3_ep0_out_start(dwc); |
1634 | ||
8698e2ac FB |
1635 | dwc3_gadget_enable_irq(dwc); |
1636 | ||
72246da4 FB |
1637 | spin_unlock_irqrestore(&dwc->lock, flags); |
1638 | ||
1639 | return 0; | |
1640 | ||
b0d7ffd4 | 1641 | err3: |
72246da4 FB |
1642 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1643 | ||
b0d7ffd4 | 1644 | err2: |
cdcedd69 | 1645 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1646 | |
1647 | err1: | |
72246da4 FB |
1648 | spin_unlock_irqrestore(&dwc->lock, flags); |
1649 | ||
b0d7ffd4 FB |
1650 | free_irq(irq, dwc); |
1651 | ||
1652 | err0: | |
72246da4 FB |
1653 | return ret; |
1654 | } | |
1655 | ||
22835b80 | 1656 | static int dwc3_gadget_stop(struct usb_gadget *g) |
72246da4 FB |
1657 | { |
1658 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1659 | unsigned long flags; | |
8698e2ac | 1660 | int irq; |
72246da4 FB |
1661 | |
1662 | spin_lock_irqsave(&dwc->lock, flags); | |
1663 | ||
8698e2ac | 1664 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1665 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1666 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1667 | ||
1668 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1669 | |
1670 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1671 | ||
b0d7ffd4 FB |
1672 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1673 | free_irq(irq, dwc); | |
1674 | ||
72246da4 FB |
1675 | return 0; |
1676 | } | |
802fde98 | 1677 | |
72246da4 FB |
1678 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1679 | .get_frame = dwc3_gadget_get_frame, | |
1680 | .wakeup = dwc3_gadget_wakeup, | |
1681 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1682 | .pullup = dwc3_gadget_pullup, | |
1683 | .udc_start = dwc3_gadget_start, | |
1684 | .udc_stop = dwc3_gadget_stop, | |
1685 | }; | |
1686 | ||
1687 | /* -------------------------------------------------------------------------- */ | |
1688 | ||
6a1e3ef4 FB |
1689 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1690 | u8 num, u32 direction) | |
72246da4 FB |
1691 | { |
1692 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1693 | u8 i; |
72246da4 | 1694 | |
6a1e3ef4 FB |
1695 | for (i = 0; i < num; i++) { |
1696 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1697 | |
72246da4 | 1698 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1699 | if (!dep) |
72246da4 | 1700 | return -ENOMEM; |
72246da4 FB |
1701 | |
1702 | dep->dwc = dwc; | |
1703 | dep->number = epnum; | |
9aa62ae4 | 1704 | dep->direction = !!direction; |
72246da4 FB |
1705 | dwc->eps[epnum] = dep; |
1706 | ||
1707 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1708 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1709 | |
72246da4 | 1710 | dep->endpoint.name = dep->name; |
72246da4 | 1711 | |
73815280 | 1712 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); |
653df35e | 1713 | |
72246da4 | 1714 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1715 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1716 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1717 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1718 | if (!epnum) | |
1719 | dwc->gadget.ep0 = &dep->endpoint; | |
1720 | } else { | |
1721 | int ret; | |
1722 | ||
e117e742 | 1723 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1724 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1725 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1726 | list_add_tail(&dep->endpoint.ep_list, | |
1727 | &dwc->gadget.ep_list); | |
1728 | ||
1729 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1730 | if (ret) |
72246da4 | 1731 | return ret; |
72246da4 | 1732 | } |
25b8ff68 | 1733 | |
a474d3b7 RB |
1734 | if (epnum == 0 || epnum == 1) { |
1735 | dep->endpoint.caps.type_control = true; | |
1736 | } else { | |
1737 | dep->endpoint.caps.type_iso = true; | |
1738 | dep->endpoint.caps.type_bulk = true; | |
1739 | dep->endpoint.caps.type_int = true; | |
1740 | } | |
1741 | ||
1742 | dep->endpoint.caps.dir_in = !!direction; | |
1743 | dep->endpoint.caps.dir_out = !direction; | |
1744 | ||
72246da4 FB |
1745 | INIT_LIST_HEAD(&dep->request_list); |
1746 | INIT_LIST_HEAD(&dep->req_queued); | |
1747 | } | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
6a1e3ef4 FB |
1752 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1753 | { | |
1754 | int ret; | |
1755 | ||
1756 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1757 | ||
1758 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1759 | if (ret < 0) { | |
73815280 FB |
1760 | dwc3_trace(trace_dwc3_gadget, |
1761 | "failed to allocate OUT endpoints"); | |
6a1e3ef4 FB |
1762 | return ret; |
1763 | } | |
1764 | ||
1765 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1766 | if (ret < 0) { | |
73815280 FB |
1767 | dwc3_trace(trace_dwc3_gadget, |
1768 | "failed to allocate IN endpoints"); | |
6a1e3ef4 FB |
1769 | return ret; |
1770 | } | |
1771 | ||
1772 | return 0; | |
1773 | } | |
1774 | ||
72246da4 FB |
1775 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1776 | { | |
1777 | struct dwc3_ep *dep; | |
1778 | u8 epnum; | |
1779 | ||
1780 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1781 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1782 | if (!dep) |
1783 | continue; | |
5bf8fae3 GC |
1784 | /* |
1785 | * Physical endpoints 0 and 1 are special; they form the | |
1786 | * bi-directional USB endpoint 0. | |
1787 | * | |
1788 | * For those two physical endpoints, we don't allocate a TRB | |
1789 | * pool nor do we add them the endpoints list. Due to that, we | |
1790 | * shouldn't do these two operations otherwise we would end up | |
1791 | * with all sorts of bugs when removing dwc3.ko. | |
1792 | */ | |
1793 | if (epnum != 0 && epnum != 1) { | |
1794 | dwc3_free_trb_pool(dep); | |
72246da4 | 1795 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1796 | } |
72246da4 FB |
1797 | |
1798 | kfree(dep); | |
1799 | } | |
1800 | } | |
1801 | ||
72246da4 | 1802 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1803 | |
e5ba5ec8 PA |
1804 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1805 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1806 | const struct dwc3_event_depevt *event, int status) |
1807 | { | |
72246da4 FB |
1808 | unsigned int count; |
1809 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1810 | unsigned int trb_status; |
72246da4 | 1811 | |
2c4cbe6e FB |
1812 | trace_dwc3_complete_trb(dep, trb); |
1813 | ||
e5ba5ec8 PA |
1814 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1815 | /* | |
1816 | * We continue despite the error. There is not much we | |
1817 | * can do. If we don't clean it up we loop forever. If | |
1818 | * we skip the TRB then it gets overwritten after a | |
1819 | * while since we use them in a ring buffer. A BUG() | |
1820 | * would help. Lets hope that if this occurs, someone | |
1821 | * fixes the root cause instead of looking away :) | |
1822 | */ | |
1823 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1824 | dep->name, trb); | |
1825 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1826 | ||
1827 | if (dep->direction) { | |
1828 | if (count) { | |
1829 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1830 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1831 | dev_dbg(dwc->dev, "incomplete IN transfer %s\n", | |
1832 | dep->name); | |
1833 | /* | |
1834 | * If missed isoc occurred and there is | |
1835 | * no request queued then issue END | |
1836 | * TRANSFER, so that core generates | |
1837 | * next xfernotready and we will issue | |
1838 | * a fresh START TRANSFER. | |
1839 | * If there are still queued request | |
1840 | * then wait, do not issue either END | |
1841 | * or UPDATE TRANSFER, just attach next | |
1842 | * request in request_list during | |
1843 | * giveback.If any future queued request | |
1844 | * is successfully transferred then we | |
1845 | * will issue UPDATE TRANSFER for all | |
1846 | * request in the request_list. | |
1847 | */ | |
1848 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1849 | } else { | |
1850 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1851 | dep->name); | |
1852 | status = -ECONNRESET; | |
1853 | } | |
1854 | } else { | |
1855 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1856 | } | |
1857 | } else { | |
1858 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1859 | s_pkt = 1; | |
1860 | } | |
1861 | ||
1862 | /* | |
1863 | * We assume here we will always receive the entire data block | |
1864 | * which we should receive. Meaning, if we program RX to | |
1865 | * receive 4K but we receive only 2K, we assume that's all we | |
1866 | * should receive and we simply bounce the request back to the | |
1867 | * gadget driver for further processing. | |
1868 | */ | |
1869 | req->request.actual += req->request.length - count; | |
1870 | if (s_pkt) | |
1871 | return 1; | |
1872 | if ((event->status & DEPEVT_STATUS_LST) && | |
1873 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1874 | DWC3_TRB_CTRL_HWO))) | |
1875 | return 1; | |
1876 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1877 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1878 | return 1; | |
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1883 | const struct dwc3_event_depevt *event, int status) | |
1884 | { | |
1885 | struct dwc3_request *req; | |
1886 | struct dwc3_trb *trb; | |
1887 | unsigned int slot; | |
1888 | unsigned int i; | |
1889 | int ret; | |
1890 | ||
8f2c9544 FB |
1891 | req = next_request(&dep->req_queued); |
1892 | if (!req) { | |
1893 | WARN_ON_ONCE(1); | |
1894 | return 1; | |
1895 | } | |
1896 | i = 0; | |
72246da4 | 1897 | do { |
8f2c9544 FB |
1898 | slot = req->start_slot + i; |
1899 | if ((slot == DWC3_TRB_NUM - 1) && | |
e5ba5ec8 | 1900 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
8f2c9544 FB |
1901 | slot++; |
1902 | slot %= DWC3_TRB_NUM; | |
1903 | trb = &dep->trb_pool[slot]; | |
e5ba5ec8 | 1904 | |
8f2c9544 FB |
1905 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
1906 | event, status); | |
e5ba5ec8 | 1907 | if (ret) |
72246da4 | 1908 | break; |
8f2c9544 FB |
1909 | } while (++i < req->request.num_mapped_sgs); |
1910 | ||
1911 | dwc3_gadget_giveback(dep, req, status); | |
72246da4 | 1912 | |
cdc359dd PA |
1913 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1914 | list_empty(&dep->req_queued)) { | |
1915 | if (list_empty(&dep->request_list)) { | |
1916 | /* | |
1917 | * If there is no entry in request list then do | |
1918 | * not issue END TRANSFER now. Just set PENDING | |
1919 | * flag, so that END TRANSFER is issued when an | |
1920 | * entry is added into request list. | |
1921 | */ | |
1922 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1923 | } else { | |
b992e681 | 1924 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1925 | dep->flags = DWC3_EP_ENABLED; |
1926 | } | |
7efea86c PA |
1927 | return 1; |
1928 | } | |
1929 | ||
72246da4 FB |
1930 | return 1; |
1931 | } | |
1932 | ||
1933 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 1934 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
1935 | { |
1936 | unsigned status = 0; | |
1937 | int clean_busy; | |
e18b7975 FB |
1938 | u32 is_xfer_complete; |
1939 | ||
1940 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
1941 | |
1942 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1943 | status = -ECONNRESET; | |
1944 | ||
1d046793 | 1945 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
e18b7975 FB |
1946 | if (clean_busy && (is_xfer_complete || |
1947 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) | |
72246da4 | 1948 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1949 | |
1950 | /* | |
1951 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1952 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1953 | */ | |
1954 | if (dwc->revision < DWC3_REVISION_183A) { | |
1955 | u32 reg; | |
1956 | int i; | |
1957 | ||
1958 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 1959 | dep = dwc->eps[i]; |
fae2b904 FB |
1960 | |
1961 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1962 | continue; | |
1963 | ||
1964 | if (!list_empty(&dep->req_queued)) | |
1965 | return; | |
1966 | } | |
1967 | ||
1968 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1969 | reg |= dwc->u1u2; | |
1970 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1971 | ||
1972 | dwc->u1u2 = 0; | |
1973 | } | |
72246da4 FB |
1974 | } |
1975 | ||
72246da4 FB |
1976 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
1977 | const struct dwc3_event_depevt *event) | |
1978 | { | |
1979 | struct dwc3_ep *dep; | |
1980 | u8 epnum = event->endpoint_number; | |
1981 | ||
1982 | dep = dwc->eps[epnum]; | |
1983 | ||
3336abb5 FB |
1984 | if (!(dep->flags & DWC3_EP_ENABLED)) |
1985 | return; | |
1986 | ||
72246da4 FB |
1987 | if (epnum == 0 || epnum == 1) { |
1988 | dwc3_ep0_interrupt(dwc, event); | |
1989 | return; | |
1990 | } | |
1991 | ||
1992 | switch (event->endpoint_event) { | |
1993 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 1994 | dep->resource_index = 0; |
c2df85ca | 1995 | |
16e78db7 | 1996 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1997 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
1998 | dep->name); | |
1999 | return; | |
2000 | } | |
2001 | ||
029d97ff | 2002 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2003 | break; |
2004 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2005 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2006 | break; |
2007 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2008 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2009 | dwc3_gadget_start_isoc(dwc, dep, event); |
2010 | } else { | |
2011 | int ret; | |
2012 | ||
73815280 | 2013 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", |
40aa41fb FB |
2014 | dep->name, event->status & |
2015 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
2016 | ? "Transfer Active" |
2017 | : "Transfer Not Active"); | |
2018 | ||
2019 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
2020 | if (!ret || ret == -EBUSY) | |
2021 | return; | |
2022 | ||
2023 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
2024 | dep->name); | |
2025 | } | |
2026 | ||
879631aa FB |
2027 | break; |
2028 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2029 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2030 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2031 | dep->name); | |
2032 | return; | |
2033 | } | |
2034 | ||
2035 | switch (event->status) { | |
2036 | case DEPEVT_STREAMEVT_FOUND: | |
73815280 FB |
2037 | dwc3_trace(trace_dwc3_gadget, |
2038 | "Stream %d found and started", | |
879631aa FB |
2039 | event->parameters); |
2040 | ||
2041 | break; | |
2042 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2043 | /* FALLTHROUGH */ | |
2044 | default: | |
2045 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
2046 | } | |
72246da4 FB |
2047 | break; |
2048 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
2049 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
2050 | break; | |
72246da4 | 2051 | case DWC3_DEPEVT_EPCMDCMPLT: |
73815280 | 2052 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); |
72246da4 FB |
2053 | break; |
2054 | } | |
2055 | } | |
2056 | ||
2057 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2058 | { | |
2059 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2060 | spin_unlock(&dwc->lock); | |
2061 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2062 | spin_lock(&dwc->lock); | |
2063 | } | |
2064 | } | |
2065 | ||
bc5ba2e0 FB |
2066 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2067 | { | |
73a30bfc | 2068 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2069 | spin_unlock(&dwc->lock); |
2070 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2071 | spin_lock(&dwc->lock); | |
2072 | } | |
2073 | } | |
2074 | ||
2075 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2076 | { | |
73a30bfc | 2077 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2078 | spin_unlock(&dwc->lock); |
2079 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2080 | spin_lock(&dwc->lock); |
8e74475b FB |
2081 | } |
2082 | } | |
2083 | ||
2084 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2085 | { | |
2086 | if (!dwc->gadget_driver) | |
2087 | return; | |
2088 | ||
2089 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2090 | spin_unlock(&dwc->lock); | |
2091 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2092 | spin_lock(&dwc->lock); |
2093 | } | |
2094 | } | |
2095 | ||
b992e681 | 2096 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2097 | { |
2098 | struct dwc3_ep *dep; | |
2099 | struct dwc3_gadget_ep_cmd_params params; | |
2100 | u32 cmd; | |
2101 | int ret; | |
2102 | ||
2103 | dep = dwc->eps[epnum]; | |
2104 | ||
b4996a86 | 2105 | if (!dep->resource_index) |
3daf74d7 PA |
2106 | return; |
2107 | ||
57911504 PA |
2108 | /* |
2109 | * NOTICE: We are violating what the Databook says about the | |
2110 | * EndTransfer command. Ideally we would _always_ wait for the | |
2111 | * EndTransfer Command Completion IRQ, but that's causing too | |
2112 | * much trouble synchronizing between us and gadget driver. | |
2113 | * | |
2114 | * We have discussed this with the IP Provider and it was | |
2115 | * suggested to giveback all requests here, but give HW some | |
2116 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2117 | * an arbitrary 100us delay for that. |
57911504 PA |
2118 | * |
2119 | * Note also that a similar handling was tested by Synopsys | |
2120 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2121 | * In short, what we're doing is: | |
2122 | * | |
2123 | * - Issue EndTransfer WITH CMDIOC bit set | |
2124 | * - Wait 100us | |
2125 | */ | |
2126 | ||
3daf74d7 | 2127 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2128 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2129 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2130 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2131 | memset(¶ms, 0, sizeof(params)); |
2132 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2133 | WARN_ON_ONCE(ret); | |
b4996a86 | 2134 | dep->resource_index = 0; |
041d81f4 | 2135 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2136 | udelay(100); |
72246da4 FB |
2137 | } |
2138 | ||
2139 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2140 | { | |
2141 | u32 epnum; | |
2142 | ||
2143 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2144 | struct dwc3_ep *dep; | |
2145 | ||
2146 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2147 | if (!dep) |
2148 | continue; | |
2149 | ||
72246da4 FB |
2150 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2151 | continue; | |
2152 | ||
624407f9 | 2153 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2154 | } |
2155 | } | |
2156 | ||
2157 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2158 | { | |
2159 | u32 epnum; | |
2160 | ||
2161 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2162 | struct dwc3_ep *dep; | |
2163 | struct dwc3_gadget_ep_cmd_params params; | |
2164 | int ret; | |
2165 | ||
2166 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2167 | if (!dep) |
2168 | continue; | |
72246da4 FB |
2169 | |
2170 | if (!(dep->flags & DWC3_EP_STALL)) | |
2171 | continue; | |
2172 | ||
2173 | dep->flags &= ~DWC3_EP_STALL; | |
2174 | ||
2175 | memset(¶ms, 0, sizeof(params)); | |
2176 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2177 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2178 | WARN_ON_ONCE(ret); | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2183 | { | |
c4430a26 FB |
2184 | int reg; |
2185 | ||
72246da4 FB |
2186 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2187 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2188 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2189 | ||
2190 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2191 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2192 | |
72246da4 | 2193 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2194 | dwc->start_config_issued = false; |
72246da4 FB |
2195 | |
2196 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2197 | dwc->setup_packet_pending = false; |
06a374ed | 2198 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
72246da4 FB |
2199 | } |
2200 | ||
72246da4 FB |
2201 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2202 | { | |
2203 | u32 reg; | |
2204 | ||
df62df56 FB |
2205 | /* |
2206 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2207 | * would cause a missing Disconnect Event if there's a | |
2208 | * pending Setup Packet in the FIFO. | |
2209 | * | |
2210 | * There's no suggested workaround on the official Bug | |
2211 | * report, which states that "unless the driver/application | |
2212 | * is doing any special handling of a disconnect event, | |
2213 | * there is no functional issue". | |
2214 | * | |
2215 | * Unfortunately, it turns out that we _do_ some special | |
2216 | * handling of a disconnect event, namely complete all | |
2217 | * pending transfers, notify gadget driver of the | |
2218 | * disconnection, and so on. | |
2219 | * | |
2220 | * Our suggested workaround is to follow the Disconnect | |
2221 | * Event steps here, instead, based on a setup_packet_pending | |
2222 | * flag. Such flag gets set whenever we have a XferNotReady | |
2223 | * event on EP0 and gets cleared on XferComplete for the | |
2224 | * same endpoint. | |
2225 | * | |
2226 | * Refers to: | |
2227 | * | |
2228 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2229 | * generated if setup packet pending in FIFO | |
2230 | */ | |
2231 | if (dwc->revision < DWC3_REVISION_188A) { | |
2232 | if (dwc->setup_packet_pending) | |
2233 | dwc3_gadget_disconnect_interrupt(dwc); | |
2234 | } | |
2235 | ||
8e74475b | 2236 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2237 | |
2238 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2239 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2240 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2241 | dwc->test_mode = false; |
72246da4 FB |
2242 | |
2243 | dwc3_stop_active_transfers(dwc); | |
2244 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2245 | dwc->start_config_issued = false; |
72246da4 FB |
2246 | |
2247 | /* Reset device address to zero */ | |
2248 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2249 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2250 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2251 | } |
2252 | ||
2253 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2254 | { | |
2255 | u32 reg; | |
2256 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2257 | ||
2258 | /* | |
2259 | * We change the clock only at SS but I dunno why I would want to do | |
2260 | * this. Maybe it becomes part of the power saving plan. | |
2261 | */ | |
2262 | ||
2263 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2264 | return; | |
2265 | ||
2266 | /* | |
2267 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2268 | * each time on Connect Done. | |
2269 | */ | |
2270 | if (!usb30_clock) | |
2271 | return; | |
2272 | ||
2273 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2274 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2275 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2276 | } | |
2277 | ||
72246da4 FB |
2278 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2279 | { | |
72246da4 FB |
2280 | struct dwc3_ep *dep; |
2281 | int ret; | |
2282 | u32 reg; | |
2283 | u8 speed; | |
2284 | ||
72246da4 FB |
2285 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2286 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2287 | dwc->speed = speed; | |
2288 | ||
2289 | dwc3_update_ram_clk_sel(dwc, speed); | |
2290 | ||
2291 | switch (speed) { | |
2292 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2293 | /* |
2294 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2295 | * would cause a missing USB3 Reset event. | |
2296 | * | |
2297 | * In such situations, we should force a USB3 Reset | |
2298 | * event by calling our dwc3_gadget_reset_interrupt() | |
2299 | * routine. | |
2300 | * | |
2301 | * Refers to: | |
2302 | * | |
2303 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2304 | * not be generated always when the link enters poll | |
2305 | */ | |
2306 | if (dwc->revision < DWC3_REVISION_190A) | |
2307 | dwc3_gadget_reset_interrupt(dwc); | |
2308 | ||
72246da4 FB |
2309 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2310 | dwc->gadget.ep0->maxpacket = 512; | |
2311 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2312 | break; | |
2313 | case DWC3_DCFG_HIGHSPEED: | |
2314 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2315 | dwc->gadget.ep0->maxpacket = 64; | |
2316 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2317 | break; | |
2318 | case DWC3_DCFG_FULLSPEED2: | |
2319 | case DWC3_DCFG_FULLSPEED1: | |
2320 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2321 | dwc->gadget.ep0->maxpacket = 64; | |
2322 | dwc->gadget.speed = USB_SPEED_FULL; | |
2323 | break; | |
2324 | case DWC3_DCFG_LOWSPEED: | |
2325 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2326 | dwc->gadget.ep0->maxpacket = 8; | |
2327 | dwc->gadget.speed = USB_SPEED_LOW; | |
2328 | break; | |
2329 | } | |
2330 | ||
2b758350 PA |
2331 | /* Enable USB2 LPM Capability */ |
2332 | ||
2333 | if ((dwc->revision > DWC3_REVISION_194A) | |
2334 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2335 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2336 | reg |= DWC3_DCFG_LPM_CAP; | |
2337 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2338 | ||
2339 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2340 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2341 | ||
460d098c | 2342 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2343 | |
80caf7d2 HR |
2344 | /* |
2345 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2346 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2347 | * BESL value in the LPM token is less than or equal to LPM | |
2348 | * NYET threshold. | |
2349 | */ | |
2350 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2351 | && dwc->has_lpm_erratum, | |
2352 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2353 | ||
2354 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2355 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2356 | ||
356363bf FB |
2357 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2358 | } else { | |
2359 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2360 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2361 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2362 | } | |
2363 | ||
72246da4 | 2364 | dep = dwc->eps[0]; |
265b70a7 PZ |
2365 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2366 | false); | |
72246da4 FB |
2367 | if (ret) { |
2368 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2369 | return; | |
2370 | } | |
2371 | ||
2372 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2373 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2374 | false); | |
72246da4 FB |
2375 | if (ret) { |
2376 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2377 | return; | |
2378 | } | |
2379 | ||
2380 | /* | |
2381 | * Configure PHY via GUSB3PIPECTLn if required. | |
2382 | * | |
2383 | * Update GTXFIFOSIZn | |
2384 | * | |
2385 | * In both cases reset values should be sufficient. | |
2386 | */ | |
2387 | } | |
2388 | ||
2389 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2390 | { | |
72246da4 FB |
2391 | /* |
2392 | * TODO take core out of low power mode when that's | |
2393 | * implemented. | |
2394 | */ | |
2395 | ||
2396 | dwc->gadget_driver->resume(&dwc->gadget); | |
2397 | } | |
2398 | ||
2399 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2400 | unsigned int evtinfo) | |
2401 | { | |
fae2b904 | 2402 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2403 | unsigned int pwropt; |
2404 | ||
2405 | /* | |
2406 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2407 | * Hibernation mode enabled which would show up when device detects | |
2408 | * host-initiated U3 exit. | |
2409 | * | |
2410 | * In that case, device will generate a Link State Change Interrupt | |
2411 | * from U3 to RESUME which is only necessary if Hibernation is | |
2412 | * configured in. | |
2413 | * | |
2414 | * There are no functional changes due to such spurious event and we | |
2415 | * just need to ignore it. | |
2416 | * | |
2417 | * Refers to: | |
2418 | * | |
2419 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2420 | * operational mode | |
2421 | */ | |
2422 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2423 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2424 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2425 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2426 | (next == DWC3_LINK_STATE_RESUME)) { | |
73815280 FB |
2427 | dwc3_trace(trace_dwc3_gadget, |
2428 | "ignoring transition U3 -> Resume"); | |
0b0cc1cd FB |
2429 | return; |
2430 | } | |
2431 | } | |
fae2b904 FB |
2432 | |
2433 | /* | |
2434 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2435 | * on the link partner, the USB session might do multiple entry/exit | |
2436 | * of low power states before a transfer takes place. | |
2437 | * | |
2438 | * Due to this problem, we might experience lower throughput. The | |
2439 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2440 | * transitioning from U1/U2 to U0 and enable those bits again | |
2441 | * after a transfer completes and there are no pending transfers | |
2442 | * on any of the enabled endpoints. | |
2443 | * | |
2444 | * This is the first half of that workaround. | |
2445 | * | |
2446 | * Refers to: | |
2447 | * | |
2448 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2449 | * core send LGO_Ux entering U0 | |
2450 | */ | |
2451 | if (dwc->revision < DWC3_REVISION_183A) { | |
2452 | if (next == DWC3_LINK_STATE_U0) { | |
2453 | u32 u1u2; | |
2454 | u32 reg; | |
2455 | ||
2456 | switch (dwc->link_state) { | |
2457 | case DWC3_LINK_STATE_U1: | |
2458 | case DWC3_LINK_STATE_U2: | |
2459 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2460 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2461 | | DWC3_DCTL_ACCEPTU2ENA | |
2462 | | DWC3_DCTL_INITU1ENA | |
2463 | | DWC3_DCTL_ACCEPTU1ENA); | |
2464 | ||
2465 | if (!dwc->u1u2) | |
2466 | dwc->u1u2 = reg & u1u2; | |
2467 | ||
2468 | reg &= ~u1u2; | |
2469 | ||
2470 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2471 | break; | |
2472 | default: | |
2473 | /* do nothing */ | |
2474 | break; | |
2475 | } | |
2476 | } | |
2477 | } | |
2478 | ||
bc5ba2e0 FB |
2479 | switch (next) { |
2480 | case DWC3_LINK_STATE_U1: | |
2481 | if (dwc->speed == USB_SPEED_SUPER) | |
2482 | dwc3_suspend_gadget(dwc); | |
2483 | break; | |
2484 | case DWC3_LINK_STATE_U2: | |
2485 | case DWC3_LINK_STATE_U3: | |
2486 | dwc3_suspend_gadget(dwc); | |
2487 | break; | |
2488 | case DWC3_LINK_STATE_RESUME: | |
2489 | dwc3_resume_gadget(dwc); | |
2490 | break; | |
2491 | default: | |
2492 | /* do nothing */ | |
2493 | break; | |
2494 | } | |
2495 | ||
e57ebc1d | 2496 | dwc->link_state = next; |
72246da4 FB |
2497 | } |
2498 | ||
e1dadd3b FB |
2499 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2500 | unsigned int evtinfo) | |
2501 | { | |
2502 | unsigned int is_ss = evtinfo & BIT(4); | |
2503 | ||
2504 | /** | |
2505 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2506 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2507 | * randomly. | |
2508 | * | |
2509 | * Because of this issue, core could generate bogus hibernation | |
2510 | * events which SW needs to ignore. | |
2511 | * | |
2512 | * Refers to: | |
2513 | * | |
2514 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2515 | * Device Fallback from SuperSpeed | |
2516 | */ | |
2517 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2518 | return; | |
2519 | ||
2520 | /* enter hibernation here */ | |
2521 | } | |
2522 | ||
72246da4 FB |
2523 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2524 | const struct dwc3_event_devt *event) | |
2525 | { | |
2526 | switch (event->type) { | |
2527 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2528 | dwc3_gadget_disconnect_interrupt(dwc); | |
2529 | break; | |
2530 | case DWC3_DEVICE_EVENT_RESET: | |
2531 | dwc3_gadget_reset_interrupt(dwc); | |
2532 | break; | |
2533 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2534 | dwc3_gadget_conndone_interrupt(dwc); | |
2535 | break; | |
2536 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2537 | dwc3_gadget_wakeup_interrupt(dwc); | |
2538 | break; | |
e1dadd3b FB |
2539 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2540 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2541 | "unexpected hibernation event\n")) | |
2542 | break; | |
2543 | ||
2544 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2545 | break; | |
72246da4 FB |
2546 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2547 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2548 | break; | |
2549 | case DWC3_DEVICE_EVENT_EOPF: | |
73815280 | 2550 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); |
72246da4 FB |
2551 | break; |
2552 | case DWC3_DEVICE_EVENT_SOF: | |
73815280 | 2553 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); |
72246da4 FB |
2554 | break; |
2555 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
73815280 | 2556 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); |
72246da4 FB |
2557 | break; |
2558 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
73815280 | 2559 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); |
72246da4 FB |
2560 | break; |
2561 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
73815280 | 2562 | dwc3_trace(trace_dwc3_gadget, "Overflow"); |
72246da4 FB |
2563 | break; |
2564 | default: | |
e9f2aa87 | 2565 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2566 | } |
2567 | } | |
2568 | ||
2569 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2570 | const union dwc3_event *event) | |
2571 | { | |
2c4cbe6e FB |
2572 | trace_dwc3_event(event->raw); |
2573 | ||
72246da4 FB |
2574 | /* Endpoint IRQ, handle it and return early */ |
2575 | if (event->type.is_devspec == 0) { | |
2576 | /* depevt */ | |
2577 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2578 | } | |
2579 | ||
2580 | switch (event->type.type) { | |
2581 | case DWC3_EVENT_TYPE_DEV: | |
2582 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2583 | break; | |
2584 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2585 | default: | |
2586 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2587 | } | |
2588 | } | |
2589 | ||
f42f2447 | 2590 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2591 | { |
f42f2447 | 2592 | struct dwc3_event_buffer *evt; |
b15a762f | 2593 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2594 | int left; |
e8adfc30 | 2595 | u32 reg; |
b15a762f | 2596 | |
f42f2447 FB |
2597 | evt = dwc->ev_buffs[buf]; |
2598 | left = evt->count; | |
b15a762f | 2599 | |
f42f2447 FB |
2600 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2601 | return IRQ_NONE; | |
b15a762f | 2602 | |
f42f2447 FB |
2603 | while (left > 0) { |
2604 | union dwc3_event event; | |
b15a762f | 2605 | |
f42f2447 | 2606 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2607 | |
f42f2447 | 2608 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2609 | |
f42f2447 FB |
2610 | /* |
2611 | * FIXME we wrap around correctly to the next entry as | |
2612 | * almost all entries are 4 bytes in size. There is one | |
2613 | * entry which has 12 bytes which is a regular entry | |
2614 | * followed by 8 bytes data. ATM I don't know how | |
2615 | * things are organized if we get next to the a | |
2616 | * boundary so I worry about that once we try to handle | |
2617 | * that. | |
2618 | */ | |
2619 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2620 | left -= 4; | |
b15a762f | 2621 | |
f42f2447 FB |
2622 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2623 | } | |
b15a762f | 2624 | |
f42f2447 FB |
2625 | evt->count = 0; |
2626 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2627 | ret = IRQ_HANDLED; | |
b15a762f | 2628 | |
f42f2447 FB |
2629 | /* Unmask interrupt */ |
2630 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2631 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2632 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2633 | |
f42f2447 FB |
2634 | return ret; |
2635 | } | |
e8adfc30 | 2636 | |
f42f2447 FB |
2637 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2638 | { | |
2639 | struct dwc3 *dwc = _dwc; | |
2640 | unsigned long flags; | |
2641 | irqreturn_t ret = IRQ_NONE; | |
2642 | int i; | |
2643 | ||
2644 | spin_lock_irqsave(&dwc->lock, flags); | |
2645 | ||
2646 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2647 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f FB |
2648 | |
2649 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2650 | ||
2651 | return ret; | |
2652 | } | |
2653 | ||
7f97aa98 | 2654 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2655 | { |
2656 | struct dwc3_event_buffer *evt; | |
72246da4 | 2657 | u32 count; |
e8adfc30 | 2658 | u32 reg; |
72246da4 | 2659 | |
b15a762f FB |
2660 | evt = dwc->ev_buffs[buf]; |
2661 | ||
72246da4 FB |
2662 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2663 | count &= DWC3_GEVNTCOUNT_MASK; | |
2664 | if (!count) | |
2665 | return IRQ_NONE; | |
2666 | ||
b15a762f FB |
2667 | evt->count = count; |
2668 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2669 | |
e8adfc30 FB |
2670 | /* Mask interrupt */ |
2671 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2672 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2673 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2674 | ||
b15a762f | 2675 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2676 | } |
2677 | ||
2678 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2679 | { | |
2680 | struct dwc3 *dwc = _dwc; | |
2681 | int i; | |
2682 | irqreturn_t ret = IRQ_NONE; | |
2683 | ||
9f622b2a | 2684 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2685 | irqreturn_t status; |
2686 | ||
7f97aa98 | 2687 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2688 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2689 | ret = status; |
2690 | } | |
2691 | ||
72246da4 FB |
2692 | return ret; |
2693 | } | |
2694 | ||
2695 | /** | |
2696 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2697 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2698 | * |
2699 | * Returns 0 on success otherwise negative errno. | |
2700 | */ | |
41ac7b3a | 2701 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2702 | { |
72246da4 | 2703 | int ret; |
72246da4 FB |
2704 | |
2705 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2706 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2707 | if (!dwc->ctrl_req) { | |
2708 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2709 | ret = -ENOMEM; | |
2710 | goto err0; | |
2711 | } | |
2712 | ||
2abd9d5f | 2713 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2714 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2715 | if (!dwc->ep0_trb) { | |
2716 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2717 | ret = -ENOMEM; | |
2718 | goto err1; | |
2719 | } | |
2720 | ||
3ef35faf | 2721 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2722 | if (!dwc->setup_buf) { |
72246da4 FB |
2723 | ret = -ENOMEM; |
2724 | goto err2; | |
2725 | } | |
2726 | ||
5812b1c2 | 2727 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2728 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2729 | GFP_KERNEL); | |
5812b1c2 FB |
2730 | if (!dwc->ep0_bounce) { |
2731 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2732 | ret = -ENOMEM; | |
2733 | goto err3; | |
2734 | } | |
2735 | ||
72246da4 | 2736 | dwc->gadget.ops = &dwc3_gadget_ops; |
d327ab5b | 2737 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 | 2738 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2739 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2740 | dwc->gadget.name = "dwc3-gadget"; |
2741 | ||
a4b9d94b DC |
2742 | /* |
2743 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2744 | * on ep out. | |
2745 | */ | |
2746 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2747 | ||
72246da4 FB |
2748 | /* |
2749 | * REVISIT: Here we should clear all pending IRQs to be | |
2750 | * sure we're starting from a well known location. | |
2751 | */ | |
2752 | ||
2753 | ret = dwc3_gadget_init_endpoints(dwc); | |
2754 | if (ret) | |
5812b1c2 | 2755 | goto err4; |
72246da4 | 2756 | |
72246da4 FB |
2757 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2758 | if (ret) { | |
2759 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2760 | goto err4; |
72246da4 FB |
2761 | } |
2762 | ||
2763 | return 0; | |
2764 | ||
5812b1c2 | 2765 | err4: |
e1f80467 | 2766 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2767 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2768 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2769 | |
72246da4 | 2770 | err3: |
0fc9a1be | 2771 | kfree(dwc->setup_buf); |
72246da4 FB |
2772 | |
2773 | err2: | |
2774 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2775 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2776 | ||
2777 | err1: | |
2778 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2779 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2780 | ||
2781 | err0: | |
2782 | return ret; | |
2783 | } | |
2784 | ||
7415f17c FB |
2785 | /* -------------------------------------------------------------------------- */ |
2786 | ||
72246da4 FB |
2787 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2788 | { | |
72246da4 | 2789 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2790 | |
72246da4 FB |
2791 | dwc3_gadget_free_endpoints(dwc); |
2792 | ||
3ef35faf FB |
2793 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2794 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2795 | |
0fc9a1be | 2796 | kfree(dwc->setup_buf); |
72246da4 FB |
2797 | |
2798 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2799 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2800 | ||
2801 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2802 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2803 | } |
7415f17c | 2804 | |
0b0231aa | 2805 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 2806 | { |
7b2a0368 | 2807 | if (dwc->pullups_connected) { |
7415f17c | 2808 | dwc3_gadget_disable_irq(dwc); |
7b2a0368 FB |
2809 | dwc3_gadget_run_stop(dwc, true, true); |
2810 | } | |
7415f17c | 2811 | |
7415f17c FB |
2812 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2813 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2814 | ||
2815 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2816 | ||
2817 | return 0; | |
2818 | } | |
2819 | ||
2820 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2821 | { | |
2822 | struct dwc3_ep *dep; | |
2823 | int ret; | |
2824 | ||
2825 | /* Start with SuperSpeed Default */ | |
2826 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2827 | ||
2828 | dep = dwc->eps[0]; | |
265b70a7 PZ |
2829 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2830 | false); | |
7415f17c FB |
2831 | if (ret) |
2832 | goto err0; | |
2833 | ||
2834 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2835 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2836 | false); | |
7415f17c FB |
2837 | if (ret) |
2838 | goto err1; | |
2839 | ||
2840 | /* begin to receive SETUP packets */ | |
2841 | dwc->ep0state = EP0_SETUP_PHASE; | |
2842 | dwc3_ep0_out_start(dwc); | |
2843 | ||
2844 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2845 | ||
0b0231aa FB |
2846 | if (dwc->pullups_connected) { |
2847 | dwc3_gadget_enable_irq(dwc); | |
2848 | dwc3_gadget_run_stop(dwc, true, false); | |
2849 | } | |
2850 | ||
7415f17c FB |
2851 | return 0; |
2852 | ||
2853 | err1: | |
2854 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2855 | ||
2856 | err0: | |
2857 | return ret; | |
2858 | } |