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USB: f_mass_storage: improve memory barriers and synchronization
[mirror_ubuntu-artful-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
4199c5f8
FB		 183 usb_gadget_unmap_request_by_dev(dwc->sysdev,
184 &req->request, req->direction);
72246da4 185
2c4cbe6e 186 trace_dwc3_gadget_giveback(req);
72246da4
FB		 187
188 spin_unlock(&dwc->lock);
304f7e5e 189 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 190 spin_lock(&dwc->lock);
fc8bb91b
FB		 191
192 if (dep->number > 1)
193 pm_runtime_put(dwc->dev);
72246da4
FB		 194}
195
3ece0ec4 196int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 197{
198 u32 timeout = 500;
71f7e702 199 int status = 0;
0fe886cd 200 int ret = 0;
b09bb642
FB		 201 u32 reg;
202
203 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
204 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
205
206 do {
207 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
208 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 209 status = DWC3_DGCMD_STATUS(reg);
210 if (status)
0fe886cd
FB		 211 ret = -EINVAL;
212 break;
b09bb642 213 }
e3aee486 214 } while (--timeout);
0fe886cd
FB		 215
216 if (!timeout) {
0fe886cd 217 ret = -ETIMEDOUT;
71f7e702 218 status = -ETIMEDOUT;
0fe886cd
FB		 219 }
220
71f7e702
FB		 221 trace_dwc3_gadget_generic_cmd(cmd, param, status);
222
0fe886cd 223 return ret;
b09bb642
FB		 224}
225
c36d8e94
FB		 226static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
227
2cd4718d
FB		 228int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
229 struct dwc3_gadget_ep_cmd_params *params)
72246da4 230{
8897a761 231 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 232 struct dwc3 *dwc = dep->dwc;
61d58242 233 u32 timeout = 500;
72246da4
FB		 234 u32 reg;
235
0933df15 236 int cmd_status = 0;
2b0f11df 237 int susphy = false;
c0ca324d 238 int ret = -EINVAL;
72246da4 239
2b0f11df
FB		 240 /*
241 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
242 * we're issuing an endpoint command, we must check if
243 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
244 *
245 * We will also set SUSPHY bit to what it was before returning as stated
246 * by the same section on Synopsys databook.
247 */
ab2a92e7
FB		 248 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
249 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
250 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
251 susphy = true;
252 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
253 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
254 }
2b0f11df
FB		 255 }
256
5999914f 257 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 258 int needs_wakeup;
259
260 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
261 dwc->link_state == DWC3_LINK_STATE_U2 ||
262 dwc->link_state == DWC3_LINK_STATE_U3);
263
264 if (unlikely(needs_wakeup)) {
265 ret = __dwc3_gadget_wakeup(dwc);
266 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
267 ret);
268 }
269 }
270
2eb88016
FB		 271 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
272 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
273 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 274
8897a761
FB		 275 /*
276 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
277 * not relying on XferNotReady, we can make use of a special "No
278 * Response Update Transfer" command where we should clear both CmdAct
279 * and CmdIOC bits.
280 *
281 * With this, we don't need to wait for command completion and can
282 * straight away issue further commands to the endpoint.
283 *
284 * NOTICE: We're making an assumption that control endpoints will never
285 * make use of Update Transfer command. This is a safe assumption
286 * because we can never have more than one request at a time with
287 * Control Endpoints. If anybody changes that assumption, this chunk
288 * needs to be updated accordingly.
289 */
290 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
291 !usb_endpoint_xfer_isoc(desc))
292 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
293 else
294 cmd |= DWC3_DEPCMD_CMDACT;
295
296 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 297 do {
2eb88016 298 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 299 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 300 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 301
7b9cc7a2
KL		 302 switch (cmd_status) {
303 case 0:
304 ret = 0;
305 break;
306 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 307 ret = -EINVAL;
c0ca324d 308 break;
7b9cc7a2
KL		 309 case DEPEVT_TRANSFER_BUS_EXPIRY:
310 /*
311 * SW issues START TRANSFER command to
312 * isochronous ep with future frame interval. If
313 * future interval time has already passed when
314 * core receives the command, it will respond
315 * with an error status of 'Bus Expiry'.
316 *
317 * Instead of always returning -EINVAL, let's
318 * give a hint to the gadget driver that this is
319 * the case by returning -EAGAIN.
320 */
7b9cc7a2
KL		 321 ret = -EAGAIN;
322 break;
323 default:
324 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
325 }
326
c0ca324d 327 break;
72246da4 328 }
f6bb225b 329 } while (--timeout);
72246da4 330
f6bb225b 331 if (timeout == 0) {
f6bb225b 332 ret = -ETIMEDOUT;
0933df15 333 cmd_status = -ETIMEDOUT;
f6bb225b 334 }
c0ca324d 335
0933df15
FB		 336 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
337
6cb2e4e3
FB		 338 if (ret == 0) {
339 switch (DWC3_DEPCMD_CMD(cmd)) {
340 case DWC3_DEPCMD_STARTTRANSFER:
341 dep->flags |= DWC3_EP_TRANSFER_STARTED;
342 break;
343 case DWC3_DEPCMD_ENDTRANSFER:
344 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
345 break;
346 default:
347 /* nothing */
348 break;
349 }
350 }
351
2b0f11df
FB		 352 if (unlikely(susphy)) {
353 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
354 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
355 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
356 }
357
c0ca324d 358 return ret;
72246da4
FB		 359}
360
50c763f8
JY		 361static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
362{
363 struct dwc3 *dwc = dep->dwc;
364 struct dwc3_gadget_ep_cmd_params params;
365 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
366
367 /*
368 * As of core revision 2.60a the recommended programming model
369 * is to set the ClearPendIN bit when issuing a Clear Stall EP
370 * command for IN endpoints. This is to prevent an issue where
371 * some (non-compliant) hosts may not send ACK TPs for pending
372 * IN transfers due to a mishandled error condition. Synopsys
373 * STAR 9000614252.
374 */
5e6c88d2
LB		 375 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
376 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 377 cmd |= DWC3_DEPCMD_CLEARPENDIN;
378
379 memset(&params, 0, sizeof(params));
380
2cd4718d 381 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 382}
383
72246da4 384static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 385 struct dwc3_trb *trb)
72246da4 386{
c439ef87 387 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 388
389 return dep->trb_pool_dma + offset;
390}
391
392static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
393{
394 struct dwc3 *dwc = dep->dwc;
395
396 if (dep->trb_pool)
397 return 0;
398
d64ff406 399 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 400 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
401 &dep->trb_pool_dma, GFP_KERNEL);
402 if (!dep->trb_pool) {
403 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
404 dep->name);
405 return -ENOMEM;
406 }
407
408 return 0;
409}
410
411static void dwc3_free_trb_pool(struct dwc3_ep *dep)
412{
413 struct dwc3 *dwc = dep->dwc;
414
d64ff406 415 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 416 dep->trb_pool, dep->trb_pool_dma);
417
418 dep->trb_pool = NULL;
419 dep->trb_pool_dma = 0;
420}
421
c4509601
JY		 422static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
423
424/**
425 * dwc3_gadget_start_config - Configure EP resources
426 * @dwc: pointer to our controller context structure
427 * @dep: endpoint that is being enabled
428 *
429 * The assignment of transfer resources cannot perfectly follow the
430 * data book due to the fact that the controller driver does not have
431 * all knowledge of the configuration in advance. It is given this
432 * information piecemeal by the composite gadget framework after every
433 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
434 * programming model in this scenario can cause errors. For two
435 * reasons:
436 *
437 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
438 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
439 * multiple interfaces.
440 *
441 * 2) The databook does not mention doing more DEPXFERCFG for new
442 * endpoint on alt setting (8.1.6).
443 *
444 * The following simplified method is used instead:
445 *
446 * All hardware endpoints can be assigned a transfer resource and this
447 * setting will stay persistent until either a core reset or
448 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
449 * do DEPXFERCFG for every hardware endpoint as well. We are
450 * guaranteed that there are as many transfer resources as endpoints.
451 *
452 * This function is called for each endpoint when it is being enabled
453 * but is triggered only when called for EP0-out, which always happens
454 * first, and which should only happen in one of the above conditions.
455 */
72246da4
FB		 456static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459 u32 cmd;
c4509601
JY		 460 int i;
461 int ret;
462
463 if (dep->number)
464 return 0;
72246da4
FB		 465
466 memset(&params, 0x00, sizeof(params));
c4509601 467 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 468
2cd4718d 469 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 470 if (ret)
471 return ret;
472
473 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
474 struct dwc3_ep *dep = dwc->eps[i];
72246da4 475
c4509601
JY		 476 if (!dep)
477 continue;
478
479 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
480 if (ret)
481 return ret;
72246da4
FB		 482 }
483
484 return 0;
485}
486
487static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 488 bool modify, bool restore)
72246da4 489{
39ebb05c
JY		 490 const struct usb_ss_ep_comp_descriptor *comp_desc;
491 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 492 struct dwc3_gadget_ep_cmd_params params;
493
21e64bf2
FB		 494 if (dev_WARN_ONCE(dwc->dev, modify && restore,
495 "Can't modify and restore\n"))
496 return -EINVAL;
497
39ebb05c
JY		 498 comp_desc = dep->endpoint.comp_desc;
499 desc = dep->endpoint.desc;
500
72246da4
FB		 501 memset(&params, 0x00, sizeof(params));
502
dc1c70a7 503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
505
506 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 507 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 508 u32 burst = dep->endpoint.maxburst;
676e3497 509 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 510 }
72246da4 511
21e64bf2
FB		 512 if (modify) {
513 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
514 } else if (restore) {
265b70a7
PZ		 515 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
516 params.param2 |= dep->saved_state;
21e64bf2
FB		 517 } else {
518 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 519 }
520
4bc48c97
FB		 521 if (usb_endpoint_xfer_control(desc))
522 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 523
524 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
525 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 526
18b7ede5 527 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 528 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
529 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 530 dep->stream_capable = true;
531 }
532
0b93a4c8 533 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 534 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 535
536 /*
537 * We are doing 1:1 mapping for endpoints, meaning
538 * Physical Endpoints 2 maps to Logical Endpoint 2 and
539 * so on. We consider the direction bit as part of the physical
540 * endpoint number. So USB endpoint 0x81 is 0x03.
541 */
dc1c70a7 542 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 543
544 /*
545 * We must use the lower 16 TX FIFOs even though
546 * HW might have more
547 */
548 if (dep->direction)
dc1c70a7 549 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 550
551 if (desc->bInterval) {
dc1c70a7 552 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 553 dep->interval = 1 << (desc->bInterval - 1);
554 }
555
2cd4718d 556 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 557}
558
559static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
560{
561 struct dwc3_gadget_ep_cmd_params params;
562
563 memset(&params, 0x00, sizeof(params));
564
dc1c70a7 565 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 566
2cd4718d
FB		 567 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
568 &params);
72246da4
FB		 569}
570
571/**
572 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
573 * @dep: endpoint to be initialized
574 * @desc: USB Endpoint Descriptor
575 *
576 * Caller should take care of locking
577 */
578static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 579 bool modify, bool restore)
72246da4 580{
39ebb05c 581 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 582 struct dwc3 *dwc = dep->dwc;
39ebb05c 583
72246da4 584 u32 reg;
b09e99ee 585 int ret;
72246da4
FB		 586
587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
589 if (ret)
590 return ret;
591 }
592
39ebb05c 593 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 594 if (ret)
595 return ret;
596
597 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 598 struct dwc3_trb *trb_st_hw;
599 struct dwc3_trb *trb_link;
72246da4 600
72246da4
FB		 601 dep->type = usb_endpoint_type(desc);
602 dep->flags |= DWC3_EP_ENABLED;
76a638f8 603 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 604
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg |= DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
608
76a638f8
BW		 609 init_waitqueue_head(&dep->wait_end_transfer);
610
36b68aae 611 if (usb_endpoint_xfer_control(desc))
2870e501 612 goto out;
72246da4 613
0d25744a
JY		 614 /* Initialize the TRB ring */
615 dep->trb_dequeue = 0;
616 dep->trb_enqueue = 0;
617 memset(dep->trb_pool, 0,
618 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
619
36b68aae 620 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 621 trb_st_hw = &dep->trb_pool[0];
622
f6bafc6a 623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 624 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
625 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
627 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 628 }
629
a97ea994
FB		 630 /*
631 * Issue StartTransfer here with no-op TRB so we can always rely on No
632 * Response Update Transfer command.
633 */
634 if (usb_endpoint_xfer_bulk(desc)) {
635 struct dwc3_gadget_ep_cmd_params params;
636 struct dwc3_trb *trb;
637 dma_addr_t trb_dma;
638 u32 cmd;
639
640 memset(&params, 0, sizeof(params));
641 trb = &dep->trb_pool[0];
642 trb_dma = dwc3_trb_dma_offset(dep, trb);
643
644 params.param0 = upper_32_bits(trb_dma);
645 params.param1 = lower_32_bits(trb_dma);
646
647 cmd = DWC3_DEPCMD_STARTTRANSFER;
648
649 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
650 if (ret < 0)
651 return ret;
652
653 dep->flags |= DWC3_EP_BUSY;
654
655 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
656 WARN_ON_ONCE(!dep->resource_index);
657 }
658
2870e501
FB		 659
660out:
661 trace_dwc3_gadget_ep_enable(dep);
662
72246da4
FB		 663 return 0;
664}
665
b992e681 666static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 667static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 668{
669 struct dwc3_request *req;
670
0e146028 671 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 672
0e146028
FB		 673 /* - giveback all requests to gadget driver */
674 while (!list_empty(&dep->started_list)) {
675 req = next_request(&dep->started_list);
1591633e 676
0e146028 677 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 678 }
679
aa3342c8
FB		 680 while (!list_empty(&dep->pending_list)) {
681 req = next_request(&dep->pending_list);
72246da4 682
624407f9 683 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 684 }
72246da4
FB		 685}
686
687/**
688 * __dwc3_gadget_ep_disable - Disables a HW endpoint
689 * @dep: the endpoint to disable
690 *
624407f9
SAS		 691 * This function also removes requests which are currently processed ny the
692 * hardware and those which are not yet scheduled.
693 * Caller should take care of locking.
72246da4 694 */
72246da4
FB		 695static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
696{
697 struct dwc3 *dwc = dep->dwc;
698 u32 reg;
699
2870e501 700 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 701
624407f9 702 dwc3_remove_requests(dwc, dep);
72246da4 703
687ef981
FB		 704 /* make sure HW endpoint isn't stalled */
705 if (dep->flags & DWC3_EP_STALL)
7a608559 706 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 707
72246da4
FB		 708 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
709 reg &= ~DWC3_DALEPENA_EP(dep->number);
710 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
711
879631aa 712 dep->stream_capable = false;
72246da4 713 dep->type = 0;
76a638f8 714 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 715
39ebb05c
JY		 716 /* Clear out the ep descriptors for non-ep0 */
717 if (dep->number > 1) {
718 dep->endpoint.comp_desc = NULL;
719 dep->endpoint.desc = NULL;
720 }
721
72246da4
FB		 722 return 0;
723}
724
725/* -------------------------------------------------------------------------- */
726
727static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
728 const struct usb_endpoint_descriptor *desc)
729{
730 return -EINVAL;
731}
732
733static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
734{
735 return -EINVAL;
736}
737
738/* -------------------------------------------------------------------------- */
739
740static int dwc3_gadget_ep_enable(struct usb_ep *ep,
741 const struct usb_endpoint_descriptor *desc)
742{
743 struct dwc3_ep *dep;
744 struct dwc3 *dwc;
745 unsigned long flags;
746 int ret;
747
748 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
749 pr_debug("dwc3: invalid parameters\n");
750 return -EINVAL;
751 }
752
753 if (!desc->wMaxPacketSize) {
754 pr_debug("dwc3: missing wMaxPacketSize\n");
755 return -EINVAL;
756 }
757
758 dep = to_dwc3_ep(ep);
759 dwc = dep->dwc;
760
95ca961c
FB		 761 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
762 "%s is already enabled\n",
763 dep->name))
c6f83f38 764 return 0;
c6f83f38 765
72246da4 766 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 767 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 768 spin_unlock_irqrestore(&dwc->lock, flags);
769
770 return ret;
771}
772
773static int dwc3_gadget_ep_disable(struct usb_ep *ep)
774{
775 struct dwc3_ep *dep;
776 struct dwc3 *dwc;
777 unsigned long flags;
778 int ret;
779
780 if (!ep) {
781 pr_debug("dwc3: invalid parameters\n");
782 return -EINVAL;
783 }
784
785 dep = to_dwc3_ep(ep);
786 dwc = dep->dwc;
787
95ca961c
FB		 788 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
789 "%s is already disabled\n",
790 dep->name))
72246da4 791 return 0;
72246da4 792
72246da4
FB		 793 spin_lock_irqsave(&dwc->lock, flags);
794 ret = __dwc3_gadget_ep_disable(dep);
795 spin_unlock_irqrestore(&dwc->lock, flags);
796
797 return ret;
798}
799
800static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
801 gfp_t gfp_flags)
802{
803 struct dwc3_request *req;
804 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 805
806 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 807 if (!req)
72246da4 808 return NULL;
72246da4
FB		 809
810 req->epnum = dep->number;
811 req->dep = dep;
72246da4 812
68d34c8a
FB		 813 dep->allocated_requests++;
814
2c4cbe6e
FB		 815 trace_dwc3_alloc_request(req);
816
72246da4
FB		 817 return &req->request;
818}
819
820static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
821 struct usb_request *request)
822{
823 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 824 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 825
68d34c8a 826 dep->allocated_requests--;
2c4cbe6e 827 trace_dwc3_free_request(req);
72246da4
FB		 828 kfree(req);
829}
830
2c78c029
FB		 831static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
832
e49d3cf4
FB		 833static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
834 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
835 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 836{
6b9018d4
FB		 837 struct dwc3 *dwc = dep->dwc;
838 struct usb_gadget *gadget = &dwc->gadget;
839 enum usb_device_speed speed = gadget->speed;
c71fc37c 840
ef966b9d 841 dwc3_ep_inc_enq(dep);
e5ba5ec8 842
f6bafc6a
FB		 843 trb->size = DWC3_TRB_SIZE_LENGTH(length);
844 trb->bpl = lower_32_bits(dma);
845 trb->bph = upper_32_bits(dma);
c71fc37c 846
16e78db7 847 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 848 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 849 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 850 break;
851
852 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 853 if (!node) {
e5ba5ec8 854 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 855
856 if (speed == USB_SPEED_HIGH) {
857 struct usb_ep *ep = &dep->endpoint;
858 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
859 }
860 } else {
e5ba5ec8 861 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 862 }
ca4d44ea
FB		 863
864 /* always enable Interrupt on Missed ISOC */
865 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 866 break;
867
868 case USB_ENDPOINT_XFER_BULK:
869 case USB_ENDPOINT_XFER_INT:
f6bafc6a 870 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 871 break;
872 default:
873 /*
874 * This is only possible with faulty memory because we
875 * checked it already :)
876 */
0a695d4c
FB		 877 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
878 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 879 }
880
ca4d44ea 881 /* always enable Continue on Short Packet */
c9508c8c 882 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 883 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 884
e49d3cf4 885 if (short_not_ok)
c9508c8c
FB		 886 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
887 }
888
e49d3cf4 889 if ((!no_interrupt && !chain) ||
2c78c029 890 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 891 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 892
e5ba5ec8
PA		 893 if (chain)
894 trb->ctrl |= DWC3_TRB_CTRL_CHN;
895
16e78db7 896 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 897 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 898
f6bafc6a 899 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 900
901 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 902}
903
e49d3cf4
FB		 904/**
905 * dwc3_prepare_one_trb - setup one TRB from one request
906 * @dep: endpoint for which this request is prepared
907 * @req: dwc3_request pointer
908 * @chain: should this TRB be chained to the next?
909 * @node: only for isochronous endpoints. First TRB needs different type.
910 */
911static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
912 struct dwc3_request *req, unsigned chain, unsigned node)
913{
914 struct dwc3_trb *trb;
915 unsigned length = req->request.length;
916 unsigned stream_id = req->request.stream_id;
917 unsigned short_not_ok = req->request.short_not_ok;
918 unsigned no_interrupt = req->request.no_interrupt;
919 dma_addr_t dma = req->request.dma;
920
921 trb = &dep->trb_pool[dep->trb_enqueue];
922
923 if (!req->trb) {
924 dwc3_gadget_move_started_request(req);
925 req->trb = trb;
926 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
927 dep->queued_requests++;
928 }
929
930 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
931 stream_id, short_not_ok, no_interrupt);
932}
933
361572b5
JY		 934/**
935 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
936 * @dep: The endpoint with the TRB ring
937 * @index: The index of the current TRB in the ring
938 *
939 * Returns the TRB prior to the one pointed to by the index. If the
940 * index is 0, we will wrap backwards, skip the link TRB, and return
941 * the one just before that.
942 */
943static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
944{
45438a0c 945 u8 tmp = index;
361572b5 946
45438a0c
FB		 947 if (!tmp)
948 tmp = DWC3_TRB_NUM - 1;
361572b5 949
45438a0c 950 return &dep->trb_pool[tmp - 1];
361572b5
JY		 951}
952
c4233573
FB		 953static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
954{
955 struct dwc3_trb *tmp;
f2694a93 956 struct dwc3 *dwc = dep->dwc;
32db3d94 957 u8 trbs_left;
c4233573
FB		 958
959 /*
960 * If enqueue & dequeue are equal than it is either full or empty.
961 *
962 * One way to know for sure is if the TRB right before us has HWO bit
963 * set or not. If it has, then we're definitely full and can't fit any
964 * more transfers in our ring.
965 */
966 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 967 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 968 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
969 "%s No TRBS left\n", dep->name))
361572b5 970 return 0;
c4233573
FB		 971
972 return DWC3_TRB_NUM - 1;
973 }
974
9d7aba77 975 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 976 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 977
9d7aba77
JY		 978 if (dep->trb_dequeue < dep->trb_enqueue)
979 trbs_left--;
980
32db3d94 981 return trbs_left;
c4233573
FB		 982}
983
5ee85d89 984static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 985 struct dwc3_request *req)
5ee85d89 986{
1f512119 987 struct scatterlist *sg = req->sg;
5ee85d89 988 struct scatterlist *s;
5ee85d89
FB		 989 int i;
990
1f512119 991 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 992 unsigned int length = req->request.length;
993 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
994 unsigned int rem = length % maxp;
5ee85d89
FB		 995 unsigned chain = true;
996
4bc48c97 997 if (sg_is_last(s))
5ee85d89
FB		 998 chain = false;
999
c6267a51
FB		 1000 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1001 struct dwc3 *dwc = dep->dwc;
1002 struct dwc3_trb *trb;
1003
1004 req->unaligned = true;
1005
1006 /* prepare normal TRB */
1007 dwc3_prepare_one_trb(dep, req, true, i);
1008
1009 /* Now prepare one extra TRB to align transfer size */
1010 trb = &dep->trb_pool[dep->trb_enqueue];
1011 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1012 maxp - rem, false, 0,
1013 req->request.stream_id,
1014 req->request.short_not_ok,
1015 req->request.no_interrupt);
1016 } else {
1017 dwc3_prepare_one_trb(dep, req, chain, i);
1018 }
5ee85d89 1019
7ae7df49 1020 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1021 break;
1022 }
1023}
1024
1025static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1026 struct dwc3_request *req)
5ee85d89 1027{
c6267a51
FB		 1028 unsigned int length = req->request.length;
1029 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1030 unsigned int rem = length % maxp;
1031
1032 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1033 struct dwc3 *dwc = dep->dwc;
1034 struct dwc3_trb *trb;
1035
1036 req->unaligned = true;
1037
1038 /* prepare normal TRB */
1039 dwc3_prepare_one_trb(dep, req, true, 0);
1040
1041 /* Now prepare one extra TRB to align transfer size */
1042 trb = &dep->trb_pool[dep->trb_enqueue];
1043 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1044 false, 0, req->request.stream_id,
1045 req->request.short_not_ok,
1046 req->request.no_interrupt);
d6e5a549
FB		 1047 } else if (req->request.zero && req->request.length &&
1048 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1049 struct dwc3 *dwc = dep->dwc;
1050 struct dwc3_trb *trb;
1051
1052 req->zero = true;
1053
1054 /* prepare normal TRB */
1055 dwc3_prepare_one_trb(dep, req, true, 0);
1056
1057 /* Now prepare one extra TRB to handle ZLP */
1058 trb = &dep->trb_pool[dep->trb_enqueue];
1059 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1060 false, 0, req->request.stream_id,
1061 req->request.short_not_ok,
1062 req->request.no_interrupt);
c6267a51
FB		 1063 } else {
1064 dwc3_prepare_one_trb(dep, req, false, 0);
1065 }
5ee85d89
FB		 1066}
1067
72246da4
FB		 1068/*
1069 * dwc3_prepare_trbs - setup TRBs from requests
1070 * @dep: endpoint for which requests are being prepared
72246da4 1071 *
1d046793
PZ		 1072 * The function goes through the requests list and sets up TRBs for the
1073 * transfers. The function returns once there are no more TRBs available or
1074 * it runs out of requests.
72246da4 1075 */
c4233573 1076static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1077{
68e823e2 1078 struct dwc3_request *req, *n;
72246da4
FB		 1079
1080 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1081
7ae7df49 1082 if (!dwc3_calc_trbs_left(dep))
89bc856e 1083 return;
72246da4 1084
d86c5a67
FB		 1085 /*
1086 * We can get in a situation where there's a request in the started list
1087 * but there weren't enough TRBs to fully kick it in the first time
1088 * around, so it has been waiting for more TRBs to be freed up.
1089 *
1090 * In that case, we should check if we have a request with pending_sgs
1091 * in the started list and prepare TRBs for that request first,
1092 * otherwise we will prepare TRBs completely out of order and that will
1093 * break things.
1094 */
1095 list_for_each_entry(req, &dep->started_list, list) {
1096 if (req->num_pending_sgs > 0)
1097 dwc3_prepare_one_trb_sg(dep, req);
1098
1099 if (!dwc3_calc_trbs_left(dep))
1100 return;
1101 }
1102
aa3342c8 1103 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1104 if (req->num_pending_sgs > 0)
7ae7df49 1105 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1106 else
7ae7df49 1107 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1108
7ae7df49 1109 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1110 return;
72246da4 1111 }
72246da4
FB		 1112}
1113
4fae2e3e 1114static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1115{
1116 struct dwc3_gadget_ep_cmd_params params;
1117 struct dwc3_request *req;
4fae2e3e 1118 int starting;
72246da4
FB		 1119 int ret;
1120 u32 cmd;
1121
4fae2e3e 1122 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1123
4fae2e3e
FB		 1124 dwc3_prepare_trbs(dep);
1125 req = next_request(&dep->started_list);
72246da4
FB		 1126 if (!req) {
1127 dep->flags |= DWC3_EP_PENDING_REQUEST;
1128 return 0;
1129 }
1130
1131 memset(&params, 0, sizeof(params));
72246da4 1132
4fae2e3e 1133 if (starting) {
1877d6c9
PA		 1134 params.param0 = upper_32_bits(req->trb_dma);
1135 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1136 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1138 } else {
b6b1c6db
FB		 1139 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1141 }
72246da4 1142
2cd4718d 1143 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1144 if (ret < 0) {
72246da4
FB		 1145 /*
1146 * FIXME we need to iterate over the list of requests
1147 * here and stop, unmap, free and del each of the linked
1d046793 1148 * requests instead of what we do now.
72246da4 1149 */
ce3fc8b3
JD		 1150 if (req->trb)
1151 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1152 dep->queued_requests--;
15b8d933 1153 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1154 return ret;
1155 }
1156
1157 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1158
4fae2e3e 1159 if (starting) {
2eb88016 1160 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1161 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1162 }
25b8ff68 1163
72246da4
FB		 1164 return 0;
1165}
1166
6cb2e4e3
FB		 1167static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1168{
1169 u32 reg;
1170
1171 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172 return DWC3_DSTS_SOFFN(reg);
1173}
1174
d6d6ec7b
PA		 1175static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176 struct dwc3_ep *dep, u32 cur_uf)
1177{
1178 u32 uf;
1179
aa3342c8 1180 if (list_empty(&dep->pending_list)) {
5eb30ced 1181 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1182 dep->name);
f4a53c55 1183 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1184 return;
1185 }
1186
af771d73
JY		 1187 /*
1188 * Schedule the first trb for one interval in the future or at
1189 * least 4 microframes.
1190 */
1191 uf = cur_uf + max_t(u32, 4, dep->interval);
d6d6ec7b 1192
4fae2e3e 1193 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1194}
1195
1196static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1197 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1198{
1199 u32 cur_uf, mask;
1200
1201 mask = ~(dep->interval - 1);
1202 cur_uf = event->parameters & mask;
1203
1204 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1205}
1206
72246da4
FB		 1207static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1208{
0fc9a1be
FB		 1209 struct dwc3 *dwc = dep->dwc;
1210 int ret;
1211
bb423984 1212 if (!dep->endpoint.desc) {
5eb30ced
FB		 1213 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1214 dep->name);
bb423984
FB		 1215 return -ESHUTDOWN;
1216 }
1217
1218 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1219 &req->request, req->dep->name)) {
5eb30ced
FB		 1220 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1221 dep->name, &req->request, req->dep->name);
bb423984
FB		 1222 return -EINVAL;
1223 }
1224
fc8bb91b
FB		 1225 pm_runtime_get(dwc->dev);
1226
72246da4
FB		 1227 req->request.actual = 0;
1228 req->request.status = -EINPROGRESS;
1229 req->direction = dep->direction;
1230 req->epnum = dep->number;
1231
fe84f522
FB		 1232 trace_dwc3_ep_queue(req);
1233
d64ff406
AB		 1234 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1235 dep->direction);
0fc9a1be
FB		 1236 if (ret)
1237 return ret;
1238
1f512119
FB		 1239 req->sg = req->request.sg;
1240 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1241
aa3342c8 1242 list_add_tail(&req->list, &dep->pending_list);
72246da4 1243
d889c23c
FB		 1244 /*
1245 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1246 * wait for a XferNotReady event so we will know what's the current
1247 * (micro-)frame number.
1248 *
1249 * Without this trick, we are very, very likely gonna get Bus Expiry
1250 * errors which will force us issue EndTransfer command.
1251 */
1252 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1253 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1254 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1255 dwc3_stop_active_transfer(dwc, dep->number, true);
1256 dep->flags = DWC3_EP_ENABLED;
1257 } else {
1258 u32 cur_uf;
1259
1260 cur_uf = __dwc3_gadget_get_frame(dwc);
1261 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1262 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1263 }
08a36b54
FB		 1264 }
1265 return 0;
a0925324 1266 }
72246da4 1267
594e121f
FB		 1268 if (!dwc3_calc_trbs_left(dep))
1269 return 0;
b997ada5 1270
08a36b54 1271 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1272 if (ret == -EBUSY)
1273 ret = 0;
1274
1275 return ret;
72246da4
FB		 1276}
1277
1278static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1279 gfp_t gfp_flags)
1280{
1281 struct dwc3_request *req = to_dwc3_request(request);
1282 struct dwc3_ep *dep = to_dwc3_ep(ep);
1283 struct dwc3 *dwc = dep->dwc;
1284
1285 unsigned long flags;
1286
1287 int ret;
1288
fdee4eba 1289 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1290 ret = __dwc3_gadget_ep_queue(dep, req);
1291 spin_unlock_irqrestore(&dwc->lock, flags);
1292
1293 return ret;
1294}
1295
1296static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1297 struct usb_request *request)
1298{
1299 struct dwc3_request *req = to_dwc3_request(request);
1300 struct dwc3_request *r = NULL;
1301
1302 struct dwc3_ep *dep = to_dwc3_ep(ep);
1303 struct dwc3 *dwc = dep->dwc;
1304
1305 unsigned long flags;
1306 int ret = 0;
1307
2c4cbe6e
FB		 1308 trace_dwc3_ep_dequeue(req);
1309
72246da4
FB		 1310 spin_lock_irqsave(&dwc->lock, flags);
1311
aa3342c8 1312 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1313 if (r == req)
1314 break;
1315 }
1316
1317 if (r != req) {
aa3342c8 1318 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1319 if (r == req)
1320 break;
1321 }
1322 if (r == req) {
1323 /* wait until it is processed */
b992e681 1324 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1325
1326 /*
1327 * If request was already started, this means we had to
1328 * stop the transfer. With that we also need to ignore
1329 * all TRBs used by the request, however TRBs can only
1330 * be modified after completion of END_TRANSFER
1331 * command. So what we do here is that we wait for
1332 * END_TRANSFER completion and only after that, we jump
1333 * over TRBs by clearing HWO and incrementing dequeue
1334 * pointer.
1335 *
1336 * Note that we have 2 possible types of transfers here:
1337 *
1338 * i) Linear buffer request
1339 * ii) SG-list based request
1340 *
1341 * SG-list based requests will have r->num_pending_sgs
1342 * set to a valid number (> 0). Linear requests,
1343 * normally use a single TRB.
1344 *
1345 * For each of these two cases, if r->unaligned flag is
1346 * set, one extra TRB has been used to align transfer
1347 * size to wMaxPacketSize.
1348 *
1349 * All of these cases need to be taken into
1350 * consideration so we don't mess up our TRB ring
1351 * pointers.
1352 */
1353 wait_event_lock_irq(dep->wait_end_transfer,
1354 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1355 dwc->lock);
1356
1357 if (!r->trb)
1358 goto out1;
1359
1360 if (r->num_pending_sgs) {
1361 struct dwc3_trb *trb;
1362 int i = 0;
1363
1364 for (i = 0; i < r->num_pending_sgs; i++) {
1365 trb = r->trb + i;
1366 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1367 dwc3_ep_inc_deq(dep);
1368 }
1369
d6e5a549 1370 if (r->unaligned || r->zero) {
cf3113d8
FB		 1371 trb = r->trb + r->num_pending_sgs + 1;
1372 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1373 dwc3_ep_inc_deq(dep);
1374 }
1375 } else {
1376 struct dwc3_trb *trb = r->trb;
1377
1378 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1379 dwc3_ep_inc_deq(dep);
1380
d6e5a549 1381 if (r->unaligned || r->zero) {
cf3113d8
FB		 1382 trb = r->trb + 1;
1383 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1384 dwc3_ep_inc_deq(dep);
1385 }
1386 }
e8d4e8be 1387 goto out1;
72246da4
FB		 1388 }
1389 dev_err(dwc->dev, "request %p was not queued to %s\n",
1390 request, ep->name);
1391 ret = -EINVAL;
1392 goto out0;
1393 }
1394
e8d4e8be 1395out1:
72246da4 1396 /* giveback the request */
cf3113d8 1397 dep->queued_requests--;
72246da4
FB		 1398 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1399
1400out0:
1401 spin_unlock_irqrestore(&dwc->lock, flags);
1402
1403 return ret;
1404}
1405
7a608559 1406int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1407{
1408 struct dwc3_gadget_ep_cmd_params params;
1409 struct dwc3 *dwc = dep->dwc;
1410 int ret;
1411
5ad02fb8
FB		 1412 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1413 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1414 return -EINVAL;
1415 }
1416
72246da4
FB		 1417 memset(&params, 0x00, sizeof(params));
1418
1419 if (value) {
69450c4d
FB		 1420 struct dwc3_trb *trb;
1421
1422 unsigned transfer_in_flight;
1423 unsigned started;
1424
ffb80fc6
FB		 1425 if (dep->flags & DWC3_EP_STALL)
1426 return 0;
1427
69450c4d
FB		 1428 if (dep->number > 1)
1429 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1430 else
1431 trb = &dwc->ep0_trb[dep->trb_enqueue];
1432
1433 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1434 started = !list_empty(&dep->started_list);
1435
1436 if (!protocol && ((dep->direction && transfer_in_flight) ||
1437 (!dep->direction && started))) {
7a608559
FB		 1438 return -EAGAIN;
1439 }
1440
2cd4718d
FB		 1441 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1442 &params);
72246da4 1443 if (ret)
3f89204b 1444 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1445 dep->name);
1446 else
1447 dep->flags |= DWC3_EP_STALL;
1448 } else {
ffb80fc6
FB		 1449 if (!(dep->flags & DWC3_EP_STALL))
1450 return 0;
2cd4718d 1451
50c763f8 1452 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1453 if (ret)
3f89204b 1454 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1455 dep->name);
1456 else
a535d81c 1457 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1458 }
5275455a 1459
72246da4
FB		 1460 return ret;
1461}
1462
1463static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1464{
1465 struct dwc3_ep *dep = to_dwc3_ep(ep);
1466 struct dwc3 *dwc = dep->dwc;
1467
1468 unsigned long flags;
1469
1470 int ret;
1471
1472 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1473 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1474 spin_unlock_irqrestore(&dwc->lock, flags);
1475
1476 return ret;
1477}
1478
1479static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1480{
1481 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1482 struct dwc3 *dwc = dep->dwc;
1483 unsigned long flags;
95aa4e8d 1484 int ret;
72246da4 1485
249a4569 1486 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1487 dep->flags |= DWC3_EP_WEDGE;
1488
08f0d966 1489 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1490 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1491 else
7a608559 1492 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1493 spin_unlock_irqrestore(&dwc->lock, flags);
1494
1495 return ret;
72246da4
FB		 1496}
1497
1498/* -------------------------------------------------------------------------- */
1499
1500static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1501 .bLength = USB_DT_ENDPOINT_SIZE,
1502 .bDescriptorType = USB_DT_ENDPOINT,
1503 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1504};
1505
1506static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1507 .enable = dwc3_gadget_ep0_enable,
1508 .disable = dwc3_gadget_ep0_disable,
1509 .alloc_request = dwc3_gadget_ep_alloc_request,
1510 .free_request = dwc3_gadget_ep_free_request,
1511 .queue = dwc3_gadget_ep0_queue,
1512 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1513 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1514 .set_wedge = dwc3_gadget_ep_set_wedge,
1515};
1516
1517static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1518 .enable = dwc3_gadget_ep_enable,
1519 .disable = dwc3_gadget_ep_disable,
1520 .alloc_request = dwc3_gadget_ep_alloc_request,
1521 .free_request = dwc3_gadget_ep_free_request,
1522 .queue = dwc3_gadget_ep_queue,
1523 .dequeue = dwc3_gadget_ep_dequeue,
1524 .set_halt = dwc3_gadget_ep_set_halt,
1525 .set_wedge = dwc3_gadget_ep_set_wedge,
1526};
1527
1528/* -------------------------------------------------------------------------- */
1529
1530static int dwc3_gadget_get_frame(struct usb_gadget *g)
1531{
1532 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1533
6cb2e4e3 1534 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1535}
1536
218ef7b6 1537static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1538{
d6011f6f 1539 int retries;
72246da4 1540
218ef7b6 1541 int ret;
72246da4
FB		 1542 u32 reg;
1543
72246da4
FB		 1544 u8 link_state;
1545 u8 speed;
1546
72246da4
FB		 1547 /*
1548 * According to the Databook Remote wakeup request should
1549 * be issued only when the device is in early suspend state.
1550 *
1551 * We can check that via USB Link State bits in DSTS register.
1552 */
1553 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1554
1555 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1556 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1557 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1558 return 0;
72246da4
FB		 1559
1560 link_state = DWC3_DSTS_USBLNKST(reg);
1561
1562 switch (link_state) {
1563 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1564 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1565 break;
1566 default:
218ef7b6 1567 return -EINVAL;
72246da4
FB		 1568 }
1569
8598bde7
FB		 1570 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1571 if (ret < 0) {
1572 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1573 return ret;
8598bde7 1574 }
72246da4 1575
802fde98
PZ		 1576 /* Recent versions do this automatically */
1577 if (dwc->revision < DWC3_REVISION_194A) {
1578 /* write zeroes to Link Change Request */
fcc023c7 1579 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1580 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1581 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1582 }
72246da4 1583
1d046793 1584 /* poll until Link State changes to ON */
d6011f6f 1585 retries = 20000;
72246da4 1586
d6011f6f 1587 while (retries--) {
72246da4
FB		 1588 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1589
1590 /* in HS, means ON */
1591 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1592 break;
1593 }
1594
1595 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1596 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1597 return -EINVAL;
72246da4
FB		 1598 }
1599
218ef7b6
FB		 1600 return 0;
1601}
1602
1603static int dwc3_gadget_wakeup(struct usb_gadget *g)
1604{
1605 struct dwc3 *dwc = gadget_to_dwc(g);
1606 unsigned long flags;
1607 int ret;
1608
1609 spin_lock_irqsave(&dwc->lock, flags);
1610 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1611 spin_unlock_irqrestore(&dwc->lock, flags);
1612
1613 return ret;
1614}
1615
1616static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1617 int is_selfpowered)
1618{
1619 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1620 unsigned long flags;
72246da4 1621
249a4569 1622 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1623 g->is_selfpowered = !!is_selfpowered;
249a4569 1624 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1625
1626 return 0;
1627}
1628
7b2a0368 1629static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1630{
1631 u32 reg;
61d58242 1632 u32 timeout = 500;
72246da4 1633
fc8bb91b
FB		 1634 if (pm_runtime_suspended(dwc->dev))
1635 return 0;
1636
72246da4 1637 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1638 if (is_on) {
802fde98
PZ		 1639 if (dwc->revision <= DWC3_REVISION_187A) {
1640 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1641 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1642 }
1643
1644 if (dwc->revision >= DWC3_REVISION_194A)
1645 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1646 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1647
1648 if (dwc->has_hibernation)
1649 reg |= DWC3_DCTL_KEEP_CONNECT;
1650
9fcb3bd8 1651 dwc->pullups_connected = true;
8db7ed15 1652 } else {
72246da4 1653 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1654
1655 if (dwc->has_hibernation && !suspend)
1656 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1657
9fcb3bd8 1658 dwc->pullups_connected = false;
8db7ed15 1659 }
72246da4
FB		 1660
1661 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1662
1663 do {
1664 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1665 reg &= DWC3_DSTS_DEVCTRLHLT;
1666 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1667
1668 if (!timeout)
1669 return -ETIMEDOUT;
72246da4 1670
6f17f74b 1671 return 0;
72246da4
FB		 1672}
1673
1674static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1675{
1676 struct dwc3 *dwc = gadget_to_dwc(g);
1677 unsigned long flags;
6f17f74b 1678 int ret;
72246da4
FB		 1679
1680 is_on = !!is_on;
1681
bb014736
BW		 1682 /*
1683 * Per databook, when we want to stop the gadget, if a control transfer
1684 * is still in process, complete it and get the core into setup phase.
1685 */
1686 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1687 reinit_completion(&dwc->ep0_in_setup);
1688
1689 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1690 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1691 if (ret == 0) {
1692 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1693 return -ETIMEDOUT;
1694 }
1695 }
1696
72246da4 1697 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1698 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1699 spin_unlock_irqrestore(&dwc->lock, flags);
1700
6f17f74b 1701 return ret;
72246da4
FB		 1702}
1703
8698e2ac
FB		 1704static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1705{
1706 u32 reg;
1707
1708 /* Enable all but Start and End of Frame IRQs */
1709 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1710 DWC3_DEVTEN_EVNTOVERFLOWEN |
1711 DWC3_DEVTEN_CMDCMPLTEN |
1712 DWC3_DEVTEN_ERRTICERREN |
1713 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1714 DWC3_DEVTEN_CONNECTDONEEN |
1715 DWC3_DEVTEN_USBRSTEN |
1716 DWC3_DEVTEN_DISCONNEVTEN);
1717
799e9dc8
FB		 1718 if (dwc->revision < DWC3_REVISION_250A)
1719 reg |= DWC3_DEVTEN_ULSTCNGEN;
1720
8698e2ac
FB		 1721 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1722}
1723
1724static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1725{
1726 /* mask all interrupts */
1727 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1728}
1729
1730static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1731static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1732
4e99472b
FB		 1733/**
1734 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1735 * dwc: pointer to our context structure
1736 *
1737 * The following looks like complex but it's actually very simple. In order to
1738 * calculate the number of packets we can burst at once on OUT transfers, we're
1739 * gonna use RxFIFO size.
1740 *
1741 * To calculate RxFIFO size we need two numbers:
1742 * MDWIDTH = size, in bits, of the internal memory bus
1743 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1744 *
1745 * Given these two numbers, the formula is simple:
1746 *
1747 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1748 *
1749 * 24 bytes is for 3x SETUP packets
1750 * 16 bytes is a clock domain crossing tolerance
1751 *
1752 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1753 */
1754static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1755{
1756 u32 ram2_depth;
1757 u32 mdwidth;
1758 u32 nump;
1759 u32 reg;
1760
1761 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1762 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1763
1764 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1765 nump = min_t(u32, nump, 16);
1766
1767 /* update NumP */
1768 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1769 reg &= ~DWC3_DCFG_NUMP_MASK;
1770 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1771 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1772}
1773
d7be2952 1774static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1775{
72246da4 1776 struct dwc3_ep *dep;
72246da4
FB		 1777 int ret = 0;
1778 u32 reg;
1779
cf40b86b
JY		 1780 /*
1781 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1782 * the core supports IMOD, disable it.
1783 */
1784 if (dwc->imod_interval) {
1785 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1786 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1787 } else if (dwc3_has_imod(dwc)) {
1788 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1789 }
1790
72246da4
FB		 1791 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1792 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1793
1794 /**
1795 * WORKAROUND: DWC3 revision < 2.20a have an issue
1796 * which would cause metastability state on Run/Stop
1797 * bit if we try to force the IP to USB2-only mode.
1798 *
1799 * Because of that, we cannot configure the IP to any
1800 * speed other than the SuperSpeed
1801 *
1802 * Refers to:
1803 *
1804 * STAR#9000525659: Clock Domain Crossing on DCTL in
1805 * USB 2.0 Mode
1806 */
f7e846f0 1807 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1808 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1809 } else {
1810 switch (dwc->maximum_speed) {
1811 case USB_SPEED_LOW:
2da9ad76 1812 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1813 break;
1814 case USB_SPEED_FULL:
9418ee15 1815 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1816 break;
1817 case USB_SPEED_HIGH:
2da9ad76 1818 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1819 break;
7580862b 1820 case USB_SPEED_SUPER_PLUS:
2da9ad76 1821 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1822 break;
f7e846f0 1823 default:
77966eb8
JY		 1824 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1825 dwc->maximum_speed);
1826 /* fall through */
1827 case USB_SPEED_SUPER:
1828 reg |= DWC3_DCFG_SUPERSPEED;
1829 break;
f7e846f0
FB		 1830 }
1831 }
72246da4
FB		 1832 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1833
2a58f9c1
FB		 1834 /*
1835 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1836 * field instead of letting dwc3 itself calculate that automatically.
1837 *
1838 * This way, we maximize the chances that we'll be able to get several
1839 * bursts of data without going through any sort of endpoint throttling.
1840 */
1841 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1842 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1843 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1844
4e99472b
FB		 1845 dwc3_gadget_setup_nump(dwc);
1846
72246da4
FB		 1847 /* Start with SuperSpeed Default */
1848 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1849
1850 dep = dwc->eps[0];
39ebb05c 1851 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1852 if (ret) {
1853 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1854 goto err0;
72246da4
FB		 1855 }
1856
1857 dep = dwc->eps[1];
39ebb05c 1858 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1859 if (ret) {
1860 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1861 goto err1;
72246da4
FB		 1862 }
1863
1864 /* begin to receive SETUP packets */
c7fcdeb2 1865 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1866 dwc3_ep0_out_start(dwc);
1867
8698e2ac
FB		 1868 dwc3_gadget_enable_irq(dwc);
1869
72246da4
FB		 1870 return 0;
1871
b0d7ffd4 1872err1:
d7be2952 1873 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1874
1875err0:
72246da4
FB		 1876 return ret;
1877}
1878
d7be2952
FB		 1879static int dwc3_gadget_start(struct usb_gadget *g,
1880 struct usb_gadget_driver *driver)
72246da4
FB		 1881{
1882 struct dwc3 *dwc = gadget_to_dwc(g);
1883 unsigned long flags;
d7be2952 1884 int ret = 0;
8698e2ac 1885 int irq;
72246da4 1886
9522def4 1887 irq = dwc->irq_gadget;
d7be2952
FB		 1888 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1889 IRQF_SHARED, "dwc3", dwc->ev_buf);
1890 if (ret) {
1891 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1892 irq, ret);
1893 goto err0;
1894 }
1895
72246da4 1896 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1897 if (dwc->gadget_driver) {
1898 dev_err(dwc->dev, "%s is already bound to %s\n",
1899 dwc->gadget.name,
1900 dwc->gadget_driver->driver.name);
1901 ret = -EBUSY;
1902 goto err1;
1903 }
1904
1905 dwc->gadget_driver = driver;
1906
fc8bb91b
FB		 1907 if (pm_runtime_active(dwc->dev))
1908 __dwc3_gadget_start(dwc);
1909
d7be2952
FB		 1910 spin_unlock_irqrestore(&dwc->lock, flags);
1911
1912 return 0;
1913
1914err1:
1915 spin_unlock_irqrestore(&dwc->lock, flags);
1916 free_irq(irq, dwc);
1917
1918err0:
1919 return ret;
1920}
72246da4 1921
d7be2952
FB		 1922static void __dwc3_gadget_stop(struct dwc3 *dwc)
1923{
8698e2ac 1924 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1925 __dwc3_gadget_ep_disable(dwc->eps[0]);
1926 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1927}
72246da4 1928
d7be2952
FB		 1929static int dwc3_gadget_stop(struct usb_gadget *g)
1930{
1931 struct dwc3 *dwc = gadget_to_dwc(g);
1932 unsigned long flags;
76a638f8 1933 int epnum;
72246da4 1934
d7be2952 1935 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1936
1937 if (pm_runtime_suspended(dwc->dev))
1938 goto out;
1939
d7be2952 1940 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1941
1942 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1943 struct dwc3_ep *dep = dwc->eps[epnum];
1944
1945 if (!dep)
1946 continue;
1947
1948 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1949 continue;
1950
1951 wait_event_lock_irq(dep->wait_end_transfer,
1952 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1953 dwc->lock);
1954 }
1955
1956out:
d7be2952 1957 dwc->gadget_driver = NULL;
72246da4
FB		 1958 spin_unlock_irqrestore(&dwc->lock, flags);
1959
3f308d17 1960 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1961
72246da4
FB		 1962 return 0;
1963}
802fde98 1964
72246da4
FB		 1965static const struct usb_gadget_ops dwc3_gadget_ops = {
1966 .get_frame = dwc3_gadget_get_frame,
1967 .wakeup = dwc3_gadget_wakeup,
1968 .set_selfpowered = dwc3_gadget_set_selfpowered,
1969 .pullup = dwc3_gadget_pullup,
1970 .udc_start = dwc3_gadget_start,
1971 .udc_stop = dwc3_gadget_stop,
1972};
1973
1974/* -------------------------------------------------------------------------- */
1975
f3bcfc7e 1976static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
72246da4
FB		 1977{
1978 struct dwc3_ep *dep;
47d3946e 1979 u8 epnum;
72246da4 1980
f3bcfc7e
BD		 1981 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1982
47d3946e
BD		 1983 for (epnum = 0; epnum < num; epnum++) {
1984 bool direction = epnum & 1;
72246da4 1985
72246da4 1986 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1987 if (!dep)
72246da4 1988 return -ENOMEM;
72246da4
FB		 1989
1990 dep->dwc = dwc;
1991 dep->number = epnum;
47d3946e 1992 dep->direction = direction;
2eb88016 1993 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1994 dwc->eps[epnum] = dep;
1995
1996 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
47d3946e 1997 direction ? "in" : "out");
6a1e3ef4 1998
72246da4 1999 dep->endpoint.name = dep->name;
39ebb05c
JY		 2000
2001 if (!(dep->number > 1)) {
2002 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2003 dep->endpoint.comp_desc = NULL;
2004 }
2005
74674cbf 2006 spin_lock_init(&dep->lock);
72246da4
FB		 2007
2008 if (epnum == 0 || epnum == 1) {
e117e742 2009 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2010 dep->endpoint.maxburst = 1;
72246da4
FB		 2011 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2012 if (!epnum)
2013 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2014 } else if (direction) {
2015 int mdwidth;
2016 int size;
2017 int ret;
2018 int num;
2019
2020 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2021 /* MDWIDTH is represented in bits, we need it in bytes */
2022 mdwidth /= 8;
2023
47d3946e 2024 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
28781789
FB		 2025 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2026
2027 /* FIFO Depth is in MDWDITH bytes. Multiply */
2028 size *= mdwidth;
2029
2030 num = size / 1024;
2031 if (num == 0)
2032 num = 1;
2033
2034 /*
2035 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2036 * internal overhead. We don't really know how these are used,
2037 * but documentation say it exists.
2038 */
2039 size -= mdwidth * (num + 1);
2040 size /= num;
2041
2042 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2043
2044 dep->endpoint.max_streams = 15;
2045 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2046 list_add_tail(&dep->endpoint.ep_list,
2047 &dwc->gadget.ep_list);
2048
2049 ret = dwc3_alloc_trb_pool(dep);
2050 if (ret)
2051 return ret;
72246da4
FB		 2052 } else {
2053 int ret;
2054
e117e742 2055 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2056 dep->endpoint.max_streams = 15;
72246da4
FB		 2057 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2058 list_add_tail(&dep->endpoint.ep_list,
2059 &dwc->gadget.ep_list);
2060
2061 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2062 if (ret)
72246da4 2063 return ret;
72246da4 2064 }
25b8ff68 2065
a474d3b7
RB		 2066 if (epnum == 0 || epnum == 1) {
2067 dep->endpoint.caps.type_control = true;
2068 } else {
2069 dep->endpoint.caps.type_iso = true;
2070 dep->endpoint.caps.type_bulk = true;
2071 dep->endpoint.caps.type_int = true;
2072 }
2073
47d3946e 2074 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2075 dep->endpoint.caps.dir_out = !direction;
2076
aa3342c8
FB		 2077 INIT_LIST_HEAD(&dep->pending_list);
2078 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2079 }
2080
2081 return 0;
2082}
2083
2084static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2085{
2086 struct dwc3_ep *dep;
2087 u8 epnum;
2088
2089 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2090 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2091 if (!dep)
2092 continue;
5bf8fae3
GC		 2093 /*
2094 * Physical endpoints 0 and 1 are special; they form the
2095 * bi-directional USB endpoint 0.
2096 *
2097 * For those two physical endpoints, we don't allocate a TRB
2098 * pool nor do we add them the endpoints list. Due to that, we
2099 * shouldn't do these two operations otherwise we would end up
2100 * with all sorts of bugs when removing dwc3.ko.
2101 */
2102 if (epnum != 0 && epnum != 1) {
2103 dwc3_free_trb_pool(dep);
72246da4 2104 list_del(&dep->endpoint.ep_list);
5bf8fae3 2105 }
72246da4
FB		 2106
2107 kfree(dep);
2108 }
2109}
2110
72246da4 2111/* -------------------------------------------------------------------------- */
e5caff68 2112
e5ba5ec8
PA		 2113static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2114 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2115 const struct dwc3_event_depevt *event, int status,
2116 int chain)
72246da4 2117{
72246da4
FB		 2118 unsigned int count;
2119 unsigned int s_pkt = 0;
d6d6ec7b 2120 unsigned int trb_status;
72246da4 2121
dc55c67e 2122 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2123
2124 if (req->trb == trb)
2125 dep->queued_requests--;
2126
2c4cbe6e
FB		 2127 trace_dwc3_complete_trb(dep, trb);
2128
e5b36ae2
FB		 2129 /*
2130 * If we're in the middle of series of chained TRBs and we
2131 * receive a short transfer along the way, DWC3 will skip
2132 * through all TRBs including the last TRB in the chain (the
2133 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2134 * bit and SW has to do it manually.
2135 *
2136 * We're going to do that here to avoid problems of HW trying
2137 * to use bogus TRBs for transfers.
2138 */
2139 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2140 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2141
c6267a51
FB		 2142 /*
2143 * If we're dealing with unaligned size OUT transfer, we will be left
2144 * with one TRB pending in the ring. We need to manually clear HWO bit
2145 * from that TRB.
2146 */
d6e5a549 2147 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
c6267a51
FB		 2148 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2149 return 1;
2150 }
2151
e5ba5ec8 2152 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2153 req->remaining += count;
e5ba5ec8 2154
35b2719e
FB		 2155 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2156 return 1;
2157
e5ba5ec8
PA		 2158 if (dep->direction) {
2159 if (count) {
2160 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2161 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2162 /*
2163 * If missed isoc occurred and there is
2164 * no request queued then issue END
2165 * TRANSFER, so that core generates
2166 * next xfernotready and we will issue
2167 * a fresh START TRANSFER.
2168 * If there are still queued request
2169 * then wait, do not issue either END
2170 * or UPDATE TRANSFER, just attach next
aa3342c8 2171 * request in pending_list during
e5ba5ec8
PA		 2172 * giveback.If any future queued request
2173 * is successfully transferred then we
2174 * will issue UPDATE TRANSFER for all
aa3342c8 2175 * request in the pending_list.
e5ba5ec8
PA		 2176 */
2177 dep->flags |= DWC3_EP_MISSED_ISOC;
2178 } else {
2179 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2180 dep->name);
2181 status = -ECONNRESET;
2182 }
2183 } else {
2184 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2185 }
2186 } else {
2187 if (count && (event->status & DEPEVT_STATUS_SHORT))
2188 s_pkt = 1;
2189 }
2190
7c705dfe 2191 if (s_pkt && !chain)
e5ba5ec8 2192 return 1;
f99f53f2 2193
e5ba5ec8
PA		 2194 if ((event->status & DEPEVT_STATUS_IOC) &&
2195 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2196 return 1;
f99f53f2 2197
e5ba5ec8
PA		 2198 return 0;
2199}
2200
2201static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2202 const struct dwc3_event_depevt *event, int status)
2203{
31162af4 2204 struct dwc3_request *req, *n;
e5ba5ec8 2205 struct dwc3_trb *trb;
d6e10bf2 2206 bool ioc = false;
e62c5bc5 2207 int ret = 0;
e5ba5ec8 2208
31162af4 2209 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2210 unsigned length;
e5b36ae2
FB		 2211 int chain;
2212
1f512119
FB		 2213 length = req->request.length;
2214 chain = req->num_pending_sgs > 0;
31162af4 2215 if (chain) {
1f512119 2216 struct scatterlist *sg = req->sg;
31162af4 2217 struct scatterlist *s;
1f512119 2218 unsigned int pending = req->num_pending_sgs;
31162af4 2219 unsigned int i;
c7de5734 2220
1f512119 2221 for_each_sg(sg, s, pending, i) {
31162af4 2222 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2223
7282c4ef
FB		 2224 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2225 break;
2226
1f512119
FB		 2227 req->sg = sg_next(s);
2228 req->num_pending_sgs--;
2229
31162af4
FB		 2230 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2231 event, status, chain);
1f512119
FB		 2232 if (ret)
2233 break;
31162af4
FB		 2234 }
2235 } else {
737f1ae2 2236 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2237 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2238 event, status, chain);
31162af4 2239 }
d115d705 2240
d6e5a549 2241 if (req->unaligned || req->zero) {
c6267a51
FB		 2242 trb = &dep->trb_pool[dep->trb_dequeue];
2243 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2244 event, status, false);
2245 req->unaligned = false;
d6e5a549 2246 req->zero = false;
c6267a51
FB		 2247 }
2248
e62c5bc5 2249 req->request.actual = length - req->remaining;
1f512119 2250
ff377ae4 2251 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2252 return __dwc3_gadget_kick_transfer(dep, 0);
2253
d115d705 2254 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2255
d6e10bf2
AB		 2256 if (ret) {
2257 if ((event->status & DEPEVT_STATUS_IOC) &&
2258 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2259 ioc = true;
72246da4 2260 break;
d6e10bf2 2261 }
31162af4 2262 }
72246da4 2263
4cb42217
FB		 2264 /*
2265 * Our endpoint might get disabled by another thread during
2266 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2267 * early on so DWC3_EP_BUSY flag gets cleared
2268 */
2269 if (!dep->endpoint.desc)
2270 return 1;
2271
cdc359dd 2272 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2273 list_empty(&dep->started_list)) {
2274 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2275 /*
2276 * If there is no entry in request list then do
2277 * not issue END TRANSFER now. Just set PENDING
2278 * flag, so that END TRANSFER is issued when an
2279 * entry is added into request list.
2280 */
2281 dep->flags = DWC3_EP_PENDING_REQUEST;
2282 } else {
b992e681 2283 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2284 dep->flags = DWC3_EP_ENABLED;
2285 }
7efea86c
PA		 2286 return 1;
2287 }
2288
d6e10bf2
AB		 2289 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2290 return 0;
2291
72246da4
FB		 2292 return 1;
2293}
2294
2295static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2296 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2297{
2298 unsigned status = 0;
2299 int clean_busy;
e18b7975
FB		 2300 u32 is_xfer_complete;
2301
2302 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2303
2304 if (event->status & DEPEVT_STATUS_BUSERR)
2305 status = -ECONNRESET;
2306
1d046793 2307 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2308 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2309 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2310 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2311
2312 /*
2313 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2314 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2315 */
2316 if (dwc->revision < DWC3_REVISION_183A) {
2317 u32 reg;
2318 int i;
2319
2320 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2321 dep = dwc->eps[i];
fae2b904
FB		 2322
2323 if (!(dep->flags & DWC3_EP_ENABLED))
2324 continue;
2325
aa3342c8 2326 if (!list_empty(&dep->started_list))
fae2b904
FB		 2327 return;
2328 }
2329
2330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2331 reg |= dwc->u1u2;
2332 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333
2334 dwc->u1u2 = 0;
2335 }
8a1a9c9e 2336
4cb42217
FB		 2337 /*
2338 * Our endpoint might get disabled by another thread during
2339 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2340 * early on so DWC3_EP_BUSY flag gets cleared
2341 */
2342 if (!dep->endpoint.desc)
2343 return;
2344
e6e709b7 2345 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2346 int ret;
2347
4fae2e3e 2348 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2349 if (!ret || ret == -EBUSY)
2350 return;
2351 }
72246da4
FB		 2352}
2353
72246da4
FB		 2354static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2355 const struct dwc3_event_depevt *event)
2356{
2357 struct dwc3_ep *dep;
2358 u8 epnum = event->endpoint_number;
76a638f8 2359 u8 cmd;
72246da4
FB		 2360
2361 dep = dwc->eps[epnum];
2362
d7fd41c6
JD		 2363 if (!(dep->flags & DWC3_EP_ENABLED)) {
2364 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2365 return;
2366
2367 /* Handle only EPCMDCMPLT when EP disabled */
2368 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2369 return;
2370 }
3336abb5 2371
72246da4
FB		 2372 if (epnum == 0 || epnum == 1) {
2373 dwc3_ep0_interrupt(dwc, event);
2374 return;
2375 }
2376
2377 switch (event->endpoint_event) {
2378 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2379 dep->resource_index = 0;
c2df85ca 2380
16e78db7 2381 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2382 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2383 return;
2384 }
2385
029d97ff 2386 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2387 break;
2388 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2389 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2390 break;
2391 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2392 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2393 dwc3_gadget_start_isoc(dwc, dep, event);
2394 } else {
2395 int ret;
2396
4fae2e3e 2397 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2398 if (!ret || ret == -EBUSY)
2399 return;
72246da4
FB		 2400 }
2401
879631aa
FB		 2402 break;
2403 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2404 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2405 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2406 dep->name);
2407 return;
2408 }
72246da4 2409 break;
72246da4 2410 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2411 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2412
2413 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2414 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2415 wake_up(&dep->wait_end_transfer);
2416 }
2417 break;
2418 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2419 break;
2420 }
2421}
2422
2423static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2424{
2425 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2426 spin_unlock(&dwc->lock);
2427 dwc->gadget_driver->disconnect(&dwc->gadget);
2428 spin_lock(&dwc->lock);
2429 }
2430}
2431
bc5ba2e0
FB		 2432static void dwc3_suspend_gadget(struct dwc3 *dwc)
2433{
73a30bfc 2434 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2435 spin_unlock(&dwc->lock);
2436 dwc->gadget_driver->suspend(&dwc->gadget);
2437 spin_lock(&dwc->lock);
2438 }
2439}
2440
2441static void dwc3_resume_gadget(struct dwc3 *dwc)
2442{
73a30bfc 2443 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2444 spin_unlock(&dwc->lock);
2445 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2446 spin_lock(&dwc->lock);
8e74475b
FB		 2447 }
2448}
2449
2450static void dwc3_reset_gadget(struct dwc3 *dwc)
2451{
2452 if (!dwc->gadget_driver)
2453 return;
2454
2455 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2456 spin_unlock(&dwc->lock);
2457 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2458 spin_lock(&dwc->lock);
2459 }
2460}
2461
b992e681 2462static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2463{
2464 struct dwc3_ep *dep;
2465 struct dwc3_gadget_ep_cmd_params params;
2466 u32 cmd;
2467 int ret;
2468
2469 dep = dwc->eps[epnum];
2470
76a638f8
BW		 2471 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2472 !dep->resource_index)
3daf74d7
PA		 2473 return;
2474
57911504
PA		 2475 /*
2476 * NOTICE: We are violating what the Databook says about the
2477 * EndTransfer command. Ideally we would _always_ wait for the
2478 * EndTransfer Command Completion IRQ, but that's causing too
2479 * much trouble synchronizing between us and gadget driver.
2480 *
2481 * We have discussed this with the IP Provider and it was
2482 * suggested to giveback all requests here, but give HW some
2483 * extra time to synchronize with the interconnect. We're using
dc93b41a 2484 * an arbitrary 100us delay for that.
57911504
PA		 2485 *
2486 * Note also that a similar handling was tested by Synopsys
2487 * (thanks a lot Paul) and nothing bad has come out of it.
2488 * In short, what we're doing is:
2489 *
2490 * - Issue EndTransfer WITH CMDIOC bit set
2491 * - Wait 100us
06281d46
JY		 2492 *
2493 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2494 * supports a mode to work around the above limitation. The
2495 * software can poll the CMDACT bit in the DEPCMD register
2496 * after issuing a EndTransfer command. This mode is enabled
2497 * by writing GUCTL2[14]. This polling is already done in the
2498 * dwc3_send_gadget_ep_cmd() function so if the mode is
2499 * enabled, the EndTransfer command will have completed upon
2500 * returning from this function and we don't need to delay for
2501 * 100us.
2502 *
2503 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2504 */
2505
3daf74d7 2506 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2507 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2508 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2509 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2510 memset(&params, 0, sizeof(params));
2cd4718d 2511 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2512 WARN_ON_ONCE(ret);
b4996a86 2513 dep->resource_index = 0;
041d81f4 2514 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2515
76a638f8
BW		 2516 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2517 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2518 udelay(100);
76a638f8 2519 }
72246da4
FB		 2520}
2521
72246da4
FB		 2522static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2523{
2524 u32 epnum;
2525
2526 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2527 struct dwc3_ep *dep;
72246da4
FB		 2528 int ret;
2529
2530 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2531 if (!dep)
2532 continue;
72246da4
FB		 2533
2534 if (!(dep->flags & DWC3_EP_STALL))
2535 continue;
2536
2537 dep->flags &= ~DWC3_EP_STALL;
2538
50c763f8 2539 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2540 WARN_ON_ONCE(ret);
2541 }
2542}
2543
2544static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2545{
c4430a26
FB		 2546 int reg;
2547
72246da4
FB		 2548 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2549 reg &= ~DWC3_DCTL_INITU1ENA;
2550 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2551
2552 reg &= ~DWC3_DCTL_INITU2ENA;
2553 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2554
72246da4
FB		 2555 dwc3_disconnect_gadget(dwc);
2556
2557 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2558 dwc->setup_packet_pending = false;
06a374ed 2559 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2560
2561 dwc->connected = false;
72246da4
FB		 2562}
2563
72246da4
FB		 2564static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2565{
2566 u32 reg;
2567
fc8bb91b
FB		 2568 dwc->connected = true;
2569
df62df56
FB		 2570 /*
2571 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2572 * would cause a missing Disconnect Event if there's a
2573 * pending Setup Packet in the FIFO.
2574 *
2575 * There's no suggested workaround on the official Bug
2576 * report, which states that "unless the driver/application
2577 * is doing any special handling of a disconnect event,
2578 * there is no functional issue".
2579 *
2580 * Unfortunately, it turns out that we _do_ some special
2581 * handling of a disconnect event, namely complete all
2582 * pending transfers, notify gadget driver of the
2583 * disconnection, and so on.
2584 *
2585 * Our suggested workaround is to follow the Disconnect
2586 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2587 * flag. Such flag gets set whenever we have a SETUP_PENDING
2588 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2589 * same endpoint.
2590 *
2591 * Refers to:
2592 *
2593 * STAR#9000466709: RTL: Device : Disconnect event not
2594 * generated if setup packet pending in FIFO
2595 */
2596 if (dwc->revision < DWC3_REVISION_188A) {
2597 if (dwc->setup_packet_pending)
2598 dwc3_gadget_disconnect_interrupt(dwc);
2599 }
2600
8e74475b 2601 dwc3_reset_gadget(dwc);
72246da4
FB		 2602
2603 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2604 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2605 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2606 dwc->test_mode = false;
72246da4
FB		 2607 dwc3_clear_stall_all_ep(dwc);
2608
2609 /* Reset device address to zero */
2610 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2611 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2612 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2613}
2614
72246da4
FB		 2615static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2616{
72246da4
FB		 2617 struct dwc3_ep *dep;
2618 int ret;
2619 u32 reg;
2620 u8 speed;
2621
72246da4
FB		 2622 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2623 speed = reg & DWC3_DSTS_CONNECTSPD;
2624 dwc->speed = speed;
2625
5fb6fdaf
JY		 2626 /*
2627 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2628 * each time on Connect Done.
2629 *
2630 * Currently we always use the reset value. If any platform
2631 * wants to set this to a different value, we need to add a
2632 * setting and update GCTL.RAMCLKSEL here.
2633 */
72246da4
FB		 2634
2635 switch (speed) {
2da9ad76 2636 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2637 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2638 dwc->gadget.ep0->maxpacket = 512;
2639 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2640 break;
2da9ad76 2641 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2642 /*
2643 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2644 * would cause a missing USB3 Reset event.
2645 *
2646 * In such situations, we should force a USB3 Reset
2647 * event by calling our dwc3_gadget_reset_interrupt()
2648 * routine.
2649 *
2650 * Refers to:
2651 *
2652 * STAR#9000483510: RTL: SS : USB3 reset event may
2653 * not be generated always when the link enters poll
2654 */
2655 if (dwc->revision < DWC3_REVISION_190A)
2656 dwc3_gadget_reset_interrupt(dwc);
2657
72246da4
FB		 2658 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2659 dwc->gadget.ep0->maxpacket = 512;
2660 dwc->gadget.speed = USB_SPEED_SUPER;
2661 break;
2da9ad76 2662 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2663 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2664 dwc->gadget.ep0->maxpacket = 64;
2665 dwc->gadget.speed = USB_SPEED_HIGH;
2666 break;
9418ee15 2667 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2668 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2669 dwc->gadget.ep0->maxpacket = 64;
2670 dwc->gadget.speed = USB_SPEED_FULL;
2671 break;
2da9ad76 2672 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2673 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2674 dwc->gadget.ep0->maxpacket = 8;
2675 dwc->gadget.speed = USB_SPEED_LOW;
2676 break;
2677 }
2678
2b758350
PA		 2679 /* Enable USB2 LPM Capability */
2680
ee5cd41c 2681 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2682 (speed != DWC3_DSTS_SUPERSPEED) &&
2683 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2684 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2685 reg |= DWC3_DCFG_LPM_CAP;
2686 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2687
2688 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2689 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2690
460d098c 2691 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2692
80caf7d2
HR		 2693 /*
2694 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2695 * DCFG.LPMCap is set, core responses with an ACK and the
2696 * BESL value in the LPM token is less than or equal to LPM
2697 * NYET threshold.
2698 */
2699 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2700 && dwc->has_lpm_erratum,
9165dabb 2701 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2702
2703 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2704 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2705
356363bf
FB		 2706 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2707 } else {
2708 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2709 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2711 }
2712
72246da4 2713 dep = dwc->eps[0];
39ebb05c 2714 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2715 if (ret) {
2716 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2717 return;
2718 }
2719
2720 dep = dwc->eps[1];
39ebb05c 2721 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2722 if (ret) {
2723 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2724 return;
2725 }
2726
2727 /*
2728 * Configure PHY via GUSB3PIPECTLn if required.
2729 *
2730 * Update GTXFIFOSIZn
2731 *
2732 * In both cases reset values should be sufficient.
2733 */
2734}
2735
2736static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2737{
72246da4
FB		 2738 /*
2739 * TODO take core out of low power mode when that's
2740 * implemented.
2741 */
2742
ad14d4e0
JL		 2743 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2744 spin_unlock(&dwc->lock);
2745 dwc->gadget_driver->resume(&dwc->gadget);
2746 spin_lock(&dwc->lock);
2747 }
72246da4
FB		 2748}
2749
2750static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2751 unsigned int evtinfo)
2752{
fae2b904 2753 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2754 unsigned int pwropt;
2755
2756 /*
2757 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2758 * Hibernation mode enabled which would show up when device detects
2759 * host-initiated U3 exit.
2760 *
2761 * In that case, device will generate a Link State Change Interrupt
2762 * from U3 to RESUME which is only necessary if Hibernation is
2763 * configured in.
2764 *
2765 * There are no functional changes due to such spurious event and we
2766 * just need to ignore it.
2767 *
2768 * Refers to:
2769 *
2770 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2771 * operational mode
2772 */
2773 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2774 if ((dwc->revision < DWC3_REVISION_250A) &&
2775 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2776 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2777 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2778 return;
2779 }
2780 }
fae2b904
FB		 2781
2782 /*
2783 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2784 * on the link partner, the USB session might do multiple entry/exit
2785 * of low power states before a transfer takes place.
2786 *
2787 * Due to this problem, we might experience lower throughput. The
2788 * suggested workaround is to disable DCTL[12:9] bits if we're
2789 * transitioning from U1/U2 to U0 and enable those bits again
2790 * after a transfer completes and there are no pending transfers
2791 * on any of the enabled endpoints.
2792 *
2793 * This is the first half of that workaround.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2798 * core send LGO_Ux entering U0
2799 */
2800 if (dwc->revision < DWC3_REVISION_183A) {
2801 if (next == DWC3_LINK_STATE_U0) {
2802 u32 u1u2;
2803 u32 reg;
2804
2805 switch (dwc->link_state) {
2806 case DWC3_LINK_STATE_U1:
2807 case DWC3_LINK_STATE_U2:
2808 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2809 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2810 | DWC3_DCTL_ACCEPTU2ENA
2811 | DWC3_DCTL_INITU1ENA
2812 | DWC3_DCTL_ACCEPTU1ENA);
2813
2814 if (!dwc->u1u2)
2815 dwc->u1u2 = reg & u1u2;
2816
2817 reg &= ~u1u2;
2818
2819 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2820 break;
2821 default:
2822 /* do nothing */
2823 break;
2824 }
2825 }
2826 }
2827
bc5ba2e0
FB		 2828 switch (next) {
2829 case DWC3_LINK_STATE_U1:
2830 if (dwc->speed == USB_SPEED_SUPER)
2831 dwc3_suspend_gadget(dwc);
2832 break;
2833 case DWC3_LINK_STATE_U2:
2834 case DWC3_LINK_STATE_U3:
2835 dwc3_suspend_gadget(dwc);
2836 break;
2837 case DWC3_LINK_STATE_RESUME:
2838 dwc3_resume_gadget(dwc);
2839 break;
2840 default:
2841 /* do nothing */
2842 break;
2843 }
2844
e57ebc1d 2845 dwc->link_state = next;
72246da4
FB		 2846}
2847
72704f87
BW		 2848static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2849 unsigned int evtinfo)
2850{
2851 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2852
2853 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2854 dwc3_suspend_gadget(dwc);
2855
2856 dwc->link_state = next;
2857}
2858
e1dadd3b
FB		 2859static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2860 unsigned int evtinfo)
2861{
2862 unsigned int is_ss = evtinfo & BIT(4);
2863
2864 /**
2865 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2866 * have a known issue which can cause USB CV TD.9.23 to fail
2867 * randomly.
2868 *
2869 * Because of this issue, core could generate bogus hibernation
2870 * events which SW needs to ignore.
2871 *
2872 * Refers to:
2873 *
2874 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2875 * Device Fallback from SuperSpeed
2876 */
2877 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2878 return;
2879
2880 /* enter hibernation here */
2881}
2882
72246da4
FB		 2883static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2884 const struct dwc3_event_devt *event)
2885{
2886 switch (event->type) {
2887 case DWC3_DEVICE_EVENT_DISCONNECT:
2888 dwc3_gadget_disconnect_interrupt(dwc);
2889 break;
2890 case DWC3_DEVICE_EVENT_RESET:
2891 dwc3_gadget_reset_interrupt(dwc);
2892 break;
2893 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2894 dwc3_gadget_conndone_interrupt(dwc);
2895 break;
2896 case DWC3_DEVICE_EVENT_WAKEUP:
2897 dwc3_gadget_wakeup_interrupt(dwc);
2898 break;
e1dadd3b
FB		 2899 case DWC3_DEVICE_EVENT_HIBER_REQ:
2900 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2901 "unexpected hibernation event\n"))
2902 break;
2903
2904 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2905 break;
72246da4
FB		 2906 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2907 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2908 break;
2909 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2910 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2911 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2912 /*
2913 * Ignore suspend event until the gadget enters into
2914 * USB_STATE_CONFIGURED state.
2915 */
2916 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2917 dwc3_gadget_suspend_interrupt(dwc,
2918 event->event_info);
2919 }
72246da4
FB		 2920 break;
2921 case DWC3_DEVICE_EVENT_SOF:
72246da4 2922 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2923 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2924 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2925 break;
2926 default:
e9f2aa87 2927 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2928 }
2929}
2930
2931static void dwc3_process_event_entry(struct dwc3 *dwc,
2932 const union dwc3_event *event)
2933{
43c96be1 2934 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2935
72246da4
FB		 2936 /* Endpoint IRQ, handle it and return early */
2937 if (event->type.is_devspec == 0) {
2938 /* depevt */
2939 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2940 }
2941
2942 switch (event->type.type) {
2943 case DWC3_EVENT_TYPE_DEV:
2944 dwc3_gadget_interrupt(dwc, &event->devt);
2945 break;
2946 /* REVISIT what to do with Carkit and I2C events ? */
2947 default:
2948 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2949 }
2950}
2951
dea520a4 2952static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2953{
dea520a4 2954 struct dwc3 *dwc = evt->dwc;
b15a762f 2955 irqreturn_t ret = IRQ_NONE;
f42f2447 2956 int left;
e8adfc30 2957 u32 reg;
b15a762f 2958
f42f2447 2959 left = evt->count;
b15a762f 2960
f42f2447
FB		 2961 if (!(evt->flags & DWC3_EVENT_PENDING))
2962 return IRQ_NONE;
b15a762f 2963
f42f2447
FB		 2964 while (left > 0) {
2965 union dwc3_event event;
b15a762f 2966
ebbb2d59 2967 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2968
f42f2447 2969 dwc3_process_event_entry(dwc, &event);
b15a762f 2970
f42f2447
FB		 2971 /*
2972 * FIXME we wrap around correctly to the next entry as
2973 * almost all entries are 4 bytes in size. There is one
2974 * entry which has 12 bytes which is a regular entry
2975 * followed by 8 bytes data. ATM I don't know how
2976 * things are organized if we get next to the a
2977 * boundary so I worry about that once we try to handle
2978 * that.
2979 */
caefe6c7 2980 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2981 left -= 4;
f42f2447 2982 }
b15a762f 2983
f42f2447
FB		 2984 evt->count = 0;
2985 evt->flags &= ~DWC3_EVENT_PENDING;
2986 ret = IRQ_HANDLED;
b15a762f 2987
f42f2447 2988 /* Unmask interrupt */
660e9bde 2989 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2990 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2991 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2992
cf40b86b
JY		 2993 if (dwc->imod_interval) {
2994 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2995 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2996 }
2997
f42f2447
FB		 2998 return ret;
2999}
e8adfc30 3000
dea520a4 3001static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3002{
dea520a4
FB		 3003 struct dwc3_event_buffer *evt = _evt;
3004 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3005 unsigned long flags;
f42f2447 3006 irqreturn_t ret = IRQ_NONE;
f42f2447 3007
e5f68b4a 3008 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3009 ret = dwc3_process_event_buf(evt);
e5f68b4a 3010 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3011
3012 return ret;
3013}
3014
dea520a4 3015static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3016{
dea520a4 3017 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3018 u32 amount;
72246da4 3019 u32 count;
e8adfc30 3020 u32 reg;
72246da4 3021
fc8bb91b
FB		 3022 if (pm_runtime_suspended(dwc->dev)) {
3023 pm_runtime_get(dwc->dev);
3024 disable_irq_nosync(dwc->irq_gadget);
3025 dwc->pending_events = true;
3026 return IRQ_HANDLED;
3027 }
3028
660e9bde 3029 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3030 count &= DWC3_GEVNTCOUNT_MASK;
3031 if (!count)
3032 return IRQ_NONE;
3033
b15a762f
FB		 3034 evt->count = count;
3035 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3036
e8adfc30 3037 /* Mask interrupt */
660e9bde 3038 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3039 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3040 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3041
ebbb2d59
JY		 3042 amount = min(count, evt->length - evt->lpos);
3043 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3044
3045 if (amount < count)
3046 memcpy(evt->cache, evt->buf, count - amount);
3047
65aca320
JY		 3048 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3049
b15a762f 3050 return IRQ_WAKE_THREAD;
72246da4
FB		 3051}
3052
dea520a4 3053static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3054{
dea520a4 3055 struct dwc3_event_buffer *evt = _evt;
72246da4 3056
dea520a4 3057 return dwc3_check_event_buf(evt);
72246da4
FB		 3058}
3059
6db3812e
FB		 3060static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3061{
3062 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3063 int irq;
3064
3065 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3066 if (irq > 0)
3067 goto out;
3068
3069 if (irq == -EPROBE_DEFER)
3070 goto out;
3071
3072 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3073 if (irq > 0)
3074 goto out;
3075
3076 if (irq == -EPROBE_DEFER)
3077 goto out;
3078
3079 irq = platform_get_irq(dwc3_pdev, 0);
3080 if (irq > 0)
3081 goto out;
3082
3083 if (irq != -EPROBE_DEFER)
3084 dev_err(dwc->dev, "missing peripheral IRQ\n");
3085
3086 if (!irq)
3087 irq = -EINVAL;
3088
3089out:
3090 return irq;
3091}
3092
72246da4
FB		 3093/**
3094 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3095 * @dwc: pointer to our controller context structure
72246da4
FB		 3096 *
3097 * Returns 0 on success otherwise negative errno.
3098 */
41ac7b3a 3099int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3100{
6db3812e
FB		 3101 int ret;
3102 int irq;
9522def4 3103
6db3812e
FB		 3104 irq = dwc3_gadget_get_irq(dwc);
3105 if (irq < 0) {
3106 ret = irq;
3107 goto err0;
9522def4
RQ		 3108 }
3109
3110 dwc->irq_gadget = irq;
72246da4 3111
d64ff406
AB		 3112 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3113 sizeof(*dwc->ep0_trb) * 2,
3114 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3115 if (!dwc->ep0_trb) {
3116 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3117 ret = -ENOMEM;
7d5e650a 3118 goto err0;
72246da4
FB		 3119 }
3120
4199c5f8 3121 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
72246da4 3122 if (!dwc->setup_buf) {
72246da4 3123 ret = -ENOMEM;
7d5e650a 3124 goto err1;
72246da4
FB		 3125 }
3126
905dc04e
FB		 3127 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3128 &dwc->bounce_addr, GFP_KERNEL);
3129 if (!dwc->bounce) {
3130 ret = -ENOMEM;
d6e5a549 3131 goto err2;
905dc04e
FB		 3132 }
3133
bb014736
BW		 3134 init_completion(&dwc->ep0_in_setup);
3135
72246da4 3136 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3137 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3138 dwc->gadget.sg_supported = true;
72246da4 3139 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3140 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3141
b9e51b2b
BM		 3142 /*
3143 * FIXME We might be setting max_speed to <SUPER, however versions
3144 * <2.20a of dwc3 have an issue with metastability (documented
3145 * elsewhere in this driver) which tells us we can't set max speed to
3146 * anything lower than SUPER.
3147 *
3148 * Because gadget.max_speed is only used by composite.c and function
3149 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3150 * to happen so we avoid sending SuperSpeed Capability descriptor
3151 * together with our BOS descriptor as that could confuse host into
3152 * thinking we can handle super speed.
3153 *
3154 * Note that, in fact, we won't even support GetBOS requests when speed
3155 * is less than super speed because we don't have means, yet, to tell
3156 * composite.c that we are USB 2.0 + LPM ECN.
3157 */
3158 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3159 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3160 dwc->revision);
3161
3162 dwc->gadget.max_speed = dwc->maximum_speed;
3163
72246da4
FB		 3164 /*
3165 * REVISIT: Here we should clear all pending IRQs to be
3166 * sure we're starting from a well known location.
3167 */
3168
f3bcfc7e 3169 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3170 if (ret)
d6e5a549 3171 goto err3;
72246da4 3172
72246da4
FB		 3173 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3174 if (ret) {
3175 dev_err(dwc->dev, "failed to register udc\n");
d6e5a549 3176 goto err4;
72246da4
FB		 3177 }
3178
3179 return 0;
3180
7d5e650a 3181err4:
d6e5a549 3182 dwc3_gadget_free_endpoints(dwc);
04c03d10 3183
7d5e650a 3184err3:
d6e5a549
FB		 3185 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3186 dwc->bounce_addr);
5812b1c2 3187
7d5e650a 3188err2:
0fc9a1be 3189 kfree(dwc->setup_buf);
72246da4 3190
7d5e650a 3191err1:
d64ff406 3192 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3193 dwc->ep0_trb, dwc->ep0_trb_addr);
3194
72246da4
FB		 3195err0:
3196 return ret;
3197}
3198
7415f17c
FB		 3199/* -------------------------------------------------------------------------- */
3200
72246da4
FB		 3201void dwc3_gadget_exit(struct dwc3 *dwc)
3202{
72246da4 3203 usb_del_gadget_udc(&dwc->gadget);
72246da4 3204 dwc3_gadget_free_endpoints(dwc);
905dc04e 3205 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
d6e5a549 3206 dwc->bounce_addr);
0fc9a1be 3207 kfree(dwc->setup_buf);
d64ff406 3208 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
d6e5a549 3209 dwc->ep0_trb, dwc->ep0_trb_addr);
72246da4 3210}
7415f17c 3211
0b0231aa 3212int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3213{
9772b47a
RQ		 3214 if (!dwc->gadget_driver)
3215 return 0;
3216
1551e35e 3217 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3218 dwc3_disconnect_gadget(dwc);
3219 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3220
3221 return 0;
3222}
3223
3224int dwc3_gadget_resume(struct dwc3 *dwc)
3225{
7415f17c
FB		 3226 int ret;
3227
9772b47a
RQ		 3228 if (!dwc->gadget_driver)
3229 return 0;
3230
9f8a67b6
FB		 3231 ret = __dwc3_gadget_start(dwc);
3232 if (ret < 0)
7415f17c
FB		 3233 goto err0;
3234
9f8a67b6
FB		 3235 ret = dwc3_gadget_run_stop(dwc, true, false);
3236 if (ret < 0)
7415f17c
FB		 3237 goto err1;
3238
7415f17c
FB		 3239 return 0;
3240
3241err1:
9f8a67b6 3242 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3243
3244err0:
3245 return ret;
3246}
fc8bb91b
FB		 3247
3248void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3249{
3250 if (dwc->pending_events) {
3251 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3252 dwc->pending_events = false;
3253 enable_irq(dwc->irq_gadget);
3254 }
3255}
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