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[mirror_ubuntu-artful-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
de288e36 174 unsigned int unmap_after_complete = false;
72246da4 175
737f1ae2 176 req->started = false;
72246da4 177 list_del(&req->list);
eeb720fb 178 req->trb = NULL;
e62c5bc5 179 req->remaining = 0;
72246da4
FB		 180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
de288e36
JD		 184 /*
185 * NOTICE we don't want to unmap before calling ->complete() if we're
186 * dealing with a bounced ep0 request. If we unmap it here, we would end
187 * up overwritting the contents of req->buf and this could confuse the
188 * gadget driver.
189 */
190 if (dwc->ep0_bounced && dep->number <= 1) {
0416e494 191 dwc->ep0_bounced = false;
de288e36
JD		 192 unmap_after_complete = true;
193 } else {
194 usb_gadget_unmap_request_by_dev(dwc->sysdev,
195 &req->request, req->direction);
196 }
72246da4 197
2c4cbe6e 198 trace_dwc3_gadget_giveback(req);
72246da4
FB		 199
200 spin_unlock(&dwc->lock);
304f7e5e 201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 202 spin_lock(&dwc->lock);
fc8bb91b 203
de288e36
JD		 204 if (unmap_after_complete)
205 usb_gadget_unmap_request_by_dev(dwc->sysdev,
206 &req->request, req->direction);
207
fc8bb91b
FB		 208 if (dep->number > 1)
209 pm_runtime_put(dwc->dev);
72246da4
FB		 210}
211
3ece0ec4 212int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 213{
214 u32 timeout = 500;
71f7e702 215 int status = 0;
0fe886cd 216 int ret = 0;
b09bb642
FB		 217 u32 reg;
218
219 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
220 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
221
222 do {
223 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
224 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 225 status = DWC3_DGCMD_STATUS(reg);
226 if (status)
0fe886cd
FB		 227 ret = -EINVAL;
228 break;
b09bb642 229 }
e3aee486 230 } while (--timeout);
0fe886cd
FB		 231
232 if (!timeout) {
0fe886cd 233 ret = -ETIMEDOUT;
71f7e702 234 status = -ETIMEDOUT;
0fe886cd
FB		 235 }
236
71f7e702
FB		 237 trace_dwc3_gadget_generic_cmd(cmd, param, status);
238
0fe886cd 239 return ret;
b09bb642
FB		 240}
241
c36d8e94
FB		 242static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
243
2cd4718d
FB		 244int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
245 struct dwc3_gadget_ep_cmd_params *params)
72246da4 246{
8897a761 247 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 248 struct dwc3 *dwc = dep->dwc;
61d58242 249 u32 timeout = 500;
72246da4
FB		 250 u32 reg;
251
0933df15 252 int cmd_status = 0;
2b0f11df 253 int susphy = false;
c0ca324d 254 int ret = -EINVAL;
72246da4 255
2b0f11df
FB		 256 /*
257 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
258 * we're issuing an endpoint command, we must check if
259 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
260 *
261 * We will also set SUSPHY bit to what it was before returning as stated
262 * by the same section on Synopsys databook.
263 */
ab2a92e7
FB		 264 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
265 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
266 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
267 susphy = true;
268 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
269 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
270 }
2b0f11df
FB		 271 }
272
5999914f 273 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 274 int needs_wakeup;
275
276 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
277 dwc->link_state == DWC3_LINK_STATE_U2 ||
278 dwc->link_state == DWC3_LINK_STATE_U3);
279
280 if (unlikely(needs_wakeup)) {
281 ret = __dwc3_gadget_wakeup(dwc);
282 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
283 ret);
284 }
285 }
286
2eb88016
FB		 287 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
288 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
289 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 290
8897a761
FB		 291 /*
292 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
293 * not relying on XferNotReady, we can make use of a special "No
294 * Response Update Transfer" command where we should clear both CmdAct
295 * and CmdIOC bits.
296 *
297 * With this, we don't need to wait for command completion and can
298 * straight away issue further commands to the endpoint.
299 *
300 * NOTICE: We're making an assumption that control endpoints will never
301 * make use of Update Transfer command. This is a safe assumption
302 * because we can never have more than one request at a time with
303 * Control Endpoints. If anybody changes that assumption, this chunk
304 * needs to be updated accordingly.
305 */
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
307 !usb_endpoint_xfer_isoc(desc))
308 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
309 else
310 cmd |= DWC3_DEPCMD_CMDACT;
311
312 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 313 do {
2eb88016 314 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 315 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 316 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 317
7b9cc7a2
KL		 318 switch (cmd_status) {
319 case 0:
320 ret = 0;
321 break;
322 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 323 ret = -EINVAL;
c0ca324d 324 break;
7b9cc7a2
KL		 325 case DEPEVT_TRANSFER_BUS_EXPIRY:
326 /*
327 * SW issues START TRANSFER command to
328 * isochronous ep with future frame interval. If
329 * future interval time has already passed when
330 * core receives the command, it will respond
331 * with an error status of 'Bus Expiry'.
332 *
333 * Instead of always returning -EINVAL, let's
334 * give a hint to the gadget driver that this is
335 * the case by returning -EAGAIN.
336 */
7b9cc7a2
KL		 337 ret = -EAGAIN;
338 break;
339 default:
340 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
341 }
342
c0ca324d 343 break;
72246da4 344 }
f6bb225b 345 } while (--timeout);
72246da4 346
f6bb225b 347 if (timeout == 0) {
f6bb225b 348 ret = -ETIMEDOUT;
0933df15 349 cmd_status = -ETIMEDOUT;
f6bb225b 350 }
c0ca324d 351
0933df15
FB		 352 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
353
6cb2e4e3
FB		 354 if (ret == 0) {
355 switch (DWC3_DEPCMD_CMD(cmd)) {
356 case DWC3_DEPCMD_STARTTRANSFER:
357 dep->flags |= DWC3_EP_TRANSFER_STARTED;
358 break;
359 case DWC3_DEPCMD_ENDTRANSFER:
360 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
361 break;
362 default:
363 /* nothing */
364 break;
365 }
366 }
367
2b0f11df
FB		 368 if (unlikely(susphy)) {
369 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
370 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
371 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
372 }
373
c0ca324d 374 return ret;
72246da4
FB		 375}
376
50c763f8
JY		 377static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380 struct dwc3_gadget_ep_cmd_params params;
381 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
382
383 /*
384 * As of core revision 2.60a the recommended programming model
385 * is to set the ClearPendIN bit when issuing a Clear Stall EP
386 * command for IN endpoints. This is to prevent an issue where
387 * some (non-compliant) hosts may not send ACK TPs for pending
388 * IN transfers due to a mishandled error condition. Synopsys
389 * STAR 9000614252.
390 */
5e6c88d2
LB		 391 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
392 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 393 cmd |= DWC3_DEPCMD_CLEARPENDIN;
394
395 memset(&params, 0, sizeof(params));
396
2cd4718d 397 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 398}
399
72246da4 400static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 401 struct dwc3_trb *trb)
72246da4 402{
c439ef87 403 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 404
405 return dep->trb_pool_dma + offset;
406}
407
408static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
409{
410 struct dwc3 *dwc = dep->dwc;
411
412 if (dep->trb_pool)
413 return 0;
414
d64ff406 415 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 416 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
417 &dep->trb_pool_dma, GFP_KERNEL);
418 if (!dep->trb_pool) {
419 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
420 dep->name);
421 return -ENOMEM;
422 }
423
424 return 0;
425}
426
427static void dwc3_free_trb_pool(struct dwc3_ep *dep)
428{
429 struct dwc3 *dwc = dep->dwc;
430
d64ff406 431 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 432 dep->trb_pool, dep->trb_pool_dma);
433
434 dep->trb_pool = NULL;
435 dep->trb_pool_dma = 0;
436}
437
c4509601
JY		 438static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
439
440/**
441 * dwc3_gadget_start_config - Configure EP resources
442 * @dwc: pointer to our controller context structure
443 * @dep: endpoint that is being enabled
444 *
445 * The assignment of transfer resources cannot perfectly follow the
446 * data book due to the fact that the controller driver does not have
447 * all knowledge of the configuration in advance. It is given this
448 * information piecemeal by the composite gadget framework after every
449 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
450 * programming model in this scenario can cause errors. For two
451 * reasons:
452 *
453 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
454 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
455 * multiple interfaces.
456 *
457 * 2) The databook does not mention doing more DEPXFERCFG for new
458 * endpoint on alt setting (8.1.6).
459 *
460 * The following simplified method is used instead:
461 *
462 * All hardware endpoints can be assigned a transfer resource and this
463 * setting will stay persistent until either a core reset or
464 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
465 * do DEPXFERCFG for every hardware endpoint as well. We are
466 * guaranteed that there are as many transfer resources as endpoints.
467 *
468 * This function is called for each endpoint when it is being enabled
469 * but is triggered only when called for EP0-out, which always happens
470 * first, and which should only happen in one of the above conditions.
471 */
72246da4
FB		 472static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
473{
474 struct dwc3_gadget_ep_cmd_params params;
475 u32 cmd;
c4509601
JY		 476 int i;
477 int ret;
478
479 if (dep->number)
480 return 0;
72246da4
FB		 481
482 memset(&params, 0x00, sizeof(params));
c4509601 483 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 484
2cd4718d 485 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 486 if (ret)
487 return ret;
488
489 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
490 struct dwc3_ep *dep = dwc->eps[i];
72246da4 491
c4509601
JY		 492 if (!dep)
493 continue;
494
495 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
496 if (ret)
497 return ret;
72246da4
FB		 498 }
499
500 return 0;
501}
502
503static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 504 bool modify, bool restore)
72246da4 505{
39ebb05c
JY		 506 const struct usb_ss_ep_comp_descriptor *comp_desc;
507 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 508 struct dwc3_gadget_ep_cmd_params params;
509
21e64bf2
FB		 510 if (dev_WARN_ONCE(dwc->dev, modify && restore,
511 "Can't modify and restore\n"))
512 return -EINVAL;
513
39ebb05c
JY		 514 comp_desc = dep->endpoint.comp_desc;
515 desc = dep->endpoint.desc;
516
72246da4
FB		 517 memset(&params, 0x00, sizeof(params));
518
dc1c70a7 519 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 520 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
521
522 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 523 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 524 u32 burst = dep->endpoint.maxburst;
676e3497 525 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 526 }
72246da4 527
21e64bf2
FB		 528 if (modify) {
529 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
530 } else if (restore) {
265b70a7
PZ		 531 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
532 params.param2 |= dep->saved_state;
21e64bf2
FB		 533 } else {
534 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 535 }
536
4bc48c97
FB		 537 if (usb_endpoint_xfer_control(desc))
538 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 539
540 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
541 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 542
18b7ede5 543 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 544 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
545 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 546 dep->stream_capable = true;
547 }
548
0b93a4c8 549 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 550 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 551
552 /*
553 * We are doing 1:1 mapping for endpoints, meaning
554 * Physical Endpoints 2 maps to Logical Endpoint 2 and
555 * so on. We consider the direction bit as part of the physical
556 * endpoint number. So USB endpoint 0x81 is 0x03.
557 */
dc1c70a7 558 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 559
560 /*
561 * We must use the lower 16 TX FIFOs even though
562 * HW might have more
563 */
564 if (dep->direction)
dc1c70a7 565 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 566
567 if (desc->bInterval) {
dc1c70a7 568 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 569 dep->interval = 1 << (desc->bInterval - 1);
570 }
571
2cd4718d 572 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 573}
574
575static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
576{
577 struct dwc3_gadget_ep_cmd_params params;
578
579 memset(&params, 0x00, sizeof(params));
580
dc1c70a7 581 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 582
2cd4718d
FB		 583 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
584 &params);
72246da4
FB		 585}
586
587/**
588 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
589 * @dep: endpoint to be initialized
590 * @desc: USB Endpoint Descriptor
591 *
592 * Caller should take care of locking
593 */
594static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 595 bool modify, bool restore)
72246da4 596{
39ebb05c 597 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 598 struct dwc3 *dwc = dep->dwc;
39ebb05c 599
72246da4 600 u32 reg;
b09e99ee 601 int ret;
72246da4
FB		 602
603 if (!(dep->flags & DWC3_EP_ENABLED)) {
604 ret = dwc3_gadget_start_config(dwc, dep);
605 if (ret)
606 return ret;
607 }
608
39ebb05c 609 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 610 if (ret)
611 return ret;
612
613 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 614 struct dwc3_trb *trb_st_hw;
615 struct dwc3_trb *trb_link;
72246da4 616
72246da4
FB		 617 dep->type = usb_endpoint_type(desc);
618 dep->flags |= DWC3_EP_ENABLED;
76a638f8 619 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 620
621 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
622 reg |= DWC3_DALEPENA_EP(dep->number);
623 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
624
76a638f8
BW		 625 init_waitqueue_head(&dep->wait_end_transfer);
626
36b68aae 627 if (usb_endpoint_xfer_control(desc))
2870e501 628 goto out;
72246da4 629
0d25744a
JY		 630 /* Initialize the TRB ring */
631 dep->trb_dequeue = 0;
632 dep->trb_enqueue = 0;
633 memset(dep->trb_pool, 0,
634 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
635
36b68aae 636 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 637 trb_st_hw = &dep->trb_pool[0];
638
f6bafc6a 639 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 640 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
641 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
642 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
643 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 644 }
645
a97ea994
FB		 646 /*
647 * Issue StartTransfer here with no-op TRB so we can always rely on No
648 * Response Update Transfer command.
649 */
650 if (usb_endpoint_xfer_bulk(desc)) {
651 struct dwc3_gadget_ep_cmd_params params;
652 struct dwc3_trb *trb;
653 dma_addr_t trb_dma;
654 u32 cmd;
655
656 memset(&params, 0, sizeof(params));
657 trb = &dep->trb_pool[0];
658 trb_dma = dwc3_trb_dma_offset(dep, trb);
659
660 params.param0 = upper_32_bits(trb_dma);
661 params.param1 = lower_32_bits(trb_dma);
662
663 cmd = DWC3_DEPCMD_STARTTRANSFER;
664
665 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
666 if (ret < 0)
667 return ret;
668
669 dep->flags |= DWC3_EP_BUSY;
670
671 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
672 WARN_ON_ONCE(!dep->resource_index);
673 }
674
2870e501
FB		 675
676out:
677 trace_dwc3_gadget_ep_enable(dep);
678
72246da4
FB		 679 return 0;
680}
681
b992e681 682static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 683static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 684{
685 struct dwc3_request *req;
686
0e146028 687 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 688
0e146028
FB		 689 /* - giveback all requests to gadget driver */
690 while (!list_empty(&dep->started_list)) {
691 req = next_request(&dep->started_list);
1591633e 692
0e146028 693 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 694 }
695
aa3342c8
FB		 696 while (!list_empty(&dep->pending_list)) {
697 req = next_request(&dep->pending_list);
72246da4 698
624407f9 699 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 700 }
72246da4
FB		 701}
702
703/**
704 * __dwc3_gadget_ep_disable - Disables a HW endpoint
705 * @dep: the endpoint to disable
706 *
624407f9
SAS		 707 * This function also removes requests which are currently processed ny the
708 * hardware and those which are not yet scheduled.
709 * Caller should take care of locking.
72246da4 710 */
72246da4
FB		 711static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
712{
713 struct dwc3 *dwc = dep->dwc;
714 u32 reg;
715
2870e501 716 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 717
624407f9 718 dwc3_remove_requests(dwc, dep);
72246da4 719
687ef981
FB		 720 /* make sure HW endpoint isn't stalled */
721 if (dep->flags & DWC3_EP_STALL)
7a608559 722 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 723
72246da4
FB		 724 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
725 reg &= ~DWC3_DALEPENA_EP(dep->number);
726 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
727
879631aa 728 dep->stream_capable = false;
72246da4 729 dep->type = 0;
76a638f8 730 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 731
39ebb05c
JY		 732 /* Clear out the ep descriptors for non-ep0 */
733 if (dep->number > 1) {
734 dep->endpoint.comp_desc = NULL;
735 dep->endpoint.desc = NULL;
736 }
737
72246da4
FB		 738 return 0;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 return -EINVAL;
747}
748
749static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
750{
751 return -EINVAL;
752}
753
754/* -------------------------------------------------------------------------- */
755
756static int dwc3_gadget_ep_enable(struct usb_ep *ep,
757 const struct usb_endpoint_descriptor *desc)
758{
759 struct dwc3_ep *dep;
760 struct dwc3 *dwc;
761 unsigned long flags;
762 int ret;
763
764 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
765 pr_debug("dwc3: invalid parameters\n");
766 return -EINVAL;
767 }
768
769 if (!desc->wMaxPacketSize) {
770 pr_debug("dwc3: missing wMaxPacketSize\n");
771 return -EINVAL;
772 }
773
774 dep = to_dwc3_ep(ep);
775 dwc = dep->dwc;
776
95ca961c
FB		 777 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
778 "%s is already enabled\n",
779 dep->name))
c6f83f38 780 return 0;
c6f83f38 781
72246da4 782 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 783 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 784 spin_unlock_irqrestore(&dwc->lock, flags);
785
786 return ret;
787}
788
789static int dwc3_gadget_ep_disable(struct usb_ep *ep)
790{
791 struct dwc3_ep *dep;
792 struct dwc3 *dwc;
793 unsigned long flags;
794 int ret;
795
796 if (!ep) {
797 pr_debug("dwc3: invalid parameters\n");
798 return -EINVAL;
799 }
800
801 dep = to_dwc3_ep(ep);
802 dwc = dep->dwc;
803
95ca961c
FB		 804 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
805 "%s is already disabled\n",
806 dep->name))
72246da4 807 return 0;
72246da4 808
72246da4
FB		 809 spin_lock_irqsave(&dwc->lock, flags);
810 ret = __dwc3_gadget_ep_disable(dep);
811 spin_unlock_irqrestore(&dwc->lock, flags);
812
813 return ret;
814}
815
816static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
817 gfp_t gfp_flags)
818{
819 struct dwc3_request *req;
820 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 821
822 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 823 if (!req)
72246da4 824 return NULL;
72246da4
FB		 825
826 req->epnum = dep->number;
827 req->dep = dep;
72246da4 828
68d34c8a
FB		 829 dep->allocated_requests++;
830
2c4cbe6e
FB		 831 trace_dwc3_alloc_request(req);
832
72246da4
FB		 833 return &req->request;
834}
835
836static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
837 struct usb_request *request)
838{
839 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 840 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 841
68d34c8a 842 dep->allocated_requests--;
2c4cbe6e 843 trace_dwc3_free_request(req);
72246da4
FB		 844 kfree(req);
845}
846
2c78c029
FB		 847static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
848
e49d3cf4
FB		 849static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
850 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
851 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 852{
6b9018d4
FB		 853 struct dwc3 *dwc = dep->dwc;
854 struct usb_gadget *gadget = &dwc->gadget;
855 enum usb_device_speed speed = gadget->speed;
c71fc37c 856
ef966b9d 857 dwc3_ep_inc_enq(dep);
e5ba5ec8 858
f6bafc6a
FB		 859 trb->size = DWC3_TRB_SIZE_LENGTH(length);
860 trb->bpl = lower_32_bits(dma);
861 trb->bph = upper_32_bits(dma);
c71fc37c 862
16e78db7 863 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 864 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 865 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 866 break;
867
868 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 869 if (!node) {
e5ba5ec8 870 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 871
872 if (speed == USB_SPEED_HIGH) {
873 struct usb_ep *ep = &dep->endpoint;
874 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
875 }
876 } else {
e5ba5ec8 877 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 878 }
ca4d44ea
FB		 879
880 /* always enable Interrupt on Missed ISOC */
881 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 882 break;
883
884 case USB_ENDPOINT_XFER_BULK:
885 case USB_ENDPOINT_XFER_INT:
f6bafc6a 886 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 887 break;
888 default:
889 /*
890 * This is only possible with faulty memory because we
891 * checked it already :)
892 */
0a695d4c
FB		 893 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
894 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 895 }
896
ca4d44ea 897 /* always enable Continue on Short Packet */
c9508c8c 898 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 899 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 900
e49d3cf4 901 if (short_not_ok)
c9508c8c
FB		 902 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
903 }
904
e49d3cf4 905 if ((!no_interrupt && !chain) ||
2c78c029 906 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 907 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 908
e5ba5ec8
PA		 909 if (chain)
910 trb->ctrl |= DWC3_TRB_CTRL_CHN;
911
16e78db7 912 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 913 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 914
f6bafc6a 915 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 916
917 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 918}
919
e49d3cf4
FB		 920/**
921 * dwc3_prepare_one_trb - setup one TRB from one request
922 * @dep: endpoint for which this request is prepared
923 * @req: dwc3_request pointer
924 * @chain: should this TRB be chained to the next?
925 * @node: only for isochronous endpoints. First TRB needs different type.
926 */
927static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
928 struct dwc3_request *req, unsigned chain, unsigned node)
929{
930 struct dwc3_trb *trb;
931 unsigned length = req->request.length;
932 unsigned stream_id = req->request.stream_id;
933 unsigned short_not_ok = req->request.short_not_ok;
934 unsigned no_interrupt = req->request.no_interrupt;
935 dma_addr_t dma = req->request.dma;
936
937 trb = &dep->trb_pool[dep->trb_enqueue];
938
939 if (!req->trb) {
940 dwc3_gadget_move_started_request(req);
941 req->trb = trb;
942 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
943 dep->queued_requests++;
944 }
945
946 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
947 stream_id, short_not_ok, no_interrupt);
948}
949
361572b5
JY		 950/**
951 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
952 * @dep: The endpoint with the TRB ring
953 * @index: The index of the current TRB in the ring
954 *
955 * Returns the TRB prior to the one pointed to by the index. If the
956 * index is 0, we will wrap backwards, skip the link TRB, and return
957 * the one just before that.
958 */
959static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
960{
45438a0c 961 u8 tmp = index;
361572b5 962
45438a0c
FB		 963 if (!tmp)
964 tmp = DWC3_TRB_NUM - 1;
361572b5 965
45438a0c 966 return &dep->trb_pool[tmp - 1];
361572b5
JY		 967}
968
c4233573
FB		 969static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
970{
971 struct dwc3_trb *tmp;
f2694a93 972 struct dwc3 *dwc = dep->dwc;
32db3d94 973 u8 trbs_left;
c4233573
FB		 974
975 /*
976 * If enqueue & dequeue are equal than it is either full or empty.
977 *
978 * One way to know for sure is if the TRB right before us has HWO bit
979 * set or not. If it has, then we're definitely full and can't fit any
980 * more transfers in our ring.
981 */
982 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 983 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 984 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
985 "%s No TRBS left\n", dep->name))
361572b5 986 return 0;
c4233573
FB		 987
988 return DWC3_TRB_NUM - 1;
989 }
990
9d7aba77 991 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 992 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 993
9d7aba77
JY		 994 if (dep->trb_dequeue < dep->trb_enqueue)
995 trbs_left--;
996
32db3d94 997 return trbs_left;
c4233573
FB		 998}
999
5ee85d89 1000static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 1001 struct dwc3_request *req)
5ee85d89 1002{
1f512119 1003 struct scatterlist *sg = req->sg;
5ee85d89 1004 struct scatterlist *s;
5ee85d89
FB		 1005 int i;
1006
1f512119 1007 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 1008 unsigned int length = req->request.length;
1009 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1010 unsigned int rem = length % maxp;
5ee85d89
FB		 1011 unsigned chain = true;
1012
4bc48c97 1013 if (sg_is_last(s))
5ee85d89
FB		 1014 chain = false;
1015
c6267a51
FB		 1016 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1017 struct dwc3 *dwc = dep->dwc;
1018 struct dwc3_trb *trb;
1019
1020 req->unaligned = true;
1021
1022 /* prepare normal TRB */
1023 dwc3_prepare_one_trb(dep, req, true, i);
1024
1025 /* Now prepare one extra TRB to align transfer size */
1026 trb = &dep->trb_pool[dep->trb_enqueue];
1027 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1028 maxp - rem, false, 0,
1029 req->request.stream_id,
1030 req->request.short_not_ok,
1031 req->request.no_interrupt);
1032 } else {
1033 dwc3_prepare_one_trb(dep, req, chain, i);
1034 }
5ee85d89 1035
7ae7df49 1036 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1037 break;
1038 }
1039}
1040
1041static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1042 struct dwc3_request *req)
5ee85d89 1043{
c6267a51
FB		 1044 unsigned int length = req->request.length;
1045 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1046 unsigned int rem = length % maxp;
1047
1048 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1049 struct dwc3 *dwc = dep->dwc;
1050 struct dwc3_trb *trb;
1051
1052 req->unaligned = true;
1053
1054 /* prepare normal TRB */
1055 dwc3_prepare_one_trb(dep, req, true, 0);
1056
1057 /* Now prepare one extra TRB to align transfer size */
1058 trb = &dep->trb_pool[dep->trb_enqueue];
1059 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1060 false, 0, req->request.stream_id,
1061 req->request.short_not_ok,
1062 req->request.no_interrupt);
1063 } else {
1064 dwc3_prepare_one_trb(dep, req, false, 0);
1065 }
5ee85d89
FB		 1066}
1067
72246da4
FB		 1068/*
1069 * dwc3_prepare_trbs - setup TRBs from requests
1070 * @dep: endpoint for which requests are being prepared
72246da4 1071 *
1d046793
PZ		 1072 * The function goes through the requests list and sets up TRBs for the
1073 * transfers. The function returns once there are no more TRBs available or
1074 * it runs out of requests.
72246da4 1075 */
c4233573 1076static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1077{
68e823e2 1078 struct dwc3_request *req, *n;
72246da4
FB		 1079
1080 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1081
7ae7df49 1082 if (!dwc3_calc_trbs_left(dep))
89bc856e 1083 return;
72246da4 1084
d86c5a67
FB		 1085 /*
1086 * We can get in a situation where there's a request in the started list
1087 * but there weren't enough TRBs to fully kick it in the first time
1088 * around, so it has been waiting for more TRBs to be freed up.
1089 *
1090 * In that case, we should check if we have a request with pending_sgs
1091 * in the started list and prepare TRBs for that request first,
1092 * otherwise we will prepare TRBs completely out of order and that will
1093 * break things.
1094 */
1095 list_for_each_entry(req, &dep->started_list, list) {
1096 if (req->num_pending_sgs > 0)
1097 dwc3_prepare_one_trb_sg(dep, req);
1098
1099 if (!dwc3_calc_trbs_left(dep))
1100 return;
1101 }
1102
aa3342c8 1103 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1104 if (req->num_pending_sgs > 0)
7ae7df49 1105 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1106 else
7ae7df49 1107 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1108
7ae7df49 1109 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1110 return;
72246da4 1111 }
72246da4
FB		 1112}
1113
4fae2e3e 1114static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1115{
1116 struct dwc3_gadget_ep_cmd_params params;
1117 struct dwc3_request *req;
4fae2e3e 1118 int starting;
72246da4
FB		 1119 int ret;
1120 u32 cmd;
1121
4fae2e3e 1122 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1123
4fae2e3e
FB		 1124 dwc3_prepare_trbs(dep);
1125 req = next_request(&dep->started_list);
72246da4
FB		 1126 if (!req) {
1127 dep->flags |= DWC3_EP_PENDING_REQUEST;
1128 return 0;
1129 }
1130
1131 memset(&params, 0, sizeof(params));
72246da4 1132
4fae2e3e 1133 if (starting) {
1877d6c9
PA		 1134 params.param0 = upper_32_bits(req->trb_dma);
1135 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1136 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1138 } else {
b6b1c6db
FB		 1139 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1141 }
72246da4 1142
2cd4718d 1143 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1144 if (ret < 0) {
72246da4
FB		 1145 /*
1146 * FIXME we need to iterate over the list of requests
1147 * here and stop, unmap, free and del each of the linked
1d046793 1148 * requests instead of what we do now.
72246da4 1149 */
ce3fc8b3
JD		 1150 if (req->trb)
1151 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1152 dep->queued_requests--;
15b8d933 1153 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1154 return ret;
1155 }
1156
1157 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1158
4fae2e3e 1159 if (starting) {
2eb88016 1160 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1161 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1162 }
25b8ff68 1163
72246da4
FB		 1164 return 0;
1165}
1166
6cb2e4e3
FB		 1167static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1168{
1169 u32 reg;
1170
1171 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172 return DWC3_DSTS_SOFFN(reg);
1173}
1174
d6d6ec7b
PA		 1175static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176 struct dwc3_ep *dep, u32 cur_uf)
1177{
1178 u32 uf;
1179
aa3342c8 1180 if (list_empty(&dep->pending_list)) {
5eb30ced 1181 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1182 dep->name);
f4a53c55 1183 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1184 return;
1185 }
1186
1187 /* 4 micro frames in the future */
1188 uf = cur_uf + dep->interval * 4;
1189
4fae2e3e 1190 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1191}
1192
1193static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1194 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1195{
1196 u32 cur_uf, mask;
1197
1198 mask = ~(dep->interval - 1);
1199 cur_uf = event->parameters & mask;
1200
1201 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1202}
1203
72246da4
FB		 1204static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1205{
0fc9a1be
FB		 1206 struct dwc3 *dwc = dep->dwc;
1207 int ret;
1208
bb423984 1209 if (!dep->endpoint.desc) {
5eb30ced
FB		 1210 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1211 dep->name);
bb423984
FB		 1212 return -ESHUTDOWN;
1213 }
1214
1215 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1216 &req->request, req->dep->name)) {
5eb30ced
FB		 1217 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1218 dep->name, &req->request, req->dep->name);
bb423984
FB		 1219 return -EINVAL;
1220 }
1221
fc8bb91b
FB		 1222 pm_runtime_get(dwc->dev);
1223
72246da4
FB		 1224 req->request.actual = 0;
1225 req->request.status = -EINPROGRESS;
1226 req->direction = dep->direction;
1227 req->epnum = dep->number;
1228
fe84f522
FB		 1229 trace_dwc3_ep_queue(req);
1230
d64ff406
AB		 1231 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1232 dep->direction);
0fc9a1be
FB		 1233 if (ret)
1234 return ret;
1235
1f512119
FB		 1236 req->sg = req->request.sg;
1237 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1238
aa3342c8 1239 list_add_tail(&req->list, &dep->pending_list);
72246da4 1240
d889c23c
FB		 1241 /*
1242 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1243 * wait for a XferNotReady event so we will know what's the current
1244 * (micro-)frame number.
1245 *
1246 * Without this trick, we are very, very likely gonna get Bus Expiry
1247 * errors which will force us issue EndTransfer command.
1248 */
1249 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1250 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1251 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1252 dwc3_stop_active_transfer(dwc, dep->number, true);
1253 dep->flags = DWC3_EP_ENABLED;
1254 } else {
1255 u32 cur_uf;
1256
1257 cur_uf = __dwc3_gadget_get_frame(dwc);
1258 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1259 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1260 }
08a36b54
FB		 1261 }
1262 return 0;
a0925324 1263 }
72246da4 1264
594e121f
FB		 1265 if (!dwc3_calc_trbs_left(dep))
1266 return 0;
b997ada5 1267
08a36b54 1268 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1269 if (ret == -EBUSY)
1270 ret = 0;
1271
1272 return ret;
72246da4
FB		 1273}
1274
04c03d10
FB		 1275static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1276 struct usb_request *request)
1277{
1278 dwc3_gadget_ep_free_request(ep, request);
1279}
1280
1281static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1282{
1283 struct dwc3_request *req;
1284 struct usb_request *request;
1285 struct usb_ep *ep = &dep->endpoint;
1286
04c03d10
FB		 1287 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1288 if (!request)
1289 return -ENOMEM;
1290
1291 request->length = 0;
1292 request->buf = dwc->zlp_buf;
1293 request->complete = __dwc3_gadget_ep_zlp_complete;
1294
1295 req = to_dwc3_request(request);
1296
1297 return __dwc3_gadget_ep_queue(dep, req);
1298}
1299
72246da4
FB		 1300static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1301 gfp_t gfp_flags)
1302{
1303 struct dwc3_request *req = to_dwc3_request(request);
1304 struct dwc3_ep *dep = to_dwc3_ep(ep);
1305 struct dwc3 *dwc = dep->dwc;
1306
1307 unsigned long flags;
1308
1309 int ret;
1310
fdee4eba 1311 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1312 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1313
1314 /*
1315 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1316 * setting request->zero, instead of doing magic, we will just queue an
1317 * extra usb_request ourselves so that it gets handled the same way as
1318 * any other request.
1319 */
d9261898
JY		 1320 if (ret == 0 && request->zero && request->length &&
1321 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1322 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1323
72246da4
FB		 1324 spin_unlock_irqrestore(&dwc->lock, flags);
1325
1326 return ret;
1327}
1328
1329static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1330 struct usb_request *request)
1331{
1332 struct dwc3_request *req = to_dwc3_request(request);
1333 struct dwc3_request *r = NULL;
1334
1335 struct dwc3_ep *dep = to_dwc3_ep(ep);
1336 struct dwc3 *dwc = dep->dwc;
1337
1338 unsigned long flags;
1339 int ret = 0;
1340
2c4cbe6e
FB		 1341 trace_dwc3_ep_dequeue(req);
1342
72246da4
FB		 1343 spin_lock_irqsave(&dwc->lock, flags);
1344
aa3342c8 1345 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1346 if (r == req)
1347 break;
1348 }
1349
1350 if (r != req) {
aa3342c8 1351 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1352 if (r == req)
1353 break;
1354 }
1355 if (r == req) {
1356 /* wait until it is processed */
b992e681 1357 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1358
1359 /*
1360 * If request was already started, this means we had to
1361 * stop the transfer. With that we also need to ignore
1362 * all TRBs used by the request, however TRBs can only
1363 * be modified after completion of END_TRANSFER
1364 * command. So what we do here is that we wait for
1365 * END_TRANSFER completion and only after that, we jump
1366 * over TRBs by clearing HWO and incrementing dequeue
1367 * pointer.
1368 *
1369 * Note that we have 2 possible types of transfers here:
1370 *
1371 * i) Linear buffer request
1372 * ii) SG-list based request
1373 *
1374 * SG-list based requests will have r->num_pending_sgs
1375 * set to a valid number (> 0). Linear requests,
1376 * normally use a single TRB.
1377 *
1378 * For each of these two cases, if r->unaligned flag is
1379 * set, one extra TRB has been used to align transfer
1380 * size to wMaxPacketSize.
1381 *
1382 * All of these cases need to be taken into
1383 * consideration so we don't mess up our TRB ring
1384 * pointers.
1385 */
1386 wait_event_lock_irq(dep->wait_end_transfer,
1387 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1388 dwc->lock);
1389
1390 if (!r->trb)
1391 goto out1;
1392
1393 if (r->num_pending_sgs) {
1394 struct dwc3_trb *trb;
1395 int i = 0;
1396
1397 for (i = 0; i < r->num_pending_sgs; i++) {
1398 trb = r->trb + i;
1399 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1400 dwc3_ep_inc_deq(dep);
1401 }
1402
1403 if (r->unaligned) {
1404 trb = r->trb + r->num_pending_sgs + 1;
1405 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1406 dwc3_ep_inc_deq(dep);
1407 }
1408 } else {
1409 struct dwc3_trb *trb = r->trb;
1410
1411 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1412 dwc3_ep_inc_deq(dep);
1413
1414 if (r->unaligned) {
1415 trb = r->trb + 1;
1416 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1417 dwc3_ep_inc_deq(dep);
1418 }
1419 }
e8d4e8be 1420 goto out1;
72246da4
FB		 1421 }
1422 dev_err(dwc->dev, "request %p was not queued to %s\n",
1423 request, ep->name);
1424 ret = -EINVAL;
1425 goto out0;
1426 }
1427
e8d4e8be 1428out1:
72246da4 1429 /* giveback the request */
cf3113d8 1430 dep->queued_requests--;
72246da4
FB		 1431 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1432
1433out0:
1434 spin_unlock_irqrestore(&dwc->lock, flags);
1435
1436 return ret;
1437}
1438
7a608559 1439int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1440{
1441 struct dwc3_gadget_ep_cmd_params params;
1442 struct dwc3 *dwc = dep->dwc;
1443 int ret;
1444
5ad02fb8
FB		 1445 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1446 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1447 return -EINVAL;
1448 }
1449
72246da4
FB		 1450 memset(&params, 0x00, sizeof(params));
1451
1452 if (value) {
69450c4d
FB		 1453 struct dwc3_trb *trb;
1454
1455 unsigned transfer_in_flight;
1456 unsigned started;
1457
ffb80fc6
FB		 1458 if (dep->flags & DWC3_EP_STALL)
1459 return 0;
1460
69450c4d
FB		 1461 if (dep->number > 1)
1462 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1463 else
1464 trb = &dwc->ep0_trb[dep->trb_enqueue];
1465
1466 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1467 started = !list_empty(&dep->started_list);
1468
1469 if (!protocol && ((dep->direction && transfer_in_flight) ||
1470 (!dep->direction && started))) {
7a608559
FB		 1471 return -EAGAIN;
1472 }
1473
2cd4718d
FB		 1474 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1475 &params);
72246da4 1476 if (ret)
3f89204b 1477 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1478 dep->name);
1479 else
1480 dep->flags |= DWC3_EP_STALL;
1481 } else {
ffb80fc6
FB		 1482 if (!(dep->flags & DWC3_EP_STALL))
1483 return 0;
2cd4718d 1484
50c763f8 1485 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1486 if (ret)
3f89204b 1487 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1488 dep->name);
1489 else
a535d81c 1490 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1491 }
5275455a 1492
72246da4
FB		 1493 return ret;
1494}
1495
1496static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1497{
1498 struct dwc3_ep *dep = to_dwc3_ep(ep);
1499 struct dwc3 *dwc = dep->dwc;
1500
1501 unsigned long flags;
1502
1503 int ret;
1504
1505 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1506 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1507 spin_unlock_irqrestore(&dwc->lock, flags);
1508
1509 return ret;
1510}
1511
1512static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1513{
1514 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1515 struct dwc3 *dwc = dep->dwc;
1516 unsigned long flags;
95aa4e8d 1517 int ret;
72246da4 1518
249a4569 1519 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1520 dep->flags |= DWC3_EP_WEDGE;
1521
08f0d966 1522 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1523 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1524 else
7a608559 1525 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1526 spin_unlock_irqrestore(&dwc->lock, flags);
1527
1528 return ret;
72246da4
FB		 1529}
1530
1531/* -------------------------------------------------------------------------- */
1532
1533static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1534 .bLength = USB_DT_ENDPOINT_SIZE,
1535 .bDescriptorType = USB_DT_ENDPOINT,
1536 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1537};
1538
1539static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1540 .enable = dwc3_gadget_ep0_enable,
1541 .disable = dwc3_gadget_ep0_disable,
1542 .alloc_request = dwc3_gadget_ep_alloc_request,
1543 .free_request = dwc3_gadget_ep_free_request,
1544 .queue = dwc3_gadget_ep0_queue,
1545 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1546 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1547 .set_wedge = dwc3_gadget_ep_set_wedge,
1548};
1549
1550static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1551 .enable = dwc3_gadget_ep_enable,
1552 .disable = dwc3_gadget_ep_disable,
1553 .alloc_request = dwc3_gadget_ep_alloc_request,
1554 .free_request = dwc3_gadget_ep_free_request,
1555 .queue = dwc3_gadget_ep_queue,
1556 .dequeue = dwc3_gadget_ep_dequeue,
1557 .set_halt = dwc3_gadget_ep_set_halt,
1558 .set_wedge = dwc3_gadget_ep_set_wedge,
1559};
1560
1561/* -------------------------------------------------------------------------- */
1562
1563static int dwc3_gadget_get_frame(struct usb_gadget *g)
1564{
1565 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1566
6cb2e4e3 1567 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1568}
1569
218ef7b6 1570static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1571{
d6011f6f 1572 int retries;
72246da4 1573
218ef7b6 1574 int ret;
72246da4
FB		 1575 u32 reg;
1576
72246da4
FB		 1577 u8 link_state;
1578 u8 speed;
1579
72246da4
FB		 1580 /*
1581 * According to the Databook Remote wakeup request should
1582 * be issued only when the device is in early suspend state.
1583 *
1584 * We can check that via USB Link State bits in DSTS register.
1585 */
1586 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1587
1588 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1589 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1590 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1591 return 0;
72246da4
FB		 1592
1593 link_state = DWC3_DSTS_USBLNKST(reg);
1594
1595 switch (link_state) {
1596 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1597 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1598 break;
1599 default:
218ef7b6 1600 return -EINVAL;
72246da4
FB		 1601 }
1602
8598bde7
FB		 1603 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1604 if (ret < 0) {
1605 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1606 return ret;
8598bde7 1607 }
72246da4 1608
802fde98
PZ		 1609 /* Recent versions do this automatically */
1610 if (dwc->revision < DWC3_REVISION_194A) {
1611 /* write zeroes to Link Change Request */
fcc023c7 1612 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1613 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1614 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1615 }
72246da4 1616
1d046793 1617 /* poll until Link State changes to ON */
d6011f6f 1618 retries = 20000;
72246da4 1619
d6011f6f 1620 while (retries--) {
72246da4
FB		 1621 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1622
1623 /* in HS, means ON */
1624 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1625 break;
1626 }
1627
1628 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1629 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1630 return -EINVAL;
72246da4
FB		 1631 }
1632
218ef7b6
FB		 1633 return 0;
1634}
1635
1636static int dwc3_gadget_wakeup(struct usb_gadget *g)
1637{
1638 struct dwc3 *dwc = gadget_to_dwc(g);
1639 unsigned long flags;
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1650 int is_selfpowered)
1651{
1652 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1653 unsigned long flags;
72246da4 1654
249a4569 1655 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1656 g->is_selfpowered = !!is_selfpowered;
249a4569 1657 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1658
1659 return 0;
1660}
1661
7b2a0368 1662static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1663{
1664 u32 reg;
61d58242 1665 u32 timeout = 500;
72246da4 1666
fc8bb91b
FB		 1667 if (pm_runtime_suspended(dwc->dev))
1668 return 0;
1669
72246da4 1670 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1671 if (is_on) {
802fde98
PZ		 1672 if (dwc->revision <= DWC3_REVISION_187A) {
1673 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1674 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1675 }
1676
1677 if (dwc->revision >= DWC3_REVISION_194A)
1678 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1679 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1680
1681 if (dwc->has_hibernation)
1682 reg |= DWC3_DCTL_KEEP_CONNECT;
1683
9fcb3bd8 1684 dwc->pullups_connected = true;
8db7ed15 1685 } else {
72246da4 1686 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1687
1688 if (dwc->has_hibernation && !suspend)
1689 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1690
9fcb3bd8 1691 dwc->pullups_connected = false;
8db7ed15 1692 }
72246da4
FB		 1693
1694 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1695
1696 do {
1697 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1698 reg &= DWC3_DSTS_DEVCTRLHLT;
1699 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1700
1701 if (!timeout)
1702 return -ETIMEDOUT;
72246da4 1703
6f17f74b 1704 return 0;
72246da4
FB		 1705}
1706
1707static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1708{
1709 struct dwc3 *dwc = gadget_to_dwc(g);
1710 unsigned long flags;
6f17f74b 1711 int ret;
72246da4
FB		 1712
1713 is_on = !!is_on;
1714
bb014736
BW		 1715 /*
1716 * Per databook, when we want to stop the gadget, if a control transfer
1717 * is still in process, complete it and get the core into setup phase.
1718 */
1719 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1720 reinit_completion(&dwc->ep0_in_setup);
1721
1722 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1723 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1724 if (ret == 0) {
1725 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1726 return -ETIMEDOUT;
1727 }
1728 }
1729
72246da4 1730 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1731 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1732 spin_unlock_irqrestore(&dwc->lock, flags);
1733
6f17f74b 1734 return ret;
72246da4
FB		 1735}
1736
8698e2ac
FB		 1737static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1738{
1739 u32 reg;
1740
1741 /* Enable all but Start and End of Frame IRQs */
1742 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1743 DWC3_DEVTEN_EVNTOVERFLOWEN |
1744 DWC3_DEVTEN_CMDCMPLTEN |
1745 DWC3_DEVTEN_ERRTICERREN |
1746 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1747 DWC3_DEVTEN_CONNECTDONEEN |
1748 DWC3_DEVTEN_USBRSTEN |
1749 DWC3_DEVTEN_DISCONNEVTEN);
1750
799e9dc8
FB		 1751 if (dwc->revision < DWC3_REVISION_250A)
1752 reg |= DWC3_DEVTEN_ULSTCNGEN;
1753
8698e2ac
FB		 1754 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1755}
1756
1757static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1758{
1759 /* mask all interrupts */
1760 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1761}
1762
1763static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1764static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1765
4e99472b
FB		 1766/**
1767 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1768 * dwc: pointer to our context structure
1769 *
1770 * The following looks like complex but it's actually very simple. In order to
1771 * calculate the number of packets we can burst at once on OUT transfers, we're
1772 * gonna use RxFIFO size.
1773 *
1774 * To calculate RxFIFO size we need two numbers:
1775 * MDWIDTH = size, in bits, of the internal memory bus
1776 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1777 *
1778 * Given these two numbers, the formula is simple:
1779 *
1780 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1781 *
1782 * 24 bytes is for 3x SETUP packets
1783 * 16 bytes is a clock domain crossing tolerance
1784 *
1785 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1786 */
1787static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1788{
1789 u32 ram2_depth;
1790 u32 mdwidth;
1791 u32 nump;
1792 u32 reg;
1793
1794 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1795 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1796
1797 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1798 nump = min_t(u32, nump, 16);
1799
1800 /* update NumP */
1801 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1802 reg &= ~DWC3_DCFG_NUMP_MASK;
1803 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1804 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1805}
1806
d7be2952 1807static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1808{
72246da4 1809 struct dwc3_ep *dep;
72246da4
FB		 1810 int ret = 0;
1811 u32 reg;
1812
cf40b86b
JY		 1813 /*
1814 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1815 * the core supports IMOD, disable it.
1816 */
1817 if (dwc->imod_interval) {
1818 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1819 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1820 } else if (dwc3_has_imod(dwc)) {
1821 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1822 }
1823
72246da4
FB		 1824 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1825 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1826
1827 /**
1828 * WORKAROUND: DWC3 revision < 2.20a have an issue
1829 * which would cause metastability state on Run/Stop
1830 * bit if we try to force the IP to USB2-only mode.
1831 *
1832 * Because of that, we cannot configure the IP to any
1833 * speed other than the SuperSpeed
1834 *
1835 * Refers to:
1836 *
1837 * STAR#9000525659: Clock Domain Crossing on DCTL in
1838 * USB 2.0 Mode
1839 */
f7e846f0 1840 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1841 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1842 } else {
1843 switch (dwc->maximum_speed) {
1844 case USB_SPEED_LOW:
2da9ad76 1845 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1846 break;
1847 case USB_SPEED_FULL:
9418ee15 1848 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1849 break;
1850 case USB_SPEED_HIGH:
2da9ad76 1851 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1852 break;
7580862b 1853 case USB_SPEED_SUPER_PLUS:
2da9ad76 1854 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1855 break;
f7e846f0 1856 default:
77966eb8
JY		 1857 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1858 dwc->maximum_speed);
1859 /* fall through */
1860 case USB_SPEED_SUPER:
1861 reg |= DWC3_DCFG_SUPERSPEED;
1862 break;
f7e846f0
FB		 1863 }
1864 }
72246da4
FB		 1865 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1866
2a58f9c1
FB		 1867 /*
1868 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1869 * field instead of letting dwc3 itself calculate that automatically.
1870 *
1871 * This way, we maximize the chances that we'll be able to get several
1872 * bursts of data without going through any sort of endpoint throttling.
1873 */
1874 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1875 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1876 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1877
4e99472b
FB		 1878 dwc3_gadget_setup_nump(dwc);
1879
72246da4
FB		 1880 /* Start with SuperSpeed Default */
1881 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1882
1883 dep = dwc->eps[0];
39ebb05c 1884 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1885 if (ret) {
1886 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1887 goto err0;
72246da4
FB		 1888 }
1889
1890 dep = dwc->eps[1];
39ebb05c 1891 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1892 if (ret) {
1893 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1894 goto err1;
72246da4
FB		 1895 }
1896
1897 /* begin to receive SETUP packets */
c7fcdeb2 1898 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1899 dwc3_ep0_out_start(dwc);
1900
8698e2ac
FB		 1901 dwc3_gadget_enable_irq(dwc);
1902
72246da4
FB		 1903 return 0;
1904
b0d7ffd4 1905err1:
d7be2952 1906 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1907
1908err0:
72246da4
FB		 1909 return ret;
1910}
1911
d7be2952
FB		 1912static int dwc3_gadget_start(struct usb_gadget *g,
1913 struct usb_gadget_driver *driver)
72246da4
FB		 1914{
1915 struct dwc3 *dwc = gadget_to_dwc(g);
1916 unsigned long flags;
d7be2952 1917 int ret = 0;
8698e2ac 1918 int irq;
72246da4 1919
9522def4 1920 irq = dwc->irq_gadget;
d7be2952
FB		 1921 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1922 IRQF_SHARED, "dwc3", dwc->ev_buf);
1923 if (ret) {
1924 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1925 irq, ret);
1926 goto err0;
1927 }
1928
72246da4 1929 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1930 if (dwc->gadget_driver) {
1931 dev_err(dwc->dev, "%s is already bound to %s\n",
1932 dwc->gadget.name,
1933 dwc->gadget_driver->driver.name);
1934 ret = -EBUSY;
1935 goto err1;
1936 }
1937
1938 dwc->gadget_driver = driver;
1939
fc8bb91b
FB		 1940 if (pm_runtime_active(dwc->dev))
1941 __dwc3_gadget_start(dwc);
1942
d7be2952
FB		 1943 spin_unlock_irqrestore(&dwc->lock, flags);
1944
1945 return 0;
1946
1947err1:
1948 spin_unlock_irqrestore(&dwc->lock, flags);
1949 free_irq(irq, dwc);
1950
1951err0:
1952 return ret;
1953}
72246da4 1954
d7be2952
FB		 1955static void __dwc3_gadget_stop(struct dwc3 *dwc)
1956{
8698e2ac 1957 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1958 __dwc3_gadget_ep_disable(dwc->eps[0]);
1959 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1960}
72246da4 1961
d7be2952
FB		 1962static int dwc3_gadget_stop(struct usb_gadget *g)
1963{
1964 struct dwc3 *dwc = gadget_to_dwc(g);
1965 unsigned long flags;
76a638f8 1966 int epnum;
72246da4 1967
d7be2952 1968 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1969
1970 if (pm_runtime_suspended(dwc->dev))
1971 goto out;
1972
d7be2952 1973 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1974
1975 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1976 struct dwc3_ep *dep = dwc->eps[epnum];
1977
1978 if (!dep)
1979 continue;
1980
1981 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1982 continue;
1983
1984 wait_event_lock_irq(dep->wait_end_transfer,
1985 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1986 dwc->lock);
1987 }
1988
1989out:
d7be2952 1990 dwc->gadget_driver = NULL;
72246da4
FB		 1991 spin_unlock_irqrestore(&dwc->lock, flags);
1992
3f308d17 1993 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1994
72246da4
FB		 1995 return 0;
1996}
802fde98 1997
72246da4
FB		 1998static const struct usb_gadget_ops dwc3_gadget_ops = {
1999 .get_frame = dwc3_gadget_get_frame,
2000 .wakeup = dwc3_gadget_wakeup,
2001 .set_selfpowered = dwc3_gadget_set_selfpowered,
2002 .pullup = dwc3_gadget_pullup,
2003 .udc_start = dwc3_gadget_start,
2004 .udc_stop = dwc3_gadget_stop,
2005};
2006
2007/* -------------------------------------------------------------------------- */
2008
f3bcfc7e 2009static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
72246da4
FB		 2010{
2011 struct dwc3_ep *dep;
47d3946e 2012 u8 epnum;
72246da4 2013
f3bcfc7e
BD		 2014 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2015
47d3946e
BD		 2016 for (epnum = 0; epnum < num; epnum++) {
2017 bool direction = epnum & 1;
72246da4 2018
72246da4 2019 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 2020 if (!dep)
72246da4 2021 return -ENOMEM;
72246da4
FB		 2022
2023 dep->dwc = dwc;
2024 dep->number = epnum;
47d3946e 2025 dep->direction = direction;
2eb88016 2026 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 2027 dwc->eps[epnum] = dep;
2028
2029 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
47d3946e 2030 direction ? "in" : "out");
6a1e3ef4 2031
72246da4 2032 dep->endpoint.name = dep->name;
39ebb05c
JY		 2033
2034 if (!(dep->number > 1)) {
2035 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2036 dep->endpoint.comp_desc = NULL;
2037 }
2038
74674cbf 2039 spin_lock_init(&dep->lock);
72246da4
FB		 2040
2041 if (epnum == 0 || epnum == 1) {
e117e742 2042 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2043 dep->endpoint.maxburst = 1;
72246da4
FB		 2044 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2045 if (!epnum)
2046 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2047 } else if (direction) {
2048 int mdwidth;
2049 int size;
2050 int ret;
2051 int num;
2052
2053 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2054 /* MDWIDTH is represented in bits, we need it in bytes */
2055 mdwidth /= 8;
2056
47d3946e 2057 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
28781789
FB		 2058 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2059
2060 /* FIFO Depth is in MDWDITH bytes. Multiply */
2061 size *= mdwidth;
2062
2063 num = size / 1024;
2064 if (num == 0)
2065 num = 1;
2066
2067 /*
2068 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2069 * internal overhead. We don't really know how these are used,
2070 * but documentation say it exists.
2071 */
2072 size -= mdwidth * (num + 1);
2073 size /= num;
2074
2075 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2076
2077 dep->endpoint.max_streams = 15;
2078 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2079 list_add_tail(&dep->endpoint.ep_list,
2080 &dwc->gadget.ep_list);
2081
2082 ret = dwc3_alloc_trb_pool(dep);
2083 if (ret)
2084 return ret;
72246da4
FB		 2085 } else {
2086 int ret;
2087
e117e742 2088 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2089 dep->endpoint.max_streams = 15;
72246da4
FB		 2090 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2091 list_add_tail(&dep->endpoint.ep_list,
2092 &dwc->gadget.ep_list);
2093
2094 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2095 if (ret)
72246da4 2096 return ret;
72246da4 2097 }
25b8ff68 2098
a474d3b7
RB		 2099 if (epnum == 0 || epnum == 1) {
2100 dep->endpoint.caps.type_control = true;
2101 } else {
2102 dep->endpoint.caps.type_iso = true;
2103 dep->endpoint.caps.type_bulk = true;
2104 dep->endpoint.caps.type_int = true;
2105 }
2106
47d3946e 2107 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2108 dep->endpoint.caps.dir_out = !direction;
2109
aa3342c8
FB		 2110 INIT_LIST_HEAD(&dep->pending_list);
2111 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2112 }
2113
2114 return 0;
2115}
2116
2117static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2118{
2119 struct dwc3_ep *dep;
2120 u8 epnum;
2121
2122 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2123 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2124 if (!dep)
2125 continue;
5bf8fae3
GC		 2126 /*
2127 * Physical endpoints 0 and 1 are special; they form the
2128 * bi-directional USB endpoint 0.
2129 *
2130 * For those two physical endpoints, we don't allocate a TRB
2131 * pool nor do we add them the endpoints list. Due to that, we
2132 * shouldn't do these two operations otherwise we would end up
2133 * with all sorts of bugs when removing dwc3.ko.
2134 */
2135 if (epnum != 0 && epnum != 1) {
2136 dwc3_free_trb_pool(dep);
72246da4 2137 list_del(&dep->endpoint.ep_list);
5bf8fae3 2138 }
72246da4
FB		 2139
2140 kfree(dep);
2141 }
2142}
2143
72246da4 2144/* -------------------------------------------------------------------------- */
e5caff68 2145
e5ba5ec8
PA		 2146static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2147 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2148 const struct dwc3_event_depevt *event, int status,
2149 int chain)
72246da4 2150{
72246da4
FB		 2151 unsigned int count;
2152 unsigned int s_pkt = 0;
d6d6ec7b 2153 unsigned int trb_status;
72246da4 2154
dc55c67e 2155 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2156
2157 if (req->trb == trb)
2158 dep->queued_requests--;
2159
2c4cbe6e
FB		 2160 trace_dwc3_complete_trb(dep, trb);
2161
e5b36ae2
FB		 2162 /*
2163 * If we're in the middle of series of chained TRBs and we
2164 * receive a short transfer along the way, DWC3 will skip
2165 * through all TRBs including the last TRB in the chain (the
2166 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2167 * bit and SW has to do it manually.
2168 *
2169 * We're going to do that here to avoid problems of HW trying
2170 * to use bogus TRBs for transfers.
2171 */
2172 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2173 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2174
c6267a51
FB		 2175 /*
2176 * If we're dealing with unaligned size OUT transfer, we will be left
2177 * with one TRB pending in the ring. We need to manually clear HWO bit
2178 * from that TRB.
2179 */
2180 if (req->unaligned && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2181 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2182 return 1;
2183 }
2184
e5ba5ec8 2185 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2186 req->remaining += count;
e5ba5ec8 2187
35b2719e
FB		 2188 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2189 return 1;
2190
e5ba5ec8
PA		 2191 if (dep->direction) {
2192 if (count) {
2193 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2194 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2195 /*
2196 * If missed isoc occurred and there is
2197 * no request queued then issue END
2198 * TRANSFER, so that core generates
2199 * next xfernotready and we will issue
2200 * a fresh START TRANSFER.
2201 * If there are still queued request
2202 * then wait, do not issue either END
2203 * or UPDATE TRANSFER, just attach next
aa3342c8 2204 * request in pending_list during
e5ba5ec8
PA		 2205 * giveback.If any future queued request
2206 * is successfully transferred then we
2207 * will issue UPDATE TRANSFER for all
aa3342c8 2208 * request in the pending_list.
e5ba5ec8
PA		 2209 */
2210 dep->flags |= DWC3_EP_MISSED_ISOC;
2211 } else {
2212 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2213 dep->name);
2214 status = -ECONNRESET;
2215 }
2216 } else {
2217 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2218 }
2219 } else {
2220 if (count && (event->status & DEPEVT_STATUS_SHORT))
2221 s_pkt = 1;
2222 }
2223
7c705dfe 2224 if (s_pkt && !chain)
e5ba5ec8 2225 return 1;
f99f53f2 2226
e5ba5ec8
PA		 2227 if ((event->status & DEPEVT_STATUS_IOC) &&
2228 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2229 return 1;
f99f53f2 2230
e5ba5ec8
PA		 2231 return 0;
2232}
2233
2234static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2235 const struct dwc3_event_depevt *event, int status)
2236{
31162af4 2237 struct dwc3_request *req, *n;
e5ba5ec8 2238 struct dwc3_trb *trb;
d6e10bf2 2239 bool ioc = false;
e62c5bc5 2240 int ret = 0;
e5ba5ec8 2241
31162af4 2242 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2243 unsigned length;
e5b36ae2
FB		 2244 int chain;
2245
1f512119
FB		 2246 length = req->request.length;
2247 chain = req->num_pending_sgs > 0;
31162af4 2248 if (chain) {
1f512119 2249 struct scatterlist *sg = req->sg;
31162af4 2250 struct scatterlist *s;
1f512119 2251 unsigned int pending = req->num_pending_sgs;
31162af4 2252 unsigned int i;
c7de5734 2253
1f512119 2254 for_each_sg(sg, s, pending, i) {
31162af4 2255 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2256
7282c4ef
FB		 2257 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2258 break;
2259
1f512119
FB		 2260 req->sg = sg_next(s);
2261 req->num_pending_sgs--;
2262
31162af4
FB		 2263 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2264 event, status, chain);
1f512119
FB		 2265 if (ret)
2266 break;
31162af4
FB		 2267 }
2268 } else {
737f1ae2 2269 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2270 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2271 event, status, chain);
31162af4 2272 }
d115d705 2273
c6267a51
FB		 2274 if (req->unaligned) {
2275 trb = &dep->trb_pool[dep->trb_dequeue];
2276 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2277 event, status, false);
2278 req->unaligned = false;
2279 }
2280
e62c5bc5 2281 req->request.actual = length - req->remaining;
1f512119 2282
ff377ae4 2283 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2284 return __dwc3_gadget_kick_transfer(dep, 0);
2285
d115d705 2286 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2287
d6e10bf2
AB		 2288 if (ret) {
2289 if ((event->status & DEPEVT_STATUS_IOC) &&
2290 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2291 ioc = true;
72246da4 2292 break;
d6e10bf2 2293 }
31162af4 2294 }
72246da4 2295
4cb42217
FB		 2296 /*
2297 * Our endpoint might get disabled by another thread during
2298 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2299 * early on so DWC3_EP_BUSY flag gets cleared
2300 */
2301 if (!dep->endpoint.desc)
2302 return 1;
2303
cdc359dd 2304 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2305 list_empty(&dep->started_list)) {
2306 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2307 /*
2308 * If there is no entry in request list then do
2309 * not issue END TRANSFER now. Just set PENDING
2310 * flag, so that END TRANSFER is issued when an
2311 * entry is added into request list.
2312 */
2313 dep->flags = DWC3_EP_PENDING_REQUEST;
2314 } else {
b992e681 2315 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2316 dep->flags = DWC3_EP_ENABLED;
2317 }
7efea86c
PA		 2318 return 1;
2319 }
2320
d6e10bf2
AB		 2321 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2322 return 0;
2323
72246da4
FB		 2324 return 1;
2325}
2326
2327static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2328 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2329{
2330 unsigned status = 0;
2331 int clean_busy;
e18b7975
FB		 2332 u32 is_xfer_complete;
2333
2334 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2335
2336 if (event->status & DEPEVT_STATUS_BUSERR)
2337 status = -ECONNRESET;
2338
1d046793 2339 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2340 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2341 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2342 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2343
2344 /*
2345 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2346 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2347 */
2348 if (dwc->revision < DWC3_REVISION_183A) {
2349 u32 reg;
2350 int i;
2351
2352 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2353 dep = dwc->eps[i];
fae2b904
FB		 2354
2355 if (!(dep->flags & DWC3_EP_ENABLED))
2356 continue;
2357
aa3342c8 2358 if (!list_empty(&dep->started_list))
fae2b904
FB		 2359 return;
2360 }
2361
2362 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2363 reg |= dwc->u1u2;
2364 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2365
2366 dwc->u1u2 = 0;
2367 }
8a1a9c9e 2368
4cb42217
FB		 2369 /*
2370 * Our endpoint might get disabled by another thread during
2371 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2372 * early on so DWC3_EP_BUSY flag gets cleared
2373 */
2374 if (!dep->endpoint.desc)
2375 return;
2376
e6e709b7 2377 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2378 int ret;
2379
4fae2e3e 2380 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2381 if (!ret || ret == -EBUSY)
2382 return;
2383 }
72246da4
FB		 2384}
2385
72246da4
FB		 2386static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2387 const struct dwc3_event_depevt *event)
2388{
2389 struct dwc3_ep *dep;
2390 u8 epnum = event->endpoint_number;
76a638f8 2391 u8 cmd;
72246da4
FB		 2392
2393 dep = dwc->eps[epnum];
2394
d7fd41c6
JD		 2395 if (!(dep->flags & DWC3_EP_ENABLED)) {
2396 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2397 return;
2398
2399 /* Handle only EPCMDCMPLT when EP disabled */
2400 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2401 return;
2402 }
3336abb5 2403
72246da4
FB		 2404 if (epnum == 0 || epnum == 1) {
2405 dwc3_ep0_interrupt(dwc, event);
2406 return;
2407 }
2408
2409 switch (event->endpoint_event) {
2410 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2411 dep->resource_index = 0;
c2df85ca 2412
16e78db7 2413 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2414 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2415 return;
2416 }
2417
029d97ff 2418 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2419 break;
2420 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2421 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2422 break;
2423 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2424 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2425 dwc3_gadget_start_isoc(dwc, dep, event);
2426 } else {
2427 int ret;
2428
4fae2e3e 2429 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2430 if (!ret || ret == -EBUSY)
2431 return;
72246da4
FB		 2432 }
2433
879631aa
FB		 2434 break;
2435 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2436 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2437 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2438 dep->name);
2439 return;
2440 }
72246da4 2441 break;
72246da4 2442 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2443 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2444
2445 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2446 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2447 wake_up(&dep->wait_end_transfer);
2448 }
2449 break;
2450 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2451 break;
2452 }
2453}
2454
2455static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2456{
2457 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2458 spin_unlock(&dwc->lock);
2459 dwc->gadget_driver->disconnect(&dwc->gadget);
2460 spin_lock(&dwc->lock);
2461 }
2462}
2463
bc5ba2e0
FB		 2464static void dwc3_suspend_gadget(struct dwc3 *dwc)
2465{
73a30bfc 2466 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2467 spin_unlock(&dwc->lock);
2468 dwc->gadget_driver->suspend(&dwc->gadget);
2469 spin_lock(&dwc->lock);
2470 }
2471}
2472
2473static void dwc3_resume_gadget(struct dwc3 *dwc)
2474{
73a30bfc 2475 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2476 spin_unlock(&dwc->lock);
2477 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2478 spin_lock(&dwc->lock);
8e74475b
FB		 2479 }
2480}
2481
2482static void dwc3_reset_gadget(struct dwc3 *dwc)
2483{
2484 if (!dwc->gadget_driver)
2485 return;
2486
2487 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2488 spin_unlock(&dwc->lock);
2489 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2490 spin_lock(&dwc->lock);
2491 }
2492}
2493
b992e681 2494static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2495{
2496 struct dwc3_ep *dep;
2497 struct dwc3_gadget_ep_cmd_params params;
2498 u32 cmd;
2499 int ret;
2500
2501 dep = dwc->eps[epnum];
2502
76a638f8
BW		 2503 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2504 !dep->resource_index)
3daf74d7
PA		 2505 return;
2506
57911504
PA		 2507 /*
2508 * NOTICE: We are violating what the Databook says about the
2509 * EndTransfer command. Ideally we would _always_ wait for the
2510 * EndTransfer Command Completion IRQ, but that's causing too
2511 * much trouble synchronizing between us and gadget driver.
2512 *
2513 * We have discussed this with the IP Provider and it was
2514 * suggested to giveback all requests here, but give HW some
2515 * extra time to synchronize with the interconnect. We're using
dc93b41a 2516 * an arbitrary 100us delay for that.
57911504
PA		 2517 *
2518 * Note also that a similar handling was tested by Synopsys
2519 * (thanks a lot Paul) and nothing bad has come out of it.
2520 * In short, what we're doing is:
2521 *
2522 * - Issue EndTransfer WITH CMDIOC bit set
2523 * - Wait 100us
06281d46
JY		 2524 *
2525 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2526 * supports a mode to work around the above limitation. The
2527 * software can poll the CMDACT bit in the DEPCMD register
2528 * after issuing a EndTransfer command. This mode is enabled
2529 * by writing GUCTL2[14]. This polling is already done in the
2530 * dwc3_send_gadget_ep_cmd() function so if the mode is
2531 * enabled, the EndTransfer command will have completed upon
2532 * returning from this function and we don't need to delay for
2533 * 100us.
2534 *
2535 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2536 */
2537
3daf74d7 2538 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2539 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2540 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2541 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2542 memset(&params, 0, sizeof(params));
2cd4718d 2543 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2544 WARN_ON_ONCE(ret);
b4996a86 2545 dep->resource_index = 0;
041d81f4 2546 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2547
76a638f8
BW		 2548 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2549 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2550 udelay(100);
76a638f8 2551 }
72246da4
FB		 2552}
2553
72246da4
FB		 2554static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2555{
2556 u32 epnum;
2557
2558 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2559 struct dwc3_ep *dep;
72246da4
FB		 2560 int ret;
2561
2562 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2563 if (!dep)
2564 continue;
72246da4
FB		 2565
2566 if (!(dep->flags & DWC3_EP_STALL))
2567 continue;
2568
2569 dep->flags &= ~DWC3_EP_STALL;
2570
50c763f8 2571 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2572 WARN_ON_ONCE(ret);
2573 }
2574}
2575
2576static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2577{
c4430a26
FB		 2578 int reg;
2579
72246da4
FB		 2580 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2581 reg &= ~DWC3_DCTL_INITU1ENA;
2582 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2583
2584 reg &= ~DWC3_DCTL_INITU2ENA;
2585 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2586
72246da4
FB		 2587 dwc3_disconnect_gadget(dwc);
2588
2589 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2590 dwc->setup_packet_pending = false;
06a374ed 2591 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2592
2593 dwc->connected = false;
72246da4
FB		 2594}
2595
72246da4
FB		 2596static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2597{
2598 u32 reg;
2599
fc8bb91b
FB		 2600 dwc->connected = true;
2601
df62df56
FB		 2602 /*
2603 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2604 * would cause a missing Disconnect Event if there's a
2605 * pending Setup Packet in the FIFO.
2606 *
2607 * There's no suggested workaround on the official Bug
2608 * report, which states that "unless the driver/application
2609 * is doing any special handling of a disconnect event,
2610 * there is no functional issue".
2611 *
2612 * Unfortunately, it turns out that we _do_ some special
2613 * handling of a disconnect event, namely complete all
2614 * pending transfers, notify gadget driver of the
2615 * disconnection, and so on.
2616 *
2617 * Our suggested workaround is to follow the Disconnect
2618 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2619 * flag. Such flag gets set whenever we have a SETUP_PENDING
2620 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2621 * same endpoint.
2622 *
2623 * Refers to:
2624 *
2625 * STAR#9000466709: RTL: Device : Disconnect event not
2626 * generated if setup packet pending in FIFO
2627 */
2628 if (dwc->revision < DWC3_REVISION_188A) {
2629 if (dwc->setup_packet_pending)
2630 dwc3_gadget_disconnect_interrupt(dwc);
2631 }
2632
8e74475b 2633 dwc3_reset_gadget(dwc);
72246da4
FB		 2634
2635 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2636 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2637 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2638 dwc->test_mode = false;
72246da4
FB		 2639 dwc3_clear_stall_all_ep(dwc);
2640
2641 /* Reset device address to zero */
2642 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2643 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2644 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2645}
2646
72246da4
FB		 2647static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2648{
72246da4
FB		 2649 struct dwc3_ep *dep;
2650 int ret;
2651 u32 reg;
2652 u8 speed;
2653
72246da4
FB		 2654 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2655 speed = reg & DWC3_DSTS_CONNECTSPD;
2656 dwc->speed = speed;
2657
5fb6fdaf
JY		 2658 /*
2659 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2660 * each time on Connect Done.
2661 *
2662 * Currently we always use the reset value. If any platform
2663 * wants to set this to a different value, we need to add a
2664 * setting and update GCTL.RAMCLKSEL here.
2665 */
72246da4
FB		 2666
2667 switch (speed) {
2da9ad76 2668 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2669 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2670 dwc->gadget.ep0->maxpacket = 512;
2671 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2672 break;
2da9ad76 2673 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2674 /*
2675 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2676 * would cause a missing USB3 Reset event.
2677 *
2678 * In such situations, we should force a USB3 Reset
2679 * event by calling our dwc3_gadget_reset_interrupt()
2680 * routine.
2681 *
2682 * Refers to:
2683 *
2684 * STAR#9000483510: RTL: SS : USB3 reset event may
2685 * not be generated always when the link enters poll
2686 */
2687 if (dwc->revision < DWC3_REVISION_190A)
2688 dwc3_gadget_reset_interrupt(dwc);
2689
72246da4
FB		 2690 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2691 dwc->gadget.ep0->maxpacket = 512;
2692 dwc->gadget.speed = USB_SPEED_SUPER;
2693 break;
2da9ad76 2694 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2695 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2696 dwc->gadget.ep0->maxpacket = 64;
2697 dwc->gadget.speed = USB_SPEED_HIGH;
2698 break;
9418ee15 2699 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2700 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2701 dwc->gadget.ep0->maxpacket = 64;
2702 dwc->gadget.speed = USB_SPEED_FULL;
2703 break;
2da9ad76 2704 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2705 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2706 dwc->gadget.ep0->maxpacket = 8;
2707 dwc->gadget.speed = USB_SPEED_LOW;
2708 break;
2709 }
2710
2b758350
PA		 2711 /* Enable USB2 LPM Capability */
2712
ee5cd41c 2713 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2714 (speed != DWC3_DSTS_SUPERSPEED) &&
2715 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2716 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2717 reg |= DWC3_DCFG_LPM_CAP;
2718 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2719
2720 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2721 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2722
460d098c 2723 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2724
80caf7d2
HR		 2725 /*
2726 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2727 * DCFG.LPMCap is set, core responses with an ACK and the
2728 * BESL value in the LPM token is less than or equal to LPM
2729 * NYET threshold.
2730 */
2731 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2732 && dwc->has_lpm_erratum,
9165dabb 2733 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2734
2735 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2736 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2737
356363bf
FB		 2738 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2739 } else {
2740 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2741 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2742 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2743 }
2744
72246da4 2745 dep = dwc->eps[0];
39ebb05c 2746 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2747 if (ret) {
2748 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2749 return;
2750 }
2751
2752 dep = dwc->eps[1];
39ebb05c 2753 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2754 if (ret) {
2755 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2756 return;
2757 }
2758
2759 /*
2760 * Configure PHY via GUSB3PIPECTLn if required.
2761 *
2762 * Update GTXFIFOSIZn
2763 *
2764 * In both cases reset values should be sufficient.
2765 */
2766}
2767
2768static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2769{
72246da4
FB		 2770 /*
2771 * TODO take core out of low power mode when that's
2772 * implemented.
2773 */
2774
ad14d4e0
JL		 2775 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2776 spin_unlock(&dwc->lock);
2777 dwc->gadget_driver->resume(&dwc->gadget);
2778 spin_lock(&dwc->lock);
2779 }
72246da4
FB		 2780}
2781
2782static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2783 unsigned int evtinfo)
2784{
fae2b904 2785 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2786 unsigned int pwropt;
2787
2788 /*
2789 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2790 * Hibernation mode enabled which would show up when device detects
2791 * host-initiated U3 exit.
2792 *
2793 * In that case, device will generate a Link State Change Interrupt
2794 * from U3 to RESUME which is only necessary if Hibernation is
2795 * configured in.
2796 *
2797 * There are no functional changes due to such spurious event and we
2798 * just need to ignore it.
2799 *
2800 * Refers to:
2801 *
2802 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2803 * operational mode
2804 */
2805 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2806 if ((dwc->revision < DWC3_REVISION_250A) &&
2807 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2808 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2809 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2810 return;
2811 }
2812 }
fae2b904
FB		 2813
2814 /*
2815 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2816 * on the link partner, the USB session might do multiple entry/exit
2817 * of low power states before a transfer takes place.
2818 *
2819 * Due to this problem, we might experience lower throughput. The
2820 * suggested workaround is to disable DCTL[12:9] bits if we're
2821 * transitioning from U1/U2 to U0 and enable those bits again
2822 * after a transfer completes and there are no pending transfers
2823 * on any of the enabled endpoints.
2824 *
2825 * This is the first half of that workaround.
2826 *
2827 * Refers to:
2828 *
2829 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2830 * core send LGO_Ux entering U0
2831 */
2832 if (dwc->revision < DWC3_REVISION_183A) {
2833 if (next == DWC3_LINK_STATE_U0) {
2834 u32 u1u2;
2835 u32 reg;
2836
2837 switch (dwc->link_state) {
2838 case DWC3_LINK_STATE_U1:
2839 case DWC3_LINK_STATE_U2:
2840 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2841 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2842 | DWC3_DCTL_ACCEPTU2ENA
2843 | DWC3_DCTL_INITU1ENA
2844 | DWC3_DCTL_ACCEPTU1ENA);
2845
2846 if (!dwc->u1u2)
2847 dwc->u1u2 = reg & u1u2;
2848
2849 reg &= ~u1u2;
2850
2851 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2852 break;
2853 default:
2854 /* do nothing */
2855 break;
2856 }
2857 }
2858 }
2859
bc5ba2e0
FB		 2860 switch (next) {
2861 case DWC3_LINK_STATE_U1:
2862 if (dwc->speed == USB_SPEED_SUPER)
2863 dwc3_suspend_gadget(dwc);
2864 break;
2865 case DWC3_LINK_STATE_U2:
2866 case DWC3_LINK_STATE_U3:
2867 dwc3_suspend_gadget(dwc);
2868 break;
2869 case DWC3_LINK_STATE_RESUME:
2870 dwc3_resume_gadget(dwc);
2871 break;
2872 default:
2873 /* do nothing */
2874 break;
2875 }
2876
e57ebc1d 2877 dwc->link_state = next;
72246da4
FB		 2878}
2879
72704f87
BW		 2880static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2881 unsigned int evtinfo)
2882{
2883 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2884
2885 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2886 dwc3_suspend_gadget(dwc);
2887
2888 dwc->link_state = next;
2889}
2890
e1dadd3b
FB		 2891static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2892 unsigned int evtinfo)
2893{
2894 unsigned int is_ss = evtinfo & BIT(4);
2895
2896 /**
2897 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2898 * have a known issue which can cause USB CV TD.9.23 to fail
2899 * randomly.
2900 *
2901 * Because of this issue, core could generate bogus hibernation
2902 * events which SW needs to ignore.
2903 *
2904 * Refers to:
2905 *
2906 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2907 * Device Fallback from SuperSpeed
2908 */
2909 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2910 return;
2911
2912 /* enter hibernation here */
2913}
2914
72246da4
FB		 2915static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2916 const struct dwc3_event_devt *event)
2917{
2918 switch (event->type) {
2919 case DWC3_DEVICE_EVENT_DISCONNECT:
2920 dwc3_gadget_disconnect_interrupt(dwc);
2921 break;
2922 case DWC3_DEVICE_EVENT_RESET:
2923 dwc3_gadget_reset_interrupt(dwc);
2924 break;
2925 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2926 dwc3_gadget_conndone_interrupt(dwc);
2927 break;
2928 case DWC3_DEVICE_EVENT_WAKEUP:
2929 dwc3_gadget_wakeup_interrupt(dwc);
2930 break;
e1dadd3b
FB		 2931 case DWC3_DEVICE_EVENT_HIBER_REQ:
2932 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2933 "unexpected hibernation event\n"))
2934 break;
2935
2936 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2937 break;
72246da4
FB		 2938 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2939 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2940 break;
2941 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2942 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2943 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2944 /*
2945 * Ignore suspend event until the gadget enters into
2946 * USB_STATE_CONFIGURED state.
2947 */
2948 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2949 dwc3_gadget_suspend_interrupt(dwc,
2950 event->event_info);
2951 }
72246da4
FB		 2952 break;
2953 case DWC3_DEVICE_EVENT_SOF:
72246da4 2954 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2955 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2956 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2957 break;
2958 default:
e9f2aa87 2959 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2960 }
2961}
2962
2963static void dwc3_process_event_entry(struct dwc3 *dwc,
2964 const union dwc3_event *event)
2965{
43c96be1 2966 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2967
72246da4
FB		 2968 /* Endpoint IRQ, handle it and return early */
2969 if (event->type.is_devspec == 0) {
2970 /* depevt */
2971 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2972 }
2973
2974 switch (event->type.type) {
2975 case DWC3_EVENT_TYPE_DEV:
2976 dwc3_gadget_interrupt(dwc, &event->devt);
2977 break;
2978 /* REVISIT what to do with Carkit and I2C events ? */
2979 default:
2980 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2981 }
2982}
2983
dea520a4 2984static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2985{
dea520a4 2986 struct dwc3 *dwc = evt->dwc;
b15a762f 2987 irqreturn_t ret = IRQ_NONE;
f42f2447 2988 int left;
e8adfc30 2989 u32 reg;
b15a762f 2990
f42f2447 2991 left = evt->count;
b15a762f 2992
f42f2447
FB		 2993 if (!(evt->flags & DWC3_EVENT_PENDING))
2994 return IRQ_NONE;
b15a762f 2995
f42f2447
FB		 2996 while (left > 0) {
2997 union dwc3_event event;
b15a762f 2998
ebbb2d59 2999 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 3000
f42f2447 3001 dwc3_process_event_entry(dwc, &event);
b15a762f 3002
f42f2447
FB		 3003 /*
3004 * FIXME we wrap around correctly to the next entry as
3005 * almost all entries are 4 bytes in size. There is one
3006 * entry which has 12 bytes which is a regular entry
3007 * followed by 8 bytes data. ATM I don't know how
3008 * things are organized if we get next to the a
3009 * boundary so I worry about that once we try to handle
3010 * that.
3011 */
caefe6c7 3012 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 3013 left -= 4;
f42f2447 3014 }
b15a762f 3015
f42f2447
FB		 3016 evt->count = 0;
3017 evt->flags &= ~DWC3_EVENT_PENDING;
3018 ret = IRQ_HANDLED;
b15a762f 3019
f42f2447 3020 /* Unmask interrupt */
660e9bde 3021 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 3022 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 3023 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 3024
cf40b86b
JY		 3025 if (dwc->imod_interval) {
3026 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3027 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3028 }
3029
f42f2447
FB		 3030 return ret;
3031}
e8adfc30 3032
dea520a4 3033static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3034{
dea520a4
FB		 3035 struct dwc3_event_buffer *evt = _evt;
3036 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3037 unsigned long flags;
f42f2447 3038 irqreturn_t ret = IRQ_NONE;
f42f2447 3039
e5f68b4a 3040 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3041 ret = dwc3_process_event_buf(evt);
e5f68b4a 3042 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3043
3044 return ret;
3045}
3046
dea520a4 3047static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3048{
dea520a4 3049 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3050 u32 amount;
72246da4 3051 u32 count;
e8adfc30 3052 u32 reg;
72246da4 3053
fc8bb91b
FB		 3054 if (pm_runtime_suspended(dwc->dev)) {
3055 pm_runtime_get(dwc->dev);
3056 disable_irq_nosync(dwc->irq_gadget);
3057 dwc->pending_events = true;
3058 return IRQ_HANDLED;
3059 }
3060
660e9bde 3061 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3062 count &= DWC3_GEVNTCOUNT_MASK;
3063 if (!count)
3064 return IRQ_NONE;
3065
b15a762f
FB		 3066 evt->count = count;
3067 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3068
e8adfc30 3069 /* Mask interrupt */
660e9bde 3070 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3071 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3072 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3073
ebbb2d59
JY		 3074 amount = min(count, evt->length - evt->lpos);
3075 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3076
3077 if (amount < count)
3078 memcpy(evt->cache, evt->buf, count - amount);
3079
65aca320
JY		 3080 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3081
b15a762f 3082 return IRQ_WAKE_THREAD;
72246da4
FB		 3083}
3084
dea520a4 3085static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3086{
dea520a4 3087 struct dwc3_event_buffer *evt = _evt;
72246da4 3088
dea520a4 3089 return dwc3_check_event_buf(evt);
72246da4
FB		 3090}
3091
6db3812e
FB		 3092static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3093{
3094 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3095 int irq;
3096
3097 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3098 if (irq > 0)
3099 goto out;
3100
3101 if (irq == -EPROBE_DEFER)
3102 goto out;
3103
3104 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3105 if (irq > 0)
3106 goto out;
3107
3108 if (irq == -EPROBE_DEFER)
3109 goto out;
3110
3111 irq = platform_get_irq(dwc3_pdev, 0);
3112 if (irq > 0)
3113 goto out;
3114
3115 if (irq != -EPROBE_DEFER)
3116 dev_err(dwc->dev, "missing peripheral IRQ\n");
3117
3118 if (!irq)
3119 irq = -EINVAL;
3120
3121out:
3122 return irq;
3123}
3124
72246da4
FB		 3125/**
3126 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3127 * @dwc: pointer to our controller context structure
72246da4
FB		 3128 *
3129 * Returns 0 on success otherwise negative errno.
3130 */
41ac7b3a 3131int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3132{
6db3812e
FB		 3133 int ret;
3134 int irq;
9522def4 3135
6db3812e
FB		 3136 irq = dwc3_gadget_get_irq(dwc);
3137 if (irq < 0) {
3138 ret = irq;
3139 goto err0;
9522def4
RQ		 3140 }
3141
3142 dwc->irq_gadget = irq;
72246da4 3143
d64ff406 3144 dwc->ctrl_req = dma_alloc_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3145 &dwc->ctrl_req_addr, GFP_KERNEL);
3146 if (!dwc->ctrl_req) {
3147 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3148 ret = -ENOMEM;
3149 goto err0;
3150 }
3151
d64ff406
AB		 3152 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3153 sizeof(*dwc->ep0_trb) * 2,
3154 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3155 if (!dwc->ep0_trb) {
3156 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3157 ret = -ENOMEM;
3158 goto err1;
3159 }
3160
3ef35faf 3161 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 3162 if (!dwc->setup_buf) {
72246da4
FB		 3163 ret = -ENOMEM;
3164 goto err2;
3165 }
3166
d64ff406 3167 dwc->ep0_bounce = dma_alloc_coherent(dwc->sysdev,
3ef35faf
FB		 3168 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3169 GFP_KERNEL);
5812b1c2
FB		 3170 if (!dwc->ep0_bounce) {
3171 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3172 ret = -ENOMEM;
3173 goto err3;
3174 }
3175
04c03d10
FB		 3176 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3177 if (!dwc->zlp_buf) {
3178 ret = -ENOMEM;
3179 goto err4;
3180 }
3181
905dc04e
FB		 3182 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3183 &dwc->bounce_addr, GFP_KERNEL);
3184 if (!dwc->bounce) {
3185 ret = -ENOMEM;
3186 goto err5;
3187 }
3188
bb014736
BW		 3189 init_completion(&dwc->ep0_in_setup);
3190
72246da4 3191 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3192 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3193 dwc->gadget.sg_supported = true;
72246da4 3194 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3195 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3196
b9e51b2b
BM		 3197 /*
3198 * FIXME We might be setting max_speed to <SUPER, however versions
3199 * <2.20a of dwc3 have an issue with metastability (documented
3200 * elsewhere in this driver) which tells us we can't set max speed to
3201 * anything lower than SUPER.
3202 *
3203 * Because gadget.max_speed is only used by composite.c and function
3204 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3205 * to happen so we avoid sending SuperSpeed Capability descriptor
3206 * together with our BOS descriptor as that could confuse host into
3207 * thinking we can handle super speed.
3208 *
3209 * Note that, in fact, we won't even support GetBOS requests when speed
3210 * is less than super speed because we don't have means, yet, to tell
3211 * composite.c that we are USB 2.0 + LPM ECN.
3212 */
3213 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3214 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3215 dwc->revision);
3216
3217 dwc->gadget.max_speed = dwc->maximum_speed;
3218
72246da4
FB		 3219 /*
3220 * REVISIT: Here we should clear all pending IRQs to be
3221 * sure we're starting from a well known location.
3222 */
3223
f3bcfc7e 3224 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3225 if (ret)
905dc04e 3226 goto err6;
72246da4 3227
72246da4
FB		 3228 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3229 if (ret) {
3230 dev_err(dwc->dev, "failed to register udc\n");
905dc04e 3231 goto err6;
72246da4
FB		 3232 }
3233
3234 return 0;
905dc04e
FB		 3235err6:
3236 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3237 dwc->bounce_addr);
72246da4 3238
04c03d10
FB		 3239err5:
3240 kfree(dwc->zlp_buf);
3241
5812b1c2 3242err4:
e1f80467 3243 dwc3_gadget_free_endpoints(dwc);
d64ff406 3244 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3245 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3246
72246da4 3247err3:
0fc9a1be 3248 kfree(dwc->setup_buf);
72246da4
FB		 3249
3250err2:
d64ff406 3251 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3252 dwc->ep0_trb, dwc->ep0_trb_addr);
3253
3254err1:
d64ff406 3255 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3256 dwc->ctrl_req, dwc->ctrl_req_addr);
3257
3258err0:
3259 return ret;
3260}
3261
7415f17c
FB		 3262/* -------------------------------------------------------------------------- */
3263
72246da4
FB		 3264void dwc3_gadget_exit(struct dwc3 *dwc)
3265{
72246da4 3266 usb_del_gadget_udc(&dwc->gadget);
72246da4 3267
72246da4
FB		 3268 dwc3_gadget_free_endpoints(dwc);
3269
905dc04e
FB		 3270 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3271 dwc->bounce_addr);
d64ff406 3272 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3273 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3274
0fc9a1be 3275 kfree(dwc->setup_buf);
04c03d10 3276 kfree(dwc->zlp_buf);
72246da4 3277
d64ff406 3278 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3279 dwc->ep0_trb, dwc->ep0_trb_addr);
3280
d64ff406 3281 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4 3282 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3283}
7415f17c 3284
0b0231aa 3285int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3286{
9772b47a
RQ		 3287 if (!dwc->gadget_driver)
3288 return 0;
3289
1551e35e 3290 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3291 dwc3_disconnect_gadget(dwc);
3292 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3293
3294 return 0;
3295}
3296
3297int dwc3_gadget_resume(struct dwc3 *dwc)
3298{
7415f17c
FB		 3299 int ret;
3300
9772b47a
RQ		 3301 if (!dwc->gadget_driver)
3302 return 0;
3303
9f8a67b6
FB		 3304 ret = __dwc3_gadget_start(dwc);
3305 if (ret < 0)
7415f17c
FB		 3306 goto err0;
3307
9f8a67b6
FB		 3308 ret = dwc3_gadget_run_stop(dwc, true, false);
3309 if (ret < 0)
7415f17c
FB		 3310 goto err1;
3311
7415f17c
FB		 3312 return 0;
3313
3314err1:
9f8a67b6 3315 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3316
3317err0:
3318 return ret;
3319}
fc8bb91b
FB		 3320
3321void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3322{
3323 if (dwc->pending_events) {
3324 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3325 dwc->pending_events = false;
3326 enable_irq(dwc->irq_gadget);
3327 }
3328}
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