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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
62fb45d3 GKH |
49 | case USB_TEST_J: |
50 | case USB_TEST_K: | |
51 | case USB_TEST_SE0_NAK: | |
52 | case USB_TEST_PACKET: | |
53 | case USB_TEST_FORCE_ENABLE: | |
04a9bfcd FB |
54 | reg |= mode << 1; |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
9af21dd6 | 98 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 PZ |
99 | while (--retries) { |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
9af21dd6 | 125 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
126 | return 0; |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
e319bd62 FB |
230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
231 | u32 param) | |
b09bb642 FB |
232 | { |
233 | u32 timeout = 500; | |
71f7e702 | 234 | int status = 0; |
0fe886cd | 235 | int ret = 0; |
b09bb642 FB |
236 | u32 reg; |
237 | ||
238 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
239 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
240 | ||
241 | do { | |
242 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
243 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
244 | status = DWC3_DGCMD_STATUS(reg); |
245 | if (status) | |
0fe886cd FB |
246 | ret = -EINVAL; |
247 | break; | |
b09bb642 | 248 | } |
e3aee486 | 249 | } while (--timeout); |
0fe886cd FB |
250 | |
251 | if (!timeout) { | |
0fe886cd | 252 | ret = -ETIMEDOUT; |
71f7e702 | 253 | status = -ETIMEDOUT; |
0fe886cd FB |
254 | } |
255 | ||
71f7e702 FB |
256 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
257 | ||
0fe886cd | 258 | return ret; |
b09bb642 FB |
259 | } |
260 | ||
c36d8e94 FB |
261 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
262 | ||
bfad65ee FB |
263 | /** |
264 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
265 | * @dep: the endpoint to which the command is going to be issued | |
266 | * @cmd: the command to be issued | |
267 | * @params: parameters to the command | |
268 | * | |
269 | * Caller should handle locking. This function will issue @cmd with given | |
270 | * @params to @dep and wait for its completion. | |
271 | */ | |
e319bd62 | 272 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 273 | struct dwc3_gadget_ep_cmd_params *params) |
72246da4 | 274 | { |
8897a761 | 275 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 276 | struct dwc3 *dwc = dep->dwc; |
1c0e69ae | 277 | u32 timeout = 5000; |
87dd9611 | 278 | u32 saved_config = 0; |
72246da4 FB |
279 | u32 reg; |
280 | ||
0933df15 | 281 | int cmd_status = 0; |
c0ca324d | 282 | int ret = -EINVAL; |
72246da4 | 283 | |
2b0f11df | 284 | /* |
87dd9611 TN |
285 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
286 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
287 | * endpoint command. | |
2b0f11df | 288 | * |
87dd9611 TN |
289 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
290 | * settings. Restore them after the command is completed. | |
291 | * | |
292 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 293 | */ |
e81a7018 | 294 | if (dwc->gadget->speed <= USB_SPEED_HIGH) { |
ab2a92e7 FB |
295 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
296 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 297 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 298 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 299 | } |
87dd9611 TN |
300 | |
301 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
302 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
303 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
304 | } | |
305 | ||
306 | if (saved_config) | |
307 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
308 | } |
309 | ||
5999914f | 310 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c560e763 | 311 | int link_state; |
c36d8e94 | 312 | |
c560e763 TN |
313 | link_state = dwc3_gadget_get_link_state(dwc); |
314 | if (link_state == DWC3_LINK_STATE_U1 || | |
315 | link_state == DWC3_LINK_STATE_U2 || | |
316 | link_state == DWC3_LINK_STATE_U3) { | |
c36d8e94 FB |
317 | ret = __dwc3_gadget_wakeup(dwc); |
318 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
319 | ret); | |
320 | } | |
321 | } | |
322 | ||
2eb88016 FB |
323 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
324 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
325 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 326 | |
8897a761 FB |
327 | /* |
328 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
329 | * not relying on XferNotReady, we can make use of a special "No | |
330 | * Response Update Transfer" command where we should clear both CmdAct | |
331 | * and CmdIOC bits. | |
332 | * | |
333 | * With this, we don't need to wait for command completion and can | |
334 | * straight away issue further commands to the endpoint. | |
335 | * | |
336 | * NOTICE: We're making an assumption that control endpoints will never | |
337 | * make use of Update Transfer command. This is a safe assumption | |
338 | * because we can never have more than one request at a time with | |
339 | * Control Endpoints. If anybody changes that assumption, this chunk | |
340 | * needs to be updated accordingly. | |
341 | */ | |
342 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
343 | !usb_endpoint_xfer_isoc(desc)) | |
344 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
345 | else | |
346 | cmd |= DWC3_DEPCMD_CMDACT; | |
347 | ||
348 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 349 | do { |
2eb88016 | 350 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 352 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 353 | |
7b9cc7a2 KL |
354 | switch (cmd_status) { |
355 | case 0: | |
356 | ret = 0; | |
357 | break; | |
358 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
f7ac582e TN |
359 | dev_WARN(dwc->dev, "No resource for %s\n", |
360 | dep->name); | |
7b9cc7a2 | 361 | ret = -EINVAL; |
c0ca324d | 362 | break; |
7b9cc7a2 KL |
363 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
364 | /* | |
365 | * SW issues START TRANSFER command to | |
366 | * isochronous ep with future frame interval. If | |
367 | * future interval time has already passed when | |
368 | * core receives the command, it will respond | |
369 | * with an error status of 'Bus Expiry'. | |
370 | * | |
371 | * Instead of always returning -EINVAL, let's | |
372 | * give a hint to the gadget driver that this is | |
373 | * the case by returning -EAGAIN. | |
374 | */ | |
7b9cc7a2 KL |
375 | ret = -EAGAIN; |
376 | break; | |
377 | default: | |
378 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
379 | } | |
380 | ||
c0ca324d | 381 | break; |
72246da4 | 382 | } |
f6bb225b | 383 | } while (--timeout); |
72246da4 | 384 | |
f6bb225b | 385 | if (timeout == 0) { |
f6bb225b | 386 | ret = -ETIMEDOUT; |
0933df15 | 387 | cmd_status = -ETIMEDOUT; |
f6bb225b | 388 | } |
c0ca324d | 389 | |
0933df15 FB |
390 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
391 | ||
9bc3395c TN |
392 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
393 | if (ret == 0) | |
394 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
395 | ||
396 | if (ret != -ETIMEDOUT) | |
397 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
398 | } |
399 | ||
87dd9611 | 400 | if (saved_config) { |
2b0f11df | 401 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 402 | reg |= saved_config; |
2b0f11df FB |
403 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
404 | } | |
405 | ||
c0ca324d | 406 | return ret; |
72246da4 FB |
407 | } |
408 | ||
50c763f8 JY |
409 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
410 | { | |
411 | struct dwc3 *dwc = dep->dwc; | |
412 | struct dwc3_gadget_ep_cmd_params params; | |
413 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
414 | ||
415 | /* | |
416 | * As of core revision 2.60a the recommended programming model | |
417 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
418 | * command for IN endpoints. This is to prevent an issue where | |
419 | * some (non-compliant) hosts may not send ACK TPs for pending | |
420 | * IN transfers due to a mishandled error condition. Synopsys | |
421 | * STAR 9000614252. | |
422 | */ | |
9af21dd6 TN |
423 | if (dep->direction && |
424 | !DWC3_VER_IS_PRIOR(DWC3, 260A) && | |
e81a7018 | 425 | (dwc->gadget->speed >= USB_SPEED_SUPER)) |
50c763f8 JY |
426 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
427 | ||
428 | memset(¶ms, 0, sizeof(params)); | |
429 | ||
2cd4718d | 430 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
431 | } |
432 | ||
72246da4 | 433 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 434 | struct dwc3_trb *trb) |
72246da4 | 435 | { |
c439ef87 | 436 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
437 | |
438 | return dep->trb_pool_dma + offset; | |
439 | } | |
440 | ||
441 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
442 | { | |
443 | struct dwc3 *dwc = dep->dwc; | |
444 | ||
445 | if (dep->trb_pool) | |
446 | return 0; | |
447 | ||
d64ff406 | 448 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
449 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
450 | &dep->trb_pool_dma, GFP_KERNEL); | |
451 | if (!dep->trb_pool) { | |
452 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
453 | dep->name); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
461 | { | |
462 | struct dwc3 *dwc = dep->dwc; | |
463 | ||
d64ff406 | 464 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
465 | dep->trb_pool, dep->trb_pool_dma); |
466 | ||
467 | dep->trb_pool = NULL; | |
468 | dep->trb_pool_dma = 0; | |
469 | } | |
470 | ||
20d1d43f FB |
471 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
472 | { | |
473 | struct dwc3_gadget_ep_cmd_params params; | |
474 | ||
475 | memset(¶ms, 0x00, sizeof(params)); | |
476 | ||
477 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
478 | ||
479 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
480 | ¶ms); | |
481 | } | |
c4509601 JY |
482 | |
483 | /** | |
bfad65ee | 484 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
485 | * @dep: endpoint that is being enabled |
486 | * | |
bfad65ee FB |
487 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
488 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 489 | * |
bfad65ee FB |
490 | * The assignment of transfer resources cannot perfectly follow the data book |
491 | * due to the fact that the controller driver does not have all knowledge of the | |
492 | * configuration in advance. It is given this information piecemeal by the | |
493 | * composite gadget framework after every SET_CONFIGURATION and | |
494 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
495 | * scenario can cause errors. For two reasons: | |
c4509601 | 496 | * |
bfad65ee FB |
497 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
498 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
499 | * incorrect in the scenario of multiple interfaces. | |
500 | * | |
501 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
502 | * endpoint on alt setting (8.1.6). |
503 | * | |
504 | * The following simplified method is used instead: | |
505 | * | |
bfad65ee FB |
506 | * All hardware endpoints can be assigned a transfer resource and this setting |
507 | * will stay persistent until either a core reset or hibernation. So whenever we | |
508 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
509 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
510 | * guaranteed that there are as many transfer resources as endpoints. |
511 | * | |
bfad65ee FB |
512 | * This function is called for each endpoint when it is being enabled but is |
513 | * triggered only when called for EP0-out, which always happens first, and which | |
514 | * should only happen in one of the above conditions. | |
c4509601 | 515 | */ |
b07c2db8 | 516 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
517 | { |
518 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 519 | struct dwc3 *dwc; |
72246da4 | 520 | u32 cmd; |
c4509601 JY |
521 | int i; |
522 | int ret; | |
523 | ||
524 | if (dep->number) | |
525 | return 0; | |
72246da4 FB |
526 | |
527 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 528 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 529 | dwc = dep->dwc; |
72246da4 | 530 | |
2cd4718d | 531 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
532 | if (ret) |
533 | return ret; | |
534 | ||
535 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
536 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 537 | |
c4509601 JY |
538 | if (!dep) |
539 | continue; | |
540 | ||
b07c2db8 | 541 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
542 | if (ret) |
543 | return ret; | |
72246da4 FB |
544 | } |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
b07c2db8 | 549 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 550 | { |
39ebb05c JY |
551 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
552 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 553 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 554 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 555 | |
39ebb05c JY |
556 | comp_desc = dep->endpoint.comp_desc; |
557 | desc = dep->endpoint.desc; | |
558 | ||
72246da4 FB |
559 | memset(¶ms, 0x00, sizeof(params)); |
560 | ||
dc1c70a7 | 561 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
562 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
563 | ||
564 | /* Burst size is only needed in SuperSpeed mode */ | |
e81a7018 | 565 | if (dwc->gadget->speed >= USB_SPEED_SUPER) { |
676e3497 | 566 | u32 burst = dep->endpoint.maxburst; |
e319bd62 | 567 | |
676e3497 | 568 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 569 | } |
72246da4 | 570 | |
a2d23f08 FB |
571 | params.param0 |= action; |
572 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 573 | params.param2 |= dep->saved_state; |
265b70a7 | 574 | |
4bc48c97 FB |
575 | if (usb_endpoint_xfer_control(desc)) |
576 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
577 | |
578 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
579 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 580 | |
18b7ede5 | 581 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 | 582 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
548f8b31 | 583 | | DWC3_DEPCFG_XFER_COMPLETE_EN |
dc1c70a7 | 584 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
879631aa FB |
585 | dep->stream_capable = true; |
586 | } | |
587 | ||
0b93a4c8 | 588 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 589 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
590 | |
591 | /* | |
592 | * We are doing 1:1 mapping for endpoints, meaning | |
593 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
594 | * so on. We consider the direction bit as part of the physical | |
595 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
596 | */ | |
dc1c70a7 | 597 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
598 | |
599 | /* | |
600 | * We must use the lower 16 TX FIFOs even though | |
601 | * HW might have more | |
602 | */ | |
603 | if (dep->direction) | |
dc1c70a7 | 604 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
605 | |
606 | if (desc->bInterval) { | |
a1679af8 TN |
607 | u8 bInterval_m1; |
608 | ||
609 | /* | |
3232a3ce TN |
610 | * Valid range for DEPCFG.bInterval_m1 is from 0 to 13. |
611 | * | |
612 | * NOTE: The programming guide incorrectly stated bInterval_m1 | |
613 | * must be set to 0 when operating in fullspeed. Internally the | |
614 | * controller does not have this limitation. See DWC_usb3x | |
615 | * programming guide section 3.2.2.1. | |
a1679af8 TN |
616 | */ |
617 | bInterval_m1 = min_t(u8, desc->bInterval - 1, 13); | |
a1679af8 | 618 | |
4b049f55 TN |
619 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT && |
620 | dwc->gadget->speed == USB_SPEED_FULL) | |
621 | dep->interval = desc->bInterval; | |
622 | else | |
623 | dep->interval = 1 << (desc->bInterval - 1); | |
624 | ||
a1679af8 | 625 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1); |
72246da4 FB |
626 | } |
627 | ||
2cd4718d | 628 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
629 | } |
630 | ||
140ca4cf TN |
631 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
632 | bool interrupt); | |
633 | ||
9f607a30 WC |
634 | /** |
635 | * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value | |
636 | * @dwc: pointer to the DWC3 context | |
637 | * @nfifos: number of fifos to calculate for | |
638 | * | |
639 | * Calculates the size value based on the equation below: | |
640 | * | |
641 | * DWC3 revision 280A and prior: | |
642 | * fifo_size = mult * (max_packet / mdwidth) + 1; | |
643 | * | |
644 | * DWC3 revision 290A and onwards: | |
645 | * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 | |
646 | * | |
647 | * The max packet size is set to 1024, as the txfifo requirements mainly apply | |
648 | * to super speed USB use cases. However, it is safe to overestimate the fifo | |
649 | * allocations for other scenarios, i.e. high speed USB. | |
650 | */ | |
651 | static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult) | |
652 | { | |
653 | int max_packet = 1024; | |
654 | int fifo_size; | |
655 | int mdwidth; | |
656 | ||
657 | mdwidth = dwc3_mdwidth(dwc); | |
658 | ||
659 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
660 | mdwidth >>= 3; | |
661 | ||
662 | if (DWC3_VER_IS_PRIOR(DWC3, 290A)) | |
663 | fifo_size = mult * (max_packet / mdwidth) + 1; | |
664 | else | |
665 | fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1; | |
666 | return fifo_size; | |
667 | } | |
668 | ||
669 | /** | |
670 | * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation | |
671 | * @dwc: pointer to the DWC3 context | |
672 | * | |
673 | * Iterates through all the endpoint registers and clears the previous txfifo | |
674 | * allocations. | |
675 | */ | |
676 | void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) | |
677 | { | |
678 | struct dwc3_ep *dep; | |
679 | int fifo_depth; | |
680 | int size; | |
681 | int num; | |
682 | ||
683 | if (!dwc->do_fifo_resize) | |
684 | return; | |
685 | ||
686 | /* Read ep0IN related TXFIFO size */ | |
687 | dep = dwc->eps[1]; | |
688 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); | |
689 | if (DWC3_IP_IS(DWC3)) | |
690 | fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size); | |
691 | else | |
692 | fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
693 | ||
694 | dwc->last_fifo_depth = fifo_depth; | |
695 | /* Clear existing TXFIFO for all IN eps except ep0 */ | |
696 | for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM); | |
697 | num += 2) { | |
698 | dep = dwc->eps[num]; | |
699 | /* Don't change TXFRAMNUM on usb31 version */ | |
700 | size = DWC3_IP_IS(DWC3) ? 0 : | |
701 | dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) & | |
702 | DWC31_GTXFIFOSIZ_TXFRAMNUM; | |
703 | ||
704 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size); | |
705 | } | |
706 | dwc->num_ep_resized = 0; | |
707 | } | |
708 | ||
709 | /* | |
710 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
711 | * @dwc: pointer to our context structure | |
712 | * | |
713 | * This function will a best effort FIFO allocation in order | |
714 | * to improve FIFO usage and throughput, while still allowing | |
715 | * us to enable as many endpoints as possible. | |
716 | * | |
717 | * Keep in mind that this operation will be highly dependent | |
718 | * on the configured size for RAM1 - which contains TxFifo -, | |
719 | * the amount of endpoints enabled on coreConsultant tool, and | |
720 | * the width of the Master Bus. | |
721 | * | |
722 | * In general, FIFO depths are represented with the following equation: | |
723 | * | |
724 | * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 | |
725 | * | |
726 | * In conjunction with dwc3_gadget_check_config(), this resizing logic will | |
727 | * ensure that all endpoints will have enough internal memory for one max | |
728 | * packet per endpoint. | |
729 | */ | |
730 | static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) | |
731 | { | |
732 | struct dwc3 *dwc = dep->dwc; | |
733 | int fifo_0_start; | |
734 | int ram1_depth; | |
735 | int fifo_size; | |
736 | int min_depth; | |
737 | int num_in_ep; | |
738 | int remaining; | |
739 | int num_fifos = 1; | |
740 | int fifo; | |
741 | int tmp; | |
742 | ||
743 | if (!dwc->do_fifo_resize) | |
744 | return 0; | |
745 | ||
746 | /* resize IN endpoints except ep0 */ | |
747 | if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1) | |
748 | return 0; | |
749 | ||
750 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
751 | ||
752 | if ((dep->endpoint.maxburst > 1 && | |
753 | usb_endpoint_xfer_bulk(dep->endpoint.desc)) || | |
754 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
755 | num_fifos = 3; | |
756 | ||
757 | if (dep->endpoint.maxburst > 6 && | |
758 | usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31)) | |
759 | num_fifos = dwc->tx_fifo_resize_max_num; | |
760 | ||
761 | /* FIFO size for a single buffer */ | |
762 | fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1); | |
763 | ||
764 | /* Calculate the number of remaining EPs w/o any FIFO */ | |
765 | num_in_ep = dwc->max_cfg_eps; | |
766 | num_in_ep -= dwc->num_ep_resized; | |
767 | ||
768 | /* Reserve at least one FIFO for the number of IN EPs */ | |
769 | min_depth = num_in_ep * (fifo + 1); | |
770 | remaining = ram1_depth - min_depth - dwc->last_fifo_depth; | |
771 | remaining = max_t(int, 0, remaining); | |
772 | /* | |
773 | * We've already reserved 1 FIFO per EP, so check what we can fit in | |
774 | * addition to it. If there is not enough remaining space, allocate | |
775 | * all the remaining space to the EP. | |
776 | */ | |
777 | fifo_size = (num_fifos - 1) * fifo; | |
778 | if (remaining < fifo_size) | |
779 | fifo_size = remaining; | |
780 | ||
781 | fifo_size += fifo; | |
782 | /* Last increment according to the TX FIFO size equation */ | |
783 | fifo_size++; | |
784 | ||
785 | /* Check if TXFIFOs start at non-zero addr */ | |
786 | tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); | |
787 | fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp); | |
788 | ||
789 | fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16)); | |
790 | if (DWC3_IP_IS(DWC3)) | |
791 | dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size); | |
792 | else | |
793 | dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size); | |
794 | ||
795 | /* Check fifo size allocation doesn't exceed available RAM size. */ | |
796 | if (dwc->last_fifo_depth >= ram1_depth) { | |
797 | dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n", | |
798 | dwc->last_fifo_depth, ram1_depth, | |
799 | dep->endpoint.name, fifo_size); | |
800 | if (DWC3_IP_IS(DWC3)) | |
801 | fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size); | |
802 | else | |
803 | fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size); | |
804 | ||
805 | dwc->last_fifo_depth -= fifo_size; | |
806 | return -ENOMEM; | |
807 | } | |
808 | ||
809 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size); | |
810 | dwc->num_ep_resized++; | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
72246da4 | 815 | /** |
bfad65ee | 816 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 817 | * @dep: endpoint to be initialized |
a2d23f08 | 818 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 819 | * |
bfad65ee FB |
820 | * Caller should take care of locking. Execute all necessary commands to |
821 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 822 | */ |
a2d23f08 | 823 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 824 | { |
39ebb05c | 825 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 826 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 827 | |
72246da4 | 828 | u32 reg; |
b09e99ee | 829 | int ret; |
72246da4 FB |
830 | |
831 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
9f607a30 WC |
832 | ret = dwc3_gadget_resize_tx_fifos(dep); |
833 | if (ret) | |
834 | return ret; | |
835 | ||
b07c2db8 | 836 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
837 | if (ret) |
838 | return ret; | |
839 | } | |
840 | ||
b07c2db8 | 841 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
842 | if (ret) |
843 | return ret; | |
844 | ||
845 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
846 | struct dwc3_trb *trb_st_hw; |
847 | struct dwc3_trb *trb_link; | |
72246da4 | 848 | |
72246da4 FB |
849 | dep->type = usb_endpoint_type(desc); |
850 | dep->flags |= DWC3_EP_ENABLED; | |
851 | ||
852 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
853 | reg |= DWC3_DALEPENA_EP(dep->number); | |
854 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
855 | ||
36b68aae | 856 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 857 | goto out; |
72246da4 | 858 | |
0d25744a JY |
859 | /* Initialize the TRB ring */ |
860 | dep->trb_dequeue = 0; | |
861 | dep->trb_enqueue = 0; | |
862 | memset(dep->trb_pool, 0, | |
863 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
864 | ||
36b68aae | 865 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
866 | trb_st_hw = &dep->trb_pool[0]; |
867 | ||
f6bafc6a | 868 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
869 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
870 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
871 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
872 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
873 | } |
874 | ||
a97ea994 FB |
875 | /* |
876 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
877 | * Response Update Transfer command. | |
878 | */ | |
140ca4cf | 879 | if (usb_endpoint_xfer_bulk(desc) || |
52fcc0be | 880 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
881 | struct dwc3_gadget_ep_cmd_params params; |
882 | struct dwc3_trb *trb; | |
883 | dma_addr_t trb_dma; | |
884 | u32 cmd; | |
885 | ||
886 | memset(¶ms, 0, sizeof(params)); | |
887 | trb = &dep->trb_pool[0]; | |
888 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
889 | ||
890 | params.param0 = upper_32_bits(trb_dma); | |
891 | params.param1 = lower_32_bits(trb_dma); | |
892 | ||
893 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
894 | ||
895 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
896 | if (ret < 0) | |
897 | return ret; | |
140ca4cf TN |
898 | |
899 | if (dep->stream_capable) { | |
900 | /* | |
901 | * For streams, at start, there maybe a race where the | |
902 | * host primes the endpoint before the function driver | |
903 | * queues a request to initiate a stream. In that case, | |
904 | * the controller will not see the prime to generate the | |
905 | * ERDY and start stream. To workaround this, issue a | |
906 | * no-op TRB as normal, but end it immediately. As a | |
907 | * result, when the function driver queues the request, | |
908 | * the next START_TRANSFER command will cause the | |
909 | * controller to generate an ERDY to initiate the | |
910 | * stream. | |
911 | */ | |
912 | dwc3_stop_active_transfer(dep, true, true); | |
913 | ||
914 | /* | |
915 | * All stream eps will reinitiate stream on NoStream | |
916 | * rejection until we can determine that the host can | |
917 | * prime after the first transfer. | |
ddae7979 TN |
918 | * |
919 | * However, if the controller is capable of | |
920 | * TXF_FLUSH_BYPASS, then IN direction endpoints will | |
921 | * automatically restart the stream without the driver | |
922 | * initiation. | |
140ca4cf | 923 | */ |
ddae7979 TN |
924 | if (!dep->direction || |
925 | !(dwc->hwparams.hwparams9 & | |
926 | DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS)) | |
927 | dep->flags |= DWC3_EP_FORCE_RESTART_STREAM; | |
140ca4cf | 928 | } |
a97ea994 FB |
929 | } |
930 | ||
2870e501 FB |
931 | out: |
932 | trace_dwc3_gadget_ep_enable(dep); | |
933 | ||
72246da4 FB |
934 | return 0; |
935 | } | |
936 | ||
624407f9 | 937 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
938 | { |
939 | struct dwc3_request *req; | |
940 | ||
c5353b22 | 941 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 942 | |
0e146028 FB |
943 | /* - giveback all requests to gadget driver */ |
944 | while (!list_empty(&dep->started_list)) { | |
945 | req = next_request(&dep->started_list); | |
1591633e | 946 | |
0e146028 | 947 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
948 | } |
949 | ||
aa3342c8 FB |
950 | while (!list_empty(&dep->pending_list)) { |
951 | req = next_request(&dep->pending_list); | |
72246da4 | 952 | |
d8eca64e FB |
953 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
954 | } | |
955 | ||
956 | while (!list_empty(&dep->cancelled_list)) { | |
957 | req = next_request(&dep->cancelled_list); | |
958 | ||
624407f9 | 959 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 960 | } |
72246da4 FB |
961 | } |
962 | ||
963 | /** | |
bfad65ee | 964 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
965 | * @dep: the endpoint to disable |
966 | * | |
bfad65ee FB |
967 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
968 | * requests which are currently being processed by the hardware and those which | |
969 | * are not yet scheduled. | |
970 | * | |
624407f9 | 971 | * Caller should take care of locking. |
72246da4 | 972 | */ |
72246da4 FB |
973 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
974 | { | |
975 | struct dwc3 *dwc = dep->dwc; | |
976 | u32 reg; | |
977 | ||
2870e501 | 978 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 979 | |
687ef981 FB |
980 | /* make sure HW endpoint isn't stalled */ |
981 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 982 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 983 | |
72246da4 FB |
984 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
985 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
986 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
987 | ||
39ebb05c JY |
988 | /* Clear out the ep descriptors for non-ep0 */ |
989 | if (dep->number > 1) { | |
990 | dep->endpoint.comp_desc = NULL; | |
991 | dep->endpoint.desc = NULL; | |
992 | } | |
993 | ||
f09ddcfc WC |
994 | dwc3_remove_requests(dwc, dep); |
995 | ||
5aef6297 WC |
996 | dep->stream_capable = false; |
997 | dep->type = 0; | |
998 | dep->flags = 0; | |
999 | ||
72246da4 FB |
1000 | return 0; |
1001 | } | |
1002 | ||
1003 | /* -------------------------------------------------------------------------- */ | |
1004 | ||
1005 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
1006 | const struct usb_endpoint_descriptor *desc) | |
1007 | { | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | ||
1011 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
1012 | { | |
1013 | return -EINVAL; | |
1014 | } | |
1015 | ||
1016 | /* -------------------------------------------------------------------------- */ | |
1017 | ||
1018 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
1019 | const struct usb_endpoint_descriptor *desc) | |
1020 | { | |
1021 | struct dwc3_ep *dep; | |
1022 | struct dwc3 *dwc; | |
1023 | unsigned long flags; | |
1024 | int ret; | |
1025 | ||
1026 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
1027 | pr_debug("dwc3: invalid parameters\n"); | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | ||
1031 | if (!desc->wMaxPacketSize) { | |
1032 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
1033 | return -EINVAL; | |
1034 | } | |
1035 | ||
1036 | dep = to_dwc3_ep(ep); | |
1037 | dwc = dep->dwc; | |
1038 | ||
95ca961c FB |
1039 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
1040 | "%s is already enabled\n", | |
1041 | dep->name)) | |
c6f83f38 | 1042 | return 0; |
c6f83f38 | 1043 | |
72246da4 | 1044 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 1045 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
1046 | spin_unlock_irqrestore(&dwc->lock, flags); |
1047 | ||
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
1052 | { | |
1053 | struct dwc3_ep *dep; | |
1054 | struct dwc3 *dwc; | |
1055 | unsigned long flags; | |
1056 | int ret; | |
1057 | ||
1058 | if (!ep) { | |
1059 | pr_debug("dwc3: invalid parameters\n"); | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | ||
1063 | dep = to_dwc3_ep(ep); | |
1064 | dwc = dep->dwc; | |
1065 | ||
95ca961c FB |
1066 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
1067 | "%s is already disabled\n", | |
1068 | dep->name)) | |
72246da4 | 1069 | return 0; |
72246da4 | 1070 | |
72246da4 FB |
1071 | spin_lock_irqsave(&dwc->lock, flags); |
1072 | ret = __dwc3_gadget_ep_disable(dep); | |
1073 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1074 | ||
1075 | return ret; | |
1076 | } | |
1077 | ||
1078 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 1079 | gfp_t gfp_flags) |
72246da4 FB |
1080 | { |
1081 | struct dwc3_request *req; | |
1082 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
1083 | |
1084 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 1085 | if (!req) |
72246da4 | 1086 | return NULL; |
72246da4 | 1087 | |
31a2f5a7 | 1088 | req->direction = dep->direction; |
72246da4 FB |
1089 | req->epnum = dep->number; |
1090 | req->dep = dep; | |
a3af5e3a | 1091 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 1092 | |
2c4cbe6e FB |
1093 | trace_dwc3_alloc_request(req); |
1094 | ||
72246da4 FB |
1095 | return &req->request; |
1096 | } | |
1097 | ||
1098 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
1099 | struct usb_request *request) | |
1100 | { | |
1101 | struct dwc3_request *req = to_dwc3_request(request); | |
1102 | ||
2c4cbe6e | 1103 | trace_dwc3_free_request(req); |
72246da4 FB |
1104 | kfree(req); |
1105 | } | |
1106 | ||
42626919 FB |
1107 | /** |
1108 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
1109 | * @dep: The endpoint with the TRB ring | |
1110 | * @index: The index of the current TRB in the ring | |
1111 | * | |
1112 | * Returns the TRB prior to the one pointed to by the index. If the | |
1113 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
1114 | * the one just before that. | |
1115 | */ | |
1116 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
1117 | { | |
1118 | u8 tmp = index; | |
1119 | ||
1120 | if (!tmp) | |
1121 | tmp = DWC3_TRB_NUM - 1; | |
1122 | ||
1123 | return &dep->trb_pool[tmp - 1]; | |
1124 | } | |
1125 | ||
1126 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
1127 | { | |
42626919 FB |
1128 | u8 trbs_left; |
1129 | ||
1130 | /* | |
51f1954a TN |
1131 | * If the enqueue & dequeue are equal then the TRB ring is either full |
1132 | * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs | |
1133 | * pending to be processed by the driver. | |
42626919 FB |
1134 | */ |
1135 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
51f1954a TN |
1136 | /* |
1137 | * If there is any request remained in the started_list at | |
1138 | * this point, that means there is no TRB available. | |
1139 | */ | |
1140 | if (!list_empty(&dep->started_list)) | |
42626919 FB |
1141 | return 0; |
1142 | ||
1143 | return DWC3_TRB_NUM - 1; | |
1144 | } | |
1145 | ||
1146 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
1147 | trbs_left &= (DWC3_TRB_NUM - 1); | |
1148 | ||
1149 | if (dep->trb_dequeue < dep->trb_enqueue) | |
1150 | trbs_left--; | |
1151 | ||
1152 | return trbs_left; | |
1153 | } | |
2c78c029 | 1154 | |
e49d3cf4 | 1155 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
e319bd62 FB |
1156 | dma_addr_t dma, unsigned int length, unsigned int chain, |
1157 | unsigned int node, unsigned int stream_id, | |
1158 | unsigned int short_not_ok, unsigned int no_interrupt, | |
f9cc581b | 1159 | unsigned int is_last, bool must_interrupt) |
c71fc37c | 1160 | { |
6b9018d4 | 1161 | struct dwc3 *dwc = dep->dwc; |
e81a7018 | 1162 | struct usb_gadget *gadget = dwc->gadget; |
6b9018d4 | 1163 | enum usb_device_speed speed = gadget->speed; |
c71fc37c | 1164 | |
f6bafc6a FB |
1165 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
1166 | trb->bpl = lower_32_bits(dma); | |
1167 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 1168 | |
16e78db7 | 1169 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 1170 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 1171 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
1172 | break; |
1173 | ||
1174 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 1175 | if (!node) { |
e5ba5ec8 | 1176 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 1177 | |
40d829fb MG |
1178 | /* |
1179 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
1180 | * there is only a single transaction in the microframe, | |
1181 | * only a DATA0 data packet PID is used. If there are | |
1182 | * two transactions per microframe, DATA1 is used for | |
1183 | * the first transaction data packet and DATA0 is used | |
1184 | * for the second transaction data packet. If there are | |
1185 | * three transactions per microframe, DATA2 is used for | |
1186 | * the first transaction data packet, DATA1 is used for | |
1187 | * the second, and DATA0 is used for the third." | |
1188 | * | |
1189 | * IOW, we should satisfy the following cases: | |
1190 | * | |
1191 | * 1) length <= maxpacket | |
1192 | * - DATA0 | |
1193 | * | |
1194 | * 2) maxpacket < length <= (2 * maxpacket) | |
1195 | * - DATA1, DATA0 | |
1196 | * | |
1197 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
1198 | * - DATA2, DATA1, DATA0 | |
1199 | */ | |
6b9018d4 FB |
1200 | if (speed == USB_SPEED_HIGH) { |
1201 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 1202 | unsigned int mult = 2; |
40d829fb MG |
1203 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
1204 | ||
1205 | if (length <= (2 * maxp)) | |
1206 | mult--; | |
1207 | ||
1208 | if (length <= maxp) | |
1209 | mult--; | |
1210 | ||
1211 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
1212 | } |
1213 | } else { | |
e5ba5ec8 | 1214 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 1215 | } |
ca4d44ea FB |
1216 | |
1217 | /* always enable Interrupt on Missed ISOC */ | |
1218 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
1219 | break; |
1220 | ||
1221 | case USB_ENDPOINT_XFER_BULK: | |
1222 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 1223 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
1224 | break; |
1225 | default: | |
1226 | /* | |
1227 | * This is only possible with faulty memory because we | |
1228 | * checked it already :) | |
1229 | */ | |
0a695d4c FB |
1230 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
1231 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
1232 | } |
1233 | ||
244add8e TJ |
1234 | /* |
1235 | * Enable Continue on Short Packet | |
1236 | * when endpoint is not a stream capable | |
1237 | */ | |
c9508c8c | 1238 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
1239 | if (!dep->stream_capable) |
1240 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 1241 | |
e49d3cf4 | 1242 | if (short_not_ok) |
c9508c8c FB |
1243 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1244 | } | |
1245 | ||
8dbbe48c | 1246 | if ((!no_interrupt && !chain) || must_interrupt) |
c9508c8c | 1247 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1248 | |
e5ba5ec8 PA |
1249 | if (chain) |
1250 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
3eaecd0c TN |
1251 | else if (dep->stream_capable && is_last) |
1252 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
e5ba5ec8 | 1253 | |
16e78db7 | 1254 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1255 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1256 | |
f6bafc6a | 1257 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1258 | |
b7a4fbe2 AKV |
1259 | dwc3_ep_inc_enq(dep); |
1260 | ||
2c4cbe6e | 1261 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1262 | } |
1263 | ||
e49d3cf4 FB |
1264 | /** |
1265 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1266 | * @dep: endpoint for which this request is prepared | |
1267 | * @req: dwc3_request pointer | |
5d187c04 | 1268 | * @trb_length: buffer size of the TRB |
e49d3cf4 FB |
1269 | * @chain: should this TRB be chained to the next? |
1270 | * @node: only for isochronous endpoints. First TRB needs different type. | |
2b80357b | 1271 | * @use_bounce_buffer: set to use bounce buffer |
f9cc581b | 1272 | * @must_interrupt: set to interrupt on TRB completion |
e49d3cf4 FB |
1273 | */ |
1274 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
5d187c04 | 1275 | struct dwc3_request *req, unsigned int trb_length, |
f9cc581b TN |
1276 | unsigned int chain, unsigned int node, bool use_bounce_buffer, |
1277 | bool must_interrupt) | |
e49d3cf4 FB |
1278 | { |
1279 | struct dwc3_trb *trb; | |
a31e63b6 | 1280 | dma_addr_t dma; |
e319bd62 FB |
1281 | unsigned int stream_id = req->request.stream_id; |
1282 | unsigned int short_not_ok = req->request.short_not_ok; | |
1283 | unsigned int no_interrupt = req->request.no_interrupt; | |
1284 | unsigned int is_last = req->request.is_last; | |
a31e63b6 | 1285 | |
2b80357b TN |
1286 | if (use_bounce_buffer) |
1287 | dma = dep->dwc->bounce_addr; | |
1288 | else if (req->request.num_sgs > 0) | |
a31e63b6 | 1289 | dma = sg_dma_address(req->start_sg); |
5d187c04 | 1290 | else |
a31e63b6 | 1291 | dma = req->request.dma; |
e49d3cf4 FB |
1292 | |
1293 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1294 | ||
1295 | if (!req->trb) { | |
1296 | dwc3_gadget_move_started_request(req); | |
1297 | req->trb = trb; | |
1298 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1299 | } |
1300 | ||
09fe1f8d FB |
1301 | req->num_trbs++; |
1302 | ||
5d187c04 | 1303 | __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node, |
f9cc581b TN |
1304 | stream_id, short_not_ok, no_interrupt, is_last, |
1305 | must_interrupt); | |
1306 | } | |
1307 | ||
1308 | static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req) | |
1309 | { | |
1310 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1311 | unsigned int rem = req->request.length % maxp; | |
1312 | ||
1313 | if ((req->request.length && req->request.zero && !rem && | |
1314 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) || | |
1315 | (!req->direction && rem)) | |
1316 | return true; | |
1317 | ||
1318 | return false; | |
e49d3cf4 FB |
1319 | } |
1320 | ||
cb1b3997 TN |
1321 | /** |
1322 | * dwc3_prepare_last_sg - prepare TRBs for the last SG entry | |
1323 | * @dep: The endpoint that the request belongs to | |
1324 | * @req: The request to prepare | |
1325 | * @entry_length: The last SG entry size | |
1326 | * @node: Indicates whether this is not the first entry (for isoc only) | |
1327 | * | |
1328 | * Return the number of TRBs prepared. | |
1329 | */ | |
1330 | static int dwc3_prepare_last_sg(struct dwc3_ep *dep, | |
1331 | struct dwc3_request *req, unsigned int entry_length, | |
1332 | unsigned int node) | |
1333 | { | |
1334 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1335 | unsigned int rem = req->request.length % maxp; | |
1336 | unsigned int num_trbs = 1; | |
1337 | ||
f9cc581b | 1338 | if (dwc3_needs_extra_trb(dep, req)) |
cb1b3997 TN |
1339 | num_trbs++; |
1340 | ||
1341 | if (dwc3_calc_trbs_left(dep) < num_trbs) | |
1342 | return 0; | |
1343 | ||
1344 | req->needs_extra_trb = num_trbs > 1; | |
1345 | ||
1346 | /* Prepare a normal TRB */ | |
1347 | if (req->direction || req->request.length) | |
1348 | dwc3_prepare_one_trb(dep, req, entry_length, | |
f9cc581b | 1349 | req->needs_extra_trb, node, false, false); |
cb1b3997 TN |
1350 | |
1351 | /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */ | |
1352 | if ((!req->direction && !req->request.length) || req->needs_extra_trb) | |
1353 | dwc3_prepare_one_trb(dep, req, | |
1354 | req->direction ? 0 : maxp - rem, | |
f9cc581b | 1355 | false, 1, true, false); |
cb1b3997 TN |
1356 | |
1357 | return num_trbs; | |
1358 | } | |
1359 | ||
7f2958d9 | 1360 | static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep, |
7ae7df49 | 1361 | struct dwc3_request *req) |
5ee85d89 | 1362 | { |
a31e63b6 | 1363 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1364 | struct scatterlist *s; |
5ee85d89 | 1365 | int i; |
5d187c04 | 1366 | unsigned int length = req->request.length; |
c96e6725 AKV |
1367 | unsigned int remaining = req->request.num_mapped_sgs |
1368 | - req->num_queued_sgs; | |
13111fcb | 1369 | unsigned int num_trbs = req->num_trbs; |
f9cc581b | 1370 | bool needs_extra_trb = dwc3_needs_extra_trb(dep, req); |
c96e6725 | 1371 | |
5d187c04 TN |
1372 | /* |
1373 | * If we resume preparing the request, then get the remaining length of | |
1374 | * the request and resume where we left off. | |
1375 | */ | |
1376 | for_each_sg(req->request.sg, s, req->num_queued_sgs, i) | |
1377 | length -= sg_dma_len(s); | |
1378 | ||
c96e6725 | 1379 | for_each_sg(sg, s, remaining, i) { |
8dbbe48c | 1380 | unsigned int num_trbs_left = dwc3_calc_trbs_left(dep); |
5d187c04 | 1381 | unsigned int trb_length; |
f9cc581b | 1382 | bool must_interrupt = false; |
cb1b3997 | 1383 | bool last_sg = false; |
5ee85d89 | 1384 | |
5d187c04 TN |
1385 | trb_length = min_t(unsigned int, length, sg_dma_len(s)); |
1386 | ||
1387 | length -= trb_length; | |
1388 | ||
dad2aff3 PP |
1389 | /* |
1390 | * IOMMU driver is coalescing the list of sgs which shares a | |
1391 | * page boundary into one and giving it to USB driver. With | |
1392 | * this the number of sgs mapped is not equal to the number of | |
1393 | * sgs passed. So mark the chain bit to false if it isthe last | |
1394 | * mapped sg. | |
1395 | */ | |
5d187c04 | 1396 | if ((i == remaining - 1) || !length) |
cb1b3997 | 1397 | last_sg = true; |
5ee85d89 | 1398 | |
8dbbe48c | 1399 | if (!num_trbs_left) |
13111fcb TN |
1400 | break; |
1401 | ||
cb1b3997 TN |
1402 | if (last_sg) { |
1403 | if (!dwc3_prepare_last_sg(dep, req, trb_length, i)) | |
f9cc581b | 1404 | break; |
c6267a51 | 1405 | } else { |
f9cc581b TN |
1406 | /* |
1407 | * Look ahead to check if we have enough TRBs for the | |
8dbbe48c TN |
1408 | * next SG entry. If not, set interrupt on this TRB to |
1409 | * resume preparing the next SG entry when more TRBs are | |
f9cc581b TN |
1410 | * free. |
1411 | */ | |
8dbbe48c TN |
1412 | if (num_trbs_left == 1 || (needs_extra_trb && |
1413 | num_trbs_left <= 2 && | |
1414 | sg_dma_len(sg_next(s)) >= length)) | |
f9cc581b TN |
1415 | must_interrupt = true; |
1416 | ||
1417 | dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false, | |
1418 | must_interrupt); | |
c6267a51 | 1419 | } |
5ee85d89 | 1420 | |
a31e63b6 AKV |
1421 | /* |
1422 | * There can be a situation where all sgs in sglist are not | |
1423 | * queued because of insufficient trb number. To handle this | |
1424 | * case, update start_sg to next sg to be queued, so that | |
1425 | * we have free trbs we can continue queuing from where we | |
1426 | * previously stopped | |
1427 | */ | |
cb1b3997 | 1428 | if (!last_sg) |
a31e63b6 AKV |
1429 | req->start_sg = sg_next(s); |
1430 | ||
c96e6725 | 1431 | req->num_queued_sgs++; |
25dda9fc | 1432 | req->num_pending_sgs--; |
c96e6725 | 1433 | |
5d187c04 TN |
1434 | /* |
1435 | * The number of pending SG entries may not correspond to the | |
1436 | * number of mapped SG entries. If all the data are queued, then | |
1437 | * don't include unused SG entries. | |
1438 | */ | |
1439 | if (length == 0) { | |
25dda9fc | 1440 | req->num_pending_sgs = 0; |
5d187c04 TN |
1441 | break; |
1442 | } | |
1443 | ||
8dbbe48c | 1444 | if (must_interrupt) |
5ee85d89 FB |
1445 | break; |
1446 | } | |
13111fcb | 1447 | |
13111fcb | 1448 | return req->num_trbs - num_trbs; |
5ee85d89 FB |
1449 | } |
1450 | ||
7f2958d9 | 1451 | static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep, |
7ae7df49 | 1452 | struct dwc3_request *req) |
5ee85d89 | 1453 | { |
cb1b3997 | 1454 | return dwc3_prepare_last_sg(dep, req, req->request.length, 0); |
5ee85d89 FB |
1455 | } |
1456 | ||
72246da4 FB |
1457 | /* |
1458 | * dwc3_prepare_trbs - setup TRBs from requests | |
1459 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1460 | * |
1d046793 PZ |
1461 | * The function goes through the requests list and sets up TRBs for the |
1462 | * transfers. The function returns once there are no more TRBs available or | |
1463 | * it runs out of requests. | |
490410b2 TN |
1464 | * |
1465 | * Returns the number of TRBs prepared or negative errno. | |
72246da4 | 1466 | */ |
490410b2 | 1467 | static int dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1468 | { |
68e823e2 | 1469 | struct dwc3_request *req, *n; |
490410b2 | 1470 | int ret = 0; |
72246da4 FB |
1471 | |
1472 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1473 | ||
d86c5a67 FB |
1474 | /* |
1475 | * We can get in a situation where there's a request in the started list | |
1476 | * but there weren't enough TRBs to fully kick it in the first time | |
1477 | * around, so it has been waiting for more TRBs to be freed up. | |
1478 | * | |
1479 | * In that case, we should check if we have a request with pending_sgs | |
1480 | * in the started list and prepare TRBs for that request first, | |
1481 | * otherwise we will prepare TRBs completely out of order and that will | |
1482 | * break things. | |
1483 | */ | |
1484 | list_for_each_entry(req, &dep->started_list, list) { | |
490410b2 | 1485 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1486 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd | 1487 | if (!ret || req->num_pending_sgs) |
490410b2 TN |
1488 | return ret; |
1489 | } | |
d86c5a67 FB |
1490 | |
1491 | if (!dwc3_calc_trbs_left(dep)) | |
490410b2 | 1492 | return ret; |
63c7bb29 TN |
1493 | |
1494 | /* | |
1495 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1496 | * burst capability may try to read and use TRBs beyond the | |
1497 | * active transfer instead of stopping. | |
1498 | */ | |
1499 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1500 | return ret; |
d86c5a67 FB |
1501 | } |
1502 | ||
aa3342c8 | 1503 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 | 1504 | struct dwc3 *dwc = dep->dwc; |
cdb55b39 FB |
1505 | |
1506 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1507 | dep->direction); | |
1508 | if (ret) | |
490410b2 | 1509 | return ret; |
cdb55b39 FB |
1510 | |
1511 | req->sg = req->request.sg; | |
a31e63b6 | 1512 | req->start_sg = req->sg; |
c96e6725 | 1513 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1514 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1515 | ||
346a15cd | 1516 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1517 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd TN |
1518 | if (req->num_pending_sgs) |
1519 | return ret; | |
1520 | } else { | |
7f2958d9 | 1521 | ret = dwc3_prepare_trbs_linear(dep, req); |
346a15cd | 1522 | } |
72246da4 | 1523 | |
490410b2 TN |
1524 | if (!ret || !dwc3_calc_trbs_left(dep)) |
1525 | return ret; | |
aefe3d23 TN |
1526 | |
1527 | /* | |
1528 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1529 | * burst capability may try to read and use TRBs beyond the | |
1530 | * active transfer instead of stopping. | |
1531 | */ | |
1532 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1533 | return ret; |
72246da4 | 1534 | } |
490410b2 TN |
1535 | |
1536 | return ret; | |
72246da4 FB |
1537 | } |
1538 | ||
8d99087c TN |
1539 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep); |
1540 | ||
7fdca766 | 1541 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1542 | { |
1543 | struct dwc3_gadget_ep_cmd_params params; | |
1544 | struct dwc3_request *req; | |
4fae2e3e | 1545 | int starting; |
72246da4 FB |
1546 | int ret; |
1547 | u32 cmd; | |
1548 | ||
d72ecc08 TN |
1549 | /* |
1550 | * Note that it's normal to have no new TRBs prepared (i.e. ret == 0). | |
1551 | * This happens when we need to stop and restart a transfer such as in | |
1552 | * the case of reinitiating a stream or retrying an isoc transfer. | |
1553 | */ | |
490410b2 | 1554 | ret = dwc3_prepare_trbs(dep); |
d72ecc08 | 1555 | if (ret < 0) |
490410b2 | 1556 | return ret; |
ccb94ebf | 1557 | |
1912cbc6 | 1558 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1559 | |
2338484d TN |
1560 | /* |
1561 | * If there's no new TRB prepared and we don't need to restart a | |
1562 | * transfer, there's no need to update the transfer. | |
1563 | */ | |
1564 | if (!ret && !starting) | |
1565 | return ret; | |
1566 | ||
4fae2e3e | 1567 | req = next_request(&dep->started_list); |
72246da4 FB |
1568 | if (!req) { |
1569 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1570 | return 0; | |
1571 | } | |
1572 | ||
1573 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1574 | |
4fae2e3e | 1575 | if (starting) { |
1877d6c9 PA |
1576 | params.param0 = upper_32_bits(req->trb_dma); |
1577 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1578 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1579 | ||
a7351807 AKV |
1580 | if (dep->stream_capable) |
1581 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1582 | ||
7fdca766 FB |
1583 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1584 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1585 | } else { |
b6b1c6db FB |
1586 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1587 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1588 | } |
72246da4 | 1589 | |
2cd4718d | 1590 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1591 | if (ret < 0) { |
8d99087c TN |
1592 | struct dwc3_request *tmp; |
1593 | ||
1594 | if (ret == -EAGAIN) | |
1595 | return ret; | |
1596 | ||
1597 | dwc3_stop_active_transfer(dep, true, true); | |
1598 | ||
1599 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 1600 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED); |
8d99087c TN |
1601 | |
1602 | /* If ep isn't started, then there's no end transfer pending */ | |
1603 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1604 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1605 | ||
72246da4 FB |
1606 | return ret; |
1607 | } | |
1608 | ||
e0d19563 TN |
1609 | if (dep->stream_capable && req->request.is_last) |
1610 | dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
1611 | ||
72246da4 FB |
1612 | return 0; |
1613 | } | |
1614 | ||
6cb2e4e3 FB |
1615 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1616 | { | |
1617 | u32 reg; | |
1618 | ||
1619 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1620 | return DWC3_DSTS_SOFFN(reg); | |
1621 | } | |
1622 | ||
d92021f6 TN |
1623 | /** |
1624 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1625 | * @dep: isoc endpoint | |
1626 | * | |
1627 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1628 | * microframe number reported by the XferNotReady event for the future frame | |
1629 | * number to start the isoc transfer. | |
1630 | * | |
1631 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1632 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1633 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1634 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1635 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1636 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1637 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1638 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1639 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1640 | * | |
1641 | * In order to workaround this issue, we can test for the correct combination of | |
1642 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1643 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1644 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1645 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1646 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1647 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1648 | * value is the correct combination. | |
1649 | * | |
1650 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1651 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1652 | * deduce the smaller successful combination. | |
1653 | * | |
1654 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1655 | * of BIT[15:14]. The correct combination is as follow: | |
1656 | * | |
1657 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1658 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1659 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1660 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1661 | * | |
1662 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1663 | * endpoints. | |
1664 | */ | |
25abad6a | 1665 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1666 | { |
1667 | int cmd_status = 0; | |
1668 | bool test0; | |
1669 | bool test1; | |
1670 | ||
1671 | while (dep->combo_num < 2) { | |
1672 | struct dwc3_gadget_ep_cmd_params params; | |
1673 | u32 test_frame_number; | |
1674 | u32 cmd; | |
1675 | ||
1676 | /* | |
1677 | * Check if we can start isoc transfer on the next interval or | |
1678 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1679 | */ | |
ca143785 | 1680 | test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1681 | test_frame_number |= dep->combo_num << 14; |
1682 | test_frame_number += max_t(u32, 4, dep->interval); | |
1683 | ||
1684 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1685 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1686 | ||
1687 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1688 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1689 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1690 | ||
1691 | /* Redo if some other failure beside bus-expiry is received */ | |
1692 | if (cmd_status && cmd_status != -EAGAIN) { | |
1693 | dep->start_cmd_status = 0; | |
1694 | dep->combo_num = 0; | |
25abad6a | 1695 | return 0; |
d92021f6 TN |
1696 | } |
1697 | ||
1698 | /* Store the first test status */ | |
1699 | if (dep->combo_num == 0) | |
1700 | dep->start_cmd_status = cmd_status; | |
1701 | ||
1702 | dep->combo_num++; | |
1703 | ||
1704 | /* | |
1705 | * End the transfer if the START_TRANSFER command is successful | |
1706 | * to wait for the next XferNotReady to test the command again | |
1707 | */ | |
1708 | if (cmd_status == 0) { | |
c5353b22 | 1709 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1710 | return 0; |
d92021f6 TN |
1711 | } |
1712 | } | |
1713 | ||
1714 | /* test0 and test1 are both completed at this point */ | |
1715 | test0 = (dep->start_cmd_status == 0); | |
1716 | test1 = (cmd_status == 0); | |
1717 | ||
1718 | if (!test0 && test1) | |
1719 | dep->combo_num = 1; | |
1720 | else if (!test0 && !test1) | |
1721 | dep->combo_num = 2; | |
1722 | else if (test0 && !test1) | |
1723 | dep->combo_num = 3; | |
1724 | else if (test0 && test1) | |
1725 | dep->combo_num = 0; | |
1726 | ||
ca143785 | 1727 | dep->frame_number &= DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1728 | dep->frame_number |= dep->combo_num << 14; |
1729 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1730 | ||
1731 | /* Reinitialize test variables */ | |
1732 | dep->start_cmd_status = 0; | |
1733 | dep->combo_num = 0; | |
1734 | ||
25abad6a | 1735 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1736 | } |
1737 | ||
25abad6a | 1738 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1739 | { |
c5a7092f | 1740 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
d92021f6 | 1741 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1742 | int ret; |
1743 | int i; | |
d92021f6 | 1744 | |
36f05d36 TN |
1745 | if (list_empty(&dep->pending_list) && |
1746 | list_empty(&dep->started_list)) { | |
f4a53c55 | 1747 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1748 | return -EAGAIN; |
d6d6ec7b PA |
1749 | } |
1750 | ||
9af21dd6 TN |
1751 | if (!dwc->dis_start_transfer_quirk && |
1752 | (DWC3_VER_IS_PRIOR(DWC31, 170A) || | |
1753 | DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) { | |
e81a7018 | 1754 | if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction) |
25abad6a | 1755 | return dwc3_gadget_start_isoc_quirk(dep); |
d6d6ec7b PA |
1756 | } |
1757 | ||
c5a7092f | 1758 | if (desc->bInterval <= 14 && |
e81a7018 | 1759 | dwc->gadget->speed >= USB_SPEED_HIGH) { |
c5a7092f MO |
1760 | u32 frame = __dwc3_gadget_get_frame(dwc); |
1761 | bool rollover = frame < | |
1762 | (dep->frame_number & DWC3_FRNUMBER_MASK); | |
1763 | ||
1764 | /* | |
1765 | * frame_number is set from XferNotReady and may be already | |
1766 | * out of date. DSTS only provides the lower 14 bit of the | |
1767 | * current frame number. So add the upper two bits of | |
1768 | * frame_number and handle a possible rollover. | |
1769 | * This will provide the correct frame_number unless more than | |
1770 | * rollover has happened since XferNotReady. | |
1771 | */ | |
1772 | ||
1773 | dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) | | |
1774 | frame; | |
1775 | if (rollover) | |
1776 | dep->frame_number += BIT(14); | |
1777 | } | |
1778 | ||
d5370106 FB |
1779 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1780 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1781 | ||
1782 | ret = __dwc3_gadget_kick_transfer(dep); | |
1783 | if (ret != -EAGAIN) | |
1784 | break; | |
1785 | } | |
1786 | ||
36f05d36 TN |
1787 | /* |
1788 | * After a number of unsuccessful start attempts due to bus-expiry | |
1789 | * status, issue END_TRANSFER command and retry on the next XferNotReady | |
1790 | * event. | |
1791 | */ | |
1792 | if (ret == -EAGAIN) { | |
1793 | struct dwc3_gadget_ep_cmd_params params; | |
1794 | u32 cmd; | |
1795 | ||
1796 | cmd = DWC3_DEPCMD_ENDTRANSFER | | |
1797 | DWC3_DEPCMD_CMDIOC | | |
1798 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1799 | ||
1800 | dep->resource_index = 0; | |
1801 | memset(¶ms, 0, sizeof(params)); | |
1802 | ||
1803 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1804 | if (!ret) | |
1805 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
1806 | } | |
1807 | ||
d5370106 | 1808 | return ret; |
d6d6ec7b PA |
1809 | } |
1810 | ||
72246da4 FB |
1811 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1812 | { | |
0fc9a1be | 1813 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1814 | |
f09ddcfc | 1815 | if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { |
5eb30ced FB |
1816 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1817 | dep->name); | |
bb423984 FB |
1818 | return -ESHUTDOWN; |
1819 | } | |
1820 | ||
04fb365c FB |
1821 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1822 | &req->request, req->dep->name)) | |
bb423984 | 1823 | return -EINVAL; |
bb423984 | 1824 | |
b2b6d601 FB |
1825 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1826 | "%s: request %pK already in flight\n", | |
1827 | dep->name, &req->request)) | |
1828 | return -EINVAL; | |
1829 | ||
fc8bb91b FB |
1830 | pm_runtime_get(dwc->dev); |
1831 | ||
72246da4 FB |
1832 | req->request.actual = 0; |
1833 | req->request.status = -EINPROGRESS; | |
72246da4 | 1834 | |
fe84f522 FB |
1835 | trace_dwc3_ep_queue(req); |
1836 | ||
aa3342c8 | 1837 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1838 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1839 | |
e0d19563 TN |
1840 | if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE) |
1841 | return 0; | |
1842 | ||
c503672a TN |
1843 | /* |
1844 | * Start the transfer only after the END_TRANSFER is completed | |
1845 | * and endpoint STALL is cleared. | |
1846 | */ | |
1847 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || | |
1848 | (dep->flags & DWC3_EP_WEDGE) || | |
1849 | (dep->flags & DWC3_EP_STALL)) { | |
da10bcdd TN |
1850 | dep->flags |= DWC3_EP_DELAY_START; |
1851 | return 0; | |
1852 | } | |
1853 | ||
d889c23c FB |
1854 | /* |
1855 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1856 | * wait for a XferNotReady event so we will know what's the current | |
1857 | * (micro-)frame number. | |
1858 | * | |
1859 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1860 | * errors which will force us issue EndTransfer command. | |
1861 | */ | |
1862 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1863 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1864 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1865 | return 0; | |
1866 | ||
6cb2e4e3 | 1867 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
e319bd62 | 1868 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
25abad6a | 1869 | return __dwc3_gadget_start_isoc(dep); |
08a36b54 | 1870 | } |
64e01080 | 1871 | } |
b997ada5 | 1872 | |
18ffa988 WC |
1873 | __dwc3_gadget_kick_transfer(dep); |
1874 | ||
1875 | return 0; | |
72246da4 FB |
1876 | } |
1877 | ||
1878 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1879 | gfp_t gfp_flags) | |
1880 | { | |
1881 | struct dwc3_request *req = to_dwc3_request(request); | |
1882 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1883 | struct dwc3 *dwc = dep->dwc; | |
1884 | ||
1885 | unsigned long flags; | |
1886 | ||
1887 | int ret; | |
1888 | ||
fdee4eba | 1889 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1890 | ret = __dwc3_gadget_ep_queue(dep, req); |
1891 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1892 | ||
1893 | return ret; | |
1894 | } | |
1895 | ||
7746a8df FB |
1896 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1897 | { | |
1898 | int i; | |
1899 | ||
cb11ea56 TN |
1900 | /* If req->trb is not set, then the request has not started */ |
1901 | if (!req->trb) | |
1902 | return; | |
1903 | ||
7746a8df FB |
1904 | /* |
1905 | * If request was already started, this means we had to | |
1906 | * stop the transfer. With that we also need to ignore | |
1907 | * all TRBs used by the request, however TRBs can only | |
1908 | * be modified after completion of END_TRANSFER | |
1909 | * command. So what we do here is that we wait for | |
1910 | * END_TRANSFER completion and only after that, we jump | |
1911 | * over TRBs by clearing HWO and incrementing dequeue | |
1912 | * pointer. | |
1913 | */ | |
1914 | for (i = 0; i < req->num_trbs; i++) { | |
1915 | struct dwc3_trb *trb; | |
1916 | ||
2dedea03 | 1917 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1918 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1919 | dwc3_ep_inc_deq(dep); | |
1920 | } | |
c7152763 TN |
1921 | |
1922 | req->num_trbs = 0; | |
7746a8df FB |
1923 | } |
1924 | ||
d4f1afe5 FB |
1925 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1926 | { | |
1927 | struct dwc3_request *req; | |
1928 | struct dwc3_request *tmp; | |
04dd6e76 | 1929 | struct dwc3 *dwc = dep->dwc; |
d4f1afe5 | 1930 | |
664cc971 | 1931 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { |
d4f1afe5 | 1932 | dwc3_gadget_ep_skip_trbs(dep, req); |
04dd6e76 RC |
1933 | switch (req->status) { |
1934 | case DWC3_REQUEST_STATUS_DISCONNECTED: | |
1935 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
1936 | break; | |
1937 | case DWC3_REQUEST_STATUS_DEQUEUED: | |
1938 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1939 | break; | |
1940 | case DWC3_REQUEST_STATUS_STALLED: | |
1941 | dwc3_gadget_giveback(dep, req, -EPIPE); | |
1942 | break; | |
1943 | default: | |
1944 | dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status); | |
1945 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1946 | break; | |
1947 | } | |
d4f1afe5 FB |
1948 | } |
1949 | } | |
1950 | ||
72246da4 FB |
1951 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1952 | struct usb_request *request) | |
1953 | { | |
1954 | struct dwc3_request *req = to_dwc3_request(request); | |
1955 | struct dwc3_request *r = NULL; | |
1956 | ||
1957 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1958 | struct dwc3 *dwc = dep->dwc; | |
1959 | ||
1960 | unsigned long flags; | |
1961 | int ret = 0; | |
1962 | ||
2c4cbe6e FB |
1963 | trace_dwc3_ep_dequeue(req); |
1964 | ||
72246da4 FB |
1965 | spin_lock_irqsave(&dwc->lock, flags); |
1966 | ||
a7027ca6 | 1967 | list_for_each_entry(r, &dep->cancelled_list, list) { |
72246da4 | 1968 | if (r == req) |
fcd2def6 | 1969 | goto out; |
72246da4 FB |
1970 | } |
1971 | ||
aa3342c8 | 1972 | list_for_each_entry(r, &dep->pending_list, list) { |
fcd2def6 TN |
1973 | if (r == req) { |
1974 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1975 | goto out; | |
72246da4 | 1976 | } |
72246da4 FB |
1977 | } |
1978 | ||
fcd2def6 | 1979 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 | 1980 | if (r == req) { |
a7027ca6 TN |
1981 | struct dwc3_request *t; |
1982 | ||
72246da4 | 1983 | /* wait until it is processed */ |
c5353b22 | 1984 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 1985 | |
a7027ca6 TN |
1986 | /* |
1987 | * Remove any started request if the transfer is | |
1988 | * cancelled. | |
1989 | */ | |
1990 | list_for_each_entry_safe(r, t, &dep->started_list, list) | |
04dd6e76 RC |
1991 | dwc3_gadget_move_cancelled_request(r, |
1992 | DWC3_REQUEST_STATUS_DEQUEUED); | |
cf3113d8 | 1993 | |
a5c7682a TN |
1994 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; |
1995 | ||
fcd2def6 | 1996 | goto out; |
72246da4 | 1997 | } |
72246da4 FB |
1998 | } |
1999 | ||
fcd2def6 TN |
2000 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
2001 | request, ep->name); | |
2002 | ret = -EINVAL; | |
2003 | out: | |
72246da4 FB |
2004 | spin_unlock_irqrestore(&dwc->lock, flags); |
2005 | ||
2006 | return ret; | |
2007 | } | |
2008 | ||
7a608559 | 2009 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
2010 | { |
2011 | struct dwc3_gadget_ep_cmd_params params; | |
2012 | struct dwc3 *dwc = dep->dwc; | |
cb11ea56 TN |
2013 | struct dwc3_request *req; |
2014 | struct dwc3_request *tmp; | |
72246da4 FB |
2015 | int ret; |
2016 | ||
5ad02fb8 FB |
2017 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
2018 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
2019 | return -EINVAL; | |
2020 | } | |
2021 | ||
72246da4 FB |
2022 | memset(¶ms, 0x00, sizeof(params)); |
2023 | ||
2024 | if (value) { | |
69450c4d FB |
2025 | struct dwc3_trb *trb; |
2026 | ||
e319bd62 FB |
2027 | unsigned int transfer_in_flight; |
2028 | unsigned int started; | |
69450c4d FB |
2029 | |
2030 | if (dep->number > 1) | |
2031 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
2032 | else | |
2033 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
2034 | ||
2035 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
2036 | started = !list_empty(&dep->started_list); | |
2037 | ||
2038 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
2039 | (!dep->direction && started))) { | |
7a608559 FB |
2040 | return -EAGAIN; |
2041 | } | |
2042 | ||
2cd4718d FB |
2043 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
2044 | ¶ms); | |
72246da4 | 2045 | if (ret) |
3f89204b | 2046 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
2047 | dep->name); |
2048 | else | |
2049 | dep->flags |= DWC3_EP_STALL; | |
2050 | } else { | |
cb11ea56 TN |
2051 | /* |
2052 | * Don't issue CLEAR_STALL command to control endpoints. The | |
2053 | * controller automatically clears the STALL when it receives | |
2054 | * the SETUP token. | |
2055 | */ | |
2056 | if (dep->number <= 1) { | |
2057 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
2058 | return 0; | |
2059 | } | |
2cd4718d | 2060 | |
d97c78a1 TN |
2061 | dwc3_stop_active_transfer(dep, true, true); |
2062 | ||
2063 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 2064 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED); |
d97c78a1 TN |
2065 | |
2066 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
2067 | dep->flags |= DWC3_EP_PENDING_CLEAR_STALL; | |
2068 | return 0; | |
2069 | } | |
2070 | ||
2071 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
2072 | ||
50c763f8 | 2073 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
cb11ea56 | 2074 | if (ret) { |
3f89204b | 2075 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 | 2076 | dep->name); |
cb11ea56 TN |
2077 | return ret; |
2078 | } | |
2079 | ||
2080 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
2081 | ||
c503672a TN |
2082 | if ((dep->flags & DWC3_EP_DELAY_START) && |
2083 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2084 | __dwc3_gadget_kick_transfer(dep); | |
2085 | ||
2086 | dep->flags &= ~DWC3_EP_DELAY_START; | |
72246da4 | 2087 | } |
5275455a | 2088 | |
72246da4 FB |
2089 | return ret; |
2090 | } | |
2091 | ||
2092 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
2093 | { | |
2094 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
2095 | struct dwc3 *dwc = dep->dwc; | |
2096 | ||
2097 | unsigned long flags; | |
2098 | ||
2099 | int ret; | |
2100 | ||
2101 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 2102 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
2103 | spin_unlock_irqrestore(&dwc->lock, flags); |
2104 | ||
2105 | return ret; | |
2106 | } | |
2107 | ||
2108 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
2109 | { | |
2110 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
2111 | struct dwc3 *dwc = dep->dwc; |
2112 | unsigned long flags; | |
95aa4e8d | 2113 | int ret; |
72246da4 | 2114 | |
249a4569 | 2115 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
2116 | dep->flags |= DWC3_EP_WEDGE; |
2117 | ||
08f0d966 | 2118 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 2119 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 2120 | else |
7a608559 | 2121 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
2122 | spin_unlock_irqrestore(&dwc->lock, flags); |
2123 | ||
2124 | return ret; | |
72246da4 FB |
2125 | } |
2126 | ||
2127 | /* -------------------------------------------------------------------------- */ | |
2128 | ||
2129 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
2130 | .bLength = USB_DT_ENDPOINT_SIZE, | |
2131 | .bDescriptorType = USB_DT_ENDPOINT, | |
2132 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
2133 | }; | |
2134 | ||
2135 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
2136 | .enable = dwc3_gadget_ep0_enable, | |
2137 | .disable = dwc3_gadget_ep0_disable, | |
2138 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
2139 | .free_request = dwc3_gadget_ep_free_request, | |
2140 | .queue = dwc3_gadget_ep0_queue, | |
2141 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 2142 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
2143 | .set_wedge = dwc3_gadget_ep_set_wedge, |
2144 | }; | |
2145 | ||
2146 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
2147 | .enable = dwc3_gadget_ep_enable, | |
2148 | .disable = dwc3_gadget_ep_disable, | |
2149 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
2150 | .free_request = dwc3_gadget_ep_free_request, | |
2151 | .queue = dwc3_gadget_ep_queue, | |
2152 | .dequeue = dwc3_gadget_ep_dequeue, | |
2153 | .set_halt = dwc3_gadget_ep_set_halt, | |
2154 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
2155 | }; | |
2156 | ||
2157 | /* -------------------------------------------------------------------------- */ | |
2158 | ||
2159 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
2160 | { | |
2161 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 2162 | |
6cb2e4e3 | 2163 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
2164 | } |
2165 | ||
218ef7b6 | 2166 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 2167 | { |
d6011f6f | 2168 | int retries; |
72246da4 | 2169 | |
218ef7b6 | 2170 | int ret; |
72246da4 FB |
2171 | u32 reg; |
2172 | ||
72246da4 | 2173 | u8 link_state; |
72246da4 | 2174 | |
72246da4 FB |
2175 | /* |
2176 | * According to the Databook Remote wakeup request should | |
2177 | * be issued only when the device is in early suspend state. | |
2178 | * | |
2179 | * We can check that via USB Link State bits in DSTS register. | |
2180 | */ | |
2181 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
2182 | ||
72246da4 FB |
2183 | link_state = DWC3_DSTS_USBLNKST(reg); |
2184 | ||
2185 | switch (link_state) { | |
d0550cd2 | 2186 | case DWC3_LINK_STATE_RESET: |
72246da4 FB |
2187 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ |
2188 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
c560e763 TN |
2189 | case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */ |
2190 | case DWC3_LINK_STATE_U1: | |
d0550cd2 | 2191 | case DWC3_LINK_STATE_RESUME: |
72246da4 FB |
2192 | break; |
2193 | default: | |
218ef7b6 | 2194 | return -EINVAL; |
72246da4 FB |
2195 | } |
2196 | ||
8598bde7 FB |
2197 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
2198 | if (ret < 0) { | |
2199 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 2200 | return ret; |
8598bde7 | 2201 | } |
72246da4 | 2202 | |
802fde98 | 2203 | /* Recent versions do this automatically */ |
9af21dd6 | 2204 | if (DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 | 2205 | /* write zeroes to Link Change Request */ |
fcc023c7 | 2206 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
2207 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
2208 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2209 | } | |
72246da4 | 2210 | |
1d046793 | 2211 | /* poll until Link State changes to ON */ |
d6011f6f | 2212 | retries = 20000; |
72246da4 | 2213 | |
d6011f6f | 2214 | while (retries--) { |
72246da4 FB |
2215 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2216 | ||
2217 | /* in HS, means ON */ | |
2218 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
2219 | break; | |
2220 | } | |
2221 | ||
2222 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
2223 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 2224 | return -EINVAL; |
72246da4 FB |
2225 | } |
2226 | ||
218ef7b6 FB |
2227 | return 0; |
2228 | } | |
2229 | ||
2230 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
2231 | { | |
2232 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2233 | unsigned long flags; | |
2234 | int ret; | |
2235 | ||
2236 | spin_lock_irqsave(&dwc->lock, flags); | |
2237 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
2238 | spin_unlock_irqrestore(&dwc->lock, flags); |
2239 | ||
2240 | return ret; | |
2241 | } | |
2242 | ||
2243 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
2244 | int is_selfpowered) | |
2245 | { | |
2246 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 2247 | unsigned long flags; |
72246da4 | 2248 | |
249a4569 | 2249 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 2250 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 2251 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
2252 | |
2253 | return 0; | |
2254 | } | |
2255 | ||
ae7e8610 WC |
2256 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) |
2257 | { | |
2258 | u32 epnum; | |
2259 | ||
2260 | for (epnum = 2; epnum < dwc->num_eps; epnum++) { | |
2261 | struct dwc3_ep *dep; | |
2262 | ||
2263 | dep = dwc->eps[epnum]; | |
2264 | if (!dep) | |
2265 | continue; | |
2266 | ||
2267 | dwc3_remove_requests(dwc, dep); | |
2268 | } | |
2269 | } | |
2270 | ||
072cab8a TN |
2271 | static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc) |
2272 | { | |
2273 | enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate; | |
2274 | u32 reg; | |
2275 | ||
2276 | if (ssp_rate == USB_SSP_GEN_UNKNOWN) | |
2277 | ssp_rate = dwc->max_ssp_rate; | |
2278 | ||
2279 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2280 | reg &= ~DWC3_DCFG_SPEED_MASK; | |
2281 | reg &= ~DWC3_DCFG_NUMLANES(~0); | |
2282 | ||
2283 | if (ssp_rate == USB_SSP_GEN_1x2) | |
2284 | reg |= DWC3_DCFG_SUPERSPEED; | |
2285 | else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2) | |
2286 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2287 | ||
2288 | if (ssp_rate != USB_SSP_GEN_2x1 && | |
2289 | dwc->max_ssp_rate != USB_SSP_GEN_2x1) | |
2290 | reg |= DWC3_DCFG_NUMLANES(1); | |
2291 | ||
2292 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2293 | } | |
2294 | ||
7c9a2598 WC |
2295 | static void __dwc3_gadget_set_speed(struct dwc3 *dwc) |
2296 | { | |
450b9e9f | 2297 | enum usb_device_speed speed; |
7c9a2598 WC |
2298 | u32 reg; |
2299 | ||
450b9e9f | 2300 | speed = dwc->gadget_max_speed; |
93f1d43c | 2301 | if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed) |
450b9e9f TN |
2302 | speed = dwc->maximum_speed; |
2303 | ||
2304 | if (speed == USB_SPEED_SUPER_PLUS && | |
072cab8a TN |
2305 | DWC3_IP_IS(DWC32)) { |
2306 | __dwc3_gadget_set_ssp_rate(dwc); | |
2307 | return; | |
2308 | } | |
2309 | ||
7c9a2598 WC |
2310 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2311 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2312 | ||
2313 | /* | |
2314 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2315 | * which would cause metastability state on Run/Stop | |
2316 | * bit if we try to force the IP to USB2-only mode. | |
2317 | * | |
2318 | * Because of that, we cannot configure the IP to any | |
2319 | * speed other than the SuperSpeed | |
2320 | * | |
2321 | * Refers to: | |
2322 | * | |
2323 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2324 | * USB 2.0 Mode | |
2325 | */ | |
2326 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && | |
2327 | !dwc->dis_metastability_quirk) { | |
2328 | reg |= DWC3_DCFG_SUPERSPEED; | |
2329 | } else { | |
450b9e9f | 2330 | switch (speed) { |
7c9a2598 WC |
2331 | case USB_SPEED_FULL: |
2332 | reg |= DWC3_DCFG_FULLSPEED; | |
2333 | break; | |
2334 | case USB_SPEED_HIGH: | |
2335 | reg |= DWC3_DCFG_HIGHSPEED; | |
2336 | break; | |
2337 | case USB_SPEED_SUPER: | |
2338 | reg |= DWC3_DCFG_SUPERSPEED; | |
2339 | break; | |
2340 | case USB_SPEED_SUPER_PLUS: | |
2341 | if (DWC3_IP_IS(DWC3)) | |
2342 | reg |= DWC3_DCFG_SUPERSPEED; | |
2343 | else | |
2344 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2345 | break; | |
2346 | default: | |
450b9e9f | 2347 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); |
7c9a2598 WC |
2348 | |
2349 | if (DWC3_IP_IS(DWC3)) | |
2350 | reg |= DWC3_DCFG_SUPERSPEED; | |
2351 | else | |
2352 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2353 | } | |
2354 | } | |
f551037c TN |
2355 | |
2356 | if (DWC3_IP_IS(DWC32) && | |
450b9e9f TN |
2357 | speed > USB_SPEED_UNKNOWN && |
2358 | speed < USB_SPEED_SUPER_PLUS) | |
f551037c TN |
2359 | reg &= ~DWC3_DCFG_NUMLANES(~0); |
2360 | ||
7c9a2598 WC |
2361 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
2362 | } | |
2363 | ||
7b2a0368 | 2364 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
2365 | { |
2366 | u32 reg; | |
61d58242 | 2367 | u32 timeout = 500; |
72246da4 | 2368 | |
fc8bb91b FB |
2369 | if (pm_runtime_suspended(dwc->dev)) |
2370 | return 0; | |
2371 | ||
72246da4 | 2372 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 2373 | if (is_on) { |
9af21dd6 | 2374 | if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) { |
802fde98 PZ |
2375 | reg &= ~DWC3_DCTL_TRGTULST_MASK; |
2376 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
2377 | } | |
2378 | ||
9af21dd6 | 2379 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
2380 | reg &= ~DWC3_DCTL_KEEP_CONNECT; |
2381 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
2382 | |
2383 | if (dwc->has_hibernation) | |
2384 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
2385 | ||
7c9a2598 | 2386 | __dwc3_gadget_set_speed(dwc); |
9fcb3bd8 | 2387 | dwc->pullups_connected = true; |
8db7ed15 | 2388 | } else { |
72246da4 | 2389 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
2390 | |
2391 | if (dwc->has_hibernation && !suspend) | |
2392 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
2393 | ||
9fcb3bd8 | 2394 | dwc->pullups_connected = false; |
8db7ed15 | 2395 | } |
72246da4 | 2396 | |
5b738211 | 2397 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
2398 | |
2399 | do { | |
2400 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
2401 | reg &= DWC3_DSTS_DEVCTRLHLT; |
2402 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
2403 | |
2404 | if (!timeout) | |
2405 | return -ETIMEDOUT; | |
72246da4 | 2406 | |
6f17f74b | 2407 | return 0; |
72246da4 FB |
2408 | } |
2409 | ||
ae7e8610 WC |
2410 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc); |
2411 | static void __dwc3_gadget_stop(struct dwc3 *dwc); | |
a1383b35 | 2412 | static int __dwc3_gadget_start(struct dwc3 *dwc); |
ae7e8610 | 2413 | |
72246da4 FB |
2414 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) |
2415 | { | |
2416 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2417 | unsigned long flags; | |
6f17f74b | 2418 | int ret; |
72246da4 FB |
2419 | |
2420 | is_on = !!is_on; | |
2421 | ||
bb014736 BW |
2422 | /* |
2423 | * Per databook, when we want to stop the gadget, if a control transfer | |
2424 | * is still in process, complete it and get the core into setup phase. | |
2425 | */ | |
2426 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
2427 | reinit_completion(&dwc->ep0_in_setup); | |
2428 | ||
2429 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
2430 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
4a1e25c0 WC |
2431 | if (ret == 0) |
2432 | dev_warn(dwc->dev, "timed out waiting for SETUP phase\n"); | |
bb014736 BW |
2433 | } |
2434 | ||
cb10f68a WC |
2435 | /* |
2436 | * Avoid issuing a runtime resume if the device is already in the | |
2437 | * suspended state during gadget disconnect. DWC3 gadget was already | |
2438 | * halted/stopped during runtime suspend. | |
2439 | */ | |
2440 | if (!is_on) { | |
2441 | pm_runtime_barrier(dwc->dev); | |
2442 | if (pm_runtime_suspended(dwc->dev)) | |
2443 | return 0; | |
2444 | } | |
2445 | ||
77adb8bd WC |
2446 | /* |
2447 | * Check the return value for successful resume, or error. For a | |
2448 | * successful resume, the DWC3 runtime PM resume routine will handle | |
2449 | * the run stop sequence, so avoid duplicate operations here. | |
2450 | */ | |
2451 | ret = pm_runtime_get_sync(dwc->dev); | |
2452 | if (!ret || ret < 0) { | |
2453 | pm_runtime_put(dwc->dev); | |
2454 | return 0; | |
2455 | } | |
2456 | ||
ae7e8610 | 2457 | /* |
82129373 WC |
2458 | * Synchronize and disable any further event handling while controller |
2459 | * is being enabled/disabled. | |
ae7e8610 | 2460 | */ |
82129373 | 2461 | disable_irq(dwc->irq_gadget); |
ae7e8610 | 2462 | |
72246da4 | 2463 | spin_lock_irqsave(&dwc->lock, flags); |
ae7e8610 WC |
2464 | |
2465 | if (!is_on) { | |
2466 | u32 count; | |
2467 | ||
f09ddcfc | 2468 | dwc->connected = false; |
ae7e8610 WC |
2469 | /* |
2470 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
2471 | * Section 4.1.8 Table 4-7, it states that for a device-initiated | |
2472 | * disconnect, the SW needs to ensure that it sends "a DEPENDXFER | |
2473 | * command for any active transfers" before clearing the RunStop | |
2474 | * bit. | |
2475 | */ | |
2476 | dwc3_stop_active_transfers(dwc); | |
2477 | __dwc3_gadget_stop(dwc); | |
2478 | ||
2479 | /* | |
2480 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
2481 | * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the | |
2482 | * "software needs to acknowledge the events that are generated | |
2483 | * (by writing to GEVNTCOUNTn) while it is waiting for this bit | |
2484 | * to be set to '1'." | |
2485 | */ | |
2486 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); | |
2487 | count &= DWC3_GEVNTCOUNT_MASK; | |
2488 | if (count > 0) { | |
2489 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); | |
2490 | dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) % | |
2491 | dwc->ev_buf->length; | |
2492 | } | |
a1383b35 WC |
2493 | } else { |
2494 | __dwc3_gadget_start(dwc); | |
ae7e8610 WC |
2495 | } |
2496 | ||
7b2a0368 | 2497 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 | 2498 | spin_unlock_irqrestore(&dwc->lock, flags); |
82129373 WC |
2499 | enable_irq(dwc->irq_gadget); |
2500 | ||
77adb8bd | 2501 | pm_runtime_put(dwc->dev); |
72246da4 | 2502 | |
6f17f74b | 2503 | return ret; |
72246da4 FB |
2504 | } |
2505 | ||
8698e2ac FB |
2506 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
2507 | { | |
2508 | u32 reg; | |
2509 | ||
2510 | /* Enable all but Start and End of Frame IRQs */ | |
132ee0da | 2511 | reg = (DWC3_DEVTEN_EVNTOVERFLOWEN | |
8698e2ac FB |
2512 | DWC3_DEVTEN_CMDCMPLTEN | |
2513 | DWC3_DEVTEN_ERRTICERREN | | |
2514 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
2515 | DWC3_DEVTEN_CONNECTDONEEN | |
2516 | DWC3_DEVTEN_USBRSTEN | | |
2517 | DWC3_DEVTEN_DISCONNEVTEN); | |
2518 | ||
9af21dd6 | 2519 | if (DWC3_VER_IS_PRIOR(DWC3, 250A)) |
799e9dc8 FB |
2520 | reg |= DWC3_DEVTEN_ULSTCNGEN; |
2521 | ||
d1d90dd2 JP |
2522 | /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */ |
2523 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) | |
6f26ebb7 | 2524 | reg |= DWC3_DEVTEN_U3L2L1SUSPEN; |
d1d90dd2 | 2525 | |
8698e2ac FB |
2526 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
2527 | } | |
2528 | ||
2529 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
2530 | { | |
2531 | /* mask all interrupts */ | |
2532 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2533 | } | |
2534 | ||
2535 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 2536 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 2537 | |
4e99472b | 2538 | /** |
bfad65ee FB |
2539 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
2540 | * @dwc: pointer to our context structure | |
4e99472b FB |
2541 | * |
2542 | * The following looks like complex but it's actually very simple. In order to | |
2543 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
2544 | * gonna use RxFIFO size. | |
2545 | * | |
2546 | * To calculate RxFIFO size we need two numbers: | |
2547 | * MDWIDTH = size, in bits, of the internal memory bus | |
2548 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
2549 | * | |
2550 | * Given these two numbers, the formula is simple: | |
2551 | * | |
2552 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
2553 | * | |
2554 | * 24 bytes is for 3x SETUP packets | |
2555 | * 16 bytes is a clock domain crossing tolerance | |
2556 | * | |
2557 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
2558 | */ | |
2559 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
2560 | { | |
2561 | u32 ram2_depth; | |
2562 | u32 mdwidth; | |
2563 | u32 nump; | |
2564 | u32 reg; | |
2565 | ||
2566 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
d00be779 | 2567 | mdwidth = dwc3_mdwidth(dwc); |
4e99472b FB |
2568 | |
2569 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
2570 | nump = min_t(u32, nump, 16); | |
2571 | ||
2572 | /* update NumP */ | |
2573 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2574 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
2575 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
2576 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2577 | } | |
2578 | ||
d7be2952 | 2579 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 2580 | { |
72246da4 | 2581 | struct dwc3_ep *dep; |
72246da4 FB |
2582 | int ret = 0; |
2583 | u32 reg; | |
2584 | ||
cf40b86b JY |
2585 | /* |
2586 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
2587 | * the core supports IMOD, disable it. | |
2588 | */ | |
2589 | if (dwc->imod_interval) { | |
2590 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
2591 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
2592 | } else if (dwc3_has_imod(dwc)) { | |
2593 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
2594 | } | |
2595 | ||
2a58f9c1 FB |
2596 | /* |
2597 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
2598 | * field instead of letting dwc3 itself calculate that automatically. | |
2599 | * | |
2600 | * This way, we maximize the chances that we'll be able to get several | |
2601 | * bursts of data without going through any sort of endpoint throttling. | |
2602 | */ | |
2603 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
9af21dd6 | 2604 | if (DWC3_IP_IS(DWC3)) |
01b0e2cc | 2605 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; |
9af21dd6 TN |
2606 | else |
2607 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
01b0e2cc | 2608 | |
2a58f9c1 FB |
2609 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
2610 | ||
4e99472b FB |
2611 | dwc3_gadget_setup_nump(dwc); |
2612 | ||
e66bbfb0 TN |
2613 | /* |
2614 | * Currently the controller handles single stream only. So, Ignore | |
2615 | * Packet Pending bit for stream selection and don't search for another | |
2616 | * stream if the host sends Data Packet with PP=0 (for OUT direction) or | |
2617 | * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves | |
2618 | * the stream performance. | |
2619 | */ | |
2620 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2621 | reg |= DWC3_DCFG_IGNSTRMPP; | |
2622 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2623 | ||
72246da4 FB |
2624 | /* Start with SuperSpeed Default */ |
2625 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2626 | ||
2627 | dep = dwc->eps[0]; | |
a2d23f08 | 2628 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2629 | if (ret) { |
2630 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2631 | goto err0; |
72246da4 FB |
2632 | } |
2633 | ||
2634 | dep = dwc->eps[1]; | |
a2d23f08 | 2635 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2636 | if (ret) { |
2637 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2638 | goto err1; |
72246da4 FB |
2639 | } |
2640 | ||
2641 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2642 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2643 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
4a1e25c0 | 2644 | dwc->delayed_status = false; |
72246da4 FB |
2645 | dwc3_ep0_out_start(dwc); |
2646 | ||
8698e2ac FB |
2647 | dwc3_gadget_enable_irq(dwc); |
2648 | ||
72246da4 FB |
2649 | return 0; |
2650 | ||
b0d7ffd4 | 2651 | err1: |
d7be2952 | 2652 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2653 | |
2654 | err0: | |
72246da4 FB |
2655 | return ret; |
2656 | } | |
2657 | ||
d7be2952 FB |
2658 | static int dwc3_gadget_start(struct usb_gadget *g, |
2659 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2660 | { |
2661 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2662 | unsigned long flags; | |
8cf9045b | 2663 | int ret; |
8698e2ac | 2664 | int irq; |
72246da4 | 2665 | |
9522def4 | 2666 | irq = dwc->irq_gadget; |
d7be2952 FB |
2667 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2668 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2669 | if (ret) { | |
2670 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2671 | irq, ret); | |
8cf9045b | 2672 | return ret; |
d7be2952 FB |
2673 | } |
2674 | ||
72246da4 | 2675 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2676 | dwc->gadget_driver = driver; |
d7be2952 FB |
2677 | spin_unlock_irqrestore(&dwc->lock, flags); |
2678 | ||
2679 | return 0; | |
d7be2952 | 2680 | } |
72246da4 | 2681 | |
d7be2952 FB |
2682 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2683 | { | |
8698e2ac | 2684 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2685 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2686 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2687 | } |
72246da4 | 2688 | |
d7be2952 FB |
2689 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2690 | { | |
2691 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2692 | unsigned long flags; | |
72246da4 | 2693 | |
d7be2952 | 2694 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2695 | dwc->gadget_driver = NULL; |
9f607a30 | 2696 | dwc->max_cfg_eps = 0; |
72246da4 FB |
2697 | spin_unlock_irqrestore(&dwc->lock, flags); |
2698 | ||
3f308d17 | 2699 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2700 | |
72246da4 FB |
2701 | return 0; |
2702 | } | |
802fde98 | 2703 | |
729dcffd AKV |
2704 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2705 | struct usb_dcd_config_params *params) | |
2706 | { | |
2707 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2708 | ||
54fb5ba6 TN |
2709 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2710 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2711 | ||
2712 | /* Recommended BESL */ | |
2713 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2714 | /* |
2715 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2716 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2717 | * a usb reset immediately after it receives the extended BOS | |
2718 | * descriptor and the enumeration will fail. To maintain | |
2719 | * compatibility with the Windows' usb stack, let's set the | |
2720 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2721 | * within 2 to 15. | |
2722 | */ | |
2723 | params->besl_baseline = 1; | |
54fb5ba6 | 2724 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2725 | params->besl_deep = |
2726 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2727 | } |
2728 | ||
729dcffd AKV |
2729 | /* U1 Device exit Latency */ |
2730 | if (dwc->dis_u1_entry_quirk) | |
2731 | params->bU1devExitLat = 0; | |
2732 | else | |
2733 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2734 | ||
2735 | /* U2 Device exit Latency */ | |
2736 | if (dwc->dis_u2_entry_quirk) | |
2737 | params->bU2DevExitLat = 0; | |
2738 | else | |
2739 | params->bU2DevExitLat = | |
2740 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2741 | } | |
2742 | ||
7d8d0639 FB |
2743 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2744 | enum usb_device_speed speed) | |
2745 | { | |
2746 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2747 | unsigned long flags; | |
7d8d0639 FB |
2748 | |
2749 | spin_lock_irqsave(&dwc->lock, flags); | |
7c9a2598 | 2750 | dwc->gadget_max_speed = speed; |
7d8d0639 FB |
2751 | spin_unlock_irqrestore(&dwc->lock, flags); |
2752 | } | |
2753 | ||
072cab8a TN |
2754 | static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g, |
2755 | enum usb_ssp_rate rate) | |
2756 | { | |
2757 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2758 | unsigned long flags; | |
2759 | ||
2760 | spin_lock_irqsave(&dwc->lock, flags); | |
cdb651b6 | 2761 | dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS; |
072cab8a TN |
2762 | dwc->gadget_ssp_rate = rate; |
2763 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2764 | } | |
2765 | ||
82c46b8e WC |
2766 | static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) |
2767 | { | |
2768 | struct dwc3 *dwc = gadget_to_dwc(g); | |
99288de3 RC |
2769 | union power_supply_propval val = {0}; |
2770 | int ret; | |
82c46b8e WC |
2771 | |
2772 | if (dwc->usb2_phy) | |
2773 | return usb_phy_set_power(dwc->usb2_phy, mA); | |
2774 | ||
99288de3 RC |
2775 | if (!dwc->usb_psy) |
2776 | return -EOPNOTSUPP; | |
2777 | ||
8a5b5c3c | 2778 | val.intval = 1000 * mA; |
99288de3 RC |
2779 | ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); |
2780 | ||
2781 | return ret; | |
82c46b8e WC |
2782 | } |
2783 | ||
9f607a30 WC |
2784 | /** |
2785 | * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration | |
2786 | * @g: pointer to the USB gadget | |
2787 | * | |
2788 | * Used to record the maximum number of endpoints being used in a USB composite | |
2789 | * device. (across all configurations) This is to be used in the calculation | |
2790 | * of the TXFIFO sizes when resizing internal memory for individual endpoints. | |
2791 | * It will help ensured that the resizing logic reserves enough space for at | |
2792 | * least one max packet. | |
2793 | */ | |
2794 | static int dwc3_gadget_check_config(struct usb_gadget *g) | |
2795 | { | |
2796 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2797 | struct usb_ep *ep; | |
2798 | int fifo_size = 0; | |
2799 | int ram1_depth; | |
2800 | int ep_num = 0; | |
2801 | ||
2802 | if (!dwc->do_fifo_resize) | |
2803 | return 0; | |
2804 | ||
2805 | list_for_each_entry(ep, &g->ep_list, ep_list) { | |
2806 | /* Only interested in the IN endpoints */ | |
2807 | if (ep->claimed && (ep->address & USB_DIR_IN)) | |
2808 | ep_num++; | |
2809 | } | |
2810 | ||
2811 | if (ep_num <= dwc->max_cfg_eps) | |
2812 | return 0; | |
2813 | ||
2814 | /* Update the max number of eps in the composition */ | |
2815 | dwc->max_cfg_eps = ep_num; | |
2816 | ||
2817 | fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps); | |
2818 | /* Based on the equation, increment by one for every ep */ | |
2819 | fifo_size += dwc->max_cfg_eps; | |
2820 | ||
2821 | /* Check if we can fit a single fifo per endpoint */ | |
2822 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
2823 | if (fifo_size > ram1_depth) | |
2824 | return -ENOMEM; | |
2825 | ||
2826 | return 0; | |
2827 | } | |
2828 | ||
40edb522 LY |
2829 | static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable) |
2830 | { | |
2831 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2832 | unsigned long flags; | |
2833 | ||
2834 | spin_lock_irqsave(&dwc->lock, flags); | |
2835 | dwc->async_callbacks = enable; | |
2836 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2837 | } | |
2838 | ||
72246da4 FB |
2839 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2840 | .get_frame = dwc3_gadget_get_frame, | |
2841 | .wakeup = dwc3_gadget_wakeup, | |
2842 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2843 | .pullup = dwc3_gadget_pullup, | |
2844 | .udc_start = dwc3_gadget_start, | |
2845 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2846 | .udc_set_speed = dwc3_gadget_set_speed, |
072cab8a | 2847 | .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate, |
729dcffd | 2848 | .get_config_params = dwc3_gadget_config_params, |
82c46b8e | 2849 | .vbus_draw = dwc3_gadget_vbus_draw, |
9f607a30 | 2850 | .check_config = dwc3_gadget_check_config, |
40edb522 | 2851 | .udc_async_callbacks = dwc3_gadget_async_callbacks, |
72246da4 FB |
2852 | }; |
2853 | ||
2854 | /* -------------------------------------------------------------------------- */ | |
2855 | ||
8f1c99cd | 2856 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2857 | { |
8f1c99cd | 2858 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2859 | |
8f1c99cd FB |
2860 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2861 | dep->endpoint.maxburst = 1; | |
2862 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2863 | if (!dep->direction) | |
e81a7018 | 2864 | dwc->gadget->ep0 = &dep->endpoint; |
f3bcfc7e | 2865 | |
8f1c99cd | 2866 | dep->endpoint.caps.type_control = true; |
72246da4 | 2867 | |
8f1c99cd FB |
2868 | return 0; |
2869 | } | |
72246da4 | 2870 | |
8f1c99cd FB |
2871 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2872 | { | |
2873 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2874 | u32 mdwidth; |
8f1c99cd | 2875 | int size; |
72246da4 | 2876 | |
d00be779 | 2877 | mdwidth = dwc3_mdwidth(dwc); |
4244ba02 | 2878 | |
8f1c99cd FB |
2879 | /* MDWIDTH is represented in bits, we need it in bytes */ |
2880 | mdwidth /= 8; | |
6a1e3ef4 | 2881 | |
8f1c99cd | 2882 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
9af21dd6 | 2883 | if (DWC3_IP_IS(DWC3)) |
586f4335 | 2884 | size = DWC3_GTXFIFOSIZ_TXFDEP(size); |
9af21dd6 TN |
2885 | else |
2886 | size = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
39ebb05c | 2887 | |
8f1c99cd FB |
2888 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2889 | size *= mdwidth; | |
39ebb05c | 2890 | |
8f1c99cd | 2891 | /* |
d94ea531 TN |
2892 | * To meet performance requirement, a minimum TxFIFO size of 3x |
2893 | * MaxPacketSize is recommended for endpoints that support burst and a | |
2894 | * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't | |
2895 | * support burst. Use those numbers and we can calculate the max packet | |
2896 | * limit as below. | |
8f1c99cd | 2897 | */ |
d94ea531 TN |
2898 | if (dwc->maximum_speed >= USB_SPEED_SUPER) |
2899 | size /= 3; | |
2900 | else | |
2901 | size /= 2; | |
28781789 | 2902 | |
8f1c99cd | 2903 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2904 | |
e0a93d98 | 2905 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2906 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2907 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2908 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2909 | dep->endpoint.caps.type_iso = true; |
2910 | dep->endpoint.caps.type_bulk = true; | |
2911 | dep->endpoint.caps.type_int = true; | |
28781789 | 2912 | |
8f1c99cd FB |
2913 | return dwc3_alloc_trb_pool(dep); |
2914 | } | |
28781789 | 2915 | |
8f1c99cd FB |
2916 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2917 | { | |
2918 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2919 | u32 mdwidth; |
d94ea531 TN |
2920 | int size; |
2921 | ||
d00be779 | 2922 | mdwidth = dwc3_mdwidth(dwc); |
d94ea531 TN |
2923 | |
2924 | /* MDWIDTH is represented in bits, convert to bytes */ | |
2925 | mdwidth /= 8; | |
28781789 | 2926 | |
d94ea531 TN |
2927 | /* All OUT endpoints share a single RxFIFO space */ |
2928 | size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); | |
9af21dd6 | 2929 | if (DWC3_IP_IS(DWC3)) |
d94ea531 | 2930 | size = DWC3_GRXFIFOSIZ_RXFDEP(size); |
9af21dd6 TN |
2931 | else |
2932 | size = DWC31_GRXFIFOSIZ_RXFDEP(size); | |
d94ea531 TN |
2933 | |
2934 | /* FIFO depth is in MDWDITH bytes */ | |
2935 | size *= mdwidth; | |
2936 | ||
2937 | /* | |
2938 | * To meet performance requirement, a minimum recommended RxFIFO size | |
2939 | * is defined as follow: | |
2940 | * RxFIFO size >= (3 x MaxPacketSize) + | |
2941 | * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin) | |
2942 | * | |
2943 | * Then calculate the max packet limit as below. | |
2944 | */ | |
2945 | size -= (3 * 8) + 16; | |
2946 | if (size < 0) | |
2947 | size = 0; | |
2948 | else | |
2949 | size /= 3; | |
2950 | ||
2951 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
e0a93d98 | 2952 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2953 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2954 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2955 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2956 | dep->endpoint.caps.type_iso = true; |
2957 | dep->endpoint.caps.type_bulk = true; | |
2958 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2959 | |
8f1c99cd FB |
2960 | return dwc3_alloc_trb_pool(dep); |
2961 | } | |
72246da4 | 2962 | |
8f1c99cd FB |
2963 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2964 | { | |
2965 | struct dwc3_ep *dep; | |
2966 | bool direction = epnum & 1; | |
2967 | int ret; | |
2968 | u8 num = epnum >> 1; | |
25b8ff68 | 2969 | |
8f1c99cd FB |
2970 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2971 | if (!dep) | |
2972 | return -ENOMEM; | |
2973 | ||
2974 | dep->dwc = dwc; | |
2975 | dep->number = epnum; | |
2976 | dep->direction = direction; | |
2977 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2978 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2979 | dep->combo_num = 0; |
2980 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2981 | |
2982 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2983 | direction ? "in" : "out"); | |
2984 | ||
2985 | dep->endpoint.name = dep->name; | |
2986 | ||
2987 | if (!(dep->number > 1)) { | |
2988 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2989 | dep->endpoint.comp_desc = NULL; | |
2990 | } | |
2991 | ||
8f1c99cd FB |
2992 | if (num == 0) |
2993 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2994 | else if (direction) | |
2995 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2996 | else | |
2997 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2998 | ||
2999 | if (ret) | |
3000 | return ret; | |
a474d3b7 | 3001 | |
8f1c99cd FB |
3002 | dep->endpoint.caps.dir_in = direction; |
3003 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 3004 | |
8f1c99cd FB |
3005 | INIT_LIST_HEAD(&dep->pending_list); |
3006 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 3007 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd | 3008 | |
5ff90af9 JP |
3009 | dwc3_debugfs_create_endpoint_dir(dep); |
3010 | ||
8f1c99cd FB |
3011 | return 0; |
3012 | } | |
3013 | ||
3014 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
3015 | { | |
3016 | u8 epnum; | |
3017 | ||
e81a7018 | 3018 | INIT_LIST_HEAD(&dwc->gadget->ep_list); |
8f1c99cd FB |
3019 | |
3020 | for (epnum = 0; epnum < total; epnum++) { | |
3021 | int ret; | |
3022 | ||
3023 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
3024 | if (ret) | |
3025 | return ret; | |
72246da4 FB |
3026 | } |
3027 | ||
3028 | return 0; | |
3029 | } | |
3030 | ||
3031 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
3032 | { | |
3033 | struct dwc3_ep *dep; | |
3034 | u8 epnum; | |
3035 | ||
3036 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3037 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3038 | if (!dep) |
3039 | continue; | |
5bf8fae3 GC |
3040 | /* |
3041 | * Physical endpoints 0 and 1 are special; they form the | |
3042 | * bi-directional USB endpoint 0. | |
3043 | * | |
3044 | * For those two physical endpoints, we don't allocate a TRB | |
3045 | * pool nor do we add them the endpoints list. Due to that, we | |
3046 | * shouldn't do these two operations otherwise we would end up | |
3047 | * with all sorts of bugs when removing dwc3.ko. | |
3048 | */ | |
3049 | if (epnum != 0 && epnum != 1) { | |
3050 | dwc3_free_trb_pool(dep); | |
72246da4 | 3051 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 3052 | } |
72246da4 | 3053 | |
8562d5bf GKH |
3054 | debugfs_remove_recursive(debugfs_lookup(dep->name, |
3055 | debugfs_lookup(dev_name(dep->dwc->dev), | |
3056 | usb_debug_root))); | |
72246da4 FB |
3057 | kfree(dep); |
3058 | } | |
3059 | } | |
3060 | ||
72246da4 | 3061 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 3062 | |
8f608e8a FB |
3063 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
3064 | struct dwc3_request *req, struct dwc3_trb *trb, | |
3065 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 3066 | { |
72246da4 | 3067 | unsigned int count; |
72246da4 | 3068 | |
dc55c67e | 3069 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 3070 | |
2c4cbe6e | 3071 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 3072 | req->num_trbs--; |
2c4cbe6e | 3073 | |
e5b36ae2 FB |
3074 | /* |
3075 | * If we're in the middle of series of chained TRBs and we | |
3076 | * receive a short transfer along the way, DWC3 will skip | |
3077 | * through all TRBs including the last TRB in the chain (the | |
3078 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
3079 | * bit and SW has to do it manually. | |
3080 | * | |
3081 | * We're going to do that here to avoid problems of HW trying | |
3082 | * to use bogus TRBs for transfers. | |
3083 | */ | |
3084 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
3085 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
3086 | ||
6abfa0f5 TN |
3087 | /* |
3088 | * For isochronous transfers, the first TRB in a service interval must | |
3089 | * have the Isoc-First type. Track and report its interval frame number. | |
3090 | */ | |
3091 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
3092 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
3093 | unsigned int frame_number; | |
3094 | ||
3095 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
3096 | frame_number &= ~(dep->interval - 1); | |
3097 | req->request.frame_number = frame_number; | |
3098 | } | |
3099 | ||
c6267a51 | 3100 | /* |
a2841f41 TN |
3101 | * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If |
3102 | * this TRB points to the bounce buffer address, it's a MPS alignment | |
3103 | * TRB. Don't add it to req->remaining calculation. | |
c6267a51 | 3104 | */ |
a2841f41 TN |
3105 | if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) && |
3106 | trb->bph == upper_32_bits(dep->dwc->bounce_addr)) { | |
c6267a51 FB |
3107 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
3108 | return 1; | |
3109 | } | |
3110 | ||
e5ba5ec8 | 3111 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 3112 | req->remaining += count; |
e5ba5ec8 | 3113 | |
35b2719e FB |
3114 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
3115 | return 1; | |
3116 | ||
d80fe1b6 | 3117 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 3118 | return 1; |
f99f53f2 | 3119 | |
5ee85897 AKV |
3120 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
3121 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 3122 | return 1; |
f99f53f2 | 3123 | |
e5ba5ec8 PA |
3124 | return 0; |
3125 | } | |
3126 | ||
d3692953 FB |
3127 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
3128 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
3129 | int status) | |
3130 | { | |
3131 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
3132 | struct scatterlist *sg = req->sg; | |
3133 | struct scatterlist *s; | |
25dda9fc | 3134 | unsigned int num_queued = req->num_queued_sgs; |
d3692953 FB |
3135 | unsigned int i; |
3136 | int ret = 0; | |
3137 | ||
25dda9fc | 3138 | for_each_sg(sg, s, num_queued, i) { |
d3692953 FB |
3139 | trb = &dep->trb_pool[dep->trb_dequeue]; |
3140 | ||
d3692953 | 3141 | req->sg = sg_next(s); |
25dda9fc | 3142 | req->num_queued_sgs--; |
d3692953 FB |
3143 | |
3144 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
3145 | trb, event, status, true); | |
3146 | if (ret) | |
3147 | break; | |
3148 | } | |
3149 | ||
3150 | return ret; | |
3151 | } | |
3152 | ||
3153 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
3154 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
3155 | int status) | |
3156 | { | |
3157 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
3158 | ||
3159 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
3160 | event, status, false); | |
3161 | } | |
3162 | ||
e0c42ce5 FB |
3163 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
3164 | { | |
25dda9fc | 3165 | return req->num_pending_sgs == 0 && req->num_queued_sgs == 0; |
e0c42ce5 FB |
3166 | } |
3167 | ||
f38e35dd FB |
3168 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
3169 | const struct dwc3_event_depevt *event, | |
3170 | struct dwc3_request *req, int status) | |
3171 | { | |
3172 | int ret; | |
3173 | ||
25dda9fc | 3174 | if (req->request.num_mapped_sgs) |
f38e35dd FB |
3175 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, |
3176 | status); | |
3177 | else | |
3178 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
3179 | status); | |
3180 | ||
690e5c2d TN |
3181 | req->request.actual = req->request.length - req->remaining; |
3182 | ||
3183 | if (!dwc3_gadget_ep_request_completed(req)) | |
3184 | goto out; | |
3185 | ||
1a22ec64 | 3186 | if (req->needs_extra_trb) { |
f38e35dd FB |
3187 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
3188 | status); | |
1a22ec64 | 3189 | req->needs_extra_trb = false; |
f38e35dd FB |
3190 | } |
3191 | ||
f38e35dd FB |
3192 | dwc3_gadget_giveback(dep, req, status); |
3193 | ||
3194 | out: | |
3195 | return ret; | |
3196 | } | |
3197 | ||
12a3a4ad | 3198 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 3199 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 3200 | { |
6afbdb57 FB |
3201 | struct dwc3_request *req; |
3202 | struct dwc3_request *tmp; | |
e5ba5ec8 | 3203 | |
664cc971 | 3204 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 3205 | int ret; |
e5b36ae2 | 3206 | |
f38e35dd FB |
3207 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
3208 | req, status); | |
58f0218a | 3209 | if (ret) |
72246da4 | 3210 | break; |
31162af4 | 3211 | } |
72246da4 FB |
3212 | } |
3213 | ||
d9feef97 TN |
3214 | static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep) |
3215 | { | |
3216 | struct dwc3_request *req; | |
02fa4b98 WC |
3217 | struct dwc3 *dwc = dep->dwc; |
3218 | ||
3219 | if (!dep->endpoint.desc || !dwc->pullups_connected || | |
3220 | !dwc->connected) | |
3221 | return false; | |
d9feef97 TN |
3222 | |
3223 | if (!list_empty(&dep->pending_list)) | |
3224 | return true; | |
3225 | ||
3226 | /* | |
3227 | * We only need to check the first entry of the started list. We can | |
3228 | * assume the completed requests are removed from the started list. | |
3229 | */ | |
3230 | req = next_request(&dep->started_list); | |
3231 | if (!req) | |
3232 | return false; | |
3233 | ||
3234 | return !dwc3_gadget_ep_request_completed(req); | |
3235 | } | |
3236 | ||
ee3638b8 FB |
3237 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
3238 | const struct dwc3_event_depevt *event) | |
3239 | { | |
f62afb49 | 3240 | dep->frame_number = event->parameters; |
ee3638b8 FB |
3241 | } |
3242 | ||
2e6e9e4b TN |
3243 | static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep, |
3244 | const struct dwc3_event_depevt *event, int status) | |
72246da4 | 3245 | { |
8f608e8a | 3246 | struct dwc3 *dwc = dep->dwc; |
2e6e9e4b | 3247 | bool no_started_trb = true; |
6d8a0196 | 3248 | |
5f2e7975 | 3249 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 3250 | |
b6842d49 TN |
3251 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) |
3252 | goto out; | |
3253 | ||
f5e46aa4 MG |
3254 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
3255 | list_empty(&dep->started_list) && | |
3256 | (list_empty(&dep->pending_list) || status == -EXDEV)) | |
c5353b22 | 3257 | dwc3_stop_active_transfer(dep, true, true); |
d9feef97 | 3258 | else if (dwc3_gadget_ep_should_continue(dep)) |
2e6e9e4b TN |
3259 | if (__dwc3_gadget_kick_transfer(dep) == 0) |
3260 | no_started_trb = false; | |
6d8a0196 | 3261 | |
b6842d49 | 3262 | out: |
fae2b904 FB |
3263 | /* |
3264 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
3265 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
3266 | */ | |
9af21dd6 | 3267 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3268 | u32 reg; |
3269 | int i; | |
3270 | ||
3271 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 3272 | dep = dwc->eps[i]; |
fae2b904 FB |
3273 | |
3274 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
3275 | continue; | |
3276 | ||
aa3342c8 | 3277 | if (!list_empty(&dep->started_list)) |
2e6e9e4b | 3278 | return no_started_trb; |
fae2b904 FB |
3279 | } |
3280 | ||
3281 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3282 | reg |= dwc->u1u2; | |
3283 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3284 | ||
3285 | dwc->u1u2 = 0; | |
3286 | } | |
2e6e9e4b TN |
3287 | |
3288 | return no_started_trb; | |
3289 | } | |
3290 | ||
3291 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, | |
3292 | const struct dwc3_event_depevt *event) | |
3293 | { | |
3294 | int status = 0; | |
3295 | ||
3296 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
3297 | dwc3_gadget_endpoint_frame_from_event(dep, event); | |
3298 | ||
3299 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3300 | status = -ECONNRESET; | |
3301 | ||
3302 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) | |
3303 | status = -EXDEV; | |
3304 | ||
3305 | dwc3_gadget_endpoint_trbs_complete(dep, event, status); | |
72246da4 FB |
3306 | } |
3307 | ||
3eaecd0c TN |
3308 | static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep, |
3309 | const struct dwc3_event_depevt *event) | |
3310 | { | |
3311 | int status = 0; | |
3312 | ||
3313 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3314 | ||
3315 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3316 | status = -ECONNRESET; | |
3317 | ||
e0d19563 TN |
3318 | if (dwc3_gadget_endpoint_trbs_complete(dep, event, status)) |
3319 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
72246da4 FB |
3320 | } |
3321 | ||
8f608e8a FB |
3322 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
3323 | const struct dwc3_event_depevt *event) | |
32033865 | 3324 | { |
ee3638b8 | 3325 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
36f05d36 TN |
3326 | |
3327 | /* | |
3328 | * The XferNotReady event is generated only once before the endpoint | |
3329 | * starts. It will be generated again when END_TRANSFER command is | |
3330 | * issued. For some controller versions, the XferNotReady event may be | |
3331 | * generated while the END_TRANSFER command is still in process. Ignore | |
3332 | * it and wait for the next XferNotReady event after the command is | |
3333 | * completed. | |
3334 | */ | |
3335 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) | |
3336 | return; | |
3337 | ||
25abad6a | 3338 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
3339 | } |
3340 | ||
8266b08e TN |
3341 | static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep, |
3342 | const struct dwc3_event_depevt *event) | |
3343 | { | |
3344 | u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters); | |
3345 | ||
3346 | if (cmd != DWC3_DEPCMD_ENDTRANSFER) | |
3347 | return; | |
3348 | ||
3349 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
3350 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3351 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
3352 | ||
3353 | if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) { | |
3354 | struct dwc3 *dwc = dep->dwc; | |
3355 | ||
3356 | dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL; | |
3357 | if (dwc3_send_clear_stall_ep_cmd(dep)) { | |
3358 | struct usb_ep *ep0 = &dwc->eps[0]->endpoint; | |
3359 | ||
3360 | dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name); | |
3361 | if (dwc->delayed_status) | |
3362 | __dwc3_gadget_ep0_set_halt(ep0, 1); | |
3363 | return; | |
3364 | } | |
3365 | ||
3366 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
3367 | if (dwc->delayed_status) | |
3368 | dwc3_ep0_send_delayed_status(dwc); | |
3369 | } | |
3370 | ||
3371 | if ((dep->flags & DWC3_EP_DELAY_START) && | |
3372 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
3373 | __dwc3_gadget_kick_transfer(dep); | |
3374 | ||
3375 | dep->flags &= ~DWC3_EP_DELAY_START; | |
3376 | } | |
3377 | ||
140ca4cf TN |
3378 | static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep, |
3379 | const struct dwc3_event_depevt *event) | |
3380 | { | |
3381 | struct dwc3 *dwc = dep->dwc; | |
3382 | ||
3383 | if (event->status == DEPEVT_STREAMEVT_FOUND) { | |
3384 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3385 | goto out; | |
3386 | } | |
3387 | ||
3388 | /* Note: NoStream rejection event param value is 0 and not 0xFFFF */ | |
3389 | switch (event->parameters) { | |
3390 | case DEPEVT_STREAM_PRIME: | |
3391 | /* | |
3392 | * If the host can properly transition the endpoint state from | |
3393 | * idle to prime after a NoStream rejection, there's no need to | |
3394 | * force restarting the endpoint to reinitiate the stream. To | |
3395 | * simplify the check, assume the host follows the USB spec if | |
3396 | * it primed the endpoint more than once. | |
3397 | */ | |
3398 | if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) { | |
3399 | if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED) | |
3400 | dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM; | |
3401 | else | |
3402 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3403 | } | |
3404 | ||
3405 | break; | |
3406 | case DEPEVT_STREAM_NOSTREAM: | |
3407 | if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) || | |
3408 | !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) || | |
3409 | !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)) | |
3410 | break; | |
3411 | ||
3412 | /* | |
3413 | * If the host rejects a stream due to no active stream, by the | |
3414 | * USB and xHCI spec, the endpoint will be put back to idle | |
3415 | * state. When the host is ready (buffer added/updated), it will | |
3416 | * prime the endpoint to inform the usb device controller. This | |
3417 | * triggers the device controller to issue ERDY to restart the | |
3418 | * stream. However, some hosts don't follow this and keep the | |
3419 | * endpoint in the idle state. No prime will come despite host | |
3420 | * streams are updated, and the device controller will not be | |
3421 | * triggered to generate ERDY to move the next stream data. To | |
3422 | * workaround this and maintain compatibility with various | |
3423 | * hosts, force to reinitate the stream until the host is ready | |
3424 | * instead of waiting for the host to prime the endpoint. | |
3425 | */ | |
b10e1c25 TN |
3426 | if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) { |
3427 | unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME; | |
3428 | ||
3429 | dwc3_send_gadget_generic_command(dwc, cmd, dep->number); | |
3430 | } else { | |
3431 | dep->flags |= DWC3_EP_DELAY_START; | |
3432 | dwc3_stop_active_transfer(dep, true, true); | |
3433 | return; | |
3434 | } | |
3435 | break; | |
140ca4cf TN |
3436 | } |
3437 | ||
3438 | out: | |
3439 | dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3440 | } | |
3441 | ||
72246da4 FB |
3442 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
3443 | const struct dwc3_event_depevt *event) | |
3444 | { | |
3445 | struct dwc3_ep *dep; | |
3446 | u8 epnum = event->endpoint_number; | |
3447 | ||
3448 | dep = dwc->eps[epnum]; | |
3449 | ||
d7fd41c6 | 3450 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 3451 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
3452 | return; |
3453 | ||
3454 | /* Handle only EPCMDCMPLT when EP disabled */ | |
3455 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
3456 | return; | |
3457 | } | |
3336abb5 | 3458 | |
72246da4 FB |
3459 | if (epnum == 0 || epnum == 1) { |
3460 | dwc3_ep0_interrupt(dwc, event); | |
3461 | return; | |
3462 | } | |
3463 | ||
3464 | switch (event->endpoint_event) { | |
72246da4 | 3465 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 3466 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
3467 | break; |
3468 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 3469 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 3470 | break; |
72246da4 | 3471 | case DWC3_DEPEVT_EPCMDCMPLT: |
8266b08e | 3472 | dwc3_gadget_endpoint_command_complete(dep, event); |
76a638f8 | 3473 | break; |
742a4fff | 3474 | case DWC3_DEPEVT_XFERCOMPLETE: |
3eaecd0c TN |
3475 | dwc3_gadget_endpoint_transfer_complete(dep, event); |
3476 | break; | |
3477 | case DWC3_DEPEVT_STREAMEVT: | |
140ca4cf TN |
3478 | dwc3_gadget_endpoint_stream_event(dep, event); |
3479 | break; | |
76a638f8 | 3480 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
3481 | break; |
3482 | } | |
3483 | } | |
3484 | ||
3485 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
3486 | { | |
40edb522 | 3487 | if (dwc->async_callbacks && dwc->gadget_driver->disconnect) { |
72246da4 | 3488 | spin_unlock(&dwc->lock); |
e81a7018 | 3489 | dwc->gadget_driver->disconnect(dwc->gadget); |
72246da4 FB |
3490 | spin_lock(&dwc->lock); |
3491 | } | |
3492 | } | |
3493 | ||
bc5ba2e0 FB |
3494 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
3495 | { | |
40edb522 | 3496 | if (dwc->async_callbacks && dwc->gadget_driver->suspend) { |
bc5ba2e0 | 3497 | spin_unlock(&dwc->lock); |
e81a7018 | 3498 | dwc->gadget_driver->suspend(dwc->gadget); |
bc5ba2e0 FB |
3499 | spin_lock(&dwc->lock); |
3500 | } | |
3501 | } | |
3502 | ||
3503 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
3504 | { | |
40edb522 | 3505 | if (dwc->async_callbacks && dwc->gadget_driver->resume) { |
bc5ba2e0 | 3506 | spin_unlock(&dwc->lock); |
e81a7018 | 3507 | dwc->gadget_driver->resume(dwc->gadget); |
5c7b3b02 | 3508 | spin_lock(&dwc->lock); |
8e74475b FB |
3509 | } |
3510 | } | |
3511 | ||
3512 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
3513 | { | |
3514 | if (!dwc->gadget_driver) | |
3515 | return; | |
3516 | ||
40edb522 | 3517 | if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) { |
8e74475b | 3518 | spin_unlock(&dwc->lock); |
e81a7018 | 3519 | usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver); |
bc5ba2e0 FB |
3520 | spin_lock(&dwc->lock); |
3521 | } | |
3522 | } | |
3523 | ||
c5353b22 FB |
3524 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
3525 | bool interrupt) | |
72246da4 | 3526 | { |
72246da4 FB |
3527 | struct dwc3_gadget_ep_cmd_params params; |
3528 | u32 cmd; | |
3529 | int ret; | |
3530 | ||
c58d8bfc TN |
3531 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
3532 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
3533 | return; |
3534 | ||
57911504 PA |
3535 | /* |
3536 | * NOTICE: We are violating what the Databook says about the | |
3537 | * EndTransfer command. Ideally we would _always_ wait for the | |
3538 | * EndTransfer Command Completion IRQ, but that's causing too | |
3539 | * much trouble synchronizing between us and gadget driver. | |
3540 | * | |
3541 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 3542 | * suggested to giveback all requests here. |
57911504 PA |
3543 | * |
3544 | * Note also that a similar handling was tested by Synopsys | |
3545 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
3546 | * In short, what we're doing is issuing EndTransfer with |
3547 | * CMDIOC bit set and delay kicking transfer until the | |
3548 | * EndTransfer command had completed. | |
06281d46 JY |
3549 | * |
3550 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
3551 | * supports a mode to work around the above limitation. The | |
3552 | * software can poll the CMDACT bit in the DEPCMD register | |
3553 | * after issuing a EndTransfer command. This mode is enabled | |
3554 | * by writing GUCTL2[14]. This polling is already done in the | |
3555 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
3556 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 3557 | * returning from this function. |
06281d46 JY |
3558 | * |
3559 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
3560 | */ |
3561 | ||
3daf74d7 | 3562 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 3563 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 3564 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 3565 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 3566 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 3567 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 3568 | WARN_ON_ONCE(ret); |
b4996a86 | 3569 | dep->resource_index = 0; |
06281d46 | 3570 | |
140ca4cf TN |
3571 | /* |
3572 | * The END_TRANSFER command will cause the controller to generate a | |
3573 | * NoStream Event, and it's not due to the host DP NoStream rejection. | |
3574 | * Ignore the next NoStream event. | |
3575 | */ | |
3576 | if (dep->stream_capable) | |
3577 | dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3578 | ||
d3abda5a TN |
3579 | if (!interrupt) |
3580 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
3581 | else |
3582 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
3583 | } |
3584 | ||
72246da4 FB |
3585 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
3586 | { | |
3587 | u32 epnum; | |
3588 | ||
3589 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3590 | struct dwc3_ep *dep; | |
72246da4 FB |
3591 | int ret; |
3592 | ||
3593 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3594 | if (!dep) |
3595 | continue; | |
72246da4 FB |
3596 | |
3597 | if (!(dep->flags & DWC3_EP_STALL)) | |
3598 | continue; | |
3599 | ||
3600 | dep->flags &= ~DWC3_EP_STALL; | |
3601 | ||
50c763f8 | 3602 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
3603 | WARN_ON_ONCE(ret); |
3604 | } | |
3605 | } | |
3606 | ||
3607 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
3608 | { | |
c4430a26 FB |
3609 | int reg; |
3610 | ||
1b6009ea TN |
3611 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
3612 | ||
72246da4 FB |
3613 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3614 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 3615 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 3616 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 3617 | |
72246da4 FB |
3618 | dwc3_disconnect_gadget(dwc); |
3619 | ||
e81a7018 | 3620 | dwc->gadget->speed = USB_SPEED_UNKNOWN; |
df62df56 | 3621 | dwc->setup_packet_pending = false; |
e81a7018 | 3622 | usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
3623 | |
3624 | dwc->connected = false; | |
72246da4 FB |
3625 | } |
3626 | ||
72246da4 FB |
3627 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
3628 | { | |
3629 | u32 reg; | |
3630 | ||
71ca43f3 WC |
3631 | /* |
3632 | * Ideally, dwc3_reset_gadget() would trigger the function | |
3633 | * drivers to stop any active transfers through ep disable. | |
3634 | * However, for functions which defer ep disable, such as mass | |
3635 | * storage, we will need to rely on the call to stop active | |
3636 | * transfers here, and avoid allowing of request queuing. | |
3637 | */ | |
3638 | dwc->connected = false; | |
3639 | ||
df62df56 FB |
3640 | /* |
3641 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
3642 | * would cause a missing Disconnect Event if there's a | |
3643 | * pending Setup Packet in the FIFO. | |
3644 | * | |
3645 | * There's no suggested workaround on the official Bug | |
3646 | * report, which states that "unless the driver/application | |
3647 | * is doing any special handling of a disconnect event, | |
3648 | * there is no functional issue". | |
3649 | * | |
3650 | * Unfortunately, it turns out that we _do_ some special | |
3651 | * handling of a disconnect event, namely complete all | |
3652 | * pending transfers, notify gadget driver of the | |
3653 | * disconnection, and so on. | |
3654 | * | |
3655 | * Our suggested workaround is to follow the Disconnect | |
3656 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
3657 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
3658 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
3659 | * same endpoint. |
3660 | * | |
3661 | * Refers to: | |
3662 | * | |
3663 | * STAR#9000466709: RTL: Device : Disconnect event not | |
3664 | * generated if setup packet pending in FIFO | |
3665 | */ | |
9af21dd6 | 3666 | if (DWC3_VER_IS_PRIOR(DWC3, 188A)) { |
df62df56 FB |
3667 | if (dwc->setup_packet_pending) |
3668 | dwc3_gadget_disconnect_interrupt(dwc); | |
3669 | } | |
3670 | ||
8e74475b | 3671 | dwc3_reset_gadget(dwc); |
ae7e8610 WC |
3672 | /* |
3673 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
3674 | * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW | |
3675 | * needs to ensure that it sends "a DEPENDXFER command for any active | |
3676 | * transfers." | |
3677 | */ | |
3678 | dwc3_stop_active_transfers(dwc); | |
f09ddcfc | 3679 | dwc->connected = true; |
72246da4 FB |
3680 | |
3681 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3682 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 3683 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 3684 | dwc->test_mode = false; |
72246da4 FB |
3685 | dwc3_clear_stall_all_ep(dwc); |
3686 | ||
3687 | /* Reset device address to zero */ | |
3688 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3689 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
3690 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
3691 | } |
3692 | ||
72246da4 FB |
3693 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
3694 | { | |
72246da4 FB |
3695 | struct dwc3_ep *dep; |
3696 | int ret; | |
3697 | u32 reg; | |
f551037c | 3698 | u8 lanes = 1; |
72246da4 FB |
3699 | u8 speed; |
3700 | ||
72246da4 FB |
3701 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
3702 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
3703 | dwc->speed = speed; | |
3704 | ||
f551037c TN |
3705 | if (DWC3_IP_IS(DWC32)) |
3706 | lanes = DWC3_DSTS_CONNLANES(reg) + 1; | |
3707 | ||
3708 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; | |
3709 | ||
5fb6fdaf JY |
3710 | /* |
3711 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
3712 | * each time on Connect Done. | |
3713 | * | |
3714 | * Currently we always use the reset value. If any platform | |
3715 | * wants to set this to a different value, we need to add a | |
3716 | * setting and update GCTL.RAMCLKSEL here. | |
3717 | */ | |
72246da4 FB |
3718 | |
3719 | switch (speed) { | |
2da9ad76 | 3720 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b | 3721 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3722 | dwc->gadget->ep0->maxpacket = 512; |
3723 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
f551037c TN |
3724 | |
3725 | if (lanes > 1) | |
3726 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x2; | |
3727 | else | |
3728 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x1; | |
7580862b | 3729 | break; |
2da9ad76 | 3730 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
3731 | /* |
3732 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
3733 | * would cause a missing USB3 Reset event. | |
3734 | * | |
3735 | * In such situations, we should force a USB3 Reset | |
3736 | * event by calling our dwc3_gadget_reset_interrupt() | |
3737 | * routine. | |
3738 | * | |
3739 | * Refers to: | |
3740 | * | |
3741 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
3742 | * not be generated always when the link enters poll | |
3743 | */ | |
9af21dd6 | 3744 | if (DWC3_VER_IS_PRIOR(DWC3, 190A)) |
05870c5b FB |
3745 | dwc3_gadget_reset_interrupt(dwc); |
3746 | ||
72246da4 | 3747 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3748 | dwc->gadget->ep0->maxpacket = 512; |
3749 | dwc->gadget->speed = USB_SPEED_SUPER; | |
f551037c TN |
3750 | |
3751 | if (lanes > 1) { | |
3752 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
3753 | dwc->gadget->ssp_rate = USB_SSP_GEN_1x2; | |
3754 | } | |
72246da4 | 3755 | break; |
2da9ad76 | 3756 | case DWC3_DSTS_HIGHSPEED: |
72246da4 | 3757 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3758 | dwc->gadget->ep0->maxpacket = 64; |
3759 | dwc->gadget->speed = USB_SPEED_HIGH; | |
72246da4 | 3760 | break; |
9418ee15 | 3761 | case DWC3_DSTS_FULLSPEED: |
72246da4 | 3762 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3763 | dwc->gadget->ep0->maxpacket = 64; |
3764 | dwc->gadget->speed = USB_SPEED_FULL; | |
72246da4 | 3765 | break; |
72246da4 FB |
3766 | } |
3767 | ||
e81a7018 | 3768 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket; |
61800263 | 3769 | |
2b758350 PA |
3770 | /* Enable USB2 LPM Capability */ |
3771 | ||
9af21dd6 | 3772 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) && |
475e8be5 | 3773 | !dwc->usb2_gadget_lpm_disable && |
2da9ad76 JY |
3774 | (speed != DWC3_DSTS_SUPERSPEED) && |
3775 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
3776 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
3777 | reg |= DWC3_DCFG_LPM_CAP; | |
3778 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3779 | ||
3780 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3781 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
3782 | ||
16fe4f30 TN |
3783 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
3784 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 3785 | |
80caf7d2 HR |
3786 | /* |
3787 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
3788 | * DCFG.LPMCap is set, core responses with an ACK and the | |
3789 | * BESL value in the LPM token is less than or equal to LPM | |
3790 | * NYET threshold. | |
3791 | */ | |
9af21dd6 | 3792 | WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum, |
9165dabb | 3793 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 | 3794 | |
9af21dd6 | 3795 | if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) |
2e487d28 | 3796 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 3797 | |
5b738211 | 3798 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf | 3799 | } else { |
475e8be5 TN |
3800 | if (dwc->usb2_gadget_lpm_disable) { |
3801 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3802 | reg &= ~DWC3_DCFG_LPM_CAP; | |
3803 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3804 | } | |
3805 | ||
356363bf FB |
3806 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3807 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 3808 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
3809 | } |
3810 | ||
72246da4 | 3811 | dep = dwc->eps[0]; |
a2d23f08 | 3812 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3813 | if (ret) { |
3814 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3815 | return; | |
3816 | } | |
3817 | ||
3818 | dep = dwc->eps[1]; | |
a2d23f08 | 3819 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3820 | if (ret) { |
3821 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3822 | return; | |
3823 | } | |
3824 | ||
3825 | /* | |
3826 | * Configure PHY via GUSB3PIPECTLn if required. | |
3827 | * | |
3828 | * Update GTXFIFOSIZn | |
3829 | * | |
3830 | * In both cases reset values should be sufficient. | |
3831 | */ | |
3832 | } | |
3833 | ||
3834 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
3835 | { | |
72246da4 FB |
3836 | /* |
3837 | * TODO take core out of low power mode when that's | |
3838 | * implemented. | |
3839 | */ | |
3840 | ||
40edb522 | 3841 | if (dwc->async_callbacks && dwc->gadget_driver->resume) { |
ad14d4e0 | 3842 | spin_unlock(&dwc->lock); |
e81a7018 | 3843 | dwc->gadget_driver->resume(dwc->gadget); |
ad14d4e0 JL |
3844 | spin_lock(&dwc->lock); |
3845 | } | |
72246da4 FB |
3846 | } |
3847 | ||
3848 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
3849 | unsigned int evtinfo) | |
3850 | { | |
fae2b904 | 3851 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
3852 | unsigned int pwropt; |
3853 | ||
3854 | /* | |
3855 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
3856 | * Hibernation mode enabled which would show up when device detects | |
3857 | * host-initiated U3 exit. | |
3858 | * | |
3859 | * In that case, device will generate a Link State Change Interrupt | |
3860 | * from U3 to RESUME which is only necessary if Hibernation is | |
3861 | * configured in. | |
3862 | * | |
3863 | * There are no functional changes due to such spurious event and we | |
3864 | * just need to ignore it. | |
3865 | * | |
3866 | * Refers to: | |
3867 | * | |
3868 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3869 | * operational mode | |
3870 | */ | |
3871 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
9af21dd6 | 3872 | if (DWC3_VER_IS_PRIOR(DWC3, 250A) && |
0b0cc1cd FB |
3873 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { |
3874 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3875 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3876 | return; |
3877 | } | |
3878 | } | |
fae2b904 FB |
3879 | |
3880 | /* | |
3881 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3882 | * on the link partner, the USB session might do multiple entry/exit | |
3883 | * of low power states before a transfer takes place. | |
3884 | * | |
3885 | * Due to this problem, we might experience lower throughput. The | |
3886 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3887 | * transitioning from U1/U2 to U0 and enable those bits again | |
3888 | * after a transfer completes and there are no pending transfers | |
3889 | * on any of the enabled endpoints. | |
3890 | * | |
3891 | * This is the first half of that workaround. | |
3892 | * | |
3893 | * Refers to: | |
3894 | * | |
3895 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3896 | * core send LGO_Ux entering U0 | |
3897 | */ | |
9af21dd6 | 3898 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3899 | if (next == DWC3_LINK_STATE_U0) { |
3900 | u32 u1u2; | |
3901 | u32 reg; | |
3902 | ||
3903 | switch (dwc->link_state) { | |
3904 | case DWC3_LINK_STATE_U1: | |
3905 | case DWC3_LINK_STATE_U2: | |
3906 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3907 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3908 | | DWC3_DCTL_ACCEPTU2ENA | |
3909 | | DWC3_DCTL_INITU1ENA | |
3910 | | DWC3_DCTL_ACCEPTU1ENA); | |
3911 | ||
3912 | if (!dwc->u1u2) | |
3913 | dwc->u1u2 = reg & u1u2; | |
3914 | ||
3915 | reg &= ~u1u2; | |
3916 | ||
5b738211 | 3917 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3918 | break; |
3919 | default: | |
3920 | /* do nothing */ | |
3921 | break; | |
3922 | } | |
3923 | } | |
3924 | } | |
3925 | ||
bc5ba2e0 FB |
3926 | switch (next) { |
3927 | case DWC3_LINK_STATE_U1: | |
3928 | if (dwc->speed == USB_SPEED_SUPER) | |
3929 | dwc3_suspend_gadget(dwc); | |
3930 | break; | |
3931 | case DWC3_LINK_STATE_U2: | |
3932 | case DWC3_LINK_STATE_U3: | |
3933 | dwc3_suspend_gadget(dwc); | |
3934 | break; | |
3935 | case DWC3_LINK_STATE_RESUME: | |
3936 | dwc3_resume_gadget(dwc); | |
3937 | break; | |
3938 | default: | |
3939 | /* do nothing */ | |
3940 | break; | |
3941 | } | |
3942 | ||
e57ebc1d | 3943 | dwc->link_state = next; |
72246da4 FB |
3944 | } |
3945 | ||
72704f87 BW |
3946 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3947 | unsigned int evtinfo) | |
3948 | { | |
3949 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3950 | ||
3951 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3952 | dwc3_suspend_gadget(dwc); | |
3953 | ||
3954 | dwc->link_state = next; | |
3955 | } | |
3956 | ||
e1dadd3b FB |
3957 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3958 | unsigned int evtinfo) | |
3959 | { | |
3960 | unsigned int is_ss = evtinfo & BIT(4); | |
3961 | ||
bfad65ee | 3962 | /* |
e1dadd3b FB |
3963 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3964 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3965 | * randomly. | |
3966 | * | |
3967 | * Because of this issue, core could generate bogus hibernation | |
3968 | * events which SW needs to ignore. | |
3969 | * | |
3970 | * Refers to: | |
3971 | * | |
3972 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3973 | * Device Fallback from SuperSpeed | |
3974 | */ | |
3975 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3976 | return; | |
3977 | ||
3978 | /* enter hibernation here */ | |
3979 | } | |
3980 | ||
72246da4 FB |
3981 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3982 | const struct dwc3_event_devt *event) | |
3983 | { | |
3984 | switch (event->type) { | |
3985 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3986 | dwc3_gadget_disconnect_interrupt(dwc); | |
3987 | break; | |
3988 | case DWC3_DEVICE_EVENT_RESET: | |
3989 | dwc3_gadget_reset_interrupt(dwc); | |
3990 | break; | |
3991 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3992 | dwc3_gadget_conndone_interrupt(dwc); | |
3993 | break; | |
3994 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3995 | dwc3_gadget_wakeup_interrupt(dwc); | |
3996 | break; | |
e1dadd3b FB |
3997 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3998 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3999 | "unexpected hibernation event\n")) | |
4000 | break; | |
4001 | ||
4002 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
4003 | break; | |
72246da4 FB |
4004 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
4005 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
4006 | break; | |
6f26ebb7 | 4007 | case DWC3_DEVICE_EVENT_SUSPEND: |
72704f87 | 4008 | /* It changed to be suspend event for version 2.30a and above */ |
9af21dd6 | 4009 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) { |
72704f87 BW |
4010 | /* |
4011 | * Ignore suspend event until the gadget enters into | |
4012 | * USB_STATE_CONFIGURED state. | |
4013 | */ | |
e81a7018 | 4014 | if (dwc->gadget->state >= USB_STATE_CONFIGURED) |
72704f87 BW |
4015 | dwc3_gadget_suspend_interrupt(dwc, |
4016 | event->event_info); | |
4017 | } | |
72246da4 FB |
4018 | break; |
4019 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 4020 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 4021 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 4022 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
4023 | break; |
4024 | default: | |
e9f2aa87 | 4025 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
4026 | } |
4027 | } | |
4028 | ||
4029 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
4030 | const union dwc3_event *event) | |
4031 | { | |
43c96be1 | 4032 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 4033 | |
dfc5e805 FB |
4034 | if (!event->type.is_devspec) |
4035 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
4036 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 4037 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 4038 | else |
72246da4 | 4039 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
4040 | } |
4041 | ||
dea520a4 | 4042 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 4043 | { |
dea520a4 | 4044 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 4045 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 4046 | int left; |
e8adfc30 | 4047 | u32 reg; |
b15a762f | 4048 | |
f42f2447 | 4049 | left = evt->count; |
b15a762f | 4050 | |
f42f2447 FB |
4051 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
4052 | return IRQ_NONE; | |
b15a762f | 4053 | |
f42f2447 FB |
4054 | while (left > 0) { |
4055 | union dwc3_event event; | |
b15a762f | 4056 | |
ebbb2d59 | 4057 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 4058 | |
f42f2447 | 4059 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 4060 | |
f42f2447 FB |
4061 | /* |
4062 | * FIXME we wrap around correctly to the next entry as | |
4063 | * almost all entries are 4 bytes in size. There is one | |
4064 | * entry which has 12 bytes which is a regular entry | |
4065 | * followed by 8 bytes data. ATM I don't know how | |
4066 | * things are organized if we get next to the a | |
4067 | * boundary so I worry about that once we try to handle | |
4068 | * that. | |
4069 | */ | |
caefe6c7 | 4070 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 4071 | left -= 4; |
f42f2447 | 4072 | } |
b15a762f | 4073 | |
f42f2447 FB |
4074 | evt->count = 0; |
4075 | evt->flags &= ~DWC3_EVENT_PENDING; | |
4076 | ret = IRQ_HANDLED; | |
b15a762f | 4077 | |
f42f2447 | 4078 | /* Unmask interrupt */ |
660e9bde | 4079 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 4080 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 4081 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 4082 | |
cf40b86b JY |
4083 | if (dwc->imod_interval) { |
4084 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
4085 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
4086 | } | |
4087 | ||
f42f2447 FB |
4088 | return ret; |
4089 | } | |
e8adfc30 | 4090 | |
dea520a4 | 4091 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 4092 | { |
dea520a4 FB |
4093 | struct dwc3_event_buffer *evt = _evt; |
4094 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 4095 | unsigned long flags; |
f42f2447 | 4096 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 4097 | |
e5f68b4a | 4098 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 4099 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 4100 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
4101 | |
4102 | return ret; | |
4103 | } | |
4104 | ||
dea520a4 | 4105 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 4106 | { |
dea520a4 | 4107 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 4108 | u32 amount; |
72246da4 | 4109 | u32 count; |
e8adfc30 | 4110 | u32 reg; |
72246da4 | 4111 | |
fc8bb91b FB |
4112 | if (pm_runtime_suspended(dwc->dev)) { |
4113 | pm_runtime_get(dwc->dev); | |
4114 | disable_irq_nosync(dwc->irq_gadget); | |
4115 | dwc->pending_events = true; | |
4116 | return IRQ_HANDLED; | |
4117 | } | |
4118 | ||
d325a1de TN |
4119 | /* |
4120 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
4121 | * be called again after HW interrupt deassertion. Check if bottom-half | |
4122 | * irq event handler completes before caching new event to prevent | |
4123 | * losing events. | |
4124 | */ | |
4125 | if (evt->flags & DWC3_EVENT_PENDING) | |
4126 | return IRQ_HANDLED; | |
4127 | ||
660e9bde | 4128 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
4129 | count &= DWC3_GEVNTCOUNT_MASK; |
4130 | if (!count) | |
4131 | return IRQ_NONE; | |
4132 | ||
b15a762f FB |
4133 | evt->count = count; |
4134 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 4135 | |
e8adfc30 | 4136 | /* Mask interrupt */ |
660e9bde | 4137 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 4138 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 4139 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 4140 | |
ebbb2d59 JY |
4141 | amount = min(count, evt->length - evt->lpos); |
4142 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
4143 | ||
4144 | if (amount < count) | |
4145 | memcpy(evt->cache, evt->buf, count - amount); | |
4146 | ||
65aca320 JY |
4147 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
4148 | ||
b15a762f | 4149 | return IRQ_WAKE_THREAD; |
72246da4 FB |
4150 | } |
4151 | ||
dea520a4 | 4152 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 4153 | { |
dea520a4 | 4154 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 4155 | |
dea520a4 | 4156 | return dwc3_check_event_buf(evt); |
72246da4 FB |
4157 | } |
4158 | ||
6db3812e FB |
4159 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
4160 | { | |
4161 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
4162 | int irq; | |
4163 | ||
f146b40b | 4164 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
4165 | if (irq > 0) |
4166 | goto out; | |
4167 | ||
4168 | if (irq == -EPROBE_DEFER) | |
4169 | goto out; | |
4170 | ||
f146b40b | 4171 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
4172 | if (irq > 0) |
4173 | goto out; | |
4174 | ||
4175 | if (irq == -EPROBE_DEFER) | |
4176 | goto out; | |
4177 | ||
4178 | irq = platform_get_irq(dwc3_pdev, 0); | |
4179 | if (irq > 0) | |
4180 | goto out; | |
4181 | ||
6db3812e FB |
4182 | if (!irq) |
4183 | irq = -EINVAL; | |
4184 | ||
4185 | out: | |
4186 | return irq; | |
4187 | } | |
4188 | ||
e81a7018 PC |
4189 | static void dwc_gadget_release(struct device *dev) |
4190 | { | |
4191 | struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev); | |
4192 | ||
4193 | kfree(gadget); | |
4194 | } | |
4195 | ||
72246da4 | 4196 | /** |
bfad65ee | 4197 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 4198 | * @dwc: pointer to our controller context structure |
72246da4 FB |
4199 | * |
4200 | * Returns 0 on success otherwise negative errno. | |
4201 | */ | |
41ac7b3a | 4202 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 4203 | { |
6db3812e FB |
4204 | int ret; |
4205 | int irq; | |
e81a7018 | 4206 | struct device *dev; |
9522def4 | 4207 | |
6db3812e FB |
4208 | irq = dwc3_gadget_get_irq(dwc); |
4209 | if (irq < 0) { | |
4210 | ret = irq; | |
4211 | goto err0; | |
9522def4 RQ |
4212 | } |
4213 | ||
4214 | dwc->irq_gadget = irq; | |
72246da4 | 4215 | |
d64ff406 AB |
4216 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
4217 | sizeof(*dwc->ep0_trb) * 2, | |
4218 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
4219 | if (!dwc->ep0_trb) { |
4220 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
4221 | ret = -ENOMEM; | |
7d5e650a | 4222 | goto err0; |
72246da4 FB |
4223 | } |
4224 | ||
4199c5f8 | 4225 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 4226 | if (!dwc->setup_buf) { |
72246da4 | 4227 | ret = -ENOMEM; |
7d5e650a | 4228 | goto err1; |
72246da4 FB |
4229 | } |
4230 | ||
905dc04e FB |
4231 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
4232 | &dwc->bounce_addr, GFP_KERNEL); | |
4233 | if (!dwc->bounce) { | |
4234 | ret = -ENOMEM; | |
d6e5a549 | 4235 | goto err2; |
905dc04e FB |
4236 | } |
4237 | ||
bb014736 | 4238 | init_completion(&dwc->ep0_in_setup); |
e81a7018 PC |
4239 | dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL); |
4240 | if (!dwc->gadget) { | |
4241 | ret = -ENOMEM; | |
4242 | goto err3; | |
4243 | } | |
bb014736 | 4244 | |
e81a7018 | 4245 | |
268bbde7 | 4246 | usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release); |
e81a7018 PC |
4247 | dev = &dwc->gadget->dev; |
4248 | dev->platform_data = dwc; | |
4249 | dwc->gadget->ops = &dwc3_gadget_ops; | |
4250 | dwc->gadget->speed = USB_SPEED_UNKNOWN; | |
f551037c | 4251 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; |
e81a7018 PC |
4252 | dwc->gadget->sg_supported = true; |
4253 | dwc->gadget->name = "dwc3-gadget"; | |
475e8be5 | 4254 | dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable; |
72246da4 | 4255 | |
b9e51b2b BM |
4256 | /* |
4257 | * FIXME We might be setting max_speed to <SUPER, however versions | |
4258 | * <2.20a of dwc3 have an issue with metastability (documented | |
4259 | * elsewhere in this driver) which tells us we can't set max speed to | |
4260 | * anything lower than SUPER. | |
4261 | * | |
4262 | * Because gadget.max_speed is only used by composite.c and function | |
4263 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
4264 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
4265 | * together with our BOS descriptor as that could confuse host into | |
4266 | * thinking we can handle super speed. | |
4267 | * | |
4268 | * Note that, in fact, we won't even support GetBOS requests when speed | |
4269 | * is less than super speed because we don't have means, yet, to tell | |
4270 | * composite.c that we are USB 2.0 + LPM ECN. | |
4271 | */ | |
9af21dd6 | 4272 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && |
42bf02ec | 4273 | !dwc->dis_metastability_quirk) |
5eb30ced | 4274 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
4275 | dwc->revision); |
4276 | ||
e81a7018 | 4277 | dwc->gadget->max_speed = dwc->maximum_speed; |
67848146 | 4278 | dwc->gadget->max_ssp_rate = dwc->max_ssp_rate; |
b9e51b2b | 4279 | |
72246da4 FB |
4280 | /* |
4281 | * REVISIT: Here we should clear all pending IRQs to be | |
4282 | * sure we're starting from a well known location. | |
4283 | */ | |
4284 | ||
f3bcfc7e | 4285 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 4286 | if (ret) |
e81a7018 | 4287 | goto err4; |
72246da4 | 4288 | |
e81a7018 | 4289 | ret = usb_add_gadget(dwc->gadget); |
72246da4 | 4290 | if (ret) { |
e81a7018 PC |
4291 | dev_err(dwc->dev, "failed to add gadget\n"); |
4292 | goto err5; | |
72246da4 FB |
4293 | } |
4294 | ||
072cab8a TN |
4295 | if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS) |
4296 | dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate); | |
4297 | else | |
4298 | dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed); | |
169e3b68 | 4299 | |
72246da4 FB |
4300 | return 0; |
4301 | ||
e81a7018 | 4302 | err5: |
d6e5a549 | 4303 | dwc3_gadget_free_endpoints(dwc); |
e81a7018 PC |
4304 | err4: |
4305 | usb_put_gadget(dwc->gadget); | |
03715ea2 | 4306 | dwc->gadget = NULL; |
7d5e650a | 4307 | err3: |
d6e5a549 FB |
4308 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
4309 | dwc->bounce_addr); | |
5812b1c2 | 4310 | |
7d5e650a | 4311 | err2: |
0fc9a1be | 4312 | kfree(dwc->setup_buf); |
72246da4 | 4313 | |
7d5e650a | 4314 | err1: |
d64ff406 | 4315 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
4316 | dwc->ep0_trb, dwc->ep0_trb_addr); |
4317 | ||
72246da4 FB |
4318 | err0: |
4319 | return ret; | |
4320 | } | |
4321 | ||
7415f17c FB |
4322 | /* -------------------------------------------------------------------------- */ |
4323 | ||
72246da4 FB |
4324 | void dwc3_gadget_exit(struct dwc3 *dwc) |
4325 | { | |
03715ea2 JP |
4326 | if (!dwc->gadget) |
4327 | return; | |
4328 | ||
bb9c74a5 | 4329 | usb_del_gadget(dwc->gadget); |
72246da4 | 4330 | dwc3_gadget_free_endpoints(dwc); |
bb9c74a5 | 4331 | usb_put_gadget(dwc->gadget); |
905dc04e | 4332 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 4333 | dwc->bounce_addr); |
0fc9a1be | 4334 | kfree(dwc->setup_buf); |
d64ff406 | 4335 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 4336 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 4337 | } |
7415f17c | 4338 | |
0b0231aa | 4339 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 4340 | { |
9772b47a RQ |
4341 | if (!dwc->gadget_driver) |
4342 | return 0; | |
4343 | ||
1551e35e | 4344 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
4345 | dwc3_disconnect_gadget(dwc); |
4346 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
4347 | |
4348 | return 0; | |
4349 | } | |
4350 | ||
4351 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
4352 | { | |
7415f17c FB |
4353 | int ret; |
4354 | ||
9772b47a RQ |
4355 | if (!dwc->gadget_driver) |
4356 | return 0; | |
4357 | ||
9f8a67b6 FB |
4358 | ret = __dwc3_gadget_start(dwc); |
4359 | if (ret < 0) | |
7415f17c FB |
4360 | goto err0; |
4361 | ||
9f8a67b6 FB |
4362 | ret = dwc3_gadget_run_stop(dwc, true, false); |
4363 | if (ret < 0) | |
7415f17c FB |
4364 | goto err1; |
4365 | ||
7415f17c FB |
4366 | return 0; |
4367 | ||
4368 | err1: | |
9f8a67b6 | 4369 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
4370 | |
4371 | err0: | |
4372 | return ret; | |
4373 | } | |
fc8bb91b FB |
4374 | |
4375 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
4376 | { | |
4377 | if (dwc->pending_events) { | |
4378 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
4379 | dwc->pending_events = false; | |
4380 | enable_irq(dwc->irq_gadget); | |
4381 | } | |
4382 | } |