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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
49 | case TEST_J: | |
50 | case TEST_K: | |
51 | case TEST_SE0_NAK: | |
52 | case TEST_PACKET: | |
53 | case TEST_FORCE_EN: | |
54 | reg |= mode << 1; | |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
60 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
98 | if (dwc->revision >= DWC3_REVISION_194A) { | |
99 | while (--retries) { | |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
114 | /* set requested state */ | |
115 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
116 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
117 | ||
802fde98 PZ |
118 | /* |
119 | * The following code is racy when called from dwc3_gadget_wakeup, | |
120 | * and is not needed, at least on newer versions | |
121 | */ | |
122 | if (dwc->revision >= DWC3_REVISION_194A) | |
123 | return 0; | |
124 | ||
8598bde7 | 125 | /* wait for a change in DSTS */ |
aed430e5 | 126 | retries = 10000; |
8598bde7 FB |
127 | while (--retries) { |
128 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
129 | ||
8598bde7 FB |
130 | if (DWC3_DSTS_USBLNKST(reg) == state) |
131 | return 0; | |
132 | ||
aee63e3c | 133 | udelay(5); |
8598bde7 FB |
134 | } |
135 | ||
8598bde7 FB |
136 | return -ETIMEDOUT; |
137 | } | |
138 | ||
dca0119c | 139 | /** |
bfad65ee FB |
140 | * dwc3_ep_inc_trb - increment a trb index. |
141 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
142 | * |
143 | * The index should never point to the link TRB. After incrementing, | |
144 | * if it is point to the link TRB, wrap around to the beginning. The | |
145 | * link TRB is always at the last TRB entry. | |
146 | */ | |
147 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 148 | { |
dca0119c JY |
149 | (*index)++; |
150 | if (*index == (DWC3_TRB_NUM - 1)) | |
151 | *index = 0; | |
ef966b9d | 152 | } |
457e84b6 | 153 | |
bfad65ee FB |
154 | /** |
155 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
156 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
157 | */ | |
dca0119c | 158 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 159 | { |
dca0119c | 160 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 161 | } |
457e84b6 | 162 | |
bfad65ee FB |
163 | /** |
164 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
165 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
166 | */ | |
dca0119c | 167 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 168 | { |
dca0119c | 169 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
170 | } |
171 | ||
69102510 | 172 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 173 | struct dwc3_request *req, int status) |
72246da4 FB |
174 | { |
175 | struct dwc3 *dwc = dep->dwc; | |
176 | ||
737f1ae2 | 177 | req->started = false; |
72246da4 | 178 | list_del(&req->list); |
e62c5bc5 | 179 | req->remaining = 0; |
bd674224 | 180 | req->needs_extra_trb = false; |
72246da4 FB |
181 | |
182 | if (req->request.status == -EINPROGRESS) | |
183 | req->request.status = status; | |
184 | ||
4a71fcb8 JP |
185 | if (req->trb) |
186 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 187 | &req->request, req->direction); |
4a71fcb8 JP |
188 | |
189 | req->trb = NULL; | |
2c4cbe6e | 190 | trace_dwc3_gadget_giveback(req); |
72246da4 | 191 | |
c91815b5 FB |
192 | if (dep->number > 1) |
193 | pm_runtime_put(dwc->dev); | |
194 | } | |
195 | ||
196 | /** | |
197 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
198 | * @dep: The endpoint to whom the request belongs to | |
199 | * @req: The request we're giving back | |
200 | * @status: completion code for the request | |
201 | * | |
202 | * Must be called with controller's lock held and interrupts disabled. This | |
203 | * function will unmap @req and call its ->complete() callback to notify upper | |
204 | * layers that it has completed. | |
205 | */ | |
206 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
207 | int status) | |
208 | { | |
209 | struct dwc3 *dwc = dep->dwc; | |
210 | ||
211 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
212 | ||
72246da4 | 213 | spin_unlock(&dwc->lock); |
304f7e5e | 214 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
215 | spin_lock(&dwc->lock); |
216 | } | |
217 | ||
bfad65ee FB |
218 | /** |
219 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
220 | * @dwc: pointer to the controller context | |
221 | * @cmd: the command to be issued | |
222 | * @param: command parameter | |
223 | * | |
224 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
225 | * and wait for its completion. | |
226 | */ | |
3ece0ec4 | 227 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
228 | { |
229 | u32 timeout = 500; | |
71f7e702 | 230 | int status = 0; |
0fe886cd | 231 | int ret = 0; |
b09bb642 FB |
232 | u32 reg; |
233 | ||
234 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
235 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
236 | ||
237 | do { | |
238 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
239 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
240 | status = DWC3_DGCMD_STATUS(reg); |
241 | if (status) | |
0fe886cd FB |
242 | ret = -EINVAL; |
243 | break; | |
b09bb642 | 244 | } |
e3aee486 | 245 | } while (--timeout); |
0fe886cd FB |
246 | |
247 | if (!timeout) { | |
0fe886cd | 248 | ret = -ETIMEDOUT; |
71f7e702 | 249 | status = -ETIMEDOUT; |
0fe886cd FB |
250 | } |
251 | ||
71f7e702 FB |
252 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
253 | ||
0fe886cd | 254 | return ret; |
b09bb642 FB |
255 | } |
256 | ||
c36d8e94 FB |
257 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
258 | ||
bfad65ee FB |
259 | /** |
260 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
261 | * @dep: the endpoint to which the command is going to be issued | |
262 | * @cmd: the command to be issued | |
263 | * @params: parameters to the command | |
264 | * | |
265 | * Caller should handle locking. This function will issue @cmd with given | |
266 | * @params to @dep and wait for its completion. | |
267 | */ | |
2cd4718d FB |
268 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
269 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 270 | { |
8897a761 | 271 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 272 | struct dwc3 *dwc = dep->dwc; |
8722e095 | 273 | u32 timeout = 1000; |
87dd9611 | 274 | u32 saved_config = 0; |
72246da4 FB |
275 | u32 reg; |
276 | ||
0933df15 | 277 | int cmd_status = 0; |
c0ca324d | 278 | int ret = -EINVAL; |
72246da4 | 279 | |
2b0f11df | 280 | /* |
87dd9611 TN |
281 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
282 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
283 | * endpoint command. | |
2b0f11df | 284 | * |
87dd9611 TN |
285 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
286 | * settings. Restore them after the command is completed. | |
287 | * | |
288 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 289 | */ |
ab2a92e7 FB |
290 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
291 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
292 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 293 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 294 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 295 | } |
87dd9611 TN |
296 | |
297 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
298 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
299 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
300 | } | |
301 | ||
302 | if (saved_config) | |
303 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
304 | } |
305 | ||
5999914f | 306 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
307 | int needs_wakeup; |
308 | ||
309 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
310 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
311 | dwc->link_state == DWC3_LINK_STATE_U3); | |
312 | ||
313 | if (unlikely(needs_wakeup)) { | |
314 | ret = __dwc3_gadget_wakeup(dwc); | |
315 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
316 | ret); | |
317 | } | |
318 | } | |
319 | ||
2eb88016 FB |
320 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
321 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
322 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 323 | |
8897a761 FB |
324 | /* |
325 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
326 | * not relying on XferNotReady, we can make use of a special "No | |
327 | * Response Update Transfer" command where we should clear both CmdAct | |
328 | * and CmdIOC bits. | |
329 | * | |
330 | * With this, we don't need to wait for command completion and can | |
331 | * straight away issue further commands to the endpoint. | |
332 | * | |
333 | * NOTICE: We're making an assumption that control endpoints will never | |
334 | * make use of Update Transfer command. This is a safe assumption | |
335 | * because we can never have more than one request at a time with | |
336 | * Control Endpoints. If anybody changes that assumption, this chunk | |
337 | * needs to be updated accordingly. | |
338 | */ | |
339 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
340 | !usb_endpoint_xfer_isoc(desc)) | |
341 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
342 | else | |
343 | cmd |= DWC3_DEPCMD_CMDACT; | |
344 | ||
345 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 346 | do { |
2eb88016 | 347 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 348 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 349 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 350 | |
7b9cc7a2 KL |
351 | switch (cmd_status) { |
352 | case 0: | |
353 | ret = 0; | |
354 | break; | |
355 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
7b9cc7a2 | 356 | ret = -EINVAL; |
c0ca324d | 357 | break; |
7b9cc7a2 KL |
358 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
359 | /* | |
360 | * SW issues START TRANSFER command to | |
361 | * isochronous ep with future frame interval. If | |
362 | * future interval time has already passed when | |
363 | * core receives the command, it will respond | |
364 | * with an error status of 'Bus Expiry'. | |
365 | * | |
366 | * Instead of always returning -EINVAL, let's | |
367 | * give a hint to the gadget driver that this is | |
368 | * the case by returning -EAGAIN. | |
369 | */ | |
7b9cc7a2 KL |
370 | ret = -EAGAIN; |
371 | break; | |
372 | default: | |
373 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
374 | } | |
375 | ||
c0ca324d | 376 | break; |
72246da4 | 377 | } |
f6bb225b | 378 | } while (--timeout); |
72246da4 | 379 | |
f6bb225b | 380 | if (timeout == 0) { |
f6bb225b | 381 | ret = -ETIMEDOUT; |
0933df15 | 382 | cmd_status = -ETIMEDOUT; |
f6bb225b | 383 | } |
c0ca324d | 384 | |
0933df15 FB |
385 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
386 | ||
6cb2e4e3 FB |
387 | if (ret == 0) { |
388 | switch (DWC3_DEPCMD_CMD(cmd)) { | |
389 | case DWC3_DEPCMD_STARTTRANSFER: | |
390 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
d7ca7e18 | 391 | dwc3_gadget_ep_get_transfer_index(dep); |
6cb2e4e3 FB |
392 | break; |
393 | case DWC3_DEPCMD_ENDTRANSFER: | |
394 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
395 | break; | |
396 | default: | |
397 | /* nothing */ | |
398 | break; | |
399 | } | |
400 | } | |
401 | ||
87dd9611 | 402 | if (saved_config) { |
2b0f11df | 403 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 404 | reg |= saved_config; |
2b0f11df FB |
405 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
406 | } | |
407 | ||
c0ca324d | 408 | return ret; |
72246da4 FB |
409 | } |
410 | ||
50c763f8 JY |
411 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
412 | { | |
413 | struct dwc3 *dwc = dep->dwc; | |
414 | struct dwc3_gadget_ep_cmd_params params; | |
415 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
416 | ||
417 | /* | |
418 | * As of core revision 2.60a the recommended programming model | |
419 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
420 | * command for IN endpoints. This is to prevent an issue where | |
421 | * some (non-compliant) hosts may not send ACK TPs for pending | |
422 | * IN transfers due to a mishandled error condition. Synopsys | |
423 | * STAR 9000614252. | |
424 | */ | |
5e6c88d2 LB |
425 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
426 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
427 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
428 | ||
429 | memset(¶ms, 0, sizeof(params)); | |
430 | ||
2cd4718d | 431 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
432 | } |
433 | ||
72246da4 | 434 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 435 | struct dwc3_trb *trb) |
72246da4 | 436 | { |
c439ef87 | 437 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
438 | |
439 | return dep->trb_pool_dma + offset; | |
440 | } | |
441 | ||
442 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
443 | { | |
444 | struct dwc3 *dwc = dep->dwc; | |
445 | ||
446 | if (dep->trb_pool) | |
447 | return 0; | |
448 | ||
d64ff406 | 449 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
450 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
451 | &dep->trb_pool_dma, GFP_KERNEL); | |
452 | if (!dep->trb_pool) { | |
453 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
454 | dep->name); | |
455 | return -ENOMEM; | |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
462 | { | |
463 | struct dwc3 *dwc = dep->dwc; | |
464 | ||
d64ff406 | 465 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
466 | dep->trb_pool, dep->trb_pool_dma); |
467 | ||
468 | dep->trb_pool = NULL; | |
469 | dep->trb_pool_dma = 0; | |
470 | } | |
471 | ||
20d1d43f FB |
472 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
473 | { | |
474 | struct dwc3_gadget_ep_cmd_params params; | |
475 | ||
476 | memset(¶ms, 0x00, sizeof(params)); | |
477 | ||
478 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
479 | ||
480 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
481 | ¶ms); | |
482 | } | |
c4509601 JY |
483 | |
484 | /** | |
bfad65ee | 485 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
486 | * @dep: endpoint that is being enabled |
487 | * | |
bfad65ee FB |
488 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
489 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 490 | * |
bfad65ee FB |
491 | * The assignment of transfer resources cannot perfectly follow the data book |
492 | * due to the fact that the controller driver does not have all knowledge of the | |
493 | * configuration in advance. It is given this information piecemeal by the | |
494 | * composite gadget framework after every SET_CONFIGURATION and | |
495 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
496 | * scenario can cause errors. For two reasons: | |
c4509601 | 497 | * |
bfad65ee FB |
498 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
499 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
500 | * incorrect in the scenario of multiple interfaces. | |
501 | * | |
502 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
503 | * endpoint on alt setting (8.1.6). |
504 | * | |
505 | * The following simplified method is used instead: | |
506 | * | |
bfad65ee FB |
507 | * All hardware endpoints can be assigned a transfer resource and this setting |
508 | * will stay persistent until either a core reset or hibernation. So whenever we | |
509 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
510 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
511 | * guaranteed that there are as many transfer resources as endpoints. |
512 | * | |
bfad65ee FB |
513 | * This function is called for each endpoint when it is being enabled but is |
514 | * triggered only when called for EP0-out, which always happens first, and which | |
515 | * should only happen in one of the above conditions. | |
c4509601 | 516 | */ |
b07c2db8 | 517 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
518 | { |
519 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 520 | struct dwc3 *dwc; |
72246da4 | 521 | u32 cmd; |
c4509601 JY |
522 | int i; |
523 | int ret; | |
524 | ||
525 | if (dep->number) | |
526 | return 0; | |
72246da4 FB |
527 | |
528 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 529 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 530 | dwc = dep->dwc; |
72246da4 | 531 | |
2cd4718d | 532 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
533 | if (ret) |
534 | return ret; | |
535 | ||
536 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
537 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 538 | |
c4509601 JY |
539 | if (!dep) |
540 | continue; | |
541 | ||
b07c2db8 | 542 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
543 | if (ret) |
544 | return ret; | |
72246da4 FB |
545 | } |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
b07c2db8 | 550 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 551 | { |
39ebb05c JY |
552 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
553 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 554 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 555 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 556 | |
39ebb05c JY |
557 | comp_desc = dep->endpoint.comp_desc; |
558 | desc = dep->endpoint.desc; | |
559 | ||
72246da4 FB |
560 | memset(¶ms, 0x00, sizeof(params)); |
561 | ||
dc1c70a7 | 562 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
563 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
564 | ||
565 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 566 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 567 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 568 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 569 | } |
72246da4 | 570 | |
a2d23f08 FB |
571 | params.param0 |= action; |
572 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 573 | params.param2 |= dep->saved_state; |
265b70a7 | 574 | |
4bc48c97 FB |
575 | if (usb_endpoint_xfer_control(desc)) |
576 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
577 | |
578 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
579 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 580 | |
18b7ede5 | 581 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
582 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
583 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
584 | dep->stream_capable = true; |
585 | } | |
586 | ||
0b93a4c8 | 587 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 588 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
589 | |
590 | /* | |
591 | * We are doing 1:1 mapping for endpoints, meaning | |
592 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
593 | * so on. We consider the direction bit as part of the physical | |
594 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
595 | */ | |
dc1c70a7 | 596 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
597 | |
598 | /* | |
599 | * We must use the lower 16 TX FIFOs even though | |
600 | * HW might have more | |
601 | */ | |
602 | if (dep->direction) | |
dc1c70a7 | 603 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
604 | |
605 | if (desc->bInterval) { | |
dc1c70a7 | 606 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
607 | dep->interval = 1 << (desc->bInterval - 1); |
608 | } | |
609 | ||
2cd4718d | 610 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
611 | } |
612 | ||
72246da4 | 613 | /** |
bfad65ee | 614 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 615 | * @dep: endpoint to be initialized |
a2d23f08 | 616 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 617 | * |
bfad65ee FB |
618 | * Caller should take care of locking. Execute all necessary commands to |
619 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 620 | */ |
a2d23f08 | 621 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 622 | { |
39ebb05c | 623 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 624 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 625 | |
72246da4 | 626 | u32 reg; |
b09e99ee | 627 | int ret; |
72246da4 FB |
628 | |
629 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
b07c2db8 | 630 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
631 | if (ret) |
632 | return ret; | |
633 | } | |
634 | ||
b07c2db8 | 635 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
636 | if (ret) |
637 | return ret; | |
638 | ||
639 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
640 | struct dwc3_trb *trb_st_hw; |
641 | struct dwc3_trb *trb_link; | |
72246da4 | 642 | |
72246da4 FB |
643 | dep->type = usb_endpoint_type(desc); |
644 | dep->flags |= DWC3_EP_ENABLED; | |
76a638f8 | 645 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
646 | |
647 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
648 | reg |= DWC3_DALEPENA_EP(dep->number); | |
649 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
650 | ||
36b68aae | 651 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 652 | goto out; |
72246da4 | 653 | |
0d25744a JY |
654 | /* Initialize the TRB ring */ |
655 | dep->trb_dequeue = 0; | |
656 | dep->trb_enqueue = 0; | |
657 | memset(dep->trb_pool, 0, | |
658 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
659 | ||
36b68aae | 660 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
661 | trb_st_hw = &dep->trb_pool[0]; |
662 | ||
f6bafc6a | 663 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
664 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
665 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
666 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
667 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
668 | } |
669 | ||
a97ea994 FB |
670 | /* |
671 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
672 | * Response Update Transfer command. | |
673 | */ | |
26d62b4d | 674 | if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) || |
52fcc0be | 675 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
676 | struct dwc3_gadget_ep_cmd_params params; |
677 | struct dwc3_trb *trb; | |
678 | dma_addr_t trb_dma; | |
679 | u32 cmd; | |
680 | ||
681 | memset(¶ms, 0, sizeof(params)); | |
682 | trb = &dep->trb_pool[0]; | |
683 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
684 | ||
685 | params.param0 = upper_32_bits(trb_dma); | |
686 | params.param1 = lower_32_bits(trb_dma); | |
687 | ||
688 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
689 | ||
690 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
691 | if (ret < 0) | |
692 | return ret; | |
a97ea994 FB |
693 | } |
694 | ||
2870e501 FB |
695 | out: |
696 | trace_dwc3_gadget_ep_enable(dep); | |
697 | ||
72246da4 FB |
698 | return 0; |
699 | } | |
700 | ||
8f608e8a | 701 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force); |
624407f9 | 702 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
703 | { |
704 | struct dwc3_request *req; | |
705 | ||
8f608e8a | 706 | dwc3_stop_active_transfer(dep, true); |
624407f9 | 707 | |
0e146028 FB |
708 | /* - giveback all requests to gadget driver */ |
709 | while (!list_empty(&dep->started_list)) { | |
710 | req = next_request(&dep->started_list); | |
1591633e | 711 | |
0e146028 | 712 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
713 | } |
714 | ||
aa3342c8 FB |
715 | while (!list_empty(&dep->pending_list)) { |
716 | req = next_request(&dep->pending_list); | |
72246da4 | 717 | |
624407f9 | 718 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 719 | } |
72246da4 FB |
720 | } |
721 | ||
722 | /** | |
bfad65ee | 723 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
724 | * @dep: the endpoint to disable |
725 | * | |
bfad65ee FB |
726 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
727 | * requests which are currently being processed by the hardware and those which | |
728 | * are not yet scheduled. | |
729 | * | |
624407f9 | 730 | * Caller should take care of locking. |
72246da4 | 731 | */ |
72246da4 FB |
732 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
733 | { | |
734 | struct dwc3 *dwc = dep->dwc; | |
735 | u32 reg; | |
736 | ||
2870e501 | 737 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 738 | |
624407f9 | 739 | dwc3_remove_requests(dwc, dep); |
72246da4 | 740 | |
687ef981 FB |
741 | /* make sure HW endpoint isn't stalled */ |
742 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 743 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 744 | |
72246da4 FB |
745 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
746 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
747 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
748 | ||
879631aa | 749 | dep->stream_capable = false; |
72246da4 | 750 | dep->type = 0; |
76a638f8 | 751 | dep->flags &= DWC3_EP_END_TRANSFER_PENDING; |
72246da4 | 752 | |
39ebb05c JY |
753 | /* Clear out the ep descriptors for non-ep0 */ |
754 | if (dep->number > 1) { | |
755 | dep->endpoint.comp_desc = NULL; | |
756 | dep->endpoint.desc = NULL; | |
757 | } | |
758 | ||
72246da4 FB |
759 | return 0; |
760 | } | |
761 | ||
762 | /* -------------------------------------------------------------------------- */ | |
763 | ||
764 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
765 | const struct usb_endpoint_descriptor *desc) | |
766 | { | |
767 | return -EINVAL; | |
768 | } | |
769 | ||
770 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
771 | { | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | /* -------------------------------------------------------------------------- */ | |
776 | ||
777 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
778 | const struct usb_endpoint_descriptor *desc) | |
779 | { | |
780 | struct dwc3_ep *dep; | |
781 | struct dwc3 *dwc; | |
782 | unsigned long flags; | |
783 | int ret; | |
784 | ||
785 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
786 | pr_debug("dwc3: invalid parameters\n"); | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
790 | if (!desc->wMaxPacketSize) { | |
791 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
792 | return -EINVAL; | |
793 | } | |
794 | ||
795 | dep = to_dwc3_ep(ep); | |
796 | dwc = dep->dwc; | |
797 | ||
95ca961c FB |
798 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
799 | "%s is already enabled\n", | |
800 | dep->name)) | |
c6f83f38 | 801 | return 0; |
c6f83f38 | 802 | |
72246da4 | 803 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 804 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
805 | spin_unlock_irqrestore(&dwc->lock, flags); |
806 | ||
807 | return ret; | |
808 | } | |
809 | ||
810 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
811 | { | |
812 | struct dwc3_ep *dep; | |
813 | struct dwc3 *dwc; | |
814 | unsigned long flags; | |
815 | int ret; | |
816 | ||
817 | if (!ep) { | |
818 | pr_debug("dwc3: invalid parameters\n"); | |
819 | return -EINVAL; | |
820 | } | |
821 | ||
822 | dep = to_dwc3_ep(ep); | |
823 | dwc = dep->dwc; | |
824 | ||
95ca961c FB |
825 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
826 | "%s is already disabled\n", | |
827 | dep->name)) | |
72246da4 | 828 | return 0; |
72246da4 | 829 | |
72246da4 FB |
830 | spin_lock_irqsave(&dwc->lock, flags); |
831 | ret = __dwc3_gadget_ep_disable(dep); | |
832 | spin_unlock_irqrestore(&dwc->lock, flags); | |
833 | ||
834 | return ret; | |
835 | } | |
836 | ||
837 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 838 | gfp_t gfp_flags) |
72246da4 FB |
839 | { |
840 | struct dwc3_request *req; | |
841 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
842 | |
843 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 844 | if (!req) |
72246da4 | 845 | return NULL; |
72246da4 | 846 | |
31a2f5a7 | 847 | req->direction = dep->direction; |
72246da4 FB |
848 | req->epnum = dep->number; |
849 | req->dep = dep; | |
72246da4 | 850 | |
2c4cbe6e FB |
851 | trace_dwc3_alloc_request(req); |
852 | ||
72246da4 FB |
853 | return &req->request; |
854 | } | |
855 | ||
856 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
857 | struct usb_request *request) | |
858 | { | |
859 | struct dwc3_request *req = to_dwc3_request(request); | |
860 | ||
2c4cbe6e | 861 | trace_dwc3_free_request(req); |
72246da4 FB |
862 | kfree(req); |
863 | } | |
864 | ||
42626919 FB |
865 | /** |
866 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
867 | * @dep: The endpoint with the TRB ring | |
868 | * @index: The index of the current TRB in the ring | |
869 | * | |
870 | * Returns the TRB prior to the one pointed to by the index. If the | |
871 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
872 | * the one just before that. | |
873 | */ | |
874 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
875 | { | |
876 | u8 tmp = index; | |
877 | ||
878 | if (!tmp) | |
879 | tmp = DWC3_TRB_NUM - 1; | |
880 | ||
881 | return &dep->trb_pool[tmp - 1]; | |
882 | } | |
883 | ||
884 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
885 | { | |
886 | struct dwc3_trb *tmp; | |
887 | u8 trbs_left; | |
888 | ||
889 | /* | |
890 | * If enqueue & dequeue are equal than it is either full or empty. | |
891 | * | |
892 | * One way to know for sure is if the TRB right before us has HWO bit | |
893 | * set or not. If it has, then we're definitely full and can't fit any | |
894 | * more transfers in our ring. | |
895 | */ | |
896 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
897 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
898 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
899 | return 0; | |
900 | ||
901 | return DWC3_TRB_NUM - 1; | |
902 | } | |
903 | ||
904 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
905 | trbs_left &= (DWC3_TRB_NUM - 1); | |
906 | ||
907 | if (dep->trb_dequeue < dep->trb_enqueue) | |
908 | trbs_left--; | |
909 | ||
910 | return trbs_left; | |
911 | } | |
2c78c029 | 912 | |
e49d3cf4 FB |
913 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
914 | dma_addr_t dma, unsigned length, unsigned chain, unsigned node, | |
915 | unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt) | |
c71fc37c | 916 | { |
6b9018d4 FB |
917 | struct dwc3 *dwc = dep->dwc; |
918 | struct usb_gadget *gadget = &dwc->gadget; | |
919 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 920 | |
f6bafc6a FB |
921 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
922 | trb->bpl = lower_32_bits(dma); | |
923 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 924 | |
16e78db7 | 925 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 926 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 927 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
928 | break; |
929 | ||
930 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 931 | if (!node) { |
e5ba5ec8 | 932 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 933 | |
40d829fb MG |
934 | /* |
935 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
936 | * there is only a single transaction in the microframe, | |
937 | * only a DATA0 data packet PID is used. If there are | |
938 | * two transactions per microframe, DATA1 is used for | |
939 | * the first transaction data packet and DATA0 is used | |
940 | * for the second transaction data packet. If there are | |
941 | * three transactions per microframe, DATA2 is used for | |
942 | * the first transaction data packet, DATA1 is used for | |
943 | * the second, and DATA0 is used for the third." | |
944 | * | |
945 | * IOW, we should satisfy the following cases: | |
946 | * | |
947 | * 1) length <= maxpacket | |
948 | * - DATA0 | |
949 | * | |
950 | * 2) maxpacket < length <= (2 * maxpacket) | |
951 | * - DATA1, DATA0 | |
952 | * | |
953 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
954 | * - DATA2, DATA1, DATA0 | |
955 | */ | |
6b9018d4 FB |
956 | if (speed == USB_SPEED_HIGH) { |
957 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 958 | unsigned int mult = 2; |
40d829fb MG |
959 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
960 | ||
961 | if (length <= (2 * maxp)) | |
962 | mult--; | |
963 | ||
964 | if (length <= maxp) | |
965 | mult--; | |
966 | ||
967 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
968 | } |
969 | } else { | |
e5ba5ec8 | 970 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 971 | } |
ca4d44ea FB |
972 | |
973 | /* always enable Interrupt on Missed ISOC */ | |
974 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
975 | break; |
976 | ||
977 | case USB_ENDPOINT_XFER_BULK: | |
978 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 979 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
980 | break; |
981 | default: | |
982 | /* | |
983 | * This is only possible with faulty memory because we | |
984 | * checked it already :) | |
985 | */ | |
0a695d4c FB |
986 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
987 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
988 | } |
989 | ||
244add8e TJ |
990 | /* |
991 | * Enable Continue on Short Packet | |
992 | * when endpoint is not a stream capable | |
993 | */ | |
c9508c8c | 994 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
995 | if (!dep->stream_capable) |
996 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 997 | |
e49d3cf4 | 998 | if (short_not_ok) |
c9508c8c FB |
999 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1000 | } | |
1001 | ||
e49d3cf4 | 1002 | if ((!no_interrupt && !chain) || |
b7a4fbe2 | 1003 | (dwc3_calc_trbs_left(dep) == 1)) |
c9508c8c | 1004 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1005 | |
e5ba5ec8 PA |
1006 | if (chain) |
1007 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
1008 | ||
16e78db7 | 1009 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1010 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1011 | |
f6bafc6a | 1012 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1013 | |
b7a4fbe2 AKV |
1014 | dwc3_ep_inc_enq(dep); |
1015 | ||
2c4cbe6e | 1016 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1017 | } |
1018 | ||
e49d3cf4 FB |
1019 | /** |
1020 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1021 | * @dep: endpoint for which this request is prepared | |
1022 | * @req: dwc3_request pointer | |
1023 | * @chain: should this TRB be chained to the next? | |
1024 | * @node: only for isochronous endpoints. First TRB needs different type. | |
1025 | */ | |
1026 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
1027 | struct dwc3_request *req, unsigned chain, unsigned node) | |
1028 | { | |
1029 | struct dwc3_trb *trb; | |
a31e63b6 AKV |
1030 | unsigned int length; |
1031 | dma_addr_t dma; | |
e49d3cf4 FB |
1032 | unsigned stream_id = req->request.stream_id; |
1033 | unsigned short_not_ok = req->request.short_not_ok; | |
1034 | unsigned no_interrupt = req->request.no_interrupt; | |
a31e63b6 AKV |
1035 | |
1036 | if (req->request.num_sgs > 0) { | |
1037 | length = sg_dma_len(req->start_sg); | |
1038 | dma = sg_dma_address(req->start_sg); | |
1039 | } else { | |
1040 | length = req->request.length; | |
1041 | dma = req->request.dma; | |
1042 | } | |
e49d3cf4 FB |
1043 | |
1044 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1045 | ||
1046 | if (!req->trb) { | |
1047 | dwc3_gadget_move_started_request(req); | |
1048 | req->trb = trb; | |
1049 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e49d3cf4 FB |
1050 | } |
1051 | ||
09fe1f8d FB |
1052 | req->num_trbs++; |
1053 | ||
e49d3cf4 FB |
1054 | __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, |
1055 | stream_id, short_not_ok, no_interrupt); | |
1056 | } | |
1057 | ||
5ee85d89 | 1058 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 1059 | struct dwc3_request *req) |
5ee85d89 | 1060 | { |
a31e63b6 | 1061 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1062 | struct scatterlist *s; |
5ee85d89 FB |
1063 | int i; |
1064 | ||
c96e6725 AKV |
1065 | unsigned int remaining = req->request.num_mapped_sgs |
1066 | - req->num_queued_sgs; | |
1067 | ||
1068 | for_each_sg(sg, s, remaining, i) { | |
c6267a51 FB |
1069 | unsigned int length = req->request.length; |
1070 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1071 | unsigned int rem = length % maxp; | |
5ee85d89 FB |
1072 | unsigned chain = true; |
1073 | ||
4bc48c97 | 1074 | if (sg_is_last(s)) |
5ee85d89 FB |
1075 | chain = false; |
1076 | ||
c6267a51 FB |
1077 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { |
1078 | struct dwc3 *dwc = dep->dwc; | |
1079 | struct dwc3_trb *trb; | |
1080 | ||
1a22ec64 | 1081 | req->needs_extra_trb = true; |
c6267a51 FB |
1082 | |
1083 | /* prepare normal TRB */ | |
1084 | dwc3_prepare_one_trb(dep, req, true, i); | |
1085 | ||
1086 | /* Now prepare one extra TRB to align transfer size */ | |
1087 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1088 | req->num_trbs++; |
c6267a51 | 1089 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, |
2fc6d4be | 1090 | maxp - rem, false, 1, |
c6267a51 FB |
1091 | req->request.stream_id, |
1092 | req->request.short_not_ok, | |
1093 | req->request.no_interrupt); | |
1094 | } else { | |
1095 | dwc3_prepare_one_trb(dep, req, chain, i); | |
1096 | } | |
5ee85d89 | 1097 | |
a31e63b6 AKV |
1098 | /* |
1099 | * There can be a situation where all sgs in sglist are not | |
1100 | * queued because of insufficient trb number. To handle this | |
1101 | * case, update start_sg to next sg to be queued, so that | |
1102 | * we have free trbs we can continue queuing from where we | |
1103 | * previously stopped | |
1104 | */ | |
1105 | if (chain) | |
1106 | req->start_sg = sg_next(s); | |
1107 | ||
c96e6725 AKV |
1108 | req->num_queued_sgs++; |
1109 | ||
7ae7df49 | 1110 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
1111 | break; |
1112 | } | |
1113 | } | |
1114 | ||
1115 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 1116 | struct dwc3_request *req) |
5ee85d89 | 1117 | { |
c6267a51 FB |
1118 | unsigned int length = req->request.length; |
1119 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1120 | unsigned int rem = length % maxp; | |
1121 | ||
1e19cdc8 | 1122 | if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) { |
c6267a51 FB |
1123 | struct dwc3 *dwc = dep->dwc; |
1124 | struct dwc3_trb *trb; | |
1125 | ||
1a22ec64 | 1126 | req->needs_extra_trb = true; |
c6267a51 FB |
1127 | |
1128 | /* prepare normal TRB */ | |
1129 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1130 | ||
1131 | /* Now prepare one extra TRB to align transfer size */ | |
1132 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1133 | req->num_trbs++; |
c6267a51 | 1134 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, |
2fc6d4be | 1135 | false, 1, req->request.stream_id, |
c6267a51 FB |
1136 | req->request.short_not_ok, |
1137 | req->request.no_interrupt); | |
d6e5a549 | 1138 | } else if (req->request.zero && req->request.length && |
4ea438da | 1139 | (IS_ALIGNED(req->request.length, maxp))) { |
d6e5a549 FB |
1140 | struct dwc3 *dwc = dep->dwc; |
1141 | struct dwc3_trb *trb; | |
1142 | ||
1a22ec64 | 1143 | req->needs_extra_trb = true; |
d6e5a549 FB |
1144 | |
1145 | /* prepare normal TRB */ | |
1146 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1147 | ||
1148 | /* Now prepare one extra TRB to handle ZLP */ | |
1149 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
09fe1f8d | 1150 | req->num_trbs++; |
d6e5a549 | 1151 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, |
2fc6d4be | 1152 | false, 1, req->request.stream_id, |
d6e5a549 FB |
1153 | req->request.short_not_ok, |
1154 | req->request.no_interrupt); | |
c6267a51 FB |
1155 | } else { |
1156 | dwc3_prepare_one_trb(dep, req, false, 0); | |
1157 | } | |
5ee85d89 FB |
1158 | } |
1159 | ||
72246da4 FB |
1160 | /* |
1161 | * dwc3_prepare_trbs - setup TRBs from requests | |
1162 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1163 | * |
1d046793 PZ |
1164 | * The function goes through the requests list and sets up TRBs for the |
1165 | * transfers. The function returns once there are no more TRBs available or | |
1166 | * it runs out of requests. | |
72246da4 | 1167 | */ |
c4233573 | 1168 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1169 | { |
68e823e2 | 1170 | struct dwc3_request *req, *n; |
72246da4 FB |
1171 | |
1172 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1173 | ||
d86c5a67 FB |
1174 | /* |
1175 | * We can get in a situation where there's a request in the started list | |
1176 | * but there weren't enough TRBs to fully kick it in the first time | |
1177 | * around, so it has been waiting for more TRBs to be freed up. | |
1178 | * | |
1179 | * In that case, we should check if we have a request with pending_sgs | |
1180 | * in the started list and prepare TRBs for that request first, | |
1181 | * otherwise we will prepare TRBs completely out of order and that will | |
1182 | * break things. | |
1183 | */ | |
1184 | list_for_each_entry(req, &dep->started_list, list) { | |
1185 | if (req->num_pending_sgs > 0) | |
1186 | dwc3_prepare_one_trb_sg(dep, req); | |
1187 | ||
1188 | if (!dwc3_calc_trbs_left(dep)) | |
1189 | return; | |
1190 | } | |
1191 | ||
aa3342c8 | 1192 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 FB |
1193 | struct dwc3 *dwc = dep->dwc; |
1194 | int ret; | |
1195 | ||
1196 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1197 | dep->direction); | |
1198 | if (ret) | |
1199 | return; | |
1200 | ||
1201 | req->sg = req->request.sg; | |
a31e63b6 | 1202 | req->start_sg = req->sg; |
c96e6725 | 1203 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1204 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1205 | ||
1f512119 | 1206 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1207 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1208 | else |
7ae7df49 | 1209 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1210 | |
7ae7df49 | 1211 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1212 | return; |
72246da4 | 1213 | } |
72246da4 FB |
1214 | } |
1215 | ||
7fdca766 | 1216 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1217 | { |
1218 | struct dwc3_gadget_ep_cmd_params params; | |
1219 | struct dwc3_request *req; | |
4fae2e3e | 1220 | int starting; |
72246da4 FB |
1221 | int ret; |
1222 | u32 cmd; | |
1223 | ||
ccb94ebf FB |
1224 | if (!dwc3_calc_trbs_left(dep)) |
1225 | return 0; | |
1226 | ||
1912cbc6 | 1227 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1228 | |
4fae2e3e FB |
1229 | dwc3_prepare_trbs(dep); |
1230 | req = next_request(&dep->started_list); | |
72246da4 FB |
1231 | if (!req) { |
1232 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1237 | |
4fae2e3e | 1238 | if (starting) { |
1877d6c9 PA |
1239 | params.param0 = upper_32_bits(req->trb_dma); |
1240 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1241 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1242 | ||
a7351807 AKV |
1243 | if (dep->stream_capable) |
1244 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1245 | ||
7fdca766 FB |
1246 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1247 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1248 | } else { |
b6b1c6db FB |
1249 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1250 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1251 | } |
72246da4 | 1252 | |
2cd4718d | 1253 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1254 | if (ret < 0) { |
72246da4 FB |
1255 | /* |
1256 | * FIXME we need to iterate over the list of requests | |
1257 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1258 | * requests instead of what we do now. |
72246da4 | 1259 | */ |
ce3fc8b3 JD |
1260 | if (req->trb) |
1261 | memset(req->trb, 0, sizeof(struct dwc3_trb)); | |
c91815b5 | 1262 | dwc3_gadget_del_and_unmap_request(dep, req, ret); |
72246da4 FB |
1263 | return ret; |
1264 | } | |
1265 | ||
72246da4 FB |
1266 | return 0; |
1267 | } | |
1268 | ||
6cb2e4e3 FB |
1269 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1270 | { | |
1271 | u32 reg; | |
1272 | ||
1273 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1274 | return DWC3_DSTS_SOFFN(reg); | |
1275 | } | |
1276 | ||
d92021f6 TN |
1277 | /** |
1278 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1279 | * @dep: isoc endpoint | |
1280 | * | |
1281 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1282 | * microframe number reported by the XferNotReady event for the future frame | |
1283 | * number to start the isoc transfer. | |
1284 | * | |
1285 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1286 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1287 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1288 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1289 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1290 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1291 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1292 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1293 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1294 | * | |
1295 | * In order to workaround this issue, we can test for the correct combination of | |
1296 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1297 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1298 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1299 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1300 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1301 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1302 | * value is the correct combination. | |
1303 | * | |
1304 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1305 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1306 | * deduce the smaller successful combination. | |
1307 | * | |
1308 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1309 | * of BIT[15:14]. The correct combination is as follow: | |
1310 | * | |
1311 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1312 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1313 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1314 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1315 | * | |
1316 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1317 | * endpoints. | |
1318 | */ | |
25abad6a | 1319 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1320 | { |
1321 | int cmd_status = 0; | |
1322 | bool test0; | |
1323 | bool test1; | |
1324 | ||
1325 | while (dep->combo_num < 2) { | |
1326 | struct dwc3_gadget_ep_cmd_params params; | |
1327 | u32 test_frame_number; | |
1328 | u32 cmd; | |
1329 | ||
1330 | /* | |
1331 | * Check if we can start isoc transfer on the next interval or | |
1332 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1333 | */ | |
1334 | test_frame_number = dep->frame_number & 0x3fff; | |
1335 | test_frame_number |= dep->combo_num << 14; | |
1336 | test_frame_number += max_t(u32, 4, dep->interval); | |
1337 | ||
1338 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1339 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1340 | ||
1341 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1342 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1343 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1344 | ||
1345 | /* Redo if some other failure beside bus-expiry is received */ | |
1346 | if (cmd_status && cmd_status != -EAGAIN) { | |
1347 | dep->start_cmd_status = 0; | |
1348 | dep->combo_num = 0; | |
25abad6a | 1349 | return 0; |
d92021f6 TN |
1350 | } |
1351 | ||
1352 | /* Store the first test status */ | |
1353 | if (dep->combo_num == 0) | |
1354 | dep->start_cmd_status = cmd_status; | |
1355 | ||
1356 | dep->combo_num++; | |
1357 | ||
1358 | /* | |
1359 | * End the transfer if the START_TRANSFER command is successful | |
1360 | * to wait for the next XferNotReady to test the command again | |
1361 | */ | |
1362 | if (cmd_status == 0) { | |
1363 | dwc3_stop_active_transfer(dep, true); | |
25abad6a | 1364 | return 0; |
d92021f6 TN |
1365 | } |
1366 | } | |
1367 | ||
1368 | /* test0 and test1 are both completed at this point */ | |
1369 | test0 = (dep->start_cmd_status == 0); | |
1370 | test1 = (cmd_status == 0); | |
1371 | ||
1372 | if (!test0 && test1) | |
1373 | dep->combo_num = 1; | |
1374 | else if (!test0 && !test1) | |
1375 | dep->combo_num = 2; | |
1376 | else if (test0 && !test1) | |
1377 | dep->combo_num = 3; | |
1378 | else if (test0 && test1) | |
1379 | dep->combo_num = 0; | |
1380 | ||
1381 | dep->frame_number &= 0x3fff; | |
1382 | dep->frame_number |= dep->combo_num << 14; | |
1383 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1384 | ||
1385 | /* Reinitialize test variables */ | |
1386 | dep->start_cmd_status = 0; | |
1387 | dep->combo_num = 0; | |
1388 | ||
25abad6a | 1389 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1390 | } |
1391 | ||
25abad6a | 1392 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1393 | { |
d92021f6 | 1394 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1395 | int ret; |
1396 | int i; | |
d92021f6 | 1397 | |
aa3342c8 | 1398 | if (list_empty(&dep->pending_list)) { |
f4a53c55 | 1399 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1400 | return -EAGAIN; |
d6d6ec7b PA |
1401 | } |
1402 | ||
d92021f6 TN |
1403 | if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) && |
1404 | (dwc->revision <= DWC3_USB31_REVISION_160A || | |
1405 | (dwc->revision == DWC3_USB31_REVISION_170A && | |
1406 | dwc->version_type >= DWC31_VERSIONTYPE_EA01 && | |
1407 | dwc->version_type <= DWC31_VERSIONTYPE_EA06))) { | |
1408 | ||
25abad6a FB |
1409 | if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) |
1410 | return dwc3_gadget_start_isoc_quirk(dep); | |
d6d6ec7b PA |
1411 | } |
1412 | ||
d5370106 FB |
1413 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1414 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1415 | ||
1416 | ret = __dwc3_gadget_kick_transfer(dep); | |
1417 | if (ret != -EAGAIN) | |
1418 | break; | |
1419 | } | |
1420 | ||
1421 | return ret; | |
d6d6ec7b PA |
1422 | } |
1423 | ||
72246da4 FB |
1424 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1425 | { | |
0fc9a1be | 1426 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1427 | |
bb423984 | 1428 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1429 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1430 | dep->name); | |
bb423984 FB |
1431 | return -ESHUTDOWN; |
1432 | } | |
1433 | ||
04fb365c FB |
1434 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1435 | &req->request, req->dep->name)) | |
bb423984 | 1436 | return -EINVAL; |
bb423984 | 1437 | |
fc8bb91b FB |
1438 | pm_runtime_get(dwc->dev); |
1439 | ||
72246da4 FB |
1440 | req->request.actual = 0; |
1441 | req->request.status = -EINPROGRESS; | |
72246da4 | 1442 | |
fe84f522 FB |
1443 | trace_dwc3_ep_queue(req); |
1444 | ||
aa3342c8 | 1445 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1446 | |
d889c23c FB |
1447 | /* |
1448 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1449 | * wait for a XferNotReady event so we will know what's the current | |
1450 | * (micro-)frame number. | |
1451 | * | |
1452 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1453 | * errors which will force us issue EndTransfer command. | |
1454 | */ | |
1455 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1456 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1457 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1458 | return 0; | |
1459 | ||
6cb2e4e3 | 1460 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
fe990cea | 1461 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { |
25abad6a | 1462 | return __dwc3_gadget_start_isoc(dep); |
6cb2e4e3 | 1463 | } |
08a36b54 | 1464 | } |
64e01080 | 1465 | } |
b997ada5 | 1466 | |
7fdca766 | 1467 | return __dwc3_gadget_kick_transfer(dep); |
72246da4 FB |
1468 | } |
1469 | ||
1470 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1471 | gfp_t gfp_flags) | |
1472 | { | |
1473 | struct dwc3_request *req = to_dwc3_request(request); | |
1474 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1475 | struct dwc3 *dwc = dep->dwc; | |
1476 | ||
1477 | unsigned long flags; | |
1478 | ||
1479 | int ret; | |
1480 | ||
fdee4eba | 1481 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1482 | ret = __dwc3_gadget_ep_queue(dep, req); |
1483 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1484 | ||
1485 | return ret; | |
1486 | } | |
1487 | ||
7746a8df FB |
1488 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1489 | { | |
1490 | int i; | |
1491 | ||
1492 | /* | |
1493 | * If request was already started, this means we had to | |
1494 | * stop the transfer. With that we also need to ignore | |
1495 | * all TRBs used by the request, however TRBs can only | |
1496 | * be modified after completion of END_TRANSFER | |
1497 | * command. So what we do here is that we wait for | |
1498 | * END_TRANSFER completion and only after that, we jump | |
1499 | * over TRBs by clearing HWO and incrementing dequeue | |
1500 | * pointer. | |
1501 | */ | |
1502 | for (i = 0; i < req->num_trbs; i++) { | |
1503 | struct dwc3_trb *trb; | |
1504 | ||
1505 | trb = req->trb + i; | |
1506 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1507 | dwc3_ep_inc_deq(dep); | |
1508 | } | |
1509 | } | |
1510 | ||
d4f1afe5 FB |
1511 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1512 | { | |
1513 | struct dwc3_request *req; | |
1514 | struct dwc3_request *tmp; | |
1515 | ||
1516 | list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { | |
1517 | dwc3_gadget_ep_skip_trbs(dep, req); | |
1518 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1519 | } | |
1520 | } | |
1521 | ||
72246da4 FB |
1522 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1523 | struct usb_request *request) | |
1524 | { | |
1525 | struct dwc3_request *req = to_dwc3_request(request); | |
1526 | struct dwc3_request *r = NULL; | |
1527 | ||
1528 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1529 | struct dwc3 *dwc = dep->dwc; | |
1530 | ||
1531 | unsigned long flags; | |
1532 | int ret = 0; | |
1533 | ||
2c4cbe6e FB |
1534 | trace_dwc3_ep_dequeue(req); |
1535 | ||
72246da4 FB |
1536 | spin_lock_irqsave(&dwc->lock, flags); |
1537 | ||
aa3342c8 | 1538 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1539 | if (r == req) |
1540 | break; | |
1541 | } | |
1542 | ||
1543 | if (r != req) { | |
aa3342c8 | 1544 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1545 | if (r == req) |
1546 | break; | |
1547 | } | |
1548 | if (r == req) { | |
1549 | /* wait until it is processed */ | |
8f608e8a | 1550 | dwc3_stop_active_transfer(dep, true); |
cf3113d8 | 1551 | |
cf3113d8 | 1552 | if (!r->trb) |
05645366 | 1553 | goto out0; |
cf3113d8 | 1554 | |
d4f1afe5 | 1555 | dwc3_gadget_move_cancelled_request(req); |
d4f1afe5 | 1556 | goto out0; |
72246da4 | 1557 | } |
04fb365c | 1558 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
72246da4 FB |
1559 | request, ep->name); |
1560 | ret = -EINVAL; | |
1561 | goto out0; | |
1562 | } | |
1563 | ||
72246da4 FB |
1564 | dwc3_gadget_giveback(dep, req, -ECONNRESET); |
1565 | ||
1566 | out0: | |
1567 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1568 | ||
1569 | return ret; | |
1570 | } | |
1571 | ||
7a608559 | 1572 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1573 | { |
1574 | struct dwc3_gadget_ep_cmd_params params; | |
1575 | struct dwc3 *dwc = dep->dwc; | |
1576 | int ret; | |
1577 | ||
5ad02fb8 FB |
1578 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1579 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1580 | return -EINVAL; | |
1581 | } | |
1582 | ||
72246da4 FB |
1583 | memset(¶ms, 0x00, sizeof(params)); |
1584 | ||
1585 | if (value) { | |
69450c4d FB |
1586 | struct dwc3_trb *trb; |
1587 | ||
1588 | unsigned transfer_in_flight; | |
1589 | unsigned started; | |
1590 | ||
1591 | if (dep->number > 1) | |
1592 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1593 | else | |
1594 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1595 | ||
1596 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1597 | started = !list_empty(&dep->started_list); | |
1598 | ||
1599 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1600 | (!dep->direction && started))) { | |
7a608559 FB |
1601 | return -EAGAIN; |
1602 | } | |
1603 | ||
2cd4718d FB |
1604 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1605 | ¶ms); | |
72246da4 | 1606 | if (ret) |
3f89204b | 1607 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1608 | dep->name); |
1609 | else | |
1610 | dep->flags |= DWC3_EP_STALL; | |
1611 | } else { | |
2cd4718d | 1612 | |
50c763f8 | 1613 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1614 | if (ret) |
3f89204b | 1615 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1616 | dep->name); |
1617 | else | |
a535d81c | 1618 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1619 | } |
5275455a | 1620 | |
72246da4 FB |
1621 | return ret; |
1622 | } | |
1623 | ||
1624 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1625 | { | |
1626 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1627 | struct dwc3 *dwc = dep->dwc; | |
1628 | ||
1629 | unsigned long flags; | |
1630 | ||
1631 | int ret; | |
1632 | ||
1633 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1634 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1635 | spin_unlock_irqrestore(&dwc->lock, flags); |
1636 | ||
1637 | return ret; | |
1638 | } | |
1639 | ||
1640 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1641 | { | |
1642 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1643 | struct dwc3 *dwc = dep->dwc; |
1644 | unsigned long flags; | |
95aa4e8d | 1645 | int ret; |
72246da4 | 1646 | |
249a4569 | 1647 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1648 | dep->flags |= DWC3_EP_WEDGE; |
1649 | ||
08f0d966 | 1650 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1651 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1652 | else |
7a608559 | 1653 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1654 | spin_unlock_irqrestore(&dwc->lock, flags); |
1655 | ||
1656 | return ret; | |
72246da4 FB |
1657 | } |
1658 | ||
1659 | /* -------------------------------------------------------------------------- */ | |
1660 | ||
1661 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1662 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1663 | .bDescriptorType = USB_DT_ENDPOINT, | |
1664 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1665 | }; | |
1666 | ||
1667 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1668 | .enable = dwc3_gadget_ep0_enable, | |
1669 | .disable = dwc3_gadget_ep0_disable, | |
1670 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1671 | .free_request = dwc3_gadget_ep_free_request, | |
1672 | .queue = dwc3_gadget_ep0_queue, | |
1673 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1674 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1675 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1676 | }; | |
1677 | ||
1678 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1679 | .enable = dwc3_gadget_ep_enable, | |
1680 | .disable = dwc3_gadget_ep_disable, | |
1681 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1682 | .free_request = dwc3_gadget_ep_free_request, | |
1683 | .queue = dwc3_gadget_ep_queue, | |
1684 | .dequeue = dwc3_gadget_ep_dequeue, | |
1685 | .set_halt = dwc3_gadget_ep_set_halt, | |
1686 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1687 | }; | |
1688 | ||
1689 | /* -------------------------------------------------------------------------- */ | |
1690 | ||
1691 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1692 | { | |
1693 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1694 | |
6cb2e4e3 | 1695 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1696 | } |
1697 | ||
218ef7b6 | 1698 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1699 | { |
d6011f6f | 1700 | int retries; |
72246da4 | 1701 | |
218ef7b6 | 1702 | int ret; |
72246da4 FB |
1703 | u32 reg; |
1704 | ||
72246da4 FB |
1705 | u8 link_state; |
1706 | u8 speed; | |
1707 | ||
72246da4 FB |
1708 | /* |
1709 | * According to the Databook Remote wakeup request should | |
1710 | * be issued only when the device is in early suspend state. | |
1711 | * | |
1712 | * We can check that via USB Link State bits in DSTS register. | |
1713 | */ | |
1714 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1715 | ||
1716 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c | 1717 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
5eb30ced | 1718 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) |
6b742899 | 1719 | return 0; |
72246da4 FB |
1720 | |
1721 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1722 | ||
1723 | switch (link_state) { | |
1724 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1725 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1726 | break; | |
1727 | default: | |
218ef7b6 | 1728 | return -EINVAL; |
72246da4 FB |
1729 | } |
1730 | ||
8598bde7 FB |
1731 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1732 | if (ret < 0) { | |
1733 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1734 | return ret; |
8598bde7 | 1735 | } |
72246da4 | 1736 | |
802fde98 PZ |
1737 | /* Recent versions do this automatically */ |
1738 | if (dwc->revision < DWC3_REVISION_194A) { | |
1739 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1740 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1741 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1742 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1743 | } | |
72246da4 | 1744 | |
1d046793 | 1745 | /* poll until Link State changes to ON */ |
d6011f6f | 1746 | retries = 20000; |
72246da4 | 1747 | |
d6011f6f | 1748 | while (retries--) { |
72246da4 FB |
1749 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1750 | ||
1751 | /* in HS, means ON */ | |
1752 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1753 | break; | |
1754 | } | |
1755 | ||
1756 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1757 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1758 | return -EINVAL; |
72246da4 FB |
1759 | } |
1760 | ||
218ef7b6 FB |
1761 | return 0; |
1762 | } | |
1763 | ||
1764 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1765 | { | |
1766 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1767 | unsigned long flags; | |
1768 | int ret; | |
1769 | ||
1770 | spin_lock_irqsave(&dwc->lock, flags); | |
1771 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1772 | spin_unlock_irqrestore(&dwc->lock, flags); |
1773 | ||
1774 | return ret; | |
1775 | } | |
1776 | ||
1777 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1778 | int is_selfpowered) | |
1779 | { | |
1780 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1781 | unsigned long flags; |
72246da4 | 1782 | |
249a4569 | 1783 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1784 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1785 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1786 | |
1787 | return 0; | |
1788 | } | |
1789 | ||
7b2a0368 | 1790 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1791 | { |
1792 | u32 reg; | |
61d58242 | 1793 | u32 timeout = 500; |
72246da4 | 1794 | |
fc8bb91b FB |
1795 | if (pm_runtime_suspended(dwc->dev)) |
1796 | return 0; | |
1797 | ||
72246da4 | 1798 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1799 | if (is_on) { |
802fde98 PZ |
1800 | if (dwc->revision <= DWC3_REVISION_187A) { |
1801 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1802 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1803 | } | |
1804 | ||
1805 | if (dwc->revision >= DWC3_REVISION_194A) | |
1806 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1807 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1808 | |
1809 | if (dwc->has_hibernation) | |
1810 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1811 | ||
9fcb3bd8 | 1812 | dwc->pullups_connected = true; |
8db7ed15 | 1813 | } else { |
72246da4 | 1814 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1815 | |
1816 | if (dwc->has_hibernation && !suspend) | |
1817 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1818 | ||
9fcb3bd8 | 1819 | dwc->pullups_connected = false; |
8db7ed15 | 1820 | } |
72246da4 FB |
1821 | |
1822 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1823 | ||
1824 | do { | |
1825 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1826 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1827 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1828 | |
1829 | if (!timeout) | |
1830 | return -ETIMEDOUT; | |
72246da4 | 1831 | |
6f17f74b | 1832 | return 0; |
72246da4 FB |
1833 | } |
1834 | ||
1835 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1836 | { | |
1837 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1838 | unsigned long flags; | |
6f17f74b | 1839 | int ret; |
72246da4 FB |
1840 | |
1841 | is_on = !!is_on; | |
1842 | ||
bb014736 BW |
1843 | /* |
1844 | * Per databook, when we want to stop the gadget, if a control transfer | |
1845 | * is still in process, complete it and get the core into setup phase. | |
1846 | */ | |
1847 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1848 | reinit_completion(&dwc->ep0_in_setup); | |
1849 | ||
1850 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1851 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1852 | if (ret == 0) { | |
1853 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1854 | return -ETIMEDOUT; | |
1855 | } | |
1856 | } | |
1857 | ||
72246da4 | 1858 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1859 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1860 | spin_unlock_irqrestore(&dwc->lock, flags); |
1861 | ||
6f17f74b | 1862 | return ret; |
72246da4 FB |
1863 | } |
1864 | ||
8698e2ac FB |
1865 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1866 | { | |
1867 | u32 reg; | |
1868 | ||
1869 | /* Enable all but Start and End of Frame IRQs */ | |
1870 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1871 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1872 | DWC3_DEVTEN_CMDCMPLTEN | | |
1873 | DWC3_DEVTEN_ERRTICERREN | | |
1874 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1875 | DWC3_DEVTEN_CONNECTDONEEN | |
1876 | DWC3_DEVTEN_USBRSTEN | | |
1877 | DWC3_DEVTEN_DISCONNEVTEN); | |
1878 | ||
799e9dc8 FB |
1879 | if (dwc->revision < DWC3_REVISION_250A) |
1880 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1881 | ||
8698e2ac FB |
1882 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1883 | } | |
1884 | ||
1885 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1886 | { | |
1887 | /* mask all interrupts */ | |
1888 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1889 | } | |
1890 | ||
1891 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1892 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1893 | |
4e99472b | 1894 | /** |
bfad65ee FB |
1895 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
1896 | * @dwc: pointer to our context structure | |
4e99472b FB |
1897 | * |
1898 | * The following looks like complex but it's actually very simple. In order to | |
1899 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1900 | * gonna use RxFIFO size. | |
1901 | * | |
1902 | * To calculate RxFIFO size we need two numbers: | |
1903 | * MDWIDTH = size, in bits, of the internal memory bus | |
1904 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1905 | * | |
1906 | * Given these two numbers, the formula is simple: | |
1907 | * | |
1908 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1909 | * | |
1910 | * 24 bytes is for 3x SETUP packets | |
1911 | * 16 bytes is a clock domain crossing tolerance | |
1912 | * | |
1913 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1914 | */ | |
1915 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1916 | { | |
1917 | u32 ram2_depth; | |
1918 | u32 mdwidth; | |
1919 | u32 nump; | |
1920 | u32 reg; | |
1921 | ||
1922 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1923 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1924 | ||
1925 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1926 | nump = min_t(u32, nump, 16); | |
1927 | ||
1928 | /* update NumP */ | |
1929 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1930 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1931 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1932 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1933 | } | |
1934 | ||
d7be2952 | 1935 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1936 | { |
72246da4 | 1937 | struct dwc3_ep *dep; |
72246da4 FB |
1938 | int ret = 0; |
1939 | u32 reg; | |
1940 | ||
cf40b86b JY |
1941 | /* |
1942 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
1943 | * the core supports IMOD, disable it. | |
1944 | */ | |
1945 | if (dwc->imod_interval) { | |
1946 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
1947 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
1948 | } else if (dwc3_has_imod(dwc)) { | |
1949 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
1950 | } | |
1951 | ||
2a58f9c1 FB |
1952 | /* |
1953 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1954 | * field instead of letting dwc3 itself calculate that automatically. | |
1955 | * | |
1956 | * This way, we maximize the chances that we'll be able to get several | |
1957 | * bursts of data without going through any sort of endpoint throttling. | |
1958 | */ | |
1959 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
01b0e2cc TN |
1960 | if (dwc3_is_usb31(dwc)) |
1961 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
1962 | else | |
1963 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1964 | ||
2a58f9c1 FB |
1965 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
1966 | ||
4e99472b FB |
1967 | dwc3_gadget_setup_nump(dwc); |
1968 | ||
72246da4 FB |
1969 | /* Start with SuperSpeed Default */ |
1970 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1971 | ||
1972 | dep = dwc->eps[0]; | |
a2d23f08 | 1973 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
1974 | if (ret) { |
1975 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1976 | goto err0; |
72246da4 FB |
1977 | } |
1978 | ||
1979 | dep = dwc->eps[1]; | |
a2d23f08 | 1980 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
1981 | if (ret) { |
1982 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1983 | goto err1; |
72246da4 FB |
1984 | } |
1985 | ||
1986 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1987 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 1988 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
72246da4 FB |
1989 | dwc3_ep0_out_start(dwc); |
1990 | ||
8698e2ac FB |
1991 | dwc3_gadget_enable_irq(dwc); |
1992 | ||
72246da4 FB |
1993 | return 0; |
1994 | ||
b0d7ffd4 | 1995 | err1: |
d7be2952 | 1996 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1997 | |
1998 | err0: | |
72246da4 FB |
1999 | return ret; |
2000 | } | |
2001 | ||
d7be2952 FB |
2002 | static int dwc3_gadget_start(struct usb_gadget *g, |
2003 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2004 | { |
2005 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2006 | unsigned long flags; | |
d7be2952 | 2007 | int ret = 0; |
8698e2ac | 2008 | int irq; |
72246da4 | 2009 | |
9522def4 | 2010 | irq = dwc->irq_gadget; |
d7be2952 FB |
2011 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2012 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2013 | if (ret) { | |
2014 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2015 | irq, ret); | |
2016 | goto err0; | |
2017 | } | |
2018 | ||
72246da4 | 2019 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
2020 | if (dwc->gadget_driver) { |
2021 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
2022 | dwc->gadget.name, | |
2023 | dwc->gadget_driver->driver.name); | |
2024 | ret = -EBUSY; | |
2025 | goto err1; | |
2026 | } | |
2027 | ||
2028 | dwc->gadget_driver = driver; | |
2029 | ||
fc8bb91b FB |
2030 | if (pm_runtime_active(dwc->dev)) |
2031 | __dwc3_gadget_start(dwc); | |
2032 | ||
d7be2952 FB |
2033 | spin_unlock_irqrestore(&dwc->lock, flags); |
2034 | ||
2035 | return 0; | |
2036 | ||
2037 | err1: | |
2038 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2039 | free_irq(irq, dwc); | |
2040 | ||
2041 | err0: | |
2042 | return ret; | |
2043 | } | |
72246da4 | 2044 | |
d7be2952 FB |
2045 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2046 | { | |
8698e2ac | 2047 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2048 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2049 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2050 | } |
72246da4 | 2051 | |
d7be2952 FB |
2052 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2053 | { | |
2054 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2055 | unsigned long flags; | |
72246da4 | 2056 | |
d7be2952 | 2057 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
2058 | |
2059 | if (pm_runtime_suspended(dwc->dev)) | |
2060 | goto out; | |
2061 | ||
d7be2952 | 2062 | __dwc3_gadget_stop(dwc); |
76a638f8 | 2063 | |
76a638f8 | 2064 | out: |
d7be2952 | 2065 | dwc->gadget_driver = NULL; |
72246da4 FB |
2066 | spin_unlock_irqrestore(&dwc->lock, flags); |
2067 | ||
3f308d17 | 2068 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2069 | |
72246da4 FB |
2070 | return 0; |
2071 | } | |
802fde98 | 2072 | |
7d8d0639 FB |
2073 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2074 | enum usb_device_speed speed) | |
2075 | { | |
2076 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2077 | unsigned long flags; | |
2078 | u32 reg; | |
2079 | ||
2080 | spin_lock_irqsave(&dwc->lock, flags); | |
2081 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2082 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2083 | ||
2084 | /* | |
2085 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2086 | * which would cause metastability state on Run/Stop | |
2087 | * bit if we try to force the IP to USB2-only mode. | |
2088 | * | |
2089 | * Because of that, we cannot configure the IP to any | |
2090 | * speed other than the SuperSpeed | |
2091 | * | |
2092 | * Refers to: | |
2093 | * | |
2094 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2095 | * USB 2.0 Mode | |
2096 | */ | |
42bf02ec RQ |
2097 | if (dwc->revision < DWC3_REVISION_220A && |
2098 | !dwc->dis_metastability_quirk) { | |
7d8d0639 FB |
2099 | reg |= DWC3_DCFG_SUPERSPEED; |
2100 | } else { | |
2101 | switch (speed) { | |
2102 | case USB_SPEED_LOW: | |
2103 | reg |= DWC3_DCFG_LOWSPEED; | |
2104 | break; | |
2105 | case USB_SPEED_FULL: | |
2106 | reg |= DWC3_DCFG_FULLSPEED; | |
2107 | break; | |
2108 | case USB_SPEED_HIGH: | |
2109 | reg |= DWC3_DCFG_HIGHSPEED; | |
2110 | break; | |
2111 | case USB_SPEED_SUPER: | |
2112 | reg |= DWC3_DCFG_SUPERSPEED; | |
2113 | break; | |
2114 | case USB_SPEED_SUPER_PLUS: | |
2f3090c6 TN |
2115 | if (dwc3_is_usb31(dwc)) |
2116 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2117 | else | |
2118 | reg |= DWC3_DCFG_SUPERSPEED; | |
7d8d0639 FB |
2119 | break; |
2120 | default: | |
2121 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); | |
2122 | ||
2123 | if (dwc->revision & DWC3_REVISION_IS_DWC31) | |
2124 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2125 | else | |
2126 | reg |= DWC3_DCFG_SUPERSPEED; | |
2127 | } | |
2128 | } | |
2129 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2130 | ||
2131 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2132 | } | |
2133 | ||
72246da4 FB |
2134 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2135 | .get_frame = dwc3_gadget_get_frame, | |
2136 | .wakeup = dwc3_gadget_wakeup, | |
2137 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2138 | .pullup = dwc3_gadget_pullup, | |
2139 | .udc_start = dwc3_gadget_start, | |
2140 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2141 | .udc_set_speed = dwc3_gadget_set_speed, |
72246da4 FB |
2142 | }; |
2143 | ||
2144 | /* -------------------------------------------------------------------------- */ | |
2145 | ||
8f1c99cd | 2146 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2147 | { |
8f1c99cd | 2148 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2149 | |
8f1c99cd FB |
2150 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2151 | dep->endpoint.maxburst = 1; | |
2152 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2153 | if (!dep->direction) | |
2154 | dwc->gadget.ep0 = &dep->endpoint; | |
f3bcfc7e | 2155 | |
8f1c99cd | 2156 | dep->endpoint.caps.type_control = true; |
72246da4 | 2157 | |
8f1c99cd FB |
2158 | return 0; |
2159 | } | |
72246da4 | 2160 | |
8f1c99cd FB |
2161 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2162 | { | |
2163 | struct dwc3 *dwc = dep->dwc; | |
2164 | int mdwidth; | |
2165 | int kbytes; | |
2166 | int size; | |
72246da4 | 2167 | |
8f1c99cd FB |
2168 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); |
2169 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
2170 | mdwidth /= 8; | |
6a1e3ef4 | 2171 | |
8f1c99cd FB |
2172 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
2173 | if (dwc3_is_usb31(dwc)) | |
2174 | size = DWC31_GTXFIFOSIZ_TXFDEF(size); | |
2175 | else | |
2176 | size = DWC3_GTXFIFOSIZ_TXFDEF(size); | |
39ebb05c | 2177 | |
8f1c99cd FB |
2178 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2179 | size *= mdwidth; | |
39ebb05c | 2180 | |
8f1c99cd FB |
2181 | kbytes = size / 1024; |
2182 | if (kbytes == 0) | |
2183 | kbytes = 1; | |
28781789 | 2184 | |
8f1c99cd FB |
2185 | /* |
2186 | * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for | |
2187 | * internal overhead. We don't really know how these are used, | |
2188 | * but documentation say it exists. | |
2189 | */ | |
2190 | size -= mdwidth * (kbytes + 1); | |
2191 | size /= kbytes; | |
28781789 | 2192 | |
8f1c99cd | 2193 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2194 | |
8f1c99cd FB |
2195 | dep->endpoint.max_streams = 15; |
2196 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2197 | list_add_tail(&dep->endpoint.ep_list, | |
2198 | &dwc->gadget.ep_list); | |
2199 | dep->endpoint.caps.type_iso = true; | |
2200 | dep->endpoint.caps.type_bulk = true; | |
2201 | dep->endpoint.caps.type_int = true; | |
28781789 | 2202 | |
8f1c99cd FB |
2203 | return dwc3_alloc_trb_pool(dep); |
2204 | } | |
28781789 | 2205 | |
8f1c99cd FB |
2206 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2207 | { | |
2208 | struct dwc3 *dwc = dep->dwc; | |
28781789 | 2209 | |
8f1c99cd FB |
2210 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
2211 | dep->endpoint.max_streams = 15; | |
2212 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2213 | list_add_tail(&dep->endpoint.ep_list, | |
2214 | &dwc->gadget.ep_list); | |
2215 | dep->endpoint.caps.type_iso = true; | |
2216 | dep->endpoint.caps.type_bulk = true; | |
2217 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2218 | |
8f1c99cd FB |
2219 | return dwc3_alloc_trb_pool(dep); |
2220 | } | |
72246da4 | 2221 | |
8f1c99cd FB |
2222 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2223 | { | |
2224 | struct dwc3_ep *dep; | |
2225 | bool direction = epnum & 1; | |
2226 | int ret; | |
2227 | u8 num = epnum >> 1; | |
25b8ff68 | 2228 | |
8f1c99cd FB |
2229 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
2230 | if (!dep) | |
2231 | return -ENOMEM; | |
2232 | ||
2233 | dep->dwc = dwc; | |
2234 | dep->number = epnum; | |
2235 | dep->direction = direction; | |
2236 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
2237 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
2238 | dep->combo_num = 0; |
2239 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
2240 | |
2241 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
2242 | direction ? "in" : "out"); | |
2243 | ||
2244 | dep->endpoint.name = dep->name; | |
2245 | ||
2246 | if (!(dep->number > 1)) { | |
2247 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2248 | dep->endpoint.comp_desc = NULL; | |
2249 | } | |
2250 | ||
2251 | spin_lock_init(&dep->lock); | |
2252 | ||
2253 | if (num == 0) | |
2254 | ret = dwc3_gadget_init_control_endpoint(dep); | |
2255 | else if (direction) | |
2256 | ret = dwc3_gadget_init_in_endpoint(dep); | |
2257 | else | |
2258 | ret = dwc3_gadget_init_out_endpoint(dep); | |
2259 | ||
2260 | if (ret) | |
2261 | return ret; | |
a474d3b7 | 2262 | |
8f1c99cd FB |
2263 | dep->endpoint.caps.dir_in = direction; |
2264 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 2265 | |
8f1c99cd FB |
2266 | INIT_LIST_HEAD(&dep->pending_list); |
2267 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 2268 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd FB |
2269 | |
2270 | return 0; | |
2271 | } | |
2272 | ||
2273 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
2274 | { | |
2275 | u8 epnum; | |
2276 | ||
2277 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
2278 | ||
2279 | for (epnum = 0; epnum < total; epnum++) { | |
2280 | int ret; | |
2281 | ||
2282 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
2283 | if (ret) | |
2284 | return ret; | |
72246da4 FB |
2285 | } |
2286 | ||
2287 | return 0; | |
2288 | } | |
2289 | ||
2290 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2291 | { | |
2292 | struct dwc3_ep *dep; | |
2293 | u8 epnum; | |
2294 | ||
2295 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2296 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2297 | if (!dep) |
2298 | continue; | |
5bf8fae3 GC |
2299 | /* |
2300 | * Physical endpoints 0 and 1 are special; they form the | |
2301 | * bi-directional USB endpoint 0. | |
2302 | * | |
2303 | * For those two physical endpoints, we don't allocate a TRB | |
2304 | * pool nor do we add them the endpoints list. Due to that, we | |
2305 | * shouldn't do these two operations otherwise we would end up | |
2306 | * with all sorts of bugs when removing dwc3.ko. | |
2307 | */ | |
2308 | if (epnum != 0 && epnum != 1) { | |
2309 | dwc3_free_trb_pool(dep); | |
72246da4 | 2310 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2311 | } |
72246da4 FB |
2312 | |
2313 | kfree(dep); | |
2314 | } | |
2315 | } | |
2316 | ||
72246da4 | 2317 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2318 | |
8f608e8a FB |
2319 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
2320 | struct dwc3_request *req, struct dwc3_trb *trb, | |
2321 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 2322 | { |
72246da4 | 2323 | unsigned int count; |
72246da4 | 2324 | |
dc55c67e | 2325 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 2326 | |
2c4cbe6e | 2327 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 2328 | req->num_trbs--; |
2c4cbe6e | 2329 | |
e5b36ae2 FB |
2330 | /* |
2331 | * If we're in the middle of series of chained TRBs and we | |
2332 | * receive a short transfer along the way, DWC3 will skip | |
2333 | * through all TRBs including the last TRB in the chain (the | |
2334 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2335 | * bit and SW has to do it manually. | |
2336 | * | |
2337 | * We're going to do that here to avoid problems of HW trying | |
2338 | * to use bogus TRBs for transfers. | |
2339 | */ | |
2340 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2341 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2342 | ||
6abfa0f5 TN |
2343 | /* |
2344 | * For isochronous transfers, the first TRB in a service interval must | |
2345 | * have the Isoc-First type. Track and report its interval frame number. | |
2346 | */ | |
2347 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
2348 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
2349 | unsigned int frame_number; | |
2350 | ||
2351 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
2352 | frame_number &= ~(dep->interval - 1); | |
2353 | req->request.frame_number = frame_number; | |
2354 | } | |
2355 | ||
c6267a51 FB |
2356 | /* |
2357 | * If we're dealing with unaligned size OUT transfer, we will be left | |
2358 | * with one TRB pending in the ring. We need to manually clear HWO bit | |
2359 | * from that TRB. | |
2360 | */ | |
1a22ec64 FB |
2361 | |
2362 | if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { | |
c6267a51 FB |
2363 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2364 | return 1; | |
2365 | } | |
2366 | ||
e5ba5ec8 | 2367 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2368 | req->remaining += count; |
e5ba5ec8 | 2369 | |
35b2719e FB |
2370 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2371 | return 1; | |
2372 | ||
d80fe1b6 | 2373 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 2374 | return 1; |
f99f53f2 | 2375 | |
e0c42ce5 | 2376 | if (event->status & DEPEVT_STATUS_IOC) |
e5ba5ec8 | 2377 | return 1; |
f99f53f2 | 2378 | |
e5ba5ec8 PA |
2379 | return 0; |
2380 | } | |
2381 | ||
d3692953 FB |
2382 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
2383 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2384 | int status) | |
2385 | { | |
2386 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2387 | struct scatterlist *sg = req->sg; | |
2388 | struct scatterlist *s; | |
2389 | unsigned int pending = req->num_pending_sgs; | |
2390 | unsigned int i; | |
2391 | int ret = 0; | |
2392 | ||
2393 | for_each_sg(sg, s, pending, i) { | |
2394 | trb = &dep->trb_pool[dep->trb_dequeue]; | |
2395 | ||
2396 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) | |
2397 | break; | |
2398 | ||
2399 | req->sg = sg_next(s); | |
2400 | req->num_pending_sgs--; | |
2401 | ||
2402 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
2403 | trb, event, status, true); | |
2404 | if (ret) | |
2405 | break; | |
2406 | } | |
2407 | ||
2408 | return ret; | |
2409 | } | |
2410 | ||
2411 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
2412 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
2413 | int status) | |
2414 | { | |
2415 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
2416 | ||
2417 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
2418 | event, status, false); | |
2419 | } | |
2420 | ||
e0c42ce5 FB |
2421 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
2422 | { | |
2423 | return req->request.actual == req->request.length; | |
2424 | } | |
2425 | ||
f38e35dd FB |
2426 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
2427 | const struct dwc3_event_depevt *event, | |
2428 | struct dwc3_request *req, int status) | |
2429 | { | |
2430 | int ret; | |
2431 | ||
2432 | if (req->num_pending_sgs) | |
2433 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, | |
2434 | status); | |
2435 | else | |
2436 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
2437 | status); | |
2438 | ||
1a22ec64 | 2439 | if (req->needs_extra_trb) { |
f38e35dd FB |
2440 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
2441 | status); | |
1a22ec64 | 2442 | req->needs_extra_trb = false; |
f38e35dd FB |
2443 | } |
2444 | ||
2445 | req->request.actual = req->request.length - req->remaining; | |
2446 | ||
2447 | if (!dwc3_gadget_ep_request_completed(req) && | |
2448 | req->num_pending_sgs) { | |
2449 | __dwc3_gadget_kick_transfer(dep); | |
2450 | goto out; | |
2451 | } | |
2452 | ||
2453 | dwc3_gadget_giveback(dep, req, status); | |
2454 | ||
2455 | out: | |
2456 | return ret; | |
2457 | } | |
2458 | ||
12a3a4ad | 2459 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 2460 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 2461 | { |
6afbdb57 FB |
2462 | struct dwc3_request *req; |
2463 | struct dwc3_request *tmp; | |
e5ba5ec8 | 2464 | |
6afbdb57 | 2465 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) { |
fee73e61 | 2466 | int ret; |
e5b36ae2 | 2467 | |
f38e35dd FB |
2468 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
2469 | req, status); | |
58f0218a | 2470 | if (ret) |
72246da4 | 2471 | break; |
31162af4 | 2472 | } |
72246da4 FB |
2473 | } |
2474 | ||
ee3638b8 FB |
2475 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
2476 | const struct dwc3_event_depevt *event) | |
2477 | { | |
f62afb49 | 2478 | dep->frame_number = event->parameters; |
ee3638b8 FB |
2479 | } |
2480 | ||
8f608e8a FB |
2481 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, |
2482 | const struct dwc3_event_depevt *event) | |
72246da4 | 2483 | { |
8f608e8a | 2484 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2485 | unsigned status = 0; |
6d8a0196 | 2486 | bool stop = false; |
72246da4 | 2487 | |
ee3638b8 FB |
2488 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
2489 | ||
72246da4 FB |
2490 | if (event->status & DEPEVT_STATUS_BUSERR) |
2491 | status = -ECONNRESET; | |
2492 | ||
6d8a0196 FB |
2493 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) { |
2494 | status = -EXDEV; | |
d513320f FB |
2495 | |
2496 | if (list_empty(&dep->started_list)) | |
2497 | stop = true; | |
6d8a0196 FB |
2498 | } |
2499 | ||
5f2e7975 | 2500 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 2501 | |
6d8a0196 FB |
2502 | if (stop) { |
2503 | dwc3_stop_active_transfer(dep, true); | |
2504 | dep->flags = DWC3_EP_ENABLED; | |
2505 | } | |
2506 | ||
fae2b904 FB |
2507 | /* |
2508 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2509 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2510 | */ | |
2511 | if (dwc->revision < DWC3_REVISION_183A) { | |
2512 | u32 reg; | |
2513 | int i; | |
2514 | ||
2515 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2516 | dep = dwc->eps[i]; |
fae2b904 FB |
2517 | |
2518 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2519 | continue; | |
2520 | ||
aa3342c8 | 2521 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2522 | return; |
2523 | } | |
2524 | ||
2525 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2526 | reg |= dwc->u1u2; | |
2527 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2528 | ||
2529 | dwc->u1u2 = 0; | |
2530 | } | |
72246da4 FB |
2531 | } |
2532 | ||
8f608e8a FB |
2533 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
2534 | const struct dwc3_event_depevt *event) | |
32033865 | 2535 | { |
ee3638b8 | 2536 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
25abad6a | 2537 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
2538 | } |
2539 | ||
72246da4 FB |
2540 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2541 | const struct dwc3_event_depevt *event) | |
2542 | { | |
2543 | struct dwc3_ep *dep; | |
2544 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2545 | u8 cmd; |
72246da4 FB |
2546 | |
2547 | dep = dwc->eps[epnum]; | |
2548 | ||
d7fd41c6 JD |
2549 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
2550 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
2551 | return; | |
2552 | ||
2553 | /* Handle only EPCMDCMPLT when EP disabled */ | |
2554 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
2555 | return; | |
2556 | } | |
3336abb5 | 2557 | |
72246da4 FB |
2558 | if (epnum == 0 || epnum == 1) { |
2559 | dwc3_ep0_interrupt(dwc, event); | |
2560 | return; | |
2561 | } | |
2562 | ||
2563 | switch (event->endpoint_event) { | |
72246da4 | 2564 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 2565 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
2566 | break; |
2567 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 2568 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 2569 | break; |
72246da4 | 2570 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2571 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2572 | ||
2573 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
2574 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
fec9095b | 2575 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); |
76a638f8 BW |
2576 | } |
2577 | break; | |
a24a6ab1 | 2578 | case DWC3_DEPEVT_STREAMEVT: |
742a4fff | 2579 | case DWC3_DEPEVT_XFERCOMPLETE: |
76a638f8 | 2580 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
2581 | break; |
2582 | } | |
2583 | } | |
2584 | ||
2585 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2586 | { | |
2587 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2588 | spin_unlock(&dwc->lock); | |
2589 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2590 | spin_lock(&dwc->lock); | |
2591 | } | |
2592 | } | |
2593 | ||
bc5ba2e0 FB |
2594 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2595 | { | |
73a30bfc | 2596 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2597 | spin_unlock(&dwc->lock); |
2598 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2599 | spin_lock(&dwc->lock); | |
2600 | } | |
2601 | } | |
2602 | ||
2603 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2604 | { | |
73a30bfc | 2605 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2606 | spin_unlock(&dwc->lock); |
2607 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2608 | spin_lock(&dwc->lock); |
8e74475b FB |
2609 | } |
2610 | } | |
2611 | ||
2612 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2613 | { | |
2614 | if (!dwc->gadget_driver) | |
2615 | return; | |
2616 | ||
2617 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2618 | spin_unlock(&dwc->lock); | |
2619 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2620 | spin_lock(&dwc->lock); |
2621 | } | |
2622 | } | |
2623 | ||
8f608e8a | 2624 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force) |
72246da4 | 2625 | { |
8f608e8a | 2626 | struct dwc3 *dwc = dep->dwc; |
72246da4 FB |
2627 | struct dwc3_gadget_ep_cmd_params params; |
2628 | u32 cmd; | |
2629 | int ret; | |
2630 | ||
76a638f8 BW |
2631 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || |
2632 | !dep->resource_index) | |
3daf74d7 PA |
2633 | return; |
2634 | ||
57911504 PA |
2635 | /* |
2636 | * NOTICE: We are violating what the Databook says about the | |
2637 | * EndTransfer command. Ideally we would _always_ wait for the | |
2638 | * EndTransfer Command Completion IRQ, but that's causing too | |
2639 | * much trouble synchronizing between us and gadget driver. | |
2640 | * | |
2641 | * We have discussed this with the IP Provider and it was | |
2642 | * suggested to giveback all requests here, but give HW some | |
2643 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2644 | * an arbitrary 100us delay for that. |
57911504 PA |
2645 | * |
2646 | * Note also that a similar handling was tested by Synopsys | |
2647 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2648 | * In short, what we're doing is: | |
2649 | * | |
2650 | * - Issue EndTransfer WITH CMDIOC bit set | |
2651 | * - Wait 100us | |
06281d46 JY |
2652 | * |
2653 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2654 | * supports a mode to work around the above limitation. The | |
2655 | * software can poll the CMDACT bit in the DEPCMD register | |
2656 | * after issuing a EndTransfer command. This mode is enabled | |
2657 | * by writing GUCTL2[14]. This polling is already done in the | |
2658 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2659 | * enabled, the EndTransfer command will have completed upon | |
2660 | * returning from this function and we don't need to delay for | |
2661 | * 100us. | |
2662 | * | |
2663 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2664 | */ |
2665 | ||
3daf74d7 | 2666 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2667 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2668 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2669 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2670 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2671 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2672 | WARN_ON_ONCE(ret); |
b4996a86 | 2673 | dep->resource_index = 0; |
06281d46 | 2674 | |
76a638f8 BW |
2675 | if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) { |
2676 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
06281d46 | 2677 | udelay(100); |
76a638f8 | 2678 | } |
72246da4 FB |
2679 | } |
2680 | ||
72246da4 FB |
2681 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2682 | { | |
2683 | u32 epnum; | |
2684 | ||
2685 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2686 | struct dwc3_ep *dep; | |
72246da4 FB |
2687 | int ret; |
2688 | ||
2689 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2690 | if (!dep) |
2691 | continue; | |
72246da4 FB |
2692 | |
2693 | if (!(dep->flags & DWC3_EP_STALL)) | |
2694 | continue; | |
2695 | ||
2696 | dep->flags &= ~DWC3_EP_STALL; | |
2697 | ||
50c763f8 | 2698 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2699 | WARN_ON_ONCE(ret); |
2700 | } | |
2701 | } | |
2702 | ||
2703 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2704 | { | |
c4430a26 FB |
2705 | int reg; |
2706 | ||
72246da4 FB |
2707 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2708 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2709 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2710 | ||
2711 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2712 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2713 | |
72246da4 FB |
2714 | dwc3_disconnect_gadget(dwc); |
2715 | ||
2716 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2717 | dwc->setup_packet_pending = false; |
06a374ed | 2718 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2719 | |
2720 | dwc->connected = false; | |
72246da4 FB |
2721 | } |
2722 | ||
72246da4 FB |
2723 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2724 | { | |
2725 | u32 reg; | |
2726 | ||
fc8bb91b FB |
2727 | dwc->connected = true; |
2728 | ||
df62df56 FB |
2729 | /* |
2730 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2731 | * would cause a missing Disconnect Event if there's a | |
2732 | * pending Setup Packet in the FIFO. | |
2733 | * | |
2734 | * There's no suggested workaround on the official Bug | |
2735 | * report, which states that "unless the driver/application | |
2736 | * is doing any special handling of a disconnect event, | |
2737 | * there is no functional issue". | |
2738 | * | |
2739 | * Unfortunately, it turns out that we _do_ some special | |
2740 | * handling of a disconnect event, namely complete all | |
2741 | * pending transfers, notify gadget driver of the | |
2742 | * disconnection, and so on. | |
2743 | * | |
2744 | * Our suggested workaround is to follow the Disconnect | |
2745 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2746 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2747 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2748 | * same endpoint. |
2749 | * | |
2750 | * Refers to: | |
2751 | * | |
2752 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2753 | * generated if setup packet pending in FIFO | |
2754 | */ | |
2755 | if (dwc->revision < DWC3_REVISION_188A) { | |
2756 | if (dwc->setup_packet_pending) | |
2757 | dwc3_gadget_disconnect_interrupt(dwc); | |
2758 | } | |
2759 | ||
8e74475b | 2760 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2761 | |
2762 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2763 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2764 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2765 | dwc->test_mode = false; |
72246da4 FB |
2766 | dwc3_clear_stall_all_ep(dwc); |
2767 | ||
2768 | /* Reset device address to zero */ | |
2769 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2770 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2771 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2772 | } |
2773 | ||
72246da4 FB |
2774 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2775 | { | |
72246da4 FB |
2776 | struct dwc3_ep *dep; |
2777 | int ret; | |
2778 | u32 reg; | |
2779 | u8 speed; | |
2780 | ||
72246da4 FB |
2781 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2782 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2783 | dwc->speed = speed; | |
2784 | ||
5fb6fdaf JY |
2785 | /* |
2786 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2787 | * each time on Connect Done. | |
2788 | * | |
2789 | * Currently we always use the reset value. If any platform | |
2790 | * wants to set this to a different value, we need to add a | |
2791 | * setting and update GCTL.RAMCLKSEL here. | |
2792 | */ | |
72246da4 FB |
2793 | |
2794 | switch (speed) { | |
2da9ad76 | 2795 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2796 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2797 | dwc->gadget.ep0->maxpacket = 512; | |
2798 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2799 | break; | |
2da9ad76 | 2800 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2801 | /* |
2802 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2803 | * would cause a missing USB3 Reset event. | |
2804 | * | |
2805 | * In such situations, we should force a USB3 Reset | |
2806 | * event by calling our dwc3_gadget_reset_interrupt() | |
2807 | * routine. | |
2808 | * | |
2809 | * Refers to: | |
2810 | * | |
2811 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2812 | * not be generated always when the link enters poll | |
2813 | */ | |
2814 | if (dwc->revision < DWC3_REVISION_190A) | |
2815 | dwc3_gadget_reset_interrupt(dwc); | |
2816 | ||
72246da4 FB |
2817 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2818 | dwc->gadget.ep0->maxpacket = 512; | |
2819 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2820 | break; | |
2da9ad76 | 2821 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2822 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2823 | dwc->gadget.ep0->maxpacket = 64; | |
2824 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2825 | break; | |
9418ee15 | 2826 | case DWC3_DSTS_FULLSPEED: |
72246da4 FB |
2827 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2828 | dwc->gadget.ep0->maxpacket = 64; | |
2829 | dwc->gadget.speed = USB_SPEED_FULL; | |
2830 | break; | |
2da9ad76 | 2831 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2832 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
2833 | dwc->gadget.ep0->maxpacket = 8; | |
2834 | dwc->gadget.speed = USB_SPEED_LOW; | |
2835 | break; | |
2836 | } | |
2837 | ||
61800263 TN |
2838 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; |
2839 | ||
2b758350 PA |
2840 | /* Enable USB2 LPM Capability */ |
2841 | ||
ee5cd41c | 2842 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
2843 | (speed != DWC3_DSTS_SUPERSPEED) && |
2844 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2845 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2846 | reg |= DWC3_DCFG_LPM_CAP; | |
2847 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2848 | ||
2849 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2850 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2851 | ||
460d098c | 2852 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2853 | |
80caf7d2 HR |
2854 | /* |
2855 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2856 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2857 | * BESL value in the LPM token is less than or equal to LPM | |
2858 | * NYET threshold. | |
2859 | */ | |
2860 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2861 | && dwc->has_lpm_erratum, | |
9165dabb | 2862 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 HR |
2863 | |
2864 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2865 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2866 | ||
356363bf FB |
2867 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2868 | } else { | |
2869 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2870 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2871 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2872 | } | |
2873 | ||
72246da4 | 2874 | dep = dwc->eps[0]; |
a2d23f08 | 2875 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
2876 | if (ret) { |
2877 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2878 | return; | |
2879 | } | |
2880 | ||
2881 | dep = dwc->eps[1]; | |
a2d23f08 | 2882 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
2883 | if (ret) { |
2884 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2885 | return; | |
2886 | } | |
2887 | ||
2888 | /* | |
2889 | * Configure PHY via GUSB3PIPECTLn if required. | |
2890 | * | |
2891 | * Update GTXFIFOSIZn | |
2892 | * | |
2893 | * In both cases reset values should be sufficient. | |
2894 | */ | |
2895 | } | |
2896 | ||
2897 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2898 | { | |
72246da4 FB |
2899 | /* |
2900 | * TODO take core out of low power mode when that's | |
2901 | * implemented. | |
2902 | */ | |
2903 | ||
ad14d4e0 JL |
2904 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2905 | spin_unlock(&dwc->lock); | |
2906 | dwc->gadget_driver->resume(&dwc->gadget); | |
2907 | spin_lock(&dwc->lock); | |
2908 | } | |
72246da4 FB |
2909 | } |
2910 | ||
2911 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2912 | unsigned int evtinfo) | |
2913 | { | |
fae2b904 | 2914 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2915 | unsigned int pwropt; |
2916 | ||
2917 | /* | |
2918 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2919 | * Hibernation mode enabled which would show up when device detects | |
2920 | * host-initiated U3 exit. | |
2921 | * | |
2922 | * In that case, device will generate a Link State Change Interrupt | |
2923 | * from U3 to RESUME which is only necessary if Hibernation is | |
2924 | * configured in. | |
2925 | * | |
2926 | * There are no functional changes due to such spurious event and we | |
2927 | * just need to ignore it. | |
2928 | * | |
2929 | * Refers to: | |
2930 | * | |
2931 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2932 | * operational mode | |
2933 | */ | |
2934 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2935 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2936 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2937 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2938 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
2939 | return; |
2940 | } | |
2941 | } | |
fae2b904 FB |
2942 | |
2943 | /* | |
2944 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2945 | * on the link partner, the USB session might do multiple entry/exit | |
2946 | * of low power states before a transfer takes place. | |
2947 | * | |
2948 | * Due to this problem, we might experience lower throughput. The | |
2949 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2950 | * transitioning from U1/U2 to U0 and enable those bits again | |
2951 | * after a transfer completes and there are no pending transfers | |
2952 | * on any of the enabled endpoints. | |
2953 | * | |
2954 | * This is the first half of that workaround. | |
2955 | * | |
2956 | * Refers to: | |
2957 | * | |
2958 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2959 | * core send LGO_Ux entering U0 | |
2960 | */ | |
2961 | if (dwc->revision < DWC3_REVISION_183A) { | |
2962 | if (next == DWC3_LINK_STATE_U0) { | |
2963 | u32 u1u2; | |
2964 | u32 reg; | |
2965 | ||
2966 | switch (dwc->link_state) { | |
2967 | case DWC3_LINK_STATE_U1: | |
2968 | case DWC3_LINK_STATE_U2: | |
2969 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2970 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2971 | | DWC3_DCTL_ACCEPTU2ENA | |
2972 | | DWC3_DCTL_INITU1ENA | |
2973 | | DWC3_DCTL_ACCEPTU1ENA); | |
2974 | ||
2975 | if (!dwc->u1u2) | |
2976 | dwc->u1u2 = reg & u1u2; | |
2977 | ||
2978 | reg &= ~u1u2; | |
2979 | ||
2980 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2981 | break; | |
2982 | default: | |
2983 | /* do nothing */ | |
2984 | break; | |
2985 | } | |
2986 | } | |
2987 | } | |
2988 | ||
bc5ba2e0 FB |
2989 | switch (next) { |
2990 | case DWC3_LINK_STATE_U1: | |
2991 | if (dwc->speed == USB_SPEED_SUPER) | |
2992 | dwc3_suspend_gadget(dwc); | |
2993 | break; | |
2994 | case DWC3_LINK_STATE_U2: | |
2995 | case DWC3_LINK_STATE_U3: | |
2996 | dwc3_suspend_gadget(dwc); | |
2997 | break; | |
2998 | case DWC3_LINK_STATE_RESUME: | |
2999 | dwc3_resume_gadget(dwc); | |
3000 | break; | |
3001 | default: | |
3002 | /* do nothing */ | |
3003 | break; | |
3004 | } | |
3005 | ||
e57ebc1d | 3006 | dwc->link_state = next; |
72246da4 FB |
3007 | } |
3008 | ||
72704f87 BW |
3009 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
3010 | unsigned int evtinfo) | |
3011 | { | |
3012 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
3013 | ||
3014 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
3015 | dwc3_suspend_gadget(dwc); | |
3016 | ||
3017 | dwc->link_state = next; | |
3018 | } | |
3019 | ||
e1dadd3b FB |
3020 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
3021 | unsigned int evtinfo) | |
3022 | { | |
3023 | unsigned int is_ss = evtinfo & BIT(4); | |
3024 | ||
bfad65ee | 3025 | /* |
e1dadd3b FB |
3026 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
3027 | * have a known issue which can cause USB CV TD.9.23 to fail | |
3028 | * randomly. | |
3029 | * | |
3030 | * Because of this issue, core could generate bogus hibernation | |
3031 | * events which SW needs to ignore. | |
3032 | * | |
3033 | * Refers to: | |
3034 | * | |
3035 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
3036 | * Device Fallback from SuperSpeed | |
3037 | */ | |
3038 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
3039 | return; | |
3040 | ||
3041 | /* enter hibernation here */ | |
3042 | } | |
3043 | ||
72246da4 FB |
3044 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
3045 | const struct dwc3_event_devt *event) | |
3046 | { | |
3047 | switch (event->type) { | |
3048 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
3049 | dwc3_gadget_disconnect_interrupt(dwc); | |
3050 | break; | |
3051 | case DWC3_DEVICE_EVENT_RESET: | |
3052 | dwc3_gadget_reset_interrupt(dwc); | |
3053 | break; | |
3054 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
3055 | dwc3_gadget_conndone_interrupt(dwc); | |
3056 | break; | |
3057 | case DWC3_DEVICE_EVENT_WAKEUP: | |
3058 | dwc3_gadget_wakeup_interrupt(dwc); | |
3059 | break; | |
e1dadd3b FB |
3060 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
3061 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
3062 | "unexpected hibernation event\n")) | |
3063 | break; | |
3064 | ||
3065 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
3066 | break; | |
72246da4 FB |
3067 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
3068 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
3069 | break; | |
3070 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 3071 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 3072 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
3073 | /* |
3074 | * Ignore suspend event until the gadget enters into | |
3075 | * USB_STATE_CONFIGURED state. | |
3076 | */ | |
3077 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
3078 | dwc3_gadget_suspend_interrupt(dwc, | |
3079 | event->event_info); | |
3080 | } | |
72246da4 FB |
3081 | break; |
3082 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 3083 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 3084 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 3085 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
3086 | break; |
3087 | default: | |
e9f2aa87 | 3088 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
3089 | } |
3090 | } | |
3091 | ||
3092 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
3093 | const union dwc3_event *event) | |
3094 | { | |
43c96be1 | 3095 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 3096 | |
dfc5e805 FB |
3097 | if (!event->type.is_devspec) |
3098 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
3099 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 3100 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 3101 | else |
72246da4 | 3102 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
3103 | } |
3104 | ||
dea520a4 | 3105 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 3106 | { |
dea520a4 | 3107 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 3108 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3109 | int left; |
e8adfc30 | 3110 | u32 reg; |
b15a762f | 3111 | |
f42f2447 | 3112 | left = evt->count; |
b15a762f | 3113 | |
f42f2447 FB |
3114 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3115 | return IRQ_NONE; | |
b15a762f | 3116 | |
f42f2447 FB |
3117 | while (left > 0) { |
3118 | union dwc3_event event; | |
b15a762f | 3119 | |
ebbb2d59 | 3120 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3121 | |
f42f2447 | 3122 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3123 | |
f42f2447 FB |
3124 | /* |
3125 | * FIXME we wrap around correctly to the next entry as | |
3126 | * almost all entries are 4 bytes in size. There is one | |
3127 | * entry which has 12 bytes which is a regular entry | |
3128 | * followed by 8 bytes data. ATM I don't know how | |
3129 | * things are organized if we get next to the a | |
3130 | * boundary so I worry about that once we try to handle | |
3131 | * that. | |
3132 | */ | |
caefe6c7 | 3133 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3134 | left -= 4; |
f42f2447 | 3135 | } |
b15a762f | 3136 | |
f42f2447 FB |
3137 | evt->count = 0; |
3138 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3139 | ret = IRQ_HANDLED; | |
b15a762f | 3140 | |
f42f2447 | 3141 | /* Unmask interrupt */ |
660e9bde | 3142 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3143 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3144 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3145 | |
cf40b86b JY |
3146 | if (dwc->imod_interval) { |
3147 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3148 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3149 | } | |
3150 | ||
f42f2447 FB |
3151 | return ret; |
3152 | } | |
e8adfc30 | 3153 | |
dea520a4 | 3154 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3155 | { |
dea520a4 FB |
3156 | struct dwc3_event_buffer *evt = _evt; |
3157 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3158 | unsigned long flags; |
f42f2447 | 3159 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3160 | |
e5f68b4a | 3161 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3162 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3163 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3164 | |
3165 | return ret; | |
3166 | } | |
3167 | ||
dea520a4 | 3168 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3169 | { |
dea520a4 | 3170 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3171 | u32 amount; |
72246da4 | 3172 | u32 count; |
e8adfc30 | 3173 | u32 reg; |
72246da4 | 3174 | |
fc8bb91b FB |
3175 | if (pm_runtime_suspended(dwc->dev)) { |
3176 | pm_runtime_get(dwc->dev); | |
3177 | disable_irq_nosync(dwc->irq_gadget); | |
3178 | dwc->pending_events = true; | |
3179 | return IRQ_HANDLED; | |
3180 | } | |
3181 | ||
d325a1de TN |
3182 | /* |
3183 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
3184 | * be called again after HW interrupt deassertion. Check if bottom-half | |
3185 | * irq event handler completes before caching new event to prevent | |
3186 | * losing events. | |
3187 | */ | |
3188 | if (evt->flags & DWC3_EVENT_PENDING) | |
3189 | return IRQ_HANDLED; | |
3190 | ||
660e9bde | 3191 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3192 | count &= DWC3_GEVNTCOUNT_MASK; |
3193 | if (!count) | |
3194 | return IRQ_NONE; | |
3195 | ||
b15a762f FB |
3196 | evt->count = count; |
3197 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3198 | |
e8adfc30 | 3199 | /* Mask interrupt */ |
660e9bde | 3200 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3201 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3202 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3203 | |
ebbb2d59 JY |
3204 | amount = min(count, evt->length - evt->lpos); |
3205 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3206 | ||
3207 | if (amount < count) | |
3208 | memcpy(evt->cache, evt->buf, count - amount); | |
3209 | ||
65aca320 JY |
3210 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3211 | ||
b15a762f | 3212 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3213 | } |
3214 | ||
dea520a4 | 3215 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3216 | { |
dea520a4 | 3217 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3218 | |
dea520a4 | 3219 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3220 | } |
3221 | ||
6db3812e FB |
3222 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3223 | { | |
3224 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3225 | int irq; | |
3226 | ||
3227 | irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); | |
3228 | if (irq > 0) | |
3229 | goto out; | |
3230 | ||
3231 | if (irq == -EPROBE_DEFER) | |
3232 | goto out; | |
3233 | ||
3234 | irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); | |
3235 | if (irq > 0) | |
3236 | goto out; | |
3237 | ||
3238 | if (irq == -EPROBE_DEFER) | |
3239 | goto out; | |
3240 | ||
3241 | irq = platform_get_irq(dwc3_pdev, 0); | |
3242 | if (irq > 0) | |
3243 | goto out; | |
3244 | ||
3245 | if (irq != -EPROBE_DEFER) | |
3246 | dev_err(dwc->dev, "missing peripheral IRQ\n"); | |
3247 | ||
3248 | if (!irq) | |
3249 | irq = -EINVAL; | |
3250 | ||
3251 | out: | |
3252 | return irq; | |
3253 | } | |
3254 | ||
72246da4 | 3255 | /** |
bfad65ee | 3256 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3257 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3258 | * |
3259 | * Returns 0 on success otherwise negative errno. | |
3260 | */ | |
41ac7b3a | 3261 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3262 | { |
6db3812e FB |
3263 | int ret; |
3264 | int irq; | |
9522def4 | 3265 | |
6db3812e FB |
3266 | irq = dwc3_gadget_get_irq(dwc); |
3267 | if (irq < 0) { | |
3268 | ret = irq; | |
3269 | goto err0; | |
9522def4 RQ |
3270 | } |
3271 | ||
3272 | dwc->irq_gadget = irq; | |
72246da4 | 3273 | |
d64ff406 AB |
3274 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3275 | sizeof(*dwc->ep0_trb) * 2, | |
3276 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3277 | if (!dwc->ep0_trb) { |
3278 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3279 | ret = -ENOMEM; | |
7d5e650a | 3280 | goto err0; |
72246da4 FB |
3281 | } |
3282 | ||
4199c5f8 | 3283 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3284 | if (!dwc->setup_buf) { |
72246da4 | 3285 | ret = -ENOMEM; |
7d5e650a | 3286 | goto err1; |
72246da4 FB |
3287 | } |
3288 | ||
905dc04e FB |
3289 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3290 | &dwc->bounce_addr, GFP_KERNEL); | |
3291 | if (!dwc->bounce) { | |
3292 | ret = -ENOMEM; | |
d6e5a549 | 3293 | goto err2; |
905dc04e FB |
3294 | } |
3295 | ||
bb014736 BW |
3296 | init_completion(&dwc->ep0_in_setup); |
3297 | ||
72246da4 | 3298 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3299 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3300 | dwc->gadget.sg_supported = true; |
72246da4 | 3301 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 3302 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 3303 | |
b9e51b2b BM |
3304 | /* |
3305 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3306 | * <2.20a of dwc3 have an issue with metastability (documented | |
3307 | * elsewhere in this driver) which tells us we can't set max speed to | |
3308 | * anything lower than SUPER. | |
3309 | * | |
3310 | * Because gadget.max_speed is only used by composite.c and function | |
3311 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3312 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3313 | * together with our BOS descriptor as that could confuse host into | |
3314 | * thinking we can handle super speed. | |
3315 | * | |
3316 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3317 | * is less than super speed because we don't have means, yet, to tell | |
3318 | * composite.c that we are USB 2.0 + LPM ECN. | |
3319 | */ | |
42bf02ec RQ |
3320 | if (dwc->revision < DWC3_REVISION_220A && |
3321 | !dwc->dis_metastability_quirk) | |
5eb30ced | 3322 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3323 | dwc->revision); |
3324 | ||
3325 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3326 | ||
72246da4 FB |
3327 | /* |
3328 | * REVISIT: Here we should clear all pending IRQs to be | |
3329 | * sure we're starting from a well known location. | |
3330 | */ | |
3331 | ||
f3bcfc7e | 3332 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 3333 | if (ret) |
d6e5a549 | 3334 | goto err3; |
72246da4 | 3335 | |
72246da4 FB |
3336 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3337 | if (ret) { | |
3338 | dev_err(dwc->dev, "failed to register udc\n"); | |
d6e5a549 | 3339 | goto err4; |
72246da4 FB |
3340 | } |
3341 | ||
3342 | return 0; | |
3343 | ||
7d5e650a | 3344 | err4: |
d6e5a549 | 3345 | dwc3_gadget_free_endpoints(dwc); |
04c03d10 | 3346 | |
7d5e650a | 3347 | err3: |
d6e5a549 FB |
3348 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
3349 | dwc->bounce_addr); | |
5812b1c2 | 3350 | |
7d5e650a | 3351 | err2: |
0fc9a1be | 3352 | kfree(dwc->setup_buf); |
72246da4 | 3353 | |
7d5e650a | 3354 | err1: |
d64ff406 | 3355 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3356 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3357 | ||
72246da4 FB |
3358 | err0: |
3359 | return ret; | |
3360 | } | |
3361 | ||
7415f17c FB |
3362 | /* -------------------------------------------------------------------------- */ |
3363 | ||
72246da4 FB |
3364 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3365 | { | |
72246da4 | 3366 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3367 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 3368 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 3369 | dwc->bounce_addr); |
0fc9a1be | 3370 | kfree(dwc->setup_buf); |
d64ff406 | 3371 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 3372 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 3373 | } |
7415f17c | 3374 | |
0b0231aa | 3375 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3376 | { |
9772b47a RQ |
3377 | if (!dwc->gadget_driver) |
3378 | return 0; | |
3379 | ||
1551e35e | 3380 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
3381 | dwc3_disconnect_gadget(dwc); |
3382 | __dwc3_gadget_stop(dwc); | |
7415f17c | 3383 | |
01c10880 BH |
3384 | synchronize_irq(dwc->irq_gadget); |
3385 | ||
7415f17c FB |
3386 | return 0; |
3387 | } | |
3388 | ||
3389 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3390 | { | |
7415f17c FB |
3391 | int ret; |
3392 | ||
9772b47a RQ |
3393 | if (!dwc->gadget_driver) |
3394 | return 0; | |
3395 | ||
9f8a67b6 FB |
3396 | ret = __dwc3_gadget_start(dwc); |
3397 | if (ret < 0) | |
7415f17c FB |
3398 | goto err0; |
3399 | ||
9f8a67b6 FB |
3400 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3401 | if (ret < 0) | |
7415f17c FB |
3402 | goto err1; |
3403 | ||
7415f17c FB |
3404 | return 0; |
3405 | ||
3406 | err1: | |
9f8a67b6 | 3407 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3408 | |
3409 | err0: | |
3410 | return ret; | |
3411 | } | |
fc8bb91b FB |
3412 | |
3413 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3414 | { | |
3415 | if (dwc->pending_events) { | |
3416 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3417 | dwc->pending_events = false; | |
3418 | enable_irq(dwc->irq_gadget); | |
3419 | } | |
3420 | } |