]>
Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
bfad65ee | 2 | /* |
72246da4 FB |
3 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
4 | * | |
10623b87 | 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
72246da4 FB |
6 | * |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
72246da4 FB |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | ||
22 | #include <linux/usb/ch9.h> | |
23 | #include <linux/usb/gadget.h> | |
24 | ||
80977dc9 | 25 | #include "debug.h" |
72246da4 FB |
26 | #include "core.h" |
27 | #include "gadget.h" | |
28 | #include "io.h" | |
29 | ||
d5370106 | 30 | #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ |
f62afb49 FB |
31 | & ~((d)->interval - 1)) |
32 | ||
04a9bfcd | 33 | /** |
bfad65ee | 34 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
35 | * @dwc: pointer to our context structure |
36 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
37 | * | |
bfad65ee FB |
38 | * Caller should take care of locking. This function will return 0 on |
39 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
40 | */ |
41 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
42 | { | |
43 | u32 reg; | |
44 | ||
45 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
46 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
47 | ||
48 | switch (mode) { | |
62fb45d3 GKH |
49 | case USB_TEST_J: |
50 | case USB_TEST_K: | |
51 | case USB_TEST_SE0_NAK: | |
52 | case USB_TEST_PACKET: | |
53 | case USB_TEST_FORCE_ENABLE: | |
04a9bfcd FB |
54 | reg |= mode << 1; |
55 | break; | |
56 | default: | |
57 | return -EINVAL; | |
58 | } | |
59 | ||
5b738211 | 60 | dwc3_gadget_dctl_write_safe(dwc, reg); |
04a9bfcd FB |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
911f1f88 | 65 | /** |
bfad65ee | 66 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
67 | * @dwc: pointer to our context structure |
68 | * | |
69 | * Caller should take care of locking. This function will | |
70 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
71 | */ | |
72 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
73 | { | |
74 | u32 reg; | |
75 | ||
76 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
77 | ||
78 | return DWC3_DSTS_USBLNKST(reg); | |
79 | } | |
80 | ||
8598bde7 | 81 | /** |
bfad65ee | 82 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
83 | * @dwc: pointer to our context structure |
84 | * @state: the state to put link into | |
85 | * | |
86 | * Caller should take care of locking. This function will | |
aee63e3c | 87 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
88 | */ |
89 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
90 | { | |
aee63e3c | 91 | int retries = 10000; |
8598bde7 FB |
92 | u32 reg; |
93 | ||
802fde98 PZ |
94 | /* |
95 | * Wait until device controller is ready. Only applies to 1.94a and | |
96 | * later RTL. | |
97 | */ | |
9af21dd6 | 98 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 PZ |
99 | while (--retries) { |
100 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
101 | if (reg & DWC3_DSTS_DCNRD) | |
102 | udelay(5); | |
103 | else | |
104 | break; | |
105 | } | |
106 | ||
107 | if (retries <= 0) | |
108 | return -ETIMEDOUT; | |
109 | } | |
110 | ||
8598bde7 FB |
111 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
112 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
113 | ||
2e708fa3 TN |
114 | /* set no action before sending new link state change */ |
115 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
116 | ||
8598bde7 FB |
117 | /* set requested state */ |
118 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
119 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
120 | ||
802fde98 PZ |
121 | /* |
122 | * The following code is racy when called from dwc3_gadget_wakeup, | |
123 | * and is not needed, at least on newer versions | |
124 | */ | |
9af21dd6 | 125 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
126 | return 0; |
127 | ||
8598bde7 | 128 | /* wait for a change in DSTS */ |
aed430e5 | 129 | retries = 10000; |
8598bde7 FB |
130 | while (--retries) { |
131 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
132 | ||
8598bde7 FB |
133 | if (DWC3_DSTS_USBLNKST(reg) == state) |
134 | return 0; | |
135 | ||
aee63e3c | 136 | udelay(5); |
8598bde7 FB |
137 | } |
138 | ||
8598bde7 FB |
139 | return -ETIMEDOUT; |
140 | } | |
141 | ||
dca0119c | 142 | /** |
bfad65ee FB |
143 | * dwc3_ep_inc_trb - increment a trb index. |
144 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
145 | * |
146 | * The index should never point to the link TRB. After incrementing, | |
147 | * if it is point to the link TRB, wrap around to the beginning. The | |
148 | * link TRB is always at the last TRB entry. | |
149 | */ | |
150 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 151 | { |
dca0119c JY |
152 | (*index)++; |
153 | if (*index == (DWC3_TRB_NUM - 1)) | |
154 | *index = 0; | |
ef966b9d | 155 | } |
457e84b6 | 156 | |
bfad65ee FB |
157 | /** |
158 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
159 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
160 | */ | |
dca0119c | 161 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 162 | { |
dca0119c | 163 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 164 | } |
457e84b6 | 165 | |
bfad65ee FB |
166 | /** |
167 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
168 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
169 | */ | |
dca0119c | 170 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 171 | { |
dca0119c | 172 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
173 | } |
174 | ||
69102510 | 175 | static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, |
c91815b5 | 176 | struct dwc3_request *req, int status) |
72246da4 FB |
177 | { |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
72246da4 | 180 | list_del(&req->list); |
e62c5bc5 | 181 | req->remaining = 0; |
bd674224 | 182 | req->needs_extra_trb = false; |
72246da4 FB |
183 | |
184 | if (req->request.status == -EINPROGRESS) | |
185 | req->request.status = status; | |
186 | ||
4a71fcb8 JP |
187 | if (req->trb) |
188 | usb_gadget_unmap_request_by_dev(dwc->sysdev, | |
c91815b5 | 189 | &req->request, req->direction); |
4a71fcb8 JP |
190 | |
191 | req->trb = NULL; | |
2c4cbe6e | 192 | trace_dwc3_gadget_giveback(req); |
72246da4 | 193 | |
c91815b5 FB |
194 | if (dep->number > 1) |
195 | pm_runtime_put(dwc->dev); | |
196 | } | |
197 | ||
198 | /** | |
199 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
200 | * @dep: The endpoint to whom the request belongs to | |
201 | * @req: The request we're giving back | |
202 | * @status: completion code for the request | |
203 | * | |
204 | * Must be called with controller's lock held and interrupts disabled. This | |
205 | * function will unmap @req and call its ->complete() callback to notify upper | |
206 | * layers that it has completed. | |
207 | */ | |
208 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, | |
209 | int status) | |
210 | { | |
211 | struct dwc3 *dwc = dep->dwc; | |
212 | ||
213 | dwc3_gadget_del_and_unmap_request(dep, req, status); | |
a3af5e3a | 214 | req->status = DWC3_REQUEST_STATUS_COMPLETED; |
c91815b5 | 215 | |
72246da4 | 216 | spin_unlock(&dwc->lock); |
304f7e5e | 217 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
218 | spin_lock(&dwc->lock); |
219 | } | |
220 | ||
bfad65ee FB |
221 | /** |
222 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
223 | * @dwc: pointer to the controller context | |
224 | * @cmd: the command to be issued | |
225 | * @param: command parameter | |
226 | * | |
227 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
228 | * and wait for its completion. | |
229 | */ | |
e319bd62 FB |
230 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, |
231 | u32 param) | |
b09bb642 FB |
232 | { |
233 | u32 timeout = 500; | |
71f7e702 | 234 | int status = 0; |
0fe886cd | 235 | int ret = 0; |
b09bb642 FB |
236 | u32 reg; |
237 | ||
238 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
239 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
240 | ||
241 | do { | |
242 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
243 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
244 | status = DWC3_DGCMD_STATUS(reg); |
245 | if (status) | |
0fe886cd FB |
246 | ret = -EINVAL; |
247 | break; | |
b09bb642 | 248 | } |
e3aee486 | 249 | } while (--timeout); |
0fe886cd FB |
250 | |
251 | if (!timeout) { | |
0fe886cd | 252 | ret = -ETIMEDOUT; |
71f7e702 | 253 | status = -ETIMEDOUT; |
0fe886cd FB |
254 | } |
255 | ||
71f7e702 FB |
256 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
257 | ||
0fe886cd | 258 | return ret; |
b09bb642 FB |
259 | } |
260 | ||
c36d8e94 FB |
261 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
262 | ||
bfad65ee FB |
263 | /** |
264 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
265 | * @dep: the endpoint to which the command is going to be issued | |
266 | * @cmd: the command to be issued | |
267 | * @params: parameters to the command | |
268 | * | |
269 | * Caller should handle locking. This function will issue @cmd with given | |
270 | * @params to @dep and wait for its completion. | |
271 | */ | |
e319bd62 | 272 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, |
2cd4718d | 273 | struct dwc3_gadget_ep_cmd_params *params) |
72246da4 | 274 | { |
8897a761 | 275 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 276 | struct dwc3 *dwc = dep->dwc; |
1c0e69ae | 277 | u32 timeout = 5000; |
87dd9611 | 278 | u32 saved_config = 0; |
72246da4 FB |
279 | u32 reg; |
280 | ||
0933df15 | 281 | int cmd_status = 0; |
c0ca324d | 282 | int ret = -EINVAL; |
72246da4 | 283 | |
2b0f11df | 284 | /* |
87dd9611 TN |
285 | * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or |
286 | * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an | |
287 | * endpoint command. | |
2b0f11df | 288 | * |
87dd9611 TN |
289 | * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY |
290 | * settings. Restore them after the command is completed. | |
291 | * | |
292 | * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 | |
2b0f11df | 293 | */ |
76ed3ae7 TN |
294 | if (dwc->gadget->speed <= USB_SPEED_HIGH || |
295 | DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) { | |
ab2a92e7 FB |
296 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
297 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
87dd9611 | 298 | saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 299 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; |
ab2a92e7 | 300 | } |
87dd9611 TN |
301 | |
302 | if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { | |
303 | saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; | |
304 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
305 | } | |
306 | ||
307 | if (saved_config) | |
308 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
2b0f11df FB |
309 | } |
310 | ||
5999914f | 311 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c560e763 | 312 | int link_state; |
c36d8e94 | 313 | |
d3d1d6a1 TN |
314 | /* |
315 | * Initiate remote wakeup if the link state is in U3 when | |
316 | * operating in SS/SSP or L1/L2 when operating in HS/FS. If the | |
317 | * link state is in U1/U2, no remote wakeup is needed. The Start | |
318 | * Transfer command will initiate the link recovery. | |
319 | */ | |
c560e763 | 320 | link_state = dwc3_gadget_get_link_state(dwc); |
d3d1d6a1 TN |
321 | switch (link_state) { |
322 | case DWC3_LINK_STATE_U2: | |
323 | if (dwc->gadget->speed >= USB_SPEED_SUPER) | |
324 | break; | |
325 | ||
326 | fallthrough; | |
327 | case DWC3_LINK_STATE_U3: | |
c36d8e94 FB |
328 | ret = __dwc3_gadget_wakeup(dwc); |
329 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
330 | ret); | |
d3d1d6a1 | 331 | break; |
c36d8e94 FB |
332 | } |
333 | } | |
334 | ||
2eb88016 FB |
335 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
336 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
337 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 338 | |
8897a761 FB |
339 | /* |
340 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
341 | * not relying on XferNotReady, we can make use of a special "No | |
342 | * Response Update Transfer" command where we should clear both CmdAct | |
343 | * and CmdIOC bits. | |
344 | * | |
345 | * With this, we don't need to wait for command completion and can | |
346 | * straight away issue further commands to the endpoint. | |
347 | * | |
348 | * NOTICE: We're making an assumption that control endpoints will never | |
349 | * make use of Update Transfer command. This is a safe assumption | |
350 | * because we can never have more than one request at a time with | |
351 | * Control Endpoints. If anybody changes that assumption, this chunk | |
352 | * needs to be updated accordingly. | |
353 | */ | |
354 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
355 | !usb_endpoint_xfer_isoc(desc)) | |
356 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
357 | else | |
358 | cmd |= DWC3_DEPCMD_CMDACT; | |
359 | ||
360 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 361 | do { |
2eb88016 | 362 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 363 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 364 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 365 | |
7b9cc7a2 KL |
366 | switch (cmd_status) { |
367 | case 0: | |
368 | ret = 0; | |
369 | break; | |
370 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
f7ac582e TN |
371 | dev_WARN(dwc->dev, "No resource for %s\n", |
372 | dep->name); | |
7b9cc7a2 | 373 | ret = -EINVAL; |
c0ca324d | 374 | break; |
7b9cc7a2 KL |
375 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
376 | /* | |
377 | * SW issues START TRANSFER command to | |
378 | * isochronous ep with future frame interval. If | |
379 | * future interval time has already passed when | |
380 | * core receives the command, it will respond | |
381 | * with an error status of 'Bus Expiry'. | |
382 | * | |
383 | * Instead of always returning -EINVAL, let's | |
384 | * give a hint to the gadget driver that this is | |
385 | * the case by returning -EAGAIN. | |
386 | */ | |
7b9cc7a2 KL |
387 | ret = -EAGAIN; |
388 | break; | |
389 | default: | |
390 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
391 | } | |
392 | ||
c0ca324d | 393 | break; |
72246da4 | 394 | } |
f6bb225b | 395 | } while (--timeout); |
72246da4 | 396 | |
f6bb225b | 397 | if (timeout == 0) { |
f6bb225b | 398 | ret = -ETIMEDOUT; |
0933df15 | 399 | cmd_status = -ETIMEDOUT; |
f6bb225b | 400 | } |
c0ca324d | 401 | |
0933df15 FB |
402 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
403 | ||
9bc3395c TN |
404 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
405 | if (ret == 0) | |
406 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
407 | ||
408 | if (ret != -ETIMEDOUT) | |
409 | dwc3_gadget_ep_get_transfer_index(dep); | |
6cb2e4e3 FB |
410 | } |
411 | ||
87dd9611 | 412 | if (saved_config) { |
2b0f11df | 413 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
87dd9611 | 414 | reg |= saved_config; |
2b0f11df FB |
415 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
416 | } | |
417 | ||
c0ca324d | 418 | return ret; |
72246da4 FB |
419 | } |
420 | ||
50c763f8 JY |
421 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
422 | { | |
423 | struct dwc3 *dwc = dep->dwc; | |
424 | struct dwc3_gadget_ep_cmd_params params; | |
425 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
426 | ||
427 | /* | |
428 | * As of core revision 2.60a the recommended programming model | |
429 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
430 | * command for IN endpoints. This is to prevent an issue where | |
431 | * some (non-compliant) hosts may not send ACK TPs for pending | |
432 | * IN transfers due to a mishandled error condition. Synopsys | |
433 | * STAR 9000614252. | |
434 | */ | |
9af21dd6 TN |
435 | if (dep->direction && |
436 | !DWC3_VER_IS_PRIOR(DWC3, 260A) && | |
e81a7018 | 437 | (dwc->gadget->speed >= USB_SPEED_SUPER)) |
50c763f8 JY |
438 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
439 | ||
440 | memset(¶ms, 0, sizeof(params)); | |
441 | ||
2cd4718d | 442 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
443 | } |
444 | ||
72246da4 | 445 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 446 | struct dwc3_trb *trb) |
72246da4 | 447 | { |
c439ef87 | 448 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
449 | |
450 | return dep->trb_pool_dma + offset; | |
451 | } | |
452 | ||
453 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
454 | { | |
455 | struct dwc3 *dwc = dep->dwc; | |
456 | ||
457 | if (dep->trb_pool) | |
458 | return 0; | |
459 | ||
d64ff406 | 460 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
461 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
462 | &dep->trb_pool_dma, GFP_KERNEL); | |
463 | if (!dep->trb_pool) { | |
464 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
465 | dep->name); | |
466 | return -ENOMEM; | |
467 | } | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
472 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
473 | { | |
474 | struct dwc3 *dwc = dep->dwc; | |
475 | ||
d64ff406 | 476 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
477 | dep->trb_pool, dep->trb_pool_dma); |
478 | ||
479 | dep->trb_pool = NULL; | |
480 | dep->trb_pool_dma = 0; | |
481 | } | |
482 | ||
20d1d43f FB |
483 | static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) |
484 | { | |
485 | struct dwc3_gadget_ep_cmd_params params; | |
486 | ||
487 | memset(¶ms, 0x00, sizeof(params)); | |
488 | ||
489 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); | |
490 | ||
491 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, | |
492 | ¶ms); | |
493 | } | |
c4509601 JY |
494 | |
495 | /** | |
bfad65ee | 496 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
497 | * @dep: endpoint that is being enabled |
498 | * | |
bfad65ee FB |
499 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
500 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 501 | * |
bfad65ee FB |
502 | * The assignment of transfer resources cannot perfectly follow the data book |
503 | * due to the fact that the controller driver does not have all knowledge of the | |
504 | * configuration in advance. It is given this information piecemeal by the | |
505 | * composite gadget framework after every SET_CONFIGURATION and | |
506 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
507 | * scenario can cause errors. For two reasons: | |
c4509601 | 508 | * |
bfad65ee FB |
509 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
510 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
511 | * incorrect in the scenario of multiple interfaces. | |
512 | * | |
513 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
514 | * endpoint on alt setting (8.1.6). |
515 | * | |
516 | * The following simplified method is used instead: | |
517 | * | |
bfad65ee FB |
518 | * All hardware endpoints can be assigned a transfer resource and this setting |
519 | * will stay persistent until either a core reset or hibernation. So whenever we | |
520 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
521 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
522 | * guaranteed that there are as many transfer resources as endpoints. |
523 | * | |
bfad65ee FB |
524 | * This function is called for each endpoint when it is being enabled but is |
525 | * triggered only when called for EP0-out, which always happens first, and which | |
526 | * should only happen in one of the above conditions. | |
c4509601 | 527 | */ |
b07c2db8 | 528 | static int dwc3_gadget_start_config(struct dwc3_ep *dep) |
72246da4 FB |
529 | { |
530 | struct dwc3_gadget_ep_cmd_params params; | |
b07c2db8 | 531 | struct dwc3 *dwc; |
72246da4 | 532 | u32 cmd; |
c4509601 JY |
533 | int i; |
534 | int ret; | |
535 | ||
536 | if (dep->number) | |
537 | return 0; | |
72246da4 FB |
538 | |
539 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 540 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
b07c2db8 | 541 | dwc = dep->dwc; |
72246da4 | 542 | |
2cd4718d | 543 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
544 | if (ret) |
545 | return ret; | |
546 | ||
547 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
548 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 549 | |
c4509601 JY |
550 | if (!dep) |
551 | continue; | |
552 | ||
b07c2db8 | 553 | ret = dwc3_gadget_set_xfer_resource(dep); |
c4509601 JY |
554 | if (ret) |
555 | return ret; | |
72246da4 FB |
556 | } |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
b07c2db8 | 561 | static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 562 | { |
39ebb05c JY |
563 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
564 | const struct usb_endpoint_descriptor *desc; | |
72246da4 | 565 | struct dwc3_gadget_ep_cmd_params params; |
b07c2db8 | 566 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 567 | |
39ebb05c JY |
568 | comp_desc = dep->endpoint.comp_desc; |
569 | desc = dep->endpoint.desc; | |
570 | ||
72246da4 FB |
571 | memset(¶ms, 0x00, sizeof(params)); |
572 | ||
dc1c70a7 | 573 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
574 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
575 | ||
576 | /* Burst size is only needed in SuperSpeed mode */ | |
e81a7018 | 577 | if (dwc->gadget->speed >= USB_SPEED_SUPER) { |
676e3497 | 578 | u32 burst = dep->endpoint.maxburst; |
e319bd62 | 579 | |
676e3497 | 580 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 581 | } |
72246da4 | 582 | |
a2d23f08 FB |
583 | params.param0 |= action; |
584 | if (action == DWC3_DEPCFG_ACTION_RESTORE) | |
265b70a7 | 585 | params.param2 |= dep->saved_state; |
265b70a7 | 586 | |
4bc48c97 FB |
587 | if (usb_endpoint_xfer_control(desc)) |
588 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
589 | |
590 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
591 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 592 | |
18b7ede5 | 593 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 | 594 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
548f8b31 | 595 | | DWC3_DEPCFG_XFER_COMPLETE_EN |
dc1c70a7 | 596 | | DWC3_DEPCFG_STREAM_EVENT_EN; |
879631aa FB |
597 | dep->stream_capable = true; |
598 | } | |
599 | ||
0b93a4c8 | 600 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 601 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
602 | |
603 | /* | |
604 | * We are doing 1:1 mapping for endpoints, meaning | |
605 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
606 | * so on. We consider the direction bit as part of the physical | |
607 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
608 | */ | |
dc1c70a7 | 609 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
610 | |
611 | /* | |
612 | * We must use the lower 16 TX FIFOs even though | |
613 | * HW might have more | |
614 | */ | |
615 | if (dep->direction) | |
dc1c70a7 | 616 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
617 | |
618 | if (desc->bInterval) { | |
a1679af8 TN |
619 | u8 bInterval_m1; |
620 | ||
621 | /* | |
3232a3ce TN |
622 | * Valid range for DEPCFG.bInterval_m1 is from 0 to 13. |
623 | * | |
624 | * NOTE: The programming guide incorrectly stated bInterval_m1 | |
625 | * must be set to 0 when operating in fullspeed. Internally the | |
626 | * controller does not have this limitation. See DWC_usb3x | |
627 | * programming guide section 3.2.2.1. | |
a1679af8 TN |
628 | */ |
629 | bInterval_m1 = min_t(u8, desc->bInterval - 1, 13); | |
a1679af8 | 630 | |
4b049f55 TN |
631 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT && |
632 | dwc->gadget->speed == USB_SPEED_FULL) | |
633 | dep->interval = desc->bInterval; | |
634 | else | |
635 | dep->interval = 1 << (desc->bInterval - 1); | |
636 | ||
a1679af8 | 637 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1); |
72246da4 FB |
638 | } |
639 | ||
2cd4718d | 640 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
641 | } |
642 | ||
140ca4cf TN |
643 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
644 | bool interrupt); | |
645 | ||
9f607a30 WC |
646 | /** |
647 | * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value | |
648 | * @dwc: pointer to the DWC3 context | |
649 | * @nfifos: number of fifos to calculate for | |
650 | * | |
651 | * Calculates the size value based on the equation below: | |
652 | * | |
653 | * DWC3 revision 280A and prior: | |
654 | * fifo_size = mult * (max_packet / mdwidth) + 1; | |
655 | * | |
656 | * DWC3 revision 290A and onwards: | |
657 | * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 | |
658 | * | |
659 | * The max packet size is set to 1024, as the txfifo requirements mainly apply | |
660 | * to super speed USB use cases. However, it is safe to overestimate the fifo | |
661 | * allocations for other scenarios, i.e. high speed USB. | |
662 | */ | |
663 | static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult) | |
664 | { | |
665 | int max_packet = 1024; | |
666 | int fifo_size; | |
667 | int mdwidth; | |
668 | ||
669 | mdwidth = dwc3_mdwidth(dwc); | |
670 | ||
671 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
672 | mdwidth >>= 3; | |
673 | ||
674 | if (DWC3_VER_IS_PRIOR(DWC3, 290A)) | |
675 | fifo_size = mult * (max_packet / mdwidth) + 1; | |
676 | else | |
677 | fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1; | |
678 | return fifo_size; | |
679 | } | |
680 | ||
681 | /** | |
682 | * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation | |
683 | * @dwc: pointer to the DWC3 context | |
684 | * | |
685 | * Iterates through all the endpoint registers and clears the previous txfifo | |
686 | * allocations. | |
687 | */ | |
688 | void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) | |
689 | { | |
690 | struct dwc3_ep *dep; | |
691 | int fifo_depth; | |
692 | int size; | |
693 | int num; | |
694 | ||
695 | if (!dwc->do_fifo_resize) | |
696 | return; | |
697 | ||
698 | /* Read ep0IN related TXFIFO size */ | |
699 | dep = dwc->eps[1]; | |
700 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); | |
701 | if (DWC3_IP_IS(DWC3)) | |
702 | fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size); | |
703 | else | |
704 | fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
705 | ||
706 | dwc->last_fifo_depth = fifo_depth; | |
707 | /* Clear existing TXFIFO for all IN eps except ep0 */ | |
708 | for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM); | |
709 | num += 2) { | |
710 | dep = dwc->eps[num]; | |
711 | /* Don't change TXFRAMNUM on usb31 version */ | |
712 | size = DWC3_IP_IS(DWC3) ? 0 : | |
713 | dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) & | |
714 | DWC31_GTXFIFOSIZ_TXFRAMNUM; | |
715 | ||
716 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size); | |
c967d090 | 717 | dep->flags &= ~DWC3_EP_TXFIFO_RESIZED; |
9f607a30 WC |
718 | } |
719 | dwc->num_ep_resized = 0; | |
720 | } | |
721 | ||
722 | /* | |
723 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
724 | * @dwc: pointer to our context structure | |
725 | * | |
726 | * This function will a best effort FIFO allocation in order | |
727 | * to improve FIFO usage and throughput, while still allowing | |
728 | * us to enable as many endpoints as possible. | |
729 | * | |
730 | * Keep in mind that this operation will be highly dependent | |
731 | * on the configured size for RAM1 - which contains TxFifo -, | |
732 | * the amount of endpoints enabled on coreConsultant tool, and | |
733 | * the width of the Master Bus. | |
734 | * | |
735 | * In general, FIFO depths are represented with the following equation: | |
736 | * | |
737 | * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 | |
738 | * | |
739 | * In conjunction with dwc3_gadget_check_config(), this resizing logic will | |
740 | * ensure that all endpoints will have enough internal memory for one max | |
741 | * packet per endpoint. | |
742 | */ | |
743 | static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep) | |
744 | { | |
745 | struct dwc3 *dwc = dep->dwc; | |
746 | int fifo_0_start; | |
747 | int ram1_depth; | |
748 | int fifo_size; | |
749 | int min_depth; | |
750 | int num_in_ep; | |
751 | int remaining; | |
752 | int num_fifos = 1; | |
753 | int fifo; | |
754 | int tmp; | |
755 | ||
756 | if (!dwc->do_fifo_resize) | |
757 | return 0; | |
758 | ||
759 | /* resize IN endpoints except ep0 */ | |
760 | if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1) | |
761 | return 0; | |
762 | ||
c967d090 JP |
763 | /* bail if already resized */ |
764 | if (dep->flags & DWC3_EP_TXFIFO_RESIZED) | |
765 | return 0; | |
766 | ||
9f607a30 WC |
767 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); |
768 | ||
769 | if ((dep->endpoint.maxburst > 1 && | |
770 | usb_endpoint_xfer_bulk(dep->endpoint.desc)) || | |
771 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
772 | num_fifos = 3; | |
773 | ||
774 | if (dep->endpoint.maxburst > 6 && | |
775 | usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31)) | |
776 | num_fifos = dwc->tx_fifo_resize_max_num; | |
777 | ||
778 | /* FIFO size for a single buffer */ | |
779 | fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1); | |
780 | ||
781 | /* Calculate the number of remaining EPs w/o any FIFO */ | |
782 | num_in_ep = dwc->max_cfg_eps; | |
783 | num_in_ep -= dwc->num_ep_resized; | |
784 | ||
785 | /* Reserve at least one FIFO for the number of IN EPs */ | |
786 | min_depth = num_in_ep * (fifo + 1); | |
787 | remaining = ram1_depth - min_depth - dwc->last_fifo_depth; | |
788 | remaining = max_t(int, 0, remaining); | |
789 | /* | |
790 | * We've already reserved 1 FIFO per EP, so check what we can fit in | |
791 | * addition to it. If there is not enough remaining space, allocate | |
792 | * all the remaining space to the EP. | |
793 | */ | |
794 | fifo_size = (num_fifos - 1) * fifo; | |
795 | if (remaining < fifo_size) | |
796 | fifo_size = remaining; | |
797 | ||
798 | fifo_size += fifo; | |
799 | /* Last increment according to the TX FIFO size equation */ | |
800 | fifo_size++; | |
801 | ||
802 | /* Check if TXFIFOs start at non-zero addr */ | |
803 | tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); | |
804 | fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp); | |
805 | ||
806 | fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16)); | |
807 | if (DWC3_IP_IS(DWC3)) | |
808 | dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size); | |
809 | else | |
810 | dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size); | |
811 | ||
812 | /* Check fifo size allocation doesn't exceed available RAM size. */ | |
813 | if (dwc->last_fifo_depth >= ram1_depth) { | |
814 | dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n", | |
815 | dwc->last_fifo_depth, ram1_depth, | |
816 | dep->endpoint.name, fifo_size); | |
817 | if (DWC3_IP_IS(DWC3)) | |
818 | fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size); | |
819 | else | |
820 | fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size); | |
821 | ||
822 | dwc->last_fifo_depth -= fifo_size; | |
823 | return -ENOMEM; | |
824 | } | |
825 | ||
826 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size); | |
c967d090 | 827 | dep->flags |= DWC3_EP_TXFIFO_RESIZED; |
9f607a30 WC |
828 | dwc->num_ep_resized++; |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
72246da4 | 833 | /** |
bfad65ee | 834 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 835 | * @dep: endpoint to be initialized |
a2d23f08 | 836 | * @action: one of INIT, MODIFY or RESTORE |
72246da4 | 837 | * |
bfad65ee FB |
838 | * Caller should take care of locking. Execute all necessary commands to |
839 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 | 840 | */ |
a2d23f08 | 841 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) |
72246da4 | 842 | { |
39ebb05c | 843 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 844 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 845 | |
72246da4 | 846 | u32 reg; |
b09e99ee | 847 | int ret; |
72246da4 FB |
848 | |
849 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
9f607a30 WC |
850 | ret = dwc3_gadget_resize_tx_fifos(dep); |
851 | if (ret) | |
852 | return ret; | |
853 | ||
b07c2db8 | 854 | ret = dwc3_gadget_start_config(dep); |
72246da4 FB |
855 | if (ret) |
856 | return ret; | |
857 | } | |
858 | ||
b07c2db8 | 859 | ret = dwc3_gadget_set_ep_config(dep, action); |
72246da4 FB |
860 | if (ret) |
861 | return ret; | |
862 | ||
863 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
864 | struct dwc3_trb *trb_st_hw; |
865 | struct dwc3_trb *trb_link; | |
72246da4 | 866 | |
72246da4 FB |
867 | dep->type = usb_endpoint_type(desc); |
868 | dep->flags |= DWC3_EP_ENABLED; | |
869 | ||
870 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
871 | reg |= DWC3_DALEPENA_EP(dep->number); | |
872 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
873 | ||
36b68aae | 874 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 875 | goto out; |
72246da4 | 876 | |
0d25744a JY |
877 | /* Initialize the TRB ring */ |
878 | dep->trb_dequeue = 0; | |
879 | dep->trb_enqueue = 0; | |
880 | memset(dep->trb_pool, 0, | |
881 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
882 | ||
36b68aae | 883 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
884 | trb_st_hw = &dep->trb_pool[0]; |
885 | ||
f6bafc6a | 886 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
887 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
888 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
889 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
890 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
891 | } |
892 | ||
a97ea994 FB |
893 | /* |
894 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
895 | * Response Update Transfer command. | |
896 | */ | |
140ca4cf | 897 | if (usb_endpoint_xfer_bulk(desc) || |
52fcc0be | 898 | usb_endpoint_xfer_int(desc)) { |
a97ea994 FB |
899 | struct dwc3_gadget_ep_cmd_params params; |
900 | struct dwc3_trb *trb; | |
901 | dma_addr_t trb_dma; | |
902 | u32 cmd; | |
903 | ||
904 | memset(¶ms, 0, sizeof(params)); | |
905 | trb = &dep->trb_pool[0]; | |
906 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
907 | ||
908 | params.param0 = upper_32_bits(trb_dma); | |
909 | params.param1 = lower_32_bits(trb_dma); | |
910 | ||
911 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
912 | ||
913 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
914 | if (ret < 0) | |
915 | return ret; | |
140ca4cf TN |
916 | |
917 | if (dep->stream_capable) { | |
918 | /* | |
919 | * For streams, at start, there maybe a race where the | |
920 | * host primes the endpoint before the function driver | |
921 | * queues a request to initiate a stream. In that case, | |
922 | * the controller will not see the prime to generate the | |
923 | * ERDY and start stream. To workaround this, issue a | |
924 | * no-op TRB as normal, but end it immediately. As a | |
925 | * result, when the function driver queues the request, | |
926 | * the next START_TRANSFER command will cause the | |
927 | * controller to generate an ERDY to initiate the | |
928 | * stream. | |
929 | */ | |
930 | dwc3_stop_active_transfer(dep, true, true); | |
931 | ||
932 | /* | |
933 | * All stream eps will reinitiate stream on NoStream | |
934 | * rejection until we can determine that the host can | |
935 | * prime after the first transfer. | |
ddae7979 TN |
936 | * |
937 | * However, if the controller is capable of | |
938 | * TXF_FLUSH_BYPASS, then IN direction endpoints will | |
939 | * automatically restart the stream without the driver | |
940 | * initiation. | |
140ca4cf | 941 | */ |
ddae7979 TN |
942 | if (!dep->direction || |
943 | !(dwc->hwparams.hwparams9 & | |
944 | DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS)) | |
945 | dep->flags |= DWC3_EP_FORCE_RESTART_STREAM; | |
140ca4cf | 946 | } |
a97ea994 FB |
947 | } |
948 | ||
2870e501 FB |
949 | out: |
950 | trace_dwc3_gadget_ep_enable(dep); | |
951 | ||
72246da4 FB |
952 | return 0; |
953 | } | |
954 | ||
20606c74 | 955 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status) |
72246da4 FB |
956 | { |
957 | struct dwc3_request *req; | |
958 | ||
c5353b22 | 959 | dwc3_stop_active_transfer(dep, true, false); |
624407f9 | 960 | |
0e146028 FB |
961 | /* - giveback all requests to gadget driver */ |
962 | while (!list_empty(&dep->started_list)) { | |
963 | req = next_request(&dep->started_list); | |
1591633e | 964 | |
20606c74 | 965 | dwc3_gadget_giveback(dep, req, status); |
ea53b882 FB |
966 | } |
967 | ||
aa3342c8 FB |
968 | while (!list_empty(&dep->pending_list)) { |
969 | req = next_request(&dep->pending_list); | |
72246da4 | 970 | |
20606c74 | 971 | dwc3_gadget_giveback(dep, req, status); |
d8eca64e FB |
972 | } |
973 | ||
974 | while (!list_empty(&dep->cancelled_list)) { | |
975 | req = next_request(&dep->cancelled_list); | |
976 | ||
20606c74 | 977 | dwc3_gadget_giveback(dep, req, status); |
72246da4 | 978 | } |
72246da4 FB |
979 | } |
980 | ||
981 | /** | |
bfad65ee | 982 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
983 | * @dep: the endpoint to disable |
984 | * | |
bfad65ee FB |
985 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
986 | * requests which are currently being processed by the hardware and those which | |
987 | * are not yet scheduled. | |
988 | * | |
624407f9 | 989 | * Caller should take care of locking. |
72246da4 | 990 | */ |
72246da4 FB |
991 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
992 | { | |
993 | struct dwc3 *dwc = dep->dwc; | |
994 | u32 reg; | |
995 | ||
2870e501 | 996 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 997 | |
687ef981 FB |
998 | /* make sure HW endpoint isn't stalled */ |
999 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 1000 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 1001 | |
72246da4 FB |
1002 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
1003 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
1004 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
1005 | ||
6376bf7e | 1006 | dwc3_remove_requests(dwc, dep, -ESHUTDOWN); |
f09ddcfc | 1007 | |
5aef6297 WC |
1008 | dep->stream_capable = false; |
1009 | dep->type = 0; | |
c967d090 | 1010 | dep->flags &= DWC3_EP_TXFIFO_RESIZED; |
5aef6297 | 1011 | |
b11bb703 TN |
1012 | /* Clear out the ep descriptors for non-ep0 */ |
1013 | if (dep->number > 1) { | |
1014 | dep->endpoint.comp_desc = NULL; | |
1015 | dep->endpoint.desc = NULL; | |
1016 | } | |
1017 | ||
72246da4 FB |
1018 | return 0; |
1019 | } | |
1020 | ||
1021 | /* -------------------------------------------------------------------------- */ | |
1022 | ||
1023 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
1024 | const struct usb_endpoint_descriptor *desc) | |
1025 | { | |
1026 | return -EINVAL; | |
1027 | } | |
1028 | ||
1029 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
1030 | { | |
1031 | return -EINVAL; | |
1032 | } | |
1033 | ||
1034 | /* -------------------------------------------------------------------------- */ | |
1035 | ||
1036 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
1037 | const struct usb_endpoint_descriptor *desc) | |
1038 | { | |
1039 | struct dwc3_ep *dep; | |
1040 | struct dwc3 *dwc; | |
1041 | unsigned long flags; | |
1042 | int ret; | |
1043 | ||
1044 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
1045 | pr_debug("dwc3: invalid parameters\n"); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
1049 | if (!desc->wMaxPacketSize) { | |
1050 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | dep = to_dwc3_ep(ep); | |
1055 | dwc = dep->dwc; | |
1056 | ||
95ca961c FB |
1057 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
1058 | "%s is already enabled\n", | |
1059 | dep->name)) | |
c6f83f38 | 1060 | return 0; |
c6f83f38 | 1061 | |
72246da4 | 1062 | spin_lock_irqsave(&dwc->lock, flags); |
a2d23f08 | 1063 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
1064 | spin_unlock_irqrestore(&dwc->lock, flags); |
1065 | ||
1066 | return ret; | |
1067 | } | |
1068 | ||
1069 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
1070 | { | |
1071 | struct dwc3_ep *dep; | |
1072 | struct dwc3 *dwc; | |
1073 | unsigned long flags; | |
1074 | int ret; | |
1075 | ||
1076 | if (!ep) { | |
1077 | pr_debug("dwc3: invalid parameters\n"); | |
1078 | return -EINVAL; | |
1079 | } | |
1080 | ||
1081 | dep = to_dwc3_ep(ep); | |
1082 | dwc = dep->dwc; | |
1083 | ||
95ca961c FB |
1084 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
1085 | "%s is already disabled\n", | |
1086 | dep->name)) | |
72246da4 | 1087 | return 0; |
72246da4 | 1088 | |
72246da4 FB |
1089 | spin_lock_irqsave(&dwc->lock, flags); |
1090 | ret = __dwc3_gadget_ep_disable(dep); | |
1091 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1092 | ||
1093 | return ret; | |
1094 | } | |
1095 | ||
1096 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
0bd0f6d2 | 1097 | gfp_t gfp_flags) |
72246da4 FB |
1098 | { |
1099 | struct dwc3_request *req; | |
1100 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
1101 | |
1102 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 1103 | if (!req) |
72246da4 | 1104 | return NULL; |
72246da4 | 1105 | |
31a2f5a7 | 1106 | req->direction = dep->direction; |
72246da4 FB |
1107 | req->epnum = dep->number; |
1108 | req->dep = dep; | |
a3af5e3a | 1109 | req->status = DWC3_REQUEST_STATUS_UNKNOWN; |
72246da4 | 1110 | |
2c4cbe6e FB |
1111 | trace_dwc3_alloc_request(req); |
1112 | ||
72246da4 FB |
1113 | return &req->request; |
1114 | } | |
1115 | ||
1116 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
1117 | struct usb_request *request) | |
1118 | { | |
1119 | struct dwc3_request *req = to_dwc3_request(request); | |
1120 | ||
2c4cbe6e | 1121 | trace_dwc3_free_request(req); |
72246da4 FB |
1122 | kfree(req); |
1123 | } | |
1124 | ||
42626919 FB |
1125 | /** |
1126 | * dwc3_ep_prev_trb - returns the previous TRB in the ring | |
1127 | * @dep: The endpoint with the TRB ring | |
1128 | * @index: The index of the current TRB in the ring | |
1129 | * | |
1130 | * Returns the TRB prior to the one pointed to by the index. If the | |
1131 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
1132 | * the one just before that. | |
1133 | */ | |
1134 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
1135 | { | |
1136 | u8 tmp = index; | |
1137 | ||
1138 | if (!tmp) | |
1139 | tmp = DWC3_TRB_NUM - 1; | |
1140 | ||
1141 | return &dep->trb_pool[tmp - 1]; | |
1142 | } | |
1143 | ||
1144 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) | |
1145 | { | |
42626919 FB |
1146 | u8 trbs_left; |
1147 | ||
1148 | /* | |
51f1954a TN |
1149 | * If the enqueue & dequeue are equal then the TRB ring is either full |
1150 | * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs | |
1151 | * pending to be processed by the driver. | |
42626919 FB |
1152 | */ |
1153 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
51f1954a TN |
1154 | /* |
1155 | * If there is any request remained in the started_list at | |
1156 | * this point, that means there is no TRB available. | |
1157 | */ | |
1158 | if (!list_empty(&dep->started_list)) | |
42626919 FB |
1159 | return 0; |
1160 | ||
1161 | return DWC3_TRB_NUM - 1; | |
1162 | } | |
1163 | ||
1164 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; | |
1165 | trbs_left &= (DWC3_TRB_NUM - 1); | |
1166 | ||
1167 | if (dep->trb_dequeue < dep->trb_enqueue) | |
1168 | trbs_left--; | |
1169 | ||
1170 | return trbs_left; | |
1171 | } | |
2c78c029 | 1172 | |
117ac1a2 MG |
1173 | /** |
1174 | * dwc3_prepare_one_trb - setup one TRB from one request | |
1175 | * @dep: endpoint for which this request is prepared | |
1176 | * @req: dwc3_request pointer | |
1177 | * @trb_length: buffer size of the TRB | |
1178 | * @chain: should this TRB be chained to the next? | |
1179 | * @node: only for isochronous endpoints. First TRB needs different type. | |
1180 | * @use_bounce_buffer: set to use bounce buffer | |
1181 | * @must_interrupt: set to interrupt on TRB completion | |
1182 | */ | |
1183 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
1184 | struct dwc3_request *req, unsigned int trb_length, | |
1185 | unsigned int chain, unsigned int node, bool use_bounce_buffer, | |
1186 | bool must_interrupt) | |
c71fc37c | 1187 | { |
117ac1a2 MG |
1188 | struct dwc3_trb *trb; |
1189 | dma_addr_t dma; | |
1190 | unsigned int stream_id = req->request.stream_id; | |
1191 | unsigned int short_not_ok = req->request.short_not_ok; | |
1192 | unsigned int no_interrupt = req->request.no_interrupt; | |
1193 | unsigned int is_last = req->request.is_last; | |
6b9018d4 | 1194 | struct dwc3 *dwc = dep->dwc; |
e81a7018 | 1195 | struct usb_gadget *gadget = dwc->gadget; |
6b9018d4 | 1196 | enum usb_device_speed speed = gadget->speed; |
c71fc37c | 1197 | |
117ac1a2 MG |
1198 | if (use_bounce_buffer) |
1199 | dma = dep->dwc->bounce_addr; | |
1200 | else if (req->request.num_sgs > 0) | |
1201 | dma = sg_dma_address(req->start_sg); | |
1202 | else | |
1203 | dma = req->request.dma; | |
1204 | ||
1205 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1206 | ||
1207 | if (!req->trb) { | |
1208 | dwc3_gadget_move_started_request(req); | |
1209 | req->trb = trb; | |
1210 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
1211 | } | |
1212 | ||
1213 | req->num_trbs++; | |
1214 | ||
1215 | trb->size = DWC3_TRB_SIZE_LENGTH(trb_length); | |
f6bafc6a FB |
1216 | trb->bpl = lower_32_bits(dma); |
1217 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 1218 | |
16e78db7 | 1219 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 1220 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 1221 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
1222 | break; |
1223 | ||
1224 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 1225 | if (!node) { |
e5ba5ec8 | 1226 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 | 1227 | |
40d829fb MG |
1228 | /* |
1229 | * USB Specification 2.0 Section 5.9.2 states that: "If | |
1230 | * there is only a single transaction in the microframe, | |
1231 | * only a DATA0 data packet PID is used. If there are | |
1232 | * two transactions per microframe, DATA1 is used for | |
1233 | * the first transaction data packet and DATA0 is used | |
1234 | * for the second transaction data packet. If there are | |
1235 | * three transactions per microframe, DATA2 is used for | |
1236 | * the first transaction data packet, DATA1 is used for | |
1237 | * the second, and DATA0 is used for the third." | |
1238 | * | |
1239 | * IOW, we should satisfy the following cases: | |
1240 | * | |
1241 | * 1) length <= maxpacket | |
1242 | * - DATA0 | |
1243 | * | |
1244 | * 2) maxpacket < length <= (2 * maxpacket) | |
1245 | * - DATA1, DATA0 | |
1246 | * | |
1247 | * 3) (2 * maxpacket) < length <= (3 * maxpacket) | |
1248 | * - DATA2, DATA1, DATA0 | |
1249 | */ | |
6b9018d4 FB |
1250 | if (speed == USB_SPEED_HIGH) { |
1251 | struct usb_ep *ep = &dep->endpoint; | |
ec5bb87e | 1252 | unsigned int mult = 2; |
40d829fb MG |
1253 | unsigned int maxp = usb_endpoint_maxp(ep->desc); |
1254 | ||
01e5e5bc | 1255 | if (req->request.length <= (2 * maxp)) |
40d829fb MG |
1256 | mult--; |
1257 | ||
01e5e5bc | 1258 | if (req->request.length <= maxp) |
40d829fb MG |
1259 | mult--; |
1260 | ||
1261 | trb->size |= DWC3_TRB_SIZE_PCM1(mult); | |
6b9018d4 FB |
1262 | } |
1263 | } else { | |
e5ba5ec8 | 1264 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 1265 | } |
ca4d44ea | 1266 | |
1e98cc2a TN |
1267 | if (!no_interrupt && !chain) |
1268 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
1269 | break; |
1270 | ||
1271 | case USB_ENDPOINT_XFER_BULK: | |
1272 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 1273 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
1274 | break; |
1275 | default: | |
1276 | /* | |
1277 | * This is only possible with faulty memory because we | |
1278 | * checked it already :) | |
1279 | */ | |
0a695d4c FB |
1280 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
1281 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
1282 | } |
1283 | ||
244add8e TJ |
1284 | /* |
1285 | * Enable Continue on Short Packet | |
1286 | * when endpoint is not a stream capable | |
1287 | */ | |
c9508c8c | 1288 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
244add8e TJ |
1289 | if (!dep->stream_capable) |
1290 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 1291 | |
e49d3cf4 | 1292 | if (short_not_ok) |
c9508c8c FB |
1293 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
1294 | } | |
1295 | ||
8dbbe48c | 1296 | if ((!no_interrupt && !chain) || must_interrupt) |
c9508c8c | 1297 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 1298 | |
e5ba5ec8 PA |
1299 | if (chain) |
1300 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
3eaecd0c TN |
1301 | else if (dep->stream_capable && is_last) |
1302 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
e5ba5ec8 | 1303 | |
16e78db7 | 1304 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 1305 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 1306 | |
06058e45 UG |
1307 | /* |
1308 | * As per data book 4.2.3.2TRB Control Bit Rules section | |
1309 | * | |
1310 | * The controller autonomously checks the HWO field of a TRB to determine if the | |
1311 | * entire TRB is valid. Therefore, software must ensure that the rest of the TRB | |
1312 | * is valid before setting the HWO field to '1'. In most systems, this means that | |
1313 | * software must update the fourth DWORD of a TRB last. | |
1314 | * | |
1315 | * However there is a possibility of CPU re-ordering here which can cause | |
1316 | * controller to observe the HWO bit set prematurely. | |
1317 | * Add a write memory barrier to prevent CPU re-ordering. | |
1318 | */ | |
1319 | wmb(); | |
f6bafc6a | 1320 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e | 1321 | |
b7a4fbe2 AKV |
1322 | dwc3_ep_inc_enq(dep); |
1323 | ||
2c4cbe6e | 1324 | trace_dwc3_prepare_trb(dep, trb); |
c71fc37c FB |
1325 | } |
1326 | ||
f9cc581b TN |
1327 | static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req) |
1328 | { | |
1329 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1330 | unsigned int rem = req->request.length % maxp; | |
1331 | ||
1332 | if ((req->request.length && req->request.zero && !rem && | |
1333 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) || | |
1334 | (!req->direction && rem)) | |
1335 | return true; | |
1336 | ||
1337 | return false; | |
e49d3cf4 FB |
1338 | } |
1339 | ||
cb1b3997 TN |
1340 | /** |
1341 | * dwc3_prepare_last_sg - prepare TRBs for the last SG entry | |
1342 | * @dep: The endpoint that the request belongs to | |
1343 | * @req: The request to prepare | |
1344 | * @entry_length: The last SG entry size | |
1345 | * @node: Indicates whether this is not the first entry (for isoc only) | |
1346 | * | |
1347 | * Return the number of TRBs prepared. | |
1348 | */ | |
1349 | static int dwc3_prepare_last_sg(struct dwc3_ep *dep, | |
1350 | struct dwc3_request *req, unsigned int entry_length, | |
1351 | unsigned int node) | |
1352 | { | |
1353 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1354 | unsigned int rem = req->request.length % maxp; | |
1355 | unsigned int num_trbs = 1; | |
1356 | ||
f9cc581b | 1357 | if (dwc3_needs_extra_trb(dep, req)) |
cb1b3997 TN |
1358 | num_trbs++; |
1359 | ||
1360 | if (dwc3_calc_trbs_left(dep) < num_trbs) | |
1361 | return 0; | |
1362 | ||
1363 | req->needs_extra_trb = num_trbs > 1; | |
1364 | ||
1365 | /* Prepare a normal TRB */ | |
1366 | if (req->direction || req->request.length) | |
1367 | dwc3_prepare_one_trb(dep, req, entry_length, | |
f9cc581b | 1368 | req->needs_extra_trb, node, false, false); |
cb1b3997 TN |
1369 | |
1370 | /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */ | |
1371 | if ((!req->direction && !req->request.length) || req->needs_extra_trb) | |
1372 | dwc3_prepare_one_trb(dep, req, | |
1373 | req->direction ? 0 : maxp - rem, | |
f9cc581b | 1374 | false, 1, true, false); |
cb1b3997 TN |
1375 | |
1376 | return num_trbs; | |
1377 | } | |
1378 | ||
7f2958d9 | 1379 | static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep, |
7ae7df49 | 1380 | struct dwc3_request *req) |
5ee85d89 | 1381 | { |
a31e63b6 | 1382 | struct scatterlist *sg = req->start_sg; |
5ee85d89 | 1383 | struct scatterlist *s; |
5ee85d89 | 1384 | int i; |
5d187c04 | 1385 | unsigned int length = req->request.length; |
c96e6725 AKV |
1386 | unsigned int remaining = req->request.num_mapped_sgs |
1387 | - req->num_queued_sgs; | |
13111fcb | 1388 | unsigned int num_trbs = req->num_trbs; |
f9cc581b | 1389 | bool needs_extra_trb = dwc3_needs_extra_trb(dep, req); |
c96e6725 | 1390 | |
5d187c04 TN |
1391 | /* |
1392 | * If we resume preparing the request, then get the remaining length of | |
1393 | * the request and resume where we left off. | |
1394 | */ | |
1395 | for_each_sg(req->request.sg, s, req->num_queued_sgs, i) | |
1396 | length -= sg_dma_len(s); | |
1397 | ||
c96e6725 | 1398 | for_each_sg(sg, s, remaining, i) { |
8dbbe48c | 1399 | unsigned int num_trbs_left = dwc3_calc_trbs_left(dep); |
5d187c04 | 1400 | unsigned int trb_length; |
f9cc581b | 1401 | bool must_interrupt = false; |
cb1b3997 | 1402 | bool last_sg = false; |
5ee85d89 | 1403 | |
5d187c04 TN |
1404 | trb_length = min_t(unsigned int, length, sg_dma_len(s)); |
1405 | ||
1406 | length -= trb_length; | |
1407 | ||
dad2aff3 PP |
1408 | /* |
1409 | * IOMMU driver is coalescing the list of sgs which shares a | |
1410 | * page boundary into one and giving it to USB driver. With | |
1411 | * this the number of sgs mapped is not equal to the number of | |
1412 | * sgs passed. So mark the chain bit to false if it isthe last | |
1413 | * mapped sg. | |
1414 | */ | |
5d187c04 | 1415 | if ((i == remaining - 1) || !length) |
cb1b3997 | 1416 | last_sg = true; |
5ee85d89 | 1417 | |
8dbbe48c | 1418 | if (!num_trbs_left) |
13111fcb TN |
1419 | break; |
1420 | ||
cb1b3997 TN |
1421 | if (last_sg) { |
1422 | if (!dwc3_prepare_last_sg(dep, req, trb_length, i)) | |
f9cc581b | 1423 | break; |
c6267a51 | 1424 | } else { |
f9cc581b TN |
1425 | /* |
1426 | * Look ahead to check if we have enough TRBs for the | |
8dbbe48c TN |
1427 | * next SG entry. If not, set interrupt on this TRB to |
1428 | * resume preparing the next SG entry when more TRBs are | |
f9cc581b TN |
1429 | * free. |
1430 | */ | |
8dbbe48c TN |
1431 | if (num_trbs_left == 1 || (needs_extra_trb && |
1432 | num_trbs_left <= 2 && | |
1433 | sg_dma_len(sg_next(s)) >= length)) | |
f9cc581b TN |
1434 | must_interrupt = true; |
1435 | ||
1436 | dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false, | |
1437 | must_interrupt); | |
c6267a51 | 1438 | } |
5ee85d89 | 1439 | |
a31e63b6 AKV |
1440 | /* |
1441 | * There can be a situation where all sgs in sglist are not | |
1442 | * queued because of insufficient trb number. To handle this | |
1443 | * case, update start_sg to next sg to be queued, so that | |
1444 | * we have free trbs we can continue queuing from where we | |
1445 | * previously stopped | |
1446 | */ | |
cb1b3997 | 1447 | if (!last_sg) |
a31e63b6 AKV |
1448 | req->start_sg = sg_next(s); |
1449 | ||
c96e6725 | 1450 | req->num_queued_sgs++; |
25dda9fc | 1451 | req->num_pending_sgs--; |
c96e6725 | 1452 | |
5d187c04 TN |
1453 | /* |
1454 | * The number of pending SG entries may not correspond to the | |
1455 | * number of mapped SG entries. If all the data are queued, then | |
1456 | * don't include unused SG entries. | |
1457 | */ | |
1458 | if (length == 0) { | |
25dda9fc | 1459 | req->num_pending_sgs = 0; |
5d187c04 TN |
1460 | break; |
1461 | } | |
1462 | ||
8dbbe48c | 1463 | if (must_interrupt) |
5ee85d89 FB |
1464 | break; |
1465 | } | |
13111fcb | 1466 | |
13111fcb | 1467 | return req->num_trbs - num_trbs; |
5ee85d89 FB |
1468 | } |
1469 | ||
7f2958d9 | 1470 | static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep, |
7ae7df49 | 1471 | struct dwc3_request *req) |
5ee85d89 | 1472 | { |
cb1b3997 | 1473 | return dwc3_prepare_last_sg(dep, req, req->request.length, 0); |
5ee85d89 FB |
1474 | } |
1475 | ||
72246da4 FB |
1476 | /* |
1477 | * dwc3_prepare_trbs - setup TRBs from requests | |
1478 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1479 | * |
1d046793 PZ |
1480 | * The function goes through the requests list and sets up TRBs for the |
1481 | * transfers. The function returns once there are no more TRBs available or | |
1482 | * it runs out of requests. | |
490410b2 TN |
1483 | * |
1484 | * Returns the number of TRBs prepared or negative errno. | |
72246da4 | 1485 | */ |
490410b2 | 1486 | static int dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1487 | { |
68e823e2 | 1488 | struct dwc3_request *req, *n; |
490410b2 | 1489 | int ret = 0; |
72246da4 FB |
1490 | |
1491 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1492 | ||
d86c5a67 FB |
1493 | /* |
1494 | * We can get in a situation where there's a request in the started list | |
1495 | * but there weren't enough TRBs to fully kick it in the first time | |
1496 | * around, so it has been waiting for more TRBs to be freed up. | |
1497 | * | |
1498 | * In that case, we should check if we have a request with pending_sgs | |
1499 | * in the started list and prepare TRBs for that request first, | |
1500 | * otherwise we will prepare TRBs completely out of order and that will | |
1501 | * break things. | |
1502 | */ | |
1503 | list_for_each_entry(req, &dep->started_list, list) { | |
490410b2 | 1504 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1505 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd | 1506 | if (!ret || req->num_pending_sgs) |
490410b2 TN |
1507 | return ret; |
1508 | } | |
d86c5a67 FB |
1509 | |
1510 | if (!dwc3_calc_trbs_left(dep)) | |
490410b2 | 1511 | return ret; |
63c7bb29 TN |
1512 | |
1513 | /* | |
1514 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1515 | * burst capability may try to read and use TRBs beyond the | |
1516 | * active transfer instead of stopping. | |
1517 | */ | |
1518 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1519 | return ret; |
d86c5a67 FB |
1520 | } |
1521 | ||
aa3342c8 | 1522 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 | 1523 | struct dwc3 *dwc = dep->dwc; |
cdb55b39 FB |
1524 | |
1525 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1526 | dep->direction); | |
1527 | if (ret) | |
490410b2 | 1528 | return ret; |
cdb55b39 FB |
1529 | |
1530 | req->sg = req->request.sg; | |
a31e63b6 | 1531 | req->start_sg = req->sg; |
c96e6725 | 1532 | req->num_queued_sgs = 0; |
cdb55b39 FB |
1533 | req->num_pending_sgs = req->request.num_mapped_sgs; |
1534 | ||
346a15cd | 1535 | if (req->num_pending_sgs > 0) { |
7f2958d9 | 1536 | ret = dwc3_prepare_trbs_sg(dep, req); |
346a15cd TN |
1537 | if (req->num_pending_sgs) |
1538 | return ret; | |
1539 | } else { | |
7f2958d9 | 1540 | ret = dwc3_prepare_trbs_linear(dep, req); |
346a15cd | 1541 | } |
72246da4 | 1542 | |
490410b2 TN |
1543 | if (!ret || !dwc3_calc_trbs_left(dep)) |
1544 | return ret; | |
aefe3d23 TN |
1545 | |
1546 | /* | |
1547 | * Don't prepare beyond a transfer. In DWC_usb32, its transfer | |
1548 | * burst capability may try to read and use TRBs beyond the | |
1549 | * active transfer instead of stopping. | |
1550 | */ | |
1551 | if (dep->stream_capable && req->request.is_last) | |
490410b2 | 1552 | return ret; |
72246da4 | 1553 | } |
490410b2 TN |
1554 | |
1555 | return ret; | |
72246da4 FB |
1556 | } |
1557 | ||
8d99087c TN |
1558 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep); |
1559 | ||
7fdca766 | 1560 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) |
72246da4 FB |
1561 | { |
1562 | struct dwc3_gadget_ep_cmd_params params; | |
1563 | struct dwc3_request *req; | |
4fae2e3e | 1564 | int starting; |
72246da4 FB |
1565 | int ret; |
1566 | u32 cmd; | |
1567 | ||
d72ecc08 TN |
1568 | /* |
1569 | * Note that it's normal to have no new TRBs prepared (i.e. ret == 0). | |
1570 | * This happens when we need to stop and restart a transfer such as in | |
1571 | * the case of reinitiating a stream or retrying an isoc transfer. | |
1572 | */ | |
490410b2 | 1573 | ret = dwc3_prepare_trbs(dep); |
d72ecc08 | 1574 | if (ret < 0) |
490410b2 | 1575 | return ret; |
ccb94ebf | 1576 | |
1912cbc6 | 1577 | starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); |
72246da4 | 1578 | |
2338484d TN |
1579 | /* |
1580 | * If there's no new TRB prepared and we don't need to restart a | |
1581 | * transfer, there's no need to update the transfer. | |
1582 | */ | |
1583 | if (!ret && !starting) | |
1584 | return ret; | |
1585 | ||
4fae2e3e | 1586 | req = next_request(&dep->started_list); |
72246da4 FB |
1587 | if (!req) { |
1588 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1593 | |
4fae2e3e | 1594 | if (starting) { |
1877d6c9 PA |
1595 | params.param0 = upper_32_bits(req->trb_dma); |
1596 | params.param1 = lower_32_bits(req->trb_dma); | |
7fdca766 FB |
1597 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1598 | ||
a7351807 AKV |
1599 | if (dep->stream_capable) |
1600 | cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); | |
1601 | ||
7fdca766 FB |
1602 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
1603 | cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); | |
1877d6c9 | 1604 | } else { |
b6b1c6db FB |
1605 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1606 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1607 | } |
72246da4 | 1608 | |
2cd4718d | 1609 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1610 | if (ret < 0) { |
8d99087c TN |
1611 | struct dwc3_request *tmp; |
1612 | ||
1613 | if (ret == -EAGAIN) | |
1614 | return ret; | |
1615 | ||
1616 | dwc3_stop_active_transfer(dep, true, true); | |
1617 | ||
1618 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 1619 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED); |
8d99087c TN |
1620 | |
1621 | /* If ep isn't started, then there's no end transfer pending */ | |
1622 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1623 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
1624 | ||
72246da4 FB |
1625 | return ret; |
1626 | } | |
1627 | ||
e0d19563 TN |
1628 | if (dep->stream_capable && req->request.is_last) |
1629 | dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
1630 | ||
72246da4 FB |
1631 | return 0; |
1632 | } | |
1633 | ||
6cb2e4e3 FB |
1634 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1635 | { | |
1636 | u32 reg; | |
1637 | ||
1638 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1639 | return DWC3_DSTS_SOFFN(reg); | |
1640 | } | |
1641 | ||
d92021f6 TN |
1642 | /** |
1643 | * dwc3_gadget_start_isoc_quirk - workaround invalid frame number | |
1644 | * @dep: isoc endpoint | |
1645 | * | |
1646 | * This function tests for the correct combination of BIT[15:14] from the 16-bit | |
1647 | * microframe number reported by the XferNotReady event for the future frame | |
1648 | * number to start the isoc transfer. | |
1649 | * | |
1650 | * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed | |
1651 | * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the | |
1652 | * XferNotReady event are invalid. The driver uses this number to schedule the | |
1653 | * isochronous transfer and passes it to the START TRANSFER command. Because | |
1654 | * this number is invalid, the command may fail. If BIT[15:14] matches the | |
1655 | * internal 16-bit microframe, the START TRANSFER command will pass and the | |
1656 | * transfer will start at the scheduled time, if it is off by 1, the command | |
1657 | * will still pass, but the transfer will start 2 seconds in the future. For all | |
1658 | * other conditions, the START TRANSFER command will fail with bus-expiry. | |
1659 | * | |
1660 | * In order to workaround this issue, we can test for the correct combination of | |
1661 | * BIT[15:14] by sending START TRANSFER commands with different values of | |
1662 | * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart | |
1663 | * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. | |
1664 | * As the result, within the 4 possible combinations for BIT[15:14], there will | |
1665 | * be 2 successful and 2 failure START COMMAND status. One of the 2 successful | |
1666 | * command status will result in a 2-second delay start. The smaller BIT[15:14] | |
1667 | * value is the correct combination. | |
1668 | * | |
1669 | * Since there are only 4 outcomes and the results are ordered, we can simply | |
1670 | * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to | |
1671 | * deduce the smaller successful combination. | |
1672 | * | |
1673 | * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 | |
1674 | * of BIT[15:14]. The correct combination is as follow: | |
1675 | * | |
1676 | * if test0 fails and test1 passes, BIT[15:14] is 'b01 | |
1677 | * if test0 fails and test1 fails, BIT[15:14] is 'b10 | |
1678 | * if test0 passes and test1 fails, BIT[15:14] is 'b11 | |
1679 | * if test0 passes and test1 passes, BIT[15:14] is 'b00 | |
1680 | * | |
1681 | * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN | |
1682 | * endpoints. | |
1683 | */ | |
25abad6a | 1684 | static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) |
d92021f6 TN |
1685 | { |
1686 | int cmd_status = 0; | |
1687 | bool test0; | |
1688 | bool test1; | |
1689 | ||
1690 | while (dep->combo_num < 2) { | |
1691 | struct dwc3_gadget_ep_cmd_params params; | |
1692 | u32 test_frame_number; | |
1693 | u32 cmd; | |
1694 | ||
1695 | /* | |
1696 | * Check if we can start isoc transfer on the next interval or | |
1697 | * 4 uframes in the future with BIT[15:14] as dep->combo_num | |
1698 | */ | |
ca143785 | 1699 | test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1700 | test_frame_number |= dep->combo_num << 14; |
1701 | test_frame_number += max_t(u32, 4, dep->interval); | |
1702 | ||
1703 | params.param0 = upper_32_bits(dep->dwc->bounce_addr); | |
1704 | params.param1 = lower_32_bits(dep->dwc->bounce_addr); | |
1705 | ||
1706 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
1707 | cmd |= DWC3_DEPCMD_PARAM(test_frame_number); | |
1708 | cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1709 | ||
1710 | /* Redo if some other failure beside bus-expiry is received */ | |
1711 | if (cmd_status && cmd_status != -EAGAIN) { | |
1712 | dep->start_cmd_status = 0; | |
1713 | dep->combo_num = 0; | |
25abad6a | 1714 | return 0; |
d92021f6 TN |
1715 | } |
1716 | ||
1717 | /* Store the first test status */ | |
1718 | if (dep->combo_num == 0) | |
1719 | dep->start_cmd_status = cmd_status; | |
1720 | ||
1721 | dep->combo_num++; | |
1722 | ||
1723 | /* | |
1724 | * End the transfer if the START_TRANSFER command is successful | |
1725 | * to wait for the next XferNotReady to test the command again | |
1726 | */ | |
1727 | if (cmd_status == 0) { | |
c5353b22 | 1728 | dwc3_stop_active_transfer(dep, true, true); |
25abad6a | 1729 | return 0; |
d92021f6 TN |
1730 | } |
1731 | } | |
1732 | ||
1733 | /* test0 and test1 are both completed at this point */ | |
1734 | test0 = (dep->start_cmd_status == 0); | |
1735 | test1 = (cmd_status == 0); | |
1736 | ||
1737 | if (!test0 && test1) | |
1738 | dep->combo_num = 1; | |
1739 | else if (!test0 && !test1) | |
1740 | dep->combo_num = 2; | |
1741 | else if (test0 && !test1) | |
1742 | dep->combo_num = 3; | |
1743 | else if (test0 && test1) | |
1744 | dep->combo_num = 0; | |
1745 | ||
ca143785 | 1746 | dep->frame_number &= DWC3_FRNUMBER_MASK; |
d92021f6 TN |
1747 | dep->frame_number |= dep->combo_num << 14; |
1748 | dep->frame_number += max_t(u32, 4, dep->interval); | |
1749 | ||
1750 | /* Reinitialize test variables */ | |
1751 | dep->start_cmd_status = 0; | |
1752 | dep->combo_num = 0; | |
1753 | ||
25abad6a | 1754 | return __dwc3_gadget_kick_transfer(dep); |
d92021f6 TN |
1755 | } |
1756 | ||
25abad6a | 1757 | static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) |
d6d6ec7b | 1758 | { |
c5a7092f | 1759 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
d92021f6 | 1760 | struct dwc3 *dwc = dep->dwc; |
d5370106 FB |
1761 | int ret; |
1762 | int i; | |
d92021f6 | 1763 | |
36f05d36 TN |
1764 | if (list_empty(&dep->pending_list) && |
1765 | list_empty(&dep->started_list)) { | |
f4a53c55 | 1766 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
25abad6a | 1767 | return -EAGAIN; |
d6d6ec7b PA |
1768 | } |
1769 | ||
9af21dd6 TN |
1770 | if (!dwc->dis_start_transfer_quirk && |
1771 | (DWC3_VER_IS_PRIOR(DWC31, 170A) || | |
1772 | DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) { | |
e81a7018 | 1773 | if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction) |
25abad6a | 1774 | return dwc3_gadget_start_isoc_quirk(dep); |
d6d6ec7b PA |
1775 | } |
1776 | ||
c5a7092f | 1777 | if (desc->bInterval <= 14 && |
e81a7018 | 1778 | dwc->gadget->speed >= USB_SPEED_HIGH) { |
c5a7092f MO |
1779 | u32 frame = __dwc3_gadget_get_frame(dwc); |
1780 | bool rollover = frame < | |
1781 | (dep->frame_number & DWC3_FRNUMBER_MASK); | |
1782 | ||
1783 | /* | |
1784 | * frame_number is set from XferNotReady and may be already | |
1785 | * out of date. DSTS only provides the lower 14 bit of the | |
1786 | * current frame number. So add the upper two bits of | |
1787 | * frame_number and handle a possible rollover. | |
1788 | * This will provide the correct frame_number unless more than | |
1789 | * rollover has happened since XferNotReady. | |
1790 | */ | |
1791 | ||
1792 | dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) | | |
1793 | frame; | |
1794 | if (rollover) | |
1795 | dep->frame_number += BIT(14); | |
1796 | } | |
1797 | ||
d5370106 FB |
1798 | for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { |
1799 | dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); | |
1800 | ||
1801 | ret = __dwc3_gadget_kick_transfer(dep); | |
1802 | if (ret != -EAGAIN) | |
1803 | break; | |
1804 | } | |
1805 | ||
36f05d36 TN |
1806 | /* |
1807 | * After a number of unsuccessful start attempts due to bus-expiry | |
1808 | * status, issue END_TRANSFER command and retry on the next XferNotReady | |
1809 | * event. | |
1810 | */ | |
1811 | if (ret == -EAGAIN) { | |
1812 | struct dwc3_gadget_ep_cmd_params params; | |
1813 | u32 cmd; | |
1814 | ||
1815 | cmd = DWC3_DEPCMD_ENDTRANSFER | | |
1816 | DWC3_DEPCMD_CMDIOC | | |
1817 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1818 | ||
1819 | dep->resource_index = 0; | |
1820 | memset(¶ms, 0, sizeof(params)); | |
1821 | ||
1822 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
1823 | if (!ret) | |
1824 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
1825 | } | |
1826 | ||
d5370106 | 1827 | return ret; |
d6d6ec7b PA |
1828 | } |
1829 | ||
72246da4 FB |
1830 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1831 | { | |
0fc9a1be | 1832 | struct dwc3 *dwc = dep->dwc; |
0fc9a1be | 1833 | |
f09ddcfc | 1834 | if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { |
5eb30ced FB |
1835 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1836 | dep->name); | |
bb423984 FB |
1837 | return -ESHUTDOWN; |
1838 | } | |
1839 | ||
04fb365c FB |
1840 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1841 | &req->request, req->dep->name)) | |
bb423984 | 1842 | return -EINVAL; |
bb423984 | 1843 | |
b2b6d601 FB |
1844 | if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, |
1845 | "%s: request %pK already in flight\n", | |
1846 | dep->name, &req->request)) | |
1847 | return -EINVAL; | |
1848 | ||
fc8bb91b FB |
1849 | pm_runtime_get(dwc->dev); |
1850 | ||
72246da4 FB |
1851 | req->request.actual = 0; |
1852 | req->request.status = -EINPROGRESS; | |
72246da4 | 1853 | |
fe84f522 FB |
1854 | trace_dwc3_ep_queue(req); |
1855 | ||
aa3342c8 | 1856 | list_add_tail(&req->list, &dep->pending_list); |
a3af5e3a | 1857 | req->status = DWC3_REQUEST_STATUS_QUEUED; |
72246da4 | 1858 | |
e0d19563 TN |
1859 | if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE) |
1860 | return 0; | |
1861 | ||
c503672a TN |
1862 | /* |
1863 | * Start the transfer only after the END_TRANSFER is completed | |
1864 | * and endpoint STALL is cleared. | |
1865 | */ | |
1866 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || | |
1867 | (dep->flags & DWC3_EP_WEDGE) || | |
1868 | (dep->flags & DWC3_EP_STALL)) { | |
da10bcdd TN |
1869 | dep->flags |= DWC3_EP_DELAY_START; |
1870 | return 0; | |
1871 | } | |
1872 | ||
d889c23c FB |
1873 | /* |
1874 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1875 | * wait for a XferNotReady event so we will know what's the current | |
1876 | * (micro-)frame number. | |
1877 | * | |
1878 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1879 | * errors which will force us issue EndTransfer command. | |
1880 | */ | |
1881 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
fe990cea FB |
1882 | if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && |
1883 | !(dep->flags & DWC3_EP_TRANSFER_STARTED)) | |
1884 | return 0; | |
1885 | ||
6cb2e4e3 | 1886 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
e319bd62 | 1887 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
25abad6a | 1888 | return __dwc3_gadget_start_isoc(dep); |
08a36b54 | 1889 | } |
64e01080 | 1890 | } |
b997ada5 | 1891 | |
18ffa988 WC |
1892 | __dwc3_gadget_kick_transfer(dep); |
1893 | ||
1894 | return 0; | |
72246da4 FB |
1895 | } |
1896 | ||
1897 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1898 | gfp_t gfp_flags) | |
1899 | { | |
1900 | struct dwc3_request *req = to_dwc3_request(request); | |
1901 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1902 | struct dwc3 *dwc = dep->dwc; | |
1903 | ||
1904 | unsigned long flags; | |
1905 | ||
1906 | int ret; | |
1907 | ||
fdee4eba | 1908 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1909 | ret = __dwc3_gadget_ep_queue(dep, req); |
1910 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1911 | ||
1912 | return ret; | |
1913 | } | |
1914 | ||
7746a8df FB |
1915 | static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) |
1916 | { | |
1917 | int i; | |
1918 | ||
cb11ea56 TN |
1919 | /* If req->trb is not set, then the request has not started */ |
1920 | if (!req->trb) | |
1921 | return; | |
1922 | ||
7746a8df FB |
1923 | /* |
1924 | * If request was already started, this means we had to | |
1925 | * stop the transfer. With that we also need to ignore | |
1926 | * all TRBs used by the request, however TRBs can only | |
1927 | * be modified after completion of END_TRANSFER | |
1928 | * command. So what we do here is that we wait for | |
1929 | * END_TRANSFER completion and only after that, we jump | |
1930 | * over TRBs by clearing HWO and incrementing dequeue | |
1931 | * pointer. | |
1932 | */ | |
1933 | for (i = 0; i < req->num_trbs; i++) { | |
1934 | struct dwc3_trb *trb; | |
1935 | ||
2dedea03 | 1936 | trb = &dep->trb_pool[dep->trb_dequeue]; |
7746a8df FB |
1937 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
1938 | dwc3_ep_inc_deq(dep); | |
1939 | } | |
c7152763 TN |
1940 | |
1941 | req->num_trbs = 0; | |
7746a8df FB |
1942 | } |
1943 | ||
d4f1afe5 FB |
1944 | static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) |
1945 | { | |
1946 | struct dwc3_request *req; | |
04dd6e76 | 1947 | struct dwc3 *dwc = dep->dwc; |
d4f1afe5 | 1948 | |
b5d6478d WC |
1949 | while (!list_empty(&dep->cancelled_list)) { |
1950 | req = next_request(&dep->cancelled_list); | |
d4f1afe5 | 1951 | dwc3_gadget_ep_skip_trbs(dep, req); |
04dd6e76 RC |
1952 | switch (req->status) { |
1953 | case DWC3_REQUEST_STATUS_DISCONNECTED: | |
1954 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
1955 | break; | |
1956 | case DWC3_REQUEST_STATUS_DEQUEUED: | |
1957 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1958 | break; | |
1959 | case DWC3_REQUEST_STATUS_STALLED: | |
1960 | dwc3_gadget_giveback(dep, req, -EPIPE); | |
1961 | break; | |
1962 | default: | |
1963 | dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status); | |
1964 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1965 | break; | |
1966 | } | |
b5d6478d WC |
1967 | /* |
1968 | * The endpoint is disabled, let the dwc3_remove_requests() | |
1969 | * handle the cleanup. | |
1970 | */ | |
1971 | if (!dep->endpoint.desc) | |
1972 | break; | |
d4f1afe5 FB |
1973 | } |
1974 | } | |
1975 | ||
72246da4 FB |
1976 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, |
1977 | struct usb_request *request) | |
1978 | { | |
1979 | struct dwc3_request *req = to_dwc3_request(request); | |
1980 | struct dwc3_request *r = NULL; | |
1981 | ||
1982 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1983 | struct dwc3 *dwc = dep->dwc; | |
1984 | ||
1985 | unsigned long flags; | |
1986 | int ret = 0; | |
1987 | ||
2c4cbe6e FB |
1988 | trace_dwc3_ep_dequeue(req); |
1989 | ||
72246da4 FB |
1990 | spin_lock_irqsave(&dwc->lock, flags); |
1991 | ||
a7027ca6 | 1992 | list_for_each_entry(r, &dep->cancelled_list, list) { |
72246da4 | 1993 | if (r == req) |
fcd2def6 | 1994 | goto out; |
72246da4 FB |
1995 | } |
1996 | ||
aa3342c8 | 1997 | list_for_each_entry(r, &dep->pending_list, list) { |
fcd2def6 TN |
1998 | if (r == req) { |
1999 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
2000 | goto out; | |
72246da4 | 2001 | } |
72246da4 FB |
2002 | } |
2003 | ||
fcd2def6 | 2004 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 | 2005 | if (r == req) { |
a7027ca6 TN |
2006 | struct dwc3_request *t; |
2007 | ||
72246da4 | 2008 | /* wait until it is processed */ |
c5353b22 | 2009 | dwc3_stop_active_transfer(dep, true, true); |
cf3113d8 | 2010 | |
a7027ca6 TN |
2011 | /* |
2012 | * Remove any started request if the transfer is | |
2013 | * cancelled. | |
2014 | */ | |
2015 | list_for_each_entry_safe(r, t, &dep->started_list, list) | |
04dd6e76 RC |
2016 | dwc3_gadget_move_cancelled_request(r, |
2017 | DWC3_REQUEST_STATUS_DEQUEUED); | |
cf3113d8 | 2018 | |
a5c7682a TN |
2019 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; |
2020 | ||
fcd2def6 | 2021 | goto out; |
72246da4 | 2022 | } |
72246da4 FB |
2023 | } |
2024 | ||
fcd2def6 TN |
2025 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
2026 | request, ep->name); | |
2027 | ret = -EINVAL; | |
2028 | out: | |
72246da4 FB |
2029 | spin_unlock_irqrestore(&dwc->lock, flags); |
2030 | ||
2031 | return ret; | |
2032 | } | |
2033 | ||
7a608559 | 2034 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
2035 | { |
2036 | struct dwc3_gadget_ep_cmd_params params; | |
2037 | struct dwc3 *dwc = dep->dwc; | |
cb11ea56 TN |
2038 | struct dwc3_request *req; |
2039 | struct dwc3_request *tmp; | |
72246da4 FB |
2040 | int ret; |
2041 | ||
5ad02fb8 FB |
2042 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
2043 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
2044 | return -EINVAL; | |
2045 | } | |
2046 | ||
72246da4 FB |
2047 | memset(¶ms, 0x00, sizeof(params)); |
2048 | ||
2049 | if (value) { | |
69450c4d FB |
2050 | struct dwc3_trb *trb; |
2051 | ||
e319bd62 FB |
2052 | unsigned int transfer_in_flight; |
2053 | unsigned int started; | |
69450c4d FB |
2054 | |
2055 | if (dep->number > 1) | |
2056 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
2057 | else | |
2058 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
2059 | ||
2060 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
2061 | started = !list_empty(&dep->started_list); | |
2062 | ||
2063 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
2064 | (!dep->direction && started))) { | |
7a608559 FB |
2065 | return -EAGAIN; |
2066 | } | |
2067 | ||
2cd4718d FB |
2068 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
2069 | ¶ms); | |
72246da4 | 2070 | if (ret) |
3f89204b | 2071 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
2072 | dep->name); |
2073 | else | |
2074 | dep->flags |= DWC3_EP_STALL; | |
2075 | } else { | |
cb11ea56 TN |
2076 | /* |
2077 | * Don't issue CLEAR_STALL command to control endpoints. The | |
2078 | * controller automatically clears the STALL when it receives | |
2079 | * the SETUP token. | |
2080 | */ | |
2081 | if (dep->number <= 1) { | |
2082 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
2083 | return 0; | |
2084 | } | |
2cd4718d | 2085 | |
d97c78a1 TN |
2086 | dwc3_stop_active_transfer(dep, true, true); |
2087 | ||
2088 | list_for_each_entry_safe(req, tmp, &dep->started_list, list) | |
04dd6e76 | 2089 | dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED); |
d97c78a1 TN |
2090 | |
2091 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { | |
2092 | dep->flags |= DWC3_EP_PENDING_CLEAR_STALL; | |
2093 | return 0; | |
2094 | } | |
2095 | ||
2096 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
2097 | ||
50c763f8 | 2098 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
cb11ea56 | 2099 | if (ret) { |
3f89204b | 2100 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 | 2101 | dep->name); |
cb11ea56 TN |
2102 | return ret; |
2103 | } | |
2104 | ||
2105 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
2106 | ||
c503672a TN |
2107 | if ((dep->flags & DWC3_EP_DELAY_START) && |
2108 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2109 | __dwc3_gadget_kick_transfer(dep); | |
2110 | ||
2111 | dep->flags &= ~DWC3_EP_DELAY_START; | |
72246da4 | 2112 | } |
5275455a | 2113 | |
72246da4 FB |
2114 | return ret; |
2115 | } | |
2116 | ||
2117 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
2118 | { | |
2119 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
2120 | struct dwc3 *dwc = dep->dwc; | |
2121 | ||
2122 | unsigned long flags; | |
2123 | ||
2124 | int ret; | |
2125 | ||
2126 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 2127 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
2128 | spin_unlock_irqrestore(&dwc->lock, flags); |
2129 | ||
2130 | return ret; | |
2131 | } | |
2132 | ||
2133 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
2134 | { | |
2135 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
2136 | struct dwc3 *dwc = dep->dwc; |
2137 | unsigned long flags; | |
95aa4e8d | 2138 | int ret; |
72246da4 | 2139 | |
249a4569 | 2140 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
2141 | dep->flags |= DWC3_EP_WEDGE; |
2142 | ||
08f0d966 | 2143 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 2144 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 2145 | else |
7a608559 | 2146 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
2147 | spin_unlock_irqrestore(&dwc->lock, flags); |
2148 | ||
2149 | return ret; | |
72246da4 FB |
2150 | } |
2151 | ||
2152 | /* -------------------------------------------------------------------------- */ | |
2153 | ||
2154 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
2155 | .bLength = USB_DT_ENDPOINT_SIZE, | |
2156 | .bDescriptorType = USB_DT_ENDPOINT, | |
2157 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
2158 | }; | |
2159 | ||
2160 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
2161 | .enable = dwc3_gadget_ep0_enable, | |
2162 | .disable = dwc3_gadget_ep0_disable, | |
2163 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
2164 | .free_request = dwc3_gadget_ep_free_request, | |
2165 | .queue = dwc3_gadget_ep0_queue, | |
2166 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 2167 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
2168 | .set_wedge = dwc3_gadget_ep_set_wedge, |
2169 | }; | |
2170 | ||
2171 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
2172 | .enable = dwc3_gadget_ep_enable, | |
2173 | .disable = dwc3_gadget_ep_disable, | |
2174 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
2175 | .free_request = dwc3_gadget_ep_free_request, | |
2176 | .queue = dwc3_gadget_ep_queue, | |
2177 | .dequeue = dwc3_gadget_ep_dequeue, | |
2178 | .set_halt = dwc3_gadget_ep_set_halt, | |
2179 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
2180 | }; | |
2181 | ||
2182 | /* -------------------------------------------------------------------------- */ | |
2183 | ||
2184 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
2185 | { | |
2186 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 2187 | |
6cb2e4e3 | 2188 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
2189 | } |
2190 | ||
218ef7b6 | 2191 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 2192 | { |
d6011f6f | 2193 | int retries; |
72246da4 | 2194 | |
218ef7b6 | 2195 | int ret; |
72246da4 FB |
2196 | u32 reg; |
2197 | ||
72246da4 | 2198 | u8 link_state; |
72246da4 | 2199 | |
72246da4 FB |
2200 | /* |
2201 | * According to the Databook Remote wakeup request should | |
2202 | * be issued only when the device is in early suspend state. | |
2203 | * | |
2204 | * We can check that via USB Link State bits in DSTS register. | |
2205 | */ | |
2206 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
2207 | ||
72246da4 FB |
2208 | link_state = DWC3_DSTS_USBLNKST(reg); |
2209 | ||
2210 | switch (link_state) { | |
d0550cd2 | 2211 | case DWC3_LINK_STATE_RESET: |
72246da4 FB |
2212 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ |
2213 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
c560e763 TN |
2214 | case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */ |
2215 | case DWC3_LINK_STATE_U1: | |
d0550cd2 | 2216 | case DWC3_LINK_STATE_RESUME: |
72246da4 FB |
2217 | break; |
2218 | default: | |
218ef7b6 | 2219 | return -EINVAL; |
72246da4 FB |
2220 | } |
2221 | ||
8598bde7 FB |
2222 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
2223 | if (ret < 0) { | |
2224 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 2225 | return ret; |
8598bde7 | 2226 | } |
72246da4 | 2227 | |
802fde98 | 2228 | /* Recent versions do this automatically */ |
9af21dd6 | 2229 | if (DWC3_VER_IS_PRIOR(DWC3, 194A)) { |
802fde98 | 2230 | /* write zeroes to Link Change Request */ |
fcc023c7 | 2231 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
2232 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
2233 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2234 | } | |
72246da4 | 2235 | |
1d046793 | 2236 | /* poll until Link State changes to ON */ |
d6011f6f | 2237 | retries = 20000; |
72246da4 | 2238 | |
d6011f6f | 2239 | while (retries--) { |
72246da4 FB |
2240 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2241 | ||
2242 | /* in HS, means ON */ | |
2243 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
2244 | break; | |
2245 | } | |
2246 | ||
2247 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
2248 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 2249 | return -EINVAL; |
72246da4 FB |
2250 | } |
2251 | ||
218ef7b6 FB |
2252 | return 0; |
2253 | } | |
2254 | ||
2255 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
2256 | { | |
2257 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2258 | unsigned long flags; | |
2259 | int ret; | |
2260 | ||
2261 | spin_lock_irqsave(&dwc->lock, flags); | |
2262 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
2263 | spin_unlock_irqrestore(&dwc->lock, flags); |
2264 | ||
2265 | return ret; | |
2266 | } | |
2267 | ||
2268 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
2269 | int is_selfpowered) | |
2270 | { | |
2271 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 2272 | unsigned long flags; |
72246da4 | 2273 | |
249a4569 | 2274 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 2275 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 2276 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
2277 | |
2278 | return 0; | |
2279 | } | |
2280 | ||
ae7e8610 WC |
2281 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) |
2282 | { | |
2283 | u32 epnum; | |
2284 | ||
2285 | for (epnum = 2; epnum < dwc->num_eps; epnum++) { | |
2286 | struct dwc3_ep *dep; | |
2287 | ||
2288 | dep = dwc->eps[epnum]; | |
2289 | if (!dep) | |
2290 | continue; | |
2291 | ||
20606c74 | 2292 | dwc3_remove_requests(dwc, dep, -ESHUTDOWN); |
ae7e8610 WC |
2293 | } |
2294 | } | |
2295 | ||
072cab8a TN |
2296 | static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc) |
2297 | { | |
2298 | enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate; | |
2299 | u32 reg; | |
2300 | ||
2301 | if (ssp_rate == USB_SSP_GEN_UNKNOWN) | |
2302 | ssp_rate = dwc->max_ssp_rate; | |
2303 | ||
2304 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2305 | reg &= ~DWC3_DCFG_SPEED_MASK; | |
2306 | reg &= ~DWC3_DCFG_NUMLANES(~0); | |
2307 | ||
2308 | if (ssp_rate == USB_SSP_GEN_1x2) | |
2309 | reg |= DWC3_DCFG_SUPERSPEED; | |
2310 | else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2) | |
2311 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2312 | ||
2313 | if (ssp_rate != USB_SSP_GEN_2x1 && | |
2314 | dwc->max_ssp_rate != USB_SSP_GEN_2x1) | |
2315 | reg |= DWC3_DCFG_NUMLANES(1); | |
2316 | ||
2317 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2318 | } | |
2319 | ||
7c9a2598 WC |
2320 | static void __dwc3_gadget_set_speed(struct dwc3 *dwc) |
2321 | { | |
450b9e9f | 2322 | enum usb_device_speed speed; |
7c9a2598 WC |
2323 | u32 reg; |
2324 | ||
450b9e9f | 2325 | speed = dwc->gadget_max_speed; |
93f1d43c | 2326 | if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed) |
450b9e9f TN |
2327 | speed = dwc->maximum_speed; |
2328 | ||
2329 | if (speed == USB_SPEED_SUPER_PLUS && | |
072cab8a TN |
2330 | DWC3_IP_IS(DWC32)) { |
2331 | __dwc3_gadget_set_ssp_rate(dwc); | |
2332 | return; | |
2333 | } | |
2334 | ||
7c9a2598 WC |
2335 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2336 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
2337 | ||
2338 | /* | |
2339 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
2340 | * which would cause metastability state on Run/Stop | |
2341 | * bit if we try to force the IP to USB2-only mode. | |
2342 | * | |
2343 | * Because of that, we cannot configure the IP to any | |
2344 | * speed other than the SuperSpeed | |
2345 | * | |
2346 | * Refers to: | |
2347 | * | |
2348 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
2349 | * USB 2.0 Mode | |
2350 | */ | |
2351 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && | |
2352 | !dwc->dis_metastability_quirk) { | |
2353 | reg |= DWC3_DCFG_SUPERSPEED; | |
2354 | } else { | |
450b9e9f | 2355 | switch (speed) { |
7c9a2598 WC |
2356 | case USB_SPEED_FULL: |
2357 | reg |= DWC3_DCFG_FULLSPEED; | |
2358 | break; | |
2359 | case USB_SPEED_HIGH: | |
2360 | reg |= DWC3_DCFG_HIGHSPEED; | |
2361 | break; | |
2362 | case USB_SPEED_SUPER: | |
2363 | reg |= DWC3_DCFG_SUPERSPEED; | |
2364 | break; | |
2365 | case USB_SPEED_SUPER_PLUS: | |
2366 | if (DWC3_IP_IS(DWC3)) | |
2367 | reg |= DWC3_DCFG_SUPERSPEED; | |
2368 | else | |
2369 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2370 | break; | |
2371 | default: | |
450b9e9f | 2372 | dev_err(dwc->dev, "invalid speed (%d)\n", speed); |
7c9a2598 WC |
2373 | |
2374 | if (DWC3_IP_IS(DWC3)) | |
2375 | reg |= DWC3_DCFG_SUPERSPEED; | |
2376 | else | |
2377 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; | |
2378 | } | |
2379 | } | |
f551037c TN |
2380 | |
2381 | if (DWC3_IP_IS(DWC32) && | |
450b9e9f TN |
2382 | speed > USB_SPEED_UNKNOWN && |
2383 | speed < USB_SPEED_SUPER_PLUS) | |
f551037c TN |
2384 | reg &= ~DWC3_DCFG_NUMLANES(~0); |
2385 | ||
7c9a2598 WC |
2386 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
2387 | } | |
2388 | ||
7b2a0368 | 2389 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
2390 | { |
2391 | u32 reg; | |
61d58242 | 2392 | u32 timeout = 500; |
72246da4 | 2393 | |
fc8bb91b FB |
2394 | if (pm_runtime_suspended(dwc->dev)) |
2395 | return 0; | |
2396 | ||
72246da4 | 2397 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 2398 | if (is_on) { |
9af21dd6 | 2399 | if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) { |
802fde98 PZ |
2400 | reg &= ~DWC3_DCTL_TRGTULST_MASK; |
2401 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
2402 | } | |
2403 | ||
9af21dd6 | 2404 | if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) |
802fde98 PZ |
2405 | reg &= ~DWC3_DCTL_KEEP_CONNECT; |
2406 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
2407 | |
2408 | if (dwc->has_hibernation) | |
2409 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
2410 | ||
7c9a2598 | 2411 | __dwc3_gadget_set_speed(dwc); |
9fcb3bd8 | 2412 | dwc->pullups_connected = true; |
8db7ed15 | 2413 | } else { |
72246da4 | 2414 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
2415 | |
2416 | if (dwc->has_hibernation && !suspend) | |
2417 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
2418 | ||
9fcb3bd8 | 2419 | dwc->pullups_connected = false; |
8db7ed15 | 2420 | } |
72246da4 | 2421 | |
5b738211 | 2422 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 FB |
2423 | |
2424 | do { | |
2425 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
2426 | reg &= DWC3_DSTS_DEVCTRLHLT; |
2427 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
2428 | |
2429 | if (!timeout) | |
2430 | return -ETIMEDOUT; | |
72246da4 | 2431 | |
6f17f74b | 2432 | return 0; |
72246da4 FB |
2433 | } |
2434 | ||
ae7e8610 WC |
2435 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc); |
2436 | static void __dwc3_gadget_stop(struct dwc3 *dwc); | |
a1383b35 | 2437 | static int __dwc3_gadget_start(struct dwc3 *dwc); |
ae7e8610 | 2438 | |
eef142dd TN |
2439 | static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc) |
2440 | { | |
ddb23641 | 2441 | unsigned long flags; |
eef142dd | 2442 | |
ddb23641 | 2443 | spin_lock_irqsave(&dwc->lock, flags); |
eef142dd TN |
2444 | dwc->connected = false; |
2445 | ||
2446 | /* | |
2447 | * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a | |
2448 | * Section 4.1.8 Table 4-7, it states that for a device-initiated | |
2449 | * disconnect, the SW needs to ensure that it sends "a DEPENDXFER | |
2450 | * command for any active transfers" before clearing the RunStop | |
2451 | * bit. | |
2452 | */ | |
2453 | dwc3_stop_active_transfers(dwc); | |
2454 | __dwc3_gadget_stop(dwc); | |
ddb23641 | 2455 | spin_unlock_irqrestore(&dwc->lock, flags); |
eef142dd TN |
2456 | |
2457 | /* | |
ddb23641 TN |
2458 | * Note: if the GEVNTCOUNT indicates events in the event buffer, the |
2459 | * driver needs to acknowledge them before the controller can halt. | |
2460 | * Simply let the interrupt handler acknowledges and handle the | |
2461 | * remaining event generated by the controller while polling for | |
2462 | * DSTS.DEVCTLHLT. | |
eef142dd | 2463 | */ |
eef142dd TN |
2464 | return dwc3_gadget_run_stop(dwc, false, false); |
2465 | } | |
2466 | ||
72246da4 FB |
2467 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) |
2468 | { | |
2469 | struct dwc3 *dwc = gadget_to_dwc(g); | |
6f17f74b | 2470 | int ret; |
72246da4 FB |
2471 | |
2472 | is_on = !!is_on; | |
2e4c7c82 | 2473 | |
149c9ed4 | 2474 | dwc->softconnect = is_on; |
bb014736 BW |
2475 | /* |
2476 | * Per databook, when we want to stop the gadget, if a control transfer | |
2477 | * is still in process, complete it and get the core into setup phase. | |
2478 | */ | |
2479 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
2480 | reinit_completion(&dwc->ep0_in_setup); | |
2481 | ||
2482 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
2483 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
4a1e25c0 WC |
2484 | if (ret == 0) |
2485 | dev_warn(dwc->dev, "timed out waiting for SETUP phase\n"); | |
bb014736 BW |
2486 | } |
2487 | ||
cb10f68a WC |
2488 | /* |
2489 | * Avoid issuing a runtime resume if the device is already in the | |
2490 | * suspended state during gadget disconnect. DWC3 gadget was already | |
2491 | * halted/stopped during runtime suspend. | |
2492 | */ | |
2493 | if (!is_on) { | |
2494 | pm_runtime_barrier(dwc->dev); | |
2495 | if (pm_runtime_suspended(dwc->dev)) | |
2496 | return 0; | |
2497 | } | |
2498 | ||
77adb8bd WC |
2499 | /* |
2500 | * Check the return value for successful resume, or error. For a | |
2501 | * successful resume, the DWC3 runtime PM resume routine will handle | |
2502 | * the run stop sequence, so avoid duplicate operations here. | |
2503 | */ | |
2504 | ret = pm_runtime_get_sync(dwc->dev); | |
2505 | if (!ret || ret < 0) { | |
2506 | pm_runtime_put(dwc->dev); | |
2507 | return 0; | |
2508 | } | |
2509 | ||
c9498b16 WC |
2510 | if (dwc->pullups_connected == is_on) { |
2511 | pm_runtime_put(dwc->dev); | |
2512 | return 0; | |
2513 | } | |
2514 | ||
ae7e8610 | 2515 | if (!is_on) { |
eef142dd | 2516 | ret = dwc3_gadget_soft_disconnect(dwc); |
a1383b35 | 2517 | } else { |
52af8628 WC |
2518 | /* |
2519 | * In the Synopsys DWC_usb31 1.90a programming guide section | |
2520 | * 4.1.9, it specifies that for a reconnect after a | |
2521 | * device-initiated disconnect requires a core soft reset | |
2522 | * (DCTL.CSftRst) before enabling the run/stop bit. | |
2523 | */ | |
52af8628 | 2524 | dwc3_core_soft_reset(dwc); |
52af8628 WC |
2525 | |
2526 | dwc3_event_buffers_setup(dwc); | |
a1383b35 | 2527 | __dwc3_gadget_start(dwc); |
eef142dd | 2528 | ret = dwc3_gadget_run_stop(dwc, true, false); |
ae7e8610 | 2529 | } |
82129373 | 2530 | |
77adb8bd | 2531 | pm_runtime_put(dwc->dev); |
72246da4 | 2532 | |
6f17f74b | 2533 | return ret; |
72246da4 FB |
2534 | } |
2535 | ||
8698e2ac FB |
2536 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
2537 | { | |
2538 | u32 reg; | |
2539 | ||
2540 | /* Enable all but Start and End of Frame IRQs */ | |
132ee0da | 2541 | reg = (DWC3_DEVTEN_EVNTOVERFLOWEN | |
8698e2ac FB |
2542 | DWC3_DEVTEN_CMDCMPLTEN | |
2543 | DWC3_DEVTEN_ERRTICERREN | | |
2544 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
2545 | DWC3_DEVTEN_CONNECTDONEEN | |
2546 | DWC3_DEVTEN_USBRSTEN | | |
2547 | DWC3_DEVTEN_DISCONNEVTEN); | |
2548 | ||
9af21dd6 | 2549 | if (DWC3_VER_IS_PRIOR(DWC3, 250A)) |
799e9dc8 FB |
2550 | reg |= DWC3_DEVTEN_ULSTCNGEN; |
2551 | ||
d1d90dd2 JP |
2552 | /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */ |
2553 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) | |
6f26ebb7 | 2554 | reg |= DWC3_DEVTEN_U3L2L1SUSPEN; |
d1d90dd2 | 2555 | |
8698e2ac FB |
2556 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
2557 | } | |
2558 | ||
2559 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
2560 | { | |
2561 | /* mask all interrupts */ | |
2562 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2563 | } | |
2564 | ||
2565 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 2566 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 2567 | |
4e99472b | 2568 | /** |
bfad65ee FB |
2569 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
2570 | * @dwc: pointer to our context structure | |
4e99472b FB |
2571 | * |
2572 | * The following looks like complex but it's actually very simple. In order to | |
2573 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
2574 | * gonna use RxFIFO size. | |
2575 | * | |
2576 | * To calculate RxFIFO size we need two numbers: | |
2577 | * MDWIDTH = size, in bits, of the internal memory bus | |
2578 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
2579 | * | |
2580 | * Given these two numbers, the formula is simple: | |
2581 | * | |
2582 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
2583 | * | |
2584 | * 24 bytes is for 3x SETUP packets | |
2585 | * 16 bytes is a clock domain crossing tolerance | |
2586 | * | |
2587 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
2588 | */ | |
2589 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
2590 | { | |
2591 | u32 ram2_depth; | |
2592 | u32 mdwidth; | |
2593 | u32 nump; | |
2594 | u32 reg; | |
2595 | ||
2596 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
d00be779 | 2597 | mdwidth = dwc3_mdwidth(dwc); |
4e99472b FB |
2598 | |
2599 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
2600 | nump = min_t(u32, nump, 16); | |
2601 | ||
2602 | /* update NumP */ | |
2603 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2604 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
2605 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
2606 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2607 | } | |
2608 | ||
d7be2952 | 2609 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 2610 | { |
72246da4 | 2611 | struct dwc3_ep *dep; |
72246da4 FB |
2612 | int ret = 0; |
2613 | u32 reg; | |
2614 | ||
cf40b86b JY |
2615 | /* |
2616 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
2617 | * the core supports IMOD, disable it. | |
2618 | */ | |
2619 | if (dwc->imod_interval) { | |
2620 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
2621 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
2622 | } else if (dwc3_has_imod(dwc)) { | |
2623 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
2624 | } | |
2625 | ||
2a58f9c1 FB |
2626 | /* |
2627 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
2628 | * field instead of letting dwc3 itself calculate that automatically. | |
2629 | * | |
2630 | * This way, we maximize the chances that we'll be able to get several | |
2631 | * bursts of data without going through any sort of endpoint throttling. | |
2632 | */ | |
2633 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
9af21dd6 | 2634 | if (DWC3_IP_IS(DWC3)) |
01b0e2cc | 2635 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; |
9af21dd6 TN |
2636 | else |
2637 | reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; | |
01b0e2cc | 2638 | |
2a58f9c1 FB |
2639 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); |
2640 | ||
4e99472b FB |
2641 | dwc3_gadget_setup_nump(dwc); |
2642 | ||
e66bbfb0 TN |
2643 | /* |
2644 | * Currently the controller handles single stream only. So, Ignore | |
2645 | * Packet Pending bit for stream selection and don't search for another | |
2646 | * stream if the host sends Data Packet with PP=0 (for OUT direction) or | |
2647 | * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves | |
2648 | * the stream performance. | |
2649 | */ | |
2650 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2651 | reg |= DWC3_DCFG_IGNSTRMPP; | |
2652 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2653 | ||
72246da4 FB |
2654 | /* Start with SuperSpeed Default */ |
2655 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2656 | ||
2657 | dep = dwc->eps[0]; | |
a2d23f08 | 2658 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2659 | if (ret) { |
2660 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2661 | goto err0; |
72246da4 FB |
2662 | } |
2663 | ||
2664 | dep = dwc->eps[1]; | |
a2d23f08 | 2665 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); |
72246da4 FB |
2666 | if (ret) { |
2667 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 2668 | goto err1; |
72246da4 FB |
2669 | } |
2670 | ||
2671 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 2672 | dwc->ep0state = EP0_SETUP_PHASE; |
88b1bb1f | 2673 | dwc->link_state = DWC3_LINK_STATE_SS_DIS; |
4a1e25c0 | 2674 | dwc->delayed_status = false; |
72246da4 FB |
2675 | dwc3_ep0_out_start(dwc); |
2676 | ||
8698e2ac FB |
2677 | dwc3_gadget_enable_irq(dwc); |
2678 | ||
72246da4 FB |
2679 | return 0; |
2680 | ||
b0d7ffd4 | 2681 | err1: |
d7be2952 | 2682 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
2683 | |
2684 | err0: | |
72246da4 FB |
2685 | return ret; |
2686 | } | |
2687 | ||
d7be2952 FB |
2688 | static int dwc3_gadget_start(struct usb_gadget *g, |
2689 | struct usb_gadget_driver *driver) | |
72246da4 FB |
2690 | { |
2691 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2692 | unsigned long flags; | |
8cf9045b | 2693 | int ret; |
8698e2ac | 2694 | int irq; |
72246da4 | 2695 | |
9522def4 | 2696 | irq = dwc->irq_gadget; |
d7be2952 FB |
2697 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
2698 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
2699 | if (ret) { | |
2700 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2701 | irq, ret); | |
8cf9045b | 2702 | return ret; |
d7be2952 FB |
2703 | } |
2704 | ||
72246da4 | 2705 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2706 | dwc->gadget_driver = driver; |
d7be2952 FB |
2707 | spin_unlock_irqrestore(&dwc->lock, flags); |
2708 | ||
2709 | return 0; | |
d7be2952 | 2710 | } |
72246da4 | 2711 | |
d7be2952 FB |
2712 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
2713 | { | |
8698e2ac | 2714 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
2715 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2716 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 2717 | } |
72246da4 | 2718 | |
d7be2952 FB |
2719 | static int dwc3_gadget_stop(struct usb_gadget *g) |
2720 | { | |
2721 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2722 | unsigned long flags; | |
72246da4 | 2723 | |
d7be2952 | 2724 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 | 2725 | dwc->gadget_driver = NULL; |
9f607a30 | 2726 | dwc->max_cfg_eps = 0; |
72246da4 FB |
2727 | spin_unlock_irqrestore(&dwc->lock, flags); |
2728 | ||
3f308d17 | 2729 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2730 | |
72246da4 FB |
2731 | return 0; |
2732 | } | |
802fde98 | 2733 | |
729dcffd AKV |
2734 | static void dwc3_gadget_config_params(struct usb_gadget *g, |
2735 | struct usb_dcd_config_params *params) | |
2736 | { | |
2737 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2738 | ||
54fb5ba6 TN |
2739 | params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; |
2740 | params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; | |
2741 | ||
2742 | /* Recommended BESL */ | |
2743 | if (!dwc->dis_enblslpm_quirk) { | |
17b63704 TN |
2744 | /* |
2745 | * If the recommended BESL baseline is 0 or if the BESL deep is | |
2746 | * less than 2, Microsoft's Windows 10 host usb stack will issue | |
2747 | * a usb reset immediately after it receives the extended BOS | |
2748 | * descriptor and the enumeration will fail. To maintain | |
2749 | * compatibility with the Windows' usb stack, let's set the | |
2750 | * recommended BESL baseline to 1 and clamp the BESL deep to be | |
2751 | * within 2 to 15. | |
2752 | */ | |
2753 | params->besl_baseline = 1; | |
54fb5ba6 | 2754 | if (dwc->is_utmi_l1_suspend) |
17b63704 TN |
2755 | params->besl_deep = |
2756 | clamp_t(u8, dwc->hird_threshold, 2, 15); | |
54fb5ba6 TN |
2757 | } |
2758 | ||
729dcffd AKV |
2759 | /* U1 Device exit Latency */ |
2760 | if (dwc->dis_u1_entry_quirk) | |
2761 | params->bU1devExitLat = 0; | |
2762 | else | |
2763 | params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; | |
2764 | ||
2765 | /* U2 Device exit Latency */ | |
2766 | if (dwc->dis_u2_entry_quirk) | |
2767 | params->bU2DevExitLat = 0; | |
2768 | else | |
2769 | params->bU2DevExitLat = | |
2770 | cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); | |
2771 | } | |
2772 | ||
7d8d0639 FB |
2773 | static void dwc3_gadget_set_speed(struct usb_gadget *g, |
2774 | enum usb_device_speed speed) | |
2775 | { | |
2776 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2777 | unsigned long flags; | |
7d8d0639 FB |
2778 | |
2779 | spin_lock_irqsave(&dwc->lock, flags); | |
7c9a2598 | 2780 | dwc->gadget_max_speed = speed; |
7d8d0639 FB |
2781 | spin_unlock_irqrestore(&dwc->lock, flags); |
2782 | } | |
2783 | ||
072cab8a TN |
2784 | static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g, |
2785 | enum usb_ssp_rate rate) | |
2786 | { | |
2787 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2788 | unsigned long flags; | |
2789 | ||
2790 | spin_lock_irqsave(&dwc->lock, flags); | |
cdb651b6 | 2791 | dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS; |
072cab8a TN |
2792 | dwc->gadget_ssp_rate = rate; |
2793 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2794 | } | |
2795 | ||
82c46b8e WC |
2796 | static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA) |
2797 | { | |
2798 | struct dwc3 *dwc = gadget_to_dwc(g); | |
99288de3 RC |
2799 | union power_supply_propval val = {0}; |
2800 | int ret; | |
82c46b8e WC |
2801 | |
2802 | if (dwc->usb2_phy) | |
2803 | return usb_phy_set_power(dwc->usb2_phy, mA); | |
2804 | ||
99288de3 RC |
2805 | if (!dwc->usb_psy) |
2806 | return -EOPNOTSUPP; | |
2807 | ||
8a5b5c3c | 2808 | val.intval = 1000 * mA; |
99288de3 RC |
2809 | ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); |
2810 | ||
2811 | return ret; | |
82c46b8e WC |
2812 | } |
2813 | ||
9f607a30 WC |
2814 | /** |
2815 | * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration | |
2816 | * @g: pointer to the USB gadget | |
2817 | * | |
2818 | * Used to record the maximum number of endpoints being used in a USB composite | |
2819 | * device. (across all configurations) This is to be used in the calculation | |
2820 | * of the TXFIFO sizes when resizing internal memory for individual endpoints. | |
2821 | * It will help ensured that the resizing logic reserves enough space for at | |
2822 | * least one max packet. | |
2823 | */ | |
2824 | static int dwc3_gadget_check_config(struct usb_gadget *g) | |
2825 | { | |
2826 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2827 | struct usb_ep *ep; | |
2828 | int fifo_size = 0; | |
2829 | int ram1_depth; | |
2830 | int ep_num = 0; | |
2831 | ||
2832 | if (!dwc->do_fifo_resize) | |
2833 | return 0; | |
2834 | ||
2835 | list_for_each_entry(ep, &g->ep_list, ep_list) { | |
2836 | /* Only interested in the IN endpoints */ | |
2837 | if (ep->claimed && (ep->address & USB_DIR_IN)) | |
2838 | ep_num++; | |
2839 | } | |
2840 | ||
2841 | if (ep_num <= dwc->max_cfg_eps) | |
2842 | return 0; | |
2843 | ||
2844 | /* Update the max number of eps in the composition */ | |
2845 | dwc->max_cfg_eps = ep_num; | |
2846 | ||
2847 | fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps); | |
2848 | /* Based on the equation, increment by one for every ep */ | |
2849 | fifo_size += dwc->max_cfg_eps; | |
2850 | ||
2851 | /* Check if we can fit a single fifo per endpoint */ | |
2852 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
2853 | if (fifo_size > ram1_depth) | |
2854 | return -ENOMEM; | |
2855 | ||
2856 | return 0; | |
2857 | } | |
2858 | ||
40edb522 LY |
2859 | static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable) |
2860 | { | |
2861 | struct dwc3 *dwc = gadget_to_dwc(g); | |
2862 | unsigned long flags; | |
2863 | ||
2864 | spin_lock_irqsave(&dwc->lock, flags); | |
2865 | dwc->async_callbacks = enable; | |
2866 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2867 | } | |
2868 | ||
72246da4 FB |
2869 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2870 | .get_frame = dwc3_gadget_get_frame, | |
2871 | .wakeup = dwc3_gadget_wakeup, | |
2872 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2873 | .pullup = dwc3_gadget_pullup, | |
2874 | .udc_start = dwc3_gadget_start, | |
2875 | .udc_stop = dwc3_gadget_stop, | |
7d8d0639 | 2876 | .udc_set_speed = dwc3_gadget_set_speed, |
072cab8a | 2877 | .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate, |
729dcffd | 2878 | .get_config_params = dwc3_gadget_config_params, |
82c46b8e | 2879 | .vbus_draw = dwc3_gadget_vbus_draw, |
9f607a30 | 2880 | .check_config = dwc3_gadget_check_config, |
40edb522 | 2881 | .udc_async_callbacks = dwc3_gadget_async_callbacks, |
72246da4 FB |
2882 | }; |
2883 | ||
2884 | /* -------------------------------------------------------------------------- */ | |
2885 | ||
8f1c99cd | 2886 | static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) |
72246da4 | 2887 | { |
8f1c99cd | 2888 | struct dwc3 *dwc = dep->dwc; |
72246da4 | 2889 | |
8f1c99cd FB |
2890 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
2891 | dep->endpoint.maxburst = 1; | |
2892 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
2893 | if (!dep->direction) | |
e81a7018 | 2894 | dwc->gadget->ep0 = &dep->endpoint; |
f3bcfc7e | 2895 | |
8f1c99cd | 2896 | dep->endpoint.caps.type_control = true; |
72246da4 | 2897 | |
8f1c99cd FB |
2898 | return 0; |
2899 | } | |
72246da4 | 2900 | |
8f1c99cd FB |
2901 | static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) |
2902 | { | |
2903 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2904 | u32 mdwidth; |
8f1c99cd | 2905 | int size; |
72246da4 | 2906 | |
d00be779 | 2907 | mdwidth = dwc3_mdwidth(dwc); |
4244ba02 | 2908 | |
8f1c99cd FB |
2909 | /* MDWIDTH is represented in bits, we need it in bytes */ |
2910 | mdwidth /= 8; | |
6a1e3ef4 | 2911 | |
8f1c99cd | 2912 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); |
9af21dd6 | 2913 | if (DWC3_IP_IS(DWC3)) |
586f4335 | 2914 | size = DWC3_GTXFIFOSIZ_TXFDEP(size); |
9af21dd6 TN |
2915 | else |
2916 | size = DWC31_GTXFIFOSIZ_TXFDEP(size); | |
39ebb05c | 2917 | |
8f1c99cd FB |
2918 | /* FIFO Depth is in MDWDITH bytes. Multiply */ |
2919 | size *= mdwidth; | |
39ebb05c | 2920 | |
8f1c99cd | 2921 | /* |
d94ea531 TN |
2922 | * To meet performance requirement, a minimum TxFIFO size of 3x |
2923 | * MaxPacketSize is recommended for endpoints that support burst and a | |
2924 | * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't | |
2925 | * support burst. Use those numbers and we can calculate the max packet | |
2926 | * limit as below. | |
8f1c99cd | 2927 | */ |
d94ea531 TN |
2928 | if (dwc->maximum_speed >= USB_SPEED_SUPER) |
2929 | size /= 3; | |
2930 | else | |
2931 | size /= 2; | |
28781789 | 2932 | |
8f1c99cd | 2933 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); |
28781789 | 2934 | |
e0a93d98 | 2935 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2936 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2937 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2938 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2939 | dep->endpoint.caps.type_iso = true; |
2940 | dep->endpoint.caps.type_bulk = true; | |
2941 | dep->endpoint.caps.type_int = true; | |
28781789 | 2942 | |
8f1c99cd FB |
2943 | return dwc3_alloc_trb_pool(dep); |
2944 | } | |
28781789 | 2945 | |
8f1c99cd FB |
2946 | static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) |
2947 | { | |
2948 | struct dwc3 *dwc = dep->dwc; | |
d00be779 | 2949 | u32 mdwidth; |
d94ea531 TN |
2950 | int size; |
2951 | ||
d00be779 | 2952 | mdwidth = dwc3_mdwidth(dwc); |
d94ea531 TN |
2953 | |
2954 | /* MDWIDTH is represented in bits, convert to bytes */ | |
2955 | mdwidth /= 8; | |
28781789 | 2956 | |
d94ea531 TN |
2957 | /* All OUT endpoints share a single RxFIFO space */ |
2958 | size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); | |
9af21dd6 | 2959 | if (DWC3_IP_IS(DWC3)) |
d94ea531 | 2960 | size = DWC3_GRXFIFOSIZ_RXFDEP(size); |
9af21dd6 TN |
2961 | else |
2962 | size = DWC31_GRXFIFOSIZ_RXFDEP(size); | |
d94ea531 TN |
2963 | |
2964 | /* FIFO depth is in MDWDITH bytes */ | |
2965 | size *= mdwidth; | |
2966 | ||
2967 | /* | |
2968 | * To meet performance requirement, a minimum recommended RxFIFO size | |
2969 | * is defined as follow: | |
2970 | * RxFIFO size >= (3 x MaxPacketSize) + | |
2971 | * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin) | |
2972 | * | |
2973 | * Then calculate the max packet limit as below. | |
2974 | */ | |
2975 | size -= (3 * 8) + 16; | |
2976 | if (size < 0) | |
2977 | size = 0; | |
2978 | else | |
2979 | size /= 3; | |
2980 | ||
2981 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
e0a93d98 | 2982 | dep->endpoint.max_streams = 16; |
8f1c99cd FB |
2983 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2984 | list_add_tail(&dep->endpoint.ep_list, | |
e81a7018 | 2985 | &dwc->gadget->ep_list); |
8f1c99cd FB |
2986 | dep->endpoint.caps.type_iso = true; |
2987 | dep->endpoint.caps.type_bulk = true; | |
2988 | dep->endpoint.caps.type_int = true; | |
72246da4 | 2989 | |
8f1c99cd FB |
2990 | return dwc3_alloc_trb_pool(dep); |
2991 | } | |
72246da4 | 2992 | |
8f1c99cd FB |
2993 | static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) |
2994 | { | |
2995 | struct dwc3_ep *dep; | |
2996 | bool direction = epnum & 1; | |
2997 | int ret; | |
2998 | u8 num = epnum >> 1; | |
25b8ff68 | 2999 | |
8f1c99cd FB |
3000 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
3001 | if (!dep) | |
3002 | return -ENOMEM; | |
3003 | ||
3004 | dep->dwc = dwc; | |
3005 | dep->number = epnum; | |
3006 | dep->direction = direction; | |
3007 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); | |
3008 | dwc->eps[epnum] = dep; | |
d92021f6 TN |
3009 | dep->combo_num = 0; |
3010 | dep->start_cmd_status = 0; | |
8f1c99cd FB |
3011 | |
3012 | snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, | |
3013 | direction ? "in" : "out"); | |
3014 | ||
3015 | dep->endpoint.name = dep->name; | |
3016 | ||
3017 | if (!(dep->number > 1)) { | |
3018 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
3019 | dep->endpoint.comp_desc = NULL; | |
3020 | } | |
3021 | ||
8f1c99cd FB |
3022 | if (num == 0) |
3023 | ret = dwc3_gadget_init_control_endpoint(dep); | |
3024 | else if (direction) | |
3025 | ret = dwc3_gadget_init_in_endpoint(dep); | |
3026 | else | |
3027 | ret = dwc3_gadget_init_out_endpoint(dep); | |
3028 | ||
3029 | if (ret) | |
3030 | return ret; | |
a474d3b7 | 3031 | |
8f1c99cd FB |
3032 | dep->endpoint.caps.dir_in = direction; |
3033 | dep->endpoint.caps.dir_out = !direction; | |
a474d3b7 | 3034 | |
8f1c99cd FB |
3035 | INIT_LIST_HEAD(&dep->pending_list); |
3036 | INIT_LIST_HEAD(&dep->started_list); | |
d5443bbf | 3037 | INIT_LIST_HEAD(&dep->cancelled_list); |
8f1c99cd | 3038 | |
5ff90af9 JP |
3039 | dwc3_debugfs_create_endpoint_dir(dep); |
3040 | ||
8f1c99cd FB |
3041 | return 0; |
3042 | } | |
3043 | ||
3044 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) | |
3045 | { | |
3046 | u8 epnum; | |
3047 | ||
e81a7018 | 3048 | INIT_LIST_HEAD(&dwc->gadget->ep_list); |
8f1c99cd FB |
3049 | |
3050 | for (epnum = 0; epnum < total; epnum++) { | |
3051 | int ret; | |
3052 | ||
3053 | ret = dwc3_gadget_init_endpoint(dwc, epnum); | |
3054 | if (ret) | |
3055 | return ret; | |
72246da4 FB |
3056 | } |
3057 | ||
3058 | return 0; | |
3059 | } | |
3060 | ||
3061 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
3062 | { | |
3063 | struct dwc3_ep *dep; | |
3064 | u8 epnum; | |
3065 | ||
3066 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3067 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3068 | if (!dep) |
3069 | continue; | |
5bf8fae3 GC |
3070 | /* |
3071 | * Physical endpoints 0 and 1 are special; they form the | |
3072 | * bi-directional USB endpoint 0. | |
3073 | * | |
3074 | * For those two physical endpoints, we don't allocate a TRB | |
3075 | * pool nor do we add them the endpoints list. Due to that, we | |
3076 | * shouldn't do these two operations otherwise we would end up | |
3077 | * with all sorts of bugs when removing dwc3.ko. | |
3078 | */ | |
3079 | if (epnum != 0 && epnum != 1) { | |
3080 | dwc3_free_trb_pool(dep); | |
72246da4 | 3081 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 3082 | } |
72246da4 | 3083 | |
8562d5bf GKH |
3084 | debugfs_remove_recursive(debugfs_lookup(dep->name, |
3085 | debugfs_lookup(dev_name(dep->dwc->dev), | |
3086 | usb_debug_root))); | |
72246da4 FB |
3087 | kfree(dep); |
3088 | } | |
3089 | } | |
3090 | ||
72246da4 | 3091 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 3092 | |
8f608e8a FB |
3093 | static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, |
3094 | struct dwc3_request *req, struct dwc3_trb *trb, | |
3095 | const struct dwc3_event_depevt *event, int status, int chain) | |
72246da4 | 3096 | { |
72246da4 | 3097 | unsigned int count; |
72246da4 | 3098 | |
dc55c67e | 3099 | dwc3_ep_inc_deq(dep); |
a9c3ca5f | 3100 | |
2c4cbe6e | 3101 | trace_dwc3_complete_trb(dep, trb); |
09fe1f8d | 3102 | req->num_trbs--; |
2c4cbe6e | 3103 | |
e5b36ae2 FB |
3104 | /* |
3105 | * If we're in the middle of series of chained TRBs and we | |
3106 | * receive a short transfer along the way, DWC3 will skip | |
3107 | * through all TRBs including the last TRB in the chain (the | |
3108 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
3109 | * bit and SW has to do it manually. | |
3110 | * | |
3111 | * We're going to do that here to avoid problems of HW trying | |
3112 | * to use bogus TRBs for transfers. | |
3113 | */ | |
3114 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
3115 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
3116 | ||
6abfa0f5 TN |
3117 | /* |
3118 | * For isochronous transfers, the first TRB in a service interval must | |
3119 | * have the Isoc-First type. Track and report its interval frame number. | |
3120 | */ | |
3121 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
3122 | (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { | |
3123 | unsigned int frame_number; | |
3124 | ||
3125 | frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); | |
3126 | frame_number &= ~(dep->interval - 1); | |
3127 | req->request.frame_number = frame_number; | |
3128 | } | |
3129 | ||
c6267a51 | 3130 | /* |
a2841f41 TN |
3131 | * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If |
3132 | * this TRB points to the bounce buffer address, it's a MPS alignment | |
3133 | * TRB. Don't add it to req->remaining calculation. | |
c6267a51 | 3134 | */ |
a2841f41 TN |
3135 | if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) && |
3136 | trb->bph == upper_32_bits(dep->dwc->bounce_addr)) { | |
c6267a51 FB |
3137 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
3138 | return 1; | |
3139 | } | |
3140 | ||
e5ba5ec8 | 3141 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 3142 | req->remaining += count; |
e5ba5ec8 | 3143 | |
35b2719e FB |
3144 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
3145 | return 1; | |
3146 | ||
d80fe1b6 | 3147 | if (event->status & DEPEVT_STATUS_SHORT && !chain) |
e5ba5ec8 | 3148 | return 1; |
f99f53f2 | 3149 | |
e1003cb1 TN |
3150 | if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) && |
3151 | DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC) | |
3152 | return 1; | |
3153 | ||
5ee85897 AKV |
3154 | if ((trb->ctrl & DWC3_TRB_CTRL_IOC) || |
3155 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
e5ba5ec8 | 3156 | return 1; |
f99f53f2 | 3157 | |
e5ba5ec8 PA |
3158 | return 0; |
3159 | } | |
3160 | ||
d3692953 FB |
3161 | static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, |
3162 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
3163 | int status) | |
3164 | { | |
3165 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
3166 | struct scatterlist *sg = req->sg; | |
3167 | struct scatterlist *s; | |
25dda9fc | 3168 | unsigned int num_queued = req->num_queued_sgs; |
d3692953 FB |
3169 | unsigned int i; |
3170 | int ret = 0; | |
3171 | ||
25dda9fc | 3172 | for_each_sg(sg, s, num_queued, i) { |
d3692953 FB |
3173 | trb = &dep->trb_pool[dep->trb_dequeue]; |
3174 | ||
d3692953 | 3175 | req->sg = sg_next(s); |
25dda9fc | 3176 | req->num_queued_sgs--; |
d3692953 FB |
3177 | |
3178 | ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, | |
3179 | trb, event, status, true); | |
3180 | if (ret) | |
3181 | break; | |
3182 | } | |
3183 | ||
3184 | return ret; | |
3185 | } | |
3186 | ||
3187 | static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, | |
3188 | struct dwc3_request *req, const struct dwc3_event_depevt *event, | |
3189 | int status) | |
3190 | { | |
3191 | struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; | |
3192 | ||
3193 | return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, | |
3194 | event, status, false); | |
3195 | } | |
3196 | ||
e0c42ce5 FB |
3197 | static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) |
3198 | { | |
25dda9fc | 3199 | return req->num_pending_sgs == 0 && req->num_queued_sgs == 0; |
e0c42ce5 FB |
3200 | } |
3201 | ||
f38e35dd FB |
3202 | static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, |
3203 | const struct dwc3_event_depevt *event, | |
3204 | struct dwc3_request *req, int status) | |
3205 | { | |
fb893a52 | 3206 | int request_status; |
f38e35dd FB |
3207 | int ret; |
3208 | ||
25dda9fc | 3209 | if (req->request.num_mapped_sgs) |
f38e35dd FB |
3210 | ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, |
3211 | status); | |
3212 | else | |
3213 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, | |
3214 | status); | |
3215 | ||
690e5c2d TN |
3216 | req->request.actual = req->request.length - req->remaining; |
3217 | ||
3218 | if (!dwc3_gadget_ep_request_completed(req)) | |
3219 | goto out; | |
3220 | ||
1a22ec64 | 3221 | if (req->needs_extra_trb) { |
f38e35dd FB |
3222 | ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, |
3223 | status); | |
1a22ec64 | 3224 | req->needs_extra_trb = false; |
f38e35dd FB |
3225 | } |
3226 | ||
fb893a52 TN |
3227 | /* |
3228 | * The event status only reflects the status of the TRB with IOC set. | |
3229 | * For the requests that don't set interrupt on completion, the driver | |
3230 | * needs to check and return the status of the completed TRBs associated | |
3231 | * with the request. Use the status of the last TRB of the request. | |
3232 | */ | |
3233 | if (req->request.no_interrupt) { | |
3234 | struct dwc3_trb *trb; | |
3235 | ||
3236 | trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue); | |
3237 | switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) { | |
3238 | case DWC3_TRBSTS_MISSED_ISOC: | |
3239 | /* Isoc endpoint only */ | |
3240 | request_status = -EXDEV; | |
3241 | break; | |
3242 | case DWC3_TRB_STS_XFER_IN_PROG: | |
3243 | /* Applicable when End Transfer with ForceRM=0 */ | |
3244 | case DWC3_TRBSTS_SETUP_PENDING: | |
3245 | /* Control endpoint only */ | |
3246 | case DWC3_TRBSTS_OK: | |
3247 | default: | |
3248 | request_status = 0; | |
3249 | break; | |
3250 | } | |
3251 | } else { | |
3252 | request_status = status; | |
3253 | } | |
3254 | ||
3255 | dwc3_gadget_giveback(dep, req, request_status); | |
f38e35dd FB |
3256 | |
3257 | out: | |
3258 | return ret; | |
3259 | } | |
3260 | ||
12a3a4ad | 3261 | static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, |
8f608e8a | 3262 | const struct dwc3_event_depevt *event, int status) |
e5ba5ec8 | 3263 | { |
6afbdb57 | 3264 | struct dwc3_request *req; |
e5ba5ec8 | 3265 | |
b5d6478d | 3266 | while (!list_empty(&dep->started_list)) { |
fee73e61 | 3267 | int ret; |
e5b36ae2 | 3268 | |
b5d6478d | 3269 | req = next_request(&dep->started_list); |
f38e35dd FB |
3270 | ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, |
3271 | req, status); | |
58f0218a | 3272 | if (ret) |
72246da4 | 3273 | break; |
b5d6478d WC |
3274 | /* |
3275 | * The endpoint is disabled, let the dwc3_remove_requests() | |
3276 | * handle the cleanup. | |
3277 | */ | |
3278 | if (!dep->endpoint.desc) | |
3279 | break; | |
31162af4 | 3280 | } |
72246da4 FB |
3281 | } |
3282 | ||
d9feef97 TN |
3283 | static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep) |
3284 | { | |
3285 | struct dwc3_request *req; | |
02fa4b98 WC |
3286 | struct dwc3 *dwc = dep->dwc; |
3287 | ||
3288 | if (!dep->endpoint.desc || !dwc->pullups_connected || | |
3289 | !dwc->connected) | |
3290 | return false; | |
d9feef97 TN |
3291 | |
3292 | if (!list_empty(&dep->pending_list)) | |
3293 | return true; | |
3294 | ||
3295 | /* | |
3296 | * We only need to check the first entry of the started list. We can | |
3297 | * assume the completed requests are removed from the started list. | |
3298 | */ | |
3299 | req = next_request(&dep->started_list); | |
3300 | if (!req) | |
3301 | return false; | |
3302 | ||
3303 | return !dwc3_gadget_ep_request_completed(req); | |
3304 | } | |
3305 | ||
ee3638b8 FB |
3306 | static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, |
3307 | const struct dwc3_event_depevt *event) | |
3308 | { | |
f62afb49 | 3309 | dep->frame_number = event->parameters; |
ee3638b8 FB |
3310 | } |
3311 | ||
2e6e9e4b TN |
3312 | static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep, |
3313 | const struct dwc3_event_depevt *event, int status) | |
72246da4 | 3314 | { |
8f608e8a | 3315 | struct dwc3 *dwc = dep->dwc; |
2e6e9e4b | 3316 | bool no_started_trb = true; |
6d8a0196 | 3317 | |
5f2e7975 | 3318 | dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); |
fae2b904 | 3319 | |
b6842d49 TN |
3320 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) |
3321 | goto out; | |
3322 | ||
6637d81d AW |
3323 | if (!dep->endpoint.desc) |
3324 | return no_started_trb; | |
3325 | ||
f5e46aa4 MG |
3326 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
3327 | list_empty(&dep->started_list) && | |
3328 | (list_empty(&dep->pending_list) || status == -EXDEV)) | |
c5353b22 | 3329 | dwc3_stop_active_transfer(dep, true, true); |
d9feef97 | 3330 | else if (dwc3_gadget_ep_should_continue(dep)) |
2e6e9e4b TN |
3331 | if (__dwc3_gadget_kick_transfer(dep) == 0) |
3332 | no_started_trb = false; | |
6d8a0196 | 3333 | |
b6842d49 | 3334 | out: |
fae2b904 FB |
3335 | /* |
3336 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
3337 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
3338 | */ | |
9af21dd6 | 3339 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3340 | u32 reg; |
3341 | int i; | |
3342 | ||
3343 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 3344 | dep = dwc->eps[i]; |
fae2b904 FB |
3345 | |
3346 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
3347 | continue; | |
3348 | ||
aa3342c8 | 3349 | if (!list_empty(&dep->started_list)) |
2e6e9e4b | 3350 | return no_started_trb; |
fae2b904 FB |
3351 | } |
3352 | ||
3353 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3354 | reg |= dwc->u1u2; | |
3355 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3356 | ||
3357 | dwc->u1u2 = 0; | |
3358 | } | |
2e6e9e4b TN |
3359 | |
3360 | return no_started_trb; | |
3361 | } | |
3362 | ||
3363 | static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, | |
3364 | const struct dwc3_event_depevt *event) | |
3365 | { | |
3366 | int status = 0; | |
3367 | ||
44caa167 AW |
3368 | if (!dep->endpoint.desc) |
3369 | return; | |
3370 | ||
2e6e9e4b TN |
3371 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
3372 | dwc3_gadget_endpoint_frame_from_event(dep, event); | |
3373 | ||
3374 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3375 | status = -ECONNRESET; | |
3376 | ||
3377 | if (event->status & DEPEVT_STATUS_MISSED_ISOC) | |
3378 | status = -EXDEV; | |
3379 | ||
3380 | dwc3_gadget_endpoint_trbs_complete(dep, event, status); | |
72246da4 FB |
3381 | } |
3382 | ||
3eaecd0c TN |
3383 | static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep, |
3384 | const struct dwc3_event_depevt *event) | |
3385 | { | |
3386 | int status = 0; | |
3387 | ||
3388 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3389 | ||
3390 | if (event->status & DEPEVT_STATUS_BUSERR) | |
3391 | status = -ECONNRESET; | |
3392 | ||
e0d19563 TN |
3393 | if (dwc3_gadget_endpoint_trbs_complete(dep, event, status)) |
3394 | dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE; | |
72246da4 FB |
3395 | } |
3396 | ||
8f608e8a FB |
3397 | static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, |
3398 | const struct dwc3_event_depevt *event) | |
32033865 | 3399 | { |
ee3638b8 | 3400 | dwc3_gadget_endpoint_frame_from_event(dep, event); |
36f05d36 TN |
3401 | |
3402 | /* | |
3403 | * The XferNotReady event is generated only once before the endpoint | |
3404 | * starts. It will be generated again when END_TRANSFER command is | |
3405 | * issued. For some controller versions, the XferNotReady event may be | |
3406 | * generated while the END_TRANSFER command is still in process. Ignore | |
3407 | * it and wait for the next XferNotReady event after the command is | |
3408 | * completed. | |
3409 | */ | |
3410 | if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) | |
3411 | return; | |
3412 | ||
25abad6a | 3413 | (void) __dwc3_gadget_start_isoc(dep); |
32033865 FB |
3414 | } |
3415 | ||
8266b08e TN |
3416 | static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep, |
3417 | const struct dwc3_event_depevt *event) | |
3418 | { | |
3419 | u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters); | |
3420 | ||
3421 | if (cmd != DWC3_DEPCMD_ENDTRANSFER) | |
3422 | return; | |
3423 | ||
42160efc TN |
3424 | /* |
3425 | * The END_TRANSFER command will cause the controller to generate a | |
3426 | * NoStream Event, and it's not due to the host DP NoStream rejection. | |
3427 | * Ignore the next NoStream event. | |
3428 | */ | |
3429 | if (dep->stream_capable) | |
3430 | dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3431 | ||
8266b08e TN |
3432 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
3433 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
3434 | dwc3_gadget_ep_cleanup_cancelled_requests(dep); | |
3435 | ||
3436 | if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) { | |
3437 | struct dwc3 *dwc = dep->dwc; | |
3438 | ||
3439 | dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL; | |
3440 | if (dwc3_send_clear_stall_ep_cmd(dep)) { | |
3441 | struct usb_ep *ep0 = &dwc->eps[0]->endpoint; | |
3442 | ||
3443 | dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name); | |
3444 | if (dwc->delayed_status) | |
3445 | __dwc3_gadget_ep0_set_halt(ep0, 1); | |
3446 | return; | |
3447 | } | |
3448 | ||
3449 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); | |
3450 | if (dwc->delayed_status) | |
3451 | dwc3_ep0_send_delayed_status(dwc); | |
3452 | } | |
3453 | ||
3454 | if ((dep->flags & DWC3_EP_DELAY_START) && | |
3455 | !usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
3456 | __dwc3_gadget_kick_transfer(dep); | |
3457 | ||
3458 | dep->flags &= ~DWC3_EP_DELAY_START; | |
3459 | } | |
3460 | ||
140ca4cf TN |
3461 | static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep, |
3462 | const struct dwc3_event_depevt *event) | |
3463 | { | |
3464 | struct dwc3 *dwc = dep->dwc; | |
3465 | ||
3466 | if (event->status == DEPEVT_STREAMEVT_FOUND) { | |
3467 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3468 | goto out; | |
3469 | } | |
3470 | ||
3471 | /* Note: NoStream rejection event param value is 0 and not 0xFFFF */ | |
3472 | switch (event->parameters) { | |
3473 | case DEPEVT_STREAM_PRIME: | |
3474 | /* | |
3475 | * If the host can properly transition the endpoint state from | |
3476 | * idle to prime after a NoStream rejection, there's no need to | |
3477 | * force restarting the endpoint to reinitiate the stream. To | |
3478 | * simplify the check, assume the host follows the USB spec if | |
3479 | * it primed the endpoint more than once. | |
3480 | */ | |
3481 | if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) { | |
3482 | if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED) | |
3483 | dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM; | |
3484 | else | |
3485 | dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED; | |
3486 | } | |
3487 | ||
3488 | break; | |
3489 | case DEPEVT_STREAM_NOSTREAM: | |
3490 | if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) || | |
3491 | !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) || | |
3492 | !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)) | |
3493 | break; | |
3494 | ||
3495 | /* | |
3496 | * If the host rejects a stream due to no active stream, by the | |
3497 | * USB and xHCI spec, the endpoint will be put back to idle | |
3498 | * state. When the host is ready (buffer added/updated), it will | |
3499 | * prime the endpoint to inform the usb device controller. This | |
3500 | * triggers the device controller to issue ERDY to restart the | |
3501 | * stream. However, some hosts don't follow this and keep the | |
3502 | * endpoint in the idle state. No prime will come despite host | |
3503 | * streams are updated, and the device controller will not be | |
3504 | * triggered to generate ERDY to move the next stream data. To | |
3505 | * workaround this and maintain compatibility with various | |
3506 | * hosts, force to reinitate the stream until the host is ready | |
3507 | * instead of waiting for the host to prime the endpoint. | |
3508 | */ | |
b10e1c25 TN |
3509 | if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) { |
3510 | unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME; | |
3511 | ||
3512 | dwc3_send_gadget_generic_command(dwc, cmd, dep->number); | |
3513 | } else { | |
3514 | dep->flags |= DWC3_EP_DELAY_START; | |
3515 | dwc3_stop_active_transfer(dep, true, true); | |
3516 | return; | |
3517 | } | |
3518 | break; | |
140ca4cf TN |
3519 | } |
3520 | ||
3521 | out: | |
3522 | dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM; | |
3523 | } | |
3524 | ||
72246da4 FB |
3525 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
3526 | const struct dwc3_event_depevt *event) | |
3527 | { | |
3528 | struct dwc3_ep *dep; | |
3529 | u8 epnum = event->endpoint_number; | |
3530 | ||
3531 | dep = dwc->eps[epnum]; | |
3532 | ||
d7fd41c6 | 3533 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
3aec9915 | 3534 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) |
d7fd41c6 JD |
3535 | return; |
3536 | ||
3537 | /* Handle only EPCMDCMPLT when EP disabled */ | |
3538 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
3539 | return; | |
3540 | } | |
3336abb5 | 3541 | |
72246da4 FB |
3542 | if (epnum == 0 || epnum == 1) { |
3543 | dwc3_ep0_interrupt(dwc, event); | |
3544 | return; | |
3545 | } | |
3546 | ||
3547 | switch (event->endpoint_event) { | |
72246da4 | 3548 | case DWC3_DEPEVT_XFERINPROGRESS: |
8f608e8a | 3549 | dwc3_gadget_endpoint_transfer_in_progress(dep, event); |
72246da4 FB |
3550 | break; |
3551 | case DWC3_DEPEVT_XFERNOTREADY: | |
8f608e8a | 3552 | dwc3_gadget_endpoint_transfer_not_ready(dep, event); |
879631aa | 3553 | break; |
72246da4 | 3554 | case DWC3_DEPEVT_EPCMDCMPLT: |
8266b08e | 3555 | dwc3_gadget_endpoint_command_complete(dep, event); |
76a638f8 | 3556 | break; |
742a4fff | 3557 | case DWC3_DEPEVT_XFERCOMPLETE: |
3eaecd0c TN |
3558 | dwc3_gadget_endpoint_transfer_complete(dep, event); |
3559 | break; | |
3560 | case DWC3_DEPEVT_STREAMEVT: | |
140ca4cf TN |
3561 | dwc3_gadget_endpoint_stream_event(dep, event); |
3562 | break; | |
76a638f8 | 3563 | case DWC3_DEPEVT_RXTXFIFOEVT: |
72246da4 FB |
3564 | break; |
3565 | } | |
3566 | } | |
3567 | ||
3568 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
3569 | { | |
40edb522 | 3570 | if (dwc->async_callbacks && dwc->gadget_driver->disconnect) { |
72246da4 | 3571 | spin_unlock(&dwc->lock); |
e81a7018 | 3572 | dwc->gadget_driver->disconnect(dwc->gadget); |
72246da4 FB |
3573 | spin_lock(&dwc->lock); |
3574 | } | |
3575 | } | |
3576 | ||
bc5ba2e0 FB |
3577 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
3578 | { | |
40edb522 | 3579 | if (dwc->async_callbacks && dwc->gadget_driver->suspend) { |
bc5ba2e0 | 3580 | spin_unlock(&dwc->lock); |
e81a7018 | 3581 | dwc->gadget_driver->suspend(dwc->gadget); |
bc5ba2e0 FB |
3582 | spin_lock(&dwc->lock); |
3583 | } | |
3584 | } | |
3585 | ||
3586 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
3587 | { | |
40edb522 | 3588 | if (dwc->async_callbacks && dwc->gadget_driver->resume) { |
bc5ba2e0 | 3589 | spin_unlock(&dwc->lock); |
e81a7018 | 3590 | dwc->gadget_driver->resume(dwc->gadget); |
5c7b3b02 | 3591 | spin_lock(&dwc->lock); |
8e74475b FB |
3592 | } |
3593 | } | |
3594 | ||
3595 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
3596 | { | |
3597 | if (!dwc->gadget_driver) | |
3598 | return; | |
3599 | ||
40edb522 | 3600 | if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) { |
8e74475b | 3601 | spin_unlock(&dwc->lock); |
e81a7018 | 3602 | usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver); |
bc5ba2e0 FB |
3603 | spin_lock(&dwc->lock); |
3604 | } | |
3605 | } | |
3606 | ||
c5353b22 FB |
3607 | static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, |
3608 | bool interrupt) | |
72246da4 | 3609 | { |
72246da4 FB |
3610 | struct dwc3_gadget_ep_cmd_params params; |
3611 | u32 cmd; | |
3612 | int ret; | |
3613 | ||
c58d8bfc TN |
3614 | if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || |
3615 | (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3daf74d7 PA |
3616 | return; |
3617 | ||
57911504 PA |
3618 | /* |
3619 | * NOTICE: We are violating what the Databook says about the | |
3620 | * EndTransfer command. Ideally we would _always_ wait for the | |
3621 | * EndTransfer Command Completion IRQ, but that's causing too | |
3622 | * much trouble synchronizing between us and gadget driver. | |
3623 | * | |
3624 | * We have discussed this with the IP Provider and it was | |
cf2f8b63 | 3625 | * suggested to giveback all requests here. |
57911504 PA |
3626 | * |
3627 | * Note also that a similar handling was tested by Synopsys | |
3628 | * (thanks a lot Paul) and nothing bad has come out of it. | |
cf2f8b63 TN |
3629 | * In short, what we're doing is issuing EndTransfer with |
3630 | * CMDIOC bit set and delay kicking transfer until the | |
3631 | * EndTransfer command had completed. | |
06281d46 JY |
3632 | * |
3633 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
3634 | * supports a mode to work around the above limitation. The | |
3635 | * software can poll the CMDACT bit in the DEPCMD register | |
3636 | * after issuing a EndTransfer command. This mode is enabled | |
3637 | * by writing GUCTL2[14]. This polling is already done in the | |
3638 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
3639 | * enabled, the EndTransfer command will have completed upon | |
cf2f8b63 | 3640 | * returning from this function. |
06281d46 JY |
3641 | * |
3642 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
3643 | */ |
3644 | ||
3daf74d7 | 3645 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 | 3646 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
c5353b22 | 3647 | cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; |
b4996a86 | 3648 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 3649 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 3650 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 3651 | WARN_ON_ONCE(ret); |
b4996a86 | 3652 | dep->resource_index = 0; |
06281d46 | 3653 | |
d3abda5a TN |
3654 | if (!interrupt) |
3655 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
c58d8bfc TN |
3656 | else |
3657 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
72246da4 FB |
3658 | } |
3659 | ||
72246da4 FB |
3660 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
3661 | { | |
3662 | u32 epnum; | |
3663 | ||
3664 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
3665 | struct dwc3_ep *dep; | |
72246da4 FB |
3666 | int ret; |
3667 | ||
3668 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
3669 | if (!dep) |
3670 | continue; | |
72246da4 FB |
3671 | |
3672 | if (!(dep->flags & DWC3_EP_STALL)) | |
3673 | continue; | |
3674 | ||
3675 | dep->flags &= ~DWC3_EP_STALL; | |
3676 | ||
50c763f8 | 3677 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
3678 | WARN_ON_ONCE(ret); |
3679 | } | |
3680 | } | |
3681 | ||
3682 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
3683 | { | |
c4430a26 FB |
3684 | int reg; |
3685 | ||
1b6009ea TN |
3686 | dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); |
3687 | ||
72246da4 FB |
3688 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3689 | reg &= ~DWC3_DCTL_INITU1ENA; | |
72246da4 | 3690 | reg &= ~DWC3_DCTL_INITU2ENA; |
5b738211 | 3691 | dwc3_gadget_dctl_write_safe(dwc, reg); |
72246da4 | 3692 | |
72246da4 FB |
3693 | dwc3_disconnect_gadget(dwc); |
3694 | ||
e81a7018 | 3695 | dwc->gadget->speed = USB_SPEED_UNKNOWN; |
df62df56 | 3696 | dwc->setup_packet_pending = false; |
e81a7018 | 3697 | usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
3698 | |
3699 | dwc->connected = false; | |
72246da4 FB |
3700 | } |
3701 | ||
72246da4 FB |
3702 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
3703 | { | |
3704 | u32 reg; | |
3705 | ||
71ca43f3 WC |
3706 | /* |
3707 | * Ideally, dwc3_reset_gadget() would trigger the function | |
3708 | * drivers to stop any active transfers through ep disable. | |
3709 | * However, for functions which defer ep disable, such as mass | |
3710 | * storage, we will need to rely on the call to stop active | |
3711 | * transfers here, and avoid allowing of request queuing. | |
3712 | */ | |
3713 | dwc->connected = false; | |
3714 | ||
df62df56 FB |
3715 | /* |
3716 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
3717 | * would cause a missing Disconnect Event if there's a | |
3718 | * pending Setup Packet in the FIFO. | |
3719 | * | |
3720 | * There's no suggested workaround on the official Bug | |
3721 | * report, which states that "unless the driver/application | |
3722 | * is doing any special handling of a disconnect event, | |
3723 | * there is no functional issue". | |
3724 | * | |
3725 | * Unfortunately, it turns out that we _do_ some special | |
3726 | * handling of a disconnect event, namely complete all | |
3727 | * pending transfers, notify gadget driver of the | |
3728 | * disconnection, and so on. | |
3729 | * | |
3730 | * Our suggested workaround is to follow the Disconnect | |
3731 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
3732 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
3733 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
3734 | * same endpoint. |
3735 | * | |
3736 | * Refers to: | |
3737 | * | |
3738 | * STAR#9000466709: RTL: Device : Disconnect event not | |
3739 | * generated if setup packet pending in FIFO | |
3740 | */ | |
9af21dd6 | 3741 | if (DWC3_VER_IS_PRIOR(DWC3, 188A)) { |
df62df56 FB |
3742 | if (dwc->setup_packet_pending) |
3743 | dwc3_gadget_disconnect_interrupt(dwc); | |
3744 | } | |
3745 | ||
8e74475b | 3746 | dwc3_reset_gadget(dwc); |
ae7e8610 WC |
3747 | /* |
3748 | * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a | |
3749 | * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW | |
3750 | * needs to ensure that it sends "a DEPENDXFER command for any active | |
3751 | * transfers." | |
3752 | */ | |
3753 | dwc3_stop_active_transfers(dwc); | |
f09ddcfc | 3754 | dwc->connected = true; |
72246da4 FB |
3755 | |
3756 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3757 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
5b738211 | 3758 | dwc3_gadget_dctl_write_safe(dwc, reg); |
3b637367 | 3759 | dwc->test_mode = false; |
72246da4 FB |
3760 | dwc3_clear_stall_all_ep(dwc); |
3761 | ||
3762 | /* Reset device address to zero */ | |
3763 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3764 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
3765 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
3766 | } |
3767 | ||
72246da4 FB |
3768 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
3769 | { | |
72246da4 FB |
3770 | struct dwc3_ep *dep; |
3771 | int ret; | |
3772 | u32 reg; | |
f551037c | 3773 | u8 lanes = 1; |
72246da4 FB |
3774 | u8 speed; |
3775 | ||
72246da4 FB |
3776 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
3777 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
3778 | dwc->speed = speed; | |
3779 | ||
f551037c TN |
3780 | if (DWC3_IP_IS(DWC32)) |
3781 | lanes = DWC3_DSTS_CONNLANES(reg) + 1; | |
3782 | ||
3783 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; | |
3784 | ||
5fb6fdaf JY |
3785 | /* |
3786 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
3787 | * each time on Connect Done. | |
3788 | * | |
3789 | * Currently we always use the reset value. If any platform | |
3790 | * wants to set this to a different value, we need to add a | |
3791 | * setting and update GCTL.RAMCLKSEL here. | |
3792 | */ | |
72246da4 FB |
3793 | |
3794 | switch (speed) { | |
2da9ad76 | 3795 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b | 3796 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3797 | dwc->gadget->ep0->maxpacket = 512; |
3798 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
f551037c TN |
3799 | |
3800 | if (lanes > 1) | |
3801 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x2; | |
3802 | else | |
3803 | dwc->gadget->ssp_rate = USB_SSP_GEN_2x1; | |
7580862b | 3804 | break; |
2da9ad76 | 3805 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
3806 | /* |
3807 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
3808 | * would cause a missing USB3 Reset event. | |
3809 | * | |
3810 | * In such situations, we should force a USB3 Reset | |
3811 | * event by calling our dwc3_gadget_reset_interrupt() | |
3812 | * routine. | |
3813 | * | |
3814 | * Refers to: | |
3815 | * | |
3816 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
3817 | * not be generated always when the link enters poll | |
3818 | */ | |
9af21dd6 | 3819 | if (DWC3_VER_IS_PRIOR(DWC3, 190A)) |
05870c5b FB |
3820 | dwc3_gadget_reset_interrupt(dwc); |
3821 | ||
72246da4 | 3822 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
e81a7018 PC |
3823 | dwc->gadget->ep0->maxpacket = 512; |
3824 | dwc->gadget->speed = USB_SPEED_SUPER; | |
f551037c TN |
3825 | |
3826 | if (lanes > 1) { | |
3827 | dwc->gadget->speed = USB_SPEED_SUPER_PLUS; | |
3828 | dwc->gadget->ssp_rate = USB_SSP_GEN_1x2; | |
3829 | } | |
72246da4 | 3830 | break; |
2da9ad76 | 3831 | case DWC3_DSTS_HIGHSPEED: |
72246da4 | 3832 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3833 | dwc->gadget->ep0->maxpacket = 64; |
3834 | dwc->gadget->speed = USB_SPEED_HIGH; | |
72246da4 | 3835 | break; |
9418ee15 | 3836 | case DWC3_DSTS_FULLSPEED: |
72246da4 | 3837 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
e81a7018 PC |
3838 | dwc->gadget->ep0->maxpacket = 64; |
3839 | dwc->gadget->speed = USB_SPEED_FULL; | |
72246da4 | 3840 | break; |
72246da4 FB |
3841 | } |
3842 | ||
e81a7018 | 3843 | dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket; |
61800263 | 3844 | |
2b758350 PA |
3845 | /* Enable USB2 LPM Capability */ |
3846 | ||
9af21dd6 | 3847 | if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) && |
475e8be5 | 3848 | !dwc->usb2_gadget_lpm_disable && |
2da9ad76 JY |
3849 | (speed != DWC3_DSTS_SUPERSPEED) && |
3850 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
3851 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
3852 | reg |= DWC3_DCFG_LPM_CAP; | |
3853 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3854 | ||
3855 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3856 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
3857 | ||
16fe4f30 TN |
3858 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | |
3859 | (dwc->is_utmi_l1_suspend << 4)); | |
2b758350 | 3860 | |
80caf7d2 HR |
3861 | /* |
3862 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
3863 | * DCFG.LPMCap is set, core responses with an ACK and the | |
3864 | * BESL value in the LPM token is less than or equal to LPM | |
3865 | * NYET threshold. | |
3866 | */ | |
9af21dd6 | 3867 | WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum, |
9165dabb | 3868 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 | 3869 | |
9af21dd6 | 3870 | if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) |
2e487d28 | 3871 | reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); |
80caf7d2 | 3872 | |
5b738211 | 3873 | dwc3_gadget_dctl_write_safe(dwc, reg); |
356363bf | 3874 | } else { |
475e8be5 TN |
3875 | if (dwc->usb2_gadget_lpm_disable) { |
3876 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
3877 | reg &= ~DWC3_DCFG_LPM_CAP; | |
3878 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
3879 | } | |
3880 | ||
356363bf FB |
3881 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
3882 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
5b738211 | 3883 | dwc3_gadget_dctl_write_safe(dwc, reg); |
2b758350 PA |
3884 | } |
3885 | ||
72246da4 | 3886 | dep = dwc->eps[0]; |
a2d23f08 | 3887 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3888 | if (ret) { |
3889 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3890 | return; | |
3891 | } | |
3892 | ||
3893 | dep = dwc->eps[1]; | |
a2d23f08 | 3894 | ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); |
72246da4 FB |
3895 | if (ret) { |
3896 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
3897 | return; | |
3898 | } | |
3899 | ||
3900 | /* | |
3901 | * Configure PHY via GUSB3PIPECTLn if required. | |
3902 | * | |
3903 | * Update GTXFIFOSIZn | |
3904 | * | |
3905 | * In both cases reset values should be sufficient. | |
3906 | */ | |
3907 | } | |
3908 | ||
3909 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
3910 | { | |
72246da4 FB |
3911 | /* |
3912 | * TODO take core out of low power mode when that's | |
3913 | * implemented. | |
3914 | */ | |
3915 | ||
40edb522 | 3916 | if (dwc->async_callbacks && dwc->gadget_driver->resume) { |
ad14d4e0 | 3917 | spin_unlock(&dwc->lock); |
e81a7018 | 3918 | dwc->gadget_driver->resume(dwc->gadget); |
ad14d4e0 JL |
3919 | spin_lock(&dwc->lock); |
3920 | } | |
72246da4 FB |
3921 | } |
3922 | ||
3923 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
3924 | unsigned int evtinfo) | |
3925 | { | |
fae2b904 | 3926 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
3927 | unsigned int pwropt; |
3928 | ||
3929 | /* | |
3930 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
3931 | * Hibernation mode enabled which would show up when device detects | |
3932 | * host-initiated U3 exit. | |
3933 | * | |
3934 | * In that case, device will generate a Link State Change Interrupt | |
3935 | * from U3 to RESUME which is only necessary if Hibernation is | |
3936 | * configured in. | |
3937 | * | |
3938 | * There are no functional changes due to such spurious event and we | |
3939 | * just need to ignore it. | |
3940 | * | |
3941 | * Refers to: | |
3942 | * | |
3943 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
3944 | * operational mode | |
3945 | */ | |
3946 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
9af21dd6 | 3947 | if (DWC3_VER_IS_PRIOR(DWC3, 250A) && |
0b0cc1cd FB |
3948 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { |
3949 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
3950 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
3951 | return; |
3952 | } | |
3953 | } | |
fae2b904 FB |
3954 | |
3955 | /* | |
3956 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
3957 | * on the link partner, the USB session might do multiple entry/exit | |
3958 | * of low power states before a transfer takes place. | |
3959 | * | |
3960 | * Due to this problem, we might experience lower throughput. The | |
3961 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
3962 | * transitioning from U1/U2 to U0 and enable those bits again | |
3963 | * after a transfer completes and there are no pending transfers | |
3964 | * on any of the enabled endpoints. | |
3965 | * | |
3966 | * This is the first half of that workaround. | |
3967 | * | |
3968 | * Refers to: | |
3969 | * | |
3970 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
3971 | * core send LGO_Ux entering U0 | |
3972 | */ | |
9af21dd6 | 3973 | if (DWC3_VER_IS_PRIOR(DWC3, 183A)) { |
fae2b904 FB |
3974 | if (next == DWC3_LINK_STATE_U0) { |
3975 | u32 u1u2; | |
3976 | u32 reg; | |
3977 | ||
3978 | switch (dwc->link_state) { | |
3979 | case DWC3_LINK_STATE_U1: | |
3980 | case DWC3_LINK_STATE_U2: | |
3981 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
3982 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
3983 | | DWC3_DCTL_ACCEPTU2ENA | |
3984 | | DWC3_DCTL_INITU1ENA | |
3985 | | DWC3_DCTL_ACCEPTU1ENA); | |
3986 | ||
3987 | if (!dwc->u1u2) | |
3988 | dwc->u1u2 = reg & u1u2; | |
3989 | ||
3990 | reg &= ~u1u2; | |
3991 | ||
5b738211 | 3992 | dwc3_gadget_dctl_write_safe(dwc, reg); |
fae2b904 FB |
3993 | break; |
3994 | default: | |
3995 | /* do nothing */ | |
3996 | break; | |
3997 | } | |
3998 | } | |
3999 | } | |
4000 | ||
bc5ba2e0 FB |
4001 | switch (next) { |
4002 | case DWC3_LINK_STATE_U1: | |
4003 | if (dwc->speed == USB_SPEED_SUPER) | |
4004 | dwc3_suspend_gadget(dwc); | |
4005 | break; | |
4006 | case DWC3_LINK_STATE_U2: | |
4007 | case DWC3_LINK_STATE_U3: | |
4008 | dwc3_suspend_gadget(dwc); | |
4009 | break; | |
4010 | case DWC3_LINK_STATE_RESUME: | |
4011 | dwc3_resume_gadget(dwc); | |
4012 | break; | |
4013 | default: | |
4014 | /* do nothing */ | |
4015 | break; | |
4016 | } | |
4017 | ||
e57ebc1d | 4018 | dwc->link_state = next; |
72246da4 FB |
4019 | } |
4020 | ||
72704f87 BW |
4021 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
4022 | unsigned int evtinfo) | |
4023 | { | |
4024 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
4025 | ||
4026 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
4027 | dwc3_suspend_gadget(dwc); | |
4028 | ||
4029 | dwc->link_state = next; | |
4030 | } | |
4031 | ||
e1dadd3b FB |
4032 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
4033 | unsigned int evtinfo) | |
4034 | { | |
4035 | unsigned int is_ss = evtinfo & BIT(4); | |
4036 | ||
bfad65ee | 4037 | /* |
e1dadd3b FB |
4038 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
4039 | * have a known issue which can cause USB CV TD.9.23 to fail | |
4040 | * randomly. | |
4041 | * | |
4042 | * Because of this issue, core could generate bogus hibernation | |
4043 | * events which SW needs to ignore. | |
4044 | * | |
4045 | * Refers to: | |
4046 | * | |
4047 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
4048 | * Device Fallback from SuperSpeed | |
4049 | */ | |
4050 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
4051 | return; | |
4052 | ||
4053 | /* enter hibernation here */ | |
4054 | } | |
4055 | ||
72246da4 FB |
4056 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
4057 | const struct dwc3_event_devt *event) | |
4058 | { | |
4059 | switch (event->type) { | |
4060 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
4061 | dwc3_gadget_disconnect_interrupt(dwc); | |
4062 | break; | |
4063 | case DWC3_DEVICE_EVENT_RESET: | |
4064 | dwc3_gadget_reset_interrupt(dwc); | |
4065 | break; | |
4066 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
4067 | dwc3_gadget_conndone_interrupt(dwc); | |
4068 | break; | |
4069 | case DWC3_DEVICE_EVENT_WAKEUP: | |
4070 | dwc3_gadget_wakeup_interrupt(dwc); | |
4071 | break; | |
e1dadd3b FB |
4072 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
4073 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
4074 | "unexpected hibernation event\n")) | |
4075 | break; | |
4076 | ||
4077 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
4078 | break; | |
72246da4 FB |
4079 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
4080 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
4081 | break; | |
6f26ebb7 | 4082 | case DWC3_DEVICE_EVENT_SUSPEND: |
72704f87 | 4083 | /* It changed to be suspend event for version 2.30a and above */ |
9af21dd6 | 4084 | if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) { |
72704f87 BW |
4085 | /* |
4086 | * Ignore suspend event until the gadget enters into | |
4087 | * USB_STATE_CONFIGURED state. | |
4088 | */ | |
e81a7018 | 4089 | if (dwc->gadget->state >= USB_STATE_CONFIGURED) |
72704f87 BW |
4090 | dwc3_gadget_suspend_interrupt(dwc, |
4091 | event->event_info); | |
4092 | } | |
72246da4 FB |
4093 | break; |
4094 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 4095 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 4096 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 4097 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
4098 | break; |
4099 | default: | |
e9f2aa87 | 4100 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
4101 | } |
4102 | } | |
4103 | ||
4104 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
4105 | const union dwc3_event *event) | |
4106 | { | |
43c96be1 | 4107 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 4108 | |
dfc5e805 FB |
4109 | if (!event->type.is_devspec) |
4110 | dwc3_endpoint_interrupt(dwc, &event->depevt); | |
4111 | else if (event->type.type == DWC3_EVENT_TYPE_DEV) | |
72246da4 | 4112 | dwc3_gadget_interrupt(dwc, &event->devt); |
dfc5e805 | 4113 | else |
72246da4 | 4114 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); |
72246da4 FB |
4115 | } |
4116 | ||
dea520a4 | 4117 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 4118 | { |
dea520a4 | 4119 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 4120 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 4121 | int left; |
e8adfc30 | 4122 | u32 reg; |
b15a762f | 4123 | |
f42f2447 | 4124 | left = evt->count; |
b15a762f | 4125 | |
f42f2447 FB |
4126 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
4127 | return IRQ_NONE; | |
b15a762f | 4128 | |
f42f2447 FB |
4129 | while (left > 0) { |
4130 | union dwc3_event event; | |
b15a762f | 4131 | |
ebbb2d59 | 4132 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 4133 | |
f42f2447 | 4134 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 4135 | |
f42f2447 FB |
4136 | /* |
4137 | * FIXME we wrap around correctly to the next entry as | |
4138 | * almost all entries are 4 bytes in size. There is one | |
4139 | * entry which has 12 bytes which is a regular entry | |
4140 | * followed by 8 bytes data. ATM I don't know how | |
4141 | * things are organized if we get next to the a | |
4142 | * boundary so I worry about that once we try to handle | |
4143 | * that. | |
4144 | */ | |
caefe6c7 | 4145 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 4146 | left -= 4; |
f42f2447 | 4147 | } |
b15a762f | 4148 | |
f42f2447 | 4149 | evt->count = 0; |
f42f2447 | 4150 | ret = IRQ_HANDLED; |
b15a762f | 4151 | |
f42f2447 | 4152 | /* Unmask interrupt */ |
660e9bde | 4153 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 4154 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 4155 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 4156 | |
cf40b86b JY |
4157 | if (dwc->imod_interval) { |
4158 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
4159 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
4160 | } | |
4161 | ||
9abd267d TN |
4162 | /* Keep the clearing of DWC3_EVENT_PENDING at the end */ |
4163 | evt->flags &= ~DWC3_EVENT_PENDING; | |
4164 | ||
f42f2447 FB |
4165 | return ret; |
4166 | } | |
e8adfc30 | 4167 | |
dea520a4 | 4168 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 4169 | { |
dea520a4 FB |
4170 | struct dwc3_event_buffer *evt = _evt; |
4171 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 4172 | unsigned long flags; |
f42f2447 | 4173 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 4174 | |
a43b7059 | 4175 | local_bh_disable(); |
e5f68b4a | 4176 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 4177 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 4178 | spin_unlock_irqrestore(&dwc->lock, flags); |
a43b7059 | 4179 | local_bh_enable(); |
b15a762f FB |
4180 | |
4181 | return ret; | |
4182 | } | |
4183 | ||
dea520a4 | 4184 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 4185 | { |
dea520a4 | 4186 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 4187 | u32 amount; |
72246da4 | 4188 | u32 count; |
e8adfc30 | 4189 | u32 reg; |
72246da4 | 4190 | |
fc8bb91b FB |
4191 | if (pm_runtime_suspended(dwc->dev)) { |
4192 | pm_runtime_get(dwc->dev); | |
4193 | disable_irq_nosync(dwc->irq_gadget); | |
4194 | dwc->pending_events = true; | |
4195 | return IRQ_HANDLED; | |
4196 | } | |
4197 | ||
d325a1de TN |
4198 | /* |
4199 | * With PCIe legacy interrupt, test shows that top-half irq handler can | |
4200 | * be called again after HW interrupt deassertion. Check if bottom-half | |
4201 | * irq event handler completes before caching new event to prevent | |
4202 | * losing events. | |
4203 | */ | |
4204 | if (evt->flags & DWC3_EVENT_PENDING) | |
4205 | return IRQ_HANDLED; | |
4206 | ||
660e9bde | 4207 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
4208 | count &= DWC3_GEVNTCOUNT_MASK; |
4209 | if (!count) | |
4210 | return IRQ_NONE; | |
4211 | ||
b15a762f FB |
4212 | evt->count = count; |
4213 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 4214 | |
e8adfc30 | 4215 | /* Mask interrupt */ |
660e9bde | 4216 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 4217 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 4218 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 4219 | |
ebbb2d59 JY |
4220 | amount = min(count, evt->length - evt->lpos); |
4221 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
4222 | ||
4223 | if (amount < count) | |
4224 | memcpy(evt->cache, evt->buf, count - amount); | |
4225 | ||
65aca320 JY |
4226 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
4227 | ||
b15a762f | 4228 | return IRQ_WAKE_THREAD; |
72246da4 FB |
4229 | } |
4230 | ||
dea520a4 | 4231 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 4232 | { |
dea520a4 | 4233 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 4234 | |
dea520a4 | 4235 | return dwc3_check_event_buf(evt); |
72246da4 FB |
4236 | } |
4237 | ||
6db3812e FB |
4238 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
4239 | { | |
4240 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
4241 | int irq; | |
4242 | ||
f146b40b | 4243 | irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral"); |
6db3812e FB |
4244 | if (irq > 0) |
4245 | goto out; | |
4246 | ||
4247 | if (irq == -EPROBE_DEFER) | |
4248 | goto out; | |
4249 | ||
f146b40b | 4250 | irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3"); |
6db3812e FB |
4251 | if (irq > 0) |
4252 | goto out; | |
4253 | ||
4254 | if (irq == -EPROBE_DEFER) | |
4255 | goto out; | |
4256 | ||
4257 | irq = platform_get_irq(dwc3_pdev, 0); | |
4258 | if (irq > 0) | |
4259 | goto out; | |
4260 | ||
6db3812e FB |
4261 | if (!irq) |
4262 | irq = -EINVAL; | |
4263 | ||
4264 | out: | |
4265 | return irq; | |
4266 | } | |
4267 | ||
e81a7018 PC |
4268 | static void dwc_gadget_release(struct device *dev) |
4269 | { | |
4270 | struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev); | |
4271 | ||
4272 | kfree(gadget); | |
4273 | } | |
4274 | ||
72246da4 | 4275 | /** |
bfad65ee | 4276 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 4277 | * @dwc: pointer to our controller context structure |
72246da4 FB |
4278 | * |
4279 | * Returns 0 on success otherwise negative errno. | |
4280 | */ | |
41ac7b3a | 4281 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 4282 | { |
6db3812e FB |
4283 | int ret; |
4284 | int irq; | |
e81a7018 | 4285 | struct device *dev; |
9522def4 | 4286 | |
6db3812e FB |
4287 | irq = dwc3_gadget_get_irq(dwc); |
4288 | if (irq < 0) { | |
4289 | ret = irq; | |
4290 | goto err0; | |
9522def4 RQ |
4291 | } |
4292 | ||
4293 | dwc->irq_gadget = irq; | |
72246da4 | 4294 | |
d64ff406 AB |
4295 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
4296 | sizeof(*dwc->ep0_trb) * 2, | |
4297 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
4298 | if (!dwc->ep0_trb) { |
4299 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
4300 | ret = -ENOMEM; | |
7d5e650a | 4301 | goto err0; |
72246da4 FB |
4302 | } |
4303 | ||
4199c5f8 | 4304 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 4305 | if (!dwc->setup_buf) { |
72246da4 | 4306 | ret = -ENOMEM; |
7d5e650a | 4307 | goto err1; |
72246da4 FB |
4308 | } |
4309 | ||
905dc04e FB |
4310 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
4311 | &dwc->bounce_addr, GFP_KERNEL); | |
4312 | if (!dwc->bounce) { | |
4313 | ret = -ENOMEM; | |
d6e5a549 | 4314 | goto err2; |
905dc04e FB |
4315 | } |
4316 | ||
bb014736 | 4317 | init_completion(&dwc->ep0_in_setup); |
e81a7018 PC |
4318 | dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL); |
4319 | if (!dwc->gadget) { | |
4320 | ret = -ENOMEM; | |
4321 | goto err3; | |
4322 | } | |
bb014736 | 4323 | |
e81a7018 | 4324 | |
268bbde7 | 4325 | usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release); |
e81a7018 PC |
4326 | dev = &dwc->gadget->dev; |
4327 | dev->platform_data = dwc; | |
4328 | dwc->gadget->ops = &dwc3_gadget_ops; | |
4329 | dwc->gadget->speed = USB_SPEED_UNKNOWN; | |
f551037c | 4330 | dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN; |
e81a7018 PC |
4331 | dwc->gadget->sg_supported = true; |
4332 | dwc->gadget->name = "dwc3-gadget"; | |
475e8be5 | 4333 | dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable; |
72246da4 | 4334 | |
b9e51b2b BM |
4335 | /* |
4336 | * FIXME We might be setting max_speed to <SUPER, however versions | |
4337 | * <2.20a of dwc3 have an issue with metastability (documented | |
4338 | * elsewhere in this driver) which tells us we can't set max speed to | |
4339 | * anything lower than SUPER. | |
4340 | * | |
4341 | * Because gadget.max_speed is only used by composite.c and function | |
4342 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
4343 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
4344 | * together with our BOS descriptor as that could confuse host into | |
4345 | * thinking we can handle super speed. | |
4346 | * | |
4347 | * Note that, in fact, we won't even support GetBOS requests when speed | |
4348 | * is less than super speed because we don't have means, yet, to tell | |
4349 | * composite.c that we are USB 2.0 + LPM ECN. | |
4350 | */ | |
9af21dd6 | 4351 | if (DWC3_VER_IS_PRIOR(DWC3, 220A) && |
42bf02ec | 4352 | !dwc->dis_metastability_quirk) |
5eb30ced | 4353 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
4354 | dwc->revision); |
4355 | ||
e81a7018 | 4356 | dwc->gadget->max_speed = dwc->maximum_speed; |
67848146 | 4357 | dwc->gadget->max_ssp_rate = dwc->max_ssp_rate; |
b9e51b2b | 4358 | |
72246da4 FB |
4359 | /* |
4360 | * REVISIT: Here we should clear all pending IRQs to be | |
4361 | * sure we're starting from a well known location. | |
4362 | */ | |
4363 | ||
f3bcfc7e | 4364 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 4365 | if (ret) |
e81a7018 | 4366 | goto err4; |
72246da4 | 4367 | |
e81a7018 | 4368 | ret = usb_add_gadget(dwc->gadget); |
72246da4 | 4369 | if (ret) { |
e81a7018 PC |
4370 | dev_err(dwc->dev, "failed to add gadget\n"); |
4371 | goto err5; | |
72246da4 FB |
4372 | } |
4373 | ||
072cab8a TN |
4374 | if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS) |
4375 | dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate); | |
4376 | else | |
4377 | dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed); | |
169e3b68 | 4378 | |
72246da4 FB |
4379 | return 0; |
4380 | ||
e81a7018 | 4381 | err5: |
d6e5a549 | 4382 | dwc3_gadget_free_endpoints(dwc); |
e81a7018 PC |
4383 | err4: |
4384 | usb_put_gadget(dwc->gadget); | |
03715ea2 | 4385 | dwc->gadget = NULL; |
7d5e650a | 4386 | err3: |
d6e5a549 FB |
4387 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
4388 | dwc->bounce_addr); | |
5812b1c2 | 4389 | |
7d5e650a | 4390 | err2: |
0fc9a1be | 4391 | kfree(dwc->setup_buf); |
72246da4 | 4392 | |
7d5e650a | 4393 | err1: |
d64ff406 | 4394 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
4395 | dwc->ep0_trb, dwc->ep0_trb_addr); |
4396 | ||
72246da4 FB |
4397 | err0: |
4398 | return ret; | |
4399 | } | |
4400 | ||
7415f17c FB |
4401 | /* -------------------------------------------------------------------------- */ |
4402 | ||
72246da4 FB |
4403 | void dwc3_gadget_exit(struct dwc3 *dwc) |
4404 | { | |
03715ea2 JP |
4405 | if (!dwc->gadget) |
4406 | return; | |
4407 | ||
bb9c74a5 | 4408 | usb_del_gadget(dwc->gadget); |
72246da4 | 4409 | dwc3_gadget_free_endpoints(dwc); |
bb9c74a5 | 4410 | usb_put_gadget(dwc->gadget); |
905dc04e | 4411 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 4412 | dwc->bounce_addr); |
0fc9a1be | 4413 | kfree(dwc->setup_buf); |
d64ff406 | 4414 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 4415 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 4416 | } |
7415f17c | 4417 | |
0b0231aa | 4418 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 4419 | { |
9772b47a RQ |
4420 | if (!dwc->gadget_driver) |
4421 | return 0; | |
4422 | ||
1551e35e | 4423 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
4424 | dwc3_disconnect_gadget(dwc); |
4425 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
4426 | |
4427 | return 0; | |
4428 | } | |
4429 | ||
4430 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
4431 | { | |
7415f17c FB |
4432 | int ret; |
4433 | ||
149c9ed4 | 4434 | if (!dwc->gadget_driver || !dwc->softconnect) |
9772b47a RQ |
4435 | return 0; |
4436 | ||
9f8a67b6 FB |
4437 | ret = __dwc3_gadget_start(dwc); |
4438 | if (ret < 0) | |
7415f17c FB |
4439 | goto err0; |
4440 | ||
9f8a67b6 FB |
4441 | ret = dwc3_gadget_run_stop(dwc, true, false); |
4442 | if (ret < 0) | |
7415f17c FB |
4443 | goto err1; |
4444 | ||
7415f17c FB |
4445 | return 0; |
4446 | ||
4447 | err1: | |
9f8a67b6 | 4448 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
4449 | |
4450 | err0: | |
4451 | return ret; | |
4452 | } | |
fc8bb91b FB |
4453 | |
4454 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
4455 | { | |
4456 | if (dwc->pending_events) { | |
4457 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
4458 | dwc->pending_events = false; | |
4459 | enable_irq(dwc->irq_gadget); | |
4460 | } | |
4461 | } |