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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
33 | #include "core.h" | |
34 | #include "gadget.h" | |
35 | #include "io.h" | |
36 | ||
04a9bfcd FB |
37 | /** |
38 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
39 | * @dwc: pointer to our context structure | |
40 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
41 | * | |
42 | * Caller should take care of locking. This function will | |
43 | * return 0 on success or -EINVAL if wrong Test Selector | |
44 | * is passed | |
45 | */ | |
46 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
47 | { | |
48 | u32 reg; | |
49 | ||
50 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
51 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
52 | ||
53 | switch (mode) { | |
54 | case TEST_J: | |
55 | case TEST_K: | |
56 | case TEST_SE0_NAK: | |
57 | case TEST_PACKET: | |
58 | case TEST_FORCE_EN: | |
59 | reg |= mode << 1; | |
60 | break; | |
61 | default: | |
62 | return -EINVAL; | |
63 | } | |
64 | ||
65 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
911f1f88 PZ |
70 | /** |
71 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
72 | * @dwc: pointer to our context structure | |
73 | * | |
74 | * Caller should take care of locking. This function will | |
75 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
76 | */ | |
77 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
78 | { | |
79 | u32 reg; | |
80 | ||
81 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
82 | ||
83 | return DWC3_DSTS_USBLNKST(reg); | |
84 | } | |
85 | ||
8598bde7 FB |
86 | /** |
87 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
88 | * @dwc: pointer to our context structure | |
89 | * @state: the state to put link into | |
90 | * | |
91 | * Caller should take care of locking. This function will | |
aee63e3c | 92 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
93 | */ |
94 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
95 | { | |
aee63e3c | 96 | int retries = 10000; |
8598bde7 FB |
97 | u32 reg; |
98 | ||
802fde98 PZ |
99 | /* |
100 | * Wait until device controller is ready. Only applies to 1.94a and | |
101 | * later RTL. | |
102 | */ | |
103 | if (dwc->revision >= DWC3_REVISION_194A) { | |
104 | while (--retries) { | |
105 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
106 | if (reg & DWC3_DSTS_DCNRD) | |
107 | udelay(5); | |
108 | else | |
109 | break; | |
110 | } | |
111 | ||
112 | if (retries <= 0) | |
113 | return -ETIMEDOUT; | |
114 | } | |
115 | ||
8598bde7 FB |
116 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
117 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
118 | ||
119 | /* set requested state */ | |
120 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
121 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
122 | ||
802fde98 PZ |
123 | /* |
124 | * The following code is racy when called from dwc3_gadget_wakeup, | |
125 | * and is not needed, at least on newer versions | |
126 | */ | |
127 | if (dwc->revision >= DWC3_REVISION_194A) | |
128 | return 0; | |
129 | ||
8598bde7 | 130 | /* wait for a change in DSTS */ |
aed430e5 | 131 | retries = 10000; |
8598bde7 FB |
132 | while (--retries) { |
133 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
134 | ||
8598bde7 FB |
135 | if (DWC3_DSTS_USBLNKST(reg) == state) |
136 | return 0; | |
137 | ||
aee63e3c | 138 | udelay(5); |
8598bde7 FB |
139 | } |
140 | ||
141 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
142 | ||
143 | return -ETIMEDOUT; | |
144 | } | |
145 | ||
457e84b6 FB |
146 | /** |
147 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
148 | * @dwc: pointer to our context structure | |
149 | * | |
150 | * This function will a best effort FIFO allocation in order | |
151 | * to improve FIFO usage and throughput, while still allowing | |
152 | * us to enable as many endpoints as possible. | |
153 | * | |
154 | * Keep in mind that this operation will be highly dependent | |
155 | * on the configured size for RAM1 - which contains TxFifo -, | |
156 | * the amount of endpoints enabled on coreConsultant tool, and | |
157 | * the width of the Master Bus. | |
158 | * | |
159 | * In the ideal world, we would always be able to satisfy the | |
160 | * following equation: | |
161 | * | |
162 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
163 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
164 | * | |
165 | * Unfortunately, due to many variables that's not always the case. | |
166 | */ | |
167 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
168 | { | |
169 | int last_fifo_depth = 0; | |
170 | int ram1_depth; | |
171 | int fifo_size; | |
172 | int mdwidth; | |
173 | int num; | |
174 | ||
175 | if (!dwc->needs_fifo_resize) | |
176 | return 0; | |
177 | ||
178 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
179 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
180 | ||
181 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
182 | mdwidth >>= 3; | |
183 | ||
184 | /* | |
185 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
186 | * for each enabled endpoint, later patches will come to | |
187 | * improve this algorithm so that we better use the internal | |
188 | * FIFO space | |
189 | */ | |
32702e96 JP |
190 | for (num = 0; num < dwc->num_in_eps; num++) { |
191 | /* bit0 indicates direction; 1 means IN ep */ | |
192 | struct dwc3_ep *dep = dwc->eps[(num << 1) | 1]; | |
2e81c36a | 193 | int mult = 1; |
457e84b6 FB |
194 | int tmp; |
195 | ||
457e84b6 FB |
196 | if (!(dep->flags & DWC3_EP_ENABLED)) |
197 | continue; | |
198 | ||
16e78db7 IS |
199 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
200 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
201 | mult = 3; |
202 | ||
203 | /* | |
204 | * REVISIT: the following assumes we will always have enough | |
205 | * space available on the FIFO RAM for all possible use cases. | |
206 | * Make sure that's true somehow and change FIFO allocation | |
207 | * accordingly. | |
208 | * | |
209 | * If we have Bulk or Isochronous endpoints, we want | |
210 | * them to be able to be very, very fast. So we're giving | |
211 | * those endpoints a fifo_size which is enough for 3 full | |
212 | * packets | |
213 | */ | |
214 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
215 | tmp += mdwidth; |
216 | ||
217 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 218 | |
457e84b6 FB |
219 | fifo_size |= (last_fifo_depth << 16); |
220 | ||
221 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
222 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
223 | ||
32702e96 | 224 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size); |
457e84b6 FB |
225 | |
226 | last_fifo_depth += (fifo_size & 0xffff); | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
72246da4 FB |
232 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
233 | int status) | |
234 | { | |
235 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 236 | int i; |
72246da4 FB |
237 | |
238 | if (req->queued) { | |
e5ba5ec8 PA |
239 | i = 0; |
240 | do { | |
eeb720fb | 241 | dep->busy_slot++; |
e5ba5ec8 PA |
242 | /* |
243 | * Skip LINK TRB. We can't use req->trb and check for | |
244 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
245 | * just completed (not the LINK TRB). | |
246 | */ | |
247 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
248 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 249 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
250 | dep->busy_slot++; |
251 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 252 | req->queued = false; |
72246da4 FB |
253 | } |
254 | list_del(&req->list); | |
eeb720fb | 255 | req->trb = NULL; |
72246da4 FB |
256 | |
257 | if (req->request.status == -EINPROGRESS) | |
258 | req->request.status = status; | |
259 | ||
0416e494 PA |
260 | if (dwc->ep0_bounced && dep->number == 0) |
261 | dwc->ep0_bounced = false; | |
262 | else | |
263 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
264 | req->direction); | |
72246da4 FB |
265 | |
266 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
267 | req, dep->name, req->request.actual, | |
268 | req->request.length, status); | |
269 | ||
270 | spin_unlock(&dwc->lock); | |
0fc9a1be | 271 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
272 | spin_lock(&dwc->lock); |
273 | } | |
274 | ||
275 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
276 | { | |
277 | switch (cmd) { | |
278 | case DWC3_DEPCMD_DEPSTARTCFG: | |
279 | return "Start New Configuration"; | |
280 | case DWC3_DEPCMD_ENDTRANSFER: | |
281 | return "End Transfer"; | |
282 | case DWC3_DEPCMD_UPDATETRANSFER: | |
283 | return "Update Transfer"; | |
284 | case DWC3_DEPCMD_STARTTRANSFER: | |
285 | return "Start Transfer"; | |
286 | case DWC3_DEPCMD_CLEARSTALL: | |
287 | return "Clear Stall"; | |
288 | case DWC3_DEPCMD_SETSTALL: | |
289 | return "Set Stall"; | |
802fde98 PZ |
290 | case DWC3_DEPCMD_GETEPSTATE: |
291 | return "Get Endpoint State"; | |
72246da4 FB |
292 | case DWC3_DEPCMD_SETTRANSFRESOURCE: |
293 | return "Set Endpoint Transfer Resource"; | |
294 | case DWC3_DEPCMD_SETEPCONFIG: | |
295 | return "Set Endpoint Configuration"; | |
296 | default: | |
297 | return "UNKNOWN command"; | |
298 | } | |
299 | } | |
300 | ||
427c3df6 FB |
301 | static const char *dwc3_gadget_generic_cmd_string(u8 cmd) |
302 | { | |
303 | switch (cmd) { | |
304 | case DWC3_DGCMD_SET_LMP: | |
305 | return "Set LMP"; | |
306 | case DWC3_DGCMD_SET_PERIODIC_PAR: | |
307 | return "Set Periodic Parameters"; | |
308 | case DWC3_DGCMD_XMIT_FUNCTION: | |
309 | return "Transmit Function Wake Device Notification"; | |
310 | case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO: | |
311 | return "Set Scratchpad Buffer Array Address Lo"; | |
312 | case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI: | |
313 | return "Set Scratchpad Buffer Array Address Hi"; | |
314 | case DWC3_DGCMD_SELECTED_FIFO_FLUSH: | |
315 | return "Selected FIFO Flush"; | |
316 | case DWC3_DGCMD_ALL_FIFO_FLUSH: | |
317 | return "All FIFO Flush"; | |
318 | case DWC3_DGCMD_SET_ENDPOINT_NRDY: | |
319 | return "Set Endpoint NRDY"; | |
320 | case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK: | |
321 | return "Run SoC Bus Loopback Test"; | |
322 | default: | |
323 | return "UNKNOWN"; | |
324 | } | |
325 | } | |
326 | ||
e57ebc1d FB |
327 | static const char *dwc3_gadget_link_string(enum dwc3_link_state link_state) |
328 | { | |
329 | switch (link_state) { | |
330 | case DWC3_LINK_STATE_U0: | |
331 | return "U0"; | |
332 | case DWC3_LINK_STATE_U1: | |
333 | return "U1"; | |
334 | case DWC3_LINK_STATE_U2: | |
335 | return "U2"; | |
336 | case DWC3_LINK_STATE_U3: | |
337 | return "U3"; | |
338 | case DWC3_LINK_STATE_SS_DIS: | |
339 | return "SS.Disabled"; | |
340 | case DWC3_LINK_STATE_RX_DET: | |
341 | return "RX.Detect"; | |
342 | case DWC3_LINK_STATE_SS_INACT: | |
343 | return "SS.Inactive"; | |
344 | case DWC3_LINK_STATE_POLL: | |
345 | return "Polling"; | |
346 | case DWC3_LINK_STATE_RECOV: | |
347 | return "Recovery"; | |
348 | case DWC3_LINK_STATE_HRESET: | |
349 | return "Hot Reset"; | |
350 | case DWC3_LINK_STATE_CMPLY: | |
351 | return "Compliance"; | |
352 | case DWC3_LINK_STATE_LPBK: | |
353 | return "Loopback"; | |
354 | case DWC3_LINK_STATE_RESET: | |
355 | return "Reset"; | |
356 | case DWC3_LINK_STATE_RESUME: | |
357 | return "Resume"; | |
358 | default: | |
359 | return "UNKNOWN link state\n"; | |
360 | } | |
361 | } | |
362 | ||
b09bb642 FB |
363 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
364 | { | |
365 | u32 timeout = 500; | |
366 | u32 reg; | |
367 | ||
427c3df6 FB |
368 | dev_vdbg(dwc->dev, "generic cmd '%s' [%d] param %08x\n", |
369 | dwc3_gadget_generic_cmd_string(cmd), cmd, param); | |
370 | ||
b09bb642 FB |
371 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); |
372 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
373 | ||
374 | do { | |
375 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
376 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
377 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
378 | DWC3_DGCMD_STATUS(reg)); | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* | |
383 | * We can't sleep here, because it's also called from | |
384 | * interrupt context. | |
385 | */ | |
386 | timeout--; | |
387 | if (!timeout) | |
388 | return -ETIMEDOUT; | |
389 | udelay(1); | |
390 | } while (1); | |
391 | } | |
392 | ||
72246da4 FB |
393 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
394 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
395 | { | |
396 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 397 | u32 timeout = 500; |
72246da4 FB |
398 | u32 reg; |
399 | ||
40cc57c7 | 400 | dev_vdbg(dwc->dev, "%s: cmd '%s' [%d] params %08x %08x %08x\n", |
72246da4 | 401 | dep->name, |
40cc57c7 | 402 | dwc3_gadget_ep_cmd_string(cmd), cmd, params->param0, |
dc1c70a7 | 403 | params->param1, params->param2); |
72246da4 | 404 | |
dc1c70a7 FB |
405 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
406 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
407 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
408 | |
409 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
410 | do { | |
411 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
412 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
413 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
414 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
415 | return 0; |
416 | } | |
417 | ||
418 | /* | |
72246da4 FB |
419 | * We can't sleep here, because it is also called from |
420 | * interrupt context. | |
421 | */ | |
422 | timeout--; | |
423 | if (!timeout) | |
424 | return -ETIMEDOUT; | |
425 | ||
61d58242 | 426 | udelay(1); |
72246da4 FB |
427 | } while (1); |
428 | } | |
429 | ||
430 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 431 | struct dwc3_trb *trb) |
72246da4 | 432 | { |
c439ef87 | 433 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
434 | |
435 | return dep->trb_pool_dma + offset; | |
436 | } | |
437 | ||
438 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
439 | { | |
440 | struct dwc3 *dwc = dep->dwc; | |
441 | ||
442 | if (dep->trb_pool) | |
443 | return 0; | |
444 | ||
445 | if (dep->number == 0 || dep->number == 1) | |
446 | return 0; | |
447 | ||
448 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
449 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
450 | &dep->trb_pool_dma, GFP_KERNEL); | |
451 | if (!dep->trb_pool) { | |
452 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
453 | dep->name); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
461 | { | |
462 | struct dwc3 *dwc = dep->dwc; | |
463 | ||
464 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
465 | dep->trb_pool, dep->trb_pool_dma); | |
466 | ||
467 | dep->trb_pool = NULL; | |
468 | dep->trb_pool_dma = 0; | |
469 | } | |
470 | ||
471 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
472 | { | |
473 | struct dwc3_gadget_ep_cmd_params params; | |
474 | u32 cmd; | |
475 | ||
476 | memset(¶ms, 0x00, sizeof(params)); | |
477 | ||
478 | if (dep->number != 1) { | |
479 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
480 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
481 | if (dep->number > 1) { |
482 | if (dwc->start_config_issued) | |
483 | return 0; | |
484 | dwc->start_config_issued = true; | |
72246da4 | 485 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 486 | } |
72246da4 FB |
487 | |
488 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
489 | } | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 495 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 496 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 497 | bool ignore, bool restore) |
72246da4 FB |
498 | { |
499 | struct dwc3_gadget_ep_cmd_params params; | |
500 | ||
501 | memset(¶ms, 0x00, sizeof(params)); | |
502 | ||
dc1c70a7 | 503 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
504 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
505 | ||
506 | /* Burst size is only needed in SuperSpeed mode */ | |
507 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
508 | u32 burst = dep->endpoint.maxburst - 1; | |
509 | ||
510 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
511 | } | |
72246da4 | 512 | |
4b345c9a FB |
513 | if (ignore) |
514 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
515 | ||
265b70a7 PZ |
516 | if (restore) { |
517 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
518 | params.param2 |= dep->saved_state; | |
519 | } | |
520 | ||
dc1c70a7 FB |
521 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
522 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 523 | |
18b7ede5 | 524 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
525 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
526 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
527 | dep->stream_capable = true; |
528 | } | |
529 | ||
72246da4 | 530 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 531 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
532 | |
533 | /* | |
534 | * We are doing 1:1 mapping for endpoints, meaning | |
535 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
536 | * so on. We consider the direction bit as part of the physical | |
537 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
538 | */ | |
dc1c70a7 | 539 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
540 | |
541 | /* | |
542 | * We must use the lower 16 TX FIFOs even though | |
543 | * HW might have more | |
544 | */ | |
545 | if (dep->direction) | |
dc1c70a7 | 546 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
547 | |
548 | if (desc->bInterval) { | |
dc1c70a7 | 549 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
550 | dep->interval = 1 << (desc->bInterval - 1); |
551 | } | |
552 | ||
553 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
554 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
555 | } | |
556 | ||
557 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
558 | { | |
559 | struct dwc3_gadget_ep_cmd_params params; | |
560 | ||
561 | memset(¶ms, 0x00, sizeof(params)); | |
562 | ||
dc1c70a7 | 563 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
564 | |
565 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
566 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
567 | } | |
568 | ||
569 | /** | |
570 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
571 | * @dep: endpoint to be initialized | |
572 | * @desc: USB Endpoint Descriptor | |
573 | * | |
574 | * Caller should take care of locking | |
575 | */ | |
576 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 577 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 578 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 579 | bool ignore, bool restore) |
72246da4 FB |
580 | { |
581 | struct dwc3 *dwc = dep->dwc; | |
582 | u32 reg; | |
b09e99ee | 583 | int ret; |
72246da4 | 584 | |
ff62d6b6 FB |
585 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); |
586 | ||
72246da4 FB |
587 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
588 | ret = dwc3_gadget_start_config(dwc, dep); | |
589 | if (ret) | |
590 | return ret; | |
591 | } | |
592 | ||
265b70a7 PZ |
593 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
594 | restore); | |
72246da4 FB |
595 | if (ret) |
596 | return ret; | |
597 | ||
598 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
599 | struct dwc3_trb *trb_st_hw; |
600 | struct dwc3_trb *trb_link; | |
72246da4 FB |
601 | |
602 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
603 | if (ret) | |
604 | return ret; | |
605 | ||
16e78db7 | 606 | dep->endpoint.desc = desc; |
c90bfaec | 607 | dep->comp_desc = comp_desc; |
72246da4 FB |
608 | dep->type = usb_endpoint_type(desc); |
609 | dep->flags |= DWC3_EP_ENABLED; | |
610 | ||
611 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
612 | reg |= DWC3_DALEPENA_EP(dep->number); | |
613 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
614 | ||
615 | if (!usb_endpoint_xfer_isoc(desc)) | |
616 | return 0; | |
617 | ||
618 | memset(&trb_link, 0, sizeof(trb_link)); | |
619 | ||
1d046793 | 620 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
621 | trb_st_hw = &dep->trb_pool[0]; |
622 | ||
f6bafc6a | 623 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
72246da4 | 624 | |
f6bafc6a FB |
625 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
626 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
627 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
628 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
629 | } |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
b992e681 | 634 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 635 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
636 | { |
637 | struct dwc3_request *req; | |
638 | ||
ea53b882 | 639 | if (!list_empty(&dep->req_queued)) { |
b992e681 | 640 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 641 | |
57911504 | 642 | /* - giveback all requests to gadget driver */ |
1591633e PA |
643 | while (!list_empty(&dep->req_queued)) { |
644 | req = next_request(&dep->req_queued); | |
645 | ||
646 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
647 | } | |
ea53b882 FB |
648 | } |
649 | ||
72246da4 FB |
650 | while (!list_empty(&dep->request_list)) { |
651 | req = next_request(&dep->request_list); | |
652 | ||
624407f9 | 653 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 654 | } |
72246da4 FB |
655 | } |
656 | ||
657 | /** | |
658 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
659 | * @dep: the endpoint to disable | |
660 | * | |
624407f9 SAS |
661 | * This function also removes requests which are currently processed ny the |
662 | * hardware and those which are not yet scheduled. | |
663 | * Caller should take care of locking. | |
72246da4 | 664 | */ |
72246da4 FB |
665 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
666 | { | |
667 | struct dwc3 *dwc = dep->dwc; | |
668 | u32 reg; | |
669 | ||
624407f9 | 670 | dwc3_remove_requests(dwc, dep); |
72246da4 | 671 | |
687ef981 FB |
672 | /* make sure HW endpoint isn't stalled */ |
673 | if (dep->flags & DWC3_EP_STALL) | |
674 | __dwc3_gadget_ep_set_halt(dep, 0); | |
675 | ||
72246da4 FB |
676 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
677 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
678 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
679 | ||
879631aa | 680 | dep->stream_capable = false; |
f9c56cdd | 681 | dep->endpoint.desc = NULL; |
c90bfaec | 682 | dep->comp_desc = NULL; |
72246da4 | 683 | dep->type = 0; |
879631aa | 684 | dep->flags = 0; |
72246da4 FB |
685 | |
686 | return 0; | |
687 | } | |
688 | ||
689 | /* -------------------------------------------------------------------------- */ | |
690 | ||
691 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
692 | const struct usb_endpoint_descriptor *desc) | |
693 | { | |
694 | return -EINVAL; | |
695 | } | |
696 | ||
697 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
698 | { | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | /* -------------------------------------------------------------------------- */ | |
703 | ||
704 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
705 | const struct usb_endpoint_descriptor *desc) | |
706 | { | |
707 | struct dwc3_ep *dep; | |
708 | struct dwc3 *dwc; | |
709 | unsigned long flags; | |
710 | int ret; | |
711 | ||
712 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
713 | pr_debug("dwc3: invalid parameters\n"); | |
714 | return -EINVAL; | |
715 | } | |
716 | ||
717 | if (!desc->wMaxPacketSize) { | |
718 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
719 | return -EINVAL; | |
720 | } | |
721 | ||
722 | dep = to_dwc3_ep(ep); | |
723 | dwc = dep->dwc; | |
724 | ||
c6f83f38 FB |
725 | if (dep->flags & DWC3_EP_ENABLED) { |
726 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
727 | dep->name); | |
728 | return 0; | |
729 | } | |
730 | ||
72246da4 FB |
731 | switch (usb_endpoint_type(desc)) { |
732 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 733 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
734 | break; |
735 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 736 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
737 | break; |
738 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 739 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
740 | break; |
741 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 742 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
743 | break; |
744 | default: | |
745 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
746 | } | |
747 | ||
72246da4 | 748 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 749 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
750 | spin_unlock_irqrestore(&dwc->lock, flags); |
751 | ||
752 | return ret; | |
753 | } | |
754 | ||
755 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
756 | { | |
757 | struct dwc3_ep *dep; | |
758 | struct dwc3 *dwc; | |
759 | unsigned long flags; | |
760 | int ret; | |
761 | ||
762 | if (!ep) { | |
763 | pr_debug("dwc3: invalid parameters\n"); | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
767 | dep = to_dwc3_ep(ep); | |
768 | dwc = dep->dwc; | |
769 | ||
770 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
771 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
772 | dep->name); | |
773 | return 0; | |
774 | } | |
775 | ||
776 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
777 | dep->number >> 1, | |
778 | (dep->number & 1) ? "in" : "out"); | |
779 | ||
780 | spin_lock_irqsave(&dwc->lock, flags); | |
781 | ret = __dwc3_gadget_ep_disable(dep); | |
782 | spin_unlock_irqrestore(&dwc->lock, flags); | |
783 | ||
784 | return ret; | |
785 | } | |
786 | ||
787 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
788 | gfp_t gfp_flags) | |
789 | { | |
790 | struct dwc3_request *req; | |
791 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
792 | struct dwc3 *dwc = dep->dwc; | |
793 | ||
794 | req = kzalloc(sizeof(*req), gfp_flags); | |
795 | if (!req) { | |
796 | dev_err(dwc->dev, "not enough memory\n"); | |
797 | return NULL; | |
798 | } | |
799 | ||
800 | req->epnum = dep->number; | |
801 | req->dep = dep; | |
72246da4 FB |
802 | |
803 | return &req->request; | |
804 | } | |
805 | ||
806 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
807 | struct usb_request *request) | |
808 | { | |
809 | struct dwc3_request *req = to_dwc3_request(request); | |
810 | ||
811 | kfree(req); | |
812 | } | |
813 | ||
c71fc37c FB |
814 | /** |
815 | * dwc3_prepare_one_trb - setup one TRB from one request | |
816 | * @dep: endpoint for which this request is prepared | |
817 | * @req: dwc3_request pointer | |
818 | */ | |
68e823e2 | 819 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 820 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 821 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 822 | { |
eeb720fb | 823 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 824 | struct dwc3_trb *trb; |
c71fc37c | 825 | |
eeb720fb FB |
826 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
827 | dep->name, req, (unsigned long long) dma, | |
828 | length, last ? " last" : "", | |
829 | chain ? " chain" : ""); | |
830 | ||
915e202a PA |
831 | |
832 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 833 | |
eeb720fb FB |
834 | if (!req->trb) { |
835 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
836 | req->trb = trb; |
837 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 838 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 839 | } |
c71fc37c | 840 | |
e5ba5ec8 | 841 | dep->free_slot++; |
5cd8c48d ZJC |
842 | /* Skip the LINK-TRB on ISOC */ |
843 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
844 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
845 | dep->free_slot++; | |
e5ba5ec8 | 846 | |
f6bafc6a FB |
847 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
848 | trb->bpl = lower_32_bits(dma); | |
849 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 850 | |
16e78db7 | 851 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 852 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 853 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
854 | break; |
855 | ||
856 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
857 | if (!node) |
858 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
859 | else | |
860 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c FB |
861 | break; |
862 | ||
863 | case USB_ENDPOINT_XFER_BULK: | |
864 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 865 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
866 | break; |
867 | default: | |
868 | /* | |
869 | * This is only possible with faulty memory because we | |
870 | * checked it already :) | |
871 | */ | |
872 | BUG(); | |
873 | } | |
874 | ||
f3af3651 FB |
875 | if (!req->request.no_interrupt && !chain) |
876 | trb->ctrl |= DWC3_TRB_CTRL_IOC; | |
877 | ||
16e78db7 | 878 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
879 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
880 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
881 | } else if (last) { |
882 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 883 | } |
c71fc37c | 884 | |
e5ba5ec8 PA |
885 | if (chain) |
886 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
887 | ||
16e78db7 | 888 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 889 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 890 | |
f6bafc6a | 891 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
892 | } |
893 | ||
72246da4 FB |
894 | /* |
895 | * dwc3_prepare_trbs - setup TRBs from requests | |
896 | * @dep: endpoint for which requests are being prepared | |
897 | * @starting: true if the endpoint is idle and no requests are queued. | |
898 | * | |
1d046793 PZ |
899 | * The function goes through the requests list and sets up TRBs for the |
900 | * transfers. The function returns once there are no more TRBs available or | |
901 | * it runs out of requests. | |
72246da4 | 902 | */ |
68e823e2 | 903 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 904 | { |
68e823e2 | 905 | struct dwc3_request *req, *n; |
72246da4 | 906 | u32 trbs_left; |
8d62cd65 | 907 | u32 max; |
c71fc37c | 908 | unsigned int last_one = 0; |
72246da4 FB |
909 | |
910 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
911 | ||
912 | /* the first request must not be queued */ | |
913 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 914 | |
8d62cd65 | 915 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 916 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
917 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
918 | if (trbs_left > max) | |
919 | trbs_left = max; | |
920 | } | |
921 | ||
72246da4 | 922 | /* |
1d046793 PZ |
923 | * If busy & slot are equal than it is either full or empty. If we are |
924 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
925 | * full and don't do anything |
926 | */ | |
927 | if (!trbs_left) { | |
928 | if (!starting) | |
68e823e2 | 929 | return; |
72246da4 FB |
930 | trbs_left = DWC3_TRB_NUM; |
931 | /* | |
932 | * In case we start from scratch, we queue the ISOC requests | |
933 | * starting from slot 1. This is done because we use ring | |
934 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 935 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
936 | * after the first request so we start at slot 1 and have |
937 | * 7 requests proceed before we hit the first IOC. | |
938 | * Other transfer types don't use the ring buffer and are | |
939 | * processed from the first TRB until the last one. Since we | |
940 | * don't wrap around we have to start at the beginning. | |
941 | */ | |
16e78db7 | 942 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
943 | dep->busy_slot = 1; |
944 | dep->free_slot = 1; | |
945 | } else { | |
946 | dep->busy_slot = 0; | |
947 | dep->free_slot = 0; | |
948 | } | |
949 | } | |
950 | ||
951 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 952 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 953 | return; |
72246da4 FB |
954 | |
955 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
956 | unsigned length; |
957 | dma_addr_t dma; | |
e5ba5ec8 | 958 | last_one = false; |
72246da4 | 959 | |
eeb720fb FB |
960 | if (req->request.num_mapped_sgs > 0) { |
961 | struct usb_request *request = &req->request; | |
962 | struct scatterlist *sg = request->sg; | |
963 | struct scatterlist *s; | |
964 | int i; | |
72246da4 | 965 | |
eeb720fb FB |
966 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
967 | unsigned chain = true; | |
72246da4 | 968 | |
eeb720fb FB |
969 | length = sg_dma_len(s); |
970 | dma = sg_dma_address(s); | |
72246da4 | 971 | |
1d046793 PZ |
972 | if (i == (request->num_mapped_sgs - 1) || |
973 | sg_is_last(s)) { | |
e5ba5ec8 PA |
974 | if (list_is_last(&req->list, |
975 | &dep->request_list)) | |
976 | last_one = true; | |
eeb720fb FB |
977 | chain = false; |
978 | } | |
72246da4 | 979 | |
eeb720fb FB |
980 | trbs_left--; |
981 | if (!trbs_left) | |
982 | last_one = true; | |
72246da4 | 983 | |
eeb720fb FB |
984 | if (last_one) |
985 | chain = false; | |
72246da4 | 986 | |
eeb720fb | 987 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 988 | last_one, chain, i); |
72246da4 | 989 | |
eeb720fb FB |
990 | if (last_one) |
991 | break; | |
992 | } | |
72246da4 | 993 | } else { |
eeb720fb FB |
994 | dma = req->request.dma; |
995 | length = req->request.length; | |
996 | trbs_left--; | |
72246da4 | 997 | |
eeb720fb FB |
998 | if (!trbs_left) |
999 | last_one = 1; | |
879631aa | 1000 | |
eeb720fb FB |
1001 | /* Is this the last request? */ |
1002 | if (list_is_last(&req->list, &dep->request_list)) | |
1003 | last_one = 1; | |
72246da4 | 1004 | |
eeb720fb | 1005 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 1006 | last_one, false, 0); |
72246da4 | 1007 | |
eeb720fb FB |
1008 | if (last_one) |
1009 | break; | |
72246da4 | 1010 | } |
72246da4 | 1011 | } |
72246da4 FB |
1012 | } |
1013 | ||
1014 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
1015 | int start_new) | |
1016 | { | |
1017 | struct dwc3_gadget_ep_cmd_params params; | |
1018 | struct dwc3_request *req; | |
1019 | struct dwc3 *dwc = dep->dwc; | |
1020 | int ret; | |
1021 | u32 cmd; | |
1022 | ||
1023 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
1024 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
1025 | return -EBUSY; | |
1026 | } | |
1027 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1028 | ||
1029 | /* | |
1030 | * If we are getting here after a short-out-packet we don't enqueue any | |
1031 | * new requests as we try to set the IOC bit only on the last request. | |
1032 | */ | |
1033 | if (start_new) { | |
1034 | if (list_empty(&dep->req_queued)) | |
1035 | dwc3_prepare_trbs(dep, start_new); | |
1036 | ||
1037 | /* req points to the first request which will be sent */ | |
1038 | req = next_request(&dep->req_queued); | |
1039 | } else { | |
68e823e2 FB |
1040 | dwc3_prepare_trbs(dep, start_new); |
1041 | ||
72246da4 | 1042 | /* |
1d046793 | 1043 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 1044 | */ |
68e823e2 | 1045 | req = next_request(&dep->req_queued); |
72246da4 FB |
1046 | } |
1047 | if (!req) { | |
1048 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1053 | |
1877d6c9 PA |
1054 | if (start_new) { |
1055 | params.param0 = upper_32_bits(req->trb_dma); | |
1056 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 1057 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 1058 | } else { |
72246da4 | 1059 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 1060 | } |
72246da4 FB |
1061 | |
1062 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
1063 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
1064 | if (ret < 0) { | |
1065 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
1066 | ||
1067 | /* | |
1068 | * FIXME we need to iterate over the list of requests | |
1069 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1070 | * requests instead of what we do now. |
72246da4 | 1071 | */ |
0fc9a1be FB |
1072 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
1073 | req->direction); | |
72246da4 FB |
1074 | list_del(&req->list); |
1075 | return ret; | |
1076 | } | |
1077 | ||
1078 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1079 | |
f898ae09 | 1080 | if (start_new) { |
b4996a86 | 1081 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1082 | dep->number); |
b4996a86 | 1083 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1084 | } |
25b8ff68 | 1085 | |
72246da4 FB |
1086 | return 0; |
1087 | } | |
1088 | ||
d6d6ec7b PA |
1089 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1090 | struct dwc3_ep *dep, u32 cur_uf) | |
1091 | { | |
1092 | u32 uf; | |
1093 | ||
1094 | if (list_empty(&dep->request_list)) { | |
1095 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1096 | dep->name); | |
f4a53c55 | 1097 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1098 | return; |
1099 | } | |
1100 | ||
1101 | /* 4 micro frames in the future */ | |
1102 | uf = cur_uf + dep->interval * 4; | |
1103 | ||
1104 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1105 | } | |
1106 | ||
1107 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1108 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1109 | { | |
1110 | u32 cur_uf, mask; | |
1111 | ||
1112 | mask = ~(dep->interval - 1); | |
1113 | cur_uf = event->parameters & mask; | |
1114 | ||
1115 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1116 | } | |
1117 | ||
72246da4 FB |
1118 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1119 | { | |
0fc9a1be FB |
1120 | struct dwc3 *dwc = dep->dwc; |
1121 | int ret; | |
1122 | ||
72246da4 FB |
1123 | req->request.actual = 0; |
1124 | req->request.status = -EINPROGRESS; | |
1125 | req->direction = dep->direction; | |
1126 | req->epnum = dep->number; | |
1127 | ||
1128 | /* | |
1129 | * We only add to our list of requests now and | |
1130 | * start consuming the list once we get XferNotReady | |
1131 | * IRQ. | |
1132 | * | |
1133 | * That way, we avoid doing anything that we don't need | |
1134 | * to do now and defer it until the point we receive a | |
1135 | * particular token from the Host side. | |
1136 | * | |
1137 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1138 | * many NAKs. |
72246da4 | 1139 | */ |
0fc9a1be FB |
1140 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1141 | dep->direction); | |
1142 | if (ret) | |
1143 | return ret; | |
1144 | ||
72246da4 FB |
1145 | list_add_tail(&req->list, &dep->request_list); |
1146 | ||
1147 | /* | |
b511e5e7 | 1148 | * There are a few special cases: |
72246da4 | 1149 | * |
f898ae09 PZ |
1150 | * 1. XferNotReady with empty list of requests. We need to kick the |
1151 | * transfer here in that situation, otherwise we will be NAKing | |
1152 | * forever. If we get XferNotReady before gadget driver has a | |
1153 | * chance to queue a request, we will ACK the IRQ but won't be | |
1154 | * able to receive the data until the next request is queued. | |
1155 | * The following code is handling exactly that. | |
72246da4 | 1156 | * |
72246da4 FB |
1157 | */ |
1158 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1159 | /* |
1160 | * If xfernotready is already elapsed and it is a case | |
1161 | * of isoc transfer, then issue END TRANSFER, so that | |
1162 | * you can receive xfernotready again and can have | |
1163 | * notion of current microframe. | |
1164 | */ | |
1165 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd | 1166 | if (list_empty(&dep->req_queued)) { |
b992e681 | 1167 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1168 | dep->flags = DWC3_EP_ENABLED; |
1169 | } | |
f4a53c55 PA |
1170 | return 0; |
1171 | } | |
1172 | ||
b511e5e7 | 1173 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
348e026f | 1174 | if (ret && ret != -EBUSY) |
b511e5e7 FB |
1175 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1176 | dep->name); | |
15f86bde | 1177 | return ret; |
b511e5e7 | 1178 | } |
72246da4 | 1179 | |
b511e5e7 FB |
1180 | /* |
1181 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1182 | * kick the transfer here after queuing a request, otherwise the | |
1183 | * core may not see the modified TRB(s). | |
1184 | */ | |
1185 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1186 | (dep->flags & DWC3_EP_BUSY) && |
1187 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1188 | WARN_ON_ONCE(!dep->resource_index); |
1189 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1190 | false); |
348e026f | 1191 | if (ret && ret != -EBUSY) |
72246da4 FB |
1192 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1193 | dep->name); | |
15f86bde | 1194 | return ret; |
a0925324 | 1195 | } |
72246da4 | 1196 | |
b997ada5 FB |
1197 | /* |
1198 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1199 | * right away, otherwise host will not know we have streams to be | |
1200 | * handled. | |
1201 | */ | |
1202 | if (dep->stream_capable) { | |
1203 | int ret; | |
1204 | ||
1205 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); | |
1206 | if (ret && ret != -EBUSY) { | |
1207 | struct dwc3 *dwc = dep->dwc; | |
1208 | ||
1209 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1210 | dep->name); | |
1211 | } | |
1212 | } | |
1213 | ||
72246da4 FB |
1214 | return 0; |
1215 | } | |
1216 | ||
1217 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1218 | gfp_t gfp_flags) | |
1219 | { | |
1220 | struct dwc3_request *req = to_dwc3_request(request); | |
1221 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1222 | struct dwc3 *dwc = dep->dwc; | |
1223 | ||
1224 | unsigned long flags; | |
1225 | ||
1226 | int ret; | |
1227 | ||
16e78db7 | 1228 | if (!dep->endpoint.desc) { |
72246da4 FB |
1229 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1230 | request, ep->name); | |
1231 | return -ESHUTDOWN; | |
1232 | } | |
1233 | ||
1234 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1235 | request, ep->name, request->length); | |
1236 | ||
1237 | spin_lock_irqsave(&dwc->lock, flags); | |
1238 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1239 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1240 | ||
1241 | return ret; | |
1242 | } | |
1243 | ||
1244 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1245 | struct usb_request *request) | |
1246 | { | |
1247 | struct dwc3_request *req = to_dwc3_request(request); | |
1248 | struct dwc3_request *r = NULL; | |
1249 | ||
1250 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1251 | struct dwc3 *dwc = dep->dwc; | |
1252 | ||
1253 | unsigned long flags; | |
1254 | int ret = 0; | |
1255 | ||
1256 | spin_lock_irqsave(&dwc->lock, flags); | |
1257 | ||
1258 | list_for_each_entry(r, &dep->request_list, list) { | |
1259 | if (r == req) | |
1260 | break; | |
1261 | } | |
1262 | ||
1263 | if (r != req) { | |
1264 | list_for_each_entry(r, &dep->req_queued, list) { | |
1265 | if (r == req) | |
1266 | break; | |
1267 | } | |
1268 | if (r == req) { | |
1269 | /* wait until it is processed */ | |
b992e681 | 1270 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1271 | goto out1; |
72246da4 FB |
1272 | } |
1273 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1274 | request, ep->name); | |
1275 | ret = -EINVAL; | |
1276 | goto out0; | |
1277 | } | |
1278 | ||
e8d4e8be | 1279 | out1: |
72246da4 FB |
1280 | /* giveback the request */ |
1281 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1282 | ||
1283 | out0: | |
1284 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1285 | ||
1286 | return ret; | |
1287 | } | |
1288 | ||
1289 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) | |
1290 | { | |
1291 | struct dwc3_gadget_ep_cmd_params params; | |
1292 | struct dwc3 *dwc = dep->dwc; | |
1293 | int ret; | |
1294 | ||
1295 | memset(¶ms, 0x00, sizeof(params)); | |
1296 | ||
1297 | if (value) { | |
72246da4 FB |
1298 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1299 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1300 | if (ret) | |
3f89204b | 1301 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1302 | dep->name); |
1303 | else | |
1304 | dep->flags |= DWC3_EP_STALL; | |
1305 | } else { | |
1306 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1307 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1308 | if (ret) | |
3f89204b | 1309 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1310 | dep->name); |
1311 | else | |
a535d81c | 1312 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1313 | } |
5275455a | 1314 | |
72246da4 FB |
1315 | return ret; |
1316 | } | |
1317 | ||
1318 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1319 | { | |
1320 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1321 | struct dwc3 *dwc = dep->dwc; | |
1322 | ||
1323 | unsigned long flags; | |
1324 | ||
1325 | int ret; | |
1326 | ||
1327 | spin_lock_irqsave(&dwc->lock, flags); | |
1328 | ||
16e78db7 | 1329 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1330 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1331 | ret = -EINVAL; | |
1332 | goto out; | |
1333 | } | |
1334 | ||
1335 | ret = __dwc3_gadget_ep_set_halt(dep, value); | |
1336 | out: | |
1337 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1338 | ||
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1343 | { | |
1344 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1345 | struct dwc3 *dwc = dep->dwc; |
1346 | unsigned long flags; | |
72246da4 | 1347 | |
249a4569 | 1348 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1349 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1350 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1351 | |
08f0d966 PA |
1352 | if (dep->number == 0 || dep->number == 1) |
1353 | return dwc3_gadget_ep0_set_halt(ep, 1); | |
1354 | else | |
1355 | return dwc3_gadget_ep_set_halt(ep, 1); | |
72246da4 FB |
1356 | } |
1357 | ||
1358 | /* -------------------------------------------------------------------------- */ | |
1359 | ||
1360 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1361 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1362 | .bDescriptorType = USB_DT_ENDPOINT, | |
1363 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1364 | }; | |
1365 | ||
1366 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1367 | .enable = dwc3_gadget_ep0_enable, | |
1368 | .disable = dwc3_gadget_ep0_disable, | |
1369 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1370 | .free_request = dwc3_gadget_ep_free_request, | |
1371 | .queue = dwc3_gadget_ep0_queue, | |
1372 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1373 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1374 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1375 | }; | |
1376 | ||
1377 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1378 | .enable = dwc3_gadget_ep_enable, | |
1379 | .disable = dwc3_gadget_ep_disable, | |
1380 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1381 | .free_request = dwc3_gadget_ep_free_request, | |
1382 | .queue = dwc3_gadget_ep_queue, | |
1383 | .dequeue = dwc3_gadget_ep_dequeue, | |
1384 | .set_halt = dwc3_gadget_ep_set_halt, | |
1385 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1386 | }; | |
1387 | ||
1388 | /* -------------------------------------------------------------------------- */ | |
1389 | ||
1390 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1391 | { | |
1392 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1393 | u32 reg; | |
1394 | ||
1395 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1396 | return DWC3_DSTS_SOFFN(reg); | |
1397 | } | |
1398 | ||
1399 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1400 | { | |
1401 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1402 | ||
1403 | unsigned long timeout; | |
1404 | unsigned long flags; | |
1405 | ||
1406 | u32 reg; | |
1407 | ||
1408 | int ret = 0; | |
1409 | ||
1410 | u8 link_state; | |
1411 | u8 speed; | |
1412 | ||
1413 | spin_lock_irqsave(&dwc->lock, flags); | |
1414 | ||
1415 | /* | |
1416 | * According to the Databook Remote wakeup request should | |
1417 | * be issued only when the device is in early suspend state. | |
1418 | * | |
1419 | * We can check that via USB Link State bits in DSTS register. | |
1420 | */ | |
1421 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1422 | ||
1423 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1424 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1425 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1426 | ret = -EINVAL; | |
1427 | goto out; | |
1428 | } | |
1429 | ||
1430 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1431 | ||
1432 | switch (link_state) { | |
1433 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1434 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1435 | break; | |
1436 | default: | |
1437 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1438 | link_state); | |
1439 | ret = -EINVAL; | |
1440 | goto out; | |
1441 | } | |
1442 | ||
8598bde7 FB |
1443 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1444 | if (ret < 0) { | |
1445 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1446 | goto out; | |
1447 | } | |
72246da4 | 1448 | |
802fde98 PZ |
1449 | /* Recent versions do this automatically */ |
1450 | if (dwc->revision < DWC3_REVISION_194A) { | |
1451 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1452 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1453 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1454 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1455 | } | |
72246da4 | 1456 | |
1d046793 | 1457 | /* poll until Link State changes to ON */ |
72246da4 FB |
1458 | timeout = jiffies + msecs_to_jiffies(100); |
1459 | ||
1d046793 | 1460 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1461 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1462 | ||
1463 | /* in HS, means ON */ | |
1464 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1465 | break; | |
1466 | } | |
1467 | ||
1468 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1469 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1470 | ret = -EINVAL; | |
1471 | } | |
1472 | ||
1473 | out: | |
1474 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1475 | ||
1476 | return ret; | |
1477 | } | |
1478 | ||
1479 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1480 | int is_selfpowered) | |
1481 | { | |
1482 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1483 | unsigned long flags; |
72246da4 | 1484 | |
249a4569 | 1485 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1486 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1487 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
7b2a0368 | 1492 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1493 | { |
1494 | u32 reg; | |
61d58242 | 1495 | u32 timeout = 500; |
72246da4 FB |
1496 | |
1497 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1498 | if (is_on) { |
802fde98 PZ |
1499 | if (dwc->revision <= DWC3_REVISION_187A) { |
1500 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1501 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1502 | } | |
1503 | ||
1504 | if (dwc->revision >= DWC3_REVISION_194A) | |
1505 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1506 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1507 | |
1508 | if (dwc->has_hibernation) | |
1509 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1510 | ||
9fcb3bd8 | 1511 | dwc->pullups_connected = true; |
8db7ed15 | 1512 | } else { |
72246da4 | 1513 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1514 | |
1515 | if (dwc->has_hibernation && !suspend) | |
1516 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1517 | ||
9fcb3bd8 | 1518 | dwc->pullups_connected = false; |
8db7ed15 | 1519 | } |
72246da4 FB |
1520 | |
1521 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1522 | ||
1523 | do { | |
1524 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1525 | if (is_on) { | |
1526 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1527 | break; | |
1528 | } else { | |
1529 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1530 | break; | |
1531 | } | |
72246da4 FB |
1532 | timeout--; |
1533 | if (!timeout) | |
6f17f74b | 1534 | return -ETIMEDOUT; |
61d58242 | 1535 | udelay(1); |
72246da4 FB |
1536 | } while (1); |
1537 | ||
1538 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1539 | dwc->gadget_driver | |
1540 | ? dwc->gadget_driver->function : "no-function", | |
1541 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1542 | |
1543 | return 0; | |
72246da4 FB |
1544 | } |
1545 | ||
1546 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1547 | { | |
1548 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1549 | unsigned long flags; | |
6f17f74b | 1550 | int ret; |
72246da4 FB |
1551 | |
1552 | is_on = !!is_on; | |
1553 | ||
1554 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1555 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1556 | spin_unlock_irqrestore(&dwc->lock, flags); |
1557 | ||
6f17f74b | 1558 | return ret; |
72246da4 FB |
1559 | } |
1560 | ||
8698e2ac FB |
1561 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1562 | { | |
1563 | u32 reg; | |
1564 | ||
1565 | /* Enable all but Start and End of Frame IRQs */ | |
1566 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1567 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1568 | DWC3_DEVTEN_CMDCMPLTEN | | |
1569 | DWC3_DEVTEN_ERRTICERREN | | |
1570 | DWC3_DEVTEN_WKUPEVTEN | | |
1571 | DWC3_DEVTEN_ULSTCNGEN | | |
1572 | DWC3_DEVTEN_CONNECTDONEEN | | |
1573 | DWC3_DEVTEN_USBRSTEN | | |
1574 | DWC3_DEVTEN_DISCONNEVTEN); | |
1575 | ||
1576 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1577 | } | |
1578 | ||
1579 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1580 | { | |
1581 | /* mask all interrupts */ | |
1582 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1583 | } | |
1584 | ||
1585 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1586 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1587 | |
72246da4 FB |
1588 | static int dwc3_gadget_start(struct usb_gadget *g, |
1589 | struct usb_gadget_driver *driver) | |
1590 | { | |
1591 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1592 | struct dwc3_ep *dep; | |
1593 | unsigned long flags; | |
1594 | int ret = 0; | |
8698e2ac | 1595 | int irq; |
72246da4 FB |
1596 | u32 reg; |
1597 | ||
b0d7ffd4 FB |
1598 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1599 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1600 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1601 | if (ret) { |
1602 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1603 | irq, ret); | |
1604 | goto err0; | |
1605 | } | |
1606 | ||
72246da4 FB |
1607 | spin_lock_irqsave(&dwc->lock, flags); |
1608 | ||
1609 | if (dwc->gadget_driver) { | |
1610 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1611 | dwc->gadget.name, | |
1612 | dwc->gadget_driver->driver.name); | |
1613 | ret = -EBUSY; | |
b0d7ffd4 | 1614 | goto err1; |
72246da4 FB |
1615 | } |
1616 | ||
1617 | dwc->gadget_driver = driver; | |
72246da4 | 1618 | |
72246da4 FB |
1619 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1620 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1621 | |
1622 | /** | |
1623 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1624 | * which would cause metastability state on Run/Stop | |
1625 | * bit if we try to force the IP to USB2-only mode. | |
1626 | * | |
1627 | * Because of that, we cannot configure the IP to any | |
1628 | * speed other than the SuperSpeed | |
1629 | * | |
1630 | * Refers to: | |
1631 | * | |
1632 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1633 | * USB 2.0 Mode | |
1634 | */ | |
f7e846f0 | 1635 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1636 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1637 | } else { |
1638 | switch (dwc->maximum_speed) { | |
1639 | case USB_SPEED_LOW: | |
1640 | reg |= DWC3_DSTS_LOWSPEED; | |
1641 | break; | |
1642 | case USB_SPEED_FULL: | |
1643 | reg |= DWC3_DSTS_FULLSPEED1; | |
1644 | break; | |
1645 | case USB_SPEED_HIGH: | |
1646 | reg |= DWC3_DSTS_HIGHSPEED; | |
1647 | break; | |
1648 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1649 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1650 | default: | |
1651 | reg |= DWC3_DSTS_SUPERSPEED; | |
1652 | } | |
1653 | } | |
72246da4 FB |
1654 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1655 | ||
b23c8439 PZ |
1656 | dwc->start_config_issued = false; |
1657 | ||
72246da4 FB |
1658 | /* Start with SuperSpeed Default */ |
1659 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1660 | ||
1661 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1662 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1663 | false); | |
72246da4 FB |
1664 | if (ret) { |
1665 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1666 | goto err2; |
72246da4 FB |
1667 | } |
1668 | ||
1669 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1670 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1671 | false); | |
72246da4 FB |
1672 | if (ret) { |
1673 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1674 | goto err3; |
72246da4 FB |
1675 | } |
1676 | ||
1677 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1678 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1679 | dwc3_ep0_out_start(dwc); |
1680 | ||
8698e2ac FB |
1681 | dwc3_gadget_enable_irq(dwc); |
1682 | ||
72246da4 FB |
1683 | spin_unlock_irqrestore(&dwc->lock, flags); |
1684 | ||
1685 | return 0; | |
1686 | ||
b0d7ffd4 | 1687 | err3: |
72246da4 FB |
1688 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1689 | ||
b0d7ffd4 | 1690 | err2: |
cdcedd69 | 1691 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1692 | |
1693 | err1: | |
72246da4 FB |
1694 | spin_unlock_irqrestore(&dwc->lock, flags); |
1695 | ||
b0d7ffd4 FB |
1696 | free_irq(irq, dwc); |
1697 | ||
1698 | err0: | |
72246da4 FB |
1699 | return ret; |
1700 | } | |
1701 | ||
1702 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1703 | struct usb_gadget_driver *driver) | |
1704 | { | |
1705 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1706 | unsigned long flags; | |
8698e2ac | 1707 | int irq; |
72246da4 FB |
1708 | |
1709 | spin_lock_irqsave(&dwc->lock, flags); | |
1710 | ||
8698e2ac | 1711 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1712 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1713 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1714 | ||
1715 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1716 | |
1717 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1718 | ||
b0d7ffd4 FB |
1719 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1720 | free_irq(irq, dwc); | |
1721 | ||
72246da4 FB |
1722 | return 0; |
1723 | } | |
802fde98 | 1724 | |
72246da4 FB |
1725 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1726 | .get_frame = dwc3_gadget_get_frame, | |
1727 | .wakeup = dwc3_gadget_wakeup, | |
1728 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1729 | .pullup = dwc3_gadget_pullup, | |
1730 | .udc_start = dwc3_gadget_start, | |
1731 | .udc_stop = dwc3_gadget_stop, | |
1732 | }; | |
1733 | ||
1734 | /* -------------------------------------------------------------------------- */ | |
1735 | ||
6a1e3ef4 FB |
1736 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1737 | u8 num, u32 direction) | |
72246da4 FB |
1738 | { |
1739 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1740 | u8 i; |
72246da4 | 1741 | |
6a1e3ef4 FB |
1742 | for (i = 0; i < num; i++) { |
1743 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1744 | |
72246da4 FB |
1745 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
1746 | if (!dep) { | |
1747 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1748 | epnum); | |
1749 | return -ENOMEM; | |
1750 | } | |
1751 | ||
1752 | dep->dwc = dwc; | |
1753 | dep->number = epnum; | |
9aa62ae4 | 1754 | dep->direction = !!direction; |
72246da4 FB |
1755 | dwc->eps[epnum] = dep; |
1756 | ||
1757 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1758 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1759 | |
72246da4 | 1760 | dep->endpoint.name = dep->name; |
72246da4 | 1761 | |
653df35e FB |
1762 | dev_vdbg(dwc->dev, "initializing %s\n", dep->name); |
1763 | ||
72246da4 | 1764 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1765 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1766 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1767 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1768 | if (!epnum) | |
1769 | dwc->gadget.ep0 = &dep->endpoint; | |
1770 | } else { | |
1771 | int ret; | |
1772 | ||
e117e742 | 1773 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1774 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1775 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1776 | list_add_tail(&dep->endpoint.ep_list, | |
1777 | &dwc->gadget.ep_list); | |
1778 | ||
1779 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1780 | if (ret) |
72246da4 | 1781 | return ret; |
72246da4 | 1782 | } |
25b8ff68 | 1783 | |
72246da4 FB |
1784 | INIT_LIST_HEAD(&dep->request_list); |
1785 | INIT_LIST_HEAD(&dep->req_queued); | |
1786 | } | |
1787 | ||
1788 | return 0; | |
1789 | } | |
1790 | ||
6a1e3ef4 FB |
1791 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1792 | { | |
1793 | int ret; | |
1794 | ||
1795 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1796 | ||
1797 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1798 | if (ret < 0) { | |
1799 | dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); | |
1800 | return ret; | |
1801 | } | |
1802 | ||
1803 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1804 | if (ret < 0) { | |
1805 | dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); | |
1806 | return ret; | |
1807 | } | |
1808 | ||
1809 | return 0; | |
1810 | } | |
1811 | ||
72246da4 FB |
1812 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1813 | { | |
1814 | struct dwc3_ep *dep; | |
1815 | u8 epnum; | |
1816 | ||
1817 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1818 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1819 | if (!dep) |
1820 | continue; | |
5bf8fae3 GC |
1821 | /* |
1822 | * Physical endpoints 0 and 1 are special; they form the | |
1823 | * bi-directional USB endpoint 0. | |
1824 | * | |
1825 | * For those two physical endpoints, we don't allocate a TRB | |
1826 | * pool nor do we add them the endpoints list. Due to that, we | |
1827 | * shouldn't do these two operations otherwise we would end up | |
1828 | * with all sorts of bugs when removing dwc3.ko. | |
1829 | */ | |
1830 | if (epnum != 0 && epnum != 1) { | |
1831 | dwc3_free_trb_pool(dep); | |
72246da4 | 1832 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1833 | } |
72246da4 FB |
1834 | |
1835 | kfree(dep); | |
1836 | } | |
1837 | } | |
1838 | ||
72246da4 | 1839 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1840 | |
e5ba5ec8 PA |
1841 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1842 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1843 | const struct dwc3_event_depevt *event, int status) |
1844 | { | |
72246da4 FB |
1845 | unsigned int count; |
1846 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1847 | unsigned int trb_status; |
72246da4 | 1848 | |
e5ba5ec8 PA |
1849 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1850 | /* | |
1851 | * We continue despite the error. There is not much we | |
1852 | * can do. If we don't clean it up we loop forever. If | |
1853 | * we skip the TRB then it gets overwritten after a | |
1854 | * while since we use them in a ring buffer. A BUG() | |
1855 | * would help. Lets hope that if this occurs, someone | |
1856 | * fixes the root cause instead of looking away :) | |
1857 | */ | |
1858 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1859 | dep->name, trb); | |
1860 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1861 | ||
1862 | if (dep->direction) { | |
1863 | if (count) { | |
1864 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1865 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1866 | dev_dbg(dwc->dev, "incomplete IN transfer %s\n", | |
1867 | dep->name); | |
1868 | /* | |
1869 | * If missed isoc occurred and there is | |
1870 | * no request queued then issue END | |
1871 | * TRANSFER, so that core generates | |
1872 | * next xfernotready and we will issue | |
1873 | * a fresh START TRANSFER. | |
1874 | * If there are still queued request | |
1875 | * then wait, do not issue either END | |
1876 | * or UPDATE TRANSFER, just attach next | |
1877 | * request in request_list during | |
1878 | * giveback.If any future queued request | |
1879 | * is successfully transferred then we | |
1880 | * will issue UPDATE TRANSFER for all | |
1881 | * request in the request_list. | |
1882 | */ | |
1883 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1884 | } else { | |
1885 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1886 | dep->name); | |
1887 | status = -ECONNRESET; | |
1888 | } | |
1889 | } else { | |
1890 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1891 | } | |
1892 | } else { | |
1893 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1894 | s_pkt = 1; | |
1895 | } | |
1896 | ||
1897 | /* | |
1898 | * We assume here we will always receive the entire data block | |
1899 | * which we should receive. Meaning, if we program RX to | |
1900 | * receive 4K but we receive only 2K, we assume that's all we | |
1901 | * should receive and we simply bounce the request back to the | |
1902 | * gadget driver for further processing. | |
1903 | */ | |
1904 | req->request.actual += req->request.length - count; | |
1905 | if (s_pkt) | |
1906 | return 1; | |
1907 | if ((event->status & DEPEVT_STATUS_LST) && | |
1908 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1909 | DWC3_TRB_CTRL_HWO))) | |
1910 | return 1; | |
1911 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1912 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1913 | return 1; | |
1914 | return 0; | |
1915 | } | |
1916 | ||
1917 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1918 | const struct dwc3_event_depevt *event, int status) | |
1919 | { | |
1920 | struct dwc3_request *req; | |
1921 | struct dwc3_trb *trb; | |
1922 | unsigned int slot; | |
1923 | unsigned int i; | |
1924 | int ret; | |
1925 | ||
72246da4 FB |
1926 | do { |
1927 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1928 | if (!req) { |
1929 | WARN_ON_ONCE(1); | |
1930 | return 1; | |
1931 | } | |
e5ba5ec8 PA |
1932 | i = 0; |
1933 | do { | |
1934 | slot = req->start_slot + i; | |
1935 | if ((slot == DWC3_TRB_NUM - 1) && | |
1936 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
1937 | slot++; | |
1938 | slot %= DWC3_TRB_NUM; | |
1939 | trb = &dep->trb_pool[slot]; | |
72246da4 | 1940 | |
e5ba5ec8 PA |
1941 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
1942 | event, status); | |
1943 | if (ret) | |
1944 | break; | |
1945 | }while (++i < req->request.num_mapped_sgs); | |
72246da4 | 1946 | |
72246da4 | 1947 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 PA |
1948 | |
1949 | if (ret) | |
72246da4 FB |
1950 | break; |
1951 | } while (1); | |
1952 | ||
cdc359dd PA |
1953 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1954 | list_empty(&dep->req_queued)) { | |
1955 | if (list_empty(&dep->request_list)) { | |
1956 | /* | |
1957 | * If there is no entry in request list then do | |
1958 | * not issue END TRANSFER now. Just set PENDING | |
1959 | * flag, so that END TRANSFER is issued when an | |
1960 | * entry is added into request list. | |
1961 | */ | |
1962 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1963 | } else { | |
b992e681 | 1964 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1965 | dep->flags = DWC3_EP_ENABLED; |
1966 | } | |
7efea86c PA |
1967 | return 1; |
1968 | } | |
1969 | ||
72246da4 FB |
1970 | return 1; |
1971 | } | |
1972 | ||
1973 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 1974 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
1975 | { |
1976 | unsigned status = 0; | |
1977 | int clean_busy; | |
1978 | ||
1979 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1980 | status = -ECONNRESET; | |
1981 | ||
1d046793 | 1982 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1983 | if (clean_busy) |
72246da4 | 1984 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1985 | |
1986 | /* | |
1987 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1988 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1989 | */ | |
1990 | if (dwc->revision < DWC3_REVISION_183A) { | |
1991 | u32 reg; | |
1992 | int i; | |
1993 | ||
1994 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 1995 | dep = dwc->eps[i]; |
fae2b904 FB |
1996 | |
1997 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1998 | continue; | |
1999 | ||
2000 | if (!list_empty(&dep->req_queued)) | |
2001 | return; | |
2002 | } | |
2003 | ||
2004 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2005 | reg |= dwc->u1u2; | |
2006 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2007 | ||
2008 | dwc->u1u2 = 0; | |
2009 | } | |
72246da4 FB |
2010 | } |
2011 | ||
72246da4 FB |
2012 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2013 | const struct dwc3_event_depevt *event) | |
2014 | { | |
2015 | struct dwc3_ep *dep; | |
2016 | u8 epnum = event->endpoint_number; | |
2017 | ||
2018 | dep = dwc->eps[epnum]; | |
2019 | ||
3336abb5 FB |
2020 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2021 | return; | |
2022 | ||
72246da4 FB |
2023 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, |
2024 | dwc3_ep_event_string(event->endpoint_event)); | |
2025 | ||
2026 | if (epnum == 0 || epnum == 1) { | |
2027 | dwc3_ep0_interrupt(dwc, event); | |
2028 | return; | |
2029 | } | |
2030 | ||
2031 | switch (event->endpoint_event) { | |
2032 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2033 | dep->resource_index = 0; |
c2df85ca | 2034 | |
16e78db7 | 2035 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2036 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
2037 | dep->name); | |
2038 | return; | |
2039 | } | |
2040 | ||
029d97ff | 2041 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2042 | break; |
2043 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 2044 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2045 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
2046 | dep->name); | |
2047 | return; | |
2048 | } | |
2049 | ||
029d97ff | 2050 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2051 | break; |
2052 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2053 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2054 | dwc3_gadget_start_isoc(dwc, dep, event); |
2055 | } else { | |
2056 | int ret; | |
2057 | ||
2058 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
2059 | dep->name, event->status & |
2060 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
2061 | ? "Transfer Active" |
2062 | : "Transfer Not Active"); | |
2063 | ||
2064 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
2065 | if (!ret || ret == -EBUSY) | |
2066 | return; | |
2067 | ||
2068 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
2069 | dep->name); | |
2070 | } | |
2071 | ||
879631aa FB |
2072 | break; |
2073 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2074 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2075 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2076 | dep->name); | |
2077 | return; | |
2078 | } | |
2079 | ||
2080 | switch (event->status) { | |
2081 | case DEPEVT_STREAMEVT_FOUND: | |
2082 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
2083 | event->parameters); | |
2084 | ||
2085 | break; | |
2086 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2087 | /* FALLTHROUGH */ | |
2088 | default: | |
2089 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
2090 | } | |
72246da4 FB |
2091 | break; |
2092 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
2093 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
2094 | break; | |
72246da4 | 2095 | case DWC3_DEPEVT_EPCMDCMPLT: |
ea53b882 | 2096 | dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); |
72246da4 FB |
2097 | break; |
2098 | } | |
2099 | } | |
2100 | ||
2101 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2102 | { | |
2103 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2104 | spin_unlock(&dwc->lock); | |
2105 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2106 | spin_lock(&dwc->lock); | |
2107 | } | |
2108 | } | |
2109 | ||
bc5ba2e0 FB |
2110 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2111 | { | |
73a30bfc | 2112 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2113 | spin_unlock(&dwc->lock); |
2114 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2115 | spin_lock(&dwc->lock); | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2120 | { | |
73a30bfc | 2121 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2122 | spin_unlock(&dwc->lock); |
2123 | dwc->gadget_driver->resume(&dwc->gadget); | |
2124 | spin_lock(&dwc->lock); | |
2125 | } | |
2126 | } | |
2127 | ||
b992e681 | 2128 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2129 | { |
2130 | struct dwc3_ep *dep; | |
2131 | struct dwc3_gadget_ep_cmd_params params; | |
2132 | u32 cmd; | |
2133 | int ret; | |
2134 | ||
2135 | dep = dwc->eps[epnum]; | |
2136 | ||
b4996a86 | 2137 | if (!dep->resource_index) |
3daf74d7 PA |
2138 | return; |
2139 | ||
57911504 PA |
2140 | /* |
2141 | * NOTICE: We are violating what the Databook says about the | |
2142 | * EndTransfer command. Ideally we would _always_ wait for the | |
2143 | * EndTransfer Command Completion IRQ, but that's causing too | |
2144 | * much trouble synchronizing between us and gadget driver. | |
2145 | * | |
2146 | * We have discussed this with the IP Provider and it was | |
2147 | * suggested to giveback all requests here, but give HW some | |
2148 | * extra time to synchronize with the interconnect. We're using | |
2149 | * an arbitraty 100us delay for that. | |
2150 | * | |
2151 | * Note also that a similar handling was tested by Synopsys | |
2152 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2153 | * In short, what we're doing is: | |
2154 | * | |
2155 | * - Issue EndTransfer WITH CMDIOC bit set | |
2156 | * - Wait 100us | |
2157 | */ | |
2158 | ||
3daf74d7 | 2159 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2160 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2161 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2162 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2163 | memset(¶ms, 0, sizeof(params)); |
2164 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2165 | WARN_ON_ONCE(ret); | |
b4996a86 | 2166 | dep->resource_index = 0; |
041d81f4 | 2167 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2168 | udelay(100); |
72246da4 FB |
2169 | } |
2170 | ||
2171 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2172 | { | |
2173 | u32 epnum; | |
2174 | ||
2175 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2176 | struct dwc3_ep *dep; | |
2177 | ||
2178 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2179 | if (!dep) |
2180 | continue; | |
2181 | ||
72246da4 FB |
2182 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2183 | continue; | |
2184 | ||
624407f9 | 2185 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2186 | } |
2187 | } | |
2188 | ||
2189 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2190 | { | |
2191 | u32 epnum; | |
2192 | ||
2193 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2194 | struct dwc3_ep *dep; | |
2195 | struct dwc3_gadget_ep_cmd_params params; | |
2196 | int ret; | |
2197 | ||
2198 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2199 | if (!dep) |
2200 | continue; | |
72246da4 FB |
2201 | |
2202 | if (!(dep->flags & DWC3_EP_STALL)) | |
2203 | continue; | |
2204 | ||
2205 | dep->flags &= ~DWC3_EP_STALL; | |
2206 | ||
2207 | memset(¶ms, 0, sizeof(params)); | |
2208 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2209 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2210 | WARN_ON_ONCE(ret); | |
2211 | } | |
2212 | } | |
2213 | ||
2214 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2215 | { | |
c4430a26 FB |
2216 | int reg; |
2217 | ||
72246da4 | 2218 | dev_vdbg(dwc->dev, "%s\n", __func__); |
72246da4 FB |
2219 | |
2220 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2221 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2222 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2223 | ||
2224 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2225 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2226 | |
72246da4 | 2227 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2228 | dwc->start_config_issued = false; |
72246da4 FB |
2229 | |
2230 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2231 | dwc->setup_packet_pending = false; |
72246da4 FB |
2232 | } |
2233 | ||
72246da4 FB |
2234 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2235 | { | |
2236 | u32 reg; | |
2237 | ||
2238 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2239 | ||
df62df56 FB |
2240 | /* |
2241 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2242 | * would cause a missing Disconnect Event if there's a | |
2243 | * pending Setup Packet in the FIFO. | |
2244 | * | |
2245 | * There's no suggested workaround on the official Bug | |
2246 | * report, which states that "unless the driver/application | |
2247 | * is doing any special handling of a disconnect event, | |
2248 | * there is no functional issue". | |
2249 | * | |
2250 | * Unfortunately, it turns out that we _do_ some special | |
2251 | * handling of a disconnect event, namely complete all | |
2252 | * pending transfers, notify gadget driver of the | |
2253 | * disconnection, and so on. | |
2254 | * | |
2255 | * Our suggested workaround is to follow the Disconnect | |
2256 | * Event steps here, instead, based on a setup_packet_pending | |
2257 | * flag. Such flag gets set whenever we have a XferNotReady | |
2258 | * event on EP0 and gets cleared on XferComplete for the | |
2259 | * same endpoint. | |
2260 | * | |
2261 | * Refers to: | |
2262 | * | |
2263 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2264 | * generated if setup packet pending in FIFO | |
2265 | */ | |
2266 | if (dwc->revision < DWC3_REVISION_188A) { | |
2267 | if (dwc->setup_packet_pending) | |
2268 | dwc3_gadget_disconnect_interrupt(dwc); | |
2269 | } | |
2270 | ||
961906ed | 2271 | /* after reset -> Default State */ |
14cd592f | 2272 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
961906ed | 2273 | |
72246da4 FB |
2274 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) |
2275 | dwc3_disconnect_gadget(dwc); | |
2276 | ||
2277 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2278 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2279 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2280 | dwc->test_mode = false; |
72246da4 FB |
2281 | |
2282 | dwc3_stop_active_transfers(dwc); | |
2283 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2284 | dwc->start_config_issued = false; |
72246da4 FB |
2285 | |
2286 | /* Reset device address to zero */ | |
2287 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2288 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2289 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2290 | } |
2291 | ||
2292 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2293 | { | |
2294 | u32 reg; | |
2295 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2296 | ||
2297 | /* | |
2298 | * We change the clock only at SS but I dunno why I would want to do | |
2299 | * this. Maybe it becomes part of the power saving plan. | |
2300 | */ | |
2301 | ||
2302 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2303 | return; | |
2304 | ||
2305 | /* | |
2306 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2307 | * each time on Connect Done. | |
2308 | */ | |
2309 | if (!usb30_clock) | |
2310 | return; | |
2311 | ||
2312 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2313 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2314 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2315 | } | |
2316 | ||
72246da4 FB |
2317 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2318 | { | |
72246da4 FB |
2319 | struct dwc3_ep *dep; |
2320 | int ret; | |
2321 | u32 reg; | |
2322 | u8 speed; | |
2323 | ||
2324 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2325 | ||
72246da4 FB |
2326 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2327 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2328 | dwc->speed = speed; | |
2329 | ||
2330 | dwc3_update_ram_clk_sel(dwc, speed); | |
2331 | ||
2332 | switch (speed) { | |
2333 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2334 | /* |
2335 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2336 | * would cause a missing USB3 Reset event. | |
2337 | * | |
2338 | * In such situations, we should force a USB3 Reset | |
2339 | * event by calling our dwc3_gadget_reset_interrupt() | |
2340 | * routine. | |
2341 | * | |
2342 | * Refers to: | |
2343 | * | |
2344 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2345 | * not be generated always when the link enters poll | |
2346 | */ | |
2347 | if (dwc->revision < DWC3_REVISION_190A) | |
2348 | dwc3_gadget_reset_interrupt(dwc); | |
2349 | ||
72246da4 FB |
2350 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2351 | dwc->gadget.ep0->maxpacket = 512; | |
2352 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2353 | break; | |
2354 | case DWC3_DCFG_HIGHSPEED: | |
2355 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2356 | dwc->gadget.ep0->maxpacket = 64; | |
2357 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2358 | break; | |
2359 | case DWC3_DCFG_FULLSPEED2: | |
2360 | case DWC3_DCFG_FULLSPEED1: | |
2361 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2362 | dwc->gadget.ep0->maxpacket = 64; | |
2363 | dwc->gadget.speed = USB_SPEED_FULL; | |
2364 | break; | |
2365 | case DWC3_DCFG_LOWSPEED: | |
2366 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2367 | dwc->gadget.ep0->maxpacket = 8; | |
2368 | dwc->gadget.speed = USB_SPEED_LOW; | |
2369 | break; | |
2370 | } | |
2371 | ||
2b758350 PA |
2372 | /* Enable USB2 LPM Capability */ |
2373 | ||
2374 | if ((dwc->revision > DWC3_REVISION_194A) | |
2375 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2376 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2377 | reg |= DWC3_DCFG_LPM_CAP; | |
2378 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2379 | ||
2380 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2381 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2382 | ||
1a947746 FB |
2383 | /* |
2384 | * TODO: This should be configurable. For now using | |
2385 | * maximum allowed HIRD threshold value of 0b1100 | |
2386 | */ | |
2387 | reg |= DWC3_DCTL_HIRD_THRES(12); | |
2b758350 | 2388 | |
356363bf FB |
2389 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2390 | } else { | |
2391 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2392 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2393 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2394 | } | |
2395 | ||
72246da4 | 2396 | dep = dwc->eps[0]; |
265b70a7 PZ |
2397 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2398 | false); | |
72246da4 FB |
2399 | if (ret) { |
2400 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2401 | return; | |
2402 | } | |
2403 | ||
2404 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2405 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2406 | false); | |
72246da4 FB |
2407 | if (ret) { |
2408 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2409 | return; | |
2410 | } | |
2411 | ||
2412 | /* | |
2413 | * Configure PHY via GUSB3PIPECTLn if required. | |
2414 | * | |
2415 | * Update GTXFIFOSIZn | |
2416 | * | |
2417 | * In both cases reset values should be sufficient. | |
2418 | */ | |
2419 | } | |
2420 | ||
2421 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2422 | { | |
2423 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2424 | ||
2425 | /* | |
2426 | * TODO take core out of low power mode when that's | |
2427 | * implemented. | |
2428 | */ | |
2429 | ||
2430 | dwc->gadget_driver->resume(&dwc->gadget); | |
2431 | } | |
2432 | ||
2433 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2434 | unsigned int evtinfo) | |
2435 | { | |
fae2b904 | 2436 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2437 | unsigned int pwropt; |
2438 | ||
2439 | /* | |
2440 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2441 | * Hibernation mode enabled which would show up when device detects | |
2442 | * host-initiated U3 exit. | |
2443 | * | |
2444 | * In that case, device will generate a Link State Change Interrupt | |
2445 | * from U3 to RESUME which is only necessary if Hibernation is | |
2446 | * configured in. | |
2447 | * | |
2448 | * There are no functional changes due to such spurious event and we | |
2449 | * just need to ignore it. | |
2450 | * | |
2451 | * Refers to: | |
2452 | * | |
2453 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2454 | * operational mode | |
2455 | */ | |
2456 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2457 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2458 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2459 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2460 | (next == DWC3_LINK_STATE_RESUME)) { | |
2461 | dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); | |
2462 | return; | |
2463 | } | |
2464 | } | |
fae2b904 FB |
2465 | |
2466 | /* | |
2467 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2468 | * on the link partner, the USB session might do multiple entry/exit | |
2469 | * of low power states before a transfer takes place. | |
2470 | * | |
2471 | * Due to this problem, we might experience lower throughput. The | |
2472 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2473 | * transitioning from U1/U2 to U0 and enable those bits again | |
2474 | * after a transfer completes and there are no pending transfers | |
2475 | * on any of the enabled endpoints. | |
2476 | * | |
2477 | * This is the first half of that workaround. | |
2478 | * | |
2479 | * Refers to: | |
2480 | * | |
2481 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2482 | * core send LGO_Ux entering U0 | |
2483 | */ | |
2484 | if (dwc->revision < DWC3_REVISION_183A) { | |
2485 | if (next == DWC3_LINK_STATE_U0) { | |
2486 | u32 u1u2; | |
2487 | u32 reg; | |
2488 | ||
2489 | switch (dwc->link_state) { | |
2490 | case DWC3_LINK_STATE_U1: | |
2491 | case DWC3_LINK_STATE_U2: | |
2492 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2493 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2494 | | DWC3_DCTL_ACCEPTU2ENA | |
2495 | | DWC3_DCTL_INITU1ENA | |
2496 | | DWC3_DCTL_ACCEPTU1ENA); | |
2497 | ||
2498 | if (!dwc->u1u2) | |
2499 | dwc->u1u2 = reg & u1u2; | |
2500 | ||
2501 | reg &= ~u1u2; | |
2502 | ||
2503 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2504 | break; | |
2505 | default: | |
2506 | /* do nothing */ | |
2507 | break; | |
2508 | } | |
2509 | } | |
2510 | } | |
2511 | ||
bc5ba2e0 FB |
2512 | switch (next) { |
2513 | case DWC3_LINK_STATE_U1: | |
2514 | if (dwc->speed == USB_SPEED_SUPER) | |
2515 | dwc3_suspend_gadget(dwc); | |
2516 | break; | |
2517 | case DWC3_LINK_STATE_U2: | |
2518 | case DWC3_LINK_STATE_U3: | |
2519 | dwc3_suspend_gadget(dwc); | |
2520 | break; | |
2521 | case DWC3_LINK_STATE_RESUME: | |
2522 | dwc3_resume_gadget(dwc); | |
2523 | break; | |
2524 | default: | |
2525 | /* do nothing */ | |
2526 | break; | |
2527 | } | |
2528 | ||
e57ebc1d FB |
2529 | dev_vdbg(dwc->dev, "link change: %s [%d] -> %s [%d]\n", |
2530 | dwc3_gadget_link_string(dwc->link_state), | |
2531 | dwc->link_state, dwc3_gadget_link_string(next), next); | |
2532 | ||
2533 | dwc->link_state = next; | |
72246da4 FB |
2534 | } |
2535 | ||
e1dadd3b FB |
2536 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2537 | unsigned int evtinfo) | |
2538 | { | |
2539 | unsigned int is_ss = evtinfo & BIT(4); | |
2540 | ||
2541 | /** | |
2542 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2543 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2544 | * randomly. | |
2545 | * | |
2546 | * Because of this issue, core could generate bogus hibernation | |
2547 | * events which SW needs to ignore. | |
2548 | * | |
2549 | * Refers to: | |
2550 | * | |
2551 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2552 | * Device Fallback from SuperSpeed | |
2553 | */ | |
2554 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2555 | return; | |
2556 | ||
2557 | /* enter hibernation here */ | |
2558 | } | |
2559 | ||
72246da4 FB |
2560 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2561 | const struct dwc3_event_devt *event) | |
2562 | { | |
2563 | switch (event->type) { | |
2564 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2565 | dwc3_gadget_disconnect_interrupt(dwc); | |
2566 | break; | |
2567 | case DWC3_DEVICE_EVENT_RESET: | |
2568 | dwc3_gadget_reset_interrupt(dwc); | |
2569 | break; | |
2570 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2571 | dwc3_gadget_conndone_interrupt(dwc); | |
2572 | break; | |
2573 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2574 | dwc3_gadget_wakeup_interrupt(dwc); | |
2575 | break; | |
e1dadd3b FB |
2576 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2577 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2578 | "unexpected hibernation event\n")) | |
2579 | break; | |
2580 | ||
2581 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2582 | break; | |
72246da4 FB |
2583 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2584 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2585 | break; | |
2586 | case DWC3_DEVICE_EVENT_EOPF: | |
2587 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2588 | break; | |
2589 | case DWC3_DEVICE_EVENT_SOF: | |
2590 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2591 | break; | |
2592 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2593 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2594 | break; | |
2595 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2596 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2597 | break; | |
2598 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2599 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2600 | break; | |
2601 | default: | |
2602 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2607 | const union dwc3_event *event) | |
2608 | { | |
2609 | /* Endpoint IRQ, handle it and return early */ | |
2610 | if (event->type.is_devspec == 0) { | |
2611 | /* depevt */ | |
2612 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2613 | } | |
2614 | ||
2615 | switch (event->type.type) { | |
2616 | case DWC3_EVENT_TYPE_DEV: | |
2617 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2618 | break; | |
2619 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2620 | default: | |
2621 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2622 | } | |
2623 | } | |
2624 | ||
f42f2447 | 2625 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2626 | { |
f42f2447 | 2627 | struct dwc3_event_buffer *evt; |
b15a762f | 2628 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2629 | int left; |
e8adfc30 | 2630 | u32 reg; |
b15a762f | 2631 | |
f42f2447 FB |
2632 | evt = dwc->ev_buffs[buf]; |
2633 | left = evt->count; | |
b15a762f | 2634 | |
f42f2447 FB |
2635 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2636 | return IRQ_NONE; | |
b15a762f | 2637 | |
f42f2447 FB |
2638 | while (left > 0) { |
2639 | union dwc3_event event; | |
b15a762f | 2640 | |
f42f2447 | 2641 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2642 | |
f42f2447 | 2643 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2644 | |
f42f2447 FB |
2645 | /* |
2646 | * FIXME we wrap around correctly to the next entry as | |
2647 | * almost all entries are 4 bytes in size. There is one | |
2648 | * entry which has 12 bytes which is a regular entry | |
2649 | * followed by 8 bytes data. ATM I don't know how | |
2650 | * things are organized if we get next to the a | |
2651 | * boundary so I worry about that once we try to handle | |
2652 | * that. | |
2653 | */ | |
2654 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2655 | left -= 4; | |
b15a762f | 2656 | |
f42f2447 FB |
2657 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2658 | } | |
b15a762f | 2659 | |
f42f2447 FB |
2660 | evt->count = 0; |
2661 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2662 | ret = IRQ_HANDLED; | |
b15a762f | 2663 | |
f42f2447 FB |
2664 | /* Unmask interrupt */ |
2665 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2666 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2667 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2668 | |
f42f2447 FB |
2669 | return ret; |
2670 | } | |
e8adfc30 | 2671 | |
f42f2447 FB |
2672 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2673 | { | |
2674 | struct dwc3 *dwc = _dwc; | |
2675 | unsigned long flags; | |
2676 | irqreturn_t ret = IRQ_NONE; | |
2677 | int i; | |
2678 | ||
2679 | spin_lock_irqsave(&dwc->lock, flags); | |
2680 | ||
2681 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2682 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f FB |
2683 | |
2684 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2685 | ||
2686 | return ret; | |
2687 | } | |
2688 | ||
7f97aa98 | 2689 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2690 | { |
2691 | struct dwc3_event_buffer *evt; | |
72246da4 | 2692 | u32 count; |
e8adfc30 | 2693 | u32 reg; |
72246da4 | 2694 | |
b15a762f FB |
2695 | evt = dwc->ev_buffs[buf]; |
2696 | ||
72246da4 FB |
2697 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2698 | count &= DWC3_GEVNTCOUNT_MASK; | |
2699 | if (!count) | |
2700 | return IRQ_NONE; | |
2701 | ||
b15a762f FB |
2702 | evt->count = count; |
2703 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2704 | |
e8adfc30 FB |
2705 | /* Mask interrupt */ |
2706 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2707 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2708 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2709 | ||
b15a762f | 2710 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2711 | } |
2712 | ||
2713 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2714 | { | |
2715 | struct dwc3 *dwc = _dwc; | |
2716 | int i; | |
2717 | irqreturn_t ret = IRQ_NONE; | |
2718 | ||
2719 | spin_lock(&dwc->lock); | |
2720 | ||
9f622b2a | 2721 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2722 | irqreturn_t status; |
2723 | ||
7f97aa98 | 2724 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2725 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2726 | ret = status; |
2727 | } | |
2728 | ||
2729 | spin_unlock(&dwc->lock); | |
2730 | ||
2731 | return ret; | |
2732 | } | |
2733 | ||
2734 | /** | |
2735 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2736 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2737 | * |
2738 | * Returns 0 on success otherwise negative errno. | |
2739 | */ | |
41ac7b3a | 2740 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2741 | { |
72246da4 | 2742 | int ret; |
72246da4 FB |
2743 | |
2744 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2745 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2746 | if (!dwc->ctrl_req) { | |
2747 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2748 | ret = -ENOMEM; | |
2749 | goto err0; | |
2750 | } | |
2751 | ||
2752 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2753 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2754 | if (!dwc->ep0_trb) { | |
2755 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2756 | ret = -ENOMEM; | |
2757 | goto err1; | |
2758 | } | |
2759 | ||
3ef35faf | 2760 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2761 | if (!dwc->setup_buf) { |
2762 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2763 | ret = -ENOMEM; | |
2764 | goto err2; | |
2765 | } | |
2766 | ||
5812b1c2 | 2767 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2768 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2769 | GFP_KERNEL); | |
5812b1c2 FB |
2770 | if (!dwc->ep0_bounce) { |
2771 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2772 | ret = -ENOMEM; | |
2773 | goto err3; | |
2774 | } | |
2775 | ||
72246da4 | 2776 | dwc->gadget.ops = &dwc3_gadget_ops; |
d327ab5b | 2777 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 | 2778 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2779 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2780 | dwc->gadget.name = "dwc3-gadget"; |
2781 | ||
a4b9d94b DC |
2782 | /* |
2783 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2784 | * on ep out. | |
2785 | */ | |
2786 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2787 | ||
72246da4 FB |
2788 | /* |
2789 | * REVISIT: Here we should clear all pending IRQs to be | |
2790 | * sure we're starting from a well known location. | |
2791 | */ | |
2792 | ||
2793 | ret = dwc3_gadget_init_endpoints(dwc); | |
2794 | if (ret) | |
5812b1c2 | 2795 | goto err4; |
72246da4 | 2796 | |
72246da4 FB |
2797 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2798 | if (ret) { | |
2799 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2800 | goto err4; |
72246da4 FB |
2801 | } |
2802 | ||
2803 | return 0; | |
2804 | ||
5812b1c2 | 2805 | err4: |
e1f80467 | 2806 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2807 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2808 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2809 | |
72246da4 | 2810 | err3: |
0fc9a1be | 2811 | kfree(dwc->setup_buf); |
72246da4 FB |
2812 | |
2813 | err2: | |
2814 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2815 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2816 | ||
2817 | err1: | |
2818 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2819 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2820 | ||
2821 | err0: | |
2822 | return ret; | |
2823 | } | |
2824 | ||
7415f17c FB |
2825 | /* -------------------------------------------------------------------------- */ |
2826 | ||
72246da4 FB |
2827 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2828 | { | |
72246da4 | 2829 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2830 | |
72246da4 FB |
2831 | dwc3_gadget_free_endpoints(dwc); |
2832 | ||
3ef35faf FB |
2833 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2834 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2835 | |
0fc9a1be | 2836 | kfree(dwc->setup_buf); |
72246da4 FB |
2837 | |
2838 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2839 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2840 | ||
2841 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2842 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2843 | } |
7415f17c FB |
2844 | |
2845 | int dwc3_gadget_prepare(struct dwc3 *dwc) | |
2846 | { | |
7b2a0368 | 2847 | if (dwc->pullups_connected) { |
7415f17c | 2848 | dwc3_gadget_disable_irq(dwc); |
7b2a0368 FB |
2849 | dwc3_gadget_run_stop(dwc, true, true); |
2850 | } | |
7415f17c FB |
2851 | |
2852 | return 0; | |
2853 | } | |
2854 | ||
2855 | void dwc3_gadget_complete(struct dwc3 *dwc) | |
2856 | { | |
2857 | if (dwc->pullups_connected) { | |
2858 | dwc3_gadget_enable_irq(dwc); | |
7b2a0368 | 2859 | dwc3_gadget_run_stop(dwc, true, false); |
7415f17c FB |
2860 | } |
2861 | } | |
2862 | ||
2863 | int dwc3_gadget_suspend(struct dwc3 *dwc) | |
2864 | { | |
2865 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2866 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2867 | ||
2868 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
2873 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2874 | { | |
2875 | struct dwc3_ep *dep; | |
2876 | int ret; | |
2877 | ||
2878 | /* Start with SuperSpeed Default */ | |
2879 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2880 | ||
2881 | dep = dwc->eps[0]; | |
265b70a7 PZ |
2882 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2883 | false); | |
7415f17c FB |
2884 | if (ret) |
2885 | goto err0; | |
2886 | ||
2887 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2888 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2889 | false); | |
7415f17c FB |
2890 | if (ret) |
2891 | goto err1; | |
2892 | ||
2893 | /* begin to receive SETUP packets */ | |
2894 | dwc->ep0state = EP0_SETUP_PHASE; | |
2895 | dwc3_ep0_out_start(dwc); | |
2896 | ||
2897 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2898 | ||
2899 | return 0; | |
2900 | ||
2901 | err1: | |
2902 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2903 | ||
2904 | err0: | |
2905 | return ret; | |
2906 | } |