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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
73815280 FB |
142 | dwc3_trace(trace_dwc3_gadget, |
143 | "link state change request timed out"); | |
8598bde7 FB |
144 | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
dca0119c JY |
148 | /** |
149 | * dwc3_ep_inc_trb() - Increment a TRB index. | |
150 | * @index - Pointer to the TRB index to increment. | |
151 | * | |
152 | * The index should never point to the link TRB. After incrementing, | |
153 | * if it is point to the link TRB, wrap around to the beginning. The | |
154 | * link TRB is always at the last TRB entry. | |
155 | */ | |
156 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 157 | { |
dca0119c JY |
158 | (*index)++; |
159 | if (*index == (DWC3_TRB_NUM - 1)) | |
160 | *index = 0; | |
ef966b9d | 161 | } |
457e84b6 | 162 | |
dca0119c | 163 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 164 | { |
dca0119c | 165 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 166 | } |
457e84b6 | 167 | |
dca0119c | 168 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 169 | { |
dca0119c | 170 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
171 | } |
172 | ||
72246da4 FB |
173 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
174 | int status) | |
175 | { | |
176 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 177 | int i; |
72246da4 | 178 | |
aa3342c8 | 179 | if (req->started) { |
e5ba5ec8 PA |
180 | i = 0; |
181 | do { | |
ef966b9d | 182 | dwc3_ep_inc_deq(dep); |
e5ba5ec8 | 183 | } while(++i < req->request.num_mapped_sgs); |
aa3342c8 | 184 | req->started = false; |
72246da4 FB |
185 | } |
186 | list_del(&req->list); | |
eeb720fb | 187 | req->trb = NULL; |
72246da4 FB |
188 | |
189 | if (req->request.status == -EINPROGRESS) | |
190 | req->request.status = status; | |
191 | ||
0416e494 PA |
192 | if (dwc->ep0_bounced && dep->number == 0) |
193 | dwc->ep0_bounced = false; | |
194 | else | |
195 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
196 | req->direction); | |
72246da4 | 197 | |
2c4cbe6e | 198 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
199 | |
200 | spin_unlock(&dwc->lock); | |
304f7e5e | 201 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 | 202 | spin_lock(&dwc->lock); |
fc8bb91b FB |
203 | |
204 | if (dep->number > 1) | |
205 | pm_runtime_put(dwc->dev); | |
72246da4 FB |
206 | } |
207 | ||
3ece0ec4 | 208 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
209 | { |
210 | u32 timeout = 500; | |
71f7e702 | 211 | int status = 0; |
0fe886cd | 212 | int ret = 0; |
b09bb642 FB |
213 | u32 reg; |
214 | ||
215 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
216 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
217 | ||
218 | do { | |
219 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
220 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
221 | status = DWC3_DGCMD_STATUS(reg); |
222 | if (status) | |
0fe886cd FB |
223 | ret = -EINVAL; |
224 | break; | |
b09bb642 | 225 | } |
0fe886cd FB |
226 | } while (timeout--); |
227 | ||
228 | if (!timeout) { | |
0fe886cd | 229 | ret = -ETIMEDOUT; |
71f7e702 | 230 | status = -ETIMEDOUT; |
0fe886cd FB |
231 | } |
232 | ||
71f7e702 FB |
233 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
234 | ||
0fe886cd | 235 | return ret; |
b09bb642 FB |
236 | } |
237 | ||
c36d8e94 FB |
238 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
239 | ||
2cd4718d FB |
240 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
241 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 242 | { |
2cd4718d | 243 | struct dwc3 *dwc = dep->dwc; |
61d58242 | 244 | u32 timeout = 500; |
72246da4 FB |
245 | u32 reg; |
246 | ||
0933df15 | 247 | int cmd_status = 0; |
2b0f11df | 248 | int susphy = false; |
c0ca324d | 249 | int ret = -EINVAL; |
72246da4 | 250 | |
2b0f11df FB |
251 | /* |
252 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
253 | * we're issuing an endpoint command, we must check if | |
254 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
255 | * | |
256 | * We will also set SUSPHY bit to what it was before returning as stated | |
257 | * by the same section on Synopsys databook. | |
258 | */ | |
ab2a92e7 FB |
259 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
260 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
261 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
262 | susphy = true; | |
263 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
264 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
265 | } | |
2b0f11df FB |
266 | } |
267 | ||
c36d8e94 FB |
268 | if (cmd == DWC3_DEPCMD_STARTTRANSFER) { |
269 | int needs_wakeup; | |
270 | ||
271 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
272 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
273 | dwc->link_state == DWC3_LINK_STATE_U3); | |
274 | ||
275 | if (unlikely(needs_wakeup)) { | |
276 | ret = __dwc3_gadget_wakeup(dwc); | |
277 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
278 | ret); | |
279 | } | |
280 | } | |
281 | ||
2eb88016 FB |
282 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
283 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
284 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 285 | |
2eb88016 | 286 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT); |
72246da4 | 287 | do { |
2eb88016 | 288 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 289 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 290 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 291 | |
73815280 FB |
292 | dwc3_trace(trace_dwc3_gadget, |
293 | "Command Complete --> %d", | |
7b9cc7a2 KL |
294 | cmd_status); |
295 | ||
296 | switch (cmd_status) { | |
297 | case 0: | |
298 | ret = 0; | |
299 | break; | |
300 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
ba159841 | 301 | dwc3_trace(trace_dwc3_gadget, "no resource available"); |
7b9cc7a2 | 302 | ret = -EINVAL; |
c0ca324d | 303 | break; |
7b9cc7a2 KL |
304 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
305 | /* | |
306 | * SW issues START TRANSFER command to | |
307 | * isochronous ep with future frame interval. If | |
308 | * future interval time has already passed when | |
309 | * core receives the command, it will respond | |
310 | * with an error status of 'Bus Expiry'. | |
311 | * | |
312 | * Instead of always returning -EINVAL, let's | |
313 | * give a hint to the gadget driver that this is | |
314 | * the case by returning -EAGAIN. | |
315 | */ | |
ba159841 | 316 | dwc3_trace(trace_dwc3_gadget, "bus expiry"); |
7b9cc7a2 KL |
317 | ret = -EAGAIN; |
318 | break; | |
319 | default: | |
320 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
321 | } | |
322 | ||
c0ca324d | 323 | break; |
72246da4 | 324 | } |
f6bb225b | 325 | } while (--timeout); |
72246da4 | 326 | |
f6bb225b FB |
327 | if (timeout == 0) { |
328 | dwc3_trace(trace_dwc3_gadget, | |
329 | "Command Timed Out"); | |
330 | ret = -ETIMEDOUT; | |
0933df15 | 331 | cmd_status = -ETIMEDOUT; |
f6bb225b | 332 | } |
c0ca324d | 333 | |
0933df15 FB |
334 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
335 | ||
2b0f11df FB |
336 | if (unlikely(susphy)) { |
337 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
338 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
339 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
340 | } | |
341 | ||
c0ca324d | 342 | return ret; |
72246da4 FB |
343 | } |
344 | ||
50c763f8 JY |
345 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
346 | { | |
347 | struct dwc3 *dwc = dep->dwc; | |
348 | struct dwc3_gadget_ep_cmd_params params; | |
349 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
350 | ||
351 | /* | |
352 | * As of core revision 2.60a the recommended programming model | |
353 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
354 | * command for IN endpoints. This is to prevent an issue where | |
355 | * some (non-compliant) hosts may not send ACK TPs for pending | |
356 | * IN transfers due to a mishandled error condition. Synopsys | |
357 | * STAR 9000614252. | |
358 | */ | |
359 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A)) | |
360 | cmd |= DWC3_DEPCMD_CLEARPENDIN; | |
361 | ||
362 | memset(¶ms, 0, sizeof(params)); | |
363 | ||
2cd4718d | 364 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
365 | } |
366 | ||
72246da4 | 367 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 368 | struct dwc3_trb *trb) |
72246da4 | 369 | { |
c439ef87 | 370 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
371 | |
372 | return dep->trb_pool_dma + offset; | |
373 | } | |
374 | ||
375 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
376 | { | |
377 | struct dwc3 *dwc = dep->dwc; | |
378 | ||
379 | if (dep->trb_pool) | |
380 | return 0; | |
381 | ||
72246da4 FB |
382 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
383 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
384 | &dep->trb_pool_dma, GFP_KERNEL); | |
385 | if (!dep->trb_pool) { | |
386 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
387 | dep->name); | |
388 | return -ENOMEM; | |
389 | } | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
395 | { | |
396 | struct dwc3 *dwc = dep->dwc; | |
397 | ||
398 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
399 | dep->trb_pool, dep->trb_pool_dma); | |
400 | ||
401 | dep->trb_pool = NULL; | |
402 | dep->trb_pool_dma = 0; | |
403 | } | |
404 | ||
c4509601 JY |
405 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
406 | ||
407 | /** | |
408 | * dwc3_gadget_start_config - Configure EP resources | |
409 | * @dwc: pointer to our controller context structure | |
410 | * @dep: endpoint that is being enabled | |
411 | * | |
412 | * The assignment of transfer resources cannot perfectly follow the | |
413 | * data book due to the fact that the controller driver does not have | |
414 | * all knowledge of the configuration in advance. It is given this | |
415 | * information piecemeal by the composite gadget framework after every | |
416 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
417 | * programming model in this scenario can cause errors. For two | |
418 | * reasons: | |
419 | * | |
420 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
421 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
422 | * multiple interfaces. | |
423 | * | |
424 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
425 | * endpoint on alt setting (8.1.6). | |
426 | * | |
427 | * The following simplified method is used instead: | |
428 | * | |
429 | * All hardware endpoints can be assigned a transfer resource and this | |
430 | * setting will stay persistent until either a core reset or | |
431 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
432 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
433 | * guaranteed that there are as many transfer resources as endpoints. | |
434 | * | |
435 | * This function is called for each endpoint when it is being enabled | |
436 | * but is triggered only when called for EP0-out, which always happens | |
437 | * first, and which should only happen in one of the above conditions. | |
438 | */ | |
72246da4 FB |
439 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
440 | { | |
441 | struct dwc3_gadget_ep_cmd_params params; | |
442 | u32 cmd; | |
c4509601 JY |
443 | int i; |
444 | int ret; | |
445 | ||
446 | if (dep->number) | |
447 | return 0; | |
72246da4 FB |
448 | |
449 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 450 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 451 | |
2cd4718d | 452 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
453 | if (ret) |
454 | return ret; | |
455 | ||
456 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
457 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 458 | |
c4509601 JY |
459 | if (!dep) |
460 | continue; | |
461 | ||
462 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
463 | if (ret) | |
464 | return ret; | |
72246da4 FB |
465 | } |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 471 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 472 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 473 | bool ignore, bool restore) |
72246da4 FB |
474 | { |
475 | struct dwc3_gadget_ep_cmd_params params; | |
476 | ||
477 | memset(¶ms, 0x00, sizeof(params)); | |
478 | ||
dc1c70a7 | 479 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
480 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
481 | ||
482 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 483 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 484 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 485 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 486 | } |
72246da4 | 487 | |
4b345c9a FB |
488 | if (ignore) |
489 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
490 | ||
265b70a7 PZ |
491 | if (restore) { |
492 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
493 | params.param2 |= dep->saved_state; | |
494 | } | |
495 | ||
dc1c70a7 FB |
496 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
497 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 498 | |
18b7ede5 | 499 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
500 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
501 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
502 | dep->stream_capable = true; |
503 | } | |
504 | ||
0b93a4c8 | 505 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 506 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
507 | |
508 | /* | |
509 | * We are doing 1:1 mapping for endpoints, meaning | |
510 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
511 | * so on. We consider the direction bit as part of the physical | |
512 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
513 | */ | |
dc1c70a7 | 514 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
515 | |
516 | /* | |
517 | * We must use the lower 16 TX FIFOs even though | |
518 | * HW might have more | |
519 | */ | |
520 | if (dep->direction) | |
dc1c70a7 | 521 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
522 | |
523 | if (desc->bInterval) { | |
dc1c70a7 | 524 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
525 | dep->interval = 1 << (desc->bInterval - 1); |
526 | } | |
527 | ||
2cd4718d | 528 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
529 | } |
530 | ||
531 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
532 | { | |
533 | struct dwc3_gadget_ep_cmd_params params; | |
534 | ||
535 | memset(¶ms, 0x00, sizeof(params)); | |
536 | ||
dc1c70a7 | 537 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 | 538 | |
2cd4718d FB |
539 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, |
540 | ¶ms); | |
72246da4 FB |
541 | } |
542 | ||
543 | /** | |
544 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
545 | * @dep: endpoint to be initialized | |
546 | * @desc: USB Endpoint Descriptor | |
547 | * | |
548 | * Caller should take care of locking | |
549 | */ | |
550 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 551 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 552 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 553 | bool ignore, bool restore) |
72246da4 FB |
554 | { |
555 | struct dwc3 *dwc = dep->dwc; | |
556 | u32 reg; | |
b09e99ee | 557 | int ret; |
72246da4 | 558 | |
73815280 | 559 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); |
ff62d6b6 | 560 | |
72246da4 FB |
561 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
562 | ret = dwc3_gadget_start_config(dwc, dep); | |
563 | if (ret) | |
564 | return ret; | |
565 | } | |
566 | ||
265b70a7 PZ |
567 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
568 | restore); | |
72246da4 FB |
569 | if (ret) |
570 | return ret; | |
571 | ||
572 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
573 | struct dwc3_trb *trb_st_hw; |
574 | struct dwc3_trb *trb_link; | |
72246da4 | 575 | |
16e78db7 | 576 | dep->endpoint.desc = desc; |
c90bfaec | 577 | dep->comp_desc = comp_desc; |
72246da4 FB |
578 | dep->type = usb_endpoint_type(desc); |
579 | dep->flags |= DWC3_EP_ENABLED; | |
580 | ||
581 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
582 | reg |= DWC3_DALEPENA_EP(dep->number); | |
583 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
584 | ||
36b68aae | 585 | if (usb_endpoint_xfer_control(desc)) |
7ab373aa | 586 | return 0; |
72246da4 | 587 | |
0d25744a JY |
588 | /* Initialize the TRB ring */ |
589 | dep->trb_dequeue = 0; | |
590 | dep->trb_enqueue = 0; | |
591 | memset(dep->trb_pool, 0, | |
592 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
593 | ||
36b68aae | 594 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
595 | trb_st_hw = &dep->trb_pool[0]; |
596 | ||
f6bafc6a | 597 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
598 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
599 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
600 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
601 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
602 | } |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
b992e681 | 607 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 608 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
609 | { |
610 | struct dwc3_request *req; | |
611 | ||
aa3342c8 | 612 | if (!list_empty(&dep->started_list)) { |
b992e681 | 613 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 614 | |
57911504 | 615 | /* - giveback all requests to gadget driver */ |
aa3342c8 FB |
616 | while (!list_empty(&dep->started_list)) { |
617 | req = next_request(&dep->started_list); | |
1591633e PA |
618 | |
619 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
620 | } | |
ea53b882 FB |
621 | } |
622 | ||
aa3342c8 FB |
623 | while (!list_empty(&dep->pending_list)) { |
624 | req = next_request(&dep->pending_list); | |
72246da4 | 625 | |
624407f9 | 626 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 627 | } |
72246da4 FB |
628 | } |
629 | ||
630 | /** | |
631 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
632 | * @dep: the endpoint to disable | |
633 | * | |
624407f9 SAS |
634 | * This function also removes requests which are currently processed ny the |
635 | * hardware and those which are not yet scheduled. | |
636 | * Caller should take care of locking. | |
72246da4 | 637 | */ |
72246da4 FB |
638 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
639 | { | |
640 | struct dwc3 *dwc = dep->dwc; | |
641 | u32 reg; | |
642 | ||
7eaeac5c FB |
643 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); |
644 | ||
624407f9 | 645 | dwc3_remove_requests(dwc, dep); |
72246da4 | 646 | |
687ef981 FB |
647 | /* make sure HW endpoint isn't stalled */ |
648 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 649 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 650 | |
72246da4 FB |
651 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
652 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
653 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
654 | ||
879631aa | 655 | dep->stream_capable = false; |
f9c56cdd | 656 | dep->endpoint.desc = NULL; |
c90bfaec | 657 | dep->comp_desc = NULL; |
72246da4 | 658 | dep->type = 0; |
879631aa | 659 | dep->flags = 0; |
72246da4 FB |
660 | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* -------------------------------------------------------------------------- */ | |
665 | ||
666 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
667 | const struct usb_endpoint_descriptor *desc) | |
668 | { | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
673 | { | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | /* -------------------------------------------------------------------------- */ | |
678 | ||
679 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
680 | const struct usb_endpoint_descriptor *desc) | |
681 | { | |
682 | struct dwc3_ep *dep; | |
683 | struct dwc3 *dwc; | |
684 | unsigned long flags; | |
685 | int ret; | |
686 | ||
687 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
688 | pr_debug("dwc3: invalid parameters\n"); | |
689 | return -EINVAL; | |
690 | } | |
691 | ||
692 | if (!desc->wMaxPacketSize) { | |
693 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
694 | return -EINVAL; | |
695 | } | |
696 | ||
697 | dep = to_dwc3_ep(ep); | |
698 | dwc = dep->dwc; | |
699 | ||
95ca961c FB |
700 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
701 | "%s is already enabled\n", | |
702 | dep->name)) | |
c6f83f38 | 703 | return 0; |
c6f83f38 | 704 | |
72246da4 | 705 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 706 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
707 | spin_unlock_irqrestore(&dwc->lock, flags); |
708 | ||
709 | return ret; | |
710 | } | |
711 | ||
712 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
713 | { | |
714 | struct dwc3_ep *dep; | |
715 | struct dwc3 *dwc; | |
716 | unsigned long flags; | |
717 | int ret; | |
718 | ||
719 | if (!ep) { | |
720 | pr_debug("dwc3: invalid parameters\n"); | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | dep = to_dwc3_ep(ep); | |
725 | dwc = dep->dwc; | |
726 | ||
95ca961c FB |
727 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
728 | "%s is already disabled\n", | |
729 | dep->name)) | |
72246da4 | 730 | return 0; |
72246da4 | 731 | |
72246da4 FB |
732 | spin_lock_irqsave(&dwc->lock, flags); |
733 | ret = __dwc3_gadget_ep_disable(dep); | |
734 | spin_unlock_irqrestore(&dwc->lock, flags); | |
735 | ||
736 | return ret; | |
737 | } | |
738 | ||
739 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
740 | gfp_t gfp_flags) | |
741 | { | |
742 | struct dwc3_request *req; | |
743 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
744 | |
745 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 746 | if (!req) |
72246da4 | 747 | return NULL; |
72246da4 FB |
748 | |
749 | req->epnum = dep->number; | |
750 | req->dep = dep; | |
72246da4 | 751 | |
2c4cbe6e FB |
752 | trace_dwc3_alloc_request(req); |
753 | ||
72246da4 FB |
754 | return &req->request; |
755 | } | |
756 | ||
757 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
758 | struct usb_request *request) | |
759 | { | |
760 | struct dwc3_request *req = to_dwc3_request(request); | |
761 | ||
2c4cbe6e | 762 | trace_dwc3_free_request(req); |
72246da4 FB |
763 | kfree(req); |
764 | } | |
765 | ||
c71fc37c FB |
766 | /** |
767 | * dwc3_prepare_one_trb - setup one TRB from one request | |
768 | * @dep: endpoint for which this request is prepared | |
769 | * @req: dwc3_request pointer | |
770 | */ | |
68e823e2 | 771 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 772 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 773 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 774 | { |
f6bafc6a | 775 | struct dwc3_trb *trb; |
c71fc37c | 776 | |
73815280 | 777 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s", |
eeb720fb FB |
778 | dep->name, req, (unsigned long long) dma, |
779 | length, last ? " last" : "", | |
780 | chain ? " chain" : ""); | |
781 | ||
915e202a | 782 | |
4faf7550 | 783 | trb = &dep->trb_pool[dep->trb_enqueue]; |
c71fc37c | 784 | |
eeb720fb | 785 | if (!req->trb) { |
aa3342c8 | 786 | dwc3_gadget_move_started_request(req); |
f6bafc6a FB |
787 | req->trb = trb; |
788 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
4faf7550 | 789 | req->first_trb_index = dep->trb_enqueue; |
eeb720fb | 790 | } |
c71fc37c | 791 | |
ef966b9d | 792 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 793 | |
f6bafc6a FB |
794 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
795 | trb->bpl = lower_32_bits(dma); | |
796 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 797 | |
16e78db7 | 798 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 799 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 800 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
801 | break; |
802 | ||
803 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
804 | if (!node) |
805 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
806 | else | |
807 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
ca4d44ea FB |
808 | |
809 | /* always enable Interrupt on Missed ISOC */ | |
810 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
811 | break; |
812 | ||
813 | case USB_ENDPOINT_XFER_BULK: | |
814 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 815 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
816 | break; |
817 | default: | |
818 | /* | |
819 | * This is only possible with faulty memory because we | |
820 | * checked it already :) | |
821 | */ | |
822 | BUG(); | |
823 | } | |
824 | ||
ca4d44ea FB |
825 | /* always enable Continue on Short Packet */ |
826 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 827 | |
f3af3651 | 828 | if (!req->request.no_interrupt && !chain) |
ca4d44ea | 829 | trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI; |
f3af3651 | 830 | |
ca4d44ea | 831 | if (last) |
e5ba5ec8 | 832 | trb->ctrl |= DWC3_TRB_CTRL_LST; |
c71fc37c | 833 | |
e5ba5ec8 PA |
834 | if (chain) |
835 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
836 | ||
16e78db7 | 837 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 838 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 839 | |
f6bafc6a | 840 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
841 | |
842 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
843 | } |
844 | ||
c4233573 FB |
845 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) |
846 | { | |
847 | struct dwc3_trb *tmp; | |
848 | ||
849 | /* | |
850 | * If enqueue & dequeue are equal than it is either full or empty. | |
851 | * | |
852 | * One way to know for sure is if the TRB right before us has HWO bit | |
853 | * set or not. If it has, then we're definitely full and can't fit any | |
854 | * more transfers in our ring. | |
855 | */ | |
856 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
857 | /* If we're full, enqueue/dequeue are > 0 */ | |
858 | if (dep->trb_enqueue) { | |
859 | tmp = &dep->trb_pool[dep->trb_enqueue - 1]; | |
860 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
861 | return 0; | |
862 | } | |
863 | ||
864 | return DWC3_TRB_NUM - 1; | |
865 | } | |
866 | ||
867 | return dep->trb_dequeue - dep->trb_enqueue; | |
868 | } | |
869 | ||
5ee85d89 FB |
870 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
871 | struct dwc3_request *req, unsigned int trbs_left) | |
872 | { | |
873 | struct usb_request *request = &req->request; | |
874 | struct scatterlist *sg = request->sg; | |
875 | struct scatterlist *s; | |
876 | unsigned int last = false; | |
877 | unsigned int length; | |
878 | dma_addr_t dma; | |
879 | int i; | |
880 | ||
881 | for_each_sg(sg, s, request->num_mapped_sgs, i) { | |
882 | unsigned chain = true; | |
883 | ||
884 | length = sg_dma_len(s); | |
885 | dma = sg_dma_address(s); | |
886 | ||
887 | if (sg_is_last(s)) { | |
888 | if (list_is_last(&req->list, &dep->pending_list)) | |
889 | last = true; | |
890 | ||
891 | chain = false; | |
892 | } | |
893 | ||
894 | if (!trbs_left) | |
895 | last = true; | |
896 | ||
897 | if (last) | |
898 | chain = false; | |
899 | ||
900 | dwc3_prepare_one_trb(dep, req, dma, length, | |
901 | last, chain, i); | |
902 | ||
903 | if (last) | |
904 | break; | |
905 | } | |
906 | } | |
907 | ||
908 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
909 | struct dwc3_request *req, unsigned int trbs_left) | |
910 | { | |
911 | unsigned int last = false; | |
912 | unsigned int length; | |
913 | dma_addr_t dma; | |
914 | ||
915 | dma = req->request.dma; | |
916 | length = req->request.length; | |
917 | ||
918 | if (!trbs_left) | |
919 | last = true; | |
920 | ||
921 | /* Is this the last request? */ | |
922 | if (list_is_last(&req->list, &dep->pending_list)) | |
923 | last = true; | |
924 | ||
925 | dwc3_prepare_one_trb(dep, req, dma, length, | |
926 | last, false, 0); | |
927 | } | |
928 | ||
72246da4 FB |
929 | /* |
930 | * dwc3_prepare_trbs - setup TRBs from requests | |
931 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 932 | * |
1d046793 PZ |
933 | * The function goes through the requests list and sets up TRBs for the |
934 | * transfers. The function returns once there are no more TRBs available or | |
935 | * it runs out of requests. | |
72246da4 | 936 | */ |
c4233573 | 937 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 938 | { |
68e823e2 | 939 | struct dwc3_request *req, *n; |
72246da4 FB |
940 | u32 trbs_left; |
941 | ||
942 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
943 | ||
c4233573 | 944 | trbs_left = dwc3_calc_trbs_left(dep); |
89bc856e JY |
945 | if (!trbs_left) |
946 | return; | |
72246da4 | 947 | |
aa3342c8 | 948 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
5ee85d89 FB |
949 | if (req->request.num_mapped_sgs > 0) |
950 | dwc3_prepare_one_trb_sg(dep, req, trbs_left--); | |
951 | else | |
952 | dwc3_prepare_one_trb_linear(dep, req, trbs_left--); | |
72246da4 | 953 | |
5ee85d89 FB |
954 | if (!trbs_left) |
955 | return; | |
72246da4 | 956 | } |
72246da4 FB |
957 | } |
958 | ||
4fae2e3e | 959 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) |
72246da4 FB |
960 | { |
961 | struct dwc3_gadget_ep_cmd_params params; | |
962 | struct dwc3_request *req; | |
963 | struct dwc3 *dwc = dep->dwc; | |
4fae2e3e | 964 | int starting; |
72246da4 FB |
965 | int ret; |
966 | u32 cmd; | |
967 | ||
4fae2e3e | 968 | starting = !(dep->flags & DWC3_EP_BUSY); |
72246da4 | 969 | |
4fae2e3e FB |
970 | dwc3_prepare_trbs(dep); |
971 | req = next_request(&dep->started_list); | |
72246da4 FB |
972 | if (!req) { |
973 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
974 | return 0; | |
975 | } | |
976 | ||
977 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 978 | |
4fae2e3e | 979 | if (starting) { |
1877d6c9 PA |
980 | params.param0 = upper_32_bits(req->trb_dma); |
981 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 982 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 983 | } else { |
72246da4 | 984 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 985 | } |
72246da4 FB |
986 | |
987 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
2cd4718d | 988 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 989 | if (ret < 0) { |
72246da4 FB |
990 | /* |
991 | * FIXME we need to iterate over the list of requests | |
992 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 993 | * requests instead of what we do now. |
72246da4 | 994 | */ |
0fc9a1be FB |
995 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
996 | req->direction); | |
72246da4 FB |
997 | list_del(&req->list); |
998 | return ret; | |
999 | } | |
1000 | ||
1001 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1002 | |
4fae2e3e | 1003 | if (starting) { |
2eb88016 | 1004 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
b4996a86 | 1005 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1006 | } |
25b8ff68 | 1007 | |
72246da4 FB |
1008 | return 0; |
1009 | } | |
1010 | ||
d6d6ec7b PA |
1011 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1012 | struct dwc3_ep *dep, u32 cur_uf) | |
1013 | { | |
1014 | u32 uf; | |
1015 | ||
aa3342c8 | 1016 | if (list_empty(&dep->pending_list)) { |
73815280 FB |
1017 | dwc3_trace(trace_dwc3_gadget, |
1018 | "ISOC ep %s run out for requests", | |
1019 | dep->name); | |
f4a53c55 | 1020 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1021 | return; |
1022 | } | |
1023 | ||
1024 | /* 4 micro frames in the future */ | |
1025 | uf = cur_uf + dep->interval * 4; | |
1026 | ||
4fae2e3e | 1027 | __dwc3_gadget_kick_transfer(dep, uf); |
d6d6ec7b PA |
1028 | } |
1029 | ||
1030 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1031 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1032 | { | |
1033 | u32 cur_uf, mask; | |
1034 | ||
1035 | mask = ~(dep->interval - 1); | |
1036 | cur_uf = event->parameters & mask; | |
1037 | ||
1038 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1039 | } | |
1040 | ||
72246da4 FB |
1041 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1042 | { | |
0fc9a1be FB |
1043 | struct dwc3 *dwc = dep->dwc; |
1044 | int ret; | |
1045 | ||
bb423984 | 1046 | if (!dep->endpoint.desc) { |
ec5e795c FB |
1047 | dwc3_trace(trace_dwc3_gadget, |
1048 | "trying to queue request %p to disabled %s\n", | |
bb423984 FB |
1049 | &req->request, dep->endpoint.name); |
1050 | return -ESHUTDOWN; | |
1051 | } | |
1052 | ||
1053 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1054 | &req->request, req->dep->name)) { | |
ec5e795c FB |
1055 | dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n", |
1056 | &req->request, req->dep->name); | |
bb423984 FB |
1057 | return -EINVAL; |
1058 | } | |
1059 | ||
fc8bb91b FB |
1060 | pm_runtime_get(dwc->dev); |
1061 | ||
72246da4 FB |
1062 | req->request.actual = 0; |
1063 | req->request.status = -EINPROGRESS; | |
1064 | req->direction = dep->direction; | |
1065 | req->epnum = dep->number; | |
1066 | ||
fe84f522 FB |
1067 | trace_dwc3_ep_queue(req); |
1068 | ||
72246da4 FB |
1069 | /* |
1070 | * We only add to our list of requests now and | |
1071 | * start consuming the list once we get XferNotReady | |
1072 | * IRQ. | |
1073 | * | |
1074 | * That way, we avoid doing anything that we don't need | |
1075 | * to do now and defer it until the point we receive a | |
1076 | * particular token from the Host side. | |
1077 | * | |
1078 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1079 | * many NAKs. |
72246da4 | 1080 | */ |
0fc9a1be FB |
1081 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1082 | dep->direction); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
aa3342c8 | 1086 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1087 | |
1d6a3918 FB |
1088 | /* |
1089 | * If there are no pending requests and the endpoint isn't already | |
1090 | * busy, we will just start the request straight away. | |
1091 | * | |
1092 | * This will save one IRQ (XFER_NOT_READY) and possibly make it a | |
1093 | * little bit faster. | |
1094 | */ | |
1095 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
62e345ae | 1096 | !usb_endpoint_xfer_int(dep->endpoint.desc) && |
1d6a3918 | 1097 | !(dep->flags & DWC3_EP_BUSY)) { |
4fae2e3e | 1098 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
a8f32817 | 1099 | goto out; |
1d6a3918 FB |
1100 | } |
1101 | ||
72246da4 | 1102 | /* |
b511e5e7 | 1103 | * There are a few special cases: |
72246da4 | 1104 | * |
f898ae09 PZ |
1105 | * 1. XferNotReady with empty list of requests. We need to kick the |
1106 | * transfer here in that situation, otherwise we will be NAKing | |
1107 | * forever. If we get XferNotReady before gadget driver has a | |
1108 | * chance to queue a request, we will ACK the IRQ but won't be | |
1109 | * able to receive the data until the next request is queued. | |
1110 | * The following code is handling exactly that. | |
72246da4 | 1111 | * |
72246da4 FB |
1112 | */ |
1113 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1114 | /* |
1115 | * If xfernotready is already elapsed and it is a case | |
1116 | * of isoc transfer, then issue END TRANSFER, so that | |
1117 | * you can receive xfernotready again and can have | |
1118 | * notion of current microframe. | |
1119 | */ | |
1120 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
aa3342c8 | 1121 | if (list_empty(&dep->started_list)) { |
b992e681 | 1122 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1123 | dep->flags = DWC3_EP_ENABLED; |
1124 | } | |
f4a53c55 PA |
1125 | return 0; |
1126 | } | |
1127 | ||
4fae2e3e | 1128 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
89185916 FB |
1129 | if (!ret) |
1130 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1131 | ||
a8f32817 | 1132 | goto out; |
b511e5e7 | 1133 | } |
72246da4 | 1134 | |
b511e5e7 FB |
1135 | /* |
1136 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1137 | * kick the transfer here after queuing a request, otherwise the | |
1138 | * core may not see the modified TRB(s). | |
1139 | */ | |
1140 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1141 | (dep->flags & DWC3_EP_BUSY) && |
1142 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 | 1143 | WARN_ON_ONCE(!dep->resource_index); |
4fae2e3e | 1144 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index); |
a8f32817 | 1145 | goto out; |
a0925324 | 1146 | } |
72246da4 | 1147 | |
b997ada5 FB |
1148 | /* |
1149 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1150 | * right away, otherwise host will not know we have streams to be | |
1151 | * handled. | |
1152 | */ | |
a8f32817 | 1153 | if (dep->stream_capable) |
4fae2e3e | 1154 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
b997ada5 | 1155 | |
a8f32817 FB |
1156 | out: |
1157 | if (ret && ret != -EBUSY) | |
ec5e795c FB |
1158 | dwc3_trace(trace_dwc3_gadget, |
1159 | "%s: failed to kick transfers\n", | |
a8f32817 FB |
1160 | dep->name); |
1161 | if (ret == -EBUSY) | |
1162 | ret = 0; | |
1163 | ||
1164 | return ret; | |
72246da4 FB |
1165 | } |
1166 | ||
04c03d10 FB |
1167 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, |
1168 | struct usb_request *request) | |
1169 | { | |
1170 | dwc3_gadget_ep_free_request(ep, request); | |
1171 | } | |
1172 | ||
1173 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1174 | { | |
1175 | struct dwc3_request *req; | |
1176 | struct usb_request *request; | |
1177 | struct usb_ep *ep = &dep->endpoint; | |
1178 | ||
1179 | dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n"); | |
1180 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); | |
1181 | if (!request) | |
1182 | return -ENOMEM; | |
1183 | ||
1184 | request->length = 0; | |
1185 | request->buf = dwc->zlp_buf; | |
1186 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1187 | ||
1188 | req = to_dwc3_request(request); | |
1189 | ||
1190 | return __dwc3_gadget_ep_queue(dep, req); | |
1191 | } | |
1192 | ||
72246da4 FB |
1193 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, |
1194 | gfp_t gfp_flags) | |
1195 | { | |
1196 | struct dwc3_request *req = to_dwc3_request(request); | |
1197 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1198 | struct dwc3 *dwc = dep->dwc; | |
1199 | ||
1200 | unsigned long flags; | |
1201 | ||
1202 | int ret; | |
1203 | ||
fdee4eba | 1204 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1205 | ret = __dwc3_gadget_ep_queue(dep, req); |
04c03d10 FB |
1206 | |
1207 | /* | |
1208 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1209 | * setting request->zero, instead of doing magic, we will just queue an | |
1210 | * extra usb_request ourselves so that it gets handled the same way as | |
1211 | * any other request. | |
1212 | */ | |
d9261898 JY |
1213 | if (ret == 0 && request->zero && request->length && |
1214 | (request->length % ep->maxpacket == 0)) | |
04c03d10 FB |
1215 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); |
1216 | ||
72246da4 FB |
1217 | spin_unlock_irqrestore(&dwc->lock, flags); |
1218 | ||
1219 | return ret; | |
1220 | } | |
1221 | ||
1222 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1223 | struct usb_request *request) | |
1224 | { | |
1225 | struct dwc3_request *req = to_dwc3_request(request); | |
1226 | struct dwc3_request *r = NULL; | |
1227 | ||
1228 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1229 | struct dwc3 *dwc = dep->dwc; | |
1230 | ||
1231 | unsigned long flags; | |
1232 | int ret = 0; | |
1233 | ||
2c4cbe6e FB |
1234 | trace_dwc3_ep_dequeue(req); |
1235 | ||
72246da4 FB |
1236 | spin_lock_irqsave(&dwc->lock, flags); |
1237 | ||
aa3342c8 | 1238 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1239 | if (r == req) |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | if (r != req) { | |
aa3342c8 | 1244 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1245 | if (r == req) |
1246 | break; | |
1247 | } | |
1248 | if (r == req) { | |
1249 | /* wait until it is processed */ | |
b992e681 | 1250 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1251 | goto out1; |
72246da4 FB |
1252 | } |
1253 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1254 | request, ep->name); | |
1255 | ret = -EINVAL; | |
1256 | goto out0; | |
1257 | } | |
1258 | ||
e8d4e8be | 1259 | out1: |
72246da4 FB |
1260 | /* giveback the request */ |
1261 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1262 | ||
1263 | out0: | |
1264 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1265 | ||
1266 | return ret; | |
1267 | } | |
1268 | ||
7a608559 | 1269 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1270 | { |
1271 | struct dwc3_gadget_ep_cmd_params params; | |
1272 | struct dwc3 *dwc = dep->dwc; | |
1273 | int ret; | |
1274 | ||
5ad02fb8 FB |
1275 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1276 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1277 | return -EINVAL; | |
1278 | } | |
1279 | ||
72246da4 FB |
1280 | memset(¶ms, 0x00, sizeof(params)); |
1281 | ||
1282 | if (value) { | |
7a608559 | 1283 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
aa3342c8 FB |
1284 | (!list_empty(&dep->started_list) || |
1285 | !list_empty(&dep->pending_list)))) { | |
ec5e795c | 1286 | dwc3_trace(trace_dwc3_gadget, |
052ba52e | 1287 | "%s: pending request, cannot halt", |
7a608559 FB |
1288 | dep->name); |
1289 | return -EAGAIN; | |
1290 | } | |
1291 | ||
2cd4718d FB |
1292 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1293 | ¶ms); | |
72246da4 | 1294 | if (ret) |
3f89204b | 1295 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1296 | dep->name); |
1297 | else | |
1298 | dep->flags |= DWC3_EP_STALL; | |
1299 | } else { | |
2cd4718d | 1300 | |
50c763f8 | 1301 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1302 | if (ret) |
3f89204b | 1303 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1304 | dep->name); |
1305 | else | |
a535d81c | 1306 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1307 | } |
5275455a | 1308 | |
72246da4 FB |
1309 | return ret; |
1310 | } | |
1311 | ||
1312 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1313 | { | |
1314 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1315 | struct dwc3 *dwc = dep->dwc; | |
1316 | ||
1317 | unsigned long flags; | |
1318 | ||
1319 | int ret; | |
1320 | ||
1321 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1322 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1323 | spin_unlock_irqrestore(&dwc->lock, flags); |
1324 | ||
1325 | return ret; | |
1326 | } | |
1327 | ||
1328 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1329 | { | |
1330 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1331 | struct dwc3 *dwc = dep->dwc; |
1332 | unsigned long flags; | |
95aa4e8d | 1333 | int ret; |
72246da4 | 1334 | |
249a4569 | 1335 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1336 | dep->flags |= DWC3_EP_WEDGE; |
1337 | ||
08f0d966 | 1338 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1339 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1340 | else |
7a608559 | 1341 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1342 | spin_unlock_irqrestore(&dwc->lock, flags); |
1343 | ||
1344 | return ret; | |
72246da4 FB |
1345 | } |
1346 | ||
1347 | /* -------------------------------------------------------------------------- */ | |
1348 | ||
1349 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1350 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1351 | .bDescriptorType = USB_DT_ENDPOINT, | |
1352 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1353 | }; | |
1354 | ||
1355 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1356 | .enable = dwc3_gadget_ep0_enable, | |
1357 | .disable = dwc3_gadget_ep0_disable, | |
1358 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1359 | .free_request = dwc3_gadget_ep_free_request, | |
1360 | .queue = dwc3_gadget_ep0_queue, | |
1361 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1362 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1363 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1364 | }; | |
1365 | ||
1366 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1367 | .enable = dwc3_gadget_ep_enable, | |
1368 | .disable = dwc3_gadget_ep_disable, | |
1369 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1370 | .free_request = dwc3_gadget_ep_free_request, | |
1371 | .queue = dwc3_gadget_ep_queue, | |
1372 | .dequeue = dwc3_gadget_ep_dequeue, | |
1373 | .set_halt = dwc3_gadget_ep_set_halt, | |
1374 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1375 | }; | |
1376 | ||
1377 | /* -------------------------------------------------------------------------- */ | |
1378 | ||
1379 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1380 | { | |
1381 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1382 | u32 reg; | |
1383 | ||
1384 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1385 | return DWC3_DSTS_SOFFN(reg); | |
1386 | } | |
1387 | ||
218ef7b6 | 1388 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1389 | { |
72246da4 | 1390 | unsigned long timeout; |
72246da4 | 1391 | |
218ef7b6 | 1392 | int ret; |
72246da4 FB |
1393 | u32 reg; |
1394 | ||
72246da4 FB |
1395 | u8 link_state; |
1396 | u8 speed; | |
1397 | ||
72246da4 FB |
1398 | /* |
1399 | * According to the Databook Remote wakeup request should | |
1400 | * be issued only when the device is in early suspend state. | |
1401 | * | |
1402 | * We can check that via USB Link State bits in DSTS register. | |
1403 | */ | |
1404 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1405 | ||
1406 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c JY |
1407 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
1408 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
ec5e795c | 1409 | dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n"); |
6b742899 | 1410 | return 0; |
72246da4 FB |
1411 | } |
1412 | ||
1413 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1414 | ||
1415 | switch (link_state) { | |
1416 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1417 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1418 | break; | |
1419 | default: | |
ec5e795c FB |
1420 | dwc3_trace(trace_dwc3_gadget, |
1421 | "can't wakeup from '%s'\n", | |
1422 | dwc3_gadget_link_string(link_state)); | |
218ef7b6 | 1423 | return -EINVAL; |
72246da4 FB |
1424 | } |
1425 | ||
8598bde7 FB |
1426 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1427 | if (ret < 0) { | |
1428 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1429 | return ret; |
8598bde7 | 1430 | } |
72246da4 | 1431 | |
802fde98 PZ |
1432 | /* Recent versions do this automatically */ |
1433 | if (dwc->revision < DWC3_REVISION_194A) { | |
1434 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1435 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1436 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1437 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1438 | } | |
72246da4 | 1439 | |
1d046793 | 1440 | /* poll until Link State changes to ON */ |
72246da4 FB |
1441 | timeout = jiffies + msecs_to_jiffies(100); |
1442 | ||
1d046793 | 1443 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1444 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1445 | ||
1446 | /* in HS, means ON */ | |
1447 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1448 | break; | |
1449 | } | |
1450 | ||
1451 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1452 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1453 | return -EINVAL; |
72246da4 FB |
1454 | } |
1455 | ||
218ef7b6 FB |
1456 | return 0; |
1457 | } | |
1458 | ||
1459 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1460 | { | |
1461 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1462 | unsigned long flags; | |
1463 | int ret; | |
1464 | ||
1465 | spin_lock_irqsave(&dwc->lock, flags); | |
1466 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1467 | spin_unlock_irqrestore(&dwc->lock, flags); |
1468 | ||
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1473 | int is_selfpowered) | |
1474 | { | |
1475 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1476 | unsigned long flags; |
72246da4 | 1477 | |
249a4569 | 1478 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1479 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1480 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1481 | |
1482 | return 0; | |
1483 | } | |
1484 | ||
7b2a0368 | 1485 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1486 | { |
1487 | u32 reg; | |
61d58242 | 1488 | u32 timeout = 500; |
72246da4 | 1489 | |
fc8bb91b FB |
1490 | if (pm_runtime_suspended(dwc->dev)) |
1491 | return 0; | |
1492 | ||
72246da4 | 1493 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1494 | if (is_on) { |
802fde98 PZ |
1495 | if (dwc->revision <= DWC3_REVISION_187A) { |
1496 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1497 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1498 | } | |
1499 | ||
1500 | if (dwc->revision >= DWC3_REVISION_194A) | |
1501 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1502 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1503 | |
1504 | if (dwc->has_hibernation) | |
1505 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1506 | ||
9fcb3bd8 | 1507 | dwc->pullups_connected = true; |
8db7ed15 | 1508 | } else { |
72246da4 | 1509 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1510 | |
1511 | if (dwc->has_hibernation && !suspend) | |
1512 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1513 | ||
9fcb3bd8 | 1514 | dwc->pullups_connected = false; |
8db7ed15 | 1515 | } |
72246da4 FB |
1516 | |
1517 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1518 | ||
1519 | do { | |
1520 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1521 | if (is_on) { | |
1522 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1523 | break; | |
1524 | } else { | |
1525 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1526 | break; | |
1527 | } | |
72246da4 FB |
1528 | timeout--; |
1529 | if (!timeout) | |
6f17f74b | 1530 | return -ETIMEDOUT; |
61d58242 | 1531 | udelay(1); |
72246da4 FB |
1532 | } while (1); |
1533 | ||
73815280 | 1534 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", |
72246da4 FB |
1535 | dwc->gadget_driver |
1536 | ? dwc->gadget_driver->function : "no-function", | |
1537 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1538 | |
1539 | return 0; | |
72246da4 FB |
1540 | } |
1541 | ||
1542 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1543 | { | |
1544 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1545 | unsigned long flags; | |
6f17f74b | 1546 | int ret; |
72246da4 FB |
1547 | |
1548 | is_on = !!is_on; | |
1549 | ||
1550 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1551 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1552 | spin_unlock_irqrestore(&dwc->lock, flags); |
1553 | ||
6f17f74b | 1554 | return ret; |
72246da4 FB |
1555 | } |
1556 | ||
8698e2ac FB |
1557 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1558 | { | |
1559 | u32 reg; | |
1560 | ||
1561 | /* Enable all but Start and End of Frame IRQs */ | |
1562 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1563 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1564 | DWC3_DEVTEN_CMDCMPLTEN | | |
1565 | DWC3_DEVTEN_ERRTICERREN | | |
1566 | DWC3_DEVTEN_WKUPEVTEN | | |
1567 | DWC3_DEVTEN_ULSTCNGEN | | |
1568 | DWC3_DEVTEN_CONNECTDONEEN | | |
1569 | DWC3_DEVTEN_USBRSTEN | | |
1570 | DWC3_DEVTEN_DISCONNEVTEN); | |
1571 | ||
1572 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1573 | } | |
1574 | ||
1575 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1576 | { | |
1577 | /* mask all interrupts */ | |
1578 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1579 | } | |
1580 | ||
1581 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1582 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1583 | |
4e99472b FB |
1584 | /** |
1585 | * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG | |
1586 | * dwc: pointer to our context structure | |
1587 | * | |
1588 | * The following looks like complex but it's actually very simple. In order to | |
1589 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1590 | * gonna use RxFIFO size. | |
1591 | * | |
1592 | * To calculate RxFIFO size we need two numbers: | |
1593 | * MDWIDTH = size, in bits, of the internal memory bus | |
1594 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1595 | * | |
1596 | * Given these two numbers, the formula is simple: | |
1597 | * | |
1598 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1599 | * | |
1600 | * 24 bytes is for 3x SETUP packets | |
1601 | * 16 bytes is a clock domain crossing tolerance | |
1602 | * | |
1603 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1604 | */ | |
1605 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1606 | { | |
1607 | u32 ram2_depth; | |
1608 | u32 mdwidth; | |
1609 | u32 nump; | |
1610 | u32 reg; | |
1611 | ||
1612 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1613 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1614 | ||
1615 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1616 | nump = min_t(u32, nump, 16); | |
1617 | ||
1618 | /* update NumP */ | |
1619 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1620 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1621 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1622 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1623 | } | |
1624 | ||
d7be2952 | 1625 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1626 | { |
72246da4 | 1627 | struct dwc3_ep *dep; |
72246da4 FB |
1628 | int ret = 0; |
1629 | u32 reg; | |
1630 | ||
72246da4 FB |
1631 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1632 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1633 | |
1634 | /** | |
1635 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1636 | * which would cause metastability state on Run/Stop | |
1637 | * bit if we try to force the IP to USB2-only mode. | |
1638 | * | |
1639 | * Because of that, we cannot configure the IP to any | |
1640 | * speed other than the SuperSpeed | |
1641 | * | |
1642 | * Refers to: | |
1643 | * | |
1644 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1645 | * USB 2.0 Mode | |
1646 | */ | |
f7e846f0 | 1647 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1648 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1649 | } else { |
1650 | switch (dwc->maximum_speed) { | |
1651 | case USB_SPEED_LOW: | |
1652 | reg |= DWC3_DSTS_LOWSPEED; | |
1653 | break; | |
1654 | case USB_SPEED_FULL: | |
1655 | reg |= DWC3_DSTS_FULLSPEED1; | |
1656 | break; | |
1657 | case USB_SPEED_HIGH: | |
1658 | reg |= DWC3_DSTS_HIGHSPEED; | |
1659 | break; | |
7580862b JY |
1660 | case USB_SPEED_SUPER_PLUS: |
1661 | reg |= DWC3_DSTS_SUPERSPEED_PLUS; | |
1662 | break; | |
f7e846f0 | 1663 | default: |
77966eb8 JY |
1664 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1665 | dwc->maximum_speed); | |
1666 | /* fall through */ | |
1667 | case USB_SPEED_SUPER: | |
1668 | reg |= DWC3_DCFG_SUPERSPEED; | |
1669 | break; | |
f7e846f0 FB |
1670 | } |
1671 | } | |
72246da4 FB |
1672 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1673 | ||
2a58f9c1 FB |
1674 | /* |
1675 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1676 | * field instead of letting dwc3 itself calculate that automatically. | |
1677 | * | |
1678 | * This way, we maximize the chances that we'll be able to get several | |
1679 | * bursts of data without going through any sort of endpoint throttling. | |
1680 | */ | |
1681 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1682 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1683 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1684 | ||
4e99472b FB |
1685 | dwc3_gadget_setup_nump(dwc); |
1686 | ||
72246da4 FB |
1687 | /* Start with SuperSpeed Default */ |
1688 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1689 | ||
1690 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1691 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1692 | false); | |
72246da4 FB |
1693 | if (ret) { |
1694 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1695 | goto err0; |
72246da4 FB |
1696 | } |
1697 | ||
1698 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1699 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1700 | false); | |
72246da4 FB |
1701 | if (ret) { |
1702 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1703 | goto err1; |
72246da4 FB |
1704 | } |
1705 | ||
1706 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1707 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1708 | dwc3_ep0_out_start(dwc); |
1709 | ||
8698e2ac FB |
1710 | dwc3_gadget_enable_irq(dwc); |
1711 | ||
72246da4 FB |
1712 | return 0; |
1713 | ||
b0d7ffd4 | 1714 | err1: |
d7be2952 | 1715 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1716 | |
1717 | err0: | |
72246da4 FB |
1718 | return ret; |
1719 | } | |
1720 | ||
d7be2952 FB |
1721 | static int dwc3_gadget_start(struct usb_gadget *g, |
1722 | struct usb_gadget_driver *driver) | |
72246da4 FB |
1723 | { |
1724 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1725 | unsigned long flags; | |
d7be2952 | 1726 | int ret = 0; |
8698e2ac | 1727 | int irq; |
72246da4 | 1728 | |
d7be2952 FB |
1729 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1730 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
1731 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1732 | if (ret) { | |
1733 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1734 | irq, ret); | |
1735 | goto err0; | |
1736 | } | |
3f308d17 | 1737 | dwc->irq_gadget = irq; |
d7be2952 | 1738 | |
72246da4 | 1739 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
1740 | if (dwc->gadget_driver) { |
1741 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1742 | dwc->gadget.name, | |
1743 | dwc->gadget_driver->driver.name); | |
1744 | ret = -EBUSY; | |
1745 | goto err1; | |
1746 | } | |
1747 | ||
1748 | dwc->gadget_driver = driver; | |
1749 | ||
fc8bb91b FB |
1750 | if (pm_runtime_active(dwc->dev)) |
1751 | __dwc3_gadget_start(dwc); | |
1752 | ||
d7be2952 FB |
1753 | spin_unlock_irqrestore(&dwc->lock, flags); |
1754 | ||
1755 | return 0; | |
1756 | ||
1757 | err1: | |
1758 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1759 | free_irq(irq, dwc); | |
1760 | ||
1761 | err0: | |
1762 | return ret; | |
1763 | } | |
72246da4 | 1764 | |
d7be2952 FB |
1765 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
1766 | { | |
8698e2ac | 1767 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1768 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1769 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 1770 | } |
72246da4 | 1771 | |
d7be2952 FB |
1772 | static int dwc3_gadget_stop(struct usb_gadget *g) |
1773 | { | |
1774 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1775 | unsigned long flags; | |
72246da4 | 1776 | |
d7be2952 FB |
1777 | spin_lock_irqsave(&dwc->lock, flags); |
1778 | __dwc3_gadget_stop(dwc); | |
1779 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1780 | spin_unlock_irqrestore(&dwc->lock, flags); |
1781 | ||
3f308d17 | 1782 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 1783 | |
72246da4 FB |
1784 | return 0; |
1785 | } | |
802fde98 | 1786 | |
72246da4 FB |
1787 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1788 | .get_frame = dwc3_gadget_get_frame, | |
1789 | .wakeup = dwc3_gadget_wakeup, | |
1790 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1791 | .pullup = dwc3_gadget_pullup, | |
1792 | .udc_start = dwc3_gadget_start, | |
1793 | .udc_stop = dwc3_gadget_stop, | |
1794 | }; | |
1795 | ||
1796 | /* -------------------------------------------------------------------------- */ | |
1797 | ||
6a1e3ef4 FB |
1798 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1799 | u8 num, u32 direction) | |
72246da4 FB |
1800 | { |
1801 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1802 | u8 i; |
72246da4 | 1803 | |
6a1e3ef4 | 1804 | for (i = 0; i < num; i++) { |
d07fa665 | 1805 | u8 epnum = (i << 1) | (direction ? 1 : 0); |
72246da4 | 1806 | |
72246da4 | 1807 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1808 | if (!dep) |
72246da4 | 1809 | return -ENOMEM; |
72246da4 FB |
1810 | |
1811 | dep->dwc = dwc; | |
1812 | dep->number = epnum; | |
9aa62ae4 | 1813 | dep->direction = !!direction; |
2eb88016 | 1814 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); |
72246da4 FB |
1815 | dwc->eps[epnum] = dep; |
1816 | ||
1817 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1818 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1819 | |
72246da4 | 1820 | dep->endpoint.name = dep->name; |
74674cbf | 1821 | spin_lock_init(&dep->lock); |
72246da4 | 1822 | |
73815280 | 1823 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); |
653df35e | 1824 | |
72246da4 | 1825 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1826 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1827 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1828 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1829 | if (!epnum) | |
1830 | dwc->gadget.ep0 = &dep->endpoint; | |
1831 | } else { | |
1832 | int ret; | |
1833 | ||
e117e742 | 1834 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1835 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1836 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1837 | list_add_tail(&dep->endpoint.ep_list, | |
1838 | &dwc->gadget.ep_list); | |
1839 | ||
1840 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1841 | if (ret) |
72246da4 | 1842 | return ret; |
72246da4 | 1843 | } |
25b8ff68 | 1844 | |
a474d3b7 RB |
1845 | if (epnum == 0 || epnum == 1) { |
1846 | dep->endpoint.caps.type_control = true; | |
1847 | } else { | |
1848 | dep->endpoint.caps.type_iso = true; | |
1849 | dep->endpoint.caps.type_bulk = true; | |
1850 | dep->endpoint.caps.type_int = true; | |
1851 | } | |
1852 | ||
1853 | dep->endpoint.caps.dir_in = !!direction; | |
1854 | dep->endpoint.caps.dir_out = !direction; | |
1855 | ||
aa3342c8 FB |
1856 | INIT_LIST_HEAD(&dep->pending_list); |
1857 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
1858 | } |
1859 | ||
1860 | return 0; | |
1861 | } | |
1862 | ||
6a1e3ef4 FB |
1863 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1864 | { | |
1865 | int ret; | |
1866 | ||
1867 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1868 | ||
1869 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1870 | if (ret < 0) { | |
73815280 FB |
1871 | dwc3_trace(trace_dwc3_gadget, |
1872 | "failed to allocate OUT endpoints"); | |
6a1e3ef4 FB |
1873 | return ret; |
1874 | } | |
1875 | ||
1876 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1877 | if (ret < 0) { | |
73815280 FB |
1878 | dwc3_trace(trace_dwc3_gadget, |
1879 | "failed to allocate IN endpoints"); | |
6a1e3ef4 FB |
1880 | return ret; |
1881 | } | |
1882 | ||
1883 | return 0; | |
1884 | } | |
1885 | ||
72246da4 FB |
1886 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1887 | { | |
1888 | struct dwc3_ep *dep; | |
1889 | u8 epnum; | |
1890 | ||
1891 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1892 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1893 | if (!dep) |
1894 | continue; | |
5bf8fae3 GC |
1895 | /* |
1896 | * Physical endpoints 0 and 1 are special; they form the | |
1897 | * bi-directional USB endpoint 0. | |
1898 | * | |
1899 | * For those two physical endpoints, we don't allocate a TRB | |
1900 | * pool nor do we add them the endpoints list. Due to that, we | |
1901 | * shouldn't do these two operations otherwise we would end up | |
1902 | * with all sorts of bugs when removing dwc3.ko. | |
1903 | */ | |
1904 | if (epnum != 0 && epnum != 1) { | |
1905 | dwc3_free_trb_pool(dep); | |
72246da4 | 1906 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1907 | } |
72246da4 FB |
1908 | |
1909 | kfree(dep); | |
1910 | } | |
1911 | } | |
1912 | ||
72246da4 | 1913 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1914 | |
e5ba5ec8 PA |
1915 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1916 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1917 | const struct dwc3_event_depevt *event, int status) |
1918 | { | |
72246da4 FB |
1919 | unsigned int count; |
1920 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1921 | unsigned int trb_status; |
72246da4 | 1922 | |
2c4cbe6e FB |
1923 | trace_dwc3_complete_trb(dep, trb); |
1924 | ||
e5ba5ec8 PA |
1925 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1926 | /* | |
1927 | * We continue despite the error. There is not much we | |
1928 | * can do. If we don't clean it up we loop forever. If | |
1929 | * we skip the TRB then it gets overwritten after a | |
1930 | * while since we use them in a ring buffer. A BUG() | |
1931 | * would help. Lets hope that if this occurs, someone | |
1932 | * fixes the root cause instead of looking away :) | |
1933 | */ | |
1934 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1935 | dep->name, trb); | |
1936 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1937 | ||
1938 | if (dep->direction) { | |
1939 | if (count) { | |
1940 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1941 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
ec5e795c FB |
1942 | dwc3_trace(trace_dwc3_gadget, |
1943 | "%s: incomplete IN transfer\n", | |
e5ba5ec8 PA |
1944 | dep->name); |
1945 | /* | |
1946 | * If missed isoc occurred and there is | |
1947 | * no request queued then issue END | |
1948 | * TRANSFER, so that core generates | |
1949 | * next xfernotready and we will issue | |
1950 | * a fresh START TRANSFER. | |
1951 | * If there are still queued request | |
1952 | * then wait, do not issue either END | |
1953 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 1954 | * request in pending_list during |
e5ba5ec8 PA |
1955 | * giveback.If any future queued request |
1956 | * is successfully transferred then we | |
1957 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 1958 | * request in the pending_list. |
e5ba5ec8 PA |
1959 | */ |
1960 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1961 | } else { | |
1962 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1963 | dep->name); | |
1964 | status = -ECONNRESET; | |
1965 | } | |
1966 | } else { | |
1967 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1968 | } | |
1969 | } else { | |
1970 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1971 | s_pkt = 1; | |
1972 | } | |
1973 | ||
1974 | /* | |
1975 | * We assume here we will always receive the entire data block | |
1976 | * which we should receive. Meaning, if we program RX to | |
1977 | * receive 4K but we receive only 2K, we assume that's all we | |
1978 | * should receive and we simply bounce the request back to the | |
1979 | * gadget driver for further processing. | |
1980 | */ | |
1981 | req->request.actual += req->request.length - count; | |
1982 | if (s_pkt) | |
1983 | return 1; | |
1984 | if ((event->status & DEPEVT_STATUS_LST) && | |
1985 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1986 | DWC3_TRB_CTRL_HWO))) | |
1987 | return 1; | |
1988 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1989 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1990 | return 1; | |
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1995 | const struct dwc3_event_depevt *event, int status) | |
1996 | { | |
1997 | struct dwc3_request *req; | |
1998 | struct dwc3_trb *trb; | |
1999 | unsigned int slot; | |
2000 | unsigned int i; | |
2001 | int ret; | |
2002 | ||
72246da4 | 2003 | do { |
aa3342c8 | 2004 | req = next_request(&dep->started_list); |
ac7bdcc1 | 2005 | if (WARN_ON_ONCE(!req)) |
d115d705 | 2006 | return 1; |
ac7bdcc1 | 2007 | |
d115d705 VS |
2008 | i = 0; |
2009 | do { | |
53fd8818 | 2010 | slot = req->first_trb_index + i; |
36b68aae | 2011 | if (slot == DWC3_TRB_NUM - 1) |
d115d705 VS |
2012 | slot++; |
2013 | slot %= DWC3_TRB_NUM; | |
2014 | trb = &dep->trb_pool[slot]; | |
2015 | ||
2016 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
2017 | event, status); | |
2018 | if (ret) | |
2019 | break; | |
2020 | } while (++i < req->request.num_mapped_sgs); | |
2021 | ||
2022 | dwc3_gadget_giveback(dep, req, status); | |
e5ba5ec8 PA |
2023 | |
2024 | if (ret) | |
72246da4 | 2025 | break; |
d115d705 | 2026 | } while (1); |
72246da4 | 2027 | |
4cb42217 FB |
2028 | /* |
2029 | * Our endpoint might get disabled by another thread during | |
2030 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2031 | * early on so DWC3_EP_BUSY flag gets cleared | |
2032 | */ | |
2033 | if (!dep->endpoint.desc) | |
2034 | return 1; | |
2035 | ||
cdc359dd | 2036 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
2037 | list_empty(&dep->started_list)) { |
2038 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
2039 | /* |
2040 | * If there is no entry in request list then do | |
2041 | * not issue END TRANSFER now. Just set PENDING | |
2042 | * flag, so that END TRANSFER is issued when an | |
2043 | * entry is added into request list. | |
2044 | */ | |
2045 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2046 | } else { | |
b992e681 | 2047 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
2048 | dep->flags = DWC3_EP_ENABLED; |
2049 | } | |
7efea86c PA |
2050 | return 1; |
2051 | } | |
2052 | ||
9cad39fe KL |
2053 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
2054 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2055 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2056 | return 0; | |
72246da4 FB |
2057 | return 1; |
2058 | } | |
2059 | ||
2060 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 2061 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
2062 | { |
2063 | unsigned status = 0; | |
2064 | int clean_busy; | |
e18b7975 FB |
2065 | u32 is_xfer_complete; |
2066 | ||
2067 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
2068 | |
2069 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2070 | status = -ECONNRESET; | |
2071 | ||
1d046793 | 2072 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
4cb42217 | 2073 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || |
e18b7975 | 2074 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) |
72246da4 | 2075 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2076 | |
2077 | /* | |
2078 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2079 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2080 | */ | |
2081 | if (dwc->revision < DWC3_REVISION_183A) { | |
2082 | u32 reg; | |
2083 | int i; | |
2084 | ||
2085 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2086 | dep = dwc->eps[i]; |
fae2b904 FB |
2087 | |
2088 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2089 | continue; | |
2090 | ||
aa3342c8 | 2091 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2092 | return; |
2093 | } | |
2094 | ||
2095 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2096 | reg |= dwc->u1u2; | |
2097 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2098 | ||
2099 | dwc->u1u2 = 0; | |
2100 | } | |
8a1a9c9e | 2101 | |
4cb42217 FB |
2102 | /* |
2103 | * Our endpoint might get disabled by another thread during | |
2104 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2105 | * early on so DWC3_EP_BUSY flag gets cleared | |
2106 | */ | |
2107 | if (!dep->endpoint.desc) | |
2108 | return; | |
2109 | ||
e6e709b7 | 2110 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2111 | int ret; |
2112 | ||
4fae2e3e | 2113 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
8a1a9c9e FB |
2114 | if (!ret || ret == -EBUSY) |
2115 | return; | |
2116 | } | |
72246da4 FB |
2117 | } |
2118 | ||
72246da4 FB |
2119 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2120 | const struct dwc3_event_depevt *event) | |
2121 | { | |
2122 | struct dwc3_ep *dep; | |
2123 | u8 epnum = event->endpoint_number; | |
2124 | ||
2125 | dep = dwc->eps[epnum]; | |
2126 | ||
3336abb5 FB |
2127 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2128 | return; | |
2129 | ||
72246da4 FB |
2130 | if (epnum == 0 || epnum == 1) { |
2131 | dwc3_ep0_interrupt(dwc, event); | |
2132 | return; | |
2133 | } | |
2134 | ||
2135 | switch (event->endpoint_event) { | |
2136 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2137 | dep->resource_index = 0; |
c2df85ca | 2138 | |
16e78db7 | 2139 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
ec5e795c FB |
2140 | dwc3_trace(trace_dwc3_gadget, |
2141 | "%s is an Isochronous endpoint\n", | |
72246da4 FB |
2142 | dep->name); |
2143 | return; | |
2144 | } | |
2145 | ||
029d97ff | 2146 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2147 | break; |
2148 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2149 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2150 | break; |
2151 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2152 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2153 | dwc3_gadget_start_isoc(dwc, dep, event); |
2154 | } else { | |
6bb4fe12 | 2155 | int active; |
72246da4 FB |
2156 | int ret; |
2157 | ||
6bb4fe12 FB |
2158 | active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE; |
2159 | ||
73815280 | 2160 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", |
6bb4fe12 | 2161 | dep->name, active ? "Transfer Active" |
72246da4 FB |
2162 | : "Transfer Not Active"); |
2163 | ||
4fae2e3e | 2164 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
72246da4 FB |
2165 | if (!ret || ret == -EBUSY) |
2166 | return; | |
2167 | ||
ec5e795c FB |
2168 | dwc3_trace(trace_dwc3_gadget, |
2169 | "%s: failed to kick transfers\n", | |
72246da4 FB |
2170 | dep->name); |
2171 | } | |
2172 | ||
879631aa FB |
2173 | break; |
2174 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2175 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2176 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2177 | dep->name); | |
2178 | return; | |
2179 | } | |
2180 | ||
2181 | switch (event->status) { | |
2182 | case DEPEVT_STREAMEVT_FOUND: | |
73815280 FB |
2183 | dwc3_trace(trace_dwc3_gadget, |
2184 | "Stream %d found and started", | |
879631aa FB |
2185 | event->parameters); |
2186 | ||
2187 | break; | |
2188 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2189 | /* FALLTHROUGH */ | |
2190 | default: | |
ec5e795c FB |
2191 | dwc3_trace(trace_dwc3_gadget, |
2192 | "unable to find suitable stream\n"); | |
879631aa | 2193 | } |
72246da4 FB |
2194 | break; |
2195 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
ec5e795c | 2196 | dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name); |
72246da4 | 2197 | break; |
72246da4 | 2198 | case DWC3_DEPEVT_EPCMDCMPLT: |
73815280 | 2199 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); |
72246da4 FB |
2200 | break; |
2201 | } | |
2202 | } | |
2203 | ||
2204 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2205 | { | |
2206 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2207 | spin_unlock(&dwc->lock); | |
2208 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2209 | spin_lock(&dwc->lock); | |
2210 | } | |
2211 | } | |
2212 | ||
bc5ba2e0 FB |
2213 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2214 | { | |
73a30bfc | 2215 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2216 | spin_unlock(&dwc->lock); |
2217 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2218 | spin_lock(&dwc->lock); | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2223 | { | |
73a30bfc | 2224 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2225 | spin_unlock(&dwc->lock); |
2226 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2227 | spin_lock(&dwc->lock); |
8e74475b FB |
2228 | } |
2229 | } | |
2230 | ||
2231 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2232 | { | |
2233 | if (!dwc->gadget_driver) | |
2234 | return; | |
2235 | ||
2236 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2237 | spin_unlock(&dwc->lock); | |
2238 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2239 | spin_lock(&dwc->lock); |
2240 | } | |
2241 | } | |
2242 | ||
b992e681 | 2243 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2244 | { |
2245 | struct dwc3_ep *dep; | |
2246 | struct dwc3_gadget_ep_cmd_params params; | |
2247 | u32 cmd; | |
2248 | int ret; | |
2249 | ||
2250 | dep = dwc->eps[epnum]; | |
2251 | ||
b4996a86 | 2252 | if (!dep->resource_index) |
3daf74d7 PA |
2253 | return; |
2254 | ||
57911504 PA |
2255 | /* |
2256 | * NOTICE: We are violating what the Databook says about the | |
2257 | * EndTransfer command. Ideally we would _always_ wait for the | |
2258 | * EndTransfer Command Completion IRQ, but that's causing too | |
2259 | * much trouble synchronizing between us and gadget driver. | |
2260 | * | |
2261 | * We have discussed this with the IP Provider and it was | |
2262 | * suggested to giveback all requests here, but give HW some | |
2263 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2264 | * an arbitrary 100us delay for that. |
57911504 PA |
2265 | * |
2266 | * Note also that a similar handling was tested by Synopsys | |
2267 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2268 | * In short, what we're doing is: | |
2269 | * | |
2270 | * - Issue EndTransfer WITH CMDIOC bit set | |
2271 | * - Wait 100us | |
2272 | */ | |
2273 | ||
3daf74d7 | 2274 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2275 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2276 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2277 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2278 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2279 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2280 | WARN_ON_ONCE(ret); |
b4996a86 | 2281 | dep->resource_index = 0; |
041d81f4 | 2282 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2283 | udelay(100); |
72246da4 FB |
2284 | } |
2285 | ||
2286 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2287 | { | |
2288 | u32 epnum; | |
2289 | ||
2290 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2291 | struct dwc3_ep *dep; | |
2292 | ||
2293 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2294 | if (!dep) |
2295 | continue; | |
2296 | ||
72246da4 FB |
2297 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2298 | continue; | |
2299 | ||
624407f9 | 2300 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2301 | } |
2302 | } | |
2303 | ||
2304 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2305 | { | |
2306 | u32 epnum; | |
2307 | ||
2308 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2309 | struct dwc3_ep *dep; | |
72246da4 FB |
2310 | int ret; |
2311 | ||
2312 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2313 | if (!dep) |
2314 | continue; | |
72246da4 FB |
2315 | |
2316 | if (!(dep->flags & DWC3_EP_STALL)) | |
2317 | continue; | |
2318 | ||
2319 | dep->flags &= ~DWC3_EP_STALL; | |
2320 | ||
50c763f8 | 2321 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2322 | WARN_ON_ONCE(ret); |
2323 | } | |
2324 | } | |
2325 | ||
2326 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2327 | { | |
c4430a26 FB |
2328 | int reg; |
2329 | ||
72246da4 FB |
2330 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2331 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2332 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2333 | ||
2334 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2335 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2336 | |
72246da4 FB |
2337 | dwc3_disconnect_gadget(dwc); |
2338 | ||
2339 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2340 | dwc->setup_packet_pending = false; |
06a374ed | 2341 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2342 | |
2343 | dwc->connected = false; | |
72246da4 FB |
2344 | } |
2345 | ||
72246da4 FB |
2346 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2347 | { | |
2348 | u32 reg; | |
2349 | ||
fc8bb91b FB |
2350 | dwc->connected = true; |
2351 | ||
df62df56 FB |
2352 | /* |
2353 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2354 | * would cause a missing Disconnect Event if there's a | |
2355 | * pending Setup Packet in the FIFO. | |
2356 | * | |
2357 | * There's no suggested workaround on the official Bug | |
2358 | * report, which states that "unless the driver/application | |
2359 | * is doing any special handling of a disconnect event, | |
2360 | * there is no functional issue". | |
2361 | * | |
2362 | * Unfortunately, it turns out that we _do_ some special | |
2363 | * handling of a disconnect event, namely complete all | |
2364 | * pending transfers, notify gadget driver of the | |
2365 | * disconnection, and so on. | |
2366 | * | |
2367 | * Our suggested workaround is to follow the Disconnect | |
2368 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2369 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2370 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2371 | * same endpoint. |
2372 | * | |
2373 | * Refers to: | |
2374 | * | |
2375 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2376 | * generated if setup packet pending in FIFO | |
2377 | */ | |
2378 | if (dwc->revision < DWC3_REVISION_188A) { | |
2379 | if (dwc->setup_packet_pending) | |
2380 | dwc3_gadget_disconnect_interrupt(dwc); | |
2381 | } | |
2382 | ||
8e74475b | 2383 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2384 | |
2385 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2386 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2387 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2388 | dwc->test_mode = false; |
72246da4 FB |
2389 | |
2390 | dwc3_stop_active_transfers(dwc); | |
2391 | dwc3_clear_stall_all_ep(dwc); | |
2392 | ||
2393 | /* Reset device address to zero */ | |
2394 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2395 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2396 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2397 | } |
2398 | ||
2399 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2400 | { | |
2401 | u32 reg; | |
2402 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2403 | ||
2404 | /* | |
2405 | * We change the clock only at SS but I dunno why I would want to do | |
2406 | * this. Maybe it becomes part of the power saving plan. | |
2407 | */ | |
2408 | ||
ee5cd41c JY |
2409 | if ((speed != DWC3_DSTS_SUPERSPEED) && |
2410 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
72246da4 FB |
2411 | return; |
2412 | ||
2413 | /* | |
2414 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2415 | * each time on Connect Done. | |
2416 | */ | |
2417 | if (!usb30_clock) | |
2418 | return; | |
2419 | ||
2420 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2421 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2422 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2423 | } | |
2424 | ||
72246da4 FB |
2425 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2426 | { | |
72246da4 FB |
2427 | struct dwc3_ep *dep; |
2428 | int ret; | |
2429 | u32 reg; | |
2430 | u8 speed; | |
2431 | ||
72246da4 FB |
2432 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2433 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2434 | dwc->speed = speed; | |
2435 | ||
2436 | dwc3_update_ram_clk_sel(dwc, speed); | |
2437 | ||
2438 | switch (speed) { | |
7580862b JY |
2439 | case DWC3_DCFG_SUPERSPEED_PLUS: |
2440 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2441 | dwc->gadget.ep0->maxpacket = 512; | |
2442 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2443 | break; | |
72246da4 | 2444 | case DWC3_DCFG_SUPERSPEED: |
05870c5b FB |
2445 | /* |
2446 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2447 | * would cause a missing USB3 Reset event. | |
2448 | * | |
2449 | * In such situations, we should force a USB3 Reset | |
2450 | * event by calling our dwc3_gadget_reset_interrupt() | |
2451 | * routine. | |
2452 | * | |
2453 | * Refers to: | |
2454 | * | |
2455 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2456 | * not be generated always when the link enters poll | |
2457 | */ | |
2458 | if (dwc->revision < DWC3_REVISION_190A) | |
2459 | dwc3_gadget_reset_interrupt(dwc); | |
2460 | ||
72246da4 FB |
2461 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2462 | dwc->gadget.ep0->maxpacket = 512; | |
2463 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2464 | break; | |
2465 | case DWC3_DCFG_HIGHSPEED: | |
2466 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2467 | dwc->gadget.ep0->maxpacket = 64; | |
2468 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2469 | break; | |
2470 | case DWC3_DCFG_FULLSPEED2: | |
2471 | case DWC3_DCFG_FULLSPEED1: | |
2472 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2473 | dwc->gadget.ep0->maxpacket = 64; | |
2474 | dwc->gadget.speed = USB_SPEED_FULL; | |
2475 | break; | |
2476 | case DWC3_DCFG_LOWSPEED: | |
2477 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2478 | dwc->gadget.ep0->maxpacket = 8; | |
2479 | dwc->gadget.speed = USB_SPEED_LOW; | |
2480 | break; | |
2481 | } | |
2482 | ||
2b758350 PA |
2483 | /* Enable USB2 LPM Capability */ |
2484 | ||
ee5cd41c JY |
2485 | if ((dwc->revision > DWC3_REVISION_194A) && |
2486 | (speed != DWC3_DCFG_SUPERSPEED) && | |
2487 | (speed != DWC3_DCFG_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2488 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2489 | reg |= DWC3_DCFG_LPM_CAP; | |
2490 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2491 | ||
2492 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2493 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2494 | ||
460d098c | 2495 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2496 | |
80caf7d2 HR |
2497 | /* |
2498 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2499 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2500 | * BESL value in the LPM token is less than or equal to LPM | |
2501 | * NYET threshold. | |
2502 | */ | |
2503 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2504 | && dwc->has_lpm_erratum, | |
2505 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2506 | ||
2507 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2508 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2509 | ||
356363bf FB |
2510 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2511 | } else { | |
2512 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2513 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2514 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2515 | } | |
2516 | ||
72246da4 | 2517 | dep = dwc->eps[0]; |
265b70a7 PZ |
2518 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2519 | false); | |
72246da4 FB |
2520 | if (ret) { |
2521 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2522 | return; | |
2523 | } | |
2524 | ||
2525 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2526 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2527 | false); | |
72246da4 FB |
2528 | if (ret) { |
2529 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2530 | return; | |
2531 | } | |
2532 | ||
2533 | /* | |
2534 | * Configure PHY via GUSB3PIPECTLn if required. | |
2535 | * | |
2536 | * Update GTXFIFOSIZn | |
2537 | * | |
2538 | * In both cases reset values should be sufficient. | |
2539 | */ | |
2540 | } | |
2541 | ||
2542 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2543 | { | |
72246da4 FB |
2544 | /* |
2545 | * TODO take core out of low power mode when that's | |
2546 | * implemented. | |
2547 | */ | |
2548 | ||
ad14d4e0 JL |
2549 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2550 | spin_unlock(&dwc->lock); | |
2551 | dwc->gadget_driver->resume(&dwc->gadget); | |
2552 | spin_lock(&dwc->lock); | |
2553 | } | |
72246da4 FB |
2554 | } |
2555 | ||
2556 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2557 | unsigned int evtinfo) | |
2558 | { | |
fae2b904 | 2559 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2560 | unsigned int pwropt; |
2561 | ||
2562 | /* | |
2563 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2564 | * Hibernation mode enabled which would show up when device detects | |
2565 | * host-initiated U3 exit. | |
2566 | * | |
2567 | * In that case, device will generate a Link State Change Interrupt | |
2568 | * from U3 to RESUME which is only necessary if Hibernation is | |
2569 | * configured in. | |
2570 | * | |
2571 | * There are no functional changes due to such spurious event and we | |
2572 | * just need to ignore it. | |
2573 | * | |
2574 | * Refers to: | |
2575 | * | |
2576 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2577 | * operational mode | |
2578 | */ | |
2579 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2580 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2581 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2582 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2583 | (next == DWC3_LINK_STATE_RESUME)) { | |
73815280 FB |
2584 | dwc3_trace(trace_dwc3_gadget, |
2585 | "ignoring transition U3 -> Resume"); | |
0b0cc1cd FB |
2586 | return; |
2587 | } | |
2588 | } | |
fae2b904 FB |
2589 | |
2590 | /* | |
2591 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2592 | * on the link partner, the USB session might do multiple entry/exit | |
2593 | * of low power states before a transfer takes place. | |
2594 | * | |
2595 | * Due to this problem, we might experience lower throughput. The | |
2596 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2597 | * transitioning from U1/U2 to U0 and enable those bits again | |
2598 | * after a transfer completes and there are no pending transfers | |
2599 | * on any of the enabled endpoints. | |
2600 | * | |
2601 | * This is the first half of that workaround. | |
2602 | * | |
2603 | * Refers to: | |
2604 | * | |
2605 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2606 | * core send LGO_Ux entering U0 | |
2607 | */ | |
2608 | if (dwc->revision < DWC3_REVISION_183A) { | |
2609 | if (next == DWC3_LINK_STATE_U0) { | |
2610 | u32 u1u2; | |
2611 | u32 reg; | |
2612 | ||
2613 | switch (dwc->link_state) { | |
2614 | case DWC3_LINK_STATE_U1: | |
2615 | case DWC3_LINK_STATE_U2: | |
2616 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2617 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2618 | | DWC3_DCTL_ACCEPTU2ENA | |
2619 | | DWC3_DCTL_INITU1ENA | |
2620 | | DWC3_DCTL_ACCEPTU1ENA); | |
2621 | ||
2622 | if (!dwc->u1u2) | |
2623 | dwc->u1u2 = reg & u1u2; | |
2624 | ||
2625 | reg &= ~u1u2; | |
2626 | ||
2627 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2628 | break; | |
2629 | default: | |
2630 | /* do nothing */ | |
2631 | break; | |
2632 | } | |
2633 | } | |
2634 | } | |
2635 | ||
bc5ba2e0 FB |
2636 | switch (next) { |
2637 | case DWC3_LINK_STATE_U1: | |
2638 | if (dwc->speed == USB_SPEED_SUPER) | |
2639 | dwc3_suspend_gadget(dwc); | |
2640 | break; | |
2641 | case DWC3_LINK_STATE_U2: | |
2642 | case DWC3_LINK_STATE_U3: | |
2643 | dwc3_suspend_gadget(dwc); | |
2644 | break; | |
2645 | case DWC3_LINK_STATE_RESUME: | |
2646 | dwc3_resume_gadget(dwc); | |
2647 | break; | |
2648 | default: | |
2649 | /* do nothing */ | |
2650 | break; | |
2651 | } | |
2652 | ||
e57ebc1d | 2653 | dwc->link_state = next; |
72246da4 FB |
2654 | } |
2655 | ||
e1dadd3b FB |
2656 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2657 | unsigned int evtinfo) | |
2658 | { | |
2659 | unsigned int is_ss = evtinfo & BIT(4); | |
2660 | ||
2661 | /** | |
2662 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2663 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2664 | * randomly. | |
2665 | * | |
2666 | * Because of this issue, core could generate bogus hibernation | |
2667 | * events which SW needs to ignore. | |
2668 | * | |
2669 | * Refers to: | |
2670 | * | |
2671 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2672 | * Device Fallback from SuperSpeed | |
2673 | */ | |
2674 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2675 | return; | |
2676 | ||
2677 | /* enter hibernation here */ | |
2678 | } | |
2679 | ||
72246da4 FB |
2680 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2681 | const struct dwc3_event_devt *event) | |
2682 | { | |
2683 | switch (event->type) { | |
2684 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2685 | dwc3_gadget_disconnect_interrupt(dwc); | |
2686 | break; | |
2687 | case DWC3_DEVICE_EVENT_RESET: | |
2688 | dwc3_gadget_reset_interrupt(dwc); | |
2689 | break; | |
2690 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2691 | dwc3_gadget_conndone_interrupt(dwc); | |
2692 | break; | |
2693 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2694 | dwc3_gadget_wakeup_interrupt(dwc); | |
2695 | break; | |
e1dadd3b FB |
2696 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2697 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2698 | "unexpected hibernation event\n")) | |
2699 | break; | |
2700 | ||
2701 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2702 | break; | |
72246da4 FB |
2703 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2704 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2705 | break; | |
2706 | case DWC3_DEVICE_EVENT_EOPF: | |
73815280 | 2707 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); |
72246da4 FB |
2708 | break; |
2709 | case DWC3_DEVICE_EVENT_SOF: | |
73815280 | 2710 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); |
72246da4 FB |
2711 | break; |
2712 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
73815280 | 2713 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); |
72246da4 FB |
2714 | break; |
2715 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
73815280 | 2716 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); |
72246da4 FB |
2717 | break; |
2718 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
73815280 | 2719 | dwc3_trace(trace_dwc3_gadget, "Overflow"); |
72246da4 FB |
2720 | break; |
2721 | default: | |
e9f2aa87 | 2722 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2723 | } |
2724 | } | |
2725 | ||
2726 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2727 | const union dwc3_event *event) | |
2728 | { | |
2c4cbe6e FB |
2729 | trace_dwc3_event(event->raw); |
2730 | ||
72246da4 FB |
2731 | /* Endpoint IRQ, handle it and return early */ |
2732 | if (event->type.is_devspec == 0) { | |
2733 | /* depevt */ | |
2734 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2735 | } | |
2736 | ||
2737 | switch (event->type.type) { | |
2738 | case DWC3_EVENT_TYPE_DEV: | |
2739 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2740 | break; | |
2741 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2742 | default: | |
2743 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2744 | } | |
2745 | } | |
2746 | ||
dea520a4 | 2747 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2748 | { |
dea520a4 | 2749 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2750 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2751 | int left; |
e8adfc30 | 2752 | u32 reg; |
b15a762f | 2753 | |
f42f2447 | 2754 | left = evt->count; |
b15a762f | 2755 | |
f42f2447 FB |
2756 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2757 | return IRQ_NONE; | |
b15a762f | 2758 | |
f42f2447 FB |
2759 | while (left > 0) { |
2760 | union dwc3_event event; | |
b15a762f | 2761 | |
f42f2447 | 2762 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2763 | |
f42f2447 | 2764 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2765 | |
f42f2447 FB |
2766 | /* |
2767 | * FIXME we wrap around correctly to the next entry as | |
2768 | * almost all entries are 4 bytes in size. There is one | |
2769 | * entry which has 12 bytes which is a regular entry | |
2770 | * followed by 8 bytes data. ATM I don't know how | |
2771 | * things are organized if we get next to the a | |
2772 | * boundary so I worry about that once we try to handle | |
2773 | * that. | |
2774 | */ | |
2775 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2776 | left -= 4; | |
b15a762f | 2777 | |
660e9bde | 2778 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); |
f42f2447 | 2779 | } |
b15a762f | 2780 | |
f42f2447 FB |
2781 | evt->count = 0; |
2782 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2783 | ret = IRQ_HANDLED; | |
b15a762f | 2784 | |
f42f2447 | 2785 | /* Unmask interrupt */ |
660e9bde | 2786 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 2787 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2788 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 2789 | |
f42f2447 FB |
2790 | return ret; |
2791 | } | |
e8adfc30 | 2792 | |
dea520a4 | 2793 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 2794 | { |
dea520a4 FB |
2795 | struct dwc3_event_buffer *evt = _evt; |
2796 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 2797 | unsigned long flags; |
f42f2447 | 2798 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2799 | |
e5f68b4a | 2800 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 2801 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 2802 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2803 | |
2804 | return ret; | |
2805 | } | |
2806 | ||
dea520a4 | 2807 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 2808 | { |
dea520a4 | 2809 | struct dwc3 *dwc = evt->dwc; |
72246da4 | 2810 | u32 count; |
e8adfc30 | 2811 | u32 reg; |
72246da4 | 2812 | |
fc8bb91b FB |
2813 | if (pm_runtime_suspended(dwc->dev)) { |
2814 | pm_runtime_get(dwc->dev); | |
2815 | disable_irq_nosync(dwc->irq_gadget); | |
2816 | dwc->pending_events = true; | |
2817 | return IRQ_HANDLED; | |
2818 | } | |
2819 | ||
660e9bde | 2820 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
2821 | count &= DWC3_GEVNTCOUNT_MASK; |
2822 | if (!count) | |
2823 | return IRQ_NONE; | |
2824 | ||
b15a762f FB |
2825 | evt->count = count; |
2826 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2827 | |
e8adfc30 | 2828 | /* Mask interrupt */ |
660e9bde | 2829 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 2830 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2831 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 2832 | |
b15a762f | 2833 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2834 | } |
2835 | ||
dea520a4 | 2836 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 2837 | { |
dea520a4 | 2838 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 2839 | |
dea520a4 | 2840 | return dwc3_check_event_buf(evt); |
72246da4 FB |
2841 | } |
2842 | ||
2843 | /** | |
2844 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2845 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2846 | * |
2847 | * Returns 0 on success otherwise negative errno. | |
2848 | */ | |
41ac7b3a | 2849 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2850 | { |
72246da4 | 2851 | int ret; |
72246da4 FB |
2852 | |
2853 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2854 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2855 | if (!dwc->ctrl_req) { | |
2856 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2857 | ret = -ENOMEM; | |
2858 | goto err0; | |
2859 | } | |
2860 | ||
2abd9d5f | 2861 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2862 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2863 | if (!dwc->ep0_trb) { | |
2864 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2865 | ret = -ENOMEM; | |
2866 | goto err1; | |
2867 | } | |
2868 | ||
3ef35faf | 2869 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2870 | if (!dwc->setup_buf) { |
72246da4 FB |
2871 | ret = -ENOMEM; |
2872 | goto err2; | |
2873 | } | |
2874 | ||
5812b1c2 | 2875 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2876 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2877 | GFP_KERNEL); | |
5812b1c2 FB |
2878 | if (!dwc->ep0_bounce) { |
2879 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2880 | ret = -ENOMEM; | |
2881 | goto err3; | |
2882 | } | |
2883 | ||
04c03d10 FB |
2884 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); |
2885 | if (!dwc->zlp_buf) { | |
2886 | ret = -ENOMEM; | |
2887 | goto err4; | |
2888 | } | |
2889 | ||
72246da4 | 2890 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 2891 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2892 | dwc->gadget.sg_supported = true; |
72246da4 | 2893 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 2894 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 2895 | |
b9e51b2b BM |
2896 | /* |
2897 | * FIXME We might be setting max_speed to <SUPER, however versions | |
2898 | * <2.20a of dwc3 have an issue with metastability (documented | |
2899 | * elsewhere in this driver) which tells us we can't set max speed to | |
2900 | * anything lower than SUPER. | |
2901 | * | |
2902 | * Because gadget.max_speed is only used by composite.c and function | |
2903 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
2904 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
2905 | * together with our BOS descriptor as that could confuse host into | |
2906 | * thinking we can handle super speed. | |
2907 | * | |
2908 | * Note that, in fact, we won't even support GetBOS requests when speed | |
2909 | * is less than super speed because we don't have means, yet, to tell | |
2910 | * composite.c that we are USB 2.0 + LPM ECN. | |
2911 | */ | |
2912 | if (dwc->revision < DWC3_REVISION_220A) | |
2913 | dwc3_trace(trace_dwc3_gadget, | |
2914 | "Changing max_speed on rev %08x\n", | |
2915 | dwc->revision); | |
2916 | ||
2917 | dwc->gadget.max_speed = dwc->maximum_speed; | |
2918 | ||
a4b9d94b DC |
2919 | /* |
2920 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2921 | * on ep out. | |
2922 | */ | |
2923 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2924 | ||
72246da4 FB |
2925 | /* |
2926 | * REVISIT: Here we should clear all pending IRQs to be | |
2927 | * sure we're starting from a well known location. | |
2928 | */ | |
2929 | ||
2930 | ret = dwc3_gadget_init_endpoints(dwc); | |
2931 | if (ret) | |
04c03d10 | 2932 | goto err5; |
72246da4 | 2933 | |
72246da4 FB |
2934 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2935 | if (ret) { | |
2936 | dev_err(dwc->dev, "failed to register udc\n"); | |
04c03d10 | 2937 | goto err5; |
72246da4 FB |
2938 | } |
2939 | ||
2940 | return 0; | |
2941 | ||
04c03d10 FB |
2942 | err5: |
2943 | kfree(dwc->zlp_buf); | |
2944 | ||
5812b1c2 | 2945 | err4: |
e1f80467 | 2946 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2947 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2948 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2949 | |
72246da4 | 2950 | err3: |
0fc9a1be | 2951 | kfree(dwc->setup_buf); |
72246da4 FB |
2952 | |
2953 | err2: | |
2954 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2955 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2956 | ||
2957 | err1: | |
2958 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2959 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2960 | ||
2961 | err0: | |
2962 | return ret; | |
2963 | } | |
2964 | ||
7415f17c FB |
2965 | /* -------------------------------------------------------------------------- */ |
2966 | ||
72246da4 FB |
2967 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2968 | { | |
72246da4 | 2969 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2970 | |
72246da4 FB |
2971 | dwc3_gadget_free_endpoints(dwc); |
2972 | ||
3ef35faf FB |
2973 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2974 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2975 | |
0fc9a1be | 2976 | kfree(dwc->setup_buf); |
04c03d10 | 2977 | kfree(dwc->zlp_buf); |
72246da4 FB |
2978 | |
2979 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2980 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2981 | ||
2982 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2983 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2984 | } |
7415f17c | 2985 | |
0b0231aa | 2986 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 2987 | { |
9f8a67b6 FB |
2988 | int ret; |
2989 | ||
9772b47a RQ |
2990 | if (!dwc->gadget_driver) |
2991 | return 0; | |
2992 | ||
9f8a67b6 FB |
2993 | ret = dwc3_gadget_run_stop(dwc, false, false); |
2994 | if (ret < 0) | |
2995 | return ret; | |
7415f17c | 2996 | |
9f8a67b6 FB |
2997 | dwc3_disconnect_gadget(dwc); |
2998 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
2999 | |
3000 | return 0; | |
3001 | } | |
3002 | ||
3003 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3004 | { | |
7415f17c FB |
3005 | int ret; |
3006 | ||
9772b47a RQ |
3007 | if (!dwc->gadget_driver) |
3008 | return 0; | |
3009 | ||
9f8a67b6 FB |
3010 | ret = __dwc3_gadget_start(dwc); |
3011 | if (ret < 0) | |
7415f17c FB |
3012 | goto err0; |
3013 | ||
9f8a67b6 FB |
3014 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3015 | if (ret < 0) | |
7415f17c FB |
3016 | goto err1; |
3017 | ||
7415f17c FB |
3018 | return 0; |
3019 | ||
3020 | err1: | |
9f8a67b6 | 3021 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3022 | |
3023 | err0: | |
3024 | return ret; | |
3025 | } | |
fc8bb91b FB |
3026 | |
3027 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3028 | { | |
3029 | if (dwc->pending_events) { | |
3030 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3031 | dwc->pending_events = false; | |
3032 | enable_irq(dwc->irq_gadget); | |
3033 | } | |
3034 | } |