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usb: dwc3: gadget: allocate bounce buffer for unaligned xfers
[mirror_ubuntu-artful-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
d6214592 183 if (dwc->ep0_bounced && dep->number <= 1)
0416e494 184 dwc->ep0_bounced = false;
d6214592
FB		 185
186 usb_gadget_unmap_request_by_dev(dwc->sysdev,
187 &req->request, req->direction);
72246da4 188
2c4cbe6e 189 trace_dwc3_gadget_giveback(req);
72246da4
FB		 190
191 spin_unlock(&dwc->lock);
304f7e5e 192 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 193 spin_lock(&dwc->lock);
fc8bb91b
FB		 194
195 if (dep->number > 1)
196 pm_runtime_put(dwc->dev);
72246da4
FB		 197}
198
3ece0ec4 199int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 200{
201 u32 timeout = 500;
71f7e702 202 int status = 0;
0fe886cd 203 int ret = 0;
b09bb642
FB		 204 u32 reg;
205
206 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
207 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
208
209 do {
210 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
211 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 212 status = DWC3_DGCMD_STATUS(reg);
213 if (status)
0fe886cd
FB		 214 ret = -EINVAL;
215 break;
b09bb642 216 }
e3aee486 217 } while (--timeout);
0fe886cd
FB		 218
219 if (!timeout) {
0fe886cd 220 ret = -ETIMEDOUT;
71f7e702 221 status = -ETIMEDOUT;
0fe886cd
FB		 222 }
223
71f7e702
FB		 224 trace_dwc3_gadget_generic_cmd(cmd, param, status);
225
0fe886cd 226 return ret;
b09bb642
FB		 227}
228
c36d8e94
FB		 229static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
230
2cd4718d
FB		 231int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
232 struct dwc3_gadget_ep_cmd_params *params)
72246da4 233{
8897a761 234 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 235 struct dwc3 *dwc = dep->dwc;
61d58242 236 u32 timeout = 500;
72246da4
FB		 237 u32 reg;
238
0933df15 239 int cmd_status = 0;
2b0f11df 240 int susphy = false;
c0ca324d 241 int ret = -EINVAL;
72246da4 242
2b0f11df
FB		 243 /*
244 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245 * we're issuing an endpoint command, we must check if
246 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
247 *
248 * We will also set SUSPHY bit to what it was before returning as stated
249 * by the same section on Synopsys databook.
250 */
ab2a92e7
FB		 251 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
252 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
253 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
254 susphy = true;
255 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
256 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
257 }
2b0f11df
FB		 258 }
259
5999914f 260 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 261 int needs_wakeup;
262
263 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
264 dwc->link_state == DWC3_LINK_STATE_U2 ||
265 dwc->link_state == DWC3_LINK_STATE_U3);
266
267 if (unlikely(needs_wakeup)) {
268 ret = __dwc3_gadget_wakeup(dwc);
269 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
270 ret);
271 }
272 }
273
2eb88016
FB		 274 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
275 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
276 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 277
8897a761
FB		 278 /*
279 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280 * not relying on XferNotReady, we can make use of a special "No
281 * Response Update Transfer" command where we should clear both CmdAct
282 * and CmdIOC bits.
283 *
284 * With this, we don't need to wait for command completion and can
285 * straight away issue further commands to the endpoint.
286 *
287 * NOTICE: We're making an assumption that control endpoints will never
288 * make use of Update Transfer command. This is a safe assumption
289 * because we can never have more than one request at a time with
290 * Control Endpoints. If anybody changes that assumption, this chunk
291 * needs to be updated accordingly.
292 */
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
294 !usb_endpoint_xfer_isoc(desc))
295 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
296 else
297 cmd |= DWC3_DEPCMD_CMDACT;
298
299 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 300 do {
2eb88016 301 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 302 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 303 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 304
7b9cc7a2
KL		 305 switch (cmd_status) {
306 case 0:
307 ret = 0;
308 break;
309 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 310 ret = -EINVAL;
c0ca324d 311 break;
7b9cc7a2
KL		 312 case DEPEVT_TRANSFER_BUS_EXPIRY:
313 /*
314 * SW issues START TRANSFER command to
315 * isochronous ep with future frame interval. If
316 * future interval time has already passed when
317 * core receives the command, it will respond
318 * with an error status of 'Bus Expiry'.
319 *
320 * Instead of always returning -EINVAL, let's
321 * give a hint to the gadget driver that this is
322 * the case by returning -EAGAIN.
323 */
7b9cc7a2
KL		 324 ret = -EAGAIN;
325 break;
326 default:
327 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
328 }
329
c0ca324d 330 break;
72246da4 331 }
f6bb225b 332 } while (--timeout);
72246da4 333
f6bb225b 334 if (timeout == 0) {
f6bb225b 335 ret = -ETIMEDOUT;
0933df15 336 cmd_status = -ETIMEDOUT;
f6bb225b 337 }
c0ca324d 338
0933df15
FB		 339 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
340
6cb2e4e3
FB		 341 if (ret == 0) {
342 switch (DWC3_DEPCMD_CMD(cmd)) {
343 case DWC3_DEPCMD_STARTTRANSFER:
344 dep->flags |= DWC3_EP_TRANSFER_STARTED;
345 break;
346 case DWC3_DEPCMD_ENDTRANSFER:
347 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
348 break;
349 default:
350 /* nothing */
351 break;
352 }
353 }
354
2b0f11df
FB		 355 if (unlikely(susphy)) {
356 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
357 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
358 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
359 }
360
c0ca324d 361 return ret;
72246da4
FB		 362}
363
50c763f8
JY		 364static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
365{
366 struct dwc3 *dwc = dep->dwc;
367 struct dwc3_gadget_ep_cmd_params params;
368 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
369
370 /*
371 * As of core revision 2.60a the recommended programming model
372 * is to set the ClearPendIN bit when issuing a Clear Stall EP
373 * command for IN endpoints. This is to prevent an issue where
374 * some (non-compliant) hosts may not send ACK TPs for pending
375 * IN transfers due to a mishandled error condition. Synopsys
376 * STAR 9000614252.
377 */
5e6c88d2
LB		 378 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
379 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 380 cmd |= DWC3_DEPCMD_CLEARPENDIN;
381
382 memset(&params, 0, sizeof(params));
383
2cd4718d 384 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 385}
386
72246da4 387static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 388 struct dwc3_trb *trb)
72246da4 389{
c439ef87 390 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 391
392 return dep->trb_pool_dma + offset;
393}
394
395static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398
399 if (dep->trb_pool)
400 return 0;
401
d64ff406 402 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 403 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
404 &dep->trb_pool_dma, GFP_KERNEL);
405 if (!dep->trb_pool) {
406 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
407 dep->name);
408 return -ENOMEM;
409 }
410
411 return 0;
412}
413
414static void dwc3_free_trb_pool(struct dwc3_ep *dep)
415{
416 struct dwc3 *dwc = dep->dwc;
417
d64ff406 418 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 419 dep->trb_pool, dep->trb_pool_dma);
420
421 dep->trb_pool = NULL;
422 dep->trb_pool_dma = 0;
423}
424
c4509601
JY		 425static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
426
427/**
428 * dwc3_gadget_start_config - Configure EP resources
429 * @dwc: pointer to our controller context structure
430 * @dep: endpoint that is being enabled
431 *
432 * The assignment of transfer resources cannot perfectly follow the
433 * data book due to the fact that the controller driver does not have
434 * all knowledge of the configuration in advance. It is given this
435 * information piecemeal by the composite gadget framework after every
436 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437 * programming model in this scenario can cause errors. For two
438 * reasons:
439 *
440 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442 * multiple interfaces.
443 *
444 * 2) The databook does not mention doing more DEPXFERCFG for new
445 * endpoint on alt setting (8.1.6).
446 *
447 * The following simplified method is used instead:
448 *
449 * All hardware endpoints can be assigned a transfer resource and this
450 * setting will stay persistent until either a core reset or
451 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452 * do DEPXFERCFG for every hardware endpoint as well. We are
453 * guaranteed that there are as many transfer resources as endpoints.
454 *
455 * This function is called for each endpoint when it is being enabled
456 * but is triggered only when called for EP0-out, which always happens
457 * first, and which should only happen in one of the above conditions.
458 */
72246da4
FB		 459static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
460{
461 struct dwc3_gadget_ep_cmd_params params;
462 u32 cmd;
c4509601
JY		 463 int i;
464 int ret;
465
466 if (dep->number)
467 return 0;
72246da4
FB		 468
469 memset(&params, 0x00, sizeof(params));
c4509601 470 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 471
2cd4718d 472 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 473 if (ret)
474 return ret;
475
476 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
477 struct dwc3_ep *dep = dwc->eps[i];
72246da4 478
c4509601
JY		 479 if (!dep)
480 continue;
481
482 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
483 if (ret)
484 return ret;
72246da4
FB		 485 }
486
487 return 0;
488}
489
490static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 491 bool modify, bool restore)
72246da4 492{
39ebb05c
JY		 493 const struct usb_ss_ep_comp_descriptor *comp_desc;
494 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 495 struct dwc3_gadget_ep_cmd_params params;
496
21e64bf2
FB		 497 if (dev_WARN_ONCE(dwc->dev, modify && restore,
498 "Can't modify and restore\n"))
499 return -EINVAL;
500
39ebb05c
JY		 501 comp_desc = dep->endpoint.comp_desc;
502 desc = dep->endpoint.desc;
503
72246da4
FB		 504 memset(&params, 0x00, sizeof(params));
505
dc1c70a7 506 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 507 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
508
509 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 510 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 511 u32 burst = dep->endpoint.maxburst;
676e3497 512 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 513 }
72246da4 514
21e64bf2
FB		 515 if (modify) {
516 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
517 } else if (restore) {
265b70a7
PZ		 518 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
519 params.param2 |= dep->saved_state;
21e64bf2
FB		 520 } else {
521 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 522 }
523
4bc48c97
FB		 524 if (usb_endpoint_xfer_control(desc))
525 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 526
527 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
528 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 529
18b7ede5 530 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 531 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
532 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 533 dep->stream_capable = true;
534 }
535
0b93a4c8 536 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 537 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 538
539 /*
540 * We are doing 1:1 mapping for endpoints, meaning
541 * Physical Endpoints 2 maps to Logical Endpoint 2 and
542 * so on. We consider the direction bit as part of the physical
543 * endpoint number. So USB endpoint 0x81 is 0x03.
544 */
dc1c70a7 545 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 546
547 /*
548 * We must use the lower 16 TX FIFOs even though
549 * HW might have more
550 */
551 if (dep->direction)
dc1c70a7 552 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 553
554 if (desc->bInterval) {
dc1c70a7 555 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 556 dep->interval = 1 << (desc->bInterval - 1);
557 }
558
2cd4718d 559 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 560}
561
562static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
563{
564 struct dwc3_gadget_ep_cmd_params params;
565
566 memset(&params, 0x00, sizeof(params));
567
dc1c70a7 568 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 569
2cd4718d
FB		 570 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
571 &params);
72246da4
FB		 572}
573
574/**
575 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
576 * @dep: endpoint to be initialized
577 * @desc: USB Endpoint Descriptor
578 *
579 * Caller should take care of locking
580 */
581static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 582 bool modify, bool restore)
72246da4 583{
39ebb05c 584 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 585 struct dwc3 *dwc = dep->dwc;
39ebb05c 586
72246da4 587 u32 reg;
b09e99ee 588 int ret;
72246da4
FB		 589
590 if (!(dep->flags & DWC3_EP_ENABLED)) {
591 ret = dwc3_gadget_start_config(dwc, dep);
592 if (ret)
593 return ret;
594 }
595
39ebb05c 596 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 597 if (ret)
598 return ret;
599
600 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 601 struct dwc3_trb *trb_st_hw;
602 struct dwc3_trb *trb_link;
72246da4 603
72246da4
FB		 604 dep->type = usb_endpoint_type(desc);
605 dep->flags |= DWC3_EP_ENABLED;
76a638f8 606 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 607
608 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
609 reg |= DWC3_DALEPENA_EP(dep->number);
610 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611
76a638f8
BW		 612 init_waitqueue_head(&dep->wait_end_transfer);
613
36b68aae 614 if (usb_endpoint_xfer_control(desc))
2870e501 615 goto out;
72246da4 616
0d25744a
JY		 617 /* Initialize the TRB ring */
618 dep->trb_dequeue = 0;
619 dep->trb_enqueue = 0;
620 memset(dep->trb_pool, 0,
621 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
622
36b68aae 623 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 624 trb_st_hw = &dep->trb_pool[0];
625
f6bafc6a 626 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 627 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
628 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
629 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
630 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 631 }
632
a97ea994
FB		 633 /*
634 * Issue StartTransfer here with no-op TRB so we can always rely on No
635 * Response Update Transfer command.
636 */
637 if (usb_endpoint_xfer_bulk(desc)) {
638 struct dwc3_gadget_ep_cmd_params params;
639 struct dwc3_trb *trb;
640 dma_addr_t trb_dma;
641 u32 cmd;
642
643 memset(&params, 0, sizeof(params));
644 trb = &dep->trb_pool[0];
645 trb_dma = dwc3_trb_dma_offset(dep, trb);
646
647 params.param0 = upper_32_bits(trb_dma);
648 params.param1 = lower_32_bits(trb_dma);
649
650 cmd = DWC3_DEPCMD_STARTTRANSFER;
651
652 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
653 if (ret < 0)
654 return ret;
655
656 dep->flags |= DWC3_EP_BUSY;
657
658 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
659 WARN_ON_ONCE(!dep->resource_index);
660 }
661
2870e501
FB		 662
663out:
664 trace_dwc3_gadget_ep_enable(dep);
665
72246da4
FB		 666 return 0;
667}
668
b992e681 669static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 670static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 671{
672 struct dwc3_request *req;
673
0e146028 674 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 675
0e146028
FB		 676 /* - giveback all requests to gadget driver */
677 while (!list_empty(&dep->started_list)) {
678 req = next_request(&dep->started_list);
1591633e 679
0e146028 680 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 681 }
682
aa3342c8
FB		 683 while (!list_empty(&dep->pending_list)) {
684 req = next_request(&dep->pending_list);
72246da4 685
624407f9 686 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 687 }
72246da4
FB		 688}
689
690/**
691 * __dwc3_gadget_ep_disable - Disables a HW endpoint
692 * @dep: the endpoint to disable
693 *
624407f9
SAS		 694 * This function also removes requests which are currently processed ny the
695 * hardware and those which are not yet scheduled.
696 * Caller should take care of locking.
72246da4 697 */
72246da4
FB		 698static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
699{
700 struct dwc3 *dwc = dep->dwc;
701 u32 reg;
702
2870e501 703 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 704
624407f9 705 dwc3_remove_requests(dwc, dep);
72246da4 706
687ef981
FB		 707 /* make sure HW endpoint isn't stalled */
708 if (dep->flags & DWC3_EP_STALL)
7a608559 709 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 710
72246da4
FB		 711 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
712 reg &= ~DWC3_DALEPENA_EP(dep->number);
713 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
714
879631aa 715 dep->stream_capable = false;
72246da4 716 dep->type = 0;
76a638f8 717 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 718
39ebb05c
JY		 719 /* Clear out the ep descriptors for non-ep0 */
720 if (dep->number > 1) {
721 dep->endpoint.comp_desc = NULL;
722 dep->endpoint.desc = NULL;
723 }
724
72246da4
FB		 725 return 0;
726}
727
728/* -------------------------------------------------------------------------- */
729
730static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
731 const struct usb_endpoint_descriptor *desc)
732{
733 return -EINVAL;
734}
735
736static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
737{
738 return -EINVAL;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 struct dwc3_ep *dep;
747 struct dwc3 *dwc;
748 unsigned long flags;
749 int ret;
750
751 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
752 pr_debug("dwc3: invalid parameters\n");
753 return -EINVAL;
754 }
755
756 if (!desc->wMaxPacketSize) {
757 pr_debug("dwc3: missing wMaxPacketSize\n");
758 return -EINVAL;
759 }
760
761 dep = to_dwc3_ep(ep);
762 dwc = dep->dwc;
763
95ca961c
FB		 764 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
765 "%s is already enabled\n",
766 dep->name))
c6f83f38 767 return 0;
c6f83f38 768
72246da4 769 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 770 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 771 spin_unlock_irqrestore(&dwc->lock, flags);
772
773 return ret;
774}
775
776static int dwc3_gadget_ep_disable(struct usb_ep *ep)
777{
778 struct dwc3_ep *dep;
779 struct dwc3 *dwc;
780 unsigned long flags;
781 int ret;
782
783 if (!ep) {
784 pr_debug("dwc3: invalid parameters\n");
785 return -EINVAL;
786 }
787
788 dep = to_dwc3_ep(ep);
789 dwc = dep->dwc;
790
95ca961c
FB		 791 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
792 "%s is already disabled\n",
793 dep->name))
72246da4 794 return 0;
72246da4 795
72246da4
FB		 796 spin_lock_irqsave(&dwc->lock, flags);
797 ret = __dwc3_gadget_ep_disable(dep);
798 spin_unlock_irqrestore(&dwc->lock, flags);
799
800 return ret;
801}
802
803static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
804 gfp_t gfp_flags)
805{
806 struct dwc3_request *req;
807 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 808
809 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 810 if (!req)
72246da4 811 return NULL;
72246da4
FB		 812
813 req->epnum = dep->number;
814 req->dep = dep;
72246da4 815
68d34c8a
FB		 816 dep->allocated_requests++;
817
2c4cbe6e
FB		 818 trace_dwc3_alloc_request(req);
819
72246da4
FB		 820 return &req->request;
821}
822
823static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
824 struct usb_request *request)
825{
826 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 827 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 828
68d34c8a 829 dep->allocated_requests--;
2c4cbe6e 830 trace_dwc3_free_request(req);
72246da4
FB		 831 kfree(req);
832}
833
2c78c029
FB		 834static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
835
e49d3cf4
FB		 836static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
837 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
838 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 839{
6b9018d4
FB		 840 struct dwc3 *dwc = dep->dwc;
841 struct usb_gadget *gadget = &dwc->gadget;
842 enum usb_device_speed speed = gadget->speed;
c71fc37c 843
ef966b9d 844 dwc3_ep_inc_enq(dep);
e5ba5ec8 845
f6bafc6a
FB		 846 trb->size = DWC3_TRB_SIZE_LENGTH(length);
847 trb->bpl = lower_32_bits(dma);
848 trb->bph = upper_32_bits(dma);
c71fc37c 849
16e78db7 850 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 851 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 852 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 853 break;
854
855 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 856 if (!node) {
e5ba5ec8 857 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 858
859 if (speed == USB_SPEED_HIGH) {
860 struct usb_ep *ep = &dep->endpoint;
861 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
862 }
863 } else {
e5ba5ec8 864 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 865 }
ca4d44ea
FB		 866
867 /* always enable Interrupt on Missed ISOC */
868 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 869 break;
870
871 case USB_ENDPOINT_XFER_BULK:
872 case USB_ENDPOINT_XFER_INT:
f6bafc6a 873 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 874 break;
875 default:
876 /*
877 * This is only possible with faulty memory because we
878 * checked it already :)
879 */
0a695d4c
FB		 880 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
881 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 882 }
883
ca4d44ea 884 /* always enable Continue on Short Packet */
c9508c8c 885 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 886 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 887
e49d3cf4 888 if (short_not_ok)
c9508c8c
FB		 889 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
890 }
891
e49d3cf4 892 if ((!no_interrupt && !chain) ||
2c78c029 893 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 894 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 895
e5ba5ec8
PA		 896 if (chain)
897 trb->ctrl |= DWC3_TRB_CTRL_CHN;
898
16e78db7 899 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 900 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 901
f6bafc6a 902 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 903
904 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 905}
906
e49d3cf4
FB		 907/**
908 * dwc3_prepare_one_trb - setup one TRB from one request
909 * @dep: endpoint for which this request is prepared
910 * @req: dwc3_request pointer
911 * @chain: should this TRB be chained to the next?
912 * @node: only for isochronous endpoints. First TRB needs different type.
913 */
914static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
915 struct dwc3_request *req, unsigned chain, unsigned node)
916{
917 struct dwc3_trb *trb;
918 unsigned length = req->request.length;
919 unsigned stream_id = req->request.stream_id;
920 unsigned short_not_ok = req->request.short_not_ok;
921 unsigned no_interrupt = req->request.no_interrupt;
922 dma_addr_t dma = req->request.dma;
923
924 trb = &dep->trb_pool[dep->trb_enqueue];
925
926 if (!req->trb) {
927 dwc3_gadget_move_started_request(req);
928 req->trb = trb;
929 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
930 dep->queued_requests++;
931 }
932
933 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
934 stream_id, short_not_ok, no_interrupt);
935}
936
361572b5
JY		 937/**
938 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
939 * @dep: The endpoint with the TRB ring
940 * @index: The index of the current TRB in the ring
941 *
942 * Returns the TRB prior to the one pointed to by the index. If the
943 * index is 0, we will wrap backwards, skip the link TRB, and return
944 * the one just before that.
945 */
946static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
947{
45438a0c 948 u8 tmp = index;
361572b5 949
45438a0c
FB		 950 if (!tmp)
951 tmp = DWC3_TRB_NUM - 1;
361572b5 952
45438a0c 953 return &dep->trb_pool[tmp - 1];
361572b5
JY		 954}
955
c4233573
FB		 956static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
957{
958 struct dwc3_trb *tmp;
f2694a93 959 struct dwc3 *dwc = dep->dwc;
32db3d94 960 u8 trbs_left;
c4233573
FB		 961
962 /*
963 * If enqueue & dequeue are equal than it is either full or empty.
964 *
965 * One way to know for sure is if the TRB right before us has HWO bit
966 * set or not. If it has, then we're definitely full and can't fit any
967 * more transfers in our ring.
968 */
969 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 970 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 971 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
972 "%s No TRBS left\n", dep->name))
361572b5 973 return 0;
c4233573
FB		 974
975 return DWC3_TRB_NUM - 1;
976 }
977
9d7aba77 978 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 979 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 980
9d7aba77
JY		 981 if (dep->trb_dequeue < dep->trb_enqueue)
982 trbs_left--;
983
32db3d94 984 return trbs_left;
c4233573
FB		 985}
986
5ee85d89 987static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 988 struct dwc3_request *req)
5ee85d89 989{
1f512119 990 struct scatterlist *sg = req->sg;
5ee85d89 991 struct scatterlist *s;
5ee85d89
FB		 992 int i;
993
1f512119 994 for_each_sg(sg, s, req->num_pending_sgs, i) {
5ee85d89
FB		 995 unsigned chain = true;
996
4bc48c97 997 if (sg_is_last(s))
5ee85d89
FB		 998 chain = false;
999
84305309 1000 dwc3_prepare_one_trb(dep, req, chain, i);
5ee85d89 1001
7ae7df49 1002 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1003 break;
1004 }
1005}
1006
1007static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1008 struct dwc3_request *req)
5ee85d89 1009{
84305309 1010 dwc3_prepare_one_trb(dep, req, false, 0);
5ee85d89
FB		 1011}
1012
72246da4
FB		 1013/*
1014 * dwc3_prepare_trbs - setup TRBs from requests
1015 * @dep: endpoint for which requests are being prepared
72246da4 1016 *
1d046793
PZ		 1017 * The function goes through the requests list and sets up TRBs for the
1018 * transfers. The function returns once there are no more TRBs available or
1019 * it runs out of requests.
72246da4 1020 */
c4233573 1021static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1022{
68e823e2 1023 struct dwc3_request *req, *n;
72246da4
FB		 1024
1025 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1026
7ae7df49 1027 if (!dwc3_calc_trbs_left(dep))
89bc856e 1028 return;
72246da4 1029
d86c5a67
FB		 1030 /*
1031 * We can get in a situation where there's a request in the started list
1032 * but there weren't enough TRBs to fully kick it in the first time
1033 * around, so it has been waiting for more TRBs to be freed up.
1034 *
1035 * In that case, we should check if we have a request with pending_sgs
1036 * in the started list and prepare TRBs for that request first,
1037 * otherwise we will prepare TRBs completely out of order and that will
1038 * break things.
1039 */
1040 list_for_each_entry(req, &dep->started_list, list) {
1041 if (req->num_pending_sgs > 0)
1042 dwc3_prepare_one_trb_sg(dep, req);
1043
1044 if (!dwc3_calc_trbs_left(dep))
1045 return;
1046 }
1047
aa3342c8 1048 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1049 if (req->num_pending_sgs > 0)
7ae7df49 1050 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1051 else
7ae7df49 1052 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1053
7ae7df49 1054 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1055 return;
72246da4 1056 }
72246da4
FB		 1057}
1058
4fae2e3e 1059static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1060{
1061 struct dwc3_gadget_ep_cmd_params params;
1062 struct dwc3_request *req;
4fae2e3e 1063 int starting;
72246da4
FB		 1064 int ret;
1065 u32 cmd;
1066
4fae2e3e 1067 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1068
4fae2e3e
FB		 1069 dwc3_prepare_trbs(dep);
1070 req = next_request(&dep->started_list);
72246da4
FB		 1071 if (!req) {
1072 dep->flags |= DWC3_EP_PENDING_REQUEST;
1073 return 0;
1074 }
1075
1076 memset(&params, 0, sizeof(params));
72246da4 1077
4fae2e3e 1078 if (starting) {
1877d6c9
PA		 1079 params.param0 = upper_32_bits(req->trb_dma);
1080 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1081 cmd = DWC3_DEPCMD_STARTTRANSFER |
1082 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1083 } else {
b6b1c6db
FB		 1084 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1085 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1086 }
72246da4 1087
2cd4718d 1088 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1089 if (ret < 0) {
72246da4
FB		 1090 /*
1091 * FIXME we need to iterate over the list of requests
1092 * here and stop, unmap, free and del each of the linked
1d046793 1093 * requests instead of what we do now.
72246da4 1094 */
ce3fc8b3
JD		 1095 if (req->trb)
1096 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1097 dep->queued_requests--;
15b8d933 1098 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1099 return ret;
1100 }
1101
1102 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1103
4fae2e3e 1104 if (starting) {
2eb88016 1105 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1106 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1107 }
25b8ff68 1108
72246da4
FB		 1109 return 0;
1110}
1111
6cb2e4e3
FB		 1112static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1113{
1114 u32 reg;
1115
1116 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1117 return DWC3_DSTS_SOFFN(reg);
1118}
1119
d6d6ec7b
PA		 1120static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1121 struct dwc3_ep *dep, u32 cur_uf)
1122{
1123 u32 uf;
1124
aa3342c8 1125 if (list_empty(&dep->pending_list)) {
5eb30ced 1126 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1127 dep->name);
f4a53c55 1128 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1129 return;
1130 }
1131
1132 /* 4 micro frames in the future */
1133 uf = cur_uf + dep->interval * 4;
1134
4fae2e3e 1135 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1136}
1137
1138static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1139 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1140{
1141 u32 cur_uf, mask;
1142
1143 mask = ~(dep->interval - 1);
1144 cur_uf = event->parameters & mask;
1145
1146 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1147}
1148
72246da4
FB		 1149static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1150{
0fc9a1be
FB		 1151 struct dwc3 *dwc = dep->dwc;
1152 int ret;
1153
bb423984 1154 if (!dep->endpoint.desc) {
5eb30ced
FB		 1155 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1156 dep->name);
bb423984
FB		 1157 return -ESHUTDOWN;
1158 }
1159
1160 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1161 &req->request, req->dep->name)) {
5eb30ced
FB		 1162 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1163 dep->name, &req->request, req->dep->name);
bb423984
FB		 1164 return -EINVAL;
1165 }
1166
fc8bb91b
FB		 1167 pm_runtime_get(dwc->dev);
1168
72246da4
FB		 1169 req->request.actual = 0;
1170 req->request.status = -EINPROGRESS;
1171 req->direction = dep->direction;
1172 req->epnum = dep->number;
1173
fe84f522
FB		 1174 trace_dwc3_ep_queue(req);
1175
d64ff406
AB		 1176 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1177 dep->direction);
0fc9a1be
FB		 1178 if (ret)
1179 return ret;
1180
1f512119
FB		 1181 req->sg = req->request.sg;
1182 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1183
aa3342c8 1184 list_add_tail(&req->list, &dep->pending_list);
72246da4 1185
d889c23c
FB		 1186 /*
1187 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1188 * wait for a XferNotReady event so we will know what's the current
1189 * (micro-)frame number.
1190 *
1191 * Without this trick, we are very, very likely gonna get Bus Expiry
1192 * errors which will force us issue EndTransfer command.
1193 */
1194 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1195 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1196 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1197 dwc3_stop_active_transfer(dwc, dep->number, true);
1198 dep->flags = DWC3_EP_ENABLED;
1199 } else {
1200 u32 cur_uf;
1201
1202 cur_uf = __dwc3_gadget_get_frame(dwc);
1203 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1204 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1205 }
08a36b54
FB		 1206 }
1207 return 0;
a0925324 1208 }
72246da4 1209
594e121f
FB		 1210 if (!dwc3_calc_trbs_left(dep))
1211 return 0;
b997ada5 1212
08a36b54 1213 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1214 if (ret == -EBUSY)
1215 ret = 0;
1216
1217 return ret;
72246da4
FB		 1218}
1219
04c03d10
FB		 1220static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1221 struct usb_request *request)
1222{
1223 dwc3_gadget_ep_free_request(ep, request);
1224}
1225
1226static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1227{
1228 struct dwc3_request *req;
1229 struct usb_request *request;
1230 struct usb_ep *ep = &dep->endpoint;
1231
04c03d10
FB		 1232 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1233 if (!request)
1234 return -ENOMEM;
1235
1236 request->length = 0;
1237 request->buf = dwc->zlp_buf;
1238 request->complete = __dwc3_gadget_ep_zlp_complete;
1239
1240 req = to_dwc3_request(request);
1241
1242 return __dwc3_gadget_ep_queue(dep, req);
1243}
1244
72246da4
FB		 1245static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1246 gfp_t gfp_flags)
1247{
1248 struct dwc3_request *req = to_dwc3_request(request);
1249 struct dwc3_ep *dep = to_dwc3_ep(ep);
1250 struct dwc3 *dwc = dep->dwc;
1251
1252 unsigned long flags;
1253
1254 int ret;
1255
fdee4eba 1256 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1257 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1258
1259 /*
1260 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1261 * setting request->zero, instead of doing magic, we will just queue an
1262 * extra usb_request ourselves so that it gets handled the same way as
1263 * any other request.
1264 */
d9261898
JY		 1265 if (ret == 0 && request->zero && request->length &&
1266 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1267 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1268
72246da4
FB		 1269 spin_unlock_irqrestore(&dwc->lock, flags);
1270
1271 return ret;
1272}
1273
1274static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1275 struct usb_request *request)
1276{
1277 struct dwc3_request *req = to_dwc3_request(request);
1278 struct dwc3_request *r = NULL;
1279
1280 struct dwc3_ep *dep = to_dwc3_ep(ep);
1281 struct dwc3 *dwc = dep->dwc;
1282
1283 unsigned long flags;
1284 int ret = 0;
1285
2c4cbe6e
FB		 1286 trace_dwc3_ep_dequeue(req);
1287
72246da4
FB		 1288 spin_lock_irqsave(&dwc->lock, flags);
1289
aa3342c8 1290 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1291 if (r == req)
1292 break;
1293 }
1294
1295 if (r != req) {
aa3342c8 1296 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1297 if (r == req)
1298 break;
1299 }
1300 if (r == req) {
1301 /* wait until it is processed */
b992e681 1302 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1303 goto out1;
72246da4
FB		 1304 }
1305 dev_err(dwc->dev, "request %p was not queued to %s\n",
1306 request, ep->name);
1307 ret = -EINVAL;
1308 goto out0;
1309 }
1310
e8d4e8be 1311out1:
72246da4
FB		 1312 /* giveback the request */
1313 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1314
1315out0:
1316 spin_unlock_irqrestore(&dwc->lock, flags);
1317
1318 return ret;
1319}
1320
7a608559 1321int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1322{
1323 struct dwc3_gadget_ep_cmd_params params;
1324 struct dwc3 *dwc = dep->dwc;
1325 int ret;
1326
5ad02fb8
FB		 1327 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1328 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1329 return -EINVAL;
1330 }
1331
72246da4
FB		 1332 memset(&params, 0x00, sizeof(params));
1333
1334 if (value) {
69450c4d
FB		 1335 struct dwc3_trb *trb;
1336
1337 unsigned transfer_in_flight;
1338 unsigned started;
1339
1340 if (dep->number > 1)
1341 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1342 else
1343 trb = &dwc->ep0_trb[dep->trb_enqueue];
1344
1345 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1346 started = !list_empty(&dep->started_list);
1347
1348 if (!protocol && ((dep->direction && transfer_in_flight) ||
1349 (!dep->direction && started))) {
7a608559
FB		 1350 return -EAGAIN;
1351 }
1352
2cd4718d
FB		 1353 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1354 &params);
72246da4 1355 if (ret)
3f89204b 1356 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1357 dep->name);
1358 else
1359 dep->flags |= DWC3_EP_STALL;
1360 } else {
2cd4718d 1361
50c763f8 1362 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1363 if (ret)
3f89204b 1364 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1365 dep->name);
1366 else
a535d81c 1367 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1368 }
5275455a 1369
72246da4
FB		 1370 return ret;
1371}
1372
1373static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1374{
1375 struct dwc3_ep *dep = to_dwc3_ep(ep);
1376 struct dwc3 *dwc = dep->dwc;
1377
1378 unsigned long flags;
1379
1380 int ret;
1381
1382 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1383 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1384 spin_unlock_irqrestore(&dwc->lock, flags);
1385
1386 return ret;
1387}
1388
1389static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1390{
1391 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1392 struct dwc3 *dwc = dep->dwc;
1393 unsigned long flags;
95aa4e8d 1394 int ret;
72246da4 1395
249a4569 1396 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1397 dep->flags |= DWC3_EP_WEDGE;
1398
08f0d966 1399 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1400 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1401 else
7a608559 1402 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1403 spin_unlock_irqrestore(&dwc->lock, flags);
1404
1405 return ret;
72246da4
FB		 1406}
1407
1408/* -------------------------------------------------------------------------- */
1409
1410static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1411 .bLength = USB_DT_ENDPOINT_SIZE,
1412 .bDescriptorType = USB_DT_ENDPOINT,
1413 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1414};
1415
1416static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1417 .enable = dwc3_gadget_ep0_enable,
1418 .disable = dwc3_gadget_ep0_disable,
1419 .alloc_request = dwc3_gadget_ep_alloc_request,
1420 .free_request = dwc3_gadget_ep_free_request,
1421 .queue = dwc3_gadget_ep0_queue,
1422 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1423 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1424 .set_wedge = dwc3_gadget_ep_set_wedge,
1425};
1426
1427static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1428 .enable = dwc3_gadget_ep_enable,
1429 .disable = dwc3_gadget_ep_disable,
1430 .alloc_request = dwc3_gadget_ep_alloc_request,
1431 .free_request = dwc3_gadget_ep_free_request,
1432 .queue = dwc3_gadget_ep_queue,
1433 .dequeue = dwc3_gadget_ep_dequeue,
1434 .set_halt = dwc3_gadget_ep_set_halt,
1435 .set_wedge = dwc3_gadget_ep_set_wedge,
1436};
1437
1438/* -------------------------------------------------------------------------- */
1439
1440static int dwc3_gadget_get_frame(struct usb_gadget *g)
1441{
1442 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1443
6cb2e4e3 1444 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1445}
1446
218ef7b6 1447static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1448{
d6011f6f 1449 int retries;
72246da4 1450
218ef7b6 1451 int ret;
72246da4
FB		 1452 u32 reg;
1453
72246da4
FB		 1454 u8 link_state;
1455 u8 speed;
1456
72246da4
FB		 1457 /*
1458 * According to the Databook Remote wakeup request should
1459 * be issued only when the device is in early suspend state.
1460 *
1461 * We can check that via USB Link State bits in DSTS register.
1462 */
1463 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1464
1465 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1466 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1467 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1468 return 0;
72246da4
FB		 1469
1470 link_state = DWC3_DSTS_USBLNKST(reg);
1471
1472 switch (link_state) {
1473 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1474 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1475 break;
1476 default:
218ef7b6 1477 return -EINVAL;
72246da4
FB		 1478 }
1479
8598bde7
FB		 1480 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1481 if (ret < 0) {
1482 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1483 return ret;
8598bde7 1484 }
72246da4 1485
802fde98
PZ		 1486 /* Recent versions do this automatically */
1487 if (dwc->revision < DWC3_REVISION_194A) {
1488 /* write zeroes to Link Change Request */
fcc023c7 1489 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1490 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1491 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1492 }
72246da4 1493
1d046793 1494 /* poll until Link State changes to ON */
d6011f6f 1495 retries = 20000;
72246da4 1496
d6011f6f 1497 while (retries--) {
72246da4
FB		 1498 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1499
1500 /* in HS, means ON */
1501 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1502 break;
1503 }
1504
1505 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1506 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1507 return -EINVAL;
72246da4
FB		 1508 }
1509
218ef7b6
FB		 1510 return 0;
1511}
1512
1513static int dwc3_gadget_wakeup(struct usb_gadget *g)
1514{
1515 struct dwc3 *dwc = gadget_to_dwc(g);
1516 unsigned long flags;
1517 int ret;
1518
1519 spin_lock_irqsave(&dwc->lock, flags);
1520 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1521 spin_unlock_irqrestore(&dwc->lock, flags);
1522
1523 return ret;
1524}
1525
1526static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1527 int is_selfpowered)
1528{
1529 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1530 unsigned long flags;
72246da4 1531
249a4569 1532 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1533 g->is_selfpowered = !!is_selfpowered;
249a4569 1534 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1535
1536 return 0;
1537}
1538
7b2a0368 1539static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1540{
1541 u32 reg;
61d58242 1542 u32 timeout = 500;
72246da4 1543
fc8bb91b
FB		 1544 if (pm_runtime_suspended(dwc->dev))
1545 return 0;
1546
72246da4 1547 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1548 if (is_on) {
802fde98
PZ		 1549 if (dwc->revision <= DWC3_REVISION_187A) {
1550 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1551 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1552 }
1553
1554 if (dwc->revision >= DWC3_REVISION_194A)
1555 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1556 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1557
1558 if (dwc->has_hibernation)
1559 reg |= DWC3_DCTL_KEEP_CONNECT;
1560
9fcb3bd8 1561 dwc->pullups_connected = true;
8db7ed15 1562 } else {
72246da4 1563 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1564
1565 if (dwc->has_hibernation && !suspend)
1566 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1567
9fcb3bd8 1568 dwc->pullups_connected = false;
8db7ed15 1569 }
72246da4
FB		 1570
1571 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1572
1573 do {
1574 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1575 reg &= DWC3_DSTS_DEVCTRLHLT;
1576 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1577
1578 if (!timeout)
1579 return -ETIMEDOUT;
72246da4 1580
6f17f74b 1581 return 0;
72246da4
FB		 1582}
1583
1584static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1585{
1586 struct dwc3 *dwc = gadget_to_dwc(g);
1587 unsigned long flags;
6f17f74b 1588 int ret;
72246da4
FB		 1589
1590 is_on = !!is_on;
1591
bb014736
BW		 1592 /*
1593 * Per databook, when we want to stop the gadget, if a control transfer
1594 * is still in process, complete it and get the core into setup phase.
1595 */
1596 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1597 reinit_completion(&dwc->ep0_in_setup);
1598
1599 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1600 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1601 if (ret == 0) {
1602 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1603 return -ETIMEDOUT;
1604 }
1605 }
1606
72246da4 1607 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1608 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1609 spin_unlock_irqrestore(&dwc->lock, flags);
1610
6f17f74b 1611 return ret;
72246da4
FB		 1612}
1613
8698e2ac
FB		 1614static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1615{
1616 u32 reg;
1617
1618 /* Enable all but Start and End of Frame IRQs */
1619 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1620 DWC3_DEVTEN_EVNTOVERFLOWEN |
1621 DWC3_DEVTEN_CMDCMPLTEN |
1622 DWC3_DEVTEN_ERRTICERREN |
1623 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1624 DWC3_DEVTEN_CONNECTDONEEN |
1625 DWC3_DEVTEN_USBRSTEN |
1626 DWC3_DEVTEN_DISCONNEVTEN);
1627
799e9dc8
FB		 1628 if (dwc->revision < DWC3_REVISION_250A)
1629 reg |= DWC3_DEVTEN_ULSTCNGEN;
1630
8698e2ac
FB		 1631 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1632}
1633
1634static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1635{
1636 /* mask all interrupts */
1637 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1638}
1639
1640static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1641static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1642
4e99472b
FB		 1643/**
1644 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1645 * dwc: pointer to our context structure
1646 *
1647 * The following looks like complex but it's actually very simple. In order to
1648 * calculate the number of packets we can burst at once on OUT transfers, we're
1649 * gonna use RxFIFO size.
1650 *
1651 * To calculate RxFIFO size we need two numbers:
1652 * MDWIDTH = size, in bits, of the internal memory bus
1653 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1654 *
1655 * Given these two numbers, the formula is simple:
1656 *
1657 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1658 *
1659 * 24 bytes is for 3x SETUP packets
1660 * 16 bytes is a clock domain crossing tolerance
1661 *
1662 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1663 */
1664static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1665{
1666 u32 ram2_depth;
1667 u32 mdwidth;
1668 u32 nump;
1669 u32 reg;
1670
1671 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1672 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1673
1674 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1675 nump = min_t(u32, nump, 16);
1676
1677 /* update NumP */
1678 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1679 reg &= ~DWC3_DCFG_NUMP_MASK;
1680 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1681 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1682}
1683
d7be2952 1684static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1685{
72246da4 1686 struct dwc3_ep *dep;
72246da4
FB		 1687 int ret = 0;
1688 u32 reg;
1689
cf40b86b
JY		 1690 /*
1691 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1692 * the core supports IMOD, disable it.
1693 */
1694 if (dwc->imod_interval) {
1695 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1696 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1697 } else if (dwc3_has_imod(dwc)) {
1698 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1699 }
1700
72246da4
FB		 1701 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1702 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1703
1704 /**
1705 * WORKAROUND: DWC3 revision < 2.20a have an issue
1706 * which would cause metastability state on Run/Stop
1707 * bit if we try to force the IP to USB2-only mode.
1708 *
1709 * Because of that, we cannot configure the IP to any
1710 * speed other than the SuperSpeed
1711 *
1712 * Refers to:
1713 *
1714 * STAR#9000525659: Clock Domain Crossing on DCTL in
1715 * USB 2.0 Mode
1716 */
f7e846f0 1717 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1718 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1719 } else {
1720 switch (dwc->maximum_speed) {
1721 case USB_SPEED_LOW:
2da9ad76 1722 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1723 break;
1724 case USB_SPEED_FULL:
9418ee15 1725 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1726 break;
1727 case USB_SPEED_HIGH:
2da9ad76 1728 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1729 break;
7580862b 1730 case USB_SPEED_SUPER_PLUS:
2da9ad76 1731 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1732 break;
f7e846f0 1733 default:
77966eb8
JY		 1734 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1735 dwc->maximum_speed);
1736 /* fall through */
1737 case USB_SPEED_SUPER:
1738 reg |= DWC3_DCFG_SUPERSPEED;
1739 break;
f7e846f0
FB		 1740 }
1741 }
72246da4
FB		 1742 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1743
2a58f9c1
FB		 1744 /*
1745 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1746 * field instead of letting dwc3 itself calculate that automatically.
1747 *
1748 * This way, we maximize the chances that we'll be able to get several
1749 * bursts of data without going through any sort of endpoint throttling.
1750 */
1751 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1752 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1753 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1754
4e99472b
FB		 1755 dwc3_gadget_setup_nump(dwc);
1756
72246da4
FB		 1757 /* Start with SuperSpeed Default */
1758 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1759
1760 dep = dwc->eps[0];
39ebb05c 1761 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1762 if (ret) {
1763 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1764 goto err0;
72246da4
FB		 1765 }
1766
1767 dep = dwc->eps[1];
39ebb05c 1768 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1769 if (ret) {
1770 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1771 goto err1;
72246da4
FB		 1772 }
1773
1774 /* begin to receive SETUP packets */
c7fcdeb2 1775 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1776 dwc3_ep0_out_start(dwc);
1777
8698e2ac
FB		 1778 dwc3_gadget_enable_irq(dwc);
1779
72246da4
FB		 1780 return 0;
1781
b0d7ffd4 1782err1:
d7be2952 1783 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1784
1785err0:
72246da4
FB		 1786 return ret;
1787}
1788
d7be2952
FB		 1789static int dwc3_gadget_start(struct usb_gadget *g,
1790 struct usb_gadget_driver *driver)
72246da4
FB		 1791{
1792 struct dwc3 *dwc = gadget_to_dwc(g);
1793 unsigned long flags;
d7be2952 1794 int ret = 0;
8698e2ac 1795 int irq;
72246da4 1796
9522def4 1797 irq = dwc->irq_gadget;
d7be2952
FB		 1798 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1799 IRQF_SHARED, "dwc3", dwc->ev_buf);
1800 if (ret) {
1801 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1802 irq, ret);
1803 goto err0;
1804 }
1805
72246da4 1806 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1807 if (dwc->gadget_driver) {
1808 dev_err(dwc->dev, "%s is already bound to %s\n",
1809 dwc->gadget.name,
1810 dwc->gadget_driver->driver.name);
1811 ret = -EBUSY;
1812 goto err1;
1813 }
1814
1815 dwc->gadget_driver = driver;
1816
fc8bb91b
FB		 1817 if (pm_runtime_active(dwc->dev))
1818 __dwc3_gadget_start(dwc);
1819
d7be2952
FB		 1820 spin_unlock_irqrestore(&dwc->lock, flags);
1821
1822 return 0;
1823
1824err1:
1825 spin_unlock_irqrestore(&dwc->lock, flags);
1826 free_irq(irq, dwc);
1827
1828err0:
1829 return ret;
1830}
72246da4 1831
d7be2952
FB		 1832static void __dwc3_gadget_stop(struct dwc3 *dwc)
1833{
8698e2ac 1834 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1835 __dwc3_gadget_ep_disable(dwc->eps[0]);
1836 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1837}
72246da4 1838
d7be2952
FB		 1839static int dwc3_gadget_stop(struct usb_gadget *g)
1840{
1841 struct dwc3 *dwc = gadget_to_dwc(g);
1842 unsigned long flags;
76a638f8 1843 int epnum;
72246da4 1844
d7be2952 1845 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1846
1847 if (pm_runtime_suspended(dwc->dev))
1848 goto out;
1849
d7be2952 1850 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1851
1852 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1853 struct dwc3_ep *dep = dwc->eps[epnum];
1854
1855 if (!dep)
1856 continue;
1857
1858 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1859 continue;
1860
1861 wait_event_lock_irq(dep->wait_end_transfer,
1862 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1863 dwc->lock);
1864 }
1865
1866out:
d7be2952 1867 dwc->gadget_driver = NULL;
72246da4
FB		 1868 spin_unlock_irqrestore(&dwc->lock, flags);
1869
3f308d17 1870 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1871
72246da4
FB		 1872 return 0;
1873}
802fde98 1874
72246da4
FB		 1875static const struct usb_gadget_ops dwc3_gadget_ops = {
1876 .get_frame = dwc3_gadget_get_frame,
1877 .wakeup = dwc3_gadget_wakeup,
1878 .set_selfpowered = dwc3_gadget_set_selfpowered,
1879 .pullup = dwc3_gadget_pullup,
1880 .udc_start = dwc3_gadget_start,
1881 .udc_stop = dwc3_gadget_stop,
1882};
1883
1884/* -------------------------------------------------------------------------- */
1885
6a1e3ef4
FB		 1886static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1887 u8 num, u32 direction)
72246da4
FB		 1888{
1889 struct dwc3_ep *dep;
6a1e3ef4 1890 u8 i;
72246da4 1891
6a1e3ef4 1892 for (i = 0; i < num; i++) {
d07fa665 1893 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1894
72246da4 1895 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1896 if (!dep)
72246da4 1897 return -ENOMEM;
72246da4
FB		 1898
1899 dep->dwc = dwc;
1900 dep->number = epnum;
9aa62ae4 1901 dep->direction = !!direction;
2eb88016 1902 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1903 dwc->eps[epnum] = dep;
1904
1905 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1906 (epnum & 1) ? "in" : "out");
6a1e3ef4 1907
72246da4 1908 dep->endpoint.name = dep->name;
39ebb05c
JY		 1909
1910 if (!(dep->number > 1)) {
1911 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
1912 dep->endpoint.comp_desc = NULL;
1913 }
1914
74674cbf 1915 spin_lock_init(&dep->lock);
72246da4
FB		 1916
1917 if (epnum == 0 || epnum == 1) {
e117e742 1918 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1919 dep->endpoint.maxburst = 1;
72246da4
FB		 1920 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1921 if (!epnum)
1922 dwc->gadget.ep0 = &dep->endpoint;
1923 } else {
1924 int ret;
1925
e117e742 1926 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1927 dep->endpoint.max_streams = 15;
72246da4
FB		 1928 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1929 list_add_tail(&dep->endpoint.ep_list,
1930 &dwc->gadget.ep_list);
1931
1932 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1933 if (ret)
72246da4 1934 return ret;
72246da4 1935 }
25b8ff68 1936
a474d3b7
RB		 1937 if (epnum == 0 || epnum == 1) {
1938 dep->endpoint.caps.type_control = true;
1939 } else {
1940 dep->endpoint.caps.type_iso = true;
1941 dep->endpoint.caps.type_bulk = true;
1942 dep->endpoint.caps.type_int = true;
1943 }
1944
1945 dep->endpoint.caps.dir_in = !!direction;
1946 dep->endpoint.caps.dir_out = !direction;
1947
aa3342c8
FB		 1948 INIT_LIST_HEAD(&dep->pending_list);
1949 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1950 }
1951
1952 return 0;
1953}
1954
6a1e3ef4
FB		 1955static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1956{
1957 int ret;
1958
1959 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1960
1961 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1962 if (ret < 0) {
5eb30ced 1963 dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
6a1e3ef4
FB		 1964 return ret;
1965 }
1966
1967 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1968 if (ret < 0) {
5eb30ced 1969 dev_err(dwc->dev, "failed to initialize IN endpoints\n");
6a1e3ef4
FB		 1970 return ret;
1971 }
1972
1973 return 0;
1974}
1975
72246da4
FB		 1976static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1977{
1978 struct dwc3_ep *dep;
1979 u8 epnum;
1980
1981 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1982 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1983 if (!dep)
1984 continue;
5bf8fae3
GC		 1985 /*
1986 * Physical endpoints 0 and 1 are special; they form the
1987 * bi-directional USB endpoint 0.
1988 *
1989 * For those two physical endpoints, we don't allocate a TRB
1990 * pool nor do we add them the endpoints list. Due to that, we
1991 * shouldn't do these two operations otherwise we would end up
1992 * with all sorts of bugs when removing dwc3.ko.
1993 */
1994 if (epnum != 0 && epnum != 1) {
1995 dwc3_free_trb_pool(dep);
72246da4 1996 list_del(&dep->endpoint.ep_list);
5bf8fae3 1997 }
72246da4
FB		 1998
1999 kfree(dep);
2000 }
2001}
2002
72246da4 2003/* -------------------------------------------------------------------------- */
e5caff68 2004
e5ba5ec8
PA		 2005static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2006 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2007 const struct dwc3_event_depevt *event, int status,
2008 int chain)
72246da4 2009{
72246da4
FB		 2010 unsigned int count;
2011 unsigned int s_pkt = 0;
d6d6ec7b 2012 unsigned int trb_status;
72246da4 2013
dc55c67e 2014 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2015
2016 if (req->trb == trb)
2017 dep->queued_requests--;
2018
2c4cbe6e
FB		 2019 trace_dwc3_complete_trb(dep, trb);
2020
e5b36ae2
FB		 2021 /*
2022 * If we're in the middle of series of chained TRBs and we
2023 * receive a short transfer along the way, DWC3 will skip
2024 * through all TRBs including the last TRB in the chain (the
2025 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2026 * bit and SW has to do it manually.
2027 *
2028 * We're going to do that here to avoid problems of HW trying
2029 * to use bogus TRBs for transfers.
2030 */
2031 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2032 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2033
e5ba5ec8 2034 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
a0ad85ae 2035 return 1;
e5b36ae2 2036
e5ba5ec8 2037 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2038 req->remaining += count;
e5ba5ec8
PA		 2039
2040 if (dep->direction) {
2041 if (count) {
2042 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2043 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2044 /*
2045 * If missed isoc occurred and there is
2046 * no request queued then issue END
2047 * TRANSFER, so that core generates
2048 * next xfernotready and we will issue
2049 * a fresh START TRANSFER.
2050 * If there are still queued request
2051 * then wait, do not issue either END
2052 * or UPDATE TRANSFER, just attach next
aa3342c8 2053 * request in pending_list during
e5ba5ec8
PA		 2054 * giveback.If any future queued request
2055 * is successfully transferred then we
2056 * will issue UPDATE TRANSFER for all
aa3342c8 2057 * request in the pending_list.
e5ba5ec8
PA		 2058 */
2059 dep->flags |= DWC3_EP_MISSED_ISOC;
2060 } else {
2061 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2062 dep->name);
2063 status = -ECONNRESET;
2064 }
2065 } else {
2066 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2067 }
2068 } else {
2069 if (count && (event->status & DEPEVT_STATUS_SHORT))
2070 s_pkt = 1;
2071 }
2072
7c705dfe 2073 if (s_pkt && !chain)
e5ba5ec8 2074 return 1;
f99f53f2 2075
e5ba5ec8
PA		 2076 if ((event->status & DEPEVT_STATUS_IOC) &&
2077 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2078 return 1;
f99f53f2 2079
e5ba5ec8
PA		 2080 return 0;
2081}
2082
2083static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2084 const struct dwc3_event_depevt *event, int status)
2085{
31162af4 2086 struct dwc3_request *req, *n;
e5ba5ec8 2087 struct dwc3_trb *trb;
d6e10bf2 2088 bool ioc = false;
e62c5bc5 2089 int ret = 0;
e5ba5ec8 2090
31162af4 2091 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2092 unsigned length;
e5b36ae2
FB		 2093 int chain;
2094
1f512119
FB		 2095 length = req->request.length;
2096 chain = req->num_pending_sgs > 0;
31162af4 2097 if (chain) {
1f512119 2098 struct scatterlist *sg = req->sg;
31162af4 2099 struct scatterlist *s;
1f512119 2100 unsigned int pending = req->num_pending_sgs;
31162af4 2101 unsigned int i;
c7de5734 2102
1f512119 2103 for_each_sg(sg, s, pending, i) {
31162af4 2104 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2105
7282c4ef
FB		 2106 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2107 break;
2108
1f512119
FB		 2109 req->sg = sg_next(s);
2110 req->num_pending_sgs--;
2111
31162af4
FB		 2112 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2113 event, status, chain);
1f512119
FB		 2114 if (ret)
2115 break;
31162af4
FB		 2116 }
2117 } else {
737f1ae2 2118 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2119 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2120 event, status, chain);
31162af4 2121 }
d115d705 2122
e62c5bc5 2123 req->request.actual = length - req->remaining;
1f512119 2124
ff377ae4 2125 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2126 return __dwc3_gadget_kick_transfer(dep, 0);
2127
d115d705 2128 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2129
d6e10bf2
AB		 2130 if (ret) {
2131 if ((event->status & DEPEVT_STATUS_IOC) &&
2132 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2133 ioc = true;
72246da4 2134 break;
d6e10bf2 2135 }
31162af4 2136 }
72246da4 2137
4cb42217
FB		 2138 /*
2139 * Our endpoint might get disabled by another thread during
2140 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2141 * early on so DWC3_EP_BUSY flag gets cleared
2142 */
2143 if (!dep->endpoint.desc)
2144 return 1;
2145
cdc359dd 2146 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2147 list_empty(&dep->started_list)) {
2148 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2149 /*
2150 * If there is no entry in request list then do
2151 * not issue END TRANSFER now. Just set PENDING
2152 * flag, so that END TRANSFER is issued when an
2153 * entry is added into request list.
2154 */
2155 dep->flags = DWC3_EP_PENDING_REQUEST;
2156 } else {
b992e681 2157 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2158 dep->flags = DWC3_EP_ENABLED;
2159 }
7efea86c
PA		 2160 return 1;
2161 }
2162
d6e10bf2
AB		 2163 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2164 return 0;
2165
72246da4
FB		 2166 return 1;
2167}
2168
2169static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2170 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2171{
2172 unsigned status = 0;
2173 int clean_busy;
e18b7975
FB		 2174 u32 is_xfer_complete;
2175
2176 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2177
2178 if (event->status & DEPEVT_STATUS_BUSERR)
2179 status = -ECONNRESET;
2180
1d046793 2181 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2182 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2183 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2184 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2185
2186 /*
2187 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2188 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2189 */
2190 if (dwc->revision < DWC3_REVISION_183A) {
2191 u32 reg;
2192 int i;
2193
2194 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2195 dep = dwc->eps[i];
fae2b904
FB		 2196
2197 if (!(dep->flags & DWC3_EP_ENABLED))
2198 continue;
2199
aa3342c8 2200 if (!list_empty(&dep->started_list))
fae2b904
FB		 2201 return;
2202 }
2203
2204 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2205 reg |= dwc->u1u2;
2206 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2207
2208 dwc->u1u2 = 0;
2209 }
8a1a9c9e 2210
4cb42217
FB		 2211 /*
2212 * Our endpoint might get disabled by another thread during
2213 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2214 * early on so DWC3_EP_BUSY flag gets cleared
2215 */
2216 if (!dep->endpoint.desc)
2217 return;
2218
e6e709b7 2219 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2220 int ret;
2221
4fae2e3e 2222 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2223 if (!ret || ret == -EBUSY)
2224 return;
2225 }
72246da4
FB		 2226}
2227
72246da4
FB		 2228static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2229 const struct dwc3_event_depevt *event)
2230{
2231 struct dwc3_ep *dep;
2232 u8 epnum = event->endpoint_number;
76a638f8 2233 u8 cmd;
72246da4
FB		 2234
2235 dep = dwc->eps[epnum];
2236
d7fd41c6
JD		 2237 if (!(dep->flags & DWC3_EP_ENABLED)) {
2238 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2239 return;
2240
2241 /* Handle only EPCMDCMPLT when EP disabled */
2242 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2243 return;
2244 }
3336abb5 2245
72246da4
FB		 2246 if (epnum == 0 || epnum == 1) {
2247 dwc3_ep0_interrupt(dwc, event);
2248 return;
2249 }
2250
2251 switch (event->endpoint_event) {
2252 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2253 dep->resource_index = 0;
c2df85ca 2254
16e78db7 2255 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2256 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2257 return;
2258 }
2259
029d97ff 2260 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2261 break;
2262 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2263 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2264 break;
2265 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2266 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2267 dwc3_gadget_start_isoc(dwc, dep, event);
2268 } else {
2269 int ret;
2270
4fae2e3e 2271 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2272 if (!ret || ret == -EBUSY)
2273 return;
72246da4
FB		 2274 }
2275
879631aa
FB		 2276 break;
2277 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2278 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2279 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2280 dep->name);
2281 return;
2282 }
72246da4 2283 break;
72246da4 2284 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2285 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2286
2287 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2288 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2289 wake_up(&dep->wait_end_transfer);
2290 }
2291 break;
2292 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2293 break;
2294 }
2295}
2296
2297static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2298{
2299 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2300 spin_unlock(&dwc->lock);
2301 dwc->gadget_driver->disconnect(&dwc->gadget);
2302 spin_lock(&dwc->lock);
2303 }
2304}
2305
bc5ba2e0
FB		 2306static void dwc3_suspend_gadget(struct dwc3 *dwc)
2307{
73a30bfc 2308 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2309 spin_unlock(&dwc->lock);
2310 dwc->gadget_driver->suspend(&dwc->gadget);
2311 spin_lock(&dwc->lock);
2312 }
2313}
2314
2315static void dwc3_resume_gadget(struct dwc3 *dwc)
2316{
73a30bfc 2317 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2318 spin_unlock(&dwc->lock);
2319 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2320 spin_lock(&dwc->lock);
8e74475b
FB		 2321 }
2322}
2323
2324static void dwc3_reset_gadget(struct dwc3 *dwc)
2325{
2326 if (!dwc->gadget_driver)
2327 return;
2328
2329 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2330 spin_unlock(&dwc->lock);
2331 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2332 spin_lock(&dwc->lock);
2333 }
2334}
2335
b992e681 2336static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2337{
2338 struct dwc3_ep *dep;
2339 struct dwc3_gadget_ep_cmd_params params;
2340 u32 cmd;
2341 int ret;
2342
2343 dep = dwc->eps[epnum];
2344
76a638f8
BW		 2345 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2346 !dep->resource_index)
3daf74d7
PA		 2347 return;
2348
57911504
PA		 2349 /*
2350 * NOTICE: We are violating what the Databook says about the
2351 * EndTransfer command. Ideally we would _always_ wait for the
2352 * EndTransfer Command Completion IRQ, but that's causing too
2353 * much trouble synchronizing between us and gadget driver.
2354 *
2355 * We have discussed this with the IP Provider and it was
2356 * suggested to giveback all requests here, but give HW some
2357 * extra time to synchronize with the interconnect. We're using
dc93b41a 2358 * an arbitrary 100us delay for that.
57911504
PA		 2359 *
2360 * Note also that a similar handling was tested by Synopsys
2361 * (thanks a lot Paul) and nothing bad has come out of it.
2362 * In short, what we're doing is:
2363 *
2364 * - Issue EndTransfer WITH CMDIOC bit set
2365 * - Wait 100us
06281d46
JY		 2366 *
2367 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2368 * supports a mode to work around the above limitation. The
2369 * software can poll the CMDACT bit in the DEPCMD register
2370 * after issuing a EndTransfer command. This mode is enabled
2371 * by writing GUCTL2[14]. This polling is already done in the
2372 * dwc3_send_gadget_ep_cmd() function so if the mode is
2373 * enabled, the EndTransfer command will have completed upon
2374 * returning from this function and we don't need to delay for
2375 * 100us.
2376 *
2377 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2378 */
2379
3daf74d7 2380 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2381 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2382 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2383 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2384 memset(&params, 0, sizeof(params));
2cd4718d 2385 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2386 WARN_ON_ONCE(ret);
b4996a86 2387 dep->resource_index = 0;
041d81f4 2388 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2389
76a638f8
BW		 2390 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2391 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2392 udelay(100);
76a638f8 2393 }
72246da4
FB		 2394}
2395
72246da4
FB		 2396static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2397{
2398 u32 epnum;
2399
2400 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2401 struct dwc3_ep *dep;
72246da4
FB		 2402 int ret;
2403
2404 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2405 if (!dep)
2406 continue;
72246da4
FB		 2407
2408 if (!(dep->flags & DWC3_EP_STALL))
2409 continue;
2410
2411 dep->flags &= ~DWC3_EP_STALL;
2412
50c763f8 2413 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2414 WARN_ON_ONCE(ret);
2415 }
2416}
2417
2418static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2419{
c4430a26
FB		 2420 int reg;
2421
72246da4
FB		 2422 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2423 reg &= ~DWC3_DCTL_INITU1ENA;
2424 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2425
2426 reg &= ~DWC3_DCTL_INITU2ENA;
2427 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2428
72246da4
FB		 2429 dwc3_disconnect_gadget(dwc);
2430
2431 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2432 dwc->setup_packet_pending = false;
06a374ed 2433 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2434
2435 dwc->connected = false;
72246da4
FB		 2436}
2437
72246da4
FB		 2438static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2439{
2440 u32 reg;
2441
fc8bb91b
FB		 2442 dwc->connected = true;
2443
df62df56
FB		 2444 /*
2445 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2446 * would cause a missing Disconnect Event if there's a
2447 * pending Setup Packet in the FIFO.
2448 *
2449 * There's no suggested workaround on the official Bug
2450 * report, which states that "unless the driver/application
2451 * is doing any special handling of a disconnect event,
2452 * there is no functional issue".
2453 *
2454 * Unfortunately, it turns out that we _do_ some special
2455 * handling of a disconnect event, namely complete all
2456 * pending transfers, notify gadget driver of the
2457 * disconnection, and so on.
2458 *
2459 * Our suggested workaround is to follow the Disconnect
2460 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2461 * flag. Such flag gets set whenever we have a SETUP_PENDING
2462 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2463 * same endpoint.
2464 *
2465 * Refers to:
2466 *
2467 * STAR#9000466709: RTL: Device : Disconnect event not
2468 * generated if setup packet pending in FIFO
2469 */
2470 if (dwc->revision < DWC3_REVISION_188A) {
2471 if (dwc->setup_packet_pending)
2472 dwc3_gadget_disconnect_interrupt(dwc);
2473 }
2474
8e74475b 2475 dwc3_reset_gadget(dwc);
72246da4
FB		 2476
2477 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2478 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2479 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2480 dwc->test_mode = false;
72246da4
FB		 2481 dwc3_clear_stall_all_ep(dwc);
2482
2483 /* Reset device address to zero */
2484 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2485 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2486 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2487}
2488
72246da4
FB		 2489static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2490{
72246da4
FB		 2491 struct dwc3_ep *dep;
2492 int ret;
2493 u32 reg;
2494 u8 speed;
2495
72246da4
FB		 2496 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2497 speed = reg & DWC3_DSTS_CONNECTSPD;
2498 dwc->speed = speed;
2499
5fb6fdaf
JY		 2500 /*
2501 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2502 * each time on Connect Done.
2503 *
2504 * Currently we always use the reset value. If any platform
2505 * wants to set this to a different value, we need to add a
2506 * setting and update GCTL.RAMCLKSEL here.
2507 */
72246da4
FB		 2508
2509 switch (speed) {
2da9ad76 2510 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2511 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2512 dwc->gadget.ep0->maxpacket = 512;
2513 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2514 break;
2da9ad76 2515 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2516 /*
2517 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2518 * would cause a missing USB3 Reset event.
2519 *
2520 * In such situations, we should force a USB3 Reset
2521 * event by calling our dwc3_gadget_reset_interrupt()
2522 * routine.
2523 *
2524 * Refers to:
2525 *
2526 * STAR#9000483510: RTL: SS : USB3 reset event may
2527 * not be generated always when the link enters poll
2528 */
2529 if (dwc->revision < DWC3_REVISION_190A)
2530 dwc3_gadget_reset_interrupt(dwc);
2531
72246da4
FB		 2532 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2533 dwc->gadget.ep0->maxpacket = 512;
2534 dwc->gadget.speed = USB_SPEED_SUPER;
2535 break;
2da9ad76 2536 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2537 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2538 dwc->gadget.ep0->maxpacket = 64;
2539 dwc->gadget.speed = USB_SPEED_HIGH;
2540 break;
9418ee15 2541 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2542 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2543 dwc->gadget.ep0->maxpacket = 64;
2544 dwc->gadget.speed = USB_SPEED_FULL;
2545 break;
2da9ad76 2546 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2547 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2548 dwc->gadget.ep0->maxpacket = 8;
2549 dwc->gadget.speed = USB_SPEED_LOW;
2550 break;
2551 }
2552
2b758350
PA		 2553 /* Enable USB2 LPM Capability */
2554
ee5cd41c 2555 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2556 (speed != DWC3_DSTS_SUPERSPEED) &&
2557 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2558 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2559 reg |= DWC3_DCFG_LPM_CAP;
2560 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2561
2562 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2563 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2564
460d098c 2565 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2566
80caf7d2
HR		 2567 /*
2568 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2569 * DCFG.LPMCap is set, core responses with an ACK and the
2570 * BESL value in the LPM token is less than or equal to LPM
2571 * NYET threshold.
2572 */
2573 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2574 && dwc->has_lpm_erratum,
9165dabb 2575 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2576
2577 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2578 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2579
356363bf
FB		 2580 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2581 } else {
2582 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2583 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2584 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2585 }
2586
72246da4 2587 dep = dwc->eps[0];
39ebb05c 2588 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2589 if (ret) {
2590 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2591 return;
2592 }
2593
2594 dep = dwc->eps[1];
39ebb05c 2595 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2596 if (ret) {
2597 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2598 return;
2599 }
2600
2601 /*
2602 * Configure PHY via GUSB3PIPECTLn if required.
2603 *
2604 * Update GTXFIFOSIZn
2605 *
2606 * In both cases reset values should be sufficient.
2607 */
2608}
2609
2610static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2611{
72246da4
FB		 2612 /*
2613 * TODO take core out of low power mode when that's
2614 * implemented.
2615 */
2616
ad14d4e0
JL		 2617 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2618 spin_unlock(&dwc->lock);
2619 dwc->gadget_driver->resume(&dwc->gadget);
2620 spin_lock(&dwc->lock);
2621 }
72246da4
FB		 2622}
2623
2624static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2625 unsigned int evtinfo)
2626{
fae2b904 2627 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2628 unsigned int pwropt;
2629
2630 /*
2631 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2632 * Hibernation mode enabled which would show up when device detects
2633 * host-initiated U3 exit.
2634 *
2635 * In that case, device will generate a Link State Change Interrupt
2636 * from U3 to RESUME which is only necessary if Hibernation is
2637 * configured in.
2638 *
2639 * There are no functional changes due to such spurious event and we
2640 * just need to ignore it.
2641 *
2642 * Refers to:
2643 *
2644 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2645 * operational mode
2646 */
2647 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2648 if ((dwc->revision < DWC3_REVISION_250A) &&
2649 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2650 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2651 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2652 return;
2653 }
2654 }
fae2b904
FB		 2655
2656 /*
2657 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2658 * on the link partner, the USB session might do multiple entry/exit
2659 * of low power states before a transfer takes place.
2660 *
2661 * Due to this problem, we might experience lower throughput. The
2662 * suggested workaround is to disable DCTL[12:9] bits if we're
2663 * transitioning from U1/U2 to U0 and enable those bits again
2664 * after a transfer completes and there are no pending transfers
2665 * on any of the enabled endpoints.
2666 *
2667 * This is the first half of that workaround.
2668 *
2669 * Refers to:
2670 *
2671 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2672 * core send LGO_Ux entering U0
2673 */
2674 if (dwc->revision < DWC3_REVISION_183A) {
2675 if (next == DWC3_LINK_STATE_U0) {
2676 u32 u1u2;
2677 u32 reg;
2678
2679 switch (dwc->link_state) {
2680 case DWC3_LINK_STATE_U1:
2681 case DWC3_LINK_STATE_U2:
2682 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2683 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2684 | DWC3_DCTL_ACCEPTU2ENA
2685 | DWC3_DCTL_INITU1ENA
2686 | DWC3_DCTL_ACCEPTU1ENA);
2687
2688 if (!dwc->u1u2)
2689 dwc->u1u2 = reg & u1u2;
2690
2691 reg &= ~u1u2;
2692
2693 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2694 break;
2695 default:
2696 /* do nothing */
2697 break;
2698 }
2699 }
2700 }
2701
bc5ba2e0
FB		 2702 switch (next) {
2703 case DWC3_LINK_STATE_U1:
2704 if (dwc->speed == USB_SPEED_SUPER)
2705 dwc3_suspend_gadget(dwc);
2706 break;
2707 case DWC3_LINK_STATE_U2:
2708 case DWC3_LINK_STATE_U3:
2709 dwc3_suspend_gadget(dwc);
2710 break;
2711 case DWC3_LINK_STATE_RESUME:
2712 dwc3_resume_gadget(dwc);
2713 break;
2714 default:
2715 /* do nothing */
2716 break;
2717 }
2718
e57ebc1d 2719 dwc->link_state = next;
72246da4
FB		 2720}
2721
72704f87
BW		 2722static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2723 unsigned int evtinfo)
2724{
2725 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2726
2727 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2728 dwc3_suspend_gadget(dwc);
2729
2730 dwc->link_state = next;
2731}
2732
e1dadd3b
FB		 2733static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2734 unsigned int evtinfo)
2735{
2736 unsigned int is_ss = evtinfo & BIT(4);
2737
2738 /**
2739 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2740 * have a known issue which can cause USB CV TD.9.23 to fail
2741 * randomly.
2742 *
2743 * Because of this issue, core could generate bogus hibernation
2744 * events which SW needs to ignore.
2745 *
2746 * Refers to:
2747 *
2748 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2749 * Device Fallback from SuperSpeed
2750 */
2751 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2752 return;
2753
2754 /* enter hibernation here */
2755}
2756
72246da4
FB		 2757static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2758 const struct dwc3_event_devt *event)
2759{
2760 switch (event->type) {
2761 case DWC3_DEVICE_EVENT_DISCONNECT:
2762 dwc3_gadget_disconnect_interrupt(dwc);
2763 break;
2764 case DWC3_DEVICE_EVENT_RESET:
2765 dwc3_gadget_reset_interrupt(dwc);
2766 break;
2767 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2768 dwc3_gadget_conndone_interrupt(dwc);
2769 break;
2770 case DWC3_DEVICE_EVENT_WAKEUP:
2771 dwc3_gadget_wakeup_interrupt(dwc);
2772 break;
e1dadd3b
FB		 2773 case DWC3_DEVICE_EVENT_HIBER_REQ:
2774 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2775 "unexpected hibernation event\n"))
2776 break;
2777
2778 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2779 break;
72246da4
FB		 2780 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2781 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2782 break;
2783 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2784 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2785 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2786 /*
2787 * Ignore suspend event until the gadget enters into
2788 * USB_STATE_CONFIGURED state.
2789 */
2790 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2791 dwc3_gadget_suspend_interrupt(dwc,
2792 event->event_info);
2793 }
72246da4
FB		 2794 break;
2795 case DWC3_DEVICE_EVENT_SOF:
72246da4 2796 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2797 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2798 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2799 break;
2800 default:
e9f2aa87 2801 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2802 }
2803}
2804
2805static void dwc3_process_event_entry(struct dwc3 *dwc,
2806 const union dwc3_event *event)
2807{
43c96be1 2808 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2809
72246da4
FB		 2810 /* Endpoint IRQ, handle it and return early */
2811 if (event->type.is_devspec == 0) {
2812 /* depevt */
2813 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2814 }
2815
2816 switch (event->type.type) {
2817 case DWC3_EVENT_TYPE_DEV:
2818 dwc3_gadget_interrupt(dwc, &event->devt);
2819 break;
2820 /* REVISIT what to do with Carkit and I2C events ? */
2821 default:
2822 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2823 }
2824}
2825
dea520a4 2826static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2827{
dea520a4 2828 struct dwc3 *dwc = evt->dwc;
b15a762f 2829 irqreturn_t ret = IRQ_NONE;
f42f2447 2830 int left;
e8adfc30 2831 u32 reg;
b15a762f 2832
f42f2447 2833 left = evt->count;
b15a762f 2834
f42f2447
FB		 2835 if (!(evt->flags & DWC3_EVENT_PENDING))
2836 return IRQ_NONE;
b15a762f 2837
f42f2447
FB		 2838 while (left > 0) {
2839 union dwc3_event event;
b15a762f 2840
ebbb2d59 2841 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2842
f42f2447 2843 dwc3_process_event_entry(dwc, &event);
b15a762f 2844
f42f2447
FB		 2845 /*
2846 * FIXME we wrap around correctly to the next entry as
2847 * almost all entries are 4 bytes in size. There is one
2848 * entry which has 12 bytes which is a regular entry
2849 * followed by 8 bytes data. ATM I don't know how
2850 * things are organized if we get next to the a
2851 * boundary so I worry about that once we try to handle
2852 * that.
2853 */
caefe6c7 2854 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2855 left -= 4;
f42f2447 2856 }
b15a762f 2857
f42f2447
FB		 2858 evt->count = 0;
2859 evt->flags &= ~DWC3_EVENT_PENDING;
2860 ret = IRQ_HANDLED;
b15a762f 2861
f42f2447 2862 /* Unmask interrupt */
660e9bde 2863 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2864 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2865 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2866
cf40b86b
JY		 2867 if (dwc->imod_interval) {
2868 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2869 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2870 }
2871
f42f2447
FB		 2872 return ret;
2873}
e8adfc30 2874
dea520a4 2875static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2876{
dea520a4
FB		 2877 struct dwc3_event_buffer *evt = _evt;
2878 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2879 unsigned long flags;
f42f2447 2880 irqreturn_t ret = IRQ_NONE;
f42f2447 2881
e5f68b4a 2882 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2883 ret = dwc3_process_event_buf(evt);
e5f68b4a 2884 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2885
2886 return ret;
2887}
2888
dea520a4 2889static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2890{
dea520a4 2891 struct dwc3 *dwc = evt->dwc;
ebbb2d59 2892 u32 amount;
72246da4 2893 u32 count;
e8adfc30 2894 u32 reg;
72246da4 2895
fc8bb91b
FB		 2896 if (pm_runtime_suspended(dwc->dev)) {
2897 pm_runtime_get(dwc->dev);
2898 disable_irq_nosync(dwc->irq_gadget);
2899 dwc->pending_events = true;
2900 return IRQ_HANDLED;
2901 }
2902
660e9bde 2903 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2904 count &= DWC3_GEVNTCOUNT_MASK;
2905 if (!count)
2906 return IRQ_NONE;
2907
b15a762f
FB		 2908 evt->count = count;
2909 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2910
e8adfc30 2911 /* Mask interrupt */
660e9bde 2912 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2913 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2914 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2915
ebbb2d59
JY		 2916 amount = min(count, evt->length - evt->lpos);
2917 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
2918
2919 if (amount < count)
2920 memcpy(evt->cache, evt->buf, count - amount);
2921
65aca320
JY		 2922 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2923
b15a762f 2924 return IRQ_WAKE_THREAD;
72246da4
FB		 2925}
2926
dea520a4 2927static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2928{
dea520a4 2929 struct dwc3_event_buffer *evt = _evt;
72246da4 2930
dea520a4 2931 return dwc3_check_event_buf(evt);
72246da4
FB		 2932}
2933
6db3812e
FB		 2934static int dwc3_gadget_get_irq(struct dwc3 *dwc)
2935{
2936 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2937 int irq;
2938
2939 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2940 if (irq > 0)
2941 goto out;
2942
2943 if (irq == -EPROBE_DEFER)
2944 goto out;
2945
2946 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2947 if (irq > 0)
2948 goto out;
2949
2950 if (irq == -EPROBE_DEFER)
2951 goto out;
2952
2953 irq = platform_get_irq(dwc3_pdev, 0);
2954 if (irq > 0)
2955 goto out;
2956
2957 if (irq != -EPROBE_DEFER)
2958 dev_err(dwc->dev, "missing peripheral IRQ\n");
2959
2960 if (!irq)
2961 irq = -EINVAL;
2962
2963out:
2964 return irq;
2965}
2966
72246da4
FB		 2967/**
2968 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2969 * @dwc: pointer to our controller context structure
72246da4
FB		 2970 *
2971 * Returns 0 on success otherwise negative errno.
2972 */
41ac7b3a 2973int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2974{
6db3812e
FB		 2975 int ret;
2976 int irq;
9522def4 2977
6db3812e
FB		 2978 irq = dwc3_gadget_get_irq(dwc);
2979 if (irq < 0) {
2980 ret = irq;
2981 goto err0;
9522def4
RQ		 2982 }
2983
2984 dwc->irq_gadget = irq;
72246da4 2985
d64ff406 2986 dwc->ctrl_req = dma_alloc_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 2987 &dwc->ctrl_req_addr, GFP_KERNEL);
2988 if (!dwc->ctrl_req) {
2989 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2990 ret = -ENOMEM;
2991 goto err0;
2992 }
2993
d64ff406
AB		 2994 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
2995 sizeof(*dwc->ep0_trb) * 2,
2996 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 2997 if (!dwc->ep0_trb) {
2998 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2999 ret = -ENOMEM;
3000 goto err1;
3001 }
3002
3ef35faf 3003 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 3004 if (!dwc->setup_buf) {
72246da4
FB		 3005 ret = -ENOMEM;
3006 goto err2;
3007 }
3008
d64ff406 3009 dwc->ep0_bounce = dma_alloc_coherent(dwc->sysdev,
3ef35faf
FB		 3010 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3011 GFP_KERNEL);
5812b1c2
FB		 3012 if (!dwc->ep0_bounce) {
3013 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3014 ret = -ENOMEM;
3015 goto err3;
3016 }
3017
04c03d10
FB		 3018 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3019 if (!dwc->zlp_buf) {
3020 ret = -ENOMEM;
3021 goto err4;
3022 }
3023
905dc04e
FB		 3024 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3025 &dwc->bounce_addr, GFP_KERNEL);
3026 if (!dwc->bounce) {
3027 ret = -ENOMEM;
3028 goto err5;
3029 }
3030
bb014736
BW		 3031 init_completion(&dwc->ep0_in_setup);
3032
72246da4 3033 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3034 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3035 dwc->gadget.sg_supported = true;
72246da4 3036 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3037 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3038
b9e51b2b
BM		 3039 /*
3040 * FIXME We might be setting max_speed to <SUPER, however versions
3041 * <2.20a of dwc3 have an issue with metastability (documented
3042 * elsewhere in this driver) which tells us we can't set max speed to
3043 * anything lower than SUPER.
3044 *
3045 * Because gadget.max_speed is only used by composite.c and function
3046 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3047 * to happen so we avoid sending SuperSpeed Capability descriptor
3048 * together with our BOS descriptor as that could confuse host into
3049 * thinking we can handle super speed.
3050 *
3051 * Note that, in fact, we won't even support GetBOS requests when speed
3052 * is less than super speed because we don't have means, yet, to tell
3053 * composite.c that we are USB 2.0 + LPM ECN.
3054 */
3055 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3056 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3057 dwc->revision);
3058
3059 dwc->gadget.max_speed = dwc->maximum_speed;
3060
a4b9d94b
DC		 3061 /*
3062 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3063 * on ep out.
3064 */
3065 dwc->gadget.quirk_ep_out_aligned_size = true;
3066
72246da4
FB		 3067 /*
3068 * REVISIT: Here we should clear all pending IRQs to be
3069 * sure we're starting from a well known location.
3070 */
3071
3072 ret = dwc3_gadget_init_endpoints(dwc);
3073 if (ret)
905dc04e 3074 goto err6;
72246da4 3075
72246da4
FB		 3076 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3077 if (ret) {
3078 dev_err(dwc->dev, "failed to register udc\n");
905dc04e 3079 goto err6;
72246da4
FB		 3080 }
3081
3082 return 0;
905dc04e
FB		 3083err6:
3084 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3085 dwc->bounce_addr);
72246da4 3086
04c03d10
FB		 3087err5:
3088 kfree(dwc->zlp_buf);
3089
5812b1c2 3090err4:
e1f80467 3091 dwc3_gadget_free_endpoints(dwc);
d64ff406 3092 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3093 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3094
72246da4 3095err3:
0fc9a1be 3096 kfree(dwc->setup_buf);
72246da4
FB		 3097
3098err2:
d64ff406 3099 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3100 dwc->ep0_trb, dwc->ep0_trb_addr);
3101
3102err1:
d64ff406 3103 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3104 dwc->ctrl_req, dwc->ctrl_req_addr);
3105
3106err0:
3107 return ret;
3108}
3109
7415f17c
FB		 3110/* -------------------------------------------------------------------------- */
3111
72246da4
FB		 3112void dwc3_gadget_exit(struct dwc3 *dwc)
3113{
72246da4 3114 usb_del_gadget_udc(&dwc->gadget);
72246da4 3115
72246da4
FB		 3116 dwc3_gadget_free_endpoints(dwc);
3117
905dc04e
FB		 3118 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3119 dwc->bounce_addr);
d64ff406 3120 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3121 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3122
0fc9a1be 3123 kfree(dwc->setup_buf);
04c03d10 3124 kfree(dwc->zlp_buf);
72246da4 3125
d64ff406 3126 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3127 dwc->ep0_trb, dwc->ep0_trb_addr);
3128
d64ff406 3129 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4 3130 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3131}
7415f17c 3132
0b0231aa 3133int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3134{
9f8a67b6
FB		 3135 int ret;
3136
9772b47a
RQ		 3137 if (!dwc->gadget_driver)
3138 return 0;
3139
9f8a67b6
FB		 3140 ret = dwc3_gadget_run_stop(dwc, false, false);
3141 if (ret < 0)
3142 return ret;
7415f17c 3143
9f8a67b6
FB		 3144 dwc3_disconnect_gadget(dwc);
3145 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3146
3147 return 0;
3148}
3149
3150int dwc3_gadget_resume(struct dwc3 *dwc)
3151{
7415f17c
FB		 3152 int ret;
3153
9772b47a
RQ		 3154 if (!dwc->gadget_driver)
3155 return 0;
3156
9f8a67b6
FB		 3157 ret = __dwc3_gadget_start(dwc);
3158 if (ret < 0)
7415f17c
FB		 3159 goto err0;
3160
9f8a67b6
FB		 3161 ret = dwc3_gadget_run_stop(dwc, true, false);
3162 if (ret < 0)
7415f17c
FB		 3163 goto err1;
3164
7415f17c
FB		 3165 return 0;
3166
3167err1:
9f8a67b6 3168 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3169
3170err0:
3171 return ret;
3172}
fc8bb91b
FB		 3173
3174void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3175{
3176 if (dwc->pending_events) {
3177 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3178 dwc->pending_events = false;
3179 enable_irq(dwc->irq_gadget);
3180 }
3181}
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