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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
33 | #include "core.h" | |
34 | #include "gadget.h" | |
35 | #include "io.h" | |
36 | ||
04a9bfcd FB |
37 | /** |
38 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
39 | * @dwc: pointer to our context structure | |
40 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
41 | * | |
42 | * Caller should take care of locking. This function will | |
43 | * return 0 on success or -EINVAL if wrong Test Selector | |
44 | * is passed | |
45 | */ | |
46 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
47 | { | |
48 | u32 reg; | |
49 | ||
50 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
51 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
52 | ||
53 | switch (mode) { | |
54 | case TEST_J: | |
55 | case TEST_K: | |
56 | case TEST_SE0_NAK: | |
57 | case TEST_PACKET: | |
58 | case TEST_FORCE_EN: | |
59 | reg |= mode << 1; | |
60 | break; | |
61 | default: | |
62 | return -EINVAL; | |
63 | } | |
64 | ||
65 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
911f1f88 PZ |
70 | /** |
71 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
72 | * @dwc: pointer to our context structure | |
73 | * | |
74 | * Caller should take care of locking. This function will | |
75 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
76 | */ | |
77 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
78 | { | |
79 | u32 reg; | |
80 | ||
81 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
82 | ||
83 | return DWC3_DSTS_USBLNKST(reg); | |
84 | } | |
85 | ||
8598bde7 FB |
86 | /** |
87 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
88 | * @dwc: pointer to our context structure | |
89 | * @state: the state to put link into | |
90 | * | |
91 | * Caller should take care of locking. This function will | |
aee63e3c | 92 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
93 | */ |
94 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
95 | { | |
aee63e3c | 96 | int retries = 10000; |
8598bde7 FB |
97 | u32 reg; |
98 | ||
802fde98 PZ |
99 | /* |
100 | * Wait until device controller is ready. Only applies to 1.94a and | |
101 | * later RTL. | |
102 | */ | |
103 | if (dwc->revision >= DWC3_REVISION_194A) { | |
104 | while (--retries) { | |
105 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
106 | if (reg & DWC3_DSTS_DCNRD) | |
107 | udelay(5); | |
108 | else | |
109 | break; | |
110 | } | |
111 | ||
112 | if (retries <= 0) | |
113 | return -ETIMEDOUT; | |
114 | } | |
115 | ||
8598bde7 FB |
116 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
117 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
118 | ||
119 | /* set requested state */ | |
120 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
121 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
122 | ||
802fde98 PZ |
123 | /* |
124 | * The following code is racy when called from dwc3_gadget_wakeup, | |
125 | * and is not needed, at least on newer versions | |
126 | */ | |
127 | if (dwc->revision >= DWC3_REVISION_194A) | |
128 | return 0; | |
129 | ||
8598bde7 | 130 | /* wait for a change in DSTS */ |
aed430e5 | 131 | retries = 10000; |
8598bde7 FB |
132 | while (--retries) { |
133 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
134 | ||
8598bde7 FB |
135 | if (DWC3_DSTS_USBLNKST(reg) == state) |
136 | return 0; | |
137 | ||
aee63e3c | 138 | udelay(5); |
8598bde7 FB |
139 | } |
140 | ||
141 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
142 | ||
143 | return -ETIMEDOUT; | |
144 | } | |
145 | ||
457e84b6 FB |
146 | /** |
147 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
148 | * @dwc: pointer to our context structure | |
149 | * | |
150 | * This function will a best effort FIFO allocation in order | |
151 | * to improve FIFO usage and throughput, while still allowing | |
152 | * us to enable as many endpoints as possible. | |
153 | * | |
154 | * Keep in mind that this operation will be highly dependent | |
155 | * on the configured size for RAM1 - which contains TxFifo -, | |
156 | * the amount of endpoints enabled on coreConsultant tool, and | |
157 | * the width of the Master Bus. | |
158 | * | |
159 | * In the ideal world, we would always be able to satisfy the | |
160 | * following equation: | |
161 | * | |
162 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
163 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
164 | * | |
165 | * Unfortunately, due to many variables that's not always the case. | |
166 | */ | |
167 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
168 | { | |
169 | int last_fifo_depth = 0; | |
170 | int ram1_depth; | |
171 | int fifo_size; | |
172 | int mdwidth; | |
173 | int num; | |
174 | ||
175 | if (!dwc->needs_fifo_resize) | |
176 | return 0; | |
177 | ||
178 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
179 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
180 | ||
181 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
182 | mdwidth >>= 3; | |
183 | ||
184 | /* | |
185 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
186 | * for each enabled endpoint, later patches will come to | |
187 | * improve this algorithm so that we better use the internal | |
188 | * FIFO space | |
189 | */ | |
190 | for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { | |
191 | struct dwc3_ep *dep = dwc->eps[num]; | |
192 | int fifo_number = dep->number >> 1; | |
2e81c36a | 193 | int mult = 1; |
457e84b6 FB |
194 | int tmp; |
195 | ||
196 | if (!(dep->number & 1)) | |
197 | continue; | |
198 | ||
199 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
200 | continue; | |
201 | ||
16e78db7 IS |
202 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
203 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
204 | mult = 3; |
205 | ||
206 | /* | |
207 | * REVISIT: the following assumes we will always have enough | |
208 | * space available on the FIFO RAM for all possible use cases. | |
209 | * Make sure that's true somehow and change FIFO allocation | |
210 | * accordingly. | |
211 | * | |
212 | * If we have Bulk or Isochronous endpoints, we want | |
213 | * them to be able to be very, very fast. So we're giving | |
214 | * those endpoints a fifo_size which is enough for 3 full | |
215 | * packets | |
216 | */ | |
217 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
218 | tmp += mdwidth; |
219 | ||
220 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 221 | |
457e84b6 FB |
222 | fifo_size |= (last_fifo_depth << 16); |
223 | ||
224 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
225 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
226 | ||
227 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), | |
228 | fifo_size); | |
229 | ||
230 | last_fifo_depth += (fifo_size & 0xffff); | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
72246da4 FB |
236 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
237 | int status) | |
238 | { | |
239 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 240 | int i; |
72246da4 FB |
241 | |
242 | if (req->queued) { | |
e5ba5ec8 PA |
243 | i = 0; |
244 | do { | |
eeb720fb | 245 | dep->busy_slot++; |
e5ba5ec8 PA |
246 | /* |
247 | * Skip LINK TRB. We can't use req->trb and check for | |
248 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
249 | * just completed (not the LINK TRB). | |
250 | */ | |
251 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
252 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 253 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
254 | dep->busy_slot++; |
255 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 256 | req->queued = false; |
72246da4 FB |
257 | } |
258 | list_del(&req->list); | |
eeb720fb | 259 | req->trb = NULL; |
72246da4 FB |
260 | |
261 | if (req->request.status == -EINPROGRESS) | |
262 | req->request.status = status; | |
263 | ||
0416e494 PA |
264 | if (dwc->ep0_bounced && dep->number == 0) |
265 | dwc->ep0_bounced = false; | |
266 | else | |
267 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
268 | req->direction); | |
72246da4 FB |
269 | |
270 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
271 | req, dep->name, req->request.actual, | |
272 | req->request.length, status); | |
273 | ||
274 | spin_unlock(&dwc->lock); | |
0fc9a1be | 275 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
276 | spin_lock(&dwc->lock); |
277 | } | |
278 | ||
279 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
280 | { | |
281 | switch (cmd) { | |
282 | case DWC3_DEPCMD_DEPSTARTCFG: | |
283 | return "Start New Configuration"; | |
284 | case DWC3_DEPCMD_ENDTRANSFER: | |
285 | return "End Transfer"; | |
286 | case DWC3_DEPCMD_UPDATETRANSFER: | |
287 | return "Update Transfer"; | |
288 | case DWC3_DEPCMD_STARTTRANSFER: | |
289 | return "Start Transfer"; | |
290 | case DWC3_DEPCMD_CLEARSTALL: | |
291 | return "Clear Stall"; | |
292 | case DWC3_DEPCMD_SETSTALL: | |
293 | return "Set Stall"; | |
802fde98 PZ |
294 | case DWC3_DEPCMD_GETEPSTATE: |
295 | return "Get Endpoint State"; | |
72246da4 FB |
296 | case DWC3_DEPCMD_SETTRANSFRESOURCE: |
297 | return "Set Endpoint Transfer Resource"; | |
298 | case DWC3_DEPCMD_SETEPCONFIG: | |
299 | return "Set Endpoint Configuration"; | |
300 | default: | |
301 | return "UNKNOWN command"; | |
302 | } | |
303 | } | |
304 | ||
b09bb642 FB |
305 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
306 | { | |
307 | u32 timeout = 500; | |
308 | u32 reg; | |
309 | ||
310 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
311 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
312 | ||
313 | do { | |
314 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
315 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
316 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
317 | DWC3_DGCMD_STATUS(reg)); | |
318 | return 0; | |
319 | } | |
320 | ||
321 | /* | |
322 | * We can't sleep here, because it's also called from | |
323 | * interrupt context. | |
324 | */ | |
325 | timeout--; | |
326 | if (!timeout) | |
327 | return -ETIMEDOUT; | |
328 | udelay(1); | |
329 | } while (1); | |
330 | } | |
331 | ||
72246da4 FB |
332 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
333 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
334 | { | |
335 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 336 | u32 timeout = 500; |
72246da4 FB |
337 | u32 reg; |
338 | ||
339 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", | |
340 | dep->name, | |
dc1c70a7 FB |
341 | dwc3_gadget_ep_cmd_string(cmd), params->param0, |
342 | params->param1, params->param2); | |
72246da4 | 343 | |
dc1c70a7 FB |
344 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
345 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
346 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
347 | |
348 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
349 | do { | |
350 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
351 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
352 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
353 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
354 | return 0; |
355 | } | |
356 | ||
357 | /* | |
72246da4 FB |
358 | * We can't sleep here, because it is also called from |
359 | * interrupt context. | |
360 | */ | |
361 | timeout--; | |
362 | if (!timeout) | |
363 | return -ETIMEDOUT; | |
364 | ||
61d58242 | 365 | udelay(1); |
72246da4 FB |
366 | } while (1); |
367 | } | |
368 | ||
369 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 370 | struct dwc3_trb *trb) |
72246da4 | 371 | { |
c439ef87 | 372 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
373 | |
374 | return dep->trb_pool_dma + offset; | |
375 | } | |
376 | ||
377 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
378 | { | |
379 | struct dwc3 *dwc = dep->dwc; | |
380 | ||
381 | if (dep->trb_pool) | |
382 | return 0; | |
383 | ||
384 | if (dep->number == 0 || dep->number == 1) | |
385 | return 0; | |
386 | ||
387 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
388 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
389 | &dep->trb_pool_dma, GFP_KERNEL); | |
390 | if (!dep->trb_pool) { | |
391 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
392 | dep->name); | |
393 | return -ENOMEM; | |
394 | } | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
400 | { | |
401 | struct dwc3 *dwc = dep->dwc; | |
402 | ||
403 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
404 | dep->trb_pool, dep->trb_pool_dma); | |
405 | ||
406 | dep->trb_pool = NULL; | |
407 | dep->trb_pool_dma = 0; | |
408 | } | |
409 | ||
410 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
411 | { | |
412 | struct dwc3_gadget_ep_cmd_params params; | |
413 | u32 cmd; | |
414 | ||
415 | memset(¶ms, 0x00, sizeof(params)); | |
416 | ||
417 | if (dep->number != 1) { | |
418 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
419 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
420 | if (dep->number > 1) { |
421 | if (dwc->start_config_issued) | |
422 | return 0; | |
423 | dwc->start_config_issued = true; | |
72246da4 | 424 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 425 | } |
72246da4 FB |
426 | |
427 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 434 | const struct usb_endpoint_descriptor *desc, |
4b345c9a FB |
435 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
436 | bool ignore) | |
72246da4 FB |
437 | { |
438 | struct dwc3_gadget_ep_cmd_params params; | |
439 | ||
440 | memset(¶ms, 0x00, sizeof(params)); | |
441 | ||
dc1c70a7 | 442 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
443 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
444 | ||
445 | /* Burst size is only needed in SuperSpeed mode */ | |
446 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
447 | u32 burst = dep->endpoint.maxburst - 1; | |
448 | ||
449 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
450 | } | |
72246da4 | 451 | |
4b345c9a FB |
452 | if (ignore) |
453 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
454 | ||
dc1c70a7 FB |
455 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
456 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 457 | |
18b7ede5 | 458 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
459 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
460 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
461 | dep->stream_capable = true; |
462 | } | |
463 | ||
72246da4 | 464 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 465 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
466 | |
467 | /* | |
468 | * We are doing 1:1 mapping for endpoints, meaning | |
469 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
470 | * so on. We consider the direction bit as part of the physical | |
471 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
472 | */ | |
dc1c70a7 | 473 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
474 | |
475 | /* | |
476 | * We must use the lower 16 TX FIFOs even though | |
477 | * HW might have more | |
478 | */ | |
479 | if (dep->direction) | |
dc1c70a7 | 480 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
481 | |
482 | if (desc->bInterval) { | |
dc1c70a7 | 483 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
484 | dep->interval = 1 << (desc->bInterval - 1); |
485 | } | |
486 | ||
487 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
488 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
489 | } | |
490 | ||
491 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
492 | { | |
493 | struct dwc3_gadget_ep_cmd_params params; | |
494 | ||
495 | memset(¶ms, 0x00, sizeof(params)); | |
496 | ||
dc1c70a7 | 497 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
498 | |
499 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
500 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
501 | } | |
502 | ||
503 | /** | |
504 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
505 | * @dep: endpoint to be initialized | |
506 | * @desc: USB Endpoint Descriptor | |
507 | * | |
508 | * Caller should take care of locking | |
509 | */ | |
510 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 511 | const struct usb_endpoint_descriptor *desc, |
4b345c9a FB |
512 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
513 | bool ignore) | |
72246da4 FB |
514 | { |
515 | struct dwc3 *dwc = dep->dwc; | |
516 | u32 reg; | |
517 | int ret = -ENOMEM; | |
518 | ||
ff62d6b6 FB |
519 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); |
520 | ||
72246da4 FB |
521 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
522 | ret = dwc3_gadget_start_config(dwc, dep); | |
523 | if (ret) | |
524 | return ret; | |
525 | } | |
526 | ||
4b345c9a | 527 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore); |
72246da4 FB |
528 | if (ret) |
529 | return ret; | |
530 | ||
531 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
532 | struct dwc3_trb *trb_st_hw; |
533 | struct dwc3_trb *trb_link; | |
72246da4 FB |
534 | |
535 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
536 | if (ret) | |
537 | return ret; | |
538 | ||
16e78db7 | 539 | dep->endpoint.desc = desc; |
c90bfaec | 540 | dep->comp_desc = comp_desc; |
72246da4 FB |
541 | dep->type = usb_endpoint_type(desc); |
542 | dep->flags |= DWC3_EP_ENABLED; | |
543 | ||
544 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
545 | reg |= DWC3_DALEPENA_EP(dep->number); | |
546 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
547 | ||
548 | if (!usb_endpoint_xfer_isoc(desc)) | |
549 | return 0; | |
550 | ||
551 | memset(&trb_link, 0, sizeof(trb_link)); | |
552 | ||
1d046793 | 553 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
554 | trb_st_hw = &dep->trb_pool[0]; |
555 | ||
f6bafc6a | 556 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
72246da4 | 557 | |
f6bafc6a FB |
558 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
559 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
560 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
561 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
562 | } |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
624407f9 SAS |
567 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); |
568 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) | |
72246da4 FB |
569 | { |
570 | struct dwc3_request *req; | |
571 | ||
ea53b882 | 572 | if (!list_empty(&dep->req_queued)) { |
624407f9 SAS |
573 | dwc3_stop_active_transfer(dwc, dep->number); |
574 | ||
57911504 | 575 | /* - giveback all requests to gadget driver */ |
1591633e PA |
576 | while (!list_empty(&dep->req_queued)) { |
577 | req = next_request(&dep->req_queued); | |
578 | ||
579 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
580 | } | |
ea53b882 FB |
581 | } |
582 | ||
72246da4 FB |
583 | while (!list_empty(&dep->request_list)) { |
584 | req = next_request(&dep->request_list); | |
585 | ||
624407f9 | 586 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 587 | } |
72246da4 FB |
588 | } |
589 | ||
590 | /** | |
591 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
592 | * @dep: the endpoint to disable | |
593 | * | |
624407f9 SAS |
594 | * This function also removes requests which are currently processed ny the |
595 | * hardware and those which are not yet scheduled. | |
596 | * Caller should take care of locking. | |
72246da4 | 597 | */ |
72246da4 FB |
598 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
599 | { | |
600 | struct dwc3 *dwc = dep->dwc; | |
601 | u32 reg; | |
602 | ||
624407f9 | 603 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
604 | |
605 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
606 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
607 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
608 | ||
879631aa | 609 | dep->stream_capable = false; |
f9c56cdd | 610 | dep->endpoint.desc = NULL; |
c90bfaec | 611 | dep->comp_desc = NULL; |
72246da4 | 612 | dep->type = 0; |
879631aa | 613 | dep->flags = 0; |
72246da4 FB |
614 | |
615 | return 0; | |
616 | } | |
617 | ||
618 | /* -------------------------------------------------------------------------- */ | |
619 | ||
620 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
621 | const struct usb_endpoint_descriptor *desc) | |
622 | { | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
627 | { | |
628 | return -EINVAL; | |
629 | } | |
630 | ||
631 | /* -------------------------------------------------------------------------- */ | |
632 | ||
633 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
634 | const struct usb_endpoint_descriptor *desc) | |
635 | { | |
636 | struct dwc3_ep *dep; | |
637 | struct dwc3 *dwc; | |
638 | unsigned long flags; | |
639 | int ret; | |
640 | ||
641 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
642 | pr_debug("dwc3: invalid parameters\n"); | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
646 | if (!desc->wMaxPacketSize) { | |
647 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
651 | dep = to_dwc3_ep(ep); | |
652 | dwc = dep->dwc; | |
653 | ||
c6f83f38 FB |
654 | if (dep->flags & DWC3_EP_ENABLED) { |
655 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
656 | dep->name); | |
657 | return 0; | |
658 | } | |
659 | ||
72246da4 FB |
660 | switch (usb_endpoint_type(desc)) { |
661 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 662 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
663 | break; |
664 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 665 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
666 | break; |
667 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 668 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
669 | break; |
670 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 671 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
672 | break; |
673 | default: | |
674 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
675 | } | |
676 | ||
72246da4 | 677 | spin_lock_irqsave(&dwc->lock, flags); |
4b345c9a | 678 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false); |
72246da4 FB |
679 | spin_unlock_irqrestore(&dwc->lock, flags); |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
684 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
685 | { | |
686 | struct dwc3_ep *dep; | |
687 | struct dwc3 *dwc; | |
688 | unsigned long flags; | |
689 | int ret; | |
690 | ||
691 | if (!ep) { | |
692 | pr_debug("dwc3: invalid parameters\n"); | |
693 | return -EINVAL; | |
694 | } | |
695 | ||
696 | dep = to_dwc3_ep(ep); | |
697 | dwc = dep->dwc; | |
698 | ||
699 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
700 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
701 | dep->name); | |
702 | return 0; | |
703 | } | |
704 | ||
705 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
706 | dep->number >> 1, | |
707 | (dep->number & 1) ? "in" : "out"); | |
708 | ||
709 | spin_lock_irqsave(&dwc->lock, flags); | |
710 | ret = __dwc3_gadget_ep_disable(dep); | |
711 | spin_unlock_irqrestore(&dwc->lock, flags); | |
712 | ||
713 | return ret; | |
714 | } | |
715 | ||
716 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
717 | gfp_t gfp_flags) | |
718 | { | |
719 | struct dwc3_request *req; | |
720 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
721 | struct dwc3 *dwc = dep->dwc; | |
722 | ||
723 | req = kzalloc(sizeof(*req), gfp_flags); | |
724 | if (!req) { | |
725 | dev_err(dwc->dev, "not enough memory\n"); | |
726 | return NULL; | |
727 | } | |
728 | ||
729 | req->epnum = dep->number; | |
730 | req->dep = dep; | |
72246da4 FB |
731 | |
732 | return &req->request; | |
733 | } | |
734 | ||
735 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
736 | struct usb_request *request) | |
737 | { | |
738 | struct dwc3_request *req = to_dwc3_request(request); | |
739 | ||
740 | kfree(req); | |
741 | } | |
742 | ||
c71fc37c FB |
743 | /** |
744 | * dwc3_prepare_one_trb - setup one TRB from one request | |
745 | * @dep: endpoint for which this request is prepared | |
746 | * @req: dwc3_request pointer | |
747 | */ | |
68e823e2 | 748 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 749 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 750 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 751 | { |
eeb720fb | 752 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 753 | struct dwc3_trb *trb; |
c71fc37c | 754 | |
eeb720fb FB |
755 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
756 | dep->name, req, (unsigned long long) dma, | |
757 | length, last ? " last" : "", | |
758 | chain ? " chain" : ""); | |
759 | ||
c71fc37c | 760 | /* Skip the LINK-TRB on ISOC */ |
915e202a | 761 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && |
16e78db7 | 762 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
915e202a PA |
763 | dep->free_slot++; |
764 | ||
765 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 766 | |
eeb720fb FB |
767 | if (!req->trb) { |
768 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
769 | req->trb = trb; |
770 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 771 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 772 | } |
c71fc37c | 773 | |
e5ba5ec8 PA |
774 | dep->free_slot++; |
775 | ||
f6bafc6a FB |
776 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
777 | trb->bpl = lower_32_bits(dma); | |
778 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 779 | |
16e78db7 | 780 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 781 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 782 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
783 | break; |
784 | ||
785 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
786 | if (!node) |
787 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
788 | else | |
789 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c FB |
790 | break; |
791 | ||
792 | case USB_ENDPOINT_XFER_BULK: | |
793 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 794 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
795 | break; |
796 | default: | |
797 | /* | |
798 | * This is only possible with faulty memory because we | |
799 | * checked it already :) | |
800 | */ | |
801 | BUG(); | |
802 | } | |
803 | ||
f3af3651 FB |
804 | if (!req->request.no_interrupt && !chain) |
805 | trb->ctrl |= DWC3_TRB_CTRL_IOC; | |
806 | ||
16e78db7 | 807 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
808 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
809 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
810 | } else if (last) { |
811 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 812 | } |
c71fc37c | 813 | |
e5ba5ec8 PA |
814 | if (chain) |
815 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
816 | ||
16e78db7 | 817 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 818 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 819 | |
f6bafc6a | 820 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
821 | } |
822 | ||
72246da4 FB |
823 | /* |
824 | * dwc3_prepare_trbs - setup TRBs from requests | |
825 | * @dep: endpoint for which requests are being prepared | |
826 | * @starting: true if the endpoint is idle and no requests are queued. | |
827 | * | |
1d046793 PZ |
828 | * The function goes through the requests list and sets up TRBs for the |
829 | * transfers. The function returns once there are no more TRBs available or | |
830 | * it runs out of requests. | |
72246da4 | 831 | */ |
68e823e2 | 832 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 833 | { |
68e823e2 | 834 | struct dwc3_request *req, *n; |
72246da4 | 835 | u32 trbs_left; |
8d62cd65 | 836 | u32 max; |
c71fc37c | 837 | unsigned int last_one = 0; |
72246da4 FB |
838 | |
839 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
840 | ||
841 | /* the first request must not be queued */ | |
842 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 843 | |
8d62cd65 | 844 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 845 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
846 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
847 | if (trbs_left > max) | |
848 | trbs_left = max; | |
849 | } | |
850 | ||
72246da4 | 851 | /* |
1d046793 PZ |
852 | * If busy & slot are equal than it is either full or empty. If we are |
853 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
854 | * full and don't do anything |
855 | */ | |
856 | if (!trbs_left) { | |
857 | if (!starting) | |
68e823e2 | 858 | return; |
72246da4 FB |
859 | trbs_left = DWC3_TRB_NUM; |
860 | /* | |
861 | * In case we start from scratch, we queue the ISOC requests | |
862 | * starting from slot 1. This is done because we use ring | |
863 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 864 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
865 | * after the first request so we start at slot 1 and have |
866 | * 7 requests proceed before we hit the first IOC. | |
867 | * Other transfer types don't use the ring buffer and are | |
868 | * processed from the first TRB until the last one. Since we | |
869 | * don't wrap around we have to start at the beginning. | |
870 | */ | |
16e78db7 | 871 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
872 | dep->busy_slot = 1; |
873 | dep->free_slot = 1; | |
874 | } else { | |
875 | dep->busy_slot = 0; | |
876 | dep->free_slot = 0; | |
877 | } | |
878 | } | |
879 | ||
880 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 881 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 882 | return; |
72246da4 FB |
883 | |
884 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
885 | unsigned length; |
886 | dma_addr_t dma; | |
e5ba5ec8 | 887 | last_one = false; |
72246da4 | 888 | |
eeb720fb FB |
889 | if (req->request.num_mapped_sgs > 0) { |
890 | struct usb_request *request = &req->request; | |
891 | struct scatterlist *sg = request->sg; | |
892 | struct scatterlist *s; | |
893 | int i; | |
72246da4 | 894 | |
eeb720fb FB |
895 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
896 | unsigned chain = true; | |
72246da4 | 897 | |
eeb720fb FB |
898 | length = sg_dma_len(s); |
899 | dma = sg_dma_address(s); | |
72246da4 | 900 | |
1d046793 PZ |
901 | if (i == (request->num_mapped_sgs - 1) || |
902 | sg_is_last(s)) { | |
e5ba5ec8 PA |
903 | if (list_is_last(&req->list, |
904 | &dep->request_list)) | |
905 | last_one = true; | |
eeb720fb FB |
906 | chain = false; |
907 | } | |
72246da4 | 908 | |
eeb720fb FB |
909 | trbs_left--; |
910 | if (!trbs_left) | |
911 | last_one = true; | |
72246da4 | 912 | |
eeb720fb FB |
913 | if (last_one) |
914 | chain = false; | |
72246da4 | 915 | |
eeb720fb | 916 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 917 | last_one, chain, i); |
72246da4 | 918 | |
eeb720fb FB |
919 | if (last_one) |
920 | break; | |
921 | } | |
72246da4 | 922 | } else { |
eeb720fb FB |
923 | dma = req->request.dma; |
924 | length = req->request.length; | |
925 | trbs_left--; | |
72246da4 | 926 | |
eeb720fb FB |
927 | if (!trbs_left) |
928 | last_one = 1; | |
879631aa | 929 | |
eeb720fb FB |
930 | /* Is this the last request? */ |
931 | if (list_is_last(&req->list, &dep->request_list)) | |
932 | last_one = 1; | |
72246da4 | 933 | |
eeb720fb | 934 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 935 | last_one, false, 0); |
72246da4 | 936 | |
eeb720fb FB |
937 | if (last_one) |
938 | break; | |
72246da4 | 939 | } |
72246da4 | 940 | } |
72246da4 FB |
941 | } |
942 | ||
943 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
944 | int start_new) | |
945 | { | |
946 | struct dwc3_gadget_ep_cmd_params params; | |
947 | struct dwc3_request *req; | |
948 | struct dwc3 *dwc = dep->dwc; | |
949 | int ret; | |
950 | u32 cmd; | |
951 | ||
952 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
953 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
954 | return -EBUSY; | |
955 | } | |
956 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
957 | ||
958 | /* | |
959 | * If we are getting here after a short-out-packet we don't enqueue any | |
960 | * new requests as we try to set the IOC bit only on the last request. | |
961 | */ | |
962 | if (start_new) { | |
963 | if (list_empty(&dep->req_queued)) | |
964 | dwc3_prepare_trbs(dep, start_new); | |
965 | ||
966 | /* req points to the first request which will be sent */ | |
967 | req = next_request(&dep->req_queued); | |
968 | } else { | |
68e823e2 FB |
969 | dwc3_prepare_trbs(dep, start_new); |
970 | ||
72246da4 | 971 | /* |
1d046793 | 972 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 973 | */ |
68e823e2 | 974 | req = next_request(&dep->req_queued); |
72246da4 FB |
975 | } |
976 | if (!req) { | |
977 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
978 | return 0; | |
979 | } | |
980 | ||
981 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 982 | |
1877d6c9 PA |
983 | if (start_new) { |
984 | params.param0 = upper_32_bits(req->trb_dma); | |
985 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 986 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 987 | } else { |
72246da4 | 988 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 989 | } |
72246da4 FB |
990 | |
991 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
992 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
993 | if (ret < 0) { | |
994 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
995 | ||
996 | /* | |
997 | * FIXME we need to iterate over the list of requests | |
998 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 999 | * requests instead of what we do now. |
72246da4 | 1000 | */ |
0fc9a1be FB |
1001 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
1002 | req->direction); | |
72246da4 FB |
1003 | list_del(&req->list); |
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1008 | |
f898ae09 | 1009 | if (start_new) { |
b4996a86 | 1010 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1011 | dep->number); |
b4996a86 | 1012 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1013 | } |
25b8ff68 | 1014 | |
72246da4 FB |
1015 | return 0; |
1016 | } | |
1017 | ||
d6d6ec7b PA |
1018 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1019 | struct dwc3_ep *dep, u32 cur_uf) | |
1020 | { | |
1021 | u32 uf; | |
1022 | ||
1023 | if (list_empty(&dep->request_list)) { | |
1024 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1025 | dep->name); | |
f4a53c55 | 1026 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1027 | return; |
1028 | } | |
1029 | ||
1030 | /* 4 micro frames in the future */ | |
1031 | uf = cur_uf + dep->interval * 4; | |
1032 | ||
1033 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1034 | } | |
1035 | ||
1036 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1037 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1038 | { | |
1039 | u32 cur_uf, mask; | |
1040 | ||
1041 | mask = ~(dep->interval - 1); | |
1042 | cur_uf = event->parameters & mask; | |
1043 | ||
1044 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1045 | } | |
1046 | ||
72246da4 FB |
1047 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1048 | { | |
0fc9a1be FB |
1049 | struct dwc3 *dwc = dep->dwc; |
1050 | int ret; | |
1051 | ||
72246da4 FB |
1052 | req->request.actual = 0; |
1053 | req->request.status = -EINPROGRESS; | |
1054 | req->direction = dep->direction; | |
1055 | req->epnum = dep->number; | |
1056 | ||
1057 | /* | |
1058 | * We only add to our list of requests now and | |
1059 | * start consuming the list once we get XferNotReady | |
1060 | * IRQ. | |
1061 | * | |
1062 | * That way, we avoid doing anything that we don't need | |
1063 | * to do now and defer it until the point we receive a | |
1064 | * particular token from the Host side. | |
1065 | * | |
1066 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1067 | * many NAKs. |
72246da4 | 1068 | */ |
0fc9a1be FB |
1069 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1070 | dep->direction); | |
1071 | if (ret) | |
1072 | return ret; | |
1073 | ||
72246da4 FB |
1074 | list_add_tail(&req->list, &dep->request_list); |
1075 | ||
1076 | /* | |
b511e5e7 | 1077 | * There are a few special cases: |
72246da4 | 1078 | * |
f898ae09 PZ |
1079 | * 1. XferNotReady with empty list of requests. We need to kick the |
1080 | * transfer here in that situation, otherwise we will be NAKing | |
1081 | * forever. If we get XferNotReady before gadget driver has a | |
1082 | * chance to queue a request, we will ACK the IRQ but won't be | |
1083 | * able to receive the data until the next request is queued. | |
1084 | * The following code is handling exactly that. | |
72246da4 | 1085 | * |
72246da4 FB |
1086 | */ |
1087 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1088 | /* |
1089 | * If xfernotready is already elapsed and it is a case | |
1090 | * of isoc transfer, then issue END TRANSFER, so that | |
1091 | * you can receive xfernotready again and can have | |
1092 | * notion of current microframe. | |
1093 | */ | |
1094 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd PA |
1095 | if (list_empty(&dep->req_queued)) { |
1096 | dwc3_stop_active_transfer(dwc, dep->number); | |
1097 | dep->flags = DWC3_EP_ENABLED; | |
1098 | } | |
f4a53c55 PA |
1099 | return 0; |
1100 | } | |
1101 | ||
b511e5e7 | 1102 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
348e026f | 1103 | if (ret && ret != -EBUSY) |
b511e5e7 FB |
1104 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1105 | dep->name); | |
15f86bde | 1106 | return ret; |
b511e5e7 | 1107 | } |
72246da4 | 1108 | |
b511e5e7 FB |
1109 | /* |
1110 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1111 | * kick the transfer here after queuing a request, otherwise the | |
1112 | * core may not see the modified TRB(s). | |
1113 | */ | |
1114 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1115 | (dep->flags & DWC3_EP_BUSY) && |
1116 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1117 | WARN_ON_ONCE(!dep->resource_index); |
1118 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1119 | false); |
348e026f | 1120 | if (ret && ret != -EBUSY) |
72246da4 FB |
1121 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", |
1122 | dep->name); | |
15f86bde | 1123 | return ret; |
a0925324 | 1124 | } |
72246da4 FB |
1125 | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1130 | gfp_t gfp_flags) | |
1131 | { | |
1132 | struct dwc3_request *req = to_dwc3_request(request); | |
1133 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1134 | struct dwc3 *dwc = dep->dwc; | |
1135 | ||
1136 | unsigned long flags; | |
1137 | ||
1138 | int ret; | |
1139 | ||
16e78db7 | 1140 | if (!dep->endpoint.desc) { |
72246da4 FB |
1141 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1142 | request, ep->name); | |
1143 | return -ESHUTDOWN; | |
1144 | } | |
1145 | ||
1146 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1147 | request, ep->name, request->length); | |
1148 | ||
1149 | spin_lock_irqsave(&dwc->lock, flags); | |
1150 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1151 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1152 | ||
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1157 | struct usb_request *request) | |
1158 | { | |
1159 | struct dwc3_request *req = to_dwc3_request(request); | |
1160 | struct dwc3_request *r = NULL; | |
1161 | ||
1162 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1163 | struct dwc3 *dwc = dep->dwc; | |
1164 | ||
1165 | unsigned long flags; | |
1166 | int ret = 0; | |
1167 | ||
1168 | spin_lock_irqsave(&dwc->lock, flags); | |
1169 | ||
1170 | list_for_each_entry(r, &dep->request_list, list) { | |
1171 | if (r == req) | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | if (r != req) { | |
1176 | list_for_each_entry(r, &dep->req_queued, list) { | |
1177 | if (r == req) | |
1178 | break; | |
1179 | } | |
1180 | if (r == req) { | |
1181 | /* wait until it is processed */ | |
1182 | dwc3_stop_active_transfer(dwc, dep->number); | |
e8d4e8be | 1183 | goto out1; |
72246da4 FB |
1184 | } |
1185 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1186 | request, ep->name); | |
1187 | ret = -EINVAL; | |
1188 | goto out0; | |
1189 | } | |
1190 | ||
e8d4e8be | 1191 | out1: |
72246da4 FB |
1192 | /* giveback the request */ |
1193 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1194 | ||
1195 | out0: | |
1196 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1197 | ||
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) | |
1202 | { | |
1203 | struct dwc3_gadget_ep_cmd_params params; | |
1204 | struct dwc3 *dwc = dep->dwc; | |
1205 | int ret; | |
1206 | ||
1207 | memset(¶ms, 0x00, sizeof(params)); | |
1208 | ||
1209 | if (value) { | |
72246da4 FB |
1210 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1211 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1212 | if (ret) | |
1213 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1214 | value ? "set" : "clear", | |
1215 | dep->name); | |
1216 | else | |
1217 | dep->flags |= DWC3_EP_STALL; | |
1218 | } else { | |
1219 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1220 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1221 | if (ret) | |
1222 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1223 | value ? "set" : "clear", | |
1224 | dep->name); | |
1225 | else | |
a535d81c | 1226 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1227 | } |
5275455a | 1228 | |
72246da4 FB |
1229 | return ret; |
1230 | } | |
1231 | ||
1232 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1233 | { | |
1234 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1235 | struct dwc3 *dwc = dep->dwc; | |
1236 | ||
1237 | unsigned long flags; | |
1238 | ||
1239 | int ret; | |
1240 | ||
1241 | spin_lock_irqsave(&dwc->lock, flags); | |
1242 | ||
16e78db7 | 1243 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1244 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1245 | ret = -EINVAL; | |
1246 | goto out; | |
1247 | } | |
1248 | ||
1249 | ret = __dwc3_gadget_ep_set_halt(dep, value); | |
1250 | out: | |
1251 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1252 | ||
1253 | return ret; | |
1254 | } | |
1255 | ||
1256 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1257 | { | |
1258 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1259 | struct dwc3 *dwc = dep->dwc; |
1260 | unsigned long flags; | |
72246da4 | 1261 | |
249a4569 | 1262 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1263 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1264 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1265 | |
08f0d966 PA |
1266 | if (dep->number == 0 || dep->number == 1) |
1267 | return dwc3_gadget_ep0_set_halt(ep, 1); | |
1268 | else | |
1269 | return dwc3_gadget_ep_set_halt(ep, 1); | |
72246da4 FB |
1270 | } |
1271 | ||
1272 | /* -------------------------------------------------------------------------- */ | |
1273 | ||
1274 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1275 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1276 | .bDescriptorType = USB_DT_ENDPOINT, | |
1277 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1278 | }; | |
1279 | ||
1280 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1281 | .enable = dwc3_gadget_ep0_enable, | |
1282 | .disable = dwc3_gadget_ep0_disable, | |
1283 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1284 | .free_request = dwc3_gadget_ep_free_request, | |
1285 | .queue = dwc3_gadget_ep0_queue, | |
1286 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1287 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1288 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1289 | }; | |
1290 | ||
1291 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1292 | .enable = dwc3_gadget_ep_enable, | |
1293 | .disable = dwc3_gadget_ep_disable, | |
1294 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1295 | .free_request = dwc3_gadget_ep_free_request, | |
1296 | .queue = dwc3_gadget_ep_queue, | |
1297 | .dequeue = dwc3_gadget_ep_dequeue, | |
1298 | .set_halt = dwc3_gadget_ep_set_halt, | |
1299 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1300 | }; | |
1301 | ||
1302 | /* -------------------------------------------------------------------------- */ | |
1303 | ||
1304 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1305 | { | |
1306 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1307 | u32 reg; | |
1308 | ||
1309 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1310 | return DWC3_DSTS_SOFFN(reg); | |
1311 | } | |
1312 | ||
1313 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1314 | { | |
1315 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1316 | ||
1317 | unsigned long timeout; | |
1318 | unsigned long flags; | |
1319 | ||
1320 | u32 reg; | |
1321 | ||
1322 | int ret = 0; | |
1323 | ||
1324 | u8 link_state; | |
1325 | u8 speed; | |
1326 | ||
1327 | spin_lock_irqsave(&dwc->lock, flags); | |
1328 | ||
1329 | /* | |
1330 | * According to the Databook Remote wakeup request should | |
1331 | * be issued only when the device is in early suspend state. | |
1332 | * | |
1333 | * We can check that via USB Link State bits in DSTS register. | |
1334 | */ | |
1335 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1336 | ||
1337 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1338 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1339 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1340 | ret = -EINVAL; | |
1341 | goto out; | |
1342 | } | |
1343 | ||
1344 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1345 | ||
1346 | switch (link_state) { | |
1347 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1348 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1349 | break; | |
1350 | default: | |
1351 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1352 | link_state); | |
1353 | ret = -EINVAL; | |
1354 | goto out; | |
1355 | } | |
1356 | ||
8598bde7 FB |
1357 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1358 | if (ret < 0) { | |
1359 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1360 | goto out; | |
1361 | } | |
72246da4 | 1362 | |
802fde98 PZ |
1363 | /* Recent versions do this automatically */ |
1364 | if (dwc->revision < DWC3_REVISION_194A) { | |
1365 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1366 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1367 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1368 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1369 | } | |
72246da4 | 1370 | |
1d046793 | 1371 | /* poll until Link State changes to ON */ |
72246da4 FB |
1372 | timeout = jiffies + msecs_to_jiffies(100); |
1373 | ||
1d046793 | 1374 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1375 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1376 | ||
1377 | /* in HS, means ON */ | |
1378 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1379 | break; | |
1380 | } | |
1381 | ||
1382 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1383 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1384 | ret = -EINVAL; | |
1385 | } | |
1386 | ||
1387 | out: | |
1388 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1389 | ||
1390 | return ret; | |
1391 | } | |
1392 | ||
1393 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1394 | int is_selfpowered) | |
1395 | { | |
1396 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1397 | unsigned long flags; |
72246da4 | 1398 | |
249a4569 | 1399 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1400 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1401 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1402 | |
1403 | return 0; | |
1404 | } | |
1405 | ||
6f17f74b | 1406 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) |
72246da4 FB |
1407 | { |
1408 | u32 reg; | |
61d58242 | 1409 | u32 timeout = 500; |
72246da4 FB |
1410 | |
1411 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1412 | if (is_on) { |
802fde98 PZ |
1413 | if (dwc->revision <= DWC3_REVISION_187A) { |
1414 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1415 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1416 | } | |
1417 | ||
1418 | if (dwc->revision >= DWC3_REVISION_194A) | |
1419 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1420 | reg |= DWC3_DCTL_RUN_STOP; | |
9fcb3bd8 | 1421 | dwc->pullups_connected = true; |
8db7ed15 | 1422 | } else { |
72246da4 | 1423 | reg &= ~DWC3_DCTL_RUN_STOP; |
9fcb3bd8 | 1424 | dwc->pullups_connected = false; |
8db7ed15 | 1425 | } |
72246da4 FB |
1426 | |
1427 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1428 | ||
1429 | do { | |
1430 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1431 | if (is_on) { | |
1432 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1433 | break; | |
1434 | } else { | |
1435 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1436 | break; | |
1437 | } | |
72246da4 FB |
1438 | timeout--; |
1439 | if (!timeout) | |
6f17f74b | 1440 | return -ETIMEDOUT; |
61d58242 | 1441 | udelay(1); |
72246da4 FB |
1442 | } while (1); |
1443 | ||
1444 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1445 | dwc->gadget_driver | |
1446 | ? dwc->gadget_driver->function : "no-function", | |
1447 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1448 | |
1449 | return 0; | |
72246da4 FB |
1450 | } |
1451 | ||
1452 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1453 | { | |
1454 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1455 | unsigned long flags; | |
6f17f74b | 1456 | int ret; |
72246da4 FB |
1457 | |
1458 | is_on = !!is_on; | |
1459 | ||
1460 | spin_lock_irqsave(&dwc->lock, flags); | |
6f17f74b | 1461 | ret = dwc3_gadget_run_stop(dwc, is_on); |
72246da4 FB |
1462 | spin_unlock_irqrestore(&dwc->lock, flags); |
1463 | ||
6f17f74b | 1464 | return ret; |
72246da4 FB |
1465 | } |
1466 | ||
8698e2ac FB |
1467 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1468 | { | |
1469 | u32 reg; | |
1470 | ||
1471 | /* Enable all but Start and End of Frame IRQs */ | |
1472 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1473 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1474 | DWC3_DEVTEN_CMDCMPLTEN | | |
1475 | DWC3_DEVTEN_ERRTICERREN | | |
1476 | DWC3_DEVTEN_WKUPEVTEN | | |
1477 | DWC3_DEVTEN_ULSTCNGEN | | |
1478 | DWC3_DEVTEN_CONNECTDONEEN | | |
1479 | DWC3_DEVTEN_USBRSTEN | | |
1480 | DWC3_DEVTEN_DISCONNEVTEN); | |
1481 | ||
1482 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1483 | } | |
1484 | ||
1485 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1486 | { | |
1487 | /* mask all interrupts */ | |
1488 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1489 | } | |
1490 | ||
1491 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1492 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1493 | |
72246da4 FB |
1494 | static int dwc3_gadget_start(struct usb_gadget *g, |
1495 | struct usb_gadget_driver *driver) | |
1496 | { | |
1497 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1498 | struct dwc3_ep *dep; | |
1499 | unsigned long flags; | |
1500 | int ret = 0; | |
8698e2ac | 1501 | int irq; |
72246da4 FB |
1502 | u32 reg; |
1503 | ||
b0d7ffd4 FB |
1504 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1505 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1506 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1507 | if (ret) { |
1508 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1509 | irq, ret); | |
1510 | goto err0; | |
1511 | } | |
1512 | ||
72246da4 FB |
1513 | spin_lock_irqsave(&dwc->lock, flags); |
1514 | ||
1515 | if (dwc->gadget_driver) { | |
1516 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1517 | dwc->gadget.name, | |
1518 | dwc->gadget_driver->driver.name); | |
1519 | ret = -EBUSY; | |
b0d7ffd4 | 1520 | goto err1; |
72246da4 FB |
1521 | } |
1522 | ||
1523 | dwc->gadget_driver = driver; | |
72246da4 | 1524 | |
72246da4 FB |
1525 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1526 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1527 | |
1528 | /** | |
1529 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1530 | * which would cause metastability state on Run/Stop | |
1531 | * bit if we try to force the IP to USB2-only mode. | |
1532 | * | |
1533 | * Because of that, we cannot configure the IP to any | |
1534 | * speed other than the SuperSpeed | |
1535 | * | |
1536 | * Refers to: | |
1537 | * | |
1538 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1539 | * USB 2.0 Mode | |
1540 | */ | |
f7e846f0 | 1541 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1542 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1543 | } else { |
1544 | switch (dwc->maximum_speed) { | |
1545 | case USB_SPEED_LOW: | |
1546 | reg |= DWC3_DSTS_LOWSPEED; | |
1547 | break; | |
1548 | case USB_SPEED_FULL: | |
1549 | reg |= DWC3_DSTS_FULLSPEED1; | |
1550 | break; | |
1551 | case USB_SPEED_HIGH: | |
1552 | reg |= DWC3_DSTS_HIGHSPEED; | |
1553 | break; | |
1554 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1555 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1556 | default: | |
1557 | reg |= DWC3_DSTS_SUPERSPEED; | |
1558 | } | |
1559 | } | |
72246da4 FB |
1560 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1561 | ||
b23c8439 PZ |
1562 | dwc->start_config_issued = false; |
1563 | ||
72246da4 FB |
1564 | /* Start with SuperSpeed Default */ |
1565 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1566 | ||
1567 | dep = dwc->eps[0]; | |
4b345c9a | 1568 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); |
72246da4 FB |
1569 | if (ret) { |
1570 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1571 | goto err2; |
72246da4 FB |
1572 | } |
1573 | ||
1574 | dep = dwc->eps[1]; | |
4b345c9a | 1575 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); |
72246da4 FB |
1576 | if (ret) { |
1577 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1578 | goto err3; |
72246da4 FB |
1579 | } |
1580 | ||
1581 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1582 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1583 | dwc3_ep0_out_start(dwc); |
1584 | ||
8698e2ac FB |
1585 | dwc3_gadget_enable_irq(dwc); |
1586 | ||
72246da4 FB |
1587 | spin_unlock_irqrestore(&dwc->lock, flags); |
1588 | ||
1589 | return 0; | |
1590 | ||
b0d7ffd4 | 1591 | err3: |
72246da4 FB |
1592 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1593 | ||
b0d7ffd4 | 1594 | err2: |
cdcedd69 | 1595 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1596 | |
1597 | err1: | |
72246da4 FB |
1598 | spin_unlock_irqrestore(&dwc->lock, flags); |
1599 | ||
b0d7ffd4 FB |
1600 | free_irq(irq, dwc); |
1601 | ||
1602 | err0: | |
72246da4 FB |
1603 | return ret; |
1604 | } | |
1605 | ||
1606 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1607 | struct usb_gadget_driver *driver) | |
1608 | { | |
1609 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1610 | unsigned long flags; | |
8698e2ac | 1611 | int irq; |
72246da4 FB |
1612 | |
1613 | spin_lock_irqsave(&dwc->lock, flags); | |
1614 | ||
8698e2ac | 1615 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1616 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1617 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1618 | ||
1619 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1620 | |
1621 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1622 | ||
b0d7ffd4 FB |
1623 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1624 | free_irq(irq, dwc); | |
1625 | ||
72246da4 FB |
1626 | return 0; |
1627 | } | |
802fde98 | 1628 | |
72246da4 FB |
1629 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1630 | .get_frame = dwc3_gadget_get_frame, | |
1631 | .wakeup = dwc3_gadget_wakeup, | |
1632 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1633 | .pullup = dwc3_gadget_pullup, | |
1634 | .udc_start = dwc3_gadget_start, | |
1635 | .udc_stop = dwc3_gadget_stop, | |
1636 | }; | |
1637 | ||
1638 | /* -------------------------------------------------------------------------- */ | |
1639 | ||
6a1e3ef4 FB |
1640 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1641 | u8 num, u32 direction) | |
72246da4 FB |
1642 | { |
1643 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1644 | u8 i; |
72246da4 | 1645 | |
6a1e3ef4 FB |
1646 | for (i = 0; i < num; i++) { |
1647 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1648 | |
72246da4 FB |
1649 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
1650 | if (!dep) { | |
1651 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1652 | epnum); | |
1653 | return -ENOMEM; | |
1654 | } | |
1655 | ||
1656 | dep->dwc = dwc; | |
1657 | dep->number = epnum; | |
9aa62ae4 | 1658 | dep->direction = !!direction; |
72246da4 FB |
1659 | dwc->eps[epnum] = dep; |
1660 | ||
1661 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1662 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1663 | |
72246da4 | 1664 | dep->endpoint.name = dep->name; |
72246da4 | 1665 | |
653df35e FB |
1666 | dev_vdbg(dwc->dev, "initializing %s\n", dep->name); |
1667 | ||
72246da4 | 1668 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1669 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1670 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1671 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1672 | if (!epnum) | |
1673 | dwc->gadget.ep0 = &dep->endpoint; | |
1674 | } else { | |
1675 | int ret; | |
1676 | ||
e117e742 | 1677 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1678 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1679 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1680 | list_add_tail(&dep->endpoint.ep_list, | |
1681 | &dwc->gadget.ep_list); | |
1682 | ||
1683 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1684 | if (ret) |
72246da4 | 1685 | return ret; |
72246da4 | 1686 | } |
25b8ff68 | 1687 | |
72246da4 FB |
1688 | INIT_LIST_HEAD(&dep->request_list); |
1689 | INIT_LIST_HEAD(&dep->req_queued); | |
1690 | } | |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
6a1e3ef4 FB |
1695 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1696 | { | |
1697 | int ret; | |
1698 | ||
1699 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1700 | ||
1701 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1702 | if (ret < 0) { | |
1703 | dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); | |
1704 | return ret; | |
1705 | } | |
1706 | ||
1707 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1708 | if (ret < 0) { | |
1709 | dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); | |
1710 | return ret; | |
1711 | } | |
1712 | ||
1713 | return 0; | |
1714 | } | |
1715 | ||
72246da4 FB |
1716 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1717 | { | |
1718 | struct dwc3_ep *dep; | |
1719 | u8 epnum; | |
1720 | ||
1721 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1722 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1723 | if (!dep) |
1724 | continue; | |
5bf8fae3 GC |
1725 | /* |
1726 | * Physical endpoints 0 and 1 are special; they form the | |
1727 | * bi-directional USB endpoint 0. | |
1728 | * | |
1729 | * For those two physical endpoints, we don't allocate a TRB | |
1730 | * pool nor do we add them the endpoints list. Due to that, we | |
1731 | * shouldn't do these two operations otherwise we would end up | |
1732 | * with all sorts of bugs when removing dwc3.ko. | |
1733 | */ | |
1734 | if (epnum != 0 && epnum != 1) { | |
1735 | dwc3_free_trb_pool(dep); | |
72246da4 | 1736 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1737 | } |
72246da4 FB |
1738 | |
1739 | kfree(dep); | |
1740 | } | |
1741 | } | |
1742 | ||
72246da4 | 1743 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1744 | |
e5ba5ec8 PA |
1745 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1746 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1747 | const struct dwc3_event_depevt *event, int status) |
1748 | { | |
72246da4 FB |
1749 | unsigned int count; |
1750 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1751 | unsigned int trb_status; |
72246da4 | 1752 | |
e5ba5ec8 PA |
1753 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1754 | /* | |
1755 | * We continue despite the error. There is not much we | |
1756 | * can do. If we don't clean it up we loop forever. If | |
1757 | * we skip the TRB then it gets overwritten after a | |
1758 | * while since we use them in a ring buffer. A BUG() | |
1759 | * would help. Lets hope that if this occurs, someone | |
1760 | * fixes the root cause instead of looking away :) | |
1761 | */ | |
1762 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1763 | dep->name, trb); | |
1764 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1765 | ||
1766 | if (dep->direction) { | |
1767 | if (count) { | |
1768 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1769 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
1770 | dev_dbg(dwc->dev, "incomplete IN transfer %s\n", | |
1771 | dep->name); | |
1772 | /* | |
1773 | * If missed isoc occurred and there is | |
1774 | * no request queued then issue END | |
1775 | * TRANSFER, so that core generates | |
1776 | * next xfernotready and we will issue | |
1777 | * a fresh START TRANSFER. | |
1778 | * If there are still queued request | |
1779 | * then wait, do not issue either END | |
1780 | * or UPDATE TRANSFER, just attach next | |
1781 | * request in request_list during | |
1782 | * giveback.If any future queued request | |
1783 | * is successfully transferred then we | |
1784 | * will issue UPDATE TRANSFER for all | |
1785 | * request in the request_list. | |
1786 | */ | |
1787 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1788 | } else { | |
1789 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1790 | dep->name); | |
1791 | status = -ECONNRESET; | |
1792 | } | |
1793 | } else { | |
1794 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1795 | } | |
1796 | } else { | |
1797 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1798 | s_pkt = 1; | |
1799 | } | |
1800 | ||
1801 | /* | |
1802 | * We assume here we will always receive the entire data block | |
1803 | * which we should receive. Meaning, if we program RX to | |
1804 | * receive 4K but we receive only 2K, we assume that's all we | |
1805 | * should receive and we simply bounce the request back to the | |
1806 | * gadget driver for further processing. | |
1807 | */ | |
1808 | req->request.actual += req->request.length - count; | |
1809 | if (s_pkt) | |
1810 | return 1; | |
1811 | if ((event->status & DEPEVT_STATUS_LST) && | |
1812 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1813 | DWC3_TRB_CTRL_HWO))) | |
1814 | return 1; | |
1815 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1816 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1817 | return 1; | |
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1822 | const struct dwc3_event_depevt *event, int status) | |
1823 | { | |
1824 | struct dwc3_request *req; | |
1825 | struct dwc3_trb *trb; | |
1826 | unsigned int slot; | |
1827 | unsigned int i; | |
1828 | int ret; | |
1829 | ||
72246da4 FB |
1830 | do { |
1831 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1832 | if (!req) { |
1833 | WARN_ON_ONCE(1); | |
1834 | return 1; | |
1835 | } | |
e5ba5ec8 PA |
1836 | i = 0; |
1837 | do { | |
1838 | slot = req->start_slot + i; | |
1839 | if ((slot == DWC3_TRB_NUM - 1) && | |
1840 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
1841 | slot++; | |
1842 | slot %= DWC3_TRB_NUM; | |
1843 | trb = &dep->trb_pool[slot]; | |
72246da4 | 1844 | |
e5ba5ec8 PA |
1845 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
1846 | event, status); | |
1847 | if (ret) | |
1848 | break; | |
1849 | }while (++i < req->request.num_mapped_sgs); | |
72246da4 | 1850 | |
72246da4 | 1851 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 PA |
1852 | |
1853 | if (ret) | |
72246da4 FB |
1854 | break; |
1855 | } while (1); | |
1856 | ||
cdc359dd PA |
1857 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1858 | list_empty(&dep->req_queued)) { | |
1859 | if (list_empty(&dep->request_list)) { | |
1860 | /* | |
1861 | * If there is no entry in request list then do | |
1862 | * not issue END TRANSFER now. Just set PENDING | |
1863 | * flag, so that END TRANSFER is issued when an | |
1864 | * entry is added into request list. | |
1865 | */ | |
1866 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1867 | } else { | |
1868 | dwc3_stop_active_transfer(dwc, dep->number); | |
1869 | dep->flags = DWC3_EP_ENABLED; | |
1870 | } | |
7efea86c PA |
1871 | return 1; |
1872 | } | |
1873 | ||
72246da4 FB |
1874 | return 1; |
1875 | } | |
1876 | ||
1877 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
1878 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event, | |
1879 | int start_new) | |
1880 | { | |
1881 | unsigned status = 0; | |
1882 | int clean_busy; | |
1883 | ||
1884 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1885 | status = -ECONNRESET; | |
1886 | ||
1d046793 | 1887 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1888 | if (clean_busy) |
72246da4 | 1889 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1890 | |
1891 | /* | |
1892 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1893 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1894 | */ | |
1895 | if (dwc->revision < DWC3_REVISION_183A) { | |
1896 | u32 reg; | |
1897 | int i; | |
1898 | ||
1899 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 1900 | dep = dwc->eps[i]; |
fae2b904 FB |
1901 | |
1902 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1903 | continue; | |
1904 | ||
1905 | if (!list_empty(&dep->req_queued)) | |
1906 | return; | |
1907 | } | |
1908 | ||
1909 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1910 | reg |= dwc->u1u2; | |
1911 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1912 | ||
1913 | dwc->u1u2 = 0; | |
1914 | } | |
72246da4 FB |
1915 | } |
1916 | ||
72246da4 FB |
1917 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
1918 | const struct dwc3_event_depevt *event) | |
1919 | { | |
1920 | struct dwc3_ep *dep; | |
1921 | u8 epnum = event->endpoint_number; | |
1922 | ||
1923 | dep = dwc->eps[epnum]; | |
1924 | ||
3336abb5 FB |
1925 | if (!(dep->flags & DWC3_EP_ENABLED)) |
1926 | return; | |
1927 | ||
72246da4 FB |
1928 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, |
1929 | dwc3_ep_event_string(event->endpoint_event)); | |
1930 | ||
1931 | if (epnum == 0 || epnum == 1) { | |
1932 | dwc3_ep0_interrupt(dwc, event); | |
1933 | return; | |
1934 | } | |
1935 | ||
1936 | switch (event->endpoint_event) { | |
1937 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 1938 | dep->resource_index = 0; |
c2df85ca | 1939 | |
16e78db7 | 1940 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1941 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
1942 | dep->name); | |
1943 | return; | |
1944 | } | |
1945 | ||
1946 | dwc3_endpoint_transfer_complete(dwc, dep, event, 1); | |
1947 | break; | |
1948 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 1949 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1950 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
1951 | dep->name); | |
1952 | return; | |
1953 | } | |
1954 | ||
1955 | dwc3_endpoint_transfer_complete(dwc, dep, event, 0); | |
1956 | break; | |
1957 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 1958 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1959 | dwc3_gadget_start_isoc(dwc, dep, event); |
1960 | } else { | |
1961 | int ret; | |
1962 | ||
1963 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
1964 | dep->name, event->status & |
1965 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
1966 | ? "Transfer Active" |
1967 | : "Transfer Not Active"); | |
1968 | ||
1969 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
1970 | if (!ret || ret == -EBUSY) | |
1971 | return; | |
1972 | ||
1973 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1974 | dep->name); | |
1975 | } | |
1976 | ||
879631aa FB |
1977 | break; |
1978 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 1979 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
1980 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
1981 | dep->name); | |
1982 | return; | |
1983 | } | |
1984 | ||
1985 | switch (event->status) { | |
1986 | case DEPEVT_STREAMEVT_FOUND: | |
1987 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
1988 | event->parameters); | |
1989 | ||
1990 | break; | |
1991 | case DEPEVT_STREAMEVT_NOTFOUND: | |
1992 | /* FALLTHROUGH */ | |
1993 | default: | |
1994 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
1995 | } | |
72246da4 FB |
1996 | break; |
1997 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1998 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
1999 | break; | |
72246da4 | 2000 | case DWC3_DEPEVT_EPCMDCMPLT: |
ea53b882 | 2001 | dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); |
72246da4 FB |
2002 | break; |
2003 | } | |
2004 | } | |
2005 | ||
2006 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2007 | { | |
2008 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2009 | spin_unlock(&dwc->lock); | |
2010 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2011 | spin_lock(&dwc->lock); | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) | |
2016 | { | |
2017 | struct dwc3_ep *dep; | |
2018 | struct dwc3_gadget_ep_cmd_params params; | |
2019 | u32 cmd; | |
2020 | int ret; | |
2021 | ||
2022 | dep = dwc->eps[epnum]; | |
2023 | ||
b4996a86 | 2024 | if (!dep->resource_index) |
3daf74d7 PA |
2025 | return; |
2026 | ||
57911504 PA |
2027 | /* |
2028 | * NOTICE: We are violating what the Databook says about the | |
2029 | * EndTransfer command. Ideally we would _always_ wait for the | |
2030 | * EndTransfer Command Completion IRQ, but that's causing too | |
2031 | * much trouble synchronizing between us and gadget driver. | |
2032 | * | |
2033 | * We have discussed this with the IP Provider and it was | |
2034 | * suggested to giveback all requests here, but give HW some | |
2035 | * extra time to synchronize with the interconnect. We're using | |
2036 | * an arbitraty 100us delay for that. | |
2037 | * | |
2038 | * Note also that a similar handling was tested by Synopsys | |
2039 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2040 | * In short, what we're doing is: | |
2041 | * | |
2042 | * - Issue EndTransfer WITH CMDIOC bit set | |
2043 | * - Wait 100us | |
2044 | */ | |
2045 | ||
3daf74d7 PA |
2046 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
2047 | cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2048 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2049 | memset(¶ms, 0, sizeof(params)); |
2050 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2051 | WARN_ON_ONCE(ret); | |
b4996a86 | 2052 | dep->resource_index = 0; |
041d81f4 | 2053 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2054 | udelay(100); |
72246da4 FB |
2055 | } |
2056 | ||
2057 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2058 | { | |
2059 | u32 epnum; | |
2060 | ||
2061 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2062 | struct dwc3_ep *dep; | |
2063 | ||
2064 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2065 | if (!dep) |
2066 | continue; | |
2067 | ||
72246da4 FB |
2068 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2069 | continue; | |
2070 | ||
624407f9 | 2071 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2072 | } |
2073 | } | |
2074 | ||
2075 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2076 | { | |
2077 | u32 epnum; | |
2078 | ||
2079 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2080 | struct dwc3_ep *dep; | |
2081 | struct dwc3_gadget_ep_cmd_params params; | |
2082 | int ret; | |
2083 | ||
2084 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2085 | if (!dep) |
2086 | continue; | |
72246da4 FB |
2087 | |
2088 | if (!(dep->flags & DWC3_EP_STALL)) | |
2089 | continue; | |
2090 | ||
2091 | dep->flags &= ~DWC3_EP_STALL; | |
2092 | ||
2093 | memset(¶ms, 0, sizeof(params)); | |
2094 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2095 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2096 | WARN_ON_ONCE(ret); | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2101 | { | |
c4430a26 FB |
2102 | int reg; |
2103 | ||
72246da4 | 2104 | dev_vdbg(dwc->dev, "%s\n", __func__); |
72246da4 FB |
2105 | |
2106 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2107 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2108 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2109 | ||
2110 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2111 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2112 | |
72246da4 | 2113 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2114 | dwc->start_config_issued = false; |
72246da4 FB |
2115 | |
2116 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2117 | dwc->setup_packet_pending = false; |
72246da4 FB |
2118 | } |
2119 | ||
72246da4 FB |
2120 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2121 | { | |
2122 | u32 reg; | |
2123 | ||
2124 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2125 | ||
df62df56 FB |
2126 | /* |
2127 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2128 | * would cause a missing Disconnect Event if there's a | |
2129 | * pending Setup Packet in the FIFO. | |
2130 | * | |
2131 | * There's no suggested workaround on the official Bug | |
2132 | * report, which states that "unless the driver/application | |
2133 | * is doing any special handling of a disconnect event, | |
2134 | * there is no functional issue". | |
2135 | * | |
2136 | * Unfortunately, it turns out that we _do_ some special | |
2137 | * handling of a disconnect event, namely complete all | |
2138 | * pending transfers, notify gadget driver of the | |
2139 | * disconnection, and so on. | |
2140 | * | |
2141 | * Our suggested workaround is to follow the Disconnect | |
2142 | * Event steps here, instead, based on a setup_packet_pending | |
2143 | * flag. Such flag gets set whenever we have a XferNotReady | |
2144 | * event on EP0 and gets cleared on XferComplete for the | |
2145 | * same endpoint. | |
2146 | * | |
2147 | * Refers to: | |
2148 | * | |
2149 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2150 | * generated if setup packet pending in FIFO | |
2151 | */ | |
2152 | if (dwc->revision < DWC3_REVISION_188A) { | |
2153 | if (dwc->setup_packet_pending) | |
2154 | dwc3_gadget_disconnect_interrupt(dwc); | |
2155 | } | |
2156 | ||
961906ed | 2157 | /* after reset -> Default State */ |
14cd592f | 2158 | usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); |
961906ed | 2159 | |
72246da4 FB |
2160 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) |
2161 | dwc3_disconnect_gadget(dwc); | |
2162 | ||
2163 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2164 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2165 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2166 | dwc->test_mode = false; |
72246da4 FB |
2167 | |
2168 | dwc3_stop_active_transfers(dwc); | |
2169 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2170 | dwc->start_config_issued = false; |
72246da4 FB |
2171 | |
2172 | /* Reset device address to zero */ | |
2173 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2174 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2175 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2176 | } |
2177 | ||
2178 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2179 | { | |
2180 | u32 reg; | |
2181 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2182 | ||
2183 | /* | |
2184 | * We change the clock only at SS but I dunno why I would want to do | |
2185 | * this. Maybe it becomes part of the power saving plan. | |
2186 | */ | |
2187 | ||
2188 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2189 | return; | |
2190 | ||
2191 | /* | |
2192 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2193 | * each time on Connect Done. | |
2194 | */ | |
2195 | if (!usb30_clock) | |
2196 | return; | |
2197 | ||
2198 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2199 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2200 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2201 | } | |
2202 | ||
72246da4 FB |
2203 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2204 | { | |
72246da4 FB |
2205 | struct dwc3_ep *dep; |
2206 | int ret; | |
2207 | u32 reg; | |
2208 | u8 speed; | |
2209 | ||
2210 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2211 | ||
72246da4 FB |
2212 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2213 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2214 | dwc->speed = speed; | |
2215 | ||
2216 | dwc3_update_ram_clk_sel(dwc, speed); | |
2217 | ||
2218 | switch (speed) { | |
2219 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2220 | /* |
2221 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2222 | * would cause a missing USB3 Reset event. | |
2223 | * | |
2224 | * In such situations, we should force a USB3 Reset | |
2225 | * event by calling our dwc3_gadget_reset_interrupt() | |
2226 | * routine. | |
2227 | * | |
2228 | * Refers to: | |
2229 | * | |
2230 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2231 | * not be generated always when the link enters poll | |
2232 | */ | |
2233 | if (dwc->revision < DWC3_REVISION_190A) | |
2234 | dwc3_gadget_reset_interrupt(dwc); | |
2235 | ||
72246da4 FB |
2236 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2237 | dwc->gadget.ep0->maxpacket = 512; | |
2238 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2239 | break; | |
2240 | case DWC3_DCFG_HIGHSPEED: | |
2241 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2242 | dwc->gadget.ep0->maxpacket = 64; | |
2243 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2244 | break; | |
2245 | case DWC3_DCFG_FULLSPEED2: | |
2246 | case DWC3_DCFG_FULLSPEED1: | |
2247 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2248 | dwc->gadget.ep0->maxpacket = 64; | |
2249 | dwc->gadget.speed = USB_SPEED_FULL; | |
2250 | break; | |
2251 | case DWC3_DCFG_LOWSPEED: | |
2252 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2253 | dwc->gadget.ep0->maxpacket = 8; | |
2254 | dwc->gadget.speed = USB_SPEED_LOW; | |
2255 | break; | |
2256 | } | |
2257 | ||
2b758350 PA |
2258 | /* Enable USB2 LPM Capability */ |
2259 | ||
2260 | if ((dwc->revision > DWC3_REVISION_194A) | |
2261 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2262 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2263 | reg |= DWC3_DCFG_LPM_CAP; | |
2264 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2265 | ||
2266 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2267 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2268 | ||
1a947746 FB |
2269 | /* |
2270 | * TODO: This should be configurable. For now using | |
2271 | * maximum allowed HIRD threshold value of 0b1100 | |
2272 | */ | |
2273 | reg |= DWC3_DCTL_HIRD_THRES(12); | |
2b758350 PA |
2274 | |
2275 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2276 | } | |
2277 | ||
72246da4 | 2278 | dep = dwc->eps[0]; |
4b345c9a | 2279 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); |
72246da4 FB |
2280 | if (ret) { |
2281 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2282 | return; | |
2283 | } | |
2284 | ||
2285 | dep = dwc->eps[1]; | |
4b345c9a | 2286 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); |
72246da4 FB |
2287 | if (ret) { |
2288 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2289 | return; | |
2290 | } | |
2291 | ||
2292 | /* | |
2293 | * Configure PHY via GUSB3PIPECTLn if required. | |
2294 | * | |
2295 | * Update GTXFIFOSIZn | |
2296 | * | |
2297 | * In both cases reset values should be sufficient. | |
2298 | */ | |
2299 | } | |
2300 | ||
2301 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2302 | { | |
2303 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2304 | ||
2305 | /* | |
2306 | * TODO take core out of low power mode when that's | |
2307 | * implemented. | |
2308 | */ | |
2309 | ||
2310 | dwc->gadget_driver->resume(&dwc->gadget); | |
2311 | } | |
2312 | ||
2313 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2314 | unsigned int evtinfo) | |
2315 | { | |
fae2b904 | 2316 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2317 | unsigned int pwropt; |
2318 | ||
2319 | /* | |
2320 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2321 | * Hibernation mode enabled which would show up when device detects | |
2322 | * host-initiated U3 exit. | |
2323 | * | |
2324 | * In that case, device will generate a Link State Change Interrupt | |
2325 | * from U3 to RESUME which is only necessary if Hibernation is | |
2326 | * configured in. | |
2327 | * | |
2328 | * There are no functional changes due to such spurious event and we | |
2329 | * just need to ignore it. | |
2330 | * | |
2331 | * Refers to: | |
2332 | * | |
2333 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2334 | * operational mode | |
2335 | */ | |
2336 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2337 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2338 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2339 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2340 | (next == DWC3_LINK_STATE_RESUME)) { | |
2341 | dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); | |
2342 | return; | |
2343 | } | |
2344 | } | |
fae2b904 FB |
2345 | |
2346 | /* | |
2347 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2348 | * on the link partner, the USB session might do multiple entry/exit | |
2349 | * of low power states before a transfer takes place. | |
2350 | * | |
2351 | * Due to this problem, we might experience lower throughput. The | |
2352 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2353 | * transitioning from U1/U2 to U0 and enable those bits again | |
2354 | * after a transfer completes and there are no pending transfers | |
2355 | * on any of the enabled endpoints. | |
2356 | * | |
2357 | * This is the first half of that workaround. | |
2358 | * | |
2359 | * Refers to: | |
2360 | * | |
2361 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2362 | * core send LGO_Ux entering U0 | |
2363 | */ | |
2364 | if (dwc->revision < DWC3_REVISION_183A) { | |
2365 | if (next == DWC3_LINK_STATE_U0) { | |
2366 | u32 u1u2; | |
2367 | u32 reg; | |
2368 | ||
2369 | switch (dwc->link_state) { | |
2370 | case DWC3_LINK_STATE_U1: | |
2371 | case DWC3_LINK_STATE_U2: | |
2372 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2373 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2374 | | DWC3_DCTL_ACCEPTU2ENA | |
2375 | | DWC3_DCTL_INITU1ENA | |
2376 | | DWC3_DCTL_ACCEPTU1ENA); | |
2377 | ||
2378 | if (!dwc->u1u2) | |
2379 | dwc->u1u2 = reg & u1u2; | |
2380 | ||
2381 | reg &= ~u1u2; | |
2382 | ||
2383 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2384 | break; | |
2385 | default: | |
2386 | /* do nothing */ | |
2387 | break; | |
2388 | } | |
2389 | } | |
2390 | } | |
2391 | ||
2392 | dwc->link_state = next; | |
019ac832 FB |
2393 | |
2394 | dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); | |
72246da4 FB |
2395 | } |
2396 | ||
e1dadd3b FB |
2397 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2398 | unsigned int evtinfo) | |
2399 | { | |
2400 | unsigned int is_ss = evtinfo & BIT(4); | |
2401 | ||
2402 | /** | |
2403 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2404 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2405 | * randomly. | |
2406 | * | |
2407 | * Because of this issue, core could generate bogus hibernation | |
2408 | * events which SW needs to ignore. | |
2409 | * | |
2410 | * Refers to: | |
2411 | * | |
2412 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2413 | * Device Fallback from SuperSpeed | |
2414 | */ | |
2415 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2416 | return; | |
2417 | ||
2418 | /* enter hibernation here */ | |
2419 | } | |
2420 | ||
72246da4 FB |
2421 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2422 | const struct dwc3_event_devt *event) | |
2423 | { | |
2424 | switch (event->type) { | |
2425 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2426 | dwc3_gadget_disconnect_interrupt(dwc); | |
2427 | break; | |
2428 | case DWC3_DEVICE_EVENT_RESET: | |
2429 | dwc3_gadget_reset_interrupt(dwc); | |
2430 | break; | |
2431 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2432 | dwc3_gadget_conndone_interrupt(dwc); | |
2433 | break; | |
2434 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2435 | dwc3_gadget_wakeup_interrupt(dwc); | |
2436 | break; | |
e1dadd3b FB |
2437 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2438 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2439 | "unexpected hibernation event\n")) | |
2440 | break; | |
2441 | ||
2442 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2443 | break; | |
72246da4 FB |
2444 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2445 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2446 | break; | |
2447 | case DWC3_DEVICE_EVENT_EOPF: | |
2448 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2449 | break; | |
2450 | case DWC3_DEVICE_EVENT_SOF: | |
2451 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2452 | break; | |
2453 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2454 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2455 | break; | |
2456 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2457 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2458 | break; | |
2459 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2460 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2461 | break; | |
2462 | default: | |
2463 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2464 | } | |
2465 | } | |
2466 | ||
2467 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2468 | const union dwc3_event *event) | |
2469 | { | |
2470 | /* Endpoint IRQ, handle it and return early */ | |
2471 | if (event->type.is_devspec == 0) { | |
2472 | /* depevt */ | |
2473 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2474 | } | |
2475 | ||
2476 | switch (event->type.type) { | |
2477 | case DWC3_EVENT_TYPE_DEV: | |
2478 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2479 | break; | |
2480 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2481 | default: | |
2482 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2483 | } | |
2484 | } | |
2485 | ||
f42f2447 | 2486 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2487 | { |
f42f2447 | 2488 | struct dwc3_event_buffer *evt; |
b15a762f | 2489 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2490 | int left; |
e8adfc30 | 2491 | u32 reg; |
b15a762f | 2492 | |
f42f2447 FB |
2493 | evt = dwc->ev_buffs[buf]; |
2494 | left = evt->count; | |
b15a762f | 2495 | |
f42f2447 FB |
2496 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2497 | return IRQ_NONE; | |
b15a762f | 2498 | |
f42f2447 FB |
2499 | while (left > 0) { |
2500 | union dwc3_event event; | |
b15a762f | 2501 | |
f42f2447 | 2502 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2503 | |
f42f2447 | 2504 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2505 | |
f42f2447 FB |
2506 | /* |
2507 | * FIXME we wrap around correctly to the next entry as | |
2508 | * almost all entries are 4 bytes in size. There is one | |
2509 | * entry which has 12 bytes which is a regular entry | |
2510 | * followed by 8 bytes data. ATM I don't know how | |
2511 | * things are organized if we get next to the a | |
2512 | * boundary so I worry about that once we try to handle | |
2513 | * that. | |
2514 | */ | |
2515 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2516 | left -= 4; | |
b15a762f | 2517 | |
f42f2447 FB |
2518 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2519 | } | |
b15a762f | 2520 | |
f42f2447 FB |
2521 | evt->count = 0; |
2522 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2523 | ret = IRQ_HANDLED; | |
b15a762f | 2524 | |
f42f2447 FB |
2525 | /* Unmask interrupt */ |
2526 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2527 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2528 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2529 | |
f42f2447 FB |
2530 | return ret; |
2531 | } | |
e8adfc30 | 2532 | |
f42f2447 FB |
2533 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2534 | { | |
2535 | struct dwc3 *dwc = _dwc; | |
2536 | unsigned long flags; | |
2537 | irqreturn_t ret = IRQ_NONE; | |
2538 | int i; | |
2539 | ||
2540 | spin_lock_irqsave(&dwc->lock, flags); | |
2541 | ||
2542 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2543 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f FB |
2544 | |
2545 | spin_unlock_irqrestore(&dwc->lock, flags); | |
2546 | ||
2547 | return ret; | |
2548 | } | |
2549 | ||
7f97aa98 | 2550 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2551 | { |
2552 | struct dwc3_event_buffer *evt; | |
72246da4 | 2553 | u32 count; |
e8adfc30 | 2554 | u32 reg; |
72246da4 | 2555 | |
b15a762f FB |
2556 | evt = dwc->ev_buffs[buf]; |
2557 | ||
72246da4 FB |
2558 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2559 | count &= DWC3_GEVNTCOUNT_MASK; | |
2560 | if (!count) | |
2561 | return IRQ_NONE; | |
2562 | ||
b15a762f FB |
2563 | evt->count = count; |
2564 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2565 | |
e8adfc30 FB |
2566 | /* Mask interrupt */ |
2567 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2568 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2569 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2570 | ||
b15a762f | 2571 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2572 | } |
2573 | ||
2574 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2575 | { | |
2576 | struct dwc3 *dwc = _dwc; | |
2577 | int i; | |
2578 | irqreturn_t ret = IRQ_NONE; | |
2579 | ||
2580 | spin_lock(&dwc->lock); | |
2581 | ||
9f622b2a | 2582 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2583 | irqreturn_t status; |
2584 | ||
7f97aa98 | 2585 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2586 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2587 | ret = status; |
2588 | } | |
2589 | ||
2590 | spin_unlock(&dwc->lock); | |
2591 | ||
2592 | return ret; | |
2593 | } | |
2594 | ||
2595 | /** | |
2596 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2597 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2598 | * |
2599 | * Returns 0 on success otherwise negative errno. | |
2600 | */ | |
41ac7b3a | 2601 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2602 | { |
72246da4 | 2603 | int ret; |
72246da4 FB |
2604 | |
2605 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2606 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2607 | if (!dwc->ctrl_req) { | |
2608 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2609 | ret = -ENOMEM; | |
2610 | goto err0; | |
2611 | } | |
2612 | ||
2613 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2614 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2615 | if (!dwc->ep0_trb) { | |
2616 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2617 | ret = -ENOMEM; | |
2618 | goto err1; | |
2619 | } | |
2620 | ||
3ef35faf | 2621 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2622 | if (!dwc->setup_buf) { |
2623 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2624 | ret = -ENOMEM; | |
2625 | goto err2; | |
2626 | } | |
2627 | ||
5812b1c2 | 2628 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2629 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2630 | GFP_KERNEL); | |
5812b1c2 FB |
2631 | if (!dwc->ep0_bounce) { |
2632 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2633 | ret = -ENOMEM; | |
2634 | goto err3; | |
2635 | } | |
2636 | ||
72246da4 | 2637 | dwc->gadget.ops = &dwc3_gadget_ops; |
d327ab5b | 2638 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 | 2639 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2640 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2641 | dwc->gadget.name = "dwc3-gadget"; |
2642 | ||
a4b9d94b DC |
2643 | /* |
2644 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2645 | * on ep out. | |
2646 | */ | |
2647 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2648 | ||
72246da4 FB |
2649 | /* |
2650 | * REVISIT: Here we should clear all pending IRQs to be | |
2651 | * sure we're starting from a well known location. | |
2652 | */ | |
2653 | ||
2654 | ret = dwc3_gadget_init_endpoints(dwc); | |
2655 | if (ret) | |
5812b1c2 | 2656 | goto err4; |
72246da4 | 2657 | |
72246da4 FB |
2658 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2659 | if (ret) { | |
2660 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2661 | goto err4; |
72246da4 FB |
2662 | } |
2663 | ||
2664 | return 0; | |
2665 | ||
5812b1c2 | 2666 | err4: |
e1f80467 | 2667 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2668 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2669 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2670 | |
72246da4 | 2671 | err3: |
0fc9a1be | 2672 | kfree(dwc->setup_buf); |
72246da4 FB |
2673 | |
2674 | err2: | |
2675 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2676 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2677 | ||
2678 | err1: | |
2679 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2680 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2681 | ||
2682 | err0: | |
2683 | return ret; | |
2684 | } | |
2685 | ||
7415f17c FB |
2686 | /* -------------------------------------------------------------------------- */ |
2687 | ||
72246da4 FB |
2688 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2689 | { | |
72246da4 | 2690 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2691 | |
72246da4 FB |
2692 | dwc3_gadget_free_endpoints(dwc); |
2693 | ||
3ef35faf FB |
2694 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2695 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2696 | |
0fc9a1be | 2697 | kfree(dwc->setup_buf); |
72246da4 FB |
2698 | |
2699 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2700 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2701 | ||
2702 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2703 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2704 | } |
7415f17c FB |
2705 | |
2706 | int dwc3_gadget_prepare(struct dwc3 *dwc) | |
2707 | { | |
2708 | if (dwc->pullups_connected) | |
2709 | dwc3_gadget_disable_irq(dwc); | |
2710 | ||
2711 | return 0; | |
2712 | } | |
2713 | ||
2714 | void dwc3_gadget_complete(struct dwc3 *dwc) | |
2715 | { | |
2716 | if (dwc->pullups_connected) { | |
2717 | dwc3_gadget_enable_irq(dwc); | |
2718 | dwc3_gadget_run_stop(dwc, true); | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | int dwc3_gadget_suspend(struct dwc3 *dwc) | |
2723 | { | |
2724 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2725 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2726 | ||
2727 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2728 | ||
2729 | return 0; | |
2730 | } | |
2731 | ||
2732 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2733 | { | |
2734 | struct dwc3_ep *dep; | |
2735 | int ret; | |
2736 | ||
2737 | /* Start with SuperSpeed Default */ | |
2738 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2739 | ||
2740 | dep = dwc->eps[0]; | |
2741 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); | |
2742 | if (ret) | |
2743 | goto err0; | |
2744 | ||
2745 | dep = dwc->eps[1]; | |
2746 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); | |
2747 | if (ret) | |
2748 | goto err1; | |
2749 | ||
2750 | /* begin to receive SETUP packets */ | |
2751 | dwc->ep0state = EP0_SETUP_PHASE; | |
2752 | dwc3_ep0_out_start(dwc); | |
2753 | ||
2754 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2755 | ||
2756 | return 0; | |
2757 | ||
2758 | err1: | |
2759 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2760 | ||
2761 | err0: | |
2762 | return ret; | |
2763 | } |