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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
73815280 FB |
142 | dwc3_trace(trace_dwc3_gadget, |
143 | "link state change request timed out"); | |
8598bde7 FB |
144 | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
ef966b9d FB |
148 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
149 | { | |
150 | dep->trb_enqueue++; | |
4faf7550 | 151 | dep->trb_enqueue %= DWC3_TRB_NUM; |
ef966b9d FB |
152 | } |
153 | ||
154 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) | |
155 | { | |
156 | dep->trb_dequeue++; | |
4faf7550 | 157 | dep->trb_dequeue %= DWC3_TRB_NUM; |
ef966b9d FB |
158 | } |
159 | ||
160 | static int dwc3_ep_is_last_trb(unsigned int index) | |
161 | { | |
4faf7550 | 162 | return index == DWC3_TRB_NUM - 1; |
ef966b9d FB |
163 | } |
164 | ||
72246da4 FB |
165 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
166 | int status) | |
167 | { | |
168 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 169 | int i; |
72246da4 | 170 | |
aa3342c8 | 171 | if (req->started) { |
e5ba5ec8 PA |
172 | i = 0; |
173 | do { | |
ef966b9d | 174 | dwc3_ep_inc_deq(dep); |
e5ba5ec8 PA |
175 | /* |
176 | * Skip LINK TRB. We can't use req->trb and check for | |
177 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
178 | * just completed (not the LINK TRB). | |
179 | */ | |
36b68aae | 180 | if (dwc3_ep_is_last_trb(dep->trb_dequeue)) |
ef966b9d | 181 | dwc3_ep_inc_deq(dep); |
e5ba5ec8 | 182 | } while(++i < req->request.num_mapped_sgs); |
aa3342c8 | 183 | req->started = false; |
72246da4 FB |
184 | } |
185 | list_del(&req->list); | |
eeb720fb | 186 | req->trb = NULL; |
72246da4 FB |
187 | |
188 | if (req->request.status == -EINPROGRESS) | |
189 | req->request.status = status; | |
190 | ||
0416e494 PA |
191 | if (dwc->ep0_bounced && dep->number == 0) |
192 | dwc->ep0_bounced = false; | |
193 | else | |
194 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
195 | req->direction); | |
72246da4 | 196 | |
2c4cbe6e | 197 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
198 | |
199 | spin_unlock(&dwc->lock); | |
304f7e5e | 200 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
201 | spin_lock(&dwc->lock); |
202 | } | |
203 | ||
3ece0ec4 | 204 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
205 | { |
206 | u32 timeout = 500; | |
207 | u32 reg; | |
208 | ||
2c4cbe6e | 209 | trace_dwc3_gadget_generic_cmd(cmd, param); |
427c3df6 | 210 | |
b09bb642 FB |
211 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); |
212 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
213 | ||
214 | do { | |
215 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
216 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
73815280 FB |
217 | dwc3_trace(trace_dwc3_gadget, |
218 | "Command Complete --> %d", | |
b09bb642 | 219 | DWC3_DGCMD_STATUS(reg)); |
891b1dc0 SSB |
220 | if (DWC3_DGCMD_STATUS(reg)) |
221 | return -EINVAL; | |
b09bb642 FB |
222 | return 0; |
223 | } | |
224 | ||
225 | /* | |
226 | * We can't sleep here, because it's also called from | |
227 | * interrupt context. | |
228 | */ | |
229 | timeout--; | |
73815280 FB |
230 | if (!timeout) { |
231 | dwc3_trace(trace_dwc3_gadget, | |
232 | "Command Timed Out"); | |
b09bb642 | 233 | return -ETIMEDOUT; |
73815280 | 234 | } |
b09bb642 FB |
235 | udelay(1); |
236 | } while (1); | |
237 | } | |
238 | ||
c36d8e94 FB |
239 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
240 | ||
72246da4 FB |
241 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
242 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
243 | { | |
244 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 245 | u32 timeout = 500; |
72246da4 | 246 | u32 reg; |
2b0f11df FB |
247 | |
248 | int susphy = false; | |
c0ca324d | 249 | int ret = -EINVAL; |
72246da4 | 250 | |
2c4cbe6e | 251 | trace_dwc3_gadget_ep_cmd(dep, cmd, params); |
72246da4 | 252 | |
2b0f11df FB |
253 | /* |
254 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
255 | * we're issuing an endpoint command, we must check if | |
256 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
257 | * | |
258 | * We will also set SUSPHY bit to what it was before returning as stated | |
259 | * by the same section on Synopsys databook. | |
260 | */ | |
261 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
262 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
263 | susphy = true; | |
264 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
265 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
266 | } | |
267 | ||
c36d8e94 FB |
268 | if (cmd == DWC3_DEPCMD_STARTTRANSFER) { |
269 | int needs_wakeup; | |
270 | ||
271 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
272 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
273 | dwc->link_state == DWC3_LINK_STATE_U3); | |
274 | ||
275 | if (unlikely(needs_wakeup)) { | |
276 | ret = __dwc3_gadget_wakeup(dwc); | |
277 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
278 | ret); | |
279 | } | |
280 | } | |
281 | ||
dc1c70a7 FB |
282 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
283 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
284 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
285 | |
286 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
287 | do { | |
288 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
289 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
7b9cc7a2 KL |
290 | int cmd_status = DWC3_DEPCMD_STATUS(reg); |
291 | ||
73815280 FB |
292 | dwc3_trace(trace_dwc3_gadget, |
293 | "Command Complete --> %d", | |
7b9cc7a2 KL |
294 | cmd_status); |
295 | ||
296 | switch (cmd_status) { | |
297 | case 0: | |
298 | ret = 0; | |
299 | break; | |
300 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
301 | dwc3_trace(trace_dwc3_gadget, "%s: no resource available"); | |
302 | ret = -EINVAL; | |
c0ca324d | 303 | break; |
7b9cc7a2 KL |
304 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
305 | /* | |
306 | * SW issues START TRANSFER command to | |
307 | * isochronous ep with future frame interval. If | |
308 | * future interval time has already passed when | |
309 | * core receives the command, it will respond | |
310 | * with an error status of 'Bus Expiry'. | |
311 | * | |
312 | * Instead of always returning -EINVAL, let's | |
313 | * give a hint to the gadget driver that this is | |
314 | * the case by returning -EAGAIN. | |
315 | */ | |
316 | dwc3_trace(trace_dwc3_gadget, "%s: bus expiry"); | |
317 | ret = -EAGAIN; | |
318 | break; | |
319 | default: | |
320 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
321 | } | |
322 | ||
c0ca324d | 323 | break; |
72246da4 FB |
324 | } |
325 | ||
326 | /* | |
72246da4 FB |
327 | * We can't sleep here, because it is also called from |
328 | * interrupt context. | |
329 | */ | |
330 | timeout--; | |
73815280 FB |
331 | if (!timeout) { |
332 | dwc3_trace(trace_dwc3_gadget, | |
333 | "Command Timed Out"); | |
c0ca324d FB |
334 | ret = -ETIMEDOUT; |
335 | break; | |
73815280 | 336 | } |
72246da4 | 337 | |
61d58242 | 338 | udelay(1); |
72246da4 | 339 | } while (1); |
c0ca324d | 340 | |
2b0f11df FB |
341 | if (unlikely(susphy)) { |
342 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
343 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
344 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
345 | } | |
346 | ||
c0ca324d | 347 | return ret; |
72246da4 FB |
348 | } |
349 | ||
350 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 351 | struct dwc3_trb *trb) |
72246da4 | 352 | { |
c439ef87 | 353 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
354 | |
355 | return dep->trb_pool_dma + offset; | |
356 | } | |
357 | ||
358 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
359 | { | |
360 | struct dwc3 *dwc = dep->dwc; | |
361 | ||
362 | if (dep->trb_pool) | |
363 | return 0; | |
364 | ||
72246da4 FB |
365 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
366 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
367 | &dep->trb_pool_dma, GFP_KERNEL); | |
368 | if (!dep->trb_pool) { | |
369 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
370 | dep->name); | |
371 | return -ENOMEM; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
378 | { | |
379 | struct dwc3 *dwc = dep->dwc; | |
380 | ||
381 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
382 | dep->trb_pool, dep->trb_pool_dma); | |
383 | ||
384 | dep->trb_pool = NULL; | |
385 | dep->trb_pool_dma = 0; | |
386 | } | |
387 | ||
c4509601 JY |
388 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
389 | ||
390 | /** | |
391 | * dwc3_gadget_start_config - Configure EP resources | |
392 | * @dwc: pointer to our controller context structure | |
393 | * @dep: endpoint that is being enabled | |
394 | * | |
395 | * The assignment of transfer resources cannot perfectly follow the | |
396 | * data book due to the fact that the controller driver does not have | |
397 | * all knowledge of the configuration in advance. It is given this | |
398 | * information piecemeal by the composite gadget framework after every | |
399 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
400 | * programming model in this scenario can cause errors. For two | |
401 | * reasons: | |
402 | * | |
403 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
404 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
405 | * multiple interfaces. | |
406 | * | |
407 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
408 | * endpoint on alt setting (8.1.6). | |
409 | * | |
410 | * The following simplified method is used instead: | |
411 | * | |
412 | * All hardware endpoints can be assigned a transfer resource and this | |
413 | * setting will stay persistent until either a core reset or | |
414 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
415 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
416 | * guaranteed that there are as many transfer resources as endpoints. | |
417 | * | |
418 | * This function is called for each endpoint when it is being enabled | |
419 | * but is triggered only when called for EP0-out, which always happens | |
420 | * first, and which should only happen in one of the above conditions. | |
421 | */ | |
72246da4 FB |
422 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
423 | { | |
424 | struct dwc3_gadget_ep_cmd_params params; | |
425 | u32 cmd; | |
c4509601 JY |
426 | int i; |
427 | int ret; | |
428 | ||
429 | if (dep->number) | |
430 | return 0; | |
72246da4 FB |
431 | |
432 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 433 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 434 | |
c4509601 JY |
435 | ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
440 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 441 | |
c4509601 JY |
442 | if (!dep) |
443 | continue; | |
444 | ||
445 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
446 | if (ret) | |
447 | return ret; | |
72246da4 FB |
448 | } |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 454 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 455 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 456 | bool ignore, bool restore) |
72246da4 FB |
457 | { |
458 | struct dwc3_gadget_ep_cmd_params params; | |
459 | ||
460 | memset(¶ms, 0x00, sizeof(params)); | |
461 | ||
dc1c70a7 | 462 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
463 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
464 | ||
465 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 466 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
d2e9a13a CP |
467 | u32 burst = dep->endpoint.maxburst - 1; |
468 | ||
469 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
470 | } | |
72246da4 | 471 | |
4b345c9a FB |
472 | if (ignore) |
473 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
474 | ||
265b70a7 PZ |
475 | if (restore) { |
476 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
477 | params.param2 |= dep->saved_state; | |
478 | } | |
479 | ||
dc1c70a7 FB |
480 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
481 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 482 | |
18b7ede5 | 483 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
484 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
485 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
486 | dep->stream_capable = true; |
487 | } | |
488 | ||
0b93a4c8 | 489 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 490 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
491 | |
492 | /* | |
493 | * We are doing 1:1 mapping for endpoints, meaning | |
494 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
495 | * so on. We consider the direction bit as part of the physical | |
496 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
497 | */ | |
dc1c70a7 | 498 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
499 | |
500 | /* | |
501 | * We must use the lower 16 TX FIFOs even though | |
502 | * HW might have more | |
503 | */ | |
504 | if (dep->direction) | |
dc1c70a7 | 505 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
506 | |
507 | if (desc->bInterval) { | |
dc1c70a7 | 508 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
509 | dep->interval = 1 << (desc->bInterval - 1); |
510 | } | |
511 | ||
512 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
513 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
514 | } | |
515 | ||
516 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
517 | { | |
518 | struct dwc3_gadget_ep_cmd_params params; | |
519 | ||
520 | memset(¶ms, 0x00, sizeof(params)); | |
521 | ||
dc1c70a7 | 522 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
523 | |
524 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
525 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
526 | } | |
527 | ||
528 | /** | |
529 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
530 | * @dep: endpoint to be initialized | |
531 | * @desc: USB Endpoint Descriptor | |
532 | * | |
533 | * Caller should take care of locking | |
534 | */ | |
535 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 536 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 537 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 538 | bool ignore, bool restore) |
72246da4 FB |
539 | { |
540 | struct dwc3 *dwc = dep->dwc; | |
541 | u32 reg; | |
b09e99ee | 542 | int ret; |
72246da4 | 543 | |
73815280 | 544 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); |
ff62d6b6 | 545 | |
72246da4 FB |
546 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
547 | ret = dwc3_gadget_start_config(dwc, dep); | |
548 | if (ret) | |
549 | return ret; | |
550 | } | |
551 | ||
265b70a7 PZ |
552 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
553 | restore); | |
72246da4 FB |
554 | if (ret) |
555 | return ret; | |
556 | ||
557 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
558 | struct dwc3_trb *trb_st_hw; |
559 | struct dwc3_trb *trb_link; | |
72246da4 | 560 | |
16e78db7 | 561 | dep->endpoint.desc = desc; |
c90bfaec | 562 | dep->comp_desc = comp_desc; |
72246da4 FB |
563 | dep->type = usb_endpoint_type(desc); |
564 | dep->flags |= DWC3_EP_ENABLED; | |
565 | ||
566 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
567 | reg |= DWC3_DALEPENA_EP(dep->number); | |
568 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
569 | ||
36b68aae | 570 | if (usb_endpoint_xfer_control(desc)) |
e901aa15 | 571 | goto out; |
72246da4 | 572 | |
36b68aae | 573 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
574 | trb_st_hw = &dep->trb_pool[0]; |
575 | ||
f6bafc6a | 576 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
1200a82a | 577 | memset(trb_link, 0, sizeof(*trb_link)); |
72246da4 | 578 | |
f6bafc6a FB |
579 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
580 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
581 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
582 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
583 | } |
584 | ||
e901aa15 | 585 | out: |
aa739974 FB |
586 | switch (usb_endpoint_type(desc)) { |
587 | case USB_ENDPOINT_XFER_CONTROL: | |
e901aa15 | 588 | /* don't change name */ |
aa739974 FB |
589 | break; |
590 | case USB_ENDPOINT_XFER_ISOC: | |
591 | strlcat(dep->name, "-isoc", sizeof(dep->name)); | |
592 | break; | |
593 | case USB_ENDPOINT_XFER_BULK: | |
594 | strlcat(dep->name, "-bulk", sizeof(dep->name)); | |
595 | break; | |
596 | case USB_ENDPOINT_XFER_INT: | |
597 | strlcat(dep->name, "-int", sizeof(dep->name)); | |
598 | break; | |
599 | default: | |
600 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
601 | } | |
602 | ||
72246da4 FB |
603 | return 0; |
604 | } | |
605 | ||
b992e681 | 606 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 607 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
608 | { |
609 | struct dwc3_request *req; | |
610 | ||
aa3342c8 | 611 | if (!list_empty(&dep->started_list)) { |
b992e681 | 612 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 613 | |
57911504 | 614 | /* - giveback all requests to gadget driver */ |
aa3342c8 FB |
615 | while (!list_empty(&dep->started_list)) { |
616 | req = next_request(&dep->started_list); | |
1591633e PA |
617 | |
618 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
619 | } | |
ea53b882 FB |
620 | } |
621 | ||
aa3342c8 FB |
622 | while (!list_empty(&dep->pending_list)) { |
623 | req = next_request(&dep->pending_list); | |
72246da4 | 624 | |
624407f9 | 625 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 626 | } |
72246da4 FB |
627 | } |
628 | ||
629 | /** | |
630 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
631 | * @dep: the endpoint to disable | |
632 | * | |
624407f9 SAS |
633 | * This function also removes requests which are currently processed ny the |
634 | * hardware and those which are not yet scheduled. | |
635 | * Caller should take care of locking. | |
72246da4 | 636 | */ |
72246da4 FB |
637 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
638 | { | |
639 | struct dwc3 *dwc = dep->dwc; | |
640 | u32 reg; | |
641 | ||
7eaeac5c FB |
642 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); |
643 | ||
624407f9 | 644 | dwc3_remove_requests(dwc, dep); |
72246da4 | 645 | |
687ef981 FB |
646 | /* make sure HW endpoint isn't stalled */ |
647 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 648 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 649 | |
72246da4 FB |
650 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
651 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
652 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
653 | ||
879631aa | 654 | dep->stream_capable = false; |
f9c56cdd | 655 | dep->endpoint.desc = NULL; |
c90bfaec | 656 | dep->comp_desc = NULL; |
72246da4 | 657 | dep->type = 0; |
879631aa | 658 | dep->flags = 0; |
72246da4 | 659 | |
aa739974 FB |
660 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", |
661 | dep->number >> 1, | |
662 | (dep->number & 1) ? "in" : "out"); | |
663 | ||
72246da4 FB |
664 | return 0; |
665 | } | |
666 | ||
667 | /* -------------------------------------------------------------------------- */ | |
668 | ||
669 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
670 | const struct usb_endpoint_descriptor *desc) | |
671 | { | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
676 | { | |
677 | return -EINVAL; | |
678 | } | |
679 | ||
680 | /* -------------------------------------------------------------------------- */ | |
681 | ||
682 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
683 | const struct usb_endpoint_descriptor *desc) | |
684 | { | |
685 | struct dwc3_ep *dep; | |
686 | struct dwc3 *dwc; | |
687 | unsigned long flags; | |
688 | int ret; | |
689 | ||
690 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
691 | pr_debug("dwc3: invalid parameters\n"); | |
692 | return -EINVAL; | |
693 | } | |
694 | ||
695 | if (!desc->wMaxPacketSize) { | |
696 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
697 | return -EINVAL; | |
698 | } | |
699 | ||
700 | dep = to_dwc3_ep(ep); | |
701 | dwc = dep->dwc; | |
702 | ||
95ca961c FB |
703 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
704 | "%s is already enabled\n", | |
705 | dep->name)) | |
c6f83f38 | 706 | return 0; |
c6f83f38 | 707 | |
72246da4 | 708 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 709 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
710 | spin_unlock_irqrestore(&dwc->lock, flags); |
711 | ||
712 | return ret; | |
713 | } | |
714 | ||
715 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
716 | { | |
717 | struct dwc3_ep *dep; | |
718 | struct dwc3 *dwc; | |
719 | unsigned long flags; | |
720 | int ret; | |
721 | ||
722 | if (!ep) { | |
723 | pr_debug("dwc3: invalid parameters\n"); | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
727 | dep = to_dwc3_ep(ep); | |
728 | dwc = dep->dwc; | |
729 | ||
95ca961c FB |
730 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
731 | "%s is already disabled\n", | |
732 | dep->name)) | |
72246da4 | 733 | return 0; |
72246da4 | 734 | |
72246da4 FB |
735 | spin_lock_irqsave(&dwc->lock, flags); |
736 | ret = __dwc3_gadget_ep_disable(dep); | |
737 | spin_unlock_irqrestore(&dwc->lock, flags); | |
738 | ||
739 | return ret; | |
740 | } | |
741 | ||
742 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
743 | gfp_t gfp_flags) | |
744 | { | |
745 | struct dwc3_request *req; | |
746 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
747 | |
748 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 749 | if (!req) |
72246da4 | 750 | return NULL; |
72246da4 FB |
751 | |
752 | req->epnum = dep->number; | |
753 | req->dep = dep; | |
72246da4 | 754 | |
2c4cbe6e FB |
755 | trace_dwc3_alloc_request(req); |
756 | ||
72246da4 FB |
757 | return &req->request; |
758 | } | |
759 | ||
760 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
761 | struct usb_request *request) | |
762 | { | |
763 | struct dwc3_request *req = to_dwc3_request(request); | |
764 | ||
2c4cbe6e | 765 | trace_dwc3_free_request(req); |
72246da4 FB |
766 | kfree(req); |
767 | } | |
768 | ||
c71fc37c FB |
769 | /** |
770 | * dwc3_prepare_one_trb - setup one TRB from one request | |
771 | * @dep: endpoint for which this request is prepared | |
772 | * @req: dwc3_request pointer | |
773 | */ | |
68e823e2 | 774 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 775 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 776 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 777 | { |
f6bafc6a | 778 | struct dwc3_trb *trb; |
c71fc37c | 779 | |
73815280 | 780 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s", |
eeb720fb FB |
781 | dep->name, req, (unsigned long long) dma, |
782 | length, last ? " last" : "", | |
783 | chain ? " chain" : ""); | |
784 | ||
915e202a | 785 | |
4faf7550 | 786 | trb = &dep->trb_pool[dep->trb_enqueue]; |
c71fc37c | 787 | |
eeb720fb | 788 | if (!req->trb) { |
aa3342c8 | 789 | dwc3_gadget_move_started_request(req); |
f6bafc6a FB |
790 | req->trb = trb; |
791 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
4faf7550 | 792 | req->first_trb_index = dep->trb_enqueue; |
eeb720fb | 793 | } |
c71fc37c | 794 | |
ef966b9d | 795 | dwc3_ep_inc_enq(dep); |
36b68aae FB |
796 | /* Skip the LINK-TRB */ |
797 | if (dwc3_ep_is_last_trb(dep->trb_enqueue)) | |
ef966b9d | 798 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 799 | |
f6bafc6a FB |
800 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
801 | trb->bpl = lower_32_bits(dma); | |
802 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 803 | |
16e78db7 | 804 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 805 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 806 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
807 | break; |
808 | ||
809 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
810 | if (!node) |
811 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
812 | else | |
813 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
ca4d44ea FB |
814 | |
815 | /* always enable Interrupt on Missed ISOC */ | |
816 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
817 | break; |
818 | ||
819 | case USB_ENDPOINT_XFER_BULK: | |
820 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 821 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
822 | break; |
823 | default: | |
824 | /* | |
825 | * This is only possible with faulty memory because we | |
826 | * checked it already :) | |
827 | */ | |
828 | BUG(); | |
829 | } | |
830 | ||
ca4d44ea FB |
831 | /* always enable Continue on Short Packet */ |
832 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
f3af3651 | 833 | |
8e7046b7 | 834 | if (!req->request.no_interrupt && !chain) |
ca4d44ea FB |
835 | trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI; |
836 | ||
837 | if (last) | |
e5ba5ec8 | 838 | trb->ctrl |= DWC3_TRB_CTRL_LST; |
c71fc37c | 839 | |
e5ba5ec8 PA |
840 | if (chain) |
841 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
842 | ||
16e78db7 | 843 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 844 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 845 | |
f6bafc6a | 846 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
847 | |
848 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
849 | } |
850 | ||
72246da4 FB |
851 | /* |
852 | * dwc3_prepare_trbs - setup TRBs from requests | |
853 | * @dep: endpoint for which requests are being prepared | |
854 | * @starting: true if the endpoint is idle and no requests are queued. | |
855 | * | |
1d046793 PZ |
856 | * The function goes through the requests list and sets up TRBs for the |
857 | * transfers. The function returns once there are no more TRBs available or | |
858 | * it runs out of requests. | |
72246da4 | 859 | */ |
68e823e2 | 860 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 861 | { |
68e823e2 | 862 | struct dwc3_request *req, *n; |
72246da4 | 863 | u32 trbs_left; |
c71fc37c | 864 | unsigned int last_one = 0; |
72246da4 FB |
865 | |
866 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
867 | ||
4faf7550 | 868 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; |
c71fc37c | 869 | |
72246da4 | 870 | /* |
36b68aae FB |
871 | * If enqueue & dequeue are equal than it is either full or empty. If we |
872 | * are starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
873 | * full and don't do anything |
874 | */ | |
875 | if (!trbs_left) { | |
876 | if (!starting) | |
68e823e2 | 877 | return; |
36b68aae | 878 | |
72246da4 | 879 | trbs_left = DWC3_TRB_NUM; |
72246da4 FB |
880 | } |
881 | ||
882 | /* The last TRB is a link TRB, not used for xfer */ | |
36b68aae | 883 | if (trbs_left <= 1) |
68e823e2 | 884 | return; |
72246da4 | 885 | |
aa3342c8 | 886 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
eeb720fb FB |
887 | unsigned length; |
888 | dma_addr_t dma; | |
e5ba5ec8 | 889 | last_one = false; |
72246da4 | 890 | |
eeb720fb FB |
891 | if (req->request.num_mapped_sgs > 0) { |
892 | struct usb_request *request = &req->request; | |
893 | struct scatterlist *sg = request->sg; | |
894 | struct scatterlist *s; | |
895 | int i; | |
72246da4 | 896 | |
eeb720fb FB |
897 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
898 | unsigned chain = true; | |
72246da4 | 899 | |
eeb720fb FB |
900 | length = sg_dma_len(s); |
901 | dma = sg_dma_address(s); | |
72246da4 | 902 | |
1d046793 PZ |
903 | if (i == (request->num_mapped_sgs - 1) || |
904 | sg_is_last(s)) { | |
aa3342c8 | 905 | if (list_empty(&dep->pending_list)) |
e5ba5ec8 | 906 | last_one = true; |
eeb720fb FB |
907 | chain = false; |
908 | } | |
72246da4 | 909 | |
eeb720fb FB |
910 | trbs_left--; |
911 | if (!trbs_left) | |
912 | last_one = true; | |
72246da4 | 913 | |
eeb720fb FB |
914 | if (last_one) |
915 | chain = false; | |
72246da4 | 916 | |
eeb720fb | 917 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 918 | last_one, chain, i); |
72246da4 | 919 | |
eeb720fb FB |
920 | if (last_one) |
921 | break; | |
922 | } | |
39e60635 AV |
923 | |
924 | if (last_one) | |
925 | break; | |
72246da4 | 926 | } else { |
eeb720fb FB |
927 | dma = req->request.dma; |
928 | length = req->request.length; | |
929 | trbs_left--; | |
72246da4 | 930 | |
eeb720fb FB |
931 | if (!trbs_left) |
932 | last_one = 1; | |
879631aa | 933 | |
eeb720fb | 934 | /* Is this the last request? */ |
aa3342c8 | 935 | if (list_is_last(&req->list, &dep->pending_list)) |
eeb720fb | 936 | last_one = 1; |
72246da4 | 937 | |
eeb720fb | 938 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 939 | last_one, false, 0); |
72246da4 | 940 | |
eeb720fb FB |
941 | if (last_one) |
942 | break; | |
72246da4 | 943 | } |
72246da4 | 944 | } |
72246da4 FB |
945 | } |
946 | ||
947 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
948 | int start_new) | |
949 | { | |
950 | struct dwc3_gadget_ep_cmd_params params; | |
951 | struct dwc3_request *req; | |
952 | struct dwc3 *dwc = dep->dwc; | |
953 | int ret; | |
954 | u32 cmd; | |
955 | ||
956 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
73815280 | 957 | dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name); |
72246da4 FB |
958 | return -EBUSY; |
959 | } | |
72246da4 FB |
960 | |
961 | /* | |
962 | * If we are getting here after a short-out-packet we don't enqueue any | |
963 | * new requests as we try to set the IOC bit only on the last request. | |
964 | */ | |
965 | if (start_new) { | |
aa3342c8 | 966 | if (list_empty(&dep->started_list)) |
72246da4 FB |
967 | dwc3_prepare_trbs(dep, start_new); |
968 | ||
969 | /* req points to the first request which will be sent */ | |
aa3342c8 | 970 | req = next_request(&dep->started_list); |
72246da4 | 971 | } else { |
68e823e2 FB |
972 | dwc3_prepare_trbs(dep, start_new); |
973 | ||
72246da4 | 974 | /* |
1d046793 | 975 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 976 | */ |
aa3342c8 | 977 | req = next_request(&dep->started_list); |
72246da4 FB |
978 | } |
979 | if (!req) { | |
980 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
981 | return 0; | |
982 | } | |
983 | ||
984 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 985 | |
1877d6c9 PA |
986 | if (start_new) { |
987 | params.param0 = upper_32_bits(req->trb_dma); | |
988 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 989 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 990 | } else { |
72246da4 | 991 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 992 | } |
72246da4 FB |
993 | |
994 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
995 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
996 | if (ret < 0) { | |
72246da4 FB |
997 | /* |
998 | * FIXME we need to iterate over the list of requests | |
999 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1000 | * requests instead of what we do now. |
72246da4 | 1001 | */ |
0fc9a1be FB |
1002 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
1003 | req->direction); | |
72246da4 FB |
1004 | list_del(&req->list); |
1005 | return ret; | |
1006 | } | |
1007 | ||
1008 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1009 | |
f898ae09 | 1010 | if (start_new) { |
b4996a86 | 1011 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1012 | dep->number); |
b4996a86 | 1013 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1014 | } |
25b8ff68 | 1015 | |
72246da4 FB |
1016 | return 0; |
1017 | } | |
1018 | ||
d6d6ec7b PA |
1019 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1020 | struct dwc3_ep *dep, u32 cur_uf) | |
1021 | { | |
1022 | u32 uf; | |
1023 | ||
aa3342c8 | 1024 | if (list_empty(&dep->pending_list)) { |
73815280 FB |
1025 | dwc3_trace(trace_dwc3_gadget, |
1026 | "ISOC ep %s run out for requests", | |
1027 | dep->name); | |
f4a53c55 | 1028 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1029 | return; |
1030 | } | |
1031 | ||
1032 | /* 4 micro frames in the future */ | |
1033 | uf = cur_uf + dep->interval * 4; | |
1034 | ||
1035 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1036 | } | |
1037 | ||
1038 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1039 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1040 | { | |
1041 | u32 cur_uf, mask; | |
1042 | ||
1043 | mask = ~(dep->interval - 1); | |
1044 | cur_uf = event->parameters & mask; | |
1045 | ||
1046 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1047 | } | |
1048 | ||
72246da4 FB |
1049 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1050 | { | |
0fc9a1be FB |
1051 | struct dwc3 *dwc = dep->dwc; |
1052 | int ret; | |
1053 | ||
bb423984 | 1054 | if (!dep->endpoint.desc) { |
ec5e795c FB |
1055 | dwc3_trace(trace_dwc3_gadget, |
1056 | "trying to queue request %p to disabled %s\n", | |
bb423984 FB |
1057 | &req->request, dep->endpoint.name); |
1058 | return -ESHUTDOWN; | |
1059 | } | |
1060 | ||
1061 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1062 | &req->request, req->dep->name)) { | |
ec5e795c FB |
1063 | dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n", |
1064 | &req->request, req->dep->name); | |
bb423984 FB |
1065 | return -EINVAL; |
1066 | } | |
1067 | ||
72246da4 FB |
1068 | req->request.actual = 0; |
1069 | req->request.status = -EINPROGRESS; | |
1070 | req->direction = dep->direction; | |
1071 | req->epnum = dep->number; | |
1072 | ||
fe84f522 FB |
1073 | trace_dwc3_ep_queue(req); |
1074 | ||
72246da4 FB |
1075 | /* |
1076 | * We only add to our list of requests now and | |
1077 | * start consuming the list once we get XferNotReady | |
1078 | * IRQ. | |
1079 | * | |
1080 | * That way, we avoid doing anything that we don't need | |
1081 | * to do now and defer it until the point we receive a | |
1082 | * particular token from the Host side. | |
1083 | * | |
1084 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1085 | * many NAKs. |
72246da4 | 1086 | */ |
0fc9a1be FB |
1087 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1088 | dep->direction); | |
1089 | if (ret) | |
1090 | return ret; | |
1091 | ||
aa3342c8 | 1092 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1093 | |
1d6a3918 FB |
1094 | /* |
1095 | * If there are no pending requests and the endpoint isn't already | |
1096 | * busy, we will just start the request straight away. | |
1097 | * | |
1098 | * This will save one IRQ (XFER_NOT_READY) and possibly make it a | |
1099 | * little bit faster. | |
1100 | */ | |
1101 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
62e345ae | 1102 | !usb_endpoint_xfer_int(dep->endpoint.desc) && |
1d6a3918 FB |
1103 | !(dep->flags & DWC3_EP_BUSY)) { |
1104 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); | |
a8f32817 | 1105 | goto out; |
1d6a3918 FB |
1106 | } |
1107 | ||
72246da4 | 1108 | /* |
b511e5e7 | 1109 | * There are a few special cases: |
72246da4 | 1110 | * |
f898ae09 PZ |
1111 | * 1. XferNotReady with empty list of requests. We need to kick the |
1112 | * transfer here in that situation, otherwise we will be NAKing | |
1113 | * forever. If we get XferNotReady before gadget driver has a | |
1114 | * chance to queue a request, we will ACK the IRQ but won't be | |
1115 | * able to receive the data until the next request is queued. | |
1116 | * The following code is handling exactly that. | |
72246da4 | 1117 | * |
72246da4 FB |
1118 | */ |
1119 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1120 | /* |
1121 | * If xfernotready is already elapsed and it is a case | |
1122 | * of isoc transfer, then issue END TRANSFER, so that | |
1123 | * you can receive xfernotready again and can have | |
1124 | * notion of current microframe. | |
1125 | */ | |
1126 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
aa3342c8 | 1127 | if (list_empty(&dep->started_list)) { |
b992e681 | 1128 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1129 | dep->flags = DWC3_EP_ENABLED; |
1130 | } | |
f4a53c55 PA |
1131 | return 0; |
1132 | } | |
1133 | ||
b511e5e7 | 1134 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
89185916 FB |
1135 | if (!ret) |
1136 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1137 | ||
a8f32817 | 1138 | goto out; |
b511e5e7 | 1139 | } |
72246da4 | 1140 | |
b511e5e7 FB |
1141 | /* |
1142 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1143 | * kick the transfer here after queuing a request, otherwise the | |
1144 | * core may not see the modified TRB(s). | |
1145 | */ | |
1146 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1147 | (dep->flags & DWC3_EP_BUSY) && |
1148 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1149 | WARN_ON_ONCE(!dep->resource_index); |
1150 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1151 | false); |
a8f32817 | 1152 | goto out; |
a0925324 | 1153 | } |
72246da4 | 1154 | |
b997ada5 FB |
1155 | /* |
1156 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1157 | * right away, otherwise host will not know we have streams to be | |
1158 | * handled. | |
1159 | */ | |
a8f32817 | 1160 | if (dep->stream_capable) |
b997ada5 | 1161 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
b997ada5 | 1162 | |
a8f32817 FB |
1163 | out: |
1164 | if (ret && ret != -EBUSY) | |
ec5e795c FB |
1165 | dwc3_trace(trace_dwc3_gadget, |
1166 | "%s: failed to kick transfers\n", | |
a8f32817 FB |
1167 | dep->name); |
1168 | if (ret == -EBUSY) | |
1169 | ret = 0; | |
1170 | ||
1171 | return ret; | |
72246da4 FB |
1172 | } |
1173 | ||
04c03d10 FB |
1174 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, |
1175 | struct usb_request *request) | |
1176 | { | |
1177 | dwc3_gadget_ep_free_request(ep, request); | |
1178 | } | |
1179 | ||
1180 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1181 | { | |
1182 | struct dwc3_request *req; | |
1183 | struct usb_request *request; | |
1184 | struct usb_ep *ep = &dep->endpoint; | |
1185 | ||
1186 | dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n"); | |
1187 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); | |
1188 | if (!request) | |
1189 | return -ENOMEM; | |
1190 | ||
1191 | request->length = 0; | |
1192 | request->buf = dwc->zlp_buf; | |
1193 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1194 | ||
1195 | req = to_dwc3_request(request); | |
1196 | ||
1197 | return __dwc3_gadget_ep_queue(dep, req); | |
1198 | } | |
1199 | ||
72246da4 FB |
1200 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, |
1201 | gfp_t gfp_flags) | |
1202 | { | |
1203 | struct dwc3_request *req = to_dwc3_request(request); | |
1204 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1205 | struct dwc3 *dwc = dep->dwc; | |
1206 | ||
1207 | unsigned long flags; | |
1208 | ||
1209 | int ret; | |
1210 | ||
fdee4eba | 1211 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1212 | ret = __dwc3_gadget_ep_queue(dep, req); |
04c03d10 FB |
1213 | |
1214 | /* | |
1215 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1216 | * setting request->zero, instead of doing magic, we will just queue an | |
1217 | * extra usb_request ourselves so that it gets handled the same way as | |
1218 | * any other request. | |
1219 | */ | |
d9261898 JY |
1220 | if (ret == 0 && request->zero && request->length && |
1221 | (request->length % ep->maxpacket == 0)) | |
04c03d10 FB |
1222 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); |
1223 | ||
72246da4 FB |
1224 | spin_unlock_irqrestore(&dwc->lock, flags); |
1225 | ||
1226 | return ret; | |
1227 | } | |
1228 | ||
1229 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1230 | struct usb_request *request) | |
1231 | { | |
1232 | struct dwc3_request *req = to_dwc3_request(request); | |
1233 | struct dwc3_request *r = NULL; | |
1234 | ||
1235 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1236 | struct dwc3 *dwc = dep->dwc; | |
1237 | ||
1238 | unsigned long flags; | |
1239 | int ret = 0; | |
1240 | ||
2c4cbe6e FB |
1241 | trace_dwc3_ep_dequeue(req); |
1242 | ||
72246da4 FB |
1243 | spin_lock_irqsave(&dwc->lock, flags); |
1244 | ||
aa3342c8 | 1245 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1246 | if (r == req) |
1247 | break; | |
1248 | } | |
1249 | ||
1250 | if (r != req) { | |
aa3342c8 | 1251 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1252 | if (r == req) |
1253 | break; | |
1254 | } | |
1255 | if (r == req) { | |
1256 | /* wait until it is processed */ | |
b992e681 | 1257 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1258 | goto out1; |
72246da4 FB |
1259 | } |
1260 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1261 | request, ep->name); | |
1262 | ret = -EINVAL; | |
1263 | goto out0; | |
1264 | } | |
1265 | ||
e8d4e8be | 1266 | out1: |
72246da4 FB |
1267 | /* giveback the request */ |
1268 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1269 | ||
1270 | out0: | |
1271 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1272 | ||
1273 | return ret; | |
1274 | } | |
1275 | ||
7a608559 | 1276 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1277 | { |
1278 | struct dwc3_gadget_ep_cmd_params params; | |
1279 | struct dwc3 *dwc = dep->dwc; | |
1280 | int ret; | |
1281 | ||
5ad02fb8 FB |
1282 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1283 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1284 | return -EINVAL; | |
1285 | } | |
1286 | ||
72246da4 FB |
1287 | memset(¶ms, 0x00, sizeof(params)); |
1288 | ||
1289 | if (value) { | |
7a608559 | 1290 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
aa3342c8 FB |
1291 | (!list_empty(&dep->started_list) || |
1292 | !list_empty(&dep->pending_list)))) { | |
ec5e795c | 1293 | dwc3_trace(trace_dwc3_gadget, |
052ba52e | 1294 | "%s: pending request, cannot halt", |
7a608559 FB |
1295 | dep->name); |
1296 | return -EAGAIN; | |
1297 | } | |
1298 | ||
72246da4 FB |
1299 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1300 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1301 | if (ret) | |
3f89204b | 1302 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1303 | dep->name); |
1304 | else | |
1305 | dep->flags |= DWC3_EP_STALL; | |
1306 | } else { | |
1307 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1308 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1309 | if (ret) | |
3f89204b | 1310 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1311 | dep->name); |
1312 | else | |
a535d81c | 1313 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1314 | } |
5275455a | 1315 | |
72246da4 FB |
1316 | return ret; |
1317 | } | |
1318 | ||
1319 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1320 | { | |
1321 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1322 | struct dwc3 *dwc = dep->dwc; | |
1323 | ||
1324 | unsigned long flags; | |
1325 | ||
1326 | int ret; | |
1327 | ||
1328 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1329 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1330 | spin_unlock_irqrestore(&dwc->lock, flags); |
1331 | ||
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1336 | { | |
1337 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1338 | struct dwc3 *dwc = dep->dwc; |
1339 | unsigned long flags; | |
95aa4e8d | 1340 | int ret; |
72246da4 | 1341 | |
249a4569 | 1342 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1343 | dep->flags |= DWC3_EP_WEDGE; |
1344 | ||
08f0d966 | 1345 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1346 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1347 | else |
7a608559 | 1348 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1349 | spin_unlock_irqrestore(&dwc->lock, flags); |
1350 | ||
1351 | return ret; | |
72246da4 FB |
1352 | } |
1353 | ||
1354 | /* -------------------------------------------------------------------------- */ | |
1355 | ||
1356 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1357 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1358 | .bDescriptorType = USB_DT_ENDPOINT, | |
1359 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1360 | }; | |
1361 | ||
1362 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1363 | .enable = dwc3_gadget_ep0_enable, | |
1364 | .disable = dwc3_gadget_ep0_disable, | |
1365 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1366 | .free_request = dwc3_gadget_ep_free_request, | |
1367 | .queue = dwc3_gadget_ep0_queue, | |
1368 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1369 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1370 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1371 | }; | |
1372 | ||
1373 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1374 | .enable = dwc3_gadget_ep_enable, | |
1375 | .disable = dwc3_gadget_ep_disable, | |
1376 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1377 | .free_request = dwc3_gadget_ep_free_request, | |
1378 | .queue = dwc3_gadget_ep_queue, | |
1379 | .dequeue = dwc3_gadget_ep_dequeue, | |
1380 | .set_halt = dwc3_gadget_ep_set_halt, | |
1381 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1382 | }; | |
1383 | ||
1384 | /* -------------------------------------------------------------------------- */ | |
1385 | ||
1386 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1387 | { | |
1388 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1389 | u32 reg; | |
1390 | ||
1391 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1392 | return DWC3_DSTS_SOFFN(reg); | |
1393 | } | |
1394 | ||
218ef7b6 | 1395 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1396 | { |
72246da4 | 1397 | unsigned long timeout; |
72246da4 | 1398 | |
218ef7b6 | 1399 | int ret; |
72246da4 FB |
1400 | u32 reg; |
1401 | ||
72246da4 FB |
1402 | u8 link_state; |
1403 | u8 speed; | |
1404 | ||
72246da4 FB |
1405 | /* |
1406 | * According to the Databook Remote wakeup request should | |
1407 | * be issued only when the device is in early suspend state. | |
1408 | * | |
1409 | * We can check that via USB Link State bits in DSTS register. | |
1410 | */ | |
1411 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1412 | ||
1413 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c JY |
1414 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
1415 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) { | |
ec5e795c | 1416 | dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n"); |
218ef7b6 | 1417 | return -EINVAL; |
72246da4 FB |
1418 | } |
1419 | ||
1420 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1421 | ||
1422 | switch (link_state) { | |
1423 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1424 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1425 | break; | |
1426 | default: | |
ec5e795c FB |
1427 | dwc3_trace(trace_dwc3_gadget, |
1428 | "can't wakeup from '%s'\n", | |
1429 | dwc3_gadget_link_string(link_state)); | |
218ef7b6 | 1430 | return -EINVAL; |
72246da4 FB |
1431 | } |
1432 | ||
8598bde7 FB |
1433 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1434 | if (ret < 0) { | |
1435 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1436 | return ret; |
8598bde7 | 1437 | } |
72246da4 | 1438 | |
802fde98 PZ |
1439 | /* Recent versions do this automatically */ |
1440 | if (dwc->revision < DWC3_REVISION_194A) { | |
1441 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1442 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1443 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1444 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1445 | } | |
72246da4 | 1446 | |
1d046793 | 1447 | /* poll until Link State changes to ON */ |
72246da4 FB |
1448 | timeout = jiffies + msecs_to_jiffies(100); |
1449 | ||
1d046793 | 1450 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1451 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1452 | ||
1453 | /* in HS, means ON */ | |
1454 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1455 | break; | |
1456 | } | |
1457 | ||
1458 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1459 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1460 | return -EINVAL; |
72246da4 FB |
1461 | } |
1462 | ||
218ef7b6 FB |
1463 | return 0; |
1464 | } | |
1465 | ||
1466 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1467 | { | |
1468 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1469 | unsigned long flags; | |
1470 | int ret; | |
1471 | ||
1472 | spin_lock_irqsave(&dwc->lock, flags); | |
1473 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1474 | spin_unlock_irqrestore(&dwc->lock, flags); |
1475 | ||
1476 | return ret; | |
1477 | } | |
1478 | ||
1479 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1480 | int is_selfpowered) | |
1481 | { | |
1482 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1483 | unsigned long flags; |
72246da4 | 1484 | |
249a4569 | 1485 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1486 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1487 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
7b2a0368 | 1492 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1493 | { |
1494 | u32 reg; | |
61d58242 | 1495 | u32 timeout = 500; |
72246da4 FB |
1496 | |
1497 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1498 | if (is_on) { |
802fde98 PZ |
1499 | if (dwc->revision <= DWC3_REVISION_187A) { |
1500 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1501 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1502 | } | |
1503 | ||
1504 | if (dwc->revision >= DWC3_REVISION_194A) | |
1505 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1506 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1507 | |
1508 | if (dwc->has_hibernation) | |
1509 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1510 | ||
9fcb3bd8 | 1511 | dwc->pullups_connected = true; |
8db7ed15 | 1512 | } else { |
72246da4 | 1513 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1514 | |
1515 | if (dwc->has_hibernation && !suspend) | |
1516 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1517 | ||
9fcb3bd8 | 1518 | dwc->pullups_connected = false; |
8db7ed15 | 1519 | } |
72246da4 FB |
1520 | |
1521 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1522 | ||
1523 | do { | |
1524 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1525 | if (is_on) { | |
1526 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1527 | break; | |
1528 | } else { | |
1529 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1530 | break; | |
1531 | } | |
72246da4 FB |
1532 | timeout--; |
1533 | if (!timeout) | |
6f17f74b | 1534 | return -ETIMEDOUT; |
61d58242 | 1535 | udelay(1); |
72246da4 FB |
1536 | } while (1); |
1537 | ||
73815280 | 1538 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", |
72246da4 FB |
1539 | dwc->gadget_driver |
1540 | ? dwc->gadget_driver->function : "no-function", | |
1541 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1542 | |
1543 | return 0; | |
72246da4 FB |
1544 | } |
1545 | ||
1546 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1547 | { | |
1548 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1549 | unsigned long flags; | |
6f17f74b | 1550 | int ret; |
72246da4 FB |
1551 | |
1552 | is_on = !!is_on; | |
1553 | ||
1554 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1555 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1556 | spin_unlock_irqrestore(&dwc->lock, flags); |
1557 | ||
6f17f74b | 1558 | return ret; |
72246da4 FB |
1559 | } |
1560 | ||
8698e2ac FB |
1561 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1562 | { | |
1563 | u32 reg; | |
1564 | ||
1565 | /* Enable all but Start and End of Frame IRQs */ | |
1566 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1567 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1568 | DWC3_DEVTEN_CMDCMPLTEN | | |
1569 | DWC3_DEVTEN_ERRTICERREN | | |
1570 | DWC3_DEVTEN_WKUPEVTEN | | |
1571 | DWC3_DEVTEN_ULSTCNGEN | | |
1572 | DWC3_DEVTEN_CONNECTDONEEN | | |
1573 | DWC3_DEVTEN_USBRSTEN | | |
1574 | DWC3_DEVTEN_DISCONNEVTEN); | |
1575 | ||
1576 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1577 | } | |
1578 | ||
1579 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1580 | { | |
1581 | /* mask all interrupts */ | |
1582 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1583 | } | |
1584 | ||
1585 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1586 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1587 | |
72246da4 FB |
1588 | static int dwc3_gadget_start(struct usb_gadget *g, |
1589 | struct usb_gadget_driver *driver) | |
1590 | { | |
1591 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1592 | struct dwc3_ep *dep; | |
1593 | unsigned long flags; | |
1594 | int ret = 0; | |
8698e2ac | 1595 | int irq; |
72246da4 FB |
1596 | u32 reg; |
1597 | ||
b0d7ffd4 FB |
1598 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1599 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
dea520a4 | 1600 | IRQF_SHARED, "dwc3", dwc->ev_buf); |
b0d7ffd4 FB |
1601 | if (ret) { |
1602 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1603 | irq, ret); | |
1604 | goto err0; | |
1605 | } | |
1606 | ||
72246da4 FB |
1607 | spin_lock_irqsave(&dwc->lock, flags); |
1608 | ||
1609 | if (dwc->gadget_driver) { | |
1610 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1611 | dwc->gadget.name, | |
1612 | dwc->gadget_driver->driver.name); | |
1613 | ret = -EBUSY; | |
b0d7ffd4 | 1614 | goto err1; |
72246da4 FB |
1615 | } |
1616 | ||
1617 | dwc->gadget_driver = driver; | |
72246da4 | 1618 | |
72246da4 FB |
1619 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1620 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1621 | |
1622 | /** | |
1623 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1624 | * which would cause metastability state on Run/Stop | |
1625 | * bit if we try to force the IP to USB2-only mode. | |
1626 | * | |
1627 | * Because of that, we cannot configure the IP to any | |
1628 | * speed other than the SuperSpeed | |
1629 | * | |
1630 | * Refers to: | |
1631 | * | |
1632 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1633 | * USB 2.0 Mode | |
1634 | */ | |
f7e846f0 | 1635 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1636 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1637 | } else { |
1638 | switch (dwc->maximum_speed) { | |
1639 | case USB_SPEED_LOW: | |
1640 | reg |= DWC3_DSTS_LOWSPEED; | |
1641 | break; | |
1642 | case USB_SPEED_FULL: | |
1643 | reg |= DWC3_DSTS_FULLSPEED1; | |
1644 | break; | |
1645 | case USB_SPEED_HIGH: | |
1646 | reg |= DWC3_DSTS_HIGHSPEED; | |
1647 | break; | |
7580862b JY |
1648 | case USB_SPEED_SUPER_PLUS: |
1649 | reg |= DWC3_DSTS_SUPERSPEED_PLUS; | |
1650 | break; | |
f7e846f0 | 1651 | default: |
77966eb8 JY |
1652 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1653 | dwc->maximum_speed); | |
1654 | /* fall through */ | |
1655 | case USB_SPEED_SUPER: | |
1656 | reg |= DWC3_DCFG_SUPERSPEED; | |
1657 | break; | |
f7e846f0 FB |
1658 | } |
1659 | } | |
72246da4 FB |
1660 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1661 | ||
1662 | /* Start with SuperSpeed Default */ | |
1663 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1664 | ||
1665 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1666 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1667 | false); | |
72246da4 FB |
1668 | if (ret) { |
1669 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1670 | goto err2; |
72246da4 FB |
1671 | } |
1672 | ||
1673 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1674 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1675 | false); | |
72246da4 FB |
1676 | if (ret) { |
1677 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1678 | goto err3; |
72246da4 FB |
1679 | } |
1680 | ||
1681 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1682 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1683 | dwc3_ep0_out_start(dwc); |
1684 | ||
8698e2ac FB |
1685 | dwc3_gadget_enable_irq(dwc); |
1686 | ||
72246da4 FB |
1687 | spin_unlock_irqrestore(&dwc->lock, flags); |
1688 | ||
1689 | return 0; | |
1690 | ||
b0d7ffd4 | 1691 | err3: |
72246da4 FB |
1692 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1693 | ||
b0d7ffd4 | 1694 | err2: |
cdcedd69 | 1695 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1696 | |
1697 | err1: | |
72246da4 FB |
1698 | spin_unlock_irqrestore(&dwc->lock, flags); |
1699 | ||
dea520a4 | 1700 | free_irq(irq, dwc->ev_buf); |
b0d7ffd4 FB |
1701 | |
1702 | err0: | |
72246da4 FB |
1703 | return ret; |
1704 | } | |
1705 | ||
22835b80 | 1706 | static int dwc3_gadget_stop(struct usb_gadget *g) |
72246da4 FB |
1707 | { |
1708 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1709 | unsigned long flags; | |
8698e2ac | 1710 | int irq; |
72246da4 FB |
1711 | |
1712 | spin_lock_irqsave(&dwc->lock, flags); | |
1713 | ||
8698e2ac | 1714 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1715 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1716 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1717 | ||
1718 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1719 | |
1720 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1721 | ||
b0d7ffd4 | 1722 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
dea520a4 | 1723 | free_irq(irq, dwc->ev_buf); |
b0d7ffd4 | 1724 | |
72246da4 FB |
1725 | return 0; |
1726 | } | |
802fde98 | 1727 | |
72246da4 FB |
1728 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1729 | .get_frame = dwc3_gadget_get_frame, | |
1730 | .wakeup = dwc3_gadget_wakeup, | |
1731 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1732 | .pullup = dwc3_gadget_pullup, | |
1733 | .udc_start = dwc3_gadget_start, | |
1734 | .udc_stop = dwc3_gadget_stop, | |
1735 | }; | |
1736 | ||
1737 | /* -------------------------------------------------------------------------- */ | |
1738 | ||
6a1e3ef4 FB |
1739 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1740 | u8 num, u32 direction) | |
72246da4 FB |
1741 | { |
1742 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1743 | u8 i; |
72246da4 | 1744 | |
6a1e3ef4 FB |
1745 | for (i = 0; i < num; i++) { |
1746 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1747 | |
72246da4 | 1748 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1749 | if (!dep) |
72246da4 | 1750 | return -ENOMEM; |
72246da4 FB |
1751 | |
1752 | dep->dwc = dwc; | |
1753 | dep->number = epnum; | |
9aa62ae4 | 1754 | dep->direction = !!direction; |
72246da4 FB |
1755 | dwc->eps[epnum] = dep; |
1756 | ||
1757 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1758 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1759 | |
72246da4 | 1760 | dep->endpoint.name = dep->name; |
72246da4 | 1761 | |
73815280 | 1762 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); |
653df35e | 1763 | |
72246da4 | 1764 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1765 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1766 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1767 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1768 | if (!epnum) | |
1769 | dwc->gadget.ep0 = &dep->endpoint; | |
1770 | } else { | |
1771 | int ret; | |
1772 | ||
e117e742 | 1773 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1774 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1775 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1776 | list_add_tail(&dep->endpoint.ep_list, | |
1777 | &dwc->gadget.ep_list); | |
1778 | ||
1779 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1780 | if (ret) |
72246da4 | 1781 | return ret; |
72246da4 | 1782 | } |
25b8ff68 | 1783 | |
a474d3b7 RB |
1784 | if (epnum == 0 || epnum == 1) { |
1785 | dep->endpoint.caps.type_control = true; | |
1786 | } else { | |
1787 | dep->endpoint.caps.type_iso = true; | |
1788 | dep->endpoint.caps.type_bulk = true; | |
1789 | dep->endpoint.caps.type_int = true; | |
1790 | } | |
1791 | ||
1792 | dep->endpoint.caps.dir_in = !!direction; | |
1793 | dep->endpoint.caps.dir_out = !direction; | |
1794 | ||
aa3342c8 FB |
1795 | INIT_LIST_HEAD(&dep->pending_list); |
1796 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
1797 | } |
1798 | ||
1799 | return 0; | |
1800 | } | |
1801 | ||
6a1e3ef4 FB |
1802 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1803 | { | |
1804 | int ret; | |
1805 | ||
1806 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1807 | ||
1808 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1809 | if (ret < 0) { | |
73815280 FB |
1810 | dwc3_trace(trace_dwc3_gadget, |
1811 | "failed to allocate OUT endpoints"); | |
6a1e3ef4 FB |
1812 | return ret; |
1813 | } | |
1814 | ||
1815 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1816 | if (ret < 0) { | |
73815280 FB |
1817 | dwc3_trace(trace_dwc3_gadget, |
1818 | "failed to allocate IN endpoints"); | |
6a1e3ef4 FB |
1819 | return ret; |
1820 | } | |
1821 | ||
1822 | return 0; | |
1823 | } | |
1824 | ||
72246da4 FB |
1825 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1826 | { | |
1827 | struct dwc3_ep *dep; | |
1828 | u8 epnum; | |
1829 | ||
1830 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1831 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1832 | if (!dep) |
1833 | continue; | |
5bf8fae3 GC |
1834 | /* |
1835 | * Physical endpoints 0 and 1 are special; they form the | |
1836 | * bi-directional USB endpoint 0. | |
1837 | * | |
1838 | * For those two physical endpoints, we don't allocate a TRB | |
1839 | * pool nor do we add them the endpoints list. Due to that, we | |
1840 | * shouldn't do these two operations otherwise we would end up | |
1841 | * with all sorts of bugs when removing dwc3.ko. | |
1842 | */ | |
1843 | if (epnum != 0 && epnum != 1) { | |
1844 | dwc3_free_trb_pool(dep); | |
72246da4 | 1845 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1846 | } |
72246da4 FB |
1847 | |
1848 | kfree(dep); | |
1849 | } | |
1850 | } | |
1851 | ||
72246da4 | 1852 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1853 | |
e5ba5ec8 PA |
1854 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1855 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1856 | const struct dwc3_event_depevt *event, int status) |
1857 | { | |
72246da4 FB |
1858 | unsigned int count; |
1859 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1860 | unsigned int trb_status; |
72246da4 | 1861 | |
2c4cbe6e FB |
1862 | trace_dwc3_complete_trb(dep, trb); |
1863 | ||
e5ba5ec8 PA |
1864 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1865 | /* | |
1866 | * We continue despite the error. There is not much we | |
1867 | * can do. If we don't clean it up we loop forever. If | |
1868 | * we skip the TRB then it gets overwritten after a | |
1869 | * while since we use them in a ring buffer. A BUG() | |
1870 | * would help. Lets hope that if this occurs, someone | |
1871 | * fixes the root cause instead of looking away :) | |
1872 | */ | |
1873 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1874 | dep->name, trb); | |
1875 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1876 | ||
1877 | if (dep->direction) { | |
1878 | if (count) { | |
1879 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1880 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
ec5e795c FB |
1881 | dwc3_trace(trace_dwc3_gadget, |
1882 | "%s: incomplete IN transfer\n", | |
e5ba5ec8 PA |
1883 | dep->name); |
1884 | /* | |
1885 | * If missed isoc occurred and there is | |
1886 | * no request queued then issue END | |
1887 | * TRANSFER, so that core generates | |
1888 | * next xfernotready and we will issue | |
1889 | * a fresh START TRANSFER. | |
1890 | * If there are still queued request | |
1891 | * then wait, do not issue either END | |
1892 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 1893 | * request in pending_list during |
e5ba5ec8 PA |
1894 | * giveback.If any future queued request |
1895 | * is successfully transferred then we | |
1896 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 1897 | * request in the pending_list. |
e5ba5ec8 PA |
1898 | */ |
1899 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1900 | } else { | |
1901 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1902 | dep->name); | |
1903 | status = -ECONNRESET; | |
1904 | } | |
1905 | } else { | |
1906 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1907 | } | |
1908 | } else { | |
1909 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1910 | s_pkt = 1; | |
1911 | } | |
1912 | ||
1913 | /* | |
1914 | * We assume here we will always receive the entire data block | |
1915 | * which we should receive. Meaning, if we program RX to | |
1916 | * receive 4K but we receive only 2K, we assume that's all we | |
1917 | * should receive and we simply bounce the request back to the | |
1918 | * gadget driver for further processing. | |
1919 | */ | |
1920 | req->request.actual += req->request.length - count; | |
1921 | if (s_pkt) | |
1922 | return 1; | |
1923 | if ((event->status & DEPEVT_STATUS_LST) && | |
1924 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1925 | DWC3_TRB_CTRL_HWO))) | |
1926 | return 1; | |
1927 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1928 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1929 | return 1; | |
1930 | return 0; | |
1931 | } | |
1932 | ||
1933 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1934 | const struct dwc3_event_depevt *event, int status) | |
1935 | { | |
1936 | struct dwc3_request *req; | |
1937 | struct dwc3_trb *trb; | |
1938 | unsigned int slot; | |
1939 | unsigned int i; | |
1940 | int ret; | |
1941 | ||
72246da4 | 1942 | do { |
aa3342c8 | 1943 | req = next_request(&dep->started_list); |
ac7bdcc1 | 1944 | if (WARN_ON_ONCE(!req)) |
d115d705 | 1945 | return 1; |
ac7bdcc1 | 1946 | |
d115d705 VS |
1947 | i = 0; |
1948 | do { | |
53fd8818 | 1949 | slot = req->first_trb_index + i; |
36b68aae | 1950 | if (slot == DWC3_TRB_NUM - 1) |
d115d705 VS |
1951 | slot++; |
1952 | slot %= DWC3_TRB_NUM; | |
1953 | trb = &dep->trb_pool[slot]; | |
1954 | ||
1955 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
1956 | event, status); | |
1957 | if (ret) | |
1958 | break; | |
1959 | } while (++i < req->request.num_mapped_sgs); | |
1960 | ||
1961 | dwc3_gadget_giveback(dep, req, status); | |
e5ba5ec8 PA |
1962 | |
1963 | if (ret) | |
72246da4 | 1964 | break; |
d115d705 | 1965 | } while (1); |
72246da4 | 1966 | |
cdc359dd | 1967 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
1968 | list_empty(&dep->started_list)) { |
1969 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
1970 | /* |
1971 | * If there is no entry in request list then do | |
1972 | * not issue END TRANSFER now. Just set PENDING | |
1973 | * flag, so that END TRANSFER is issued when an | |
1974 | * entry is added into request list. | |
1975 | */ | |
1976 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1977 | } else { | |
b992e681 | 1978 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1979 | dep->flags = DWC3_EP_ENABLED; |
1980 | } | |
7efea86c PA |
1981 | return 1; |
1982 | } | |
1983 | ||
72246da4 FB |
1984 | return 1; |
1985 | } | |
1986 | ||
1987 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 1988 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
1989 | { |
1990 | unsigned status = 0; | |
1991 | int clean_busy; | |
e18b7975 FB |
1992 | u32 is_xfer_complete; |
1993 | ||
1994 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
1995 | |
1996 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1997 | status = -ECONNRESET; | |
1998 | ||
1d046793 | 1999 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
e18b7975 FB |
2000 | if (clean_busy && (is_xfer_complete || |
2001 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) | |
72246da4 | 2002 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2003 | |
2004 | /* | |
2005 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2006 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2007 | */ | |
2008 | if (dwc->revision < DWC3_REVISION_183A) { | |
2009 | u32 reg; | |
2010 | int i; | |
2011 | ||
2012 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2013 | dep = dwc->eps[i]; |
fae2b904 FB |
2014 | |
2015 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2016 | continue; | |
2017 | ||
aa3342c8 | 2018 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2019 | return; |
2020 | } | |
2021 | ||
2022 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2023 | reg |= dwc->u1u2; | |
2024 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2025 | ||
2026 | dwc->u1u2 = 0; | |
2027 | } | |
8a1a9c9e | 2028 | |
e6e709b7 | 2029 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2030 | int ret; |
2031 | ||
e6e709b7 | 2032 | ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete); |
8a1a9c9e FB |
2033 | if (!ret || ret == -EBUSY) |
2034 | return; | |
2035 | } | |
72246da4 FB |
2036 | } |
2037 | ||
72246da4 FB |
2038 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2039 | const struct dwc3_event_depevt *event) | |
2040 | { | |
2041 | struct dwc3_ep *dep; | |
2042 | u8 epnum = event->endpoint_number; | |
2043 | ||
2044 | dep = dwc->eps[epnum]; | |
2045 | ||
3336abb5 FB |
2046 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2047 | return; | |
2048 | ||
72246da4 FB |
2049 | if (epnum == 0 || epnum == 1) { |
2050 | dwc3_ep0_interrupt(dwc, event); | |
2051 | return; | |
2052 | } | |
2053 | ||
2054 | switch (event->endpoint_event) { | |
2055 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2056 | dep->resource_index = 0; |
c2df85ca | 2057 | |
16e78db7 | 2058 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
ec5e795c FB |
2059 | dwc3_trace(trace_dwc3_gadget, |
2060 | "%s is an Isochronous endpoint\n", | |
72246da4 FB |
2061 | dep->name); |
2062 | return; | |
2063 | } | |
2064 | ||
029d97ff | 2065 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2066 | break; |
2067 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2068 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2069 | break; |
2070 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2071 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2072 | dwc3_gadget_start_isoc(dwc, dep, event); |
2073 | } else { | |
6bb4fe12 | 2074 | int active; |
72246da4 FB |
2075 | int ret; |
2076 | ||
6bb4fe12 FB |
2077 | active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE; |
2078 | ||
73815280 | 2079 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", |
6bb4fe12 | 2080 | dep->name, active ? "Transfer Active" |
72246da4 FB |
2081 | : "Transfer Not Active"); |
2082 | ||
6bb4fe12 | 2083 | ret = __dwc3_gadget_kick_transfer(dep, 0, !active); |
72246da4 FB |
2084 | if (!ret || ret == -EBUSY) |
2085 | return; | |
2086 | ||
ec5e795c FB |
2087 | dwc3_trace(trace_dwc3_gadget, |
2088 | "%s: failed to kick transfers\n", | |
72246da4 FB |
2089 | dep->name); |
2090 | } | |
2091 | ||
879631aa FB |
2092 | break; |
2093 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2094 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2095 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2096 | dep->name); | |
2097 | return; | |
2098 | } | |
2099 | ||
2100 | switch (event->status) { | |
2101 | case DEPEVT_STREAMEVT_FOUND: | |
73815280 FB |
2102 | dwc3_trace(trace_dwc3_gadget, |
2103 | "Stream %d found and started", | |
879631aa FB |
2104 | event->parameters); |
2105 | ||
2106 | break; | |
2107 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2108 | /* FALLTHROUGH */ | |
2109 | default: | |
ec5e795c FB |
2110 | dwc3_trace(trace_dwc3_gadget, |
2111 | "unable to find suitable stream\n"); | |
879631aa | 2112 | } |
72246da4 FB |
2113 | break; |
2114 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
ec5e795c | 2115 | dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name); |
72246da4 | 2116 | break; |
72246da4 | 2117 | case DWC3_DEPEVT_EPCMDCMPLT: |
73815280 | 2118 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); |
72246da4 FB |
2119 | break; |
2120 | } | |
2121 | } | |
2122 | ||
2123 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2124 | { | |
2125 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2126 | spin_unlock(&dwc->lock); | |
2127 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2128 | spin_lock(&dwc->lock); | |
2129 | } | |
2130 | } | |
2131 | ||
bc5ba2e0 FB |
2132 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2133 | { | |
73a30bfc | 2134 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2135 | spin_unlock(&dwc->lock); |
2136 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2137 | spin_lock(&dwc->lock); | |
2138 | } | |
2139 | } | |
2140 | ||
2141 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2142 | { | |
73a30bfc | 2143 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2144 | spin_unlock(&dwc->lock); |
2145 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2146 | spin_lock(&dwc->lock); |
8e74475b FB |
2147 | } |
2148 | } | |
2149 | ||
2150 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2151 | { | |
2152 | if (!dwc->gadget_driver) | |
2153 | return; | |
2154 | ||
2155 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2156 | spin_unlock(&dwc->lock); | |
2157 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2158 | spin_lock(&dwc->lock); |
2159 | } | |
2160 | } | |
2161 | ||
b992e681 | 2162 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2163 | { |
2164 | struct dwc3_ep *dep; | |
2165 | struct dwc3_gadget_ep_cmd_params params; | |
2166 | u32 cmd; | |
2167 | int ret; | |
2168 | ||
2169 | dep = dwc->eps[epnum]; | |
2170 | ||
b4996a86 | 2171 | if (!dep->resource_index) |
3daf74d7 PA |
2172 | return; |
2173 | ||
57911504 PA |
2174 | /* |
2175 | * NOTICE: We are violating what the Databook says about the | |
2176 | * EndTransfer command. Ideally we would _always_ wait for the | |
2177 | * EndTransfer Command Completion IRQ, but that's causing too | |
2178 | * much trouble synchronizing between us and gadget driver. | |
2179 | * | |
2180 | * We have discussed this with the IP Provider and it was | |
2181 | * suggested to giveback all requests here, but give HW some | |
2182 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2183 | * an arbitrary 100us delay for that. |
57911504 PA |
2184 | * |
2185 | * Note also that a similar handling was tested by Synopsys | |
2186 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2187 | * In short, what we're doing is: | |
2188 | * | |
2189 | * - Issue EndTransfer WITH CMDIOC bit set | |
2190 | * - Wait 100us | |
2191 | */ | |
2192 | ||
3daf74d7 | 2193 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2194 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2195 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2196 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2197 | memset(¶ms, 0, sizeof(params)); |
2198 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2199 | WARN_ON_ONCE(ret); | |
b4996a86 | 2200 | dep->resource_index = 0; |
041d81f4 | 2201 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2202 | udelay(100); |
72246da4 FB |
2203 | } |
2204 | ||
2205 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2206 | { | |
2207 | u32 epnum; | |
2208 | ||
2209 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2210 | struct dwc3_ep *dep; | |
2211 | ||
2212 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2213 | if (!dep) |
2214 | continue; | |
2215 | ||
72246da4 FB |
2216 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2217 | continue; | |
2218 | ||
624407f9 | 2219 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2220 | } |
2221 | } | |
2222 | ||
2223 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2224 | { | |
2225 | u32 epnum; | |
2226 | ||
2227 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2228 | struct dwc3_ep *dep; | |
2229 | struct dwc3_gadget_ep_cmd_params params; | |
2230 | int ret; | |
2231 | ||
2232 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2233 | if (!dep) |
2234 | continue; | |
72246da4 FB |
2235 | |
2236 | if (!(dep->flags & DWC3_EP_STALL)) | |
2237 | continue; | |
2238 | ||
2239 | dep->flags &= ~DWC3_EP_STALL; | |
2240 | ||
2241 | memset(¶ms, 0, sizeof(params)); | |
2242 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2243 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2244 | WARN_ON_ONCE(ret); | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2249 | { | |
c4430a26 FB |
2250 | int reg; |
2251 | ||
72246da4 FB |
2252 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2253 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2254 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2255 | ||
2256 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2257 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2258 | |
72246da4 FB |
2259 | dwc3_disconnect_gadget(dwc); |
2260 | ||
2261 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2262 | dwc->setup_packet_pending = false; |
06a374ed | 2263 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
72246da4 FB |
2264 | } |
2265 | ||
72246da4 FB |
2266 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2267 | { | |
2268 | u32 reg; | |
2269 | ||
df62df56 FB |
2270 | /* |
2271 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2272 | * would cause a missing Disconnect Event if there's a | |
2273 | * pending Setup Packet in the FIFO. | |
2274 | * | |
2275 | * There's no suggested workaround on the official Bug | |
2276 | * report, which states that "unless the driver/application | |
2277 | * is doing any special handling of a disconnect event, | |
2278 | * there is no functional issue". | |
2279 | * | |
2280 | * Unfortunately, it turns out that we _do_ some special | |
2281 | * handling of a disconnect event, namely complete all | |
2282 | * pending transfers, notify gadget driver of the | |
2283 | * disconnection, and so on. | |
2284 | * | |
2285 | * Our suggested workaround is to follow the Disconnect | |
2286 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2287 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2288 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2289 | * same endpoint. |
2290 | * | |
2291 | * Refers to: | |
2292 | * | |
2293 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2294 | * generated if setup packet pending in FIFO | |
2295 | */ | |
2296 | if (dwc->revision < DWC3_REVISION_188A) { | |
2297 | if (dwc->setup_packet_pending) | |
2298 | dwc3_gadget_disconnect_interrupt(dwc); | |
2299 | } | |
2300 | ||
8e74475b | 2301 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2302 | |
2303 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2304 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2305 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2306 | dwc->test_mode = false; |
72246da4 FB |
2307 | |
2308 | dwc3_stop_active_transfers(dwc); | |
2309 | dwc3_clear_stall_all_ep(dwc); | |
2310 | ||
2311 | /* Reset device address to zero */ | |
2312 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2313 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2314 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2315 | } |
2316 | ||
2317 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2318 | { | |
2319 | u32 reg; | |
2320 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2321 | ||
2322 | /* | |
2323 | * We change the clock only at SS but I dunno why I would want to do | |
2324 | * this. Maybe it becomes part of the power saving plan. | |
2325 | */ | |
2326 | ||
ee5cd41c JY |
2327 | if ((speed != DWC3_DSTS_SUPERSPEED) && |
2328 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
72246da4 FB |
2329 | return; |
2330 | ||
2331 | /* | |
2332 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2333 | * each time on Connect Done. | |
2334 | */ | |
2335 | if (!usb30_clock) | |
2336 | return; | |
2337 | ||
2338 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2339 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2340 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2341 | } | |
2342 | ||
72246da4 FB |
2343 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2344 | { | |
72246da4 FB |
2345 | struct dwc3_ep *dep; |
2346 | int ret; | |
2347 | u32 reg; | |
2348 | u8 speed; | |
2349 | ||
72246da4 FB |
2350 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2351 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2352 | dwc->speed = speed; | |
2353 | ||
2354 | dwc3_update_ram_clk_sel(dwc, speed); | |
2355 | ||
2356 | switch (speed) { | |
7580862b JY |
2357 | case DWC3_DCFG_SUPERSPEED_PLUS: |
2358 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2359 | dwc->gadget.ep0->maxpacket = 512; | |
2360 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2361 | break; | |
72246da4 | 2362 | case DWC3_DCFG_SUPERSPEED: |
05870c5b FB |
2363 | /* |
2364 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2365 | * would cause a missing USB3 Reset event. | |
2366 | * | |
2367 | * In such situations, we should force a USB3 Reset | |
2368 | * event by calling our dwc3_gadget_reset_interrupt() | |
2369 | * routine. | |
2370 | * | |
2371 | * Refers to: | |
2372 | * | |
2373 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2374 | * not be generated always when the link enters poll | |
2375 | */ | |
2376 | if (dwc->revision < DWC3_REVISION_190A) | |
2377 | dwc3_gadget_reset_interrupt(dwc); | |
2378 | ||
72246da4 FB |
2379 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2380 | dwc->gadget.ep0->maxpacket = 512; | |
2381 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2382 | break; | |
2383 | case DWC3_DCFG_HIGHSPEED: | |
2384 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2385 | dwc->gadget.ep0->maxpacket = 64; | |
2386 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2387 | break; | |
2388 | case DWC3_DCFG_FULLSPEED2: | |
2389 | case DWC3_DCFG_FULLSPEED1: | |
2390 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2391 | dwc->gadget.ep0->maxpacket = 64; | |
2392 | dwc->gadget.speed = USB_SPEED_FULL; | |
2393 | break; | |
2394 | case DWC3_DCFG_LOWSPEED: | |
2395 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2396 | dwc->gadget.ep0->maxpacket = 8; | |
2397 | dwc->gadget.speed = USB_SPEED_LOW; | |
2398 | break; | |
2399 | } | |
2400 | ||
2b758350 PA |
2401 | /* Enable USB2 LPM Capability */ |
2402 | ||
ee5cd41c JY |
2403 | if ((dwc->revision > DWC3_REVISION_194A) && |
2404 | (speed != DWC3_DCFG_SUPERSPEED) && | |
2405 | (speed != DWC3_DCFG_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2406 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2407 | reg |= DWC3_DCFG_LPM_CAP; | |
2408 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2409 | ||
2410 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2411 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2412 | ||
460d098c | 2413 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2414 | |
80caf7d2 HR |
2415 | /* |
2416 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2417 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2418 | * BESL value in the LPM token is less than or equal to LPM | |
2419 | * NYET threshold. | |
2420 | */ | |
2421 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2422 | && dwc->has_lpm_erratum, | |
2423 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2424 | ||
2425 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2426 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2427 | ||
356363bf FB |
2428 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2429 | } else { | |
2430 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2431 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2432 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2433 | } | |
2434 | ||
72246da4 | 2435 | dep = dwc->eps[0]; |
265b70a7 PZ |
2436 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2437 | false); | |
72246da4 FB |
2438 | if (ret) { |
2439 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2440 | return; | |
2441 | } | |
2442 | ||
2443 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2444 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2445 | false); | |
72246da4 FB |
2446 | if (ret) { |
2447 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2448 | return; | |
2449 | } | |
2450 | ||
2451 | /* | |
2452 | * Configure PHY via GUSB3PIPECTLn if required. | |
2453 | * | |
2454 | * Update GTXFIFOSIZn | |
2455 | * | |
2456 | * In both cases reset values should be sufficient. | |
2457 | */ | |
2458 | } | |
2459 | ||
2460 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2461 | { | |
72246da4 FB |
2462 | /* |
2463 | * TODO take core out of low power mode when that's | |
2464 | * implemented. | |
2465 | */ | |
2466 | ||
ad14d4e0 JL |
2467 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2468 | spin_unlock(&dwc->lock); | |
2469 | dwc->gadget_driver->resume(&dwc->gadget); | |
2470 | spin_lock(&dwc->lock); | |
2471 | } | |
72246da4 FB |
2472 | } |
2473 | ||
2474 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2475 | unsigned int evtinfo) | |
2476 | { | |
fae2b904 | 2477 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2478 | unsigned int pwropt; |
2479 | ||
2480 | /* | |
2481 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2482 | * Hibernation mode enabled which would show up when device detects | |
2483 | * host-initiated U3 exit. | |
2484 | * | |
2485 | * In that case, device will generate a Link State Change Interrupt | |
2486 | * from U3 to RESUME which is only necessary if Hibernation is | |
2487 | * configured in. | |
2488 | * | |
2489 | * There are no functional changes due to such spurious event and we | |
2490 | * just need to ignore it. | |
2491 | * | |
2492 | * Refers to: | |
2493 | * | |
2494 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2495 | * operational mode | |
2496 | */ | |
2497 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2498 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2499 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2500 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2501 | (next == DWC3_LINK_STATE_RESUME)) { | |
73815280 FB |
2502 | dwc3_trace(trace_dwc3_gadget, |
2503 | "ignoring transition U3 -> Resume"); | |
0b0cc1cd FB |
2504 | return; |
2505 | } | |
2506 | } | |
fae2b904 FB |
2507 | |
2508 | /* | |
2509 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2510 | * on the link partner, the USB session might do multiple entry/exit | |
2511 | * of low power states before a transfer takes place. | |
2512 | * | |
2513 | * Due to this problem, we might experience lower throughput. The | |
2514 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2515 | * transitioning from U1/U2 to U0 and enable those bits again | |
2516 | * after a transfer completes and there are no pending transfers | |
2517 | * on any of the enabled endpoints. | |
2518 | * | |
2519 | * This is the first half of that workaround. | |
2520 | * | |
2521 | * Refers to: | |
2522 | * | |
2523 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2524 | * core send LGO_Ux entering U0 | |
2525 | */ | |
2526 | if (dwc->revision < DWC3_REVISION_183A) { | |
2527 | if (next == DWC3_LINK_STATE_U0) { | |
2528 | u32 u1u2; | |
2529 | u32 reg; | |
2530 | ||
2531 | switch (dwc->link_state) { | |
2532 | case DWC3_LINK_STATE_U1: | |
2533 | case DWC3_LINK_STATE_U2: | |
2534 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2535 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2536 | | DWC3_DCTL_ACCEPTU2ENA | |
2537 | | DWC3_DCTL_INITU1ENA | |
2538 | | DWC3_DCTL_ACCEPTU1ENA); | |
2539 | ||
2540 | if (!dwc->u1u2) | |
2541 | dwc->u1u2 = reg & u1u2; | |
2542 | ||
2543 | reg &= ~u1u2; | |
2544 | ||
2545 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2546 | break; | |
2547 | default: | |
2548 | /* do nothing */ | |
2549 | break; | |
2550 | } | |
2551 | } | |
2552 | } | |
2553 | ||
bc5ba2e0 FB |
2554 | switch (next) { |
2555 | case DWC3_LINK_STATE_U1: | |
2556 | if (dwc->speed == USB_SPEED_SUPER) | |
2557 | dwc3_suspend_gadget(dwc); | |
2558 | break; | |
2559 | case DWC3_LINK_STATE_U2: | |
2560 | case DWC3_LINK_STATE_U3: | |
2561 | dwc3_suspend_gadget(dwc); | |
2562 | break; | |
2563 | case DWC3_LINK_STATE_RESUME: | |
2564 | dwc3_resume_gadget(dwc); | |
2565 | break; | |
2566 | default: | |
2567 | /* do nothing */ | |
2568 | break; | |
2569 | } | |
2570 | ||
e57ebc1d | 2571 | dwc->link_state = next; |
72246da4 FB |
2572 | } |
2573 | ||
e1dadd3b FB |
2574 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2575 | unsigned int evtinfo) | |
2576 | { | |
2577 | unsigned int is_ss = evtinfo & BIT(4); | |
2578 | ||
2579 | /** | |
2580 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2581 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2582 | * randomly. | |
2583 | * | |
2584 | * Because of this issue, core could generate bogus hibernation | |
2585 | * events which SW needs to ignore. | |
2586 | * | |
2587 | * Refers to: | |
2588 | * | |
2589 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2590 | * Device Fallback from SuperSpeed | |
2591 | */ | |
2592 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2593 | return; | |
2594 | ||
2595 | /* enter hibernation here */ | |
2596 | } | |
2597 | ||
72246da4 FB |
2598 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2599 | const struct dwc3_event_devt *event) | |
2600 | { | |
2601 | switch (event->type) { | |
2602 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2603 | dwc3_gadget_disconnect_interrupt(dwc); | |
2604 | break; | |
2605 | case DWC3_DEVICE_EVENT_RESET: | |
2606 | dwc3_gadget_reset_interrupt(dwc); | |
2607 | break; | |
2608 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2609 | dwc3_gadget_conndone_interrupt(dwc); | |
2610 | break; | |
2611 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2612 | dwc3_gadget_wakeup_interrupt(dwc); | |
2613 | break; | |
e1dadd3b FB |
2614 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2615 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2616 | "unexpected hibernation event\n")) | |
2617 | break; | |
2618 | ||
2619 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2620 | break; | |
72246da4 FB |
2621 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2622 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2623 | break; | |
2624 | case DWC3_DEVICE_EVENT_EOPF: | |
73815280 | 2625 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); |
72246da4 FB |
2626 | break; |
2627 | case DWC3_DEVICE_EVENT_SOF: | |
73815280 | 2628 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); |
72246da4 FB |
2629 | break; |
2630 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
73815280 | 2631 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); |
72246da4 FB |
2632 | break; |
2633 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
73815280 | 2634 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); |
72246da4 FB |
2635 | break; |
2636 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
73815280 | 2637 | dwc3_trace(trace_dwc3_gadget, "Overflow"); |
72246da4 FB |
2638 | break; |
2639 | default: | |
e9f2aa87 | 2640 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2641 | } |
2642 | } | |
2643 | ||
2644 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2645 | const union dwc3_event *event) | |
2646 | { | |
2c4cbe6e FB |
2647 | trace_dwc3_event(event->raw); |
2648 | ||
72246da4 FB |
2649 | /* Endpoint IRQ, handle it and return early */ |
2650 | if (event->type.is_devspec == 0) { | |
2651 | /* depevt */ | |
2652 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2653 | } | |
2654 | ||
2655 | switch (event->type.type) { | |
2656 | case DWC3_EVENT_TYPE_DEV: | |
2657 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2658 | break; | |
2659 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2660 | default: | |
2661 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2662 | } | |
2663 | } | |
2664 | ||
dea520a4 | 2665 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2666 | { |
dea520a4 | 2667 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2668 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2669 | int left; |
e8adfc30 | 2670 | u32 reg; |
b15a762f | 2671 | |
f42f2447 | 2672 | left = evt->count; |
b15a762f | 2673 | |
f42f2447 FB |
2674 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2675 | return IRQ_NONE; | |
b15a762f | 2676 | |
f42f2447 FB |
2677 | while (left > 0) { |
2678 | union dwc3_event event; | |
b15a762f | 2679 | |
f42f2447 | 2680 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2681 | |
f42f2447 | 2682 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2683 | |
f42f2447 FB |
2684 | /* |
2685 | * FIXME we wrap around correctly to the next entry as | |
2686 | * almost all entries are 4 bytes in size. There is one | |
2687 | * entry which has 12 bytes which is a regular entry | |
2688 | * followed by 8 bytes data. ATM I don't know how | |
2689 | * things are organized if we get next to the a | |
2690 | * boundary so I worry about that once we try to handle | |
2691 | * that. | |
2692 | */ | |
2693 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2694 | left -= 4; | |
b15a762f | 2695 | |
660e9bde | 2696 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); |
f42f2447 | 2697 | } |
b15a762f | 2698 | |
f42f2447 FB |
2699 | evt->count = 0; |
2700 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2701 | ret = IRQ_HANDLED; | |
b15a762f | 2702 | |
f42f2447 | 2703 | /* Unmask interrupt */ |
660e9bde | 2704 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 2705 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2706 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 2707 | |
f42f2447 FB |
2708 | return ret; |
2709 | } | |
e8adfc30 | 2710 | |
dea520a4 | 2711 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 2712 | { |
dea520a4 FB |
2713 | struct dwc3_event_buffer *evt = _evt; |
2714 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 2715 | unsigned long flags; |
f42f2447 | 2716 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2717 | |
e5f68b4a | 2718 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 2719 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 2720 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2721 | |
2722 | return ret; | |
2723 | } | |
2724 | ||
dea520a4 | 2725 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 2726 | { |
dea520a4 | 2727 | struct dwc3 *dwc = evt->dwc; |
72246da4 | 2728 | u32 count; |
e8adfc30 | 2729 | u32 reg; |
72246da4 | 2730 | |
660e9bde | 2731 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
2732 | count &= DWC3_GEVNTCOUNT_MASK; |
2733 | if (!count) | |
2734 | return IRQ_NONE; | |
2735 | ||
b15a762f FB |
2736 | evt->count = count; |
2737 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2738 | |
e8adfc30 | 2739 | /* Mask interrupt */ |
660e9bde | 2740 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 2741 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2742 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 2743 | |
b15a762f | 2744 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2745 | } |
2746 | ||
dea520a4 | 2747 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 2748 | { |
dea520a4 | 2749 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 2750 | |
dea520a4 | 2751 | return dwc3_check_event_buf(evt); |
72246da4 FB |
2752 | } |
2753 | ||
2754 | /** | |
2755 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2756 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2757 | * |
2758 | * Returns 0 on success otherwise negative errno. | |
2759 | */ | |
41ac7b3a | 2760 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2761 | { |
72246da4 | 2762 | int ret; |
72246da4 FB |
2763 | |
2764 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2765 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2766 | if (!dwc->ctrl_req) { | |
2767 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2768 | ret = -ENOMEM; | |
2769 | goto err0; | |
2770 | } | |
2771 | ||
2abd9d5f | 2772 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2773 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2774 | if (!dwc->ep0_trb) { | |
2775 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2776 | ret = -ENOMEM; | |
2777 | goto err1; | |
2778 | } | |
2779 | ||
3ef35faf | 2780 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2781 | if (!dwc->setup_buf) { |
72246da4 FB |
2782 | ret = -ENOMEM; |
2783 | goto err2; | |
2784 | } | |
2785 | ||
5812b1c2 | 2786 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2787 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2788 | GFP_KERNEL); | |
5812b1c2 FB |
2789 | if (!dwc->ep0_bounce) { |
2790 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2791 | ret = -ENOMEM; | |
2792 | goto err3; | |
2793 | } | |
2794 | ||
04c03d10 FB |
2795 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); |
2796 | if (!dwc->zlp_buf) { | |
2797 | ret = -ENOMEM; | |
2798 | goto err4; | |
2799 | } | |
2800 | ||
72246da4 | 2801 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 2802 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2803 | dwc->gadget.sg_supported = true; |
72246da4 | 2804 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 2805 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 2806 | |
b9e51b2b BM |
2807 | /* |
2808 | * FIXME We might be setting max_speed to <SUPER, however versions | |
2809 | * <2.20a of dwc3 have an issue with metastability (documented | |
2810 | * elsewhere in this driver) which tells us we can't set max speed to | |
2811 | * anything lower than SUPER. | |
2812 | * | |
2813 | * Because gadget.max_speed is only used by composite.c and function | |
2814 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
2815 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
2816 | * together with our BOS descriptor as that could confuse host into | |
2817 | * thinking we can handle super speed. | |
2818 | * | |
2819 | * Note that, in fact, we won't even support GetBOS requests when speed | |
2820 | * is less than super speed because we don't have means, yet, to tell | |
2821 | * composite.c that we are USB 2.0 + LPM ECN. | |
2822 | */ | |
2823 | if (dwc->revision < DWC3_REVISION_220A) | |
2824 | dwc3_trace(trace_dwc3_gadget, | |
2825 | "Changing max_speed on rev %08x\n", | |
2826 | dwc->revision); | |
2827 | ||
2828 | dwc->gadget.max_speed = dwc->maximum_speed; | |
2829 | ||
a4b9d94b DC |
2830 | /* |
2831 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2832 | * on ep out. | |
2833 | */ | |
2834 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2835 | ||
72246da4 FB |
2836 | /* |
2837 | * REVISIT: Here we should clear all pending IRQs to be | |
2838 | * sure we're starting from a well known location. | |
2839 | */ | |
2840 | ||
2841 | ret = dwc3_gadget_init_endpoints(dwc); | |
2842 | if (ret) | |
04c03d10 | 2843 | goto err5; |
72246da4 | 2844 | |
72246da4 FB |
2845 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2846 | if (ret) { | |
2847 | dev_err(dwc->dev, "failed to register udc\n"); | |
04c03d10 | 2848 | goto err5; |
72246da4 FB |
2849 | } |
2850 | ||
2851 | return 0; | |
2852 | ||
04c03d10 FB |
2853 | err5: |
2854 | kfree(dwc->zlp_buf); | |
2855 | ||
5812b1c2 | 2856 | err4: |
e1f80467 | 2857 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2858 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2859 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2860 | |
72246da4 | 2861 | err3: |
0fc9a1be | 2862 | kfree(dwc->setup_buf); |
72246da4 FB |
2863 | |
2864 | err2: | |
2865 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2866 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2867 | ||
2868 | err1: | |
2869 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2870 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2871 | ||
2872 | err0: | |
2873 | return ret; | |
2874 | } | |
2875 | ||
7415f17c FB |
2876 | /* -------------------------------------------------------------------------- */ |
2877 | ||
72246da4 FB |
2878 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2879 | { | |
72246da4 | 2880 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2881 | |
72246da4 FB |
2882 | dwc3_gadget_free_endpoints(dwc); |
2883 | ||
3ef35faf FB |
2884 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2885 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2886 | |
0fc9a1be | 2887 | kfree(dwc->setup_buf); |
04c03d10 | 2888 | kfree(dwc->zlp_buf); |
72246da4 FB |
2889 | |
2890 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2891 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2892 | ||
2893 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2894 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2895 | } |
7415f17c | 2896 | |
0b0231aa | 2897 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 2898 | { |
7b2a0368 | 2899 | if (dwc->pullups_connected) { |
7415f17c | 2900 | dwc3_gadget_disable_irq(dwc); |
7b2a0368 FB |
2901 | dwc3_gadget_run_stop(dwc, true, true); |
2902 | } | |
7415f17c | 2903 | |
7415f17c FB |
2904 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2905 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2906 | ||
2907 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2908 | ||
2909 | return 0; | |
2910 | } | |
2911 | ||
2912 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2913 | { | |
2914 | struct dwc3_ep *dep; | |
2915 | int ret; | |
2916 | ||
2917 | /* Start with SuperSpeed Default */ | |
2918 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2919 | ||
2920 | dep = dwc->eps[0]; | |
265b70a7 PZ |
2921 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2922 | false); | |
7415f17c FB |
2923 | if (ret) |
2924 | goto err0; | |
2925 | ||
2926 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2927 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2928 | false); | |
7415f17c FB |
2929 | if (ret) |
2930 | goto err1; | |
2931 | ||
2932 | /* begin to receive SETUP packets */ | |
2933 | dwc->ep0state = EP0_SETUP_PHASE; | |
2934 | dwc3_ep0_out_start(dwc); | |
2935 | ||
2936 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2937 | ||
0b0231aa FB |
2938 | if (dwc->pullups_connected) { |
2939 | dwc3_gadget_enable_irq(dwc); | |
2940 | dwc3_gadget_run_stop(dwc, true, false); | |
2941 | } | |
2942 | ||
7415f17c FB |
2943 | return 0; |
2944 | ||
2945 | err1: | |
2946 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2947 | ||
2948 | err0: | |
2949 | return ret; | |
2950 | } |