]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/usb/dwc3/gadget.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tools: usb: testusb: update default vary for superspeed
[mirror_ubuntu-hirsute-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
4199c5f8
FB		 183 usb_gadget_unmap_request_by_dev(dwc->sysdev,
184 &req->request, req->direction);
72246da4 185
2c4cbe6e 186 trace_dwc3_gadget_giveback(req);
72246da4
FB		 187
188 spin_unlock(&dwc->lock);
304f7e5e 189 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 190 spin_lock(&dwc->lock);
fc8bb91b
FB		 191
192 if (dep->number > 1)
193 pm_runtime_put(dwc->dev);
72246da4
FB		 194}
195
3ece0ec4 196int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 197{
198 u32 timeout = 500;
71f7e702 199 int status = 0;
0fe886cd 200 int ret = 0;
b09bb642
FB		 201 u32 reg;
202
203 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
204 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
205
206 do {
207 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
208 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 209 status = DWC3_DGCMD_STATUS(reg);
210 if (status)
0fe886cd
FB		 211 ret = -EINVAL;
212 break;
b09bb642 213 }
e3aee486 214 } while (--timeout);
0fe886cd
FB		 215
216 if (!timeout) {
0fe886cd 217 ret = -ETIMEDOUT;
71f7e702 218 status = -ETIMEDOUT;
0fe886cd
FB		 219 }
220
71f7e702
FB		 221 trace_dwc3_gadget_generic_cmd(cmd, param, status);
222
0fe886cd 223 return ret;
b09bb642
FB		 224}
225
c36d8e94
FB		 226static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
227
2cd4718d
FB		 228int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
229 struct dwc3_gadget_ep_cmd_params *params)
72246da4 230{
8897a761 231 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 232 struct dwc3 *dwc = dep->dwc;
61d58242 233 u32 timeout = 500;
72246da4
FB		 234 u32 reg;
235
0933df15 236 int cmd_status = 0;
2b0f11df 237 int susphy = false;
c0ca324d 238 int ret = -EINVAL;
72246da4 239
2b0f11df
FB		 240 /*
241 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
242 * we're issuing an endpoint command, we must check if
243 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
244 *
245 * We will also set SUSPHY bit to what it was before returning as stated
246 * by the same section on Synopsys databook.
247 */
ab2a92e7
FB		 248 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
249 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
250 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
251 susphy = true;
252 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
253 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
254 }
2b0f11df
FB		 255 }
256
5999914f 257 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 258 int needs_wakeup;
259
260 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
261 dwc->link_state == DWC3_LINK_STATE_U2 ||
262 dwc->link_state == DWC3_LINK_STATE_U3);
263
264 if (unlikely(needs_wakeup)) {
265 ret = __dwc3_gadget_wakeup(dwc);
266 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
267 ret);
268 }
269 }
270
2eb88016
FB		 271 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
272 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
273 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 274
8897a761
FB		 275 /*
276 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
277 * not relying on XferNotReady, we can make use of a special "No
278 * Response Update Transfer" command where we should clear both CmdAct
279 * and CmdIOC bits.
280 *
281 * With this, we don't need to wait for command completion and can
282 * straight away issue further commands to the endpoint.
283 *
284 * NOTICE: We're making an assumption that control endpoints will never
285 * make use of Update Transfer command. This is a safe assumption
286 * because we can never have more than one request at a time with
287 * Control Endpoints. If anybody changes that assumption, this chunk
288 * needs to be updated accordingly.
289 */
290 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
291 !usb_endpoint_xfer_isoc(desc))
292 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
293 else
294 cmd |= DWC3_DEPCMD_CMDACT;
295
296 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 297 do {
2eb88016 298 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 299 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 300 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 301
7b9cc7a2
KL		 302 switch (cmd_status) {
303 case 0:
304 ret = 0;
305 break;
306 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 307 ret = -EINVAL;
c0ca324d 308 break;
7b9cc7a2
KL		 309 case DEPEVT_TRANSFER_BUS_EXPIRY:
310 /*
311 * SW issues START TRANSFER command to
312 * isochronous ep with future frame interval. If
313 * future interval time has already passed when
314 * core receives the command, it will respond
315 * with an error status of 'Bus Expiry'.
316 *
317 * Instead of always returning -EINVAL, let's
318 * give a hint to the gadget driver that this is
319 * the case by returning -EAGAIN.
320 */
7b9cc7a2
KL		 321 ret = -EAGAIN;
322 break;
323 default:
324 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
325 }
326
c0ca324d 327 break;
72246da4 328 }
f6bb225b 329 } while (--timeout);
72246da4 330
f6bb225b 331 if (timeout == 0) {
f6bb225b 332 ret = -ETIMEDOUT;
0933df15 333 cmd_status = -ETIMEDOUT;
f6bb225b 334 }
c0ca324d 335
0933df15
FB		 336 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
337
6cb2e4e3
FB		 338 if (ret == 0) {
339 switch (DWC3_DEPCMD_CMD(cmd)) {
340 case DWC3_DEPCMD_STARTTRANSFER:
341 dep->flags |= DWC3_EP_TRANSFER_STARTED;
342 break;
343 case DWC3_DEPCMD_ENDTRANSFER:
344 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
345 break;
346 default:
347 /* nothing */
348 break;
349 }
350 }
351
2b0f11df
FB		 352 if (unlikely(susphy)) {
353 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
354 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
355 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
356 }
357
c0ca324d 358 return ret;
72246da4
FB		 359}
360
50c763f8
JY		 361static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
362{
363 struct dwc3 *dwc = dep->dwc;
364 struct dwc3_gadget_ep_cmd_params params;
365 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
366
367 /*
368 * As of core revision 2.60a the recommended programming model
369 * is to set the ClearPendIN bit when issuing a Clear Stall EP
370 * command for IN endpoints. This is to prevent an issue where
371 * some (non-compliant) hosts may not send ACK TPs for pending
372 * IN transfers due to a mishandled error condition. Synopsys
373 * STAR 9000614252.
374 */
5e6c88d2
LB		 375 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
376 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 377 cmd |= DWC3_DEPCMD_CLEARPENDIN;
378
379 memset(&params, 0, sizeof(params));
380
2cd4718d 381 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 382}
383
72246da4 384static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 385 struct dwc3_trb *trb)
72246da4 386{
c439ef87 387 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 388
389 return dep->trb_pool_dma + offset;
390}
391
392static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
393{
394 struct dwc3 *dwc = dep->dwc;
395
396 if (dep->trb_pool)
397 return 0;
398
d64ff406 399 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 400 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
401 &dep->trb_pool_dma, GFP_KERNEL);
402 if (!dep->trb_pool) {
403 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
404 dep->name);
405 return -ENOMEM;
406 }
407
408 return 0;
409}
410
411static void dwc3_free_trb_pool(struct dwc3_ep *dep)
412{
413 struct dwc3 *dwc = dep->dwc;
414
d64ff406 415 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 416 dep->trb_pool, dep->trb_pool_dma);
417
418 dep->trb_pool = NULL;
419 dep->trb_pool_dma = 0;
420}
421
c4509601
JY		 422static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
423
424/**
425 * dwc3_gadget_start_config - Configure EP resources
426 * @dwc: pointer to our controller context structure
427 * @dep: endpoint that is being enabled
428 *
429 * The assignment of transfer resources cannot perfectly follow the
430 * data book due to the fact that the controller driver does not have
431 * all knowledge of the configuration in advance. It is given this
432 * information piecemeal by the composite gadget framework after every
433 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
434 * programming model in this scenario can cause errors. For two
435 * reasons:
436 *
437 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
438 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
439 * multiple interfaces.
440 *
441 * 2) The databook does not mention doing more DEPXFERCFG for new
442 * endpoint on alt setting (8.1.6).
443 *
444 * The following simplified method is used instead:
445 *
446 * All hardware endpoints can be assigned a transfer resource and this
447 * setting will stay persistent until either a core reset or
448 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
449 * do DEPXFERCFG for every hardware endpoint as well. We are
450 * guaranteed that there are as many transfer resources as endpoints.
451 *
452 * This function is called for each endpoint when it is being enabled
453 * but is triggered only when called for EP0-out, which always happens
454 * first, and which should only happen in one of the above conditions.
455 */
72246da4
FB		 456static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459 u32 cmd;
c4509601
JY		 460 int i;
461 int ret;
462
463 if (dep->number)
464 return 0;
72246da4
FB		 465
466 memset(&params, 0x00, sizeof(params));
c4509601 467 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 468
2cd4718d 469 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 470 if (ret)
471 return ret;
472
473 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
474 struct dwc3_ep *dep = dwc->eps[i];
72246da4 475
c4509601
JY		 476 if (!dep)
477 continue;
478
479 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
480 if (ret)
481 return ret;
72246da4
FB		 482 }
483
484 return 0;
485}
486
487static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 488 bool modify, bool restore)
72246da4 489{
39ebb05c
JY		 490 const struct usb_ss_ep_comp_descriptor *comp_desc;
491 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 492 struct dwc3_gadget_ep_cmd_params params;
493
21e64bf2
FB		 494 if (dev_WARN_ONCE(dwc->dev, modify && restore,
495 "Can't modify and restore\n"))
496 return -EINVAL;
497
39ebb05c
JY		 498 comp_desc = dep->endpoint.comp_desc;
499 desc = dep->endpoint.desc;
500
72246da4
FB		 501 memset(&params, 0x00, sizeof(params));
502
dc1c70a7 503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
505
506 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 507 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 508 u32 burst = dep->endpoint.maxburst;
676e3497 509 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 510 }
72246da4 511
21e64bf2
FB		 512 if (modify) {
513 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
514 } else if (restore) {
265b70a7
PZ		 515 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
516 params.param2 |= dep->saved_state;
21e64bf2
FB		 517 } else {
518 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 519 }
520
4bc48c97
FB		 521 if (usb_endpoint_xfer_control(desc))
522 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 523
524 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
525 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 526
18b7ede5 527 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 528 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
529 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 530 dep->stream_capable = true;
531 }
532
0b93a4c8 533 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 534 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 535
536 /*
537 * We are doing 1:1 mapping for endpoints, meaning
538 * Physical Endpoints 2 maps to Logical Endpoint 2 and
539 * so on. We consider the direction bit as part of the physical
540 * endpoint number. So USB endpoint 0x81 is 0x03.
541 */
dc1c70a7 542 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 543
544 /*
545 * We must use the lower 16 TX FIFOs even though
546 * HW might have more
547 */
548 if (dep->direction)
dc1c70a7 549 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 550
551 if (desc->bInterval) {
dc1c70a7 552 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 553 dep->interval = 1 << (desc->bInterval - 1);
554 }
555
2cd4718d 556 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 557}
558
559static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
560{
561 struct dwc3_gadget_ep_cmd_params params;
562
563 memset(&params, 0x00, sizeof(params));
564
dc1c70a7 565 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 566
2cd4718d
FB		 567 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
568 &params);
72246da4
FB		 569}
570
571/**
572 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
573 * @dep: endpoint to be initialized
574 * @desc: USB Endpoint Descriptor
575 *
576 * Caller should take care of locking
577 */
578static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 579 bool modify, bool restore)
72246da4 580{
39ebb05c 581 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 582 struct dwc3 *dwc = dep->dwc;
39ebb05c 583
72246da4 584 u32 reg;
b09e99ee 585 int ret;
72246da4
FB		 586
587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
589 if (ret)
590 return ret;
591 }
592
39ebb05c 593 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 594 if (ret)
595 return ret;
596
597 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 598 struct dwc3_trb *trb_st_hw;
599 struct dwc3_trb *trb_link;
72246da4 600
72246da4
FB		 601 dep->type = usb_endpoint_type(desc);
602 dep->flags |= DWC3_EP_ENABLED;
76a638f8 603 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 604
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg |= DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
608
76a638f8
BW		 609 init_waitqueue_head(&dep->wait_end_transfer);
610
36b68aae 611 if (usb_endpoint_xfer_control(desc))
2870e501 612 goto out;
72246da4 613
0d25744a
JY		 614 /* Initialize the TRB ring */
615 dep->trb_dequeue = 0;
616 dep->trb_enqueue = 0;
617 memset(dep->trb_pool, 0,
618 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
619
36b68aae 620 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 621 trb_st_hw = &dep->trb_pool[0];
622
f6bafc6a 623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 624 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
625 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
627 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 628 }
629
a97ea994
FB		 630 /*
631 * Issue StartTransfer here with no-op TRB so we can always rely on No
632 * Response Update Transfer command.
633 */
634 if (usb_endpoint_xfer_bulk(desc)) {
635 struct dwc3_gadget_ep_cmd_params params;
636 struct dwc3_trb *trb;
637 dma_addr_t trb_dma;
638 u32 cmd;
639
640 memset(&params, 0, sizeof(params));
641 trb = &dep->trb_pool[0];
642 trb_dma = dwc3_trb_dma_offset(dep, trb);
643
644 params.param0 = upper_32_bits(trb_dma);
645 params.param1 = lower_32_bits(trb_dma);
646
647 cmd = DWC3_DEPCMD_STARTTRANSFER;
648
649 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
650 if (ret < 0)
651 return ret;
652
653 dep->flags |= DWC3_EP_BUSY;
654
655 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
656 WARN_ON_ONCE(!dep->resource_index);
657 }
658
2870e501
FB		 659
660out:
661 trace_dwc3_gadget_ep_enable(dep);
662
72246da4
FB		 663 return 0;
664}
665
b992e681 666static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 667static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 668{
669 struct dwc3_request *req;
670
0e146028 671 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 672
0e146028
FB		 673 /* - giveback all requests to gadget driver */
674 while (!list_empty(&dep->started_list)) {
675 req = next_request(&dep->started_list);
1591633e 676
0e146028 677 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 678 }
679
aa3342c8
FB		 680 while (!list_empty(&dep->pending_list)) {
681 req = next_request(&dep->pending_list);
72246da4 682
624407f9 683 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 684 }
72246da4
FB		 685}
686
687/**
688 * __dwc3_gadget_ep_disable - Disables a HW endpoint
689 * @dep: the endpoint to disable
690 *
624407f9
SAS		 691 * This function also removes requests which are currently processed ny the
692 * hardware and those which are not yet scheduled.
693 * Caller should take care of locking.
72246da4 694 */
72246da4
FB		 695static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
696{
697 struct dwc3 *dwc = dep->dwc;
698 u32 reg;
699
2870e501 700 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 701
624407f9 702 dwc3_remove_requests(dwc, dep);
72246da4 703
687ef981
FB		 704 /* make sure HW endpoint isn't stalled */
705 if (dep->flags & DWC3_EP_STALL)
7a608559 706 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 707
72246da4
FB		 708 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
709 reg &= ~DWC3_DALEPENA_EP(dep->number);
710 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
711
879631aa 712 dep->stream_capable = false;
72246da4 713 dep->type = 0;
76a638f8 714 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 715
39ebb05c
JY		 716 /* Clear out the ep descriptors for non-ep0 */
717 if (dep->number > 1) {
718 dep->endpoint.comp_desc = NULL;
719 dep->endpoint.desc = NULL;
720 }
721
72246da4
FB		 722 return 0;
723}
724
725/* -------------------------------------------------------------------------- */
726
727static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
728 const struct usb_endpoint_descriptor *desc)
729{
730 return -EINVAL;
731}
732
733static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
734{
735 return -EINVAL;
736}
737
738/* -------------------------------------------------------------------------- */
739
740static int dwc3_gadget_ep_enable(struct usb_ep *ep,
741 const struct usb_endpoint_descriptor *desc)
742{
743 struct dwc3_ep *dep;
744 struct dwc3 *dwc;
745 unsigned long flags;
746 int ret;
747
748 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
749 pr_debug("dwc3: invalid parameters\n");
750 return -EINVAL;
751 }
752
753 if (!desc->wMaxPacketSize) {
754 pr_debug("dwc3: missing wMaxPacketSize\n");
755 return -EINVAL;
756 }
757
758 dep = to_dwc3_ep(ep);
759 dwc = dep->dwc;
760
95ca961c
FB		 761 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
762 "%s is already enabled\n",
763 dep->name))
c6f83f38 764 return 0;
c6f83f38 765
72246da4 766 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 767 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 768 spin_unlock_irqrestore(&dwc->lock, flags);
769
770 return ret;
771}
772
773static int dwc3_gadget_ep_disable(struct usb_ep *ep)
774{
775 struct dwc3_ep *dep;
776 struct dwc3 *dwc;
777 unsigned long flags;
778 int ret;
779
780 if (!ep) {
781 pr_debug("dwc3: invalid parameters\n");
782 return -EINVAL;
783 }
784
785 dep = to_dwc3_ep(ep);
786 dwc = dep->dwc;
787
95ca961c
FB		 788 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
789 "%s is already disabled\n",
790 dep->name))
72246da4 791 return 0;
72246da4 792
72246da4
FB		 793 spin_lock_irqsave(&dwc->lock, flags);
794 ret = __dwc3_gadget_ep_disable(dep);
795 spin_unlock_irqrestore(&dwc->lock, flags);
796
797 return ret;
798}
799
800static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
801 gfp_t gfp_flags)
802{
803 struct dwc3_request *req;
804 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 805
806 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 807 if (!req)
72246da4 808 return NULL;
72246da4
FB		 809
810 req->epnum = dep->number;
811 req->dep = dep;
72246da4 812
68d34c8a
FB		 813 dep->allocated_requests++;
814
2c4cbe6e
FB		 815 trace_dwc3_alloc_request(req);
816
72246da4
FB		 817 return &req->request;
818}
819
820static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
821 struct usb_request *request)
822{
823 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 824 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 825
68d34c8a 826 dep->allocated_requests--;
2c4cbe6e 827 trace_dwc3_free_request(req);
72246da4
FB		 828 kfree(req);
829}
830
2c78c029
FB		 831static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
832
e49d3cf4
FB		 833static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
834 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
835 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 836{
6b9018d4
FB		 837 struct dwc3 *dwc = dep->dwc;
838 struct usb_gadget *gadget = &dwc->gadget;
839 enum usb_device_speed speed = gadget->speed;
c71fc37c 840
ef966b9d 841 dwc3_ep_inc_enq(dep);
e5ba5ec8 842
f6bafc6a
FB		 843 trb->size = DWC3_TRB_SIZE_LENGTH(length);
844 trb->bpl = lower_32_bits(dma);
845 trb->bph = upper_32_bits(dma);
c71fc37c 846
16e78db7 847 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 848 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 849 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 850 break;
851
852 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 853 if (!node) {
e5ba5ec8 854 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 855
856 if (speed == USB_SPEED_HIGH) {
857 struct usb_ep *ep = &dep->endpoint;
858 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
859 }
860 } else {
e5ba5ec8 861 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 862 }
ca4d44ea
FB		 863
864 /* always enable Interrupt on Missed ISOC */
865 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 866 break;
867
868 case USB_ENDPOINT_XFER_BULK:
869 case USB_ENDPOINT_XFER_INT:
f6bafc6a 870 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 871 break;
872 default:
873 /*
874 * This is only possible with faulty memory because we
875 * checked it already :)
876 */
0a695d4c
FB		 877 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
878 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 879 }
880
ca4d44ea 881 /* always enable Continue on Short Packet */
c9508c8c 882 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 883 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 884
e49d3cf4 885 if (short_not_ok)
c9508c8c
FB		 886 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
887 }
888
e49d3cf4 889 if ((!no_interrupt && !chain) ||
2c78c029 890 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 891 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 892
e5ba5ec8
PA		 893 if (chain)
894 trb->ctrl |= DWC3_TRB_CTRL_CHN;
895
16e78db7 896 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 897 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 898
f6bafc6a 899 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 900
901 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 902}
903
e49d3cf4
FB		 904/**
905 * dwc3_prepare_one_trb - setup one TRB from one request
906 * @dep: endpoint for which this request is prepared
907 * @req: dwc3_request pointer
908 * @chain: should this TRB be chained to the next?
909 * @node: only for isochronous endpoints. First TRB needs different type.
910 */
911static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
912 struct dwc3_request *req, unsigned chain, unsigned node)
913{
914 struct dwc3_trb *trb;
915 unsigned length = req->request.length;
916 unsigned stream_id = req->request.stream_id;
917 unsigned short_not_ok = req->request.short_not_ok;
918 unsigned no_interrupt = req->request.no_interrupt;
919 dma_addr_t dma = req->request.dma;
920
921 trb = &dep->trb_pool[dep->trb_enqueue];
922
923 if (!req->trb) {
924 dwc3_gadget_move_started_request(req);
925 req->trb = trb;
926 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
927 dep->queued_requests++;
928 }
929
930 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
931 stream_id, short_not_ok, no_interrupt);
932}
933
361572b5
JY		 934/**
935 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
936 * @dep: The endpoint with the TRB ring
937 * @index: The index of the current TRB in the ring
938 *
939 * Returns the TRB prior to the one pointed to by the index. If the
940 * index is 0, we will wrap backwards, skip the link TRB, and return
941 * the one just before that.
942 */
943static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
944{
45438a0c 945 u8 tmp = index;
361572b5 946
45438a0c
FB		 947 if (!tmp)
948 tmp = DWC3_TRB_NUM - 1;
361572b5 949
45438a0c 950 return &dep->trb_pool[tmp - 1];
361572b5
JY		 951}
952
c4233573
FB		 953static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
954{
955 struct dwc3_trb *tmp;
32db3d94 956 u8 trbs_left;
c4233573
FB		 957
958 /*
959 * If enqueue & dequeue are equal than it is either full or empty.
960 *
961 * One way to know for sure is if the TRB right before us has HWO bit
962 * set or not. If it has, then we're definitely full and can't fit any
963 * more transfers in our ring.
964 */
965 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 966 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
202adafe 967 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
361572b5 968 return 0;
c4233573
FB		 969
970 return DWC3_TRB_NUM - 1;
971 }
972
9d7aba77 973 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 974 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 975
9d7aba77
JY		 976 if (dep->trb_dequeue < dep->trb_enqueue)
977 trbs_left--;
978
32db3d94 979 return trbs_left;
c4233573
FB		 980}
981
5ee85d89 982static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 983 struct dwc3_request *req)
5ee85d89 984{
1f512119 985 struct scatterlist *sg = req->sg;
5ee85d89 986 struct scatterlist *s;
5ee85d89
FB		 987 int i;
988
1f512119 989 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 990 unsigned int length = req->request.length;
991 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
992 unsigned int rem = length % maxp;
5ee85d89
FB		 993 unsigned chain = true;
994
4bc48c97 995 if (sg_is_last(s))
5ee85d89
FB		 996 chain = false;
997
c6267a51
FB		 998 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
999 struct dwc3 *dwc = dep->dwc;
1000 struct dwc3_trb *trb;
1001
1002 req->unaligned = true;
1003
1004 /* prepare normal TRB */
1005 dwc3_prepare_one_trb(dep, req, true, i);
1006
1007 /* Now prepare one extra TRB to align transfer size */
1008 trb = &dep->trb_pool[dep->trb_enqueue];
1009 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1010 maxp - rem, false, 0,
1011 req->request.stream_id,
1012 req->request.short_not_ok,
1013 req->request.no_interrupt);
1014 } else {
1015 dwc3_prepare_one_trb(dep, req, chain, i);
1016 }
5ee85d89 1017
7ae7df49 1018 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1019 break;
1020 }
1021}
1022
1023static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1024 struct dwc3_request *req)
5ee85d89 1025{
c6267a51
FB		 1026 unsigned int length = req->request.length;
1027 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1028 unsigned int rem = length % maxp;
1029
1030 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1031 struct dwc3 *dwc = dep->dwc;
1032 struct dwc3_trb *trb;
1033
1034 req->unaligned = true;
1035
1036 /* prepare normal TRB */
1037 dwc3_prepare_one_trb(dep, req, true, 0);
1038
1039 /* Now prepare one extra TRB to align transfer size */
1040 trb = &dep->trb_pool[dep->trb_enqueue];
1041 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1042 false, 0, req->request.stream_id,
1043 req->request.short_not_ok,
1044 req->request.no_interrupt);
d6e5a549
FB		 1045 } else if (req->request.zero && req->request.length &&
1046 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1047 struct dwc3 *dwc = dep->dwc;
1048 struct dwc3_trb *trb;
1049
1050 req->zero = true;
1051
1052 /* prepare normal TRB */
1053 dwc3_prepare_one_trb(dep, req, true, 0);
1054
1055 /* Now prepare one extra TRB to handle ZLP */
1056 trb = &dep->trb_pool[dep->trb_enqueue];
1057 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1058 false, 0, req->request.stream_id,
1059 req->request.short_not_ok,
1060 req->request.no_interrupt);
c6267a51
FB		 1061 } else {
1062 dwc3_prepare_one_trb(dep, req, false, 0);
1063 }
5ee85d89
FB		 1064}
1065
72246da4
FB		 1066/*
1067 * dwc3_prepare_trbs - setup TRBs from requests
1068 * @dep: endpoint for which requests are being prepared
72246da4 1069 *
1d046793
PZ		 1070 * The function goes through the requests list and sets up TRBs for the
1071 * transfers. The function returns once there are no more TRBs available or
1072 * it runs out of requests.
72246da4 1073 */
c4233573 1074static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1075{
68e823e2 1076 struct dwc3_request *req, *n;
72246da4
FB		 1077
1078 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1079
7ae7df49 1080 if (!dwc3_calc_trbs_left(dep))
89bc856e 1081 return;
72246da4 1082
d86c5a67
FB		 1083 /*
1084 * We can get in a situation where there's a request in the started list
1085 * but there weren't enough TRBs to fully kick it in the first time
1086 * around, so it has been waiting for more TRBs to be freed up.
1087 *
1088 * In that case, we should check if we have a request with pending_sgs
1089 * in the started list and prepare TRBs for that request first,
1090 * otherwise we will prepare TRBs completely out of order and that will
1091 * break things.
1092 */
1093 list_for_each_entry(req, &dep->started_list, list) {
1094 if (req->num_pending_sgs > 0)
1095 dwc3_prepare_one_trb_sg(dep, req);
1096
1097 if (!dwc3_calc_trbs_left(dep))
1098 return;
1099 }
1100
aa3342c8 1101 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
cdb55b39
FB		 1102 struct dwc3 *dwc = dep->dwc;
1103 int ret;
1104
1105 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1106 dep->direction);
1107 if (ret)
1108 return;
1109
1110 req->sg = req->request.sg;
1111 req->num_pending_sgs = req->request.num_mapped_sgs;
1112
1f512119 1113 if (req->num_pending_sgs > 0)
7ae7df49 1114 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1115 else
7ae7df49 1116 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1117
7ae7df49 1118 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1119 return;
72246da4 1120 }
72246da4
FB		 1121}
1122
4fae2e3e 1123static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1124{
1125 struct dwc3_gadget_ep_cmd_params params;
1126 struct dwc3_request *req;
4fae2e3e 1127 int starting;
72246da4
FB		 1128 int ret;
1129 u32 cmd;
1130
4fae2e3e 1131 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1132
4fae2e3e
FB		 1133 dwc3_prepare_trbs(dep);
1134 req = next_request(&dep->started_list);
72246da4
FB		 1135 if (!req) {
1136 dep->flags |= DWC3_EP_PENDING_REQUEST;
1137 return 0;
1138 }
1139
1140 memset(&params, 0, sizeof(params));
72246da4 1141
4fae2e3e 1142 if (starting) {
1877d6c9
PA		 1143 params.param0 = upper_32_bits(req->trb_dma);
1144 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1145 cmd = DWC3_DEPCMD_STARTTRANSFER |
1146 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1147 } else {
b6b1c6db
FB		 1148 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1149 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1150 }
72246da4 1151
2cd4718d 1152 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1153 if (ret < 0) {
72246da4
FB		 1154 /*
1155 * FIXME we need to iterate over the list of requests
1156 * here and stop, unmap, free and del each of the linked
1d046793 1157 * requests instead of what we do now.
72246da4 1158 */
ce3fc8b3
JD		 1159 if (req->trb)
1160 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1161 dep->queued_requests--;
15b8d933 1162 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1163 return ret;
1164 }
1165
1166 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1167
4fae2e3e 1168 if (starting) {
2eb88016 1169 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1170 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1171 }
25b8ff68 1172
72246da4
FB		 1173 return 0;
1174}
1175
6cb2e4e3
FB		 1176static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1177{
1178 u32 reg;
1179
1180 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1181 return DWC3_DSTS_SOFFN(reg);
1182}
1183
d6d6ec7b
PA		 1184static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1185 struct dwc3_ep *dep, u32 cur_uf)
1186{
1187 u32 uf;
1188
aa3342c8 1189 if (list_empty(&dep->pending_list)) {
5eb30ced 1190 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1191 dep->name);
f4a53c55 1192 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1193 return;
1194 }
1195
af771d73
JY		 1196 /*
1197 * Schedule the first trb for one interval in the future or at
1198 * least 4 microframes.
1199 */
1200 uf = cur_uf + max_t(u32, 4, dep->interval);
d6d6ec7b 1201
4fae2e3e 1202 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1203}
1204
1205static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1206 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1207{
1208 u32 cur_uf, mask;
1209
1210 mask = ~(dep->interval - 1);
1211 cur_uf = event->parameters & mask;
1212
1213 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1214}
1215
72246da4
FB		 1216static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1217{
0fc9a1be 1218 struct dwc3 *dwc = dep->dwc;
cdb55b39 1219 int ret = 0;
0fc9a1be 1220
bb423984 1221 if (!dep->endpoint.desc) {
5eb30ced
FB		 1222 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1223 dep->name);
bb423984
FB		 1224 return -ESHUTDOWN;
1225 }
1226
04fb365c
FB		 1227 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1228 &req->request, req->dep->name))
bb423984 1229 return -EINVAL;
bb423984 1230
fc8bb91b
FB		 1231 pm_runtime_get(dwc->dev);
1232
72246da4
FB		 1233 req->request.actual = 0;
1234 req->request.status = -EINPROGRESS;
1235 req->direction = dep->direction;
1236 req->epnum = dep->number;
1237
fe84f522
FB		 1238 trace_dwc3_ep_queue(req);
1239
aa3342c8 1240 list_add_tail(&req->list, &dep->pending_list);
72246da4 1241
d889c23c
FB		 1242 /*
1243 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1244 * wait for a XferNotReady event so we will know what's the current
1245 * (micro-)frame number.
1246 *
1247 * Without this trick, we are very, very likely gonna get Bus Expiry
1248 * errors which will force us issue EndTransfer command.
1249 */
1250 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1251 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1252 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1253 dwc3_stop_active_transfer(dwc, dep->number, true);
1254 dep->flags = DWC3_EP_ENABLED;
1255 } else {
1256 u32 cur_uf;
1257
1258 cur_uf = __dwc3_gadget_get_frame(dwc);
1259 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1260 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1261 }
08a36b54
FB		 1262 }
1263 return 0;
a0925324 1264 }
72246da4 1265
594e121f
FB		 1266 if (!dwc3_calc_trbs_left(dep))
1267 return 0;
b997ada5 1268
08a36b54 1269 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1270 if (ret == -EBUSY)
1271 ret = 0;
1272
1273 return ret;
72246da4
FB		 1274}
1275
1276static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1277 gfp_t gfp_flags)
1278{
1279 struct dwc3_request *req = to_dwc3_request(request);
1280 struct dwc3_ep *dep = to_dwc3_ep(ep);
1281 struct dwc3 *dwc = dep->dwc;
1282
1283 unsigned long flags;
1284
1285 int ret;
1286
fdee4eba 1287 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1288 ret = __dwc3_gadget_ep_queue(dep, req);
1289 spin_unlock_irqrestore(&dwc->lock, flags);
1290
1291 return ret;
1292}
1293
1294static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1295 struct usb_request *request)
1296{
1297 struct dwc3_request *req = to_dwc3_request(request);
1298 struct dwc3_request *r = NULL;
1299
1300 struct dwc3_ep *dep = to_dwc3_ep(ep);
1301 struct dwc3 *dwc = dep->dwc;
1302
1303 unsigned long flags;
1304 int ret = 0;
1305
2c4cbe6e
FB		 1306 trace_dwc3_ep_dequeue(req);
1307
72246da4
FB		 1308 spin_lock_irqsave(&dwc->lock, flags);
1309
aa3342c8 1310 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1311 if (r == req)
1312 break;
1313 }
1314
1315 if (r != req) {
aa3342c8 1316 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1317 if (r == req)
1318 break;
1319 }
1320 if (r == req) {
1321 /* wait until it is processed */
b992e681 1322 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1323
1324 /*
1325 * If request was already started, this means we had to
1326 * stop the transfer. With that we also need to ignore
1327 * all TRBs used by the request, however TRBs can only
1328 * be modified after completion of END_TRANSFER
1329 * command. So what we do here is that we wait for
1330 * END_TRANSFER completion and only after that, we jump
1331 * over TRBs by clearing HWO and incrementing dequeue
1332 * pointer.
1333 *
1334 * Note that we have 2 possible types of transfers here:
1335 *
1336 * i) Linear buffer request
1337 * ii) SG-list based request
1338 *
1339 * SG-list based requests will have r->num_pending_sgs
1340 * set to a valid number (> 0). Linear requests,
1341 * normally use a single TRB.
1342 *
1343 * For each of these two cases, if r->unaligned flag is
1344 * set, one extra TRB has been used to align transfer
1345 * size to wMaxPacketSize.
1346 *
1347 * All of these cases need to be taken into
1348 * consideration so we don't mess up our TRB ring
1349 * pointers.
1350 */
1351 wait_event_lock_irq(dep->wait_end_transfer,
1352 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1353 dwc->lock);
1354
1355 if (!r->trb)
1356 goto out1;
1357
1358 if (r->num_pending_sgs) {
1359 struct dwc3_trb *trb;
1360 int i = 0;
1361
1362 for (i = 0; i < r->num_pending_sgs; i++) {
1363 trb = r->trb + i;
1364 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1365 dwc3_ep_inc_deq(dep);
1366 }
1367
d6e5a549 1368 if (r->unaligned || r->zero) {
cf3113d8
FB		 1369 trb = r->trb + r->num_pending_sgs + 1;
1370 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1371 dwc3_ep_inc_deq(dep);
1372 }
1373 } else {
1374 struct dwc3_trb *trb = r->trb;
1375
1376 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1377 dwc3_ep_inc_deq(dep);
1378
d6e5a549 1379 if (r->unaligned || r->zero) {
cf3113d8
FB		 1380 trb = r->trb + 1;
1381 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1382 dwc3_ep_inc_deq(dep);
1383 }
1384 }
e8d4e8be 1385 goto out1;
72246da4 1386 }
04fb365c 1387 dev_err(dwc->dev, "request %pK was not queued to %s\n",
72246da4
FB		 1388 request, ep->name);
1389 ret = -EINVAL;
1390 goto out0;
1391 }
1392
e8d4e8be 1393out1:
72246da4 1394 /* giveback the request */
cf3113d8 1395 dep->queued_requests--;
72246da4
FB		 1396 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1397
1398out0:
1399 spin_unlock_irqrestore(&dwc->lock, flags);
1400
1401 return ret;
1402}
1403
7a608559 1404int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1405{
1406 struct dwc3_gadget_ep_cmd_params params;
1407 struct dwc3 *dwc = dep->dwc;
1408 int ret;
1409
5ad02fb8
FB		 1410 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1411 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1412 return -EINVAL;
1413 }
1414
72246da4
FB		 1415 memset(&params, 0x00, sizeof(params));
1416
1417 if (value) {
69450c4d
FB		 1418 struct dwc3_trb *trb;
1419
1420 unsigned transfer_in_flight;
1421 unsigned started;
1422
ffb80fc6
FB		 1423 if (dep->flags & DWC3_EP_STALL)
1424 return 0;
1425
69450c4d
FB		 1426 if (dep->number > 1)
1427 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1428 else
1429 trb = &dwc->ep0_trb[dep->trb_enqueue];
1430
1431 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1432 started = !list_empty(&dep->started_list);
1433
1434 if (!protocol && ((dep->direction && transfer_in_flight) ||
1435 (!dep->direction && started))) {
7a608559
FB		 1436 return -EAGAIN;
1437 }
1438
2cd4718d
FB		 1439 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1440 &params);
72246da4 1441 if (ret)
3f89204b 1442 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1443 dep->name);
1444 else
1445 dep->flags |= DWC3_EP_STALL;
1446 } else {
ffb80fc6
FB		 1447 if (!(dep->flags & DWC3_EP_STALL))
1448 return 0;
2cd4718d 1449
50c763f8 1450 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1451 if (ret)
3f89204b 1452 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1453 dep->name);
1454 else
a535d81c 1455 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1456 }
5275455a 1457
72246da4
FB		 1458 return ret;
1459}
1460
1461static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1462{
1463 struct dwc3_ep *dep = to_dwc3_ep(ep);
1464 struct dwc3 *dwc = dep->dwc;
1465
1466 unsigned long flags;
1467
1468 int ret;
1469
1470 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1471 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1472 spin_unlock_irqrestore(&dwc->lock, flags);
1473
1474 return ret;
1475}
1476
1477static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1478{
1479 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1480 struct dwc3 *dwc = dep->dwc;
1481 unsigned long flags;
95aa4e8d 1482 int ret;
72246da4 1483
249a4569 1484 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1485 dep->flags |= DWC3_EP_WEDGE;
1486
08f0d966 1487 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1488 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1489 else
7a608559 1490 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1491 spin_unlock_irqrestore(&dwc->lock, flags);
1492
1493 return ret;
72246da4
FB		 1494}
1495
1496/* -------------------------------------------------------------------------- */
1497
1498static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1499 .bLength = USB_DT_ENDPOINT_SIZE,
1500 .bDescriptorType = USB_DT_ENDPOINT,
1501 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1502};
1503
1504static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1505 .enable = dwc3_gadget_ep0_enable,
1506 .disable = dwc3_gadget_ep0_disable,
1507 .alloc_request = dwc3_gadget_ep_alloc_request,
1508 .free_request = dwc3_gadget_ep_free_request,
1509 .queue = dwc3_gadget_ep0_queue,
1510 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1511 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1512 .set_wedge = dwc3_gadget_ep_set_wedge,
1513};
1514
1515static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1516 .enable = dwc3_gadget_ep_enable,
1517 .disable = dwc3_gadget_ep_disable,
1518 .alloc_request = dwc3_gadget_ep_alloc_request,
1519 .free_request = dwc3_gadget_ep_free_request,
1520 .queue = dwc3_gadget_ep_queue,
1521 .dequeue = dwc3_gadget_ep_dequeue,
1522 .set_halt = dwc3_gadget_ep_set_halt,
1523 .set_wedge = dwc3_gadget_ep_set_wedge,
1524};
1525
1526/* -------------------------------------------------------------------------- */
1527
1528static int dwc3_gadget_get_frame(struct usb_gadget *g)
1529{
1530 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1531
6cb2e4e3 1532 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1533}
1534
218ef7b6 1535static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1536{
d6011f6f 1537 int retries;
72246da4 1538
218ef7b6 1539 int ret;
72246da4
FB		 1540 u32 reg;
1541
72246da4
FB		 1542 u8 link_state;
1543 u8 speed;
1544
72246da4
FB		 1545 /*
1546 * According to the Databook Remote wakeup request should
1547 * be issued only when the device is in early suspend state.
1548 *
1549 * We can check that via USB Link State bits in DSTS register.
1550 */
1551 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1552
1553 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1554 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1555 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1556 return 0;
72246da4
FB		 1557
1558 link_state = DWC3_DSTS_USBLNKST(reg);
1559
1560 switch (link_state) {
1561 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1562 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1563 break;
1564 default:
218ef7b6 1565 return -EINVAL;
72246da4
FB		 1566 }
1567
8598bde7
FB		 1568 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1569 if (ret < 0) {
1570 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1571 return ret;
8598bde7 1572 }
72246da4 1573
802fde98
PZ		 1574 /* Recent versions do this automatically */
1575 if (dwc->revision < DWC3_REVISION_194A) {
1576 /* write zeroes to Link Change Request */
fcc023c7 1577 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1578 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1579 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1580 }
72246da4 1581
1d046793 1582 /* poll until Link State changes to ON */
d6011f6f 1583 retries = 20000;
72246da4 1584
d6011f6f 1585 while (retries--) {
72246da4
FB		 1586 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1587
1588 /* in HS, means ON */
1589 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1590 break;
1591 }
1592
1593 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1594 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1595 return -EINVAL;
72246da4
FB		 1596 }
1597
218ef7b6
FB		 1598 return 0;
1599}
1600
1601static int dwc3_gadget_wakeup(struct usb_gadget *g)
1602{
1603 struct dwc3 *dwc = gadget_to_dwc(g);
1604 unsigned long flags;
1605 int ret;
1606
1607 spin_lock_irqsave(&dwc->lock, flags);
1608 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1609 spin_unlock_irqrestore(&dwc->lock, flags);
1610
1611 return ret;
1612}
1613
1614static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1615 int is_selfpowered)
1616{
1617 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1618 unsigned long flags;
72246da4 1619
249a4569 1620 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1621 g->is_selfpowered = !!is_selfpowered;
249a4569 1622 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1623
1624 return 0;
1625}
1626
7b2a0368 1627static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1628{
1629 u32 reg;
61d58242 1630 u32 timeout = 500;
72246da4 1631
fc8bb91b
FB		 1632 if (pm_runtime_suspended(dwc->dev))
1633 return 0;
1634
72246da4 1635 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1636 if (is_on) {
802fde98
PZ		 1637 if (dwc->revision <= DWC3_REVISION_187A) {
1638 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1639 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1640 }
1641
1642 if (dwc->revision >= DWC3_REVISION_194A)
1643 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1644 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1645
1646 if (dwc->has_hibernation)
1647 reg |= DWC3_DCTL_KEEP_CONNECT;
1648
9fcb3bd8 1649 dwc->pullups_connected = true;
8db7ed15 1650 } else {
72246da4 1651 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1652
1653 if (dwc->has_hibernation && !suspend)
1654 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1655
9fcb3bd8 1656 dwc->pullups_connected = false;
8db7ed15 1657 }
72246da4
FB		 1658
1659 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1660
1661 do {
1662 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1663 reg &= DWC3_DSTS_DEVCTRLHLT;
1664 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1665
1666 if (!timeout)
1667 return -ETIMEDOUT;
72246da4 1668
6f17f74b 1669 return 0;
72246da4
FB		 1670}
1671
1672static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1673{
1674 struct dwc3 *dwc = gadget_to_dwc(g);
1675 unsigned long flags;
6f17f74b 1676 int ret;
72246da4
FB		 1677
1678 is_on = !!is_on;
1679
bb014736
BW		 1680 /*
1681 * Per databook, when we want to stop the gadget, if a control transfer
1682 * is still in process, complete it and get the core into setup phase.
1683 */
1684 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1685 reinit_completion(&dwc->ep0_in_setup);
1686
1687 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1688 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1689 if (ret == 0) {
1690 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1691 return -ETIMEDOUT;
1692 }
1693 }
1694
72246da4 1695 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1696 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1697 spin_unlock_irqrestore(&dwc->lock, flags);
1698
6f17f74b 1699 return ret;
72246da4
FB		 1700}
1701
8698e2ac
FB		 1702static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1703{
1704 u32 reg;
1705
1706 /* Enable all but Start and End of Frame IRQs */
1707 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1708 DWC3_DEVTEN_EVNTOVERFLOWEN |
1709 DWC3_DEVTEN_CMDCMPLTEN |
1710 DWC3_DEVTEN_ERRTICERREN |
1711 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1712 DWC3_DEVTEN_CONNECTDONEEN |
1713 DWC3_DEVTEN_USBRSTEN |
1714 DWC3_DEVTEN_DISCONNEVTEN);
1715
799e9dc8
FB		 1716 if (dwc->revision < DWC3_REVISION_250A)
1717 reg |= DWC3_DEVTEN_ULSTCNGEN;
1718
8698e2ac
FB		 1719 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1720}
1721
1722static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1723{
1724 /* mask all interrupts */
1725 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1726}
1727
1728static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1729static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1730
4e99472b
FB		 1731/**
1732 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1733 * dwc: pointer to our context structure
1734 *
1735 * The following looks like complex but it's actually very simple. In order to
1736 * calculate the number of packets we can burst at once on OUT transfers, we're
1737 * gonna use RxFIFO size.
1738 *
1739 * To calculate RxFIFO size we need two numbers:
1740 * MDWIDTH = size, in bits, of the internal memory bus
1741 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1742 *
1743 * Given these two numbers, the formula is simple:
1744 *
1745 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1746 *
1747 * 24 bytes is for 3x SETUP packets
1748 * 16 bytes is a clock domain crossing tolerance
1749 *
1750 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1751 */
1752static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1753{
1754 u32 ram2_depth;
1755 u32 mdwidth;
1756 u32 nump;
1757 u32 reg;
1758
1759 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1760 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1761
1762 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1763 nump = min_t(u32, nump, 16);
1764
1765 /* update NumP */
1766 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1767 reg &= ~DWC3_DCFG_NUMP_MASK;
1768 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1769 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1770}
1771
d7be2952 1772static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1773{
72246da4 1774 struct dwc3_ep *dep;
72246da4
FB		 1775 int ret = 0;
1776 u32 reg;
1777
cf40b86b
JY		 1778 /*
1779 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1780 * the core supports IMOD, disable it.
1781 */
1782 if (dwc->imod_interval) {
1783 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1784 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1785 } else if (dwc3_has_imod(dwc)) {
1786 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1787 }
1788
72246da4
FB		 1789 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1790 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1791
1792 /**
1793 * WORKAROUND: DWC3 revision < 2.20a have an issue
1794 * which would cause metastability state on Run/Stop
1795 * bit if we try to force the IP to USB2-only mode.
1796 *
1797 * Because of that, we cannot configure the IP to any
1798 * speed other than the SuperSpeed
1799 *
1800 * Refers to:
1801 *
1802 * STAR#9000525659: Clock Domain Crossing on DCTL in
1803 * USB 2.0 Mode
1804 */
f7e846f0 1805 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1806 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1807 } else {
1808 switch (dwc->maximum_speed) {
1809 case USB_SPEED_LOW:
2da9ad76 1810 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1811 break;
1812 case USB_SPEED_FULL:
9418ee15 1813 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1814 break;
1815 case USB_SPEED_HIGH:
2da9ad76 1816 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1817 break;
7580862b 1818 case USB_SPEED_SUPER_PLUS:
2da9ad76 1819 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1820 break;
f7e846f0 1821 default:
77966eb8
JY		 1822 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1823 dwc->maximum_speed);
1824 /* fall through */
1825 case USB_SPEED_SUPER:
1826 reg |= DWC3_DCFG_SUPERSPEED;
1827 break;
f7e846f0
FB		 1828 }
1829 }
72246da4
FB		 1830 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1831
2a58f9c1
FB		 1832 /*
1833 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1834 * field instead of letting dwc3 itself calculate that automatically.
1835 *
1836 * This way, we maximize the chances that we'll be able to get several
1837 * bursts of data without going through any sort of endpoint throttling.
1838 */
1839 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1840 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1841 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1842
4e99472b
FB		 1843 dwc3_gadget_setup_nump(dwc);
1844
72246da4
FB		 1845 /* Start with SuperSpeed Default */
1846 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1847
1848 dep = dwc->eps[0];
39ebb05c 1849 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1850 if (ret) {
1851 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1852 goto err0;
72246da4
FB		 1853 }
1854
1855 dep = dwc->eps[1];
39ebb05c 1856 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1857 if (ret) {
1858 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1859 goto err1;
72246da4
FB		 1860 }
1861
1862 /* begin to receive SETUP packets */
c7fcdeb2 1863 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1864 dwc3_ep0_out_start(dwc);
1865
8698e2ac
FB		 1866 dwc3_gadget_enable_irq(dwc);
1867
72246da4
FB		 1868 return 0;
1869
b0d7ffd4 1870err1:
d7be2952 1871 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1872
1873err0:
72246da4
FB		 1874 return ret;
1875}
1876
d7be2952
FB		 1877static int dwc3_gadget_start(struct usb_gadget *g,
1878 struct usb_gadget_driver *driver)
72246da4
FB		 1879{
1880 struct dwc3 *dwc = gadget_to_dwc(g);
1881 unsigned long flags;
d7be2952 1882 int ret = 0;
8698e2ac 1883 int irq;
72246da4 1884
9522def4 1885 irq = dwc->irq_gadget;
d7be2952
FB		 1886 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1887 IRQF_SHARED, "dwc3", dwc->ev_buf);
1888 if (ret) {
1889 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1890 irq, ret);
1891 goto err0;
1892 }
1893
72246da4 1894 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1895 if (dwc->gadget_driver) {
1896 dev_err(dwc->dev, "%s is already bound to %s\n",
1897 dwc->gadget.name,
1898 dwc->gadget_driver->driver.name);
1899 ret = -EBUSY;
1900 goto err1;
1901 }
1902
1903 dwc->gadget_driver = driver;
1904
fc8bb91b
FB		 1905 if (pm_runtime_active(dwc->dev))
1906 __dwc3_gadget_start(dwc);
1907
d7be2952
FB		 1908 spin_unlock_irqrestore(&dwc->lock, flags);
1909
1910 return 0;
1911
1912err1:
1913 spin_unlock_irqrestore(&dwc->lock, flags);
1914 free_irq(irq, dwc);
1915
1916err0:
1917 return ret;
1918}
72246da4 1919
d7be2952
FB		 1920static void __dwc3_gadget_stop(struct dwc3 *dwc)
1921{
8698e2ac 1922 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1923 __dwc3_gadget_ep_disable(dwc->eps[0]);
1924 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1925}
72246da4 1926
d7be2952
FB		 1927static int dwc3_gadget_stop(struct usb_gadget *g)
1928{
1929 struct dwc3 *dwc = gadget_to_dwc(g);
1930 unsigned long flags;
76a638f8 1931 int epnum;
72246da4 1932
d7be2952 1933 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1934
1935 if (pm_runtime_suspended(dwc->dev))
1936 goto out;
1937
d7be2952 1938 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1939
1940 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1941 struct dwc3_ep *dep = dwc->eps[epnum];
1942
1943 if (!dep)
1944 continue;
1945
1946 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1947 continue;
1948
1949 wait_event_lock_irq(dep->wait_end_transfer,
1950 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1951 dwc->lock);
1952 }
1953
1954out:
d7be2952 1955 dwc->gadget_driver = NULL;
72246da4
FB		 1956 spin_unlock_irqrestore(&dwc->lock, flags);
1957
3f308d17 1958 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1959
72246da4
FB		 1960 return 0;
1961}
802fde98 1962
72246da4
FB		 1963static const struct usb_gadget_ops dwc3_gadget_ops = {
1964 .get_frame = dwc3_gadget_get_frame,
1965 .wakeup = dwc3_gadget_wakeup,
1966 .set_selfpowered = dwc3_gadget_set_selfpowered,
1967 .pullup = dwc3_gadget_pullup,
1968 .udc_start = dwc3_gadget_start,
1969 .udc_stop = dwc3_gadget_stop,
1970};
1971
1972/* -------------------------------------------------------------------------- */
1973
f3bcfc7e 1974static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
72246da4
FB		 1975{
1976 struct dwc3_ep *dep;
47d3946e 1977 u8 epnum;
72246da4 1978
f3bcfc7e
BD		 1979 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1980
47d3946e
BD		 1981 for (epnum = 0; epnum < num; epnum++) {
1982 bool direction = epnum & 1;
72246da4 1983
72246da4 1984 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1985 if (!dep)
72246da4 1986 return -ENOMEM;
72246da4
FB		 1987
1988 dep->dwc = dwc;
1989 dep->number = epnum;
47d3946e 1990 dep->direction = direction;
2eb88016 1991 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1992 dwc->eps[epnum] = dep;
1993
1994 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
47d3946e 1995 direction ? "in" : "out");
6a1e3ef4 1996
72246da4 1997 dep->endpoint.name = dep->name;
39ebb05c
JY		 1998
1999 if (!(dep->number > 1)) {
2000 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2001 dep->endpoint.comp_desc = NULL;
2002 }
2003
74674cbf 2004 spin_lock_init(&dep->lock);
72246da4
FB		 2005
2006 if (epnum == 0 || epnum == 1) {
e117e742 2007 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2008 dep->endpoint.maxburst = 1;
72246da4
FB		 2009 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2010 if (!epnum)
2011 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2012 } else if (direction) {
2013 int mdwidth;
2014 int size;
2015 int ret;
2016 int num;
2017
2018 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2019 /* MDWIDTH is represented in bits, we need it in bytes */
2020 mdwidth /= 8;
2021
47d3946e 2022 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
28781789
FB		 2023 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2024
2025 /* FIFO Depth is in MDWDITH bytes. Multiply */
2026 size *= mdwidth;
2027
2028 num = size / 1024;
2029 if (num == 0)
2030 num = 1;
2031
2032 /*
2033 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2034 * internal overhead. We don't really know how these are used,
2035 * but documentation say it exists.
2036 */
2037 size -= mdwidth * (num + 1);
2038 size /= num;
2039
2040 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2041
2042 dep->endpoint.max_streams = 15;
2043 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2044 list_add_tail(&dep->endpoint.ep_list,
2045 &dwc->gadget.ep_list);
2046
2047 ret = dwc3_alloc_trb_pool(dep);
2048 if (ret)
2049 return ret;
72246da4
FB		 2050 } else {
2051 int ret;
2052
e117e742 2053 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2054 dep->endpoint.max_streams = 15;
72246da4
FB		 2055 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2056 list_add_tail(&dep->endpoint.ep_list,
2057 &dwc->gadget.ep_list);
2058
2059 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2060 if (ret)
72246da4 2061 return ret;
72246da4 2062 }
25b8ff68 2063
a474d3b7
RB		 2064 if (epnum == 0 || epnum == 1) {
2065 dep->endpoint.caps.type_control = true;
2066 } else {
2067 dep->endpoint.caps.type_iso = true;
2068 dep->endpoint.caps.type_bulk = true;
2069 dep->endpoint.caps.type_int = true;
2070 }
2071
47d3946e 2072 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2073 dep->endpoint.caps.dir_out = !direction;
2074
aa3342c8
FB		 2075 INIT_LIST_HEAD(&dep->pending_list);
2076 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2077 }
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2083{
2084 struct dwc3_ep *dep;
2085 u8 epnum;
2086
2087 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2088 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2089 if (!dep)
2090 continue;
5bf8fae3
GC		 2091 /*
2092 * Physical endpoints 0 and 1 are special; they form the
2093 * bi-directional USB endpoint 0.
2094 *
2095 * For those two physical endpoints, we don't allocate a TRB
2096 * pool nor do we add them the endpoints list. Due to that, we
2097 * shouldn't do these two operations otherwise we would end up
2098 * with all sorts of bugs when removing dwc3.ko.
2099 */
2100 if (epnum != 0 && epnum != 1) {
2101 dwc3_free_trb_pool(dep);
72246da4 2102 list_del(&dep->endpoint.ep_list);
5bf8fae3 2103 }
72246da4
FB		 2104
2105 kfree(dep);
2106 }
2107}
2108
72246da4 2109/* -------------------------------------------------------------------------- */
e5caff68 2110
e5ba5ec8
PA		 2111static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2112 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2113 const struct dwc3_event_depevt *event, int status,
2114 int chain)
72246da4 2115{
72246da4
FB		 2116 unsigned int count;
2117 unsigned int s_pkt = 0;
d6d6ec7b 2118 unsigned int trb_status;
72246da4 2119
dc55c67e 2120 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2121
2122 if (req->trb == trb)
2123 dep->queued_requests--;
2124
2c4cbe6e
FB		 2125 trace_dwc3_complete_trb(dep, trb);
2126
e5b36ae2
FB		 2127 /*
2128 * If we're in the middle of series of chained TRBs and we
2129 * receive a short transfer along the way, DWC3 will skip
2130 * through all TRBs including the last TRB in the chain (the
2131 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2132 * bit and SW has to do it manually.
2133 *
2134 * We're going to do that here to avoid problems of HW trying
2135 * to use bogus TRBs for transfers.
2136 */
2137 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2138 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2139
c6267a51
FB		 2140 /*
2141 * If we're dealing with unaligned size OUT transfer, we will be left
2142 * with one TRB pending in the ring. We need to manually clear HWO bit
2143 * from that TRB.
2144 */
d6e5a549 2145 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
c6267a51
FB		 2146 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2147 return 1;
2148 }
2149
e5ba5ec8 2150 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2151 req->remaining += count;
e5ba5ec8 2152
35b2719e
FB		 2153 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2154 return 1;
2155
e5ba5ec8
PA		 2156 if (dep->direction) {
2157 if (count) {
2158 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2159 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2160 /*
2161 * If missed isoc occurred and there is
2162 * no request queued then issue END
2163 * TRANSFER, so that core generates
2164 * next xfernotready and we will issue
2165 * a fresh START TRANSFER.
2166 * If there are still queued request
2167 * then wait, do not issue either END
2168 * or UPDATE TRANSFER, just attach next
aa3342c8 2169 * request in pending_list during
e5ba5ec8
PA		 2170 * giveback.If any future queued request
2171 * is successfully transferred then we
2172 * will issue UPDATE TRANSFER for all
aa3342c8 2173 * request in the pending_list.
e5ba5ec8
PA		 2174 */
2175 dep->flags |= DWC3_EP_MISSED_ISOC;
2176 } else {
2177 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2178 dep->name);
2179 status = -ECONNRESET;
2180 }
2181 } else {
2182 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2183 }
2184 } else {
2185 if (count && (event->status & DEPEVT_STATUS_SHORT))
2186 s_pkt = 1;
2187 }
2188
7c705dfe 2189 if (s_pkt && !chain)
e5ba5ec8 2190 return 1;
f99f53f2 2191
e5ba5ec8
PA		 2192 if ((event->status & DEPEVT_STATUS_IOC) &&
2193 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2194 return 1;
f99f53f2 2195
e5ba5ec8
PA		 2196 return 0;
2197}
2198
2199static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2200 const struct dwc3_event_depevt *event, int status)
2201{
31162af4 2202 struct dwc3_request *req, *n;
e5ba5ec8 2203 struct dwc3_trb *trb;
d6e10bf2 2204 bool ioc = false;
e62c5bc5 2205 int ret = 0;
e5ba5ec8 2206
31162af4 2207 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2208 unsigned length;
e5b36ae2
FB		 2209 int chain;
2210
1f512119
FB		 2211 length = req->request.length;
2212 chain = req->num_pending_sgs > 0;
31162af4 2213 if (chain) {
1f512119 2214 struct scatterlist *sg = req->sg;
31162af4 2215 struct scatterlist *s;
1f512119 2216 unsigned int pending = req->num_pending_sgs;
31162af4 2217 unsigned int i;
c7de5734 2218
1f512119 2219 for_each_sg(sg, s, pending, i) {
31162af4 2220 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2221
7282c4ef
FB		 2222 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2223 break;
2224
1f512119
FB		 2225 req->sg = sg_next(s);
2226 req->num_pending_sgs--;
2227
31162af4
FB		 2228 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2229 event, status, chain);
1f512119
FB		 2230 if (ret)
2231 break;
31162af4
FB		 2232 }
2233 } else {
737f1ae2 2234 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2235 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2236 event, status, chain);
31162af4 2237 }
d115d705 2238
d6e5a549 2239 if (req->unaligned || req->zero) {
c6267a51
FB		 2240 trb = &dep->trb_pool[dep->trb_dequeue];
2241 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2242 event, status, false);
2243 req->unaligned = false;
d6e5a549 2244 req->zero = false;
c6267a51
FB		 2245 }
2246
e62c5bc5 2247 req->request.actual = length - req->remaining;
1f512119 2248
ff377ae4 2249 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2250 return __dwc3_gadget_kick_transfer(dep, 0);
2251
d115d705 2252 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2253
d6e10bf2
AB		 2254 if (ret) {
2255 if ((event->status & DEPEVT_STATUS_IOC) &&
2256 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2257 ioc = true;
72246da4 2258 break;
d6e10bf2 2259 }
31162af4 2260 }
72246da4 2261
4cb42217
FB		 2262 /*
2263 * Our endpoint might get disabled by another thread during
2264 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2265 * early on so DWC3_EP_BUSY flag gets cleared
2266 */
2267 if (!dep->endpoint.desc)
2268 return 1;
2269
cdc359dd 2270 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2271 list_empty(&dep->started_list)) {
2272 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2273 /*
2274 * If there is no entry in request list then do
2275 * not issue END TRANSFER now. Just set PENDING
2276 * flag, so that END TRANSFER is issued when an
2277 * entry is added into request list.
2278 */
2279 dep->flags = DWC3_EP_PENDING_REQUEST;
2280 } else {
b992e681 2281 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2282 dep->flags = DWC3_EP_ENABLED;
2283 }
7efea86c
PA		 2284 return 1;
2285 }
2286
d6e10bf2
AB		 2287 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2288 return 0;
2289
72246da4
FB		 2290 return 1;
2291}
2292
2293static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2294 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2295{
2296 unsigned status = 0;
2297 int clean_busy;
e18b7975
FB		 2298 u32 is_xfer_complete;
2299
2300 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2301
2302 if (event->status & DEPEVT_STATUS_BUSERR)
2303 status = -ECONNRESET;
2304
1d046793 2305 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2306 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2307 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2308 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2309
2310 /*
2311 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2312 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2313 */
2314 if (dwc->revision < DWC3_REVISION_183A) {
2315 u32 reg;
2316 int i;
2317
2318 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2319 dep = dwc->eps[i];
fae2b904
FB		 2320
2321 if (!(dep->flags & DWC3_EP_ENABLED))
2322 continue;
2323
aa3342c8 2324 if (!list_empty(&dep->started_list))
fae2b904
FB		 2325 return;
2326 }
2327
2328 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2329 reg |= dwc->u1u2;
2330 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2331
2332 dwc->u1u2 = 0;
2333 }
8a1a9c9e 2334
4cb42217
FB		 2335 /*
2336 * Our endpoint might get disabled by another thread during
2337 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2338 * early on so DWC3_EP_BUSY flag gets cleared
2339 */
2340 if (!dep->endpoint.desc)
2341 return;
2342
e6e709b7 2343 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2344 int ret;
2345
4fae2e3e 2346 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2347 if (!ret || ret == -EBUSY)
2348 return;
2349 }
72246da4
FB		 2350}
2351
72246da4
FB		 2352static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2353 const struct dwc3_event_depevt *event)
2354{
2355 struct dwc3_ep *dep;
2356 u8 epnum = event->endpoint_number;
76a638f8 2357 u8 cmd;
72246da4
FB		 2358
2359 dep = dwc->eps[epnum];
2360
d7fd41c6
JD		 2361 if (!(dep->flags & DWC3_EP_ENABLED)) {
2362 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2363 return;
2364
2365 /* Handle only EPCMDCMPLT when EP disabled */
2366 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2367 return;
2368 }
3336abb5 2369
72246da4
FB		 2370 if (epnum == 0 || epnum == 1) {
2371 dwc3_ep0_interrupt(dwc, event);
2372 return;
2373 }
2374
2375 switch (event->endpoint_event) {
2376 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2377 dep->resource_index = 0;
c2df85ca 2378
16e78db7 2379 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2380 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2381 return;
2382 }
2383
029d97ff 2384 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2385 break;
2386 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2387 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2388 break;
2389 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2390 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2391 dwc3_gadget_start_isoc(dwc, dep, event);
2392 } else {
2393 int ret;
2394
4fae2e3e 2395 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2396 if (!ret || ret == -EBUSY)
2397 return;
72246da4
FB		 2398 }
2399
879631aa
FB		 2400 break;
2401 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2402 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2403 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2404 dep->name);
2405 return;
2406 }
72246da4 2407 break;
72246da4 2408 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2409 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2410
2411 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2412 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2413 wake_up(&dep->wait_end_transfer);
2414 }
2415 break;
2416 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2417 break;
2418 }
2419}
2420
2421static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2422{
2423 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2424 spin_unlock(&dwc->lock);
2425 dwc->gadget_driver->disconnect(&dwc->gadget);
2426 spin_lock(&dwc->lock);
2427 }
2428}
2429
bc5ba2e0
FB		 2430static void dwc3_suspend_gadget(struct dwc3 *dwc)
2431{
73a30bfc 2432 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2433 spin_unlock(&dwc->lock);
2434 dwc->gadget_driver->suspend(&dwc->gadget);
2435 spin_lock(&dwc->lock);
2436 }
2437}
2438
2439static void dwc3_resume_gadget(struct dwc3 *dwc)
2440{
73a30bfc 2441 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2442 spin_unlock(&dwc->lock);
2443 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2444 spin_lock(&dwc->lock);
8e74475b
FB		 2445 }
2446}
2447
2448static void dwc3_reset_gadget(struct dwc3 *dwc)
2449{
2450 if (!dwc->gadget_driver)
2451 return;
2452
2453 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2454 spin_unlock(&dwc->lock);
2455 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2456 spin_lock(&dwc->lock);
2457 }
2458}
2459
b992e681 2460static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2461{
2462 struct dwc3_ep *dep;
2463 struct dwc3_gadget_ep_cmd_params params;
2464 u32 cmd;
2465 int ret;
2466
2467 dep = dwc->eps[epnum];
2468
76a638f8
BW		 2469 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2470 !dep->resource_index)
3daf74d7
PA		 2471 return;
2472
57911504
PA		 2473 /*
2474 * NOTICE: We are violating what the Databook says about the
2475 * EndTransfer command. Ideally we would _always_ wait for the
2476 * EndTransfer Command Completion IRQ, but that's causing too
2477 * much trouble synchronizing between us and gadget driver.
2478 *
2479 * We have discussed this with the IP Provider and it was
2480 * suggested to giveback all requests here, but give HW some
2481 * extra time to synchronize with the interconnect. We're using
dc93b41a 2482 * an arbitrary 100us delay for that.
57911504
PA		 2483 *
2484 * Note also that a similar handling was tested by Synopsys
2485 * (thanks a lot Paul) and nothing bad has come out of it.
2486 * In short, what we're doing is:
2487 *
2488 * - Issue EndTransfer WITH CMDIOC bit set
2489 * - Wait 100us
06281d46
JY		 2490 *
2491 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2492 * supports a mode to work around the above limitation. The
2493 * software can poll the CMDACT bit in the DEPCMD register
2494 * after issuing a EndTransfer command. This mode is enabled
2495 * by writing GUCTL2[14]. This polling is already done in the
2496 * dwc3_send_gadget_ep_cmd() function so if the mode is
2497 * enabled, the EndTransfer command will have completed upon
2498 * returning from this function and we don't need to delay for
2499 * 100us.
2500 *
2501 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2502 */
2503
3daf74d7 2504 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2505 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2506 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2507 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2508 memset(&params, 0, sizeof(params));
2cd4718d 2509 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2510 WARN_ON_ONCE(ret);
b4996a86 2511 dep->resource_index = 0;
041d81f4 2512 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2513
76a638f8
BW		 2514 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2515 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2516 udelay(100);
76a638f8 2517 }
72246da4
FB		 2518}
2519
72246da4
FB		 2520static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2521{
2522 u32 epnum;
2523
2524 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2525 struct dwc3_ep *dep;
72246da4
FB		 2526 int ret;
2527
2528 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2529 if (!dep)
2530 continue;
72246da4
FB		 2531
2532 if (!(dep->flags & DWC3_EP_STALL))
2533 continue;
2534
2535 dep->flags &= ~DWC3_EP_STALL;
2536
50c763f8 2537 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2538 WARN_ON_ONCE(ret);
2539 }
2540}
2541
2542static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2543{
c4430a26
FB		 2544 int reg;
2545
72246da4
FB		 2546 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2547 reg &= ~DWC3_DCTL_INITU1ENA;
2548 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2549
2550 reg &= ~DWC3_DCTL_INITU2ENA;
2551 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2552
72246da4
FB		 2553 dwc3_disconnect_gadget(dwc);
2554
2555 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2556 dwc->setup_packet_pending = false;
06a374ed 2557 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2558
2559 dwc->connected = false;
72246da4
FB		 2560}
2561
72246da4
FB		 2562static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2563{
2564 u32 reg;
2565
fc8bb91b
FB		 2566 dwc->connected = true;
2567
df62df56
FB		 2568 /*
2569 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2570 * would cause a missing Disconnect Event if there's a
2571 * pending Setup Packet in the FIFO.
2572 *
2573 * There's no suggested workaround on the official Bug
2574 * report, which states that "unless the driver/application
2575 * is doing any special handling of a disconnect event,
2576 * there is no functional issue".
2577 *
2578 * Unfortunately, it turns out that we _do_ some special
2579 * handling of a disconnect event, namely complete all
2580 * pending transfers, notify gadget driver of the
2581 * disconnection, and so on.
2582 *
2583 * Our suggested workaround is to follow the Disconnect
2584 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2585 * flag. Such flag gets set whenever we have a SETUP_PENDING
2586 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2587 * same endpoint.
2588 *
2589 * Refers to:
2590 *
2591 * STAR#9000466709: RTL: Device : Disconnect event not
2592 * generated if setup packet pending in FIFO
2593 */
2594 if (dwc->revision < DWC3_REVISION_188A) {
2595 if (dwc->setup_packet_pending)
2596 dwc3_gadget_disconnect_interrupt(dwc);
2597 }
2598
8e74475b 2599 dwc3_reset_gadget(dwc);
72246da4
FB		 2600
2601 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2602 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2603 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2604 dwc->test_mode = false;
72246da4
FB		 2605 dwc3_clear_stall_all_ep(dwc);
2606
2607 /* Reset device address to zero */
2608 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2609 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2610 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2611}
2612
72246da4
FB		 2613static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2614{
72246da4
FB		 2615 struct dwc3_ep *dep;
2616 int ret;
2617 u32 reg;
2618 u8 speed;
2619
72246da4
FB		 2620 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2621 speed = reg & DWC3_DSTS_CONNECTSPD;
2622 dwc->speed = speed;
2623
5fb6fdaf
JY		 2624 /*
2625 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2626 * each time on Connect Done.
2627 *
2628 * Currently we always use the reset value. If any platform
2629 * wants to set this to a different value, we need to add a
2630 * setting and update GCTL.RAMCLKSEL here.
2631 */
72246da4
FB		 2632
2633 switch (speed) {
2da9ad76 2634 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2635 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2636 dwc->gadget.ep0->maxpacket = 512;
2637 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2638 break;
2da9ad76 2639 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2640 /*
2641 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2642 * would cause a missing USB3 Reset event.
2643 *
2644 * In such situations, we should force a USB3 Reset
2645 * event by calling our dwc3_gadget_reset_interrupt()
2646 * routine.
2647 *
2648 * Refers to:
2649 *
2650 * STAR#9000483510: RTL: SS : USB3 reset event may
2651 * not be generated always when the link enters poll
2652 */
2653 if (dwc->revision < DWC3_REVISION_190A)
2654 dwc3_gadget_reset_interrupt(dwc);
2655
72246da4
FB		 2656 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2657 dwc->gadget.ep0->maxpacket = 512;
2658 dwc->gadget.speed = USB_SPEED_SUPER;
2659 break;
2da9ad76 2660 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2661 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2662 dwc->gadget.ep0->maxpacket = 64;
2663 dwc->gadget.speed = USB_SPEED_HIGH;
2664 break;
9418ee15 2665 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2666 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2667 dwc->gadget.ep0->maxpacket = 64;
2668 dwc->gadget.speed = USB_SPEED_FULL;
2669 break;
2da9ad76 2670 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2671 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2672 dwc->gadget.ep0->maxpacket = 8;
2673 dwc->gadget.speed = USB_SPEED_LOW;
2674 break;
2675 }
2676
2b758350
PA		 2677 /* Enable USB2 LPM Capability */
2678
ee5cd41c 2679 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2680 (speed != DWC3_DSTS_SUPERSPEED) &&
2681 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2682 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2683 reg |= DWC3_DCFG_LPM_CAP;
2684 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2685
2686 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2687 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2688
460d098c 2689 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2690
80caf7d2
HR		 2691 /*
2692 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2693 * DCFG.LPMCap is set, core responses with an ACK and the
2694 * BESL value in the LPM token is less than or equal to LPM
2695 * NYET threshold.
2696 */
2697 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2698 && dwc->has_lpm_erratum,
9165dabb 2699 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2700
2701 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2702 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2703
356363bf
FB		 2704 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2705 } else {
2706 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2707 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2708 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2709 }
2710
72246da4 2711 dep = dwc->eps[0];
39ebb05c 2712 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2713 if (ret) {
2714 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2715 return;
2716 }
2717
2718 dep = dwc->eps[1];
39ebb05c 2719 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2720 if (ret) {
2721 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2722 return;
2723 }
2724
2725 /*
2726 * Configure PHY via GUSB3PIPECTLn if required.
2727 *
2728 * Update GTXFIFOSIZn
2729 *
2730 * In both cases reset values should be sufficient.
2731 */
2732}
2733
2734static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2735{
72246da4
FB		 2736 /*
2737 * TODO take core out of low power mode when that's
2738 * implemented.
2739 */
2740
ad14d4e0
JL		 2741 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2742 spin_unlock(&dwc->lock);
2743 dwc->gadget_driver->resume(&dwc->gadget);
2744 spin_lock(&dwc->lock);
2745 }
72246da4
FB		 2746}
2747
2748static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2749 unsigned int evtinfo)
2750{
fae2b904 2751 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2752 unsigned int pwropt;
2753
2754 /*
2755 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2756 * Hibernation mode enabled which would show up when device detects
2757 * host-initiated U3 exit.
2758 *
2759 * In that case, device will generate a Link State Change Interrupt
2760 * from U3 to RESUME which is only necessary if Hibernation is
2761 * configured in.
2762 *
2763 * There are no functional changes due to such spurious event and we
2764 * just need to ignore it.
2765 *
2766 * Refers to:
2767 *
2768 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2769 * operational mode
2770 */
2771 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2772 if ((dwc->revision < DWC3_REVISION_250A) &&
2773 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2774 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2775 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2776 return;
2777 }
2778 }
fae2b904
FB		 2779
2780 /*
2781 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2782 * on the link partner, the USB session might do multiple entry/exit
2783 * of low power states before a transfer takes place.
2784 *
2785 * Due to this problem, we might experience lower throughput. The
2786 * suggested workaround is to disable DCTL[12:9] bits if we're
2787 * transitioning from U1/U2 to U0 and enable those bits again
2788 * after a transfer completes and there are no pending transfers
2789 * on any of the enabled endpoints.
2790 *
2791 * This is the first half of that workaround.
2792 *
2793 * Refers to:
2794 *
2795 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2796 * core send LGO_Ux entering U0
2797 */
2798 if (dwc->revision < DWC3_REVISION_183A) {
2799 if (next == DWC3_LINK_STATE_U0) {
2800 u32 u1u2;
2801 u32 reg;
2802
2803 switch (dwc->link_state) {
2804 case DWC3_LINK_STATE_U1:
2805 case DWC3_LINK_STATE_U2:
2806 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2807 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2808 | DWC3_DCTL_ACCEPTU2ENA
2809 | DWC3_DCTL_INITU1ENA
2810 | DWC3_DCTL_ACCEPTU1ENA);
2811
2812 if (!dwc->u1u2)
2813 dwc->u1u2 = reg & u1u2;
2814
2815 reg &= ~u1u2;
2816
2817 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2818 break;
2819 default:
2820 /* do nothing */
2821 break;
2822 }
2823 }
2824 }
2825
bc5ba2e0
FB		 2826 switch (next) {
2827 case DWC3_LINK_STATE_U1:
2828 if (dwc->speed == USB_SPEED_SUPER)
2829 dwc3_suspend_gadget(dwc);
2830 break;
2831 case DWC3_LINK_STATE_U2:
2832 case DWC3_LINK_STATE_U3:
2833 dwc3_suspend_gadget(dwc);
2834 break;
2835 case DWC3_LINK_STATE_RESUME:
2836 dwc3_resume_gadget(dwc);
2837 break;
2838 default:
2839 /* do nothing */
2840 break;
2841 }
2842
e57ebc1d 2843 dwc->link_state = next;
72246da4
FB		 2844}
2845
72704f87
BW		 2846static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2847 unsigned int evtinfo)
2848{
2849 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2850
2851 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2852 dwc3_suspend_gadget(dwc);
2853
2854 dwc->link_state = next;
2855}
2856
e1dadd3b
FB		 2857static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2858 unsigned int evtinfo)
2859{
2860 unsigned int is_ss = evtinfo & BIT(4);
2861
2862 /**
2863 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2864 * have a known issue which can cause USB CV TD.9.23 to fail
2865 * randomly.
2866 *
2867 * Because of this issue, core could generate bogus hibernation
2868 * events which SW needs to ignore.
2869 *
2870 * Refers to:
2871 *
2872 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2873 * Device Fallback from SuperSpeed
2874 */
2875 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2876 return;
2877
2878 /* enter hibernation here */
2879}
2880
72246da4
FB		 2881static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2882 const struct dwc3_event_devt *event)
2883{
2884 switch (event->type) {
2885 case DWC3_DEVICE_EVENT_DISCONNECT:
2886 dwc3_gadget_disconnect_interrupt(dwc);
2887 break;
2888 case DWC3_DEVICE_EVENT_RESET:
2889 dwc3_gadget_reset_interrupt(dwc);
2890 break;
2891 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2892 dwc3_gadget_conndone_interrupt(dwc);
2893 break;
2894 case DWC3_DEVICE_EVENT_WAKEUP:
2895 dwc3_gadget_wakeup_interrupt(dwc);
2896 break;
e1dadd3b
FB		 2897 case DWC3_DEVICE_EVENT_HIBER_REQ:
2898 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2899 "unexpected hibernation event\n"))
2900 break;
2901
2902 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2903 break;
72246da4
FB		 2904 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2905 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2906 break;
2907 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2908 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2909 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2910 /*
2911 * Ignore suspend event until the gadget enters into
2912 * USB_STATE_CONFIGURED state.
2913 */
2914 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2915 dwc3_gadget_suspend_interrupt(dwc,
2916 event->event_info);
2917 }
72246da4
FB		 2918 break;
2919 case DWC3_DEVICE_EVENT_SOF:
72246da4 2920 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2921 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2922 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2923 break;
2924 default:
e9f2aa87 2925 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2926 }
2927}
2928
2929static void dwc3_process_event_entry(struct dwc3 *dwc,
2930 const union dwc3_event *event)
2931{
43c96be1 2932 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2933
72246da4
FB		 2934 /* Endpoint IRQ, handle it and return early */
2935 if (event->type.is_devspec == 0) {
2936 /* depevt */
2937 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2938 }
2939
2940 switch (event->type.type) {
2941 case DWC3_EVENT_TYPE_DEV:
2942 dwc3_gadget_interrupt(dwc, &event->devt);
2943 break;
2944 /* REVISIT what to do with Carkit and I2C events ? */
2945 default:
2946 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2947 }
2948}
2949
dea520a4 2950static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2951{
dea520a4 2952 struct dwc3 *dwc = evt->dwc;
b15a762f 2953 irqreturn_t ret = IRQ_NONE;
f42f2447 2954 int left;
e8adfc30 2955 u32 reg;
b15a762f 2956
f42f2447 2957 left = evt->count;
b15a762f 2958
f42f2447
FB		 2959 if (!(evt->flags & DWC3_EVENT_PENDING))
2960 return IRQ_NONE;
b15a762f 2961
f42f2447
FB		 2962 while (left > 0) {
2963 union dwc3_event event;
b15a762f 2964
ebbb2d59 2965 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2966
f42f2447 2967 dwc3_process_event_entry(dwc, &event);
b15a762f 2968
f42f2447
FB		 2969 /*
2970 * FIXME we wrap around correctly to the next entry as
2971 * almost all entries are 4 bytes in size. There is one
2972 * entry which has 12 bytes which is a regular entry
2973 * followed by 8 bytes data. ATM I don't know how
2974 * things are organized if we get next to the a
2975 * boundary so I worry about that once we try to handle
2976 * that.
2977 */
caefe6c7 2978 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2979 left -= 4;
f42f2447 2980 }
b15a762f 2981
f42f2447
FB		 2982 evt->count = 0;
2983 evt->flags &= ~DWC3_EVENT_PENDING;
2984 ret = IRQ_HANDLED;
b15a762f 2985
f42f2447 2986 /* Unmask interrupt */
660e9bde 2987 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2988 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2989 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2990
cf40b86b
JY		 2991 if (dwc->imod_interval) {
2992 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2993 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2994 }
2995
f42f2447
FB		 2996 return ret;
2997}
e8adfc30 2998
dea520a4 2999static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3000{
dea520a4
FB		 3001 struct dwc3_event_buffer *evt = _evt;
3002 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3003 unsigned long flags;
f42f2447 3004 irqreturn_t ret = IRQ_NONE;
f42f2447 3005
e5f68b4a 3006 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3007 ret = dwc3_process_event_buf(evt);
e5f68b4a 3008 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3009
3010 return ret;
3011}
3012
dea520a4 3013static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3014{
dea520a4 3015 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3016 u32 amount;
72246da4 3017 u32 count;
e8adfc30 3018 u32 reg;
72246da4 3019
fc8bb91b
FB		 3020 if (pm_runtime_suspended(dwc->dev)) {
3021 pm_runtime_get(dwc->dev);
3022 disable_irq_nosync(dwc->irq_gadget);
3023 dwc->pending_events = true;
3024 return IRQ_HANDLED;
3025 }
3026
660e9bde 3027 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3028 count &= DWC3_GEVNTCOUNT_MASK;
3029 if (!count)
3030 return IRQ_NONE;
3031
b15a762f
FB		 3032 evt->count = count;
3033 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3034
e8adfc30 3035 /* Mask interrupt */
660e9bde 3036 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3037 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3038 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3039
ebbb2d59
JY		 3040 amount = min(count, evt->length - evt->lpos);
3041 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3042
3043 if (amount < count)
3044 memcpy(evt->cache, evt->buf, count - amount);
3045
65aca320
JY		 3046 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3047
b15a762f 3048 return IRQ_WAKE_THREAD;
72246da4
FB		 3049}
3050
dea520a4 3051static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3052{
dea520a4 3053 struct dwc3_event_buffer *evt = _evt;
72246da4 3054
dea520a4 3055 return dwc3_check_event_buf(evt);
72246da4
FB		 3056}
3057
6db3812e
FB		 3058static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3059{
3060 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3061 int irq;
3062
3063 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3064 if (irq > 0)
3065 goto out;
3066
3067 if (irq == -EPROBE_DEFER)
3068 goto out;
3069
3070 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3071 if (irq > 0)
3072 goto out;
3073
3074 if (irq == -EPROBE_DEFER)
3075 goto out;
3076
3077 irq = platform_get_irq(dwc3_pdev, 0);
3078 if (irq > 0)
3079 goto out;
3080
3081 if (irq != -EPROBE_DEFER)
3082 dev_err(dwc->dev, "missing peripheral IRQ\n");
3083
3084 if (!irq)
3085 irq = -EINVAL;
3086
3087out:
3088 return irq;
3089}
3090
72246da4
FB		 3091/**
3092 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3093 * @dwc: pointer to our controller context structure
72246da4
FB		 3094 *
3095 * Returns 0 on success otherwise negative errno.
3096 */
41ac7b3a 3097int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3098{
6db3812e
FB		 3099 int ret;
3100 int irq;
9522def4 3101
6db3812e
FB		 3102 irq = dwc3_gadget_get_irq(dwc);
3103 if (irq < 0) {
3104 ret = irq;
3105 goto err0;
9522def4
RQ		 3106 }
3107
3108 dwc->irq_gadget = irq;
72246da4 3109
d64ff406
AB		 3110 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3111 sizeof(*dwc->ep0_trb) * 2,
3112 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3113 if (!dwc->ep0_trb) {
3114 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3115 ret = -ENOMEM;
7d5e650a 3116 goto err0;
72246da4
FB		 3117 }
3118
4199c5f8 3119 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
72246da4 3120 if (!dwc->setup_buf) {
72246da4 3121 ret = -ENOMEM;
7d5e650a 3122 goto err1;
72246da4
FB		 3123 }
3124
905dc04e
FB		 3125 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3126 &dwc->bounce_addr, GFP_KERNEL);
3127 if (!dwc->bounce) {
3128 ret = -ENOMEM;
d6e5a549 3129 goto err2;
905dc04e
FB		 3130 }
3131
bb014736
BW		 3132 init_completion(&dwc->ep0_in_setup);
3133
72246da4 3134 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3135 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3136 dwc->gadget.sg_supported = true;
72246da4 3137 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3138 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3139
b9e51b2b
BM		 3140 /*
3141 * FIXME We might be setting max_speed to <SUPER, however versions
3142 * <2.20a of dwc3 have an issue with metastability (documented
3143 * elsewhere in this driver) which tells us we can't set max speed to
3144 * anything lower than SUPER.
3145 *
3146 * Because gadget.max_speed is only used by composite.c and function
3147 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3148 * to happen so we avoid sending SuperSpeed Capability descriptor
3149 * together with our BOS descriptor as that could confuse host into
3150 * thinking we can handle super speed.
3151 *
3152 * Note that, in fact, we won't even support GetBOS requests when speed
3153 * is less than super speed because we don't have means, yet, to tell
3154 * composite.c that we are USB 2.0 + LPM ECN.
3155 */
3156 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3157 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3158 dwc->revision);
3159
3160 dwc->gadget.max_speed = dwc->maximum_speed;
3161
72246da4
FB		 3162 /*
3163 * REVISIT: Here we should clear all pending IRQs to be
3164 * sure we're starting from a well known location.
3165 */
3166
f3bcfc7e 3167 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3168 if (ret)
d6e5a549 3169 goto err3;
72246da4 3170
72246da4
FB		 3171 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3172 if (ret) {
3173 dev_err(dwc->dev, "failed to register udc\n");
d6e5a549 3174 goto err4;
72246da4
FB		 3175 }
3176
3177 return 0;
3178
7d5e650a 3179err4:
d6e5a549 3180 dwc3_gadget_free_endpoints(dwc);
04c03d10 3181
7d5e650a 3182err3:
d6e5a549
FB		 3183 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3184 dwc->bounce_addr);
5812b1c2 3185
7d5e650a 3186err2:
0fc9a1be 3187 kfree(dwc->setup_buf);
72246da4 3188
7d5e650a 3189err1:
d64ff406 3190 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3191 dwc->ep0_trb, dwc->ep0_trb_addr);
3192
72246da4
FB		 3193err0:
3194 return ret;
3195}
3196
7415f17c
FB		 3197/* -------------------------------------------------------------------------- */
3198
72246da4
FB		 3199void dwc3_gadget_exit(struct dwc3 *dwc)
3200{
72246da4 3201 usb_del_gadget_udc(&dwc->gadget);
72246da4 3202 dwc3_gadget_free_endpoints(dwc);
905dc04e 3203 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
d6e5a549 3204 dwc->bounce_addr);
0fc9a1be 3205 kfree(dwc->setup_buf);
d64ff406 3206 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
d6e5a549 3207 dwc->ep0_trb, dwc->ep0_trb_addr);
72246da4 3208}
7415f17c 3209
0b0231aa 3210int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3211{
9772b47a
RQ		 3212 if (!dwc->gadget_driver)
3213 return 0;
3214
1551e35e 3215 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3216 dwc3_disconnect_gadget(dwc);
3217 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3218
3219 return 0;
3220}
3221
3222int dwc3_gadget_resume(struct dwc3 *dwc)
3223{
7415f17c
FB		 3224 int ret;
3225
9772b47a
RQ		 3226 if (!dwc->gadget_driver)
3227 return 0;
3228
9f8a67b6
FB		 3229 ret = __dwc3_gadget_start(dwc);
3230 if (ret < 0)
7415f17c
FB		 3231 goto err0;
3232
9f8a67b6
FB		 3233 ret = dwc3_gadget_run_stop(dwc, true, false);
3234 if (ret < 0)
7415f17c
FB		 3235 goto err1;
3236
7415f17c
FB		 3237 return 0;
3238
3239err1:
9f8a67b6 3240 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3241
3242err0:
3243 return ret;
3244}
fc8bb91b
FB		 3245
3246void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3247{
3248 if (dwc->pending_events) {
3249 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3250 dwc->pending_events = false;
3251 enable_irq(dwc->irq_gadget);
3252 }
3253}
Ubuntu Hirsute Linux kernel mirror