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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
73815280 FB |
142 | dwc3_trace(trace_dwc3_gadget, |
143 | "link state change request timed out"); | |
8598bde7 FB |
144 | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
457e84b6 FB |
148 | /** |
149 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
150 | * @dwc: pointer to our context structure | |
151 | * | |
152 | * This function will a best effort FIFO allocation in order | |
153 | * to improve FIFO usage and throughput, while still allowing | |
154 | * us to enable as many endpoints as possible. | |
155 | * | |
156 | * Keep in mind that this operation will be highly dependent | |
157 | * on the configured size for RAM1 - which contains TxFifo -, | |
158 | * the amount of endpoints enabled on coreConsultant tool, and | |
159 | * the width of the Master Bus. | |
160 | * | |
161 | * In the ideal world, we would always be able to satisfy the | |
162 | * following equation: | |
163 | * | |
164 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
165 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
166 | * | |
167 | * Unfortunately, due to many variables that's not always the case. | |
168 | */ | |
169 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
170 | { | |
171 | int last_fifo_depth = 0; | |
172 | int ram1_depth; | |
173 | int fifo_size; | |
174 | int mdwidth; | |
175 | int num; | |
176 | ||
177 | if (!dwc->needs_fifo_resize) | |
178 | return 0; | |
179 | ||
180 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
181 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
182 | ||
183 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
184 | mdwidth >>= 3; | |
185 | ||
186 | /* | |
187 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
188 | * for each enabled endpoint, later patches will come to | |
189 | * improve this algorithm so that we better use the internal | |
190 | * FIFO space | |
191 | */ | |
32702e96 JP |
192 | for (num = 0; num < dwc->num_in_eps; num++) { |
193 | /* bit0 indicates direction; 1 means IN ep */ | |
194 | struct dwc3_ep *dep = dwc->eps[(num << 1) | 1]; | |
2e81c36a | 195 | int mult = 1; |
457e84b6 FB |
196 | int tmp; |
197 | ||
457e84b6 FB |
198 | if (!(dep->flags & DWC3_EP_ENABLED)) |
199 | continue; | |
200 | ||
16e78db7 IS |
201 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
202 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
203 | mult = 3; |
204 | ||
205 | /* | |
206 | * REVISIT: the following assumes we will always have enough | |
207 | * space available on the FIFO RAM for all possible use cases. | |
208 | * Make sure that's true somehow and change FIFO allocation | |
209 | * accordingly. | |
210 | * | |
211 | * If we have Bulk or Isochronous endpoints, we want | |
212 | * them to be able to be very, very fast. So we're giving | |
213 | * those endpoints a fifo_size which is enough for 3 full | |
214 | * packets | |
215 | */ | |
216 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
217 | tmp += mdwidth; |
218 | ||
219 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 220 | |
457e84b6 FB |
221 | fifo_size |= (last_fifo_depth << 16); |
222 | ||
73815280 | 223 | dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d", |
457e84b6 FB |
224 | dep->name, last_fifo_depth, fifo_size & 0xffff); |
225 | ||
32702e96 | 226 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size); |
457e84b6 FB |
227 | |
228 | last_fifo_depth += (fifo_size & 0xffff); | |
229 | } | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
72246da4 FB |
234 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
235 | int status) | |
236 | { | |
237 | struct dwc3 *dwc = dep->dwc; | |
e5ba5ec8 | 238 | int i; |
72246da4 FB |
239 | |
240 | if (req->queued) { | |
e5ba5ec8 PA |
241 | i = 0; |
242 | do { | |
eeb720fb | 243 | dep->busy_slot++; |
e5ba5ec8 PA |
244 | /* |
245 | * Skip LINK TRB. We can't use req->trb and check for | |
246 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we | |
247 | * just completed (not the LINK TRB). | |
248 | */ | |
249 | if (((dep->busy_slot & DWC3_TRB_MASK) == | |
250 | DWC3_TRB_NUM- 1) && | |
16e78db7 | 251 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
e5ba5ec8 PA |
252 | dep->busy_slot++; |
253 | } while(++i < req->request.num_mapped_sgs); | |
c9fda7d6 | 254 | req->queued = false; |
72246da4 FB |
255 | } |
256 | list_del(&req->list); | |
eeb720fb | 257 | req->trb = NULL; |
72246da4 FB |
258 | |
259 | if (req->request.status == -EINPROGRESS) | |
260 | req->request.status = status; | |
261 | ||
0416e494 PA |
262 | if (dwc->ep0_bounced && dep->number == 0) |
263 | dwc->ep0_bounced = false; | |
264 | else | |
265 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
266 | req->direction); | |
72246da4 | 267 | |
2c4cbe6e | 268 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
269 | |
270 | spin_unlock(&dwc->lock); | |
304f7e5e | 271 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 FB |
272 | spin_lock(&dwc->lock); |
273 | } | |
274 | ||
3ece0ec4 | 275 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
276 | { |
277 | u32 timeout = 500; | |
278 | u32 reg; | |
279 | ||
2c4cbe6e | 280 | trace_dwc3_gadget_generic_cmd(cmd, param); |
427c3df6 | 281 | |
b09bb642 FB |
282 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); |
283 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
284 | ||
285 | do { | |
286 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
287 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
73815280 FB |
288 | dwc3_trace(trace_dwc3_gadget, |
289 | "Command Complete --> %d", | |
b09bb642 | 290 | DWC3_DGCMD_STATUS(reg)); |
891b1dc0 SSB |
291 | if (DWC3_DGCMD_STATUS(reg)) |
292 | return -EINVAL; | |
b09bb642 FB |
293 | return 0; |
294 | } | |
295 | ||
296 | /* | |
297 | * We can't sleep here, because it's also called from | |
298 | * interrupt context. | |
299 | */ | |
300 | timeout--; | |
73815280 FB |
301 | if (!timeout) { |
302 | dwc3_trace(trace_dwc3_gadget, | |
303 | "Command Timed Out"); | |
b09bb642 | 304 | return -ETIMEDOUT; |
73815280 | 305 | } |
b09bb642 FB |
306 | udelay(1); |
307 | } while (1); | |
308 | } | |
309 | ||
72246da4 FB |
310 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
311 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
312 | { | |
313 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 314 | u32 timeout = 500; |
72246da4 FB |
315 | u32 reg; |
316 | ||
2c4cbe6e | 317 | trace_dwc3_gadget_ep_cmd(dep, cmd, params); |
72246da4 | 318 | |
dc1c70a7 FB |
319 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
320 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
321 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
322 | |
323 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
324 | do { | |
325 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
326 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
73815280 FB |
327 | dwc3_trace(trace_dwc3_gadget, |
328 | "Command Complete --> %d", | |
164f6e14 | 329 | DWC3_DEPCMD_STATUS(reg)); |
76e838c9 SSB |
330 | if (DWC3_DEPCMD_STATUS(reg)) |
331 | return -EINVAL; | |
72246da4 FB |
332 | return 0; |
333 | } | |
334 | ||
335 | /* | |
72246da4 FB |
336 | * We can't sleep here, because it is also called from |
337 | * interrupt context. | |
338 | */ | |
339 | timeout--; | |
73815280 FB |
340 | if (!timeout) { |
341 | dwc3_trace(trace_dwc3_gadget, | |
342 | "Command Timed Out"); | |
72246da4 | 343 | return -ETIMEDOUT; |
73815280 | 344 | } |
72246da4 | 345 | |
61d58242 | 346 | udelay(1); |
72246da4 FB |
347 | } while (1); |
348 | } | |
349 | ||
350 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 351 | struct dwc3_trb *trb) |
72246da4 | 352 | { |
c439ef87 | 353 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
354 | |
355 | return dep->trb_pool_dma + offset; | |
356 | } | |
357 | ||
358 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
359 | { | |
360 | struct dwc3 *dwc = dep->dwc; | |
361 | ||
362 | if (dep->trb_pool) | |
363 | return 0; | |
364 | ||
72246da4 FB |
365 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
366 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
367 | &dep->trb_pool_dma, GFP_KERNEL); | |
368 | if (!dep->trb_pool) { | |
369 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
370 | dep->name); | |
371 | return -ENOMEM; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
378 | { | |
379 | struct dwc3 *dwc = dep->dwc; | |
380 | ||
381 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
382 | dep->trb_pool, dep->trb_pool_dma); | |
383 | ||
384 | dep->trb_pool = NULL; | |
385 | dep->trb_pool_dma = 0; | |
386 | } | |
387 | ||
388 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
389 | { | |
390 | struct dwc3_gadget_ep_cmd_params params; | |
391 | u32 cmd; | |
392 | ||
393 | memset(¶ms, 0x00, sizeof(params)); | |
394 | ||
395 | if (dep->number != 1) { | |
396 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
397 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
398 | if (dep->number > 1) { |
399 | if (dwc->start_config_issued) | |
400 | return 0; | |
401 | dwc->start_config_issued = true; | |
72246da4 | 402 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 403 | } |
72246da4 FB |
404 | |
405 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
406 | } | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 412 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 413 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 414 | bool ignore, bool restore) |
72246da4 FB |
415 | { |
416 | struct dwc3_gadget_ep_cmd_params params; | |
417 | ||
418 | memset(¶ms, 0x00, sizeof(params)); | |
419 | ||
dc1c70a7 | 420 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
421 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
422 | ||
423 | /* Burst size is only needed in SuperSpeed mode */ | |
424 | if (dwc->gadget.speed == USB_SPEED_SUPER) { | |
425 | u32 burst = dep->endpoint.maxburst - 1; | |
426 | ||
427 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); | |
428 | } | |
72246da4 | 429 | |
4b345c9a FB |
430 | if (ignore) |
431 | params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; | |
432 | ||
265b70a7 PZ |
433 | if (restore) { |
434 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; | |
435 | params.param2 |= dep->saved_state; | |
436 | } | |
437 | ||
dc1c70a7 FB |
438 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
439 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 440 | |
18b7ede5 | 441 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
442 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
443 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
444 | dep->stream_capable = true; |
445 | } | |
446 | ||
0b93a4c8 | 447 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 448 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
449 | |
450 | /* | |
451 | * We are doing 1:1 mapping for endpoints, meaning | |
452 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
453 | * so on. We consider the direction bit as part of the physical | |
454 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
455 | */ | |
dc1c70a7 | 456 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
457 | |
458 | /* | |
459 | * We must use the lower 16 TX FIFOs even though | |
460 | * HW might have more | |
461 | */ | |
462 | if (dep->direction) | |
dc1c70a7 | 463 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
464 | |
465 | if (desc->bInterval) { | |
dc1c70a7 | 466 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
467 | dep->interval = 1 << (desc->bInterval - 1); |
468 | } | |
469 | ||
470 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
471 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
472 | } | |
473 | ||
474 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
475 | { | |
476 | struct dwc3_gadget_ep_cmd_params params; | |
477 | ||
478 | memset(¶ms, 0x00, sizeof(params)); | |
479 | ||
dc1c70a7 | 480 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
481 | |
482 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
483 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
484 | } | |
485 | ||
486 | /** | |
487 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
488 | * @dep: endpoint to be initialized | |
489 | * @desc: USB Endpoint Descriptor | |
490 | * | |
491 | * Caller should take care of locking | |
492 | */ | |
493 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 494 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 495 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
265b70a7 | 496 | bool ignore, bool restore) |
72246da4 FB |
497 | { |
498 | struct dwc3 *dwc = dep->dwc; | |
499 | u32 reg; | |
b09e99ee | 500 | int ret; |
72246da4 | 501 | |
73815280 | 502 | dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name); |
ff62d6b6 | 503 | |
72246da4 FB |
504 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
505 | ret = dwc3_gadget_start_config(dwc, dep); | |
506 | if (ret) | |
507 | return ret; | |
508 | } | |
509 | ||
265b70a7 PZ |
510 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, |
511 | restore); | |
72246da4 FB |
512 | if (ret) |
513 | return ret; | |
514 | ||
515 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
516 | struct dwc3_trb *trb_st_hw; |
517 | struct dwc3_trb *trb_link; | |
72246da4 FB |
518 | |
519 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
520 | if (ret) | |
521 | return ret; | |
522 | ||
16e78db7 | 523 | dep->endpoint.desc = desc; |
c90bfaec | 524 | dep->comp_desc = comp_desc; |
72246da4 FB |
525 | dep->type = usb_endpoint_type(desc); |
526 | dep->flags |= DWC3_EP_ENABLED; | |
527 | ||
528 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
529 | reg |= DWC3_DALEPENA_EP(dep->number); | |
530 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
531 | ||
532 | if (!usb_endpoint_xfer_isoc(desc)) | |
533 | return 0; | |
534 | ||
1d046793 | 535 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
536 | trb_st_hw = &dep->trb_pool[0]; |
537 | ||
f6bafc6a | 538 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
1200a82a | 539 | memset(trb_link, 0, sizeof(*trb_link)); |
72246da4 | 540 | |
f6bafc6a FB |
541 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
542 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
543 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
544 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
545 | } |
546 | ||
aa739974 FB |
547 | switch (usb_endpoint_type(desc)) { |
548 | case USB_ENDPOINT_XFER_CONTROL: | |
549 | strlcat(dep->name, "-control", sizeof(dep->name)); | |
550 | break; | |
551 | case USB_ENDPOINT_XFER_ISOC: | |
552 | strlcat(dep->name, "-isoc", sizeof(dep->name)); | |
553 | break; | |
554 | case USB_ENDPOINT_XFER_BULK: | |
555 | strlcat(dep->name, "-bulk", sizeof(dep->name)); | |
556 | break; | |
557 | case USB_ENDPOINT_XFER_INT: | |
558 | strlcat(dep->name, "-int", sizeof(dep->name)); | |
559 | break; | |
560 | default: | |
561 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
562 | } | |
563 | ||
72246da4 FB |
564 | return 0; |
565 | } | |
566 | ||
b992e681 | 567 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 568 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
569 | { |
570 | struct dwc3_request *req; | |
571 | ||
ea53b882 | 572 | if (!list_empty(&dep->req_queued)) { |
b992e681 | 573 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 574 | |
57911504 | 575 | /* - giveback all requests to gadget driver */ |
1591633e PA |
576 | while (!list_empty(&dep->req_queued)) { |
577 | req = next_request(&dep->req_queued); | |
578 | ||
579 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); | |
580 | } | |
ea53b882 FB |
581 | } |
582 | ||
72246da4 FB |
583 | while (!list_empty(&dep->request_list)) { |
584 | req = next_request(&dep->request_list); | |
585 | ||
624407f9 | 586 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 587 | } |
72246da4 FB |
588 | } |
589 | ||
590 | /** | |
591 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
592 | * @dep: the endpoint to disable | |
593 | * | |
624407f9 SAS |
594 | * This function also removes requests which are currently processed ny the |
595 | * hardware and those which are not yet scheduled. | |
596 | * Caller should take care of locking. | |
72246da4 | 597 | */ |
72246da4 FB |
598 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
599 | { | |
600 | struct dwc3 *dwc = dep->dwc; | |
601 | u32 reg; | |
602 | ||
7eaeac5c FB |
603 | dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name); |
604 | ||
624407f9 | 605 | dwc3_remove_requests(dwc, dep); |
72246da4 | 606 | |
687ef981 FB |
607 | /* make sure HW endpoint isn't stalled */ |
608 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 609 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 610 | |
72246da4 FB |
611 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
612 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
613 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
614 | ||
879631aa | 615 | dep->stream_capable = false; |
f9c56cdd | 616 | dep->endpoint.desc = NULL; |
c90bfaec | 617 | dep->comp_desc = NULL; |
72246da4 | 618 | dep->type = 0; |
879631aa | 619 | dep->flags = 0; |
72246da4 | 620 | |
aa739974 FB |
621 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", |
622 | dep->number >> 1, | |
623 | (dep->number & 1) ? "in" : "out"); | |
624 | ||
72246da4 FB |
625 | return 0; |
626 | } | |
627 | ||
628 | /* -------------------------------------------------------------------------- */ | |
629 | ||
630 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
631 | const struct usb_endpoint_descriptor *desc) | |
632 | { | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
636 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
637 | { | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
641 | /* -------------------------------------------------------------------------- */ | |
642 | ||
643 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
644 | const struct usb_endpoint_descriptor *desc) | |
645 | { | |
646 | struct dwc3_ep *dep; | |
647 | struct dwc3 *dwc; | |
648 | unsigned long flags; | |
649 | int ret; | |
650 | ||
651 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
652 | pr_debug("dwc3: invalid parameters\n"); | |
653 | return -EINVAL; | |
654 | } | |
655 | ||
656 | if (!desc->wMaxPacketSize) { | |
657 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | dep = to_dwc3_ep(ep); | |
662 | dwc = dep->dwc; | |
663 | ||
c6f83f38 FB |
664 | if (dep->flags & DWC3_EP_ENABLED) { |
665 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
666 | dep->name); | |
667 | return 0; | |
668 | } | |
669 | ||
72246da4 | 670 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 671 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
672 | spin_unlock_irqrestore(&dwc->lock, flags); |
673 | ||
674 | return ret; | |
675 | } | |
676 | ||
677 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
678 | { | |
679 | struct dwc3_ep *dep; | |
680 | struct dwc3 *dwc; | |
681 | unsigned long flags; | |
682 | int ret; | |
683 | ||
684 | if (!ep) { | |
685 | pr_debug("dwc3: invalid parameters\n"); | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | dep = to_dwc3_ep(ep); | |
690 | dwc = dep->dwc; | |
691 | ||
692 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
693 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
694 | dep->name); | |
695 | return 0; | |
696 | } | |
697 | ||
72246da4 FB |
698 | spin_lock_irqsave(&dwc->lock, flags); |
699 | ret = __dwc3_gadget_ep_disable(dep); | |
700 | spin_unlock_irqrestore(&dwc->lock, flags); | |
701 | ||
702 | return ret; | |
703 | } | |
704 | ||
705 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
706 | gfp_t gfp_flags) | |
707 | { | |
708 | struct dwc3_request *req; | |
709 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
710 | |
711 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 712 | if (!req) |
72246da4 | 713 | return NULL; |
72246da4 FB |
714 | |
715 | req->epnum = dep->number; | |
716 | req->dep = dep; | |
72246da4 | 717 | |
2c4cbe6e FB |
718 | trace_dwc3_alloc_request(req); |
719 | ||
72246da4 FB |
720 | return &req->request; |
721 | } | |
722 | ||
723 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
724 | struct usb_request *request) | |
725 | { | |
726 | struct dwc3_request *req = to_dwc3_request(request); | |
727 | ||
2c4cbe6e | 728 | trace_dwc3_free_request(req); |
72246da4 FB |
729 | kfree(req); |
730 | } | |
731 | ||
c71fc37c FB |
732 | /** |
733 | * dwc3_prepare_one_trb - setup one TRB from one request | |
734 | * @dep: endpoint for which this request is prepared | |
735 | * @req: dwc3_request pointer | |
736 | */ | |
68e823e2 | 737 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 738 | struct dwc3_request *req, dma_addr_t dma, |
e5ba5ec8 | 739 | unsigned length, unsigned last, unsigned chain, unsigned node) |
c71fc37c | 740 | { |
f6bafc6a | 741 | struct dwc3_trb *trb; |
c71fc37c | 742 | |
73815280 | 743 | dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s", |
eeb720fb FB |
744 | dep->name, req, (unsigned long long) dma, |
745 | length, last ? " last" : "", | |
746 | chain ? " chain" : ""); | |
747 | ||
915e202a PA |
748 | |
749 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; | |
c71fc37c | 750 | |
eeb720fb FB |
751 | if (!req->trb) { |
752 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
753 | req->trb = trb; |
754 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
e5ba5ec8 | 755 | req->start_slot = dep->free_slot & DWC3_TRB_MASK; |
eeb720fb | 756 | } |
c71fc37c | 757 | |
e5ba5ec8 | 758 | dep->free_slot++; |
5cd8c48d ZJC |
759 | /* Skip the LINK-TRB on ISOC */ |
760 | if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
761 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
762 | dep->free_slot++; | |
e5ba5ec8 | 763 | |
f6bafc6a FB |
764 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
765 | trb->bpl = lower_32_bits(dma); | |
766 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 767 | |
16e78db7 | 768 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 769 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 770 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
771 | break; |
772 | ||
773 | case USB_ENDPOINT_XFER_ISOC: | |
e5ba5ec8 PA |
774 | if (!node) |
775 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; | |
776 | else | |
777 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; | |
c71fc37c FB |
778 | break; |
779 | ||
780 | case USB_ENDPOINT_XFER_BULK: | |
781 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 782 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
783 | break; |
784 | default: | |
785 | /* | |
786 | * This is only possible with faulty memory because we | |
787 | * checked it already :) | |
788 | */ | |
789 | BUG(); | |
790 | } | |
791 | ||
f3af3651 FB |
792 | if (!req->request.no_interrupt && !chain) |
793 | trb->ctrl |= DWC3_TRB_CTRL_IOC; | |
794 | ||
16e78db7 | 795 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
796 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
797 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
e5ba5ec8 PA |
798 | } else if (last) { |
799 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
f6bafc6a | 800 | } |
c71fc37c | 801 | |
e5ba5ec8 PA |
802 | if (chain) |
803 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
804 | ||
16e78db7 | 805 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 806 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 807 | |
f6bafc6a | 808 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
809 | |
810 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
811 | } |
812 | ||
72246da4 FB |
813 | /* |
814 | * dwc3_prepare_trbs - setup TRBs from requests | |
815 | * @dep: endpoint for which requests are being prepared | |
816 | * @starting: true if the endpoint is idle and no requests are queued. | |
817 | * | |
1d046793 PZ |
818 | * The function goes through the requests list and sets up TRBs for the |
819 | * transfers. The function returns once there are no more TRBs available or | |
820 | * it runs out of requests. | |
72246da4 | 821 | */ |
68e823e2 | 822 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 823 | { |
68e823e2 | 824 | struct dwc3_request *req, *n; |
72246da4 | 825 | u32 trbs_left; |
8d62cd65 | 826 | u32 max; |
c71fc37c | 827 | unsigned int last_one = 0; |
72246da4 FB |
828 | |
829 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
830 | ||
831 | /* the first request must not be queued */ | |
832 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 833 | |
8d62cd65 | 834 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 835 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
836 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
837 | if (trbs_left > max) | |
838 | trbs_left = max; | |
839 | } | |
840 | ||
72246da4 | 841 | /* |
1d046793 PZ |
842 | * If busy & slot are equal than it is either full or empty. If we are |
843 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
844 | * full and don't do anything |
845 | */ | |
846 | if (!trbs_left) { | |
847 | if (!starting) | |
68e823e2 | 848 | return; |
72246da4 FB |
849 | trbs_left = DWC3_TRB_NUM; |
850 | /* | |
851 | * In case we start from scratch, we queue the ISOC requests | |
852 | * starting from slot 1. This is done because we use ring | |
853 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 854 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
855 | * after the first request so we start at slot 1 and have |
856 | * 7 requests proceed before we hit the first IOC. | |
857 | * Other transfer types don't use the ring buffer and are | |
858 | * processed from the first TRB until the last one. Since we | |
859 | * don't wrap around we have to start at the beginning. | |
860 | */ | |
16e78db7 | 861 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
862 | dep->busy_slot = 1; |
863 | dep->free_slot = 1; | |
864 | } else { | |
865 | dep->busy_slot = 0; | |
866 | dep->free_slot = 0; | |
867 | } | |
868 | } | |
869 | ||
870 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 871 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 872 | return; |
72246da4 FB |
873 | |
874 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
875 | unsigned length; |
876 | dma_addr_t dma; | |
e5ba5ec8 | 877 | last_one = false; |
72246da4 | 878 | |
eeb720fb FB |
879 | if (req->request.num_mapped_sgs > 0) { |
880 | struct usb_request *request = &req->request; | |
881 | struct scatterlist *sg = request->sg; | |
882 | struct scatterlist *s; | |
883 | int i; | |
72246da4 | 884 | |
eeb720fb FB |
885 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
886 | unsigned chain = true; | |
72246da4 | 887 | |
eeb720fb FB |
888 | length = sg_dma_len(s); |
889 | dma = sg_dma_address(s); | |
72246da4 | 890 | |
1d046793 PZ |
891 | if (i == (request->num_mapped_sgs - 1) || |
892 | sg_is_last(s)) { | |
ec512fb8 | 893 | if (list_empty(&dep->request_list)) |
e5ba5ec8 | 894 | last_one = true; |
eeb720fb FB |
895 | chain = false; |
896 | } | |
72246da4 | 897 | |
eeb720fb FB |
898 | trbs_left--; |
899 | if (!trbs_left) | |
900 | last_one = true; | |
72246da4 | 901 | |
eeb720fb FB |
902 | if (last_one) |
903 | chain = false; | |
72246da4 | 904 | |
eeb720fb | 905 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 906 | last_one, chain, i); |
72246da4 | 907 | |
eeb720fb FB |
908 | if (last_one) |
909 | break; | |
910 | } | |
39e60635 AV |
911 | |
912 | if (last_one) | |
913 | break; | |
72246da4 | 914 | } else { |
eeb720fb FB |
915 | dma = req->request.dma; |
916 | length = req->request.length; | |
917 | trbs_left--; | |
72246da4 | 918 | |
eeb720fb FB |
919 | if (!trbs_left) |
920 | last_one = 1; | |
879631aa | 921 | |
eeb720fb FB |
922 | /* Is this the last request? */ |
923 | if (list_is_last(&req->list, &dep->request_list)) | |
924 | last_one = 1; | |
72246da4 | 925 | |
eeb720fb | 926 | dwc3_prepare_one_trb(dep, req, dma, length, |
e5ba5ec8 | 927 | last_one, false, 0); |
72246da4 | 928 | |
eeb720fb FB |
929 | if (last_one) |
930 | break; | |
72246da4 | 931 | } |
72246da4 | 932 | } |
72246da4 FB |
933 | } |
934 | ||
935 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
936 | int start_new) | |
937 | { | |
938 | struct dwc3_gadget_ep_cmd_params params; | |
939 | struct dwc3_request *req; | |
940 | struct dwc3 *dwc = dep->dwc; | |
941 | int ret; | |
942 | u32 cmd; | |
943 | ||
944 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
73815280 | 945 | dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name); |
72246da4 FB |
946 | return -EBUSY; |
947 | } | |
72246da4 FB |
948 | |
949 | /* | |
950 | * If we are getting here after a short-out-packet we don't enqueue any | |
951 | * new requests as we try to set the IOC bit only on the last request. | |
952 | */ | |
953 | if (start_new) { | |
954 | if (list_empty(&dep->req_queued)) | |
955 | dwc3_prepare_trbs(dep, start_new); | |
956 | ||
957 | /* req points to the first request which will be sent */ | |
958 | req = next_request(&dep->req_queued); | |
959 | } else { | |
68e823e2 FB |
960 | dwc3_prepare_trbs(dep, start_new); |
961 | ||
72246da4 | 962 | /* |
1d046793 | 963 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 964 | */ |
68e823e2 | 965 | req = next_request(&dep->req_queued); |
72246da4 FB |
966 | } |
967 | if (!req) { | |
968 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
969 | return 0; | |
970 | } | |
971 | ||
972 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 973 | |
1877d6c9 PA |
974 | if (start_new) { |
975 | params.param0 = upper_32_bits(req->trb_dma); | |
976 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 | 977 | cmd = DWC3_DEPCMD_STARTTRANSFER; |
1877d6c9 | 978 | } else { |
72246da4 | 979 | cmd = DWC3_DEPCMD_UPDATETRANSFER; |
1877d6c9 | 980 | } |
72246da4 FB |
981 | |
982 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
983 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
984 | if (ret < 0) { | |
72246da4 FB |
985 | /* |
986 | * FIXME we need to iterate over the list of requests | |
987 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 988 | * requests instead of what we do now. |
72246da4 | 989 | */ |
0fc9a1be FB |
990 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
991 | req->direction); | |
72246da4 FB |
992 | list_del(&req->list); |
993 | return ret; | |
994 | } | |
995 | ||
996 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 997 | |
f898ae09 | 998 | if (start_new) { |
b4996a86 | 999 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, |
f898ae09 | 1000 | dep->number); |
b4996a86 | 1001 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1002 | } |
25b8ff68 | 1003 | |
72246da4 FB |
1004 | return 0; |
1005 | } | |
1006 | ||
d6d6ec7b PA |
1007 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1008 | struct dwc3_ep *dep, u32 cur_uf) | |
1009 | { | |
1010 | u32 uf; | |
1011 | ||
1012 | if (list_empty(&dep->request_list)) { | |
73815280 FB |
1013 | dwc3_trace(trace_dwc3_gadget, |
1014 | "ISOC ep %s run out for requests", | |
1015 | dep->name); | |
f4a53c55 | 1016 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1017 | return; |
1018 | } | |
1019 | ||
1020 | /* 4 micro frames in the future */ | |
1021 | uf = cur_uf + dep->interval * 4; | |
1022 | ||
1023 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1024 | } | |
1025 | ||
1026 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1027 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1028 | { | |
1029 | u32 cur_uf, mask; | |
1030 | ||
1031 | mask = ~(dep->interval - 1); | |
1032 | cur_uf = event->parameters & mask; | |
1033 | ||
1034 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1035 | } | |
1036 | ||
72246da4 FB |
1037 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1038 | { | |
0fc9a1be FB |
1039 | struct dwc3 *dwc = dep->dwc; |
1040 | int ret; | |
1041 | ||
bb423984 | 1042 | if (!dep->endpoint.desc) { |
ec5e795c FB |
1043 | dwc3_trace(trace_dwc3_gadget, |
1044 | "trying to queue request %p to disabled %s\n", | |
bb423984 FB |
1045 | &req->request, dep->endpoint.name); |
1046 | return -ESHUTDOWN; | |
1047 | } | |
1048 | ||
1049 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1050 | &req->request, req->dep->name)) { | |
ec5e795c FB |
1051 | dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n", |
1052 | &req->request, req->dep->name); | |
bb423984 FB |
1053 | return -EINVAL; |
1054 | } | |
1055 | ||
72246da4 FB |
1056 | req->request.actual = 0; |
1057 | req->request.status = -EINPROGRESS; | |
1058 | req->direction = dep->direction; | |
1059 | req->epnum = dep->number; | |
1060 | ||
fe84f522 FB |
1061 | trace_dwc3_ep_queue(req); |
1062 | ||
72246da4 FB |
1063 | /* |
1064 | * We only add to our list of requests now and | |
1065 | * start consuming the list once we get XferNotReady | |
1066 | * IRQ. | |
1067 | * | |
1068 | * That way, we avoid doing anything that we don't need | |
1069 | * to do now and defer it until the point we receive a | |
1070 | * particular token from the Host side. | |
1071 | * | |
1072 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1073 | * many NAKs. |
72246da4 | 1074 | */ |
0fc9a1be FB |
1075 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1076 | dep->direction); | |
1077 | if (ret) | |
1078 | return ret; | |
1079 | ||
72246da4 FB |
1080 | list_add_tail(&req->list, &dep->request_list); |
1081 | ||
1d6a3918 FB |
1082 | /* |
1083 | * If there are no pending requests and the endpoint isn't already | |
1084 | * busy, we will just start the request straight away. | |
1085 | * | |
1086 | * This will save one IRQ (XFER_NOT_READY) and possibly make it a | |
1087 | * little bit faster. | |
1088 | */ | |
1089 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
62e345ae | 1090 | !usb_endpoint_xfer_int(dep->endpoint.desc) && |
1d6a3918 FB |
1091 | !(dep->flags & DWC3_EP_BUSY)) { |
1092 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); | |
a8f32817 | 1093 | goto out; |
1d6a3918 FB |
1094 | } |
1095 | ||
72246da4 | 1096 | /* |
b511e5e7 | 1097 | * There are a few special cases: |
72246da4 | 1098 | * |
f898ae09 PZ |
1099 | * 1. XferNotReady with empty list of requests. We need to kick the |
1100 | * transfer here in that situation, otherwise we will be NAKing | |
1101 | * forever. If we get XferNotReady before gadget driver has a | |
1102 | * chance to queue a request, we will ACK the IRQ but won't be | |
1103 | * able to receive the data until the next request is queued. | |
1104 | * The following code is handling exactly that. | |
72246da4 | 1105 | * |
72246da4 FB |
1106 | */ |
1107 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f4a53c55 PA |
1108 | /* |
1109 | * If xfernotready is already elapsed and it is a case | |
1110 | * of isoc transfer, then issue END TRANSFER, so that | |
1111 | * you can receive xfernotready again and can have | |
1112 | * notion of current microframe. | |
1113 | */ | |
1114 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
cdc359dd | 1115 | if (list_empty(&dep->req_queued)) { |
b992e681 | 1116 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1117 | dep->flags = DWC3_EP_ENABLED; |
1118 | } | |
f4a53c55 PA |
1119 | return 0; |
1120 | } | |
1121 | ||
b511e5e7 | 1122 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
89185916 FB |
1123 | if (!ret) |
1124 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
1125 | ||
a8f32817 | 1126 | goto out; |
b511e5e7 | 1127 | } |
72246da4 | 1128 | |
b511e5e7 FB |
1129 | /* |
1130 | * 2. XferInProgress on Isoc EP with an active transfer. We need to | |
1131 | * kick the transfer here after queuing a request, otherwise the | |
1132 | * core may not see the modified TRB(s). | |
1133 | */ | |
1134 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && | |
79c9046e PA |
1135 | (dep->flags & DWC3_EP_BUSY) && |
1136 | !(dep->flags & DWC3_EP_MISSED_ISOC)) { | |
b4996a86 FB |
1137 | WARN_ON_ONCE(!dep->resource_index); |
1138 | ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, | |
b511e5e7 | 1139 | false); |
a8f32817 | 1140 | goto out; |
a0925324 | 1141 | } |
72246da4 | 1142 | |
b997ada5 FB |
1143 | /* |
1144 | * 4. Stream Capable Bulk Endpoints. We need to start the transfer | |
1145 | * right away, otherwise host will not know we have streams to be | |
1146 | * handled. | |
1147 | */ | |
a8f32817 | 1148 | if (dep->stream_capable) |
b997ada5 | 1149 | ret = __dwc3_gadget_kick_transfer(dep, 0, true); |
b997ada5 | 1150 | |
a8f32817 FB |
1151 | out: |
1152 | if (ret && ret != -EBUSY) | |
ec5e795c FB |
1153 | dwc3_trace(trace_dwc3_gadget, |
1154 | "%s: failed to kick transfers\n", | |
a8f32817 FB |
1155 | dep->name); |
1156 | if (ret == -EBUSY) | |
1157 | ret = 0; | |
1158 | ||
1159 | return ret; | |
72246da4 FB |
1160 | } |
1161 | ||
1162 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1163 | gfp_t gfp_flags) | |
1164 | { | |
1165 | struct dwc3_request *req = to_dwc3_request(request); | |
1166 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1167 | struct dwc3 *dwc = dep->dwc; | |
1168 | ||
1169 | unsigned long flags; | |
1170 | ||
1171 | int ret; | |
1172 | ||
fdee4eba | 1173 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1174 | ret = __dwc3_gadget_ep_queue(dep, req); |
1175 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1176 | ||
1177 | return ret; | |
1178 | } | |
1179 | ||
1180 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1181 | struct usb_request *request) | |
1182 | { | |
1183 | struct dwc3_request *req = to_dwc3_request(request); | |
1184 | struct dwc3_request *r = NULL; | |
1185 | ||
1186 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1187 | struct dwc3 *dwc = dep->dwc; | |
1188 | ||
1189 | unsigned long flags; | |
1190 | int ret = 0; | |
1191 | ||
2c4cbe6e FB |
1192 | trace_dwc3_ep_dequeue(req); |
1193 | ||
72246da4 FB |
1194 | spin_lock_irqsave(&dwc->lock, flags); |
1195 | ||
1196 | list_for_each_entry(r, &dep->request_list, list) { | |
1197 | if (r == req) | |
1198 | break; | |
1199 | } | |
1200 | ||
1201 | if (r != req) { | |
1202 | list_for_each_entry(r, &dep->req_queued, list) { | |
1203 | if (r == req) | |
1204 | break; | |
1205 | } | |
1206 | if (r == req) { | |
1207 | /* wait until it is processed */ | |
b992e681 | 1208 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1209 | goto out1; |
72246da4 FB |
1210 | } |
1211 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1212 | request, ep->name); | |
1213 | ret = -EINVAL; | |
1214 | goto out0; | |
1215 | } | |
1216 | ||
e8d4e8be | 1217 | out1: |
72246da4 FB |
1218 | /* giveback the request */ |
1219 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1220 | ||
1221 | out0: | |
1222 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1223 | ||
1224 | return ret; | |
1225 | } | |
1226 | ||
7a608559 | 1227 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1228 | { |
1229 | struct dwc3_gadget_ep_cmd_params params; | |
1230 | struct dwc3 *dwc = dep->dwc; | |
1231 | int ret; | |
1232 | ||
5ad02fb8 FB |
1233 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1234 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1235 | return -EINVAL; | |
1236 | } | |
1237 | ||
72246da4 FB |
1238 | memset(¶ms, 0x00, sizeof(params)); |
1239 | ||
1240 | if (value) { | |
7a608559 FB |
1241 | if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) || |
1242 | (!list_empty(&dep->req_queued) || | |
1243 | !list_empty(&dep->request_list)))) { | |
ec5e795c FB |
1244 | dwc3_trace(trace_dwc3_gadget, |
1245 | "%s: pending request, cannot halt\n", | |
7a608559 FB |
1246 | dep->name); |
1247 | return -EAGAIN; | |
1248 | } | |
1249 | ||
72246da4 FB |
1250 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1251 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1252 | if (ret) | |
3f89204b | 1253 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1254 | dep->name); |
1255 | else | |
1256 | dep->flags |= DWC3_EP_STALL; | |
1257 | } else { | |
1258 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1259 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1260 | if (ret) | |
3f89204b | 1261 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1262 | dep->name); |
1263 | else | |
a535d81c | 1264 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1265 | } |
5275455a | 1266 | |
72246da4 FB |
1267 | return ret; |
1268 | } | |
1269 | ||
1270 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1271 | { | |
1272 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1273 | struct dwc3 *dwc = dep->dwc; | |
1274 | ||
1275 | unsigned long flags; | |
1276 | ||
1277 | int ret; | |
1278 | ||
1279 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1280 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1281 | spin_unlock_irqrestore(&dwc->lock, flags); |
1282 | ||
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1287 | { | |
1288 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1289 | struct dwc3 *dwc = dep->dwc; |
1290 | unsigned long flags; | |
95aa4e8d | 1291 | int ret; |
72246da4 | 1292 | |
249a4569 | 1293 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1294 | dep->flags |= DWC3_EP_WEDGE; |
1295 | ||
08f0d966 | 1296 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1297 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1298 | else |
7a608559 | 1299 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1300 | spin_unlock_irqrestore(&dwc->lock, flags); |
1301 | ||
1302 | return ret; | |
72246da4 FB |
1303 | } |
1304 | ||
1305 | /* -------------------------------------------------------------------------- */ | |
1306 | ||
1307 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1308 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1309 | .bDescriptorType = USB_DT_ENDPOINT, | |
1310 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1311 | }; | |
1312 | ||
1313 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1314 | .enable = dwc3_gadget_ep0_enable, | |
1315 | .disable = dwc3_gadget_ep0_disable, | |
1316 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1317 | .free_request = dwc3_gadget_ep_free_request, | |
1318 | .queue = dwc3_gadget_ep0_queue, | |
1319 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1320 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1321 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1322 | }; | |
1323 | ||
1324 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1325 | .enable = dwc3_gadget_ep_enable, | |
1326 | .disable = dwc3_gadget_ep_disable, | |
1327 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1328 | .free_request = dwc3_gadget_ep_free_request, | |
1329 | .queue = dwc3_gadget_ep_queue, | |
1330 | .dequeue = dwc3_gadget_ep_dequeue, | |
1331 | .set_halt = dwc3_gadget_ep_set_halt, | |
1332 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1333 | }; | |
1334 | ||
1335 | /* -------------------------------------------------------------------------- */ | |
1336 | ||
1337 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1338 | { | |
1339 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1340 | u32 reg; | |
1341 | ||
1342 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1343 | return DWC3_DSTS_SOFFN(reg); | |
1344 | } | |
1345 | ||
1346 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1347 | { | |
1348 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1349 | ||
1350 | unsigned long timeout; | |
1351 | unsigned long flags; | |
1352 | ||
1353 | u32 reg; | |
1354 | ||
1355 | int ret = 0; | |
1356 | ||
1357 | u8 link_state; | |
1358 | u8 speed; | |
1359 | ||
1360 | spin_lock_irqsave(&dwc->lock, flags); | |
1361 | ||
1362 | /* | |
1363 | * According to the Databook Remote wakeup request should | |
1364 | * be issued only when the device is in early suspend state. | |
1365 | * | |
1366 | * We can check that via USB Link State bits in DSTS register. | |
1367 | */ | |
1368 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1369 | ||
1370 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1371 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
ec5e795c | 1372 | dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n"); |
72246da4 FB |
1373 | ret = -EINVAL; |
1374 | goto out; | |
1375 | } | |
1376 | ||
1377 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1378 | ||
1379 | switch (link_state) { | |
1380 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1381 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1382 | break; | |
1383 | default: | |
ec5e795c FB |
1384 | dwc3_trace(trace_dwc3_gadget, |
1385 | "can't wakeup from '%s'\n", | |
1386 | dwc3_gadget_link_string(link_state)); | |
72246da4 FB |
1387 | ret = -EINVAL; |
1388 | goto out; | |
1389 | } | |
1390 | ||
8598bde7 FB |
1391 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1392 | if (ret < 0) { | |
1393 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1394 | goto out; | |
1395 | } | |
72246da4 | 1396 | |
802fde98 PZ |
1397 | /* Recent versions do this automatically */ |
1398 | if (dwc->revision < DWC3_REVISION_194A) { | |
1399 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1400 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1401 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1402 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1403 | } | |
72246da4 | 1404 | |
1d046793 | 1405 | /* poll until Link State changes to ON */ |
72246da4 FB |
1406 | timeout = jiffies + msecs_to_jiffies(100); |
1407 | ||
1d046793 | 1408 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1409 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1410 | ||
1411 | /* in HS, means ON */ | |
1412 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1413 | break; | |
1414 | } | |
1415 | ||
1416 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1417 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1418 | ret = -EINVAL; | |
1419 | } | |
1420 | ||
1421 | out: | |
1422 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1423 | ||
1424 | return ret; | |
1425 | } | |
1426 | ||
1427 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1428 | int is_selfpowered) | |
1429 | { | |
1430 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1431 | unsigned long flags; |
72246da4 | 1432 | |
249a4569 | 1433 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1434 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1435 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1436 | |
1437 | return 0; | |
1438 | } | |
1439 | ||
7b2a0368 | 1440 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1441 | { |
1442 | u32 reg; | |
61d58242 | 1443 | u32 timeout = 500; |
72246da4 FB |
1444 | |
1445 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1446 | if (is_on) { |
802fde98 PZ |
1447 | if (dwc->revision <= DWC3_REVISION_187A) { |
1448 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1449 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1450 | } | |
1451 | ||
1452 | if (dwc->revision >= DWC3_REVISION_194A) | |
1453 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1454 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1455 | |
1456 | if (dwc->has_hibernation) | |
1457 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1458 | ||
9fcb3bd8 | 1459 | dwc->pullups_connected = true; |
8db7ed15 | 1460 | } else { |
72246da4 | 1461 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1462 | |
1463 | if (dwc->has_hibernation && !suspend) | |
1464 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1465 | ||
9fcb3bd8 | 1466 | dwc->pullups_connected = false; |
8db7ed15 | 1467 | } |
72246da4 FB |
1468 | |
1469 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1470 | ||
1471 | do { | |
1472 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1473 | if (is_on) { | |
1474 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1475 | break; | |
1476 | } else { | |
1477 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1478 | break; | |
1479 | } | |
72246da4 FB |
1480 | timeout--; |
1481 | if (!timeout) | |
6f17f74b | 1482 | return -ETIMEDOUT; |
61d58242 | 1483 | udelay(1); |
72246da4 FB |
1484 | } while (1); |
1485 | ||
73815280 | 1486 | dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s", |
72246da4 FB |
1487 | dwc->gadget_driver |
1488 | ? dwc->gadget_driver->function : "no-function", | |
1489 | is_on ? "connect" : "disconnect"); | |
6f17f74b PA |
1490 | |
1491 | return 0; | |
72246da4 FB |
1492 | } |
1493 | ||
1494 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1495 | { | |
1496 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1497 | unsigned long flags; | |
6f17f74b | 1498 | int ret; |
72246da4 FB |
1499 | |
1500 | is_on = !!is_on; | |
1501 | ||
1502 | spin_lock_irqsave(&dwc->lock, flags); | |
7b2a0368 | 1503 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1504 | spin_unlock_irqrestore(&dwc->lock, flags); |
1505 | ||
6f17f74b | 1506 | return ret; |
72246da4 FB |
1507 | } |
1508 | ||
8698e2ac FB |
1509 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1510 | { | |
1511 | u32 reg; | |
1512 | ||
1513 | /* Enable all but Start and End of Frame IRQs */ | |
1514 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1515 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1516 | DWC3_DEVTEN_CMDCMPLTEN | | |
1517 | DWC3_DEVTEN_ERRTICERREN | | |
1518 | DWC3_DEVTEN_WKUPEVTEN | | |
1519 | DWC3_DEVTEN_ULSTCNGEN | | |
1520 | DWC3_DEVTEN_CONNECTDONEEN | | |
1521 | DWC3_DEVTEN_USBRSTEN | | |
1522 | DWC3_DEVTEN_DISCONNEVTEN); | |
1523 | ||
1524 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
1525 | } | |
1526 | ||
1527 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1528 | { | |
1529 | /* mask all interrupts */ | |
1530 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1531 | } | |
1532 | ||
1533 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1534 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1535 | |
72246da4 FB |
1536 | static int dwc3_gadget_start(struct usb_gadget *g, |
1537 | struct usb_gadget_driver *driver) | |
1538 | { | |
1539 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1540 | struct dwc3_ep *dep; | |
1541 | unsigned long flags; | |
1542 | int ret = 0; | |
8698e2ac | 1543 | int irq; |
72246da4 FB |
1544 | u32 reg; |
1545 | ||
b0d7ffd4 FB |
1546 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1547 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, | |
e8adfc30 | 1548 | IRQF_SHARED, "dwc3", dwc); |
b0d7ffd4 FB |
1549 | if (ret) { |
1550 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1551 | irq, ret); | |
1552 | goto err0; | |
1553 | } | |
1554 | ||
72246da4 FB |
1555 | spin_lock_irqsave(&dwc->lock, flags); |
1556 | ||
1557 | if (dwc->gadget_driver) { | |
1558 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1559 | dwc->gadget.name, | |
1560 | dwc->gadget_driver->driver.name); | |
1561 | ret = -EBUSY; | |
b0d7ffd4 | 1562 | goto err1; |
72246da4 FB |
1563 | } |
1564 | ||
1565 | dwc->gadget_driver = driver; | |
72246da4 | 1566 | |
72246da4 FB |
1567 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1568 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1569 | |
1570 | /** | |
1571 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1572 | * which would cause metastability state on Run/Stop | |
1573 | * bit if we try to force the IP to USB2-only mode. | |
1574 | * | |
1575 | * Because of that, we cannot configure the IP to any | |
1576 | * speed other than the SuperSpeed | |
1577 | * | |
1578 | * Refers to: | |
1579 | * | |
1580 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1581 | * USB 2.0 Mode | |
1582 | */ | |
f7e846f0 | 1583 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1584 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1585 | } else { |
1586 | switch (dwc->maximum_speed) { | |
1587 | case USB_SPEED_LOW: | |
1588 | reg |= DWC3_DSTS_LOWSPEED; | |
1589 | break; | |
1590 | case USB_SPEED_FULL: | |
1591 | reg |= DWC3_DSTS_FULLSPEED1; | |
1592 | break; | |
1593 | case USB_SPEED_HIGH: | |
1594 | reg |= DWC3_DSTS_HIGHSPEED; | |
1595 | break; | |
1596 | case USB_SPEED_SUPER: /* FALLTHROUGH */ | |
1597 | case USB_SPEED_UNKNOWN: /* FALTHROUGH */ | |
1598 | default: | |
1599 | reg |= DWC3_DSTS_SUPERSPEED; | |
1600 | } | |
1601 | } | |
72246da4 FB |
1602 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1603 | ||
b23c8439 PZ |
1604 | dwc->start_config_issued = false; |
1605 | ||
72246da4 FB |
1606 | /* Start with SuperSpeed Default */ |
1607 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1608 | ||
1609 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1610 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1611 | false); | |
72246da4 FB |
1612 | if (ret) { |
1613 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1614 | goto err2; |
72246da4 FB |
1615 | } |
1616 | ||
1617 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1618 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1619 | false); | |
72246da4 FB |
1620 | if (ret) { |
1621 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
b0d7ffd4 | 1622 | goto err3; |
72246da4 FB |
1623 | } |
1624 | ||
1625 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1626 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1627 | dwc3_ep0_out_start(dwc); |
1628 | ||
8698e2ac FB |
1629 | dwc3_gadget_enable_irq(dwc); |
1630 | ||
72246da4 FB |
1631 | spin_unlock_irqrestore(&dwc->lock, flags); |
1632 | ||
1633 | return 0; | |
1634 | ||
b0d7ffd4 | 1635 | err3: |
72246da4 FB |
1636 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1637 | ||
b0d7ffd4 | 1638 | err2: |
cdcedd69 | 1639 | dwc->gadget_driver = NULL; |
b0d7ffd4 FB |
1640 | |
1641 | err1: | |
72246da4 FB |
1642 | spin_unlock_irqrestore(&dwc->lock, flags); |
1643 | ||
b0d7ffd4 FB |
1644 | free_irq(irq, dwc); |
1645 | ||
1646 | err0: | |
72246da4 FB |
1647 | return ret; |
1648 | } | |
1649 | ||
22835b80 | 1650 | static int dwc3_gadget_stop(struct usb_gadget *g) |
72246da4 FB |
1651 | { |
1652 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1653 | unsigned long flags; | |
8698e2ac | 1654 | int irq; |
72246da4 FB |
1655 | |
1656 | spin_lock_irqsave(&dwc->lock, flags); | |
1657 | ||
8698e2ac | 1658 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1659 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1660 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1661 | ||
1662 | dwc->gadget_driver = NULL; | |
72246da4 FB |
1663 | |
1664 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1665 | ||
b0d7ffd4 FB |
1666 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); |
1667 | free_irq(irq, dwc); | |
1668 | ||
72246da4 FB |
1669 | return 0; |
1670 | } | |
802fde98 | 1671 | |
72246da4 FB |
1672 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1673 | .get_frame = dwc3_gadget_get_frame, | |
1674 | .wakeup = dwc3_gadget_wakeup, | |
1675 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1676 | .pullup = dwc3_gadget_pullup, | |
1677 | .udc_start = dwc3_gadget_start, | |
1678 | .udc_stop = dwc3_gadget_stop, | |
1679 | }; | |
1680 | ||
1681 | /* -------------------------------------------------------------------------- */ | |
1682 | ||
6a1e3ef4 FB |
1683 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1684 | u8 num, u32 direction) | |
72246da4 FB |
1685 | { |
1686 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1687 | u8 i; |
72246da4 | 1688 | |
6a1e3ef4 FB |
1689 | for (i = 0; i < num; i++) { |
1690 | u8 epnum = (i << 1) | (!!direction); | |
72246da4 | 1691 | |
72246da4 | 1692 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1693 | if (!dep) |
72246da4 | 1694 | return -ENOMEM; |
72246da4 FB |
1695 | |
1696 | dep->dwc = dwc; | |
1697 | dep->number = epnum; | |
9aa62ae4 | 1698 | dep->direction = !!direction; |
72246da4 FB |
1699 | dwc->eps[epnum] = dep; |
1700 | ||
1701 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1702 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1703 | |
72246da4 | 1704 | dep->endpoint.name = dep->name; |
72246da4 | 1705 | |
73815280 | 1706 | dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name); |
653df35e | 1707 | |
72246da4 | 1708 | if (epnum == 0 || epnum == 1) { |
e117e742 | 1709 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1710 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1711 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1712 | if (!epnum) | |
1713 | dwc->gadget.ep0 = &dep->endpoint; | |
1714 | } else { | |
1715 | int ret; | |
1716 | ||
e117e742 | 1717 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1718 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1719 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1720 | list_add_tail(&dep->endpoint.ep_list, | |
1721 | &dwc->gadget.ep_list); | |
1722 | ||
1723 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1724 | if (ret) |
72246da4 | 1725 | return ret; |
72246da4 | 1726 | } |
25b8ff68 | 1727 | |
a474d3b7 RB |
1728 | if (epnum == 0 || epnum == 1) { |
1729 | dep->endpoint.caps.type_control = true; | |
1730 | } else { | |
1731 | dep->endpoint.caps.type_iso = true; | |
1732 | dep->endpoint.caps.type_bulk = true; | |
1733 | dep->endpoint.caps.type_int = true; | |
1734 | } | |
1735 | ||
1736 | dep->endpoint.caps.dir_in = !!direction; | |
1737 | dep->endpoint.caps.dir_out = !direction; | |
1738 | ||
72246da4 FB |
1739 | INIT_LIST_HEAD(&dep->request_list); |
1740 | INIT_LIST_HEAD(&dep->req_queued); | |
1741 | } | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
6a1e3ef4 FB |
1746 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1747 | { | |
1748 | int ret; | |
1749 | ||
1750 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1751 | ||
1752 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1753 | if (ret < 0) { | |
73815280 FB |
1754 | dwc3_trace(trace_dwc3_gadget, |
1755 | "failed to allocate OUT endpoints"); | |
6a1e3ef4 FB |
1756 | return ret; |
1757 | } | |
1758 | ||
1759 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1760 | if (ret < 0) { | |
73815280 FB |
1761 | dwc3_trace(trace_dwc3_gadget, |
1762 | "failed to allocate IN endpoints"); | |
6a1e3ef4 FB |
1763 | return ret; |
1764 | } | |
1765 | ||
1766 | return 0; | |
1767 | } | |
1768 | ||
72246da4 FB |
1769 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1770 | { | |
1771 | struct dwc3_ep *dep; | |
1772 | u8 epnum; | |
1773 | ||
1774 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1775 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1776 | if (!dep) |
1777 | continue; | |
5bf8fae3 GC |
1778 | /* |
1779 | * Physical endpoints 0 and 1 are special; they form the | |
1780 | * bi-directional USB endpoint 0. | |
1781 | * | |
1782 | * For those two physical endpoints, we don't allocate a TRB | |
1783 | * pool nor do we add them the endpoints list. Due to that, we | |
1784 | * shouldn't do these two operations otherwise we would end up | |
1785 | * with all sorts of bugs when removing dwc3.ko. | |
1786 | */ | |
1787 | if (epnum != 0 && epnum != 1) { | |
1788 | dwc3_free_trb_pool(dep); | |
72246da4 | 1789 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1790 | } |
72246da4 FB |
1791 | |
1792 | kfree(dep); | |
1793 | } | |
1794 | } | |
1795 | ||
72246da4 | 1796 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1797 | |
e5ba5ec8 PA |
1798 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1799 | struct dwc3_request *req, struct dwc3_trb *trb, | |
72246da4 FB |
1800 | const struct dwc3_event_depevt *event, int status) |
1801 | { | |
72246da4 FB |
1802 | unsigned int count; |
1803 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1804 | unsigned int trb_status; |
72246da4 | 1805 | |
2c4cbe6e FB |
1806 | trace_dwc3_complete_trb(dep, trb); |
1807 | ||
e5ba5ec8 PA |
1808 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
1809 | /* | |
1810 | * We continue despite the error. There is not much we | |
1811 | * can do. If we don't clean it up we loop forever. If | |
1812 | * we skip the TRB then it gets overwritten after a | |
1813 | * while since we use them in a ring buffer. A BUG() | |
1814 | * would help. Lets hope that if this occurs, someone | |
1815 | * fixes the root cause instead of looking away :) | |
1816 | */ | |
1817 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", | |
1818 | dep->name, trb); | |
1819 | count = trb->size & DWC3_TRB_SIZE_MASK; | |
1820 | ||
1821 | if (dep->direction) { | |
1822 | if (count) { | |
1823 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
1824 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
ec5e795c FB |
1825 | dwc3_trace(trace_dwc3_gadget, |
1826 | "%s: incomplete IN transfer\n", | |
e5ba5ec8 PA |
1827 | dep->name); |
1828 | /* | |
1829 | * If missed isoc occurred and there is | |
1830 | * no request queued then issue END | |
1831 | * TRANSFER, so that core generates | |
1832 | * next xfernotready and we will issue | |
1833 | * a fresh START TRANSFER. | |
1834 | * If there are still queued request | |
1835 | * then wait, do not issue either END | |
1836 | * or UPDATE TRANSFER, just attach next | |
1837 | * request in request_list during | |
1838 | * giveback.If any future queued request | |
1839 | * is successfully transferred then we | |
1840 | * will issue UPDATE TRANSFER for all | |
1841 | * request in the request_list. | |
1842 | */ | |
1843 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
1844 | } else { | |
1845 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1846 | dep->name); | |
1847 | status = -ECONNRESET; | |
1848 | } | |
1849 | } else { | |
1850 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
1851 | } | |
1852 | } else { | |
1853 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1854 | s_pkt = 1; | |
1855 | } | |
1856 | ||
1857 | /* | |
1858 | * We assume here we will always receive the entire data block | |
1859 | * which we should receive. Meaning, if we program RX to | |
1860 | * receive 4K but we receive only 2K, we assume that's all we | |
1861 | * should receive and we simply bounce the request back to the | |
1862 | * gadget driver for further processing. | |
1863 | */ | |
1864 | req->request.actual += req->request.length - count; | |
1865 | if (s_pkt) | |
1866 | return 1; | |
1867 | if ((event->status & DEPEVT_STATUS_LST) && | |
1868 | (trb->ctrl & (DWC3_TRB_CTRL_LST | | |
1869 | DWC3_TRB_CTRL_HWO))) | |
1870 | return 1; | |
1871 | if ((event->status & DEPEVT_STATUS_IOC) && | |
1872 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
1873 | return 1; | |
1874 | return 0; | |
1875 | } | |
1876 | ||
1877 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1878 | const struct dwc3_event_depevt *event, int status) | |
1879 | { | |
1880 | struct dwc3_request *req; | |
1881 | struct dwc3_trb *trb; | |
1882 | unsigned int slot; | |
1883 | unsigned int i; | |
1884 | int ret; | |
1885 | ||
72246da4 | 1886 | do { |
d115d705 | 1887 | req = next_request(&dep->req_queued); |
ac7bdcc1 | 1888 | if (WARN_ON_ONCE(!req)) |
d115d705 | 1889 | return 1; |
ac7bdcc1 | 1890 | |
d115d705 VS |
1891 | i = 0; |
1892 | do { | |
1893 | slot = req->start_slot + i; | |
1894 | if ((slot == DWC3_TRB_NUM - 1) && | |
e5ba5ec8 | 1895 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
d115d705 VS |
1896 | slot++; |
1897 | slot %= DWC3_TRB_NUM; | |
1898 | trb = &dep->trb_pool[slot]; | |
1899 | ||
1900 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
1901 | event, status); | |
1902 | if (ret) | |
1903 | break; | |
1904 | } while (++i < req->request.num_mapped_sgs); | |
1905 | ||
1906 | dwc3_gadget_giveback(dep, req, status); | |
e5ba5ec8 PA |
1907 | |
1908 | if (ret) | |
72246da4 | 1909 | break; |
d115d705 | 1910 | } while (1); |
72246da4 | 1911 | |
cdc359dd PA |
1912 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
1913 | list_empty(&dep->req_queued)) { | |
1914 | if (list_empty(&dep->request_list)) { | |
1915 | /* | |
1916 | * If there is no entry in request list then do | |
1917 | * not issue END TRANSFER now. Just set PENDING | |
1918 | * flag, so that END TRANSFER is issued when an | |
1919 | * entry is added into request list. | |
1920 | */ | |
1921 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
1922 | } else { | |
b992e681 | 1923 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
1924 | dep->flags = DWC3_EP_ENABLED; |
1925 | } | |
7efea86c PA |
1926 | return 1; |
1927 | } | |
1928 | ||
72246da4 FB |
1929 | return 1; |
1930 | } | |
1931 | ||
1932 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 1933 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
1934 | { |
1935 | unsigned status = 0; | |
1936 | int clean_busy; | |
e18b7975 FB |
1937 | u32 is_xfer_complete; |
1938 | ||
1939 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
1940 | |
1941 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1942 | status = -ECONNRESET; | |
1943 | ||
1d046793 | 1944 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
e18b7975 FB |
1945 | if (clean_busy && (is_xfer_complete || |
1946 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) | |
72246da4 | 1947 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1948 | |
1949 | /* | |
1950 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1951 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1952 | */ | |
1953 | if (dwc->revision < DWC3_REVISION_183A) { | |
1954 | u32 reg; | |
1955 | int i; | |
1956 | ||
1957 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 1958 | dep = dwc->eps[i]; |
fae2b904 FB |
1959 | |
1960 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1961 | continue; | |
1962 | ||
1963 | if (!list_empty(&dep->req_queued)) | |
1964 | return; | |
1965 | } | |
1966 | ||
1967 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1968 | reg |= dwc->u1u2; | |
1969 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1970 | ||
1971 | dwc->u1u2 = 0; | |
1972 | } | |
8a1a9c9e | 1973 | |
e6e709b7 | 1974 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
1975 | int ret; |
1976 | ||
e6e709b7 | 1977 | ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete); |
8a1a9c9e FB |
1978 | if (!ret || ret == -EBUSY) |
1979 | return; | |
1980 | } | |
72246da4 FB |
1981 | } |
1982 | ||
72246da4 FB |
1983 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
1984 | const struct dwc3_event_depevt *event) | |
1985 | { | |
1986 | struct dwc3_ep *dep; | |
1987 | u8 epnum = event->endpoint_number; | |
1988 | ||
1989 | dep = dwc->eps[epnum]; | |
1990 | ||
3336abb5 FB |
1991 | if (!(dep->flags & DWC3_EP_ENABLED)) |
1992 | return; | |
1993 | ||
72246da4 FB |
1994 | if (epnum == 0 || epnum == 1) { |
1995 | dwc3_ep0_interrupt(dwc, event); | |
1996 | return; | |
1997 | } | |
1998 | ||
1999 | switch (event->endpoint_event) { | |
2000 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2001 | dep->resource_index = 0; |
c2df85ca | 2002 | |
16e78db7 | 2003 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
ec5e795c FB |
2004 | dwc3_trace(trace_dwc3_gadget, |
2005 | "%s is an Isochronous endpoint\n", | |
72246da4 FB |
2006 | dep->name); |
2007 | return; | |
2008 | } | |
2009 | ||
029d97ff | 2010 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2011 | break; |
2012 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2013 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2014 | break; |
2015 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2016 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2017 | dwc3_gadget_start_isoc(dwc, dep, event); |
2018 | } else { | |
6bb4fe12 | 2019 | int active; |
72246da4 FB |
2020 | int ret; |
2021 | ||
6bb4fe12 FB |
2022 | active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE; |
2023 | ||
73815280 | 2024 | dwc3_trace(trace_dwc3_gadget, "%s: reason %s", |
6bb4fe12 | 2025 | dep->name, active ? "Transfer Active" |
72246da4 FB |
2026 | : "Transfer Not Active"); |
2027 | ||
6bb4fe12 | 2028 | ret = __dwc3_gadget_kick_transfer(dep, 0, !active); |
72246da4 FB |
2029 | if (!ret || ret == -EBUSY) |
2030 | return; | |
2031 | ||
ec5e795c FB |
2032 | dwc3_trace(trace_dwc3_gadget, |
2033 | "%s: failed to kick transfers\n", | |
72246da4 FB |
2034 | dep->name); |
2035 | } | |
2036 | ||
879631aa FB |
2037 | break; |
2038 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2039 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2040 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2041 | dep->name); | |
2042 | return; | |
2043 | } | |
2044 | ||
2045 | switch (event->status) { | |
2046 | case DEPEVT_STREAMEVT_FOUND: | |
73815280 FB |
2047 | dwc3_trace(trace_dwc3_gadget, |
2048 | "Stream %d found and started", | |
879631aa FB |
2049 | event->parameters); |
2050 | ||
2051 | break; | |
2052 | case DEPEVT_STREAMEVT_NOTFOUND: | |
2053 | /* FALLTHROUGH */ | |
2054 | default: | |
ec5e795c FB |
2055 | dwc3_trace(trace_dwc3_gadget, |
2056 | "unable to find suitable stream\n"); | |
879631aa | 2057 | } |
72246da4 FB |
2058 | break; |
2059 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
ec5e795c | 2060 | dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name); |
72246da4 | 2061 | break; |
72246da4 | 2062 | case DWC3_DEPEVT_EPCMDCMPLT: |
73815280 | 2063 | dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete"); |
72246da4 FB |
2064 | break; |
2065 | } | |
2066 | } | |
2067 | ||
2068 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2069 | { | |
2070 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2071 | spin_unlock(&dwc->lock); | |
2072 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2073 | spin_lock(&dwc->lock); | |
2074 | } | |
2075 | } | |
2076 | ||
bc5ba2e0 FB |
2077 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2078 | { | |
73a30bfc | 2079 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2080 | spin_unlock(&dwc->lock); |
2081 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2082 | spin_lock(&dwc->lock); | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2087 | { | |
73a30bfc | 2088 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2089 | spin_unlock(&dwc->lock); |
2090 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2091 | spin_lock(&dwc->lock); |
8e74475b FB |
2092 | } |
2093 | } | |
2094 | ||
2095 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2096 | { | |
2097 | if (!dwc->gadget_driver) | |
2098 | return; | |
2099 | ||
2100 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2101 | spin_unlock(&dwc->lock); | |
2102 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2103 | spin_lock(&dwc->lock); |
2104 | } | |
2105 | } | |
2106 | ||
b992e681 | 2107 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2108 | { |
2109 | struct dwc3_ep *dep; | |
2110 | struct dwc3_gadget_ep_cmd_params params; | |
2111 | u32 cmd; | |
2112 | int ret; | |
2113 | ||
2114 | dep = dwc->eps[epnum]; | |
2115 | ||
b4996a86 | 2116 | if (!dep->resource_index) |
3daf74d7 PA |
2117 | return; |
2118 | ||
57911504 PA |
2119 | /* |
2120 | * NOTICE: We are violating what the Databook says about the | |
2121 | * EndTransfer command. Ideally we would _always_ wait for the | |
2122 | * EndTransfer Command Completion IRQ, but that's causing too | |
2123 | * much trouble synchronizing between us and gadget driver. | |
2124 | * | |
2125 | * We have discussed this with the IP Provider and it was | |
2126 | * suggested to giveback all requests here, but give HW some | |
2127 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2128 | * an arbitrary 100us delay for that. |
57911504 PA |
2129 | * |
2130 | * Note also that a similar handling was tested by Synopsys | |
2131 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2132 | * In short, what we're doing is: | |
2133 | * | |
2134 | * - Issue EndTransfer WITH CMDIOC bit set | |
2135 | * - Wait 100us | |
2136 | */ | |
2137 | ||
3daf74d7 | 2138 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2139 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2140 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2141 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 PA |
2142 | memset(¶ms, 0, sizeof(params)); |
2143 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
2144 | WARN_ON_ONCE(ret); | |
b4996a86 | 2145 | dep->resource_index = 0; |
041d81f4 | 2146 | dep->flags &= ~DWC3_EP_BUSY; |
57911504 | 2147 | udelay(100); |
72246da4 FB |
2148 | } |
2149 | ||
2150 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
2151 | { | |
2152 | u32 epnum; | |
2153 | ||
2154 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2155 | struct dwc3_ep *dep; | |
2156 | ||
2157 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2158 | if (!dep) |
2159 | continue; | |
2160 | ||
72246da4 FB |
2161 | if (!(dep->flags & DWC3_EP_ENABLED)) |
2162 | continue; | |
2163 | ||
624407f9 | 2164 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
2165 | } |
2166 | } | |
2167 | ||
2168 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
2169 | { | |
2170 | u32 epnum; | |
2171 | ||
2172 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2173 | struct dwc3_ep *dep; | |
2174 | struct dwc3_gadget_ep_cmd_params params; | |
2175 | int ret; | |
2176 | ||
2177 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2178 | if (!dep) |
2179 | continue; | |
72246da4 FB |
2180 | |
2181 | if (!(dep->flags & DWC3_EP_STALL)) | |
2182 | continue; | |
2183 | ||
2184 | dep->flags &= ~DWC3_EP_STALL; | |
2185 | ||
2186 | memset(¶ms, 0, sizeof(params)); | |
2187 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
2188 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
2189 | WARN_ON_ONCE(ret); | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2194 | { | |
c4430a26 FB |
2195 | int reg; |
2196 | ||
72246da4 FB |
2197 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2198 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2199 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2200 | ||
2201 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2202 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2203 | |
72246da4 | 2204 | dwc3_disconnect_gadget(dwc); |
b23c8439 | 2205 | dwc->start_config_issued = false; |
72246da4 FB |
2206 | |
2207 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2208 | dwc->setup_packet_pending = false; |
06a374ed | 2209 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
72246da4 FB |
2210 | } |
2211 | ||
72246da4 FB |
2212 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2213 | { | |
2214 | u32 reg; | |
2215 | ||
df62df56 FB |
2216 | /* |
2217 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2218 | * would cause a missing Disconnect Event if there's a | |
2219 | * pending Setup Packet in the FIFO. | |
2220 | * | |
2221 | * There's no suggested workaround on the official Bug | |
2222 | * report, which states that "unless the driver/application | |
2223 | * is doing any special handling of a disconnect event, | |
2224 | * there is no functional issue". | |
2225 | * | |
2226 | * Unfortunately, it turns out that we _do_ some special | |
2227 | * handling of a disconnect event, namely complete all | |
2228 | * pending transfers, notify gadget driver of the | |
2229 | * disconnection, and so on. | |
2230 | * | |
2231 | * Our suggested workaround is to follow the Disconnect | |
2232 | * Event steps here, instead, based on a setup_packet_pending | |
2233 | * flag. Such flag gets set whenever we have a XferNotReady | |
2234 | * event on EP0 and gets cleared on XferComplete for the | |
2235 | * same endpoint. | |
2236 | * | |
2237 | * Refers to: | |
2238 | * | |
2239 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2240 | * generated if setup packet pending in FIFO | |
2241 | */ | |
2242 | if (dwc->revision < DWC3_REVISION_188A) { | |
2243 | if (dwc->setup_packet_pending) | |
2244 | dwc3_gadget_disconnect_interrupt(dwc); | |
2245 | } | |
2246 | ||
8e74475b | 2247 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2248 | |
2249 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2250 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2251 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2252 | dwc->test_mode = false; |
72246da4 FB |
2253 | |
2254 | dwc3_stop_active_transfers(dwc); | |
2255 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2256 | dwc->start_config_issued = false; |
72246da4 FB |
2257 | |
2258 | /* Reset device address to zero */ | |
2259 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2260 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2261 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2262 | } |
2263 | ||
2264 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2265 | { | |
2266 | u32 reg; | |
2267 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2268 | ||
2269 | /* | |
2270 | * We change the clock only at SS but I dunno why I would want to do | |
2271 | * this. Maybe it becomes part of the power saving plan. | |
2272 | */ | |
2273 | ||
2274 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2275 | return; | |
2276 | ||
2277 | /* | |
2278 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2279 | * each time on Connect Done. | |
2280 | */ | |
2281 | if (!usb30_clock) | |
2282 | return; | |
2283 | ||
2284 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2285 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2286 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2287 | } | |
2288 | ||
72246da4 FB |
2289 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2290 | { | |
72246da4 FB |
2291 | struct dwc3_ep *dep; |
2292 | int ret; | |
2293 | u32 reg; | |
2294 | u8 speed; | |
2295 | ||
72246da4 FB |
2296 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2297 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2298 | dwc->speed = speed; | |
2299 | ||
2300 | dwc3_update_ram_clk_sel(dwc, speed); | |
2301 | ||
2302 | switch (speed) { | |
2303 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2304 | /* |
2305 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2306 | * would cause a missing USB3 Reset event. | |
2307 | * | |
2308 | * In such situations, we should force a USB3 Reset | |
2309 | * event by calling our dwc3_gadget_reset_interrupt() | |
2310 | * routine. | |
2311 | * | |
2312 | * Refers to: | |
2313 | * | |
2314 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2315 | * not be generated always when the link enters poll | |
2316 | */ | |
2317 | if (dwc->revision < DWC3_REVISION_190A) | |
2318 | dwc3_gadget_reset_interrupt(dwc); | |
2319 | ||
72246da4 FB |
2320 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2321 | dwc->gadget.ep0->maxpacket = 512; | |
2322 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2323 | break; | |
2324 | case DWC3_DCFG_HIGHSPEED: | |
2325 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2326 | dwc->gadget.ep0->maxpacket = 64; | |
2327 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2328 | break; | |
2329 | case DWC3_DCFG_FULLSPEED2: | |
2330 | case DWC3_DCFG_FULLSPEED1: | |
2331 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2332 | dwc->gadget.ep0->maxpacket = 64; | |
2333 | dwc->gadget.speed = USB_SPEED_FULL; | |
2334 | break; | |
2335 | case DWC3_DCFG_LOWSPEED: | |
2336 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2337 | dwc->gadget.ep0->maxpacket = 8; | |
2338 | dwc->gadget.speed = USB_SPEED_LOW; | |
2339 | break; | |
2340 | } | |
2341 | ||
2b758350 PA |
2342 | /* Enable USB2 LPM Capability */ |
2343 | ||
2344 | if ((dwc->revision > DWC3_REVISION_194A) | |
2345 | && (speed != DWC3_DCFG_SUPERSPEED)) { | |
2346 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2347 | reg |= DWC3_DCFG_LPM_CAP; | |
2348 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2349 | ||
2350 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2351 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2352 | ||
460d098c | 2353 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2354 | |
80caf7d2 HR |
2355 | /* |
2356 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2357 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2358 | * BESL value in the LPM token is less than or equal to LPM | |
2359 | * NYET threshold. | |
2360 | */ | |
2361 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2362 | && dwc->has_lpm_erratum, | |
2363 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2364 | ||
2365 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2366 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2367 | ||
356363bf FB |
2368 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2369 | } else { | |
2370 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2371 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2372 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2373 | } | |
2374 | ||
72246da4 | 2375 | dep = dwc->eps[0]; |
265b70a7 PZ |
2376 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2377 | false); | |
72246da4 FB |
2378 | if (ret) { |
2379 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2380 | return; | |
2381 | } | |
2382 | ||
2383 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2384 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2385 | false); | |
72246da4 FB |
2386 | if (ret) { |
2387 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2388 | return; | |
2389 | } | |
2390 | ||
2391 | /* | |
2392 | * Configure PHY via GUSB3PIPECTLn if required. | |
2393 | * | |
2394 | * Update GTXFIFOSIZn | |
2395 | * | |
2396 | * In both cases reset values should be sufficient. | |
2397 | */ | |
2398 | } | |
2399 | ||
2400 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2401 | { | |
72246da4 FB |
2402 | /* |
2403 | * TODO take core out of low power mode when that's | |
2404 | * implemented. | |
2405 | */ | |
2406 | ||
2407 | dwc->gadget_driver->resume(&dwc->gadget); | |
2408 | } | |
2409 | ||
2410 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2411 | unsigned int evtinfo) | |
2412 | { | |
fae2b904 | 2413 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2414 | unsigned int pwropt; |
2415 | ||
2416 | /* | |
2417 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2418 | * Hibernation mode enabled which would show up when device detects | |
2419 | * host-initiated U3 exit. | |
2420 | * | |
2421 | * In that case, device will generate a Link State Change Interrupt | |
2422 | * from U3 to RESUME which is only necessary if Hibernation is | |
2423 | * configured in. | |
2424 | * | |
2425 | * There are no functional changes due to such spurious event and we | |
2426 | * just need to ignore it. | |
2427 | * | |
2428 | * Refers to: | |
2429 | * | |
2430 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2431 | * operational mode | |
2432 | */ | |
2433 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2434 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2435 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2436 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2437 | (next == DWC3_LINK_STATE_RESUME)) { | |
73815280 FB |
2438 | dwc3_trace(trace_dwc3_gadget, |
2439 | "ignoring transition U3 -> Resume"); | |
0b0cc1cd FB |
2440 | return; |
2441 | } | |
2442 | } | |
fae2b904 FB |
2443 | |
2444 | /* | |
2445 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2446 | * on the link partner, the USB session might do multiple entry/exit | |
2447 | * of low power states before a transfer takes place. | |
2448 | * | |
2449 | * Due to this problem, we might experience lower throughput. The | |
2450 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2451 | * transitioning from U1/U2 to U0 and enable those bits again | |
2452 | * after a transfer completes and there are no pending transfers | |
2453 | * on any of the enabled endpoints. | |
2454 | * | |
2455 | * This is the first half of that workaround. | |
2456 | * | |
2457 | * Refers to: | |
2458 | * | |
2459 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2460 | * core send LGO_Ux entering U0 | |
2461 | */ | |
2462 | if (dwc->revision < DWC3_REVISION_183A) { | |
2463 | if (next == DWC3_LINK_STATE_U0) { | |
2464 | u32 u1u2; | |
2465 | u32 reg; | |
2466 | ||
2467 | switch (dwc->link_state) { | |
2468 | case DWC3_LINK_STATE_U1: | |
2469 | case DWC3_LINK_STATE_U2: | |
2470 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2471 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2472 | | DWC3_DCTL_ACCEPTU2ENA | |
2473 | | DWC3_DCTL_INITU1ENA | |
2474 | | DWC3_DCTL_ACCEPTU1ENA); | |
2475 | ||
2476 | if (!dwc->u1u2) | |
2477 | dwc->u1u2 = reg & u1u2; | |
2478 | ||
2479 | reg &= ~u1u2; | |
2480 | ||
2481 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2482 | break; | |
2483 | default: | |
2484 | /* do nothing */ | |
2485 | break; | |
2486 | } | |
2487 | } | |
2488 | } | |
2489 | ||
bc5ba2e0 FB |
2490 | switch (next) { |
2491 | case DWC3_LINK_STATE_U1: | |
2492 | if (dwc->speed == USB_SPEED_SUPER) | |
2493 | dwc3_suspend_gadget(dwc); | |
2494 | break; | |
2495 | case DWC3_LINK_STATE_U2: | |
2496 | case DWC3_LINK_STATE_U3: | |
2497 | dwc3_suspend_gadget(dwc); | |
2498 | break; | |
2499 | case DWC3_LINK_STATE_RESUME: | |
2500 | dwc3_resume_gadget(dwc); | |
2501 | break; | |
2502 | default: | |
2503 | /* do nothing */ | |
2504 | break; | |
2505 | } | |
2506 | ||
e57ebc1d | 2507 | dwc->link_state = next; |
72246da4 FB |
2508 | } |
2509 | ||
e1dadd3b FB |
2510 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2511 | unsigned int evtinfo) | |
2512 | { | |
2513 | unsigned int is_ss = evtinfo & BIT(4); | |
2514 | ||
2515 | /** | |
2516 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2517 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2518 | * randomly. | |
2519 | * | |
2520 | * Because of this issue, core could generate bogus hibernation | |
2521 | * events which SW needs to ignore. | |
2522 | * | |
2523 | * Refers to: | |
2524 | * | |
2525 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2526 | * Device Fallback from SuperSpeed | |
2527 | */ | |
2528 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2529 | return; | |
2530 | ||
2531 | /* enter hibernation here */ | |
2532 | } | |
2533 | ||
72246da4 FB |
2534 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2535 | const struct dwc3_event_devt *event) | |
2536 | { | |
2537 | switch (event->type) { | |
2538 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2539 | dwc3_gadget_disconnect_interrupt(dwc); | |
2540 | break; | |
2541 | case DWC3_DEVICE_EVENT_RESET: | |
2542 | dwc3_gadget_reset_interrupt(dwc); | |
2543 | break; | |
2544 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2545 | dwc3_gadget_conndone_interrupt(dwc); | |
2546 | break; | |
2547 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2548 | dwc3_gadget_wakeup_interrupt(dwc); | |
2549 | break; | |
e1dadd3b FB |
2550 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2551 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2552 | "unexpected hibernation event\n")) | |
2553 | break; | |
2554 | ||
2555 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2556 | break; | |
72246da4 FB |
2557 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2558 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2559 | break; | |
2560 | case DWC3_DEVICE_EVENT_EOPF: | |
73815280 | 2561 | dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame"); |
72246da4 FB |
2562 | break; |
2563 | case DWC3_DEVICE_EVENT_SOF: | |
73815280 | 2564 | dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame"); |
72246da4 FB |
2565 | break; |
2566 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
73815280 | 2567 | dwc3_trace(trace_dwc3_gadget, "Erratic Error"); |
72246da4 FB |
2568 | break; |
2569 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
73815280 | 2570 | dwc3_trace(trace_dwc3_gadget, "Command Complete"); |
72246da4 FB |
2571 | break; |
2572 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
73815280 | 2573 | dwc3_trace(trace_dwc3_gadget, "Overflow"); |
72246da4 FB |
2574 | break; |
2575 | default: | |
e9f2aa87 | 2576 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2577 | } |
2578 | } | |
2579 | ||
2580 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2581 | const union dwc3_event *event) | |
2582 | { | |
2c4cbe6e FB |
2583 | trace_dwc3_event(event->raw); |
2584 | ||
72246da4 FB |
2585 | /* Endpoint IRQ, handle it and return early */ |
2586 | if (event->type.is_devspec == 0) { | |
2587 | /* depevt */ | |
2588 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2589 | } | |
2590 | ||
2591 | switch (event->type.type) { | |
2592 | case DWC3_EVENT_TYPE_DEV: | |
2593 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2594 | break; | |
2595 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2596 | default: | |
2597 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2598 | } | |
2599 | } | |
2600 | ||
f42f2447 | 2601 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) |
b15a762f | 2602 | { |
f42f2447 | 2603 | struct dwc3_event_buffer *evt; |
b15a762f | 2604 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2605 | int left; |
e8adfc30 | 2606 | u32 reg; |
b15a762f | 2607 | |
f42f2447 FB |
2608 | evt = dwc->ev_buffs[buf]; |
2609 | left = evt->count; | |
b15a762f | 2610 | |
f42f2447 FB |
2611 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2612 | return IRQ_NONE; | |
b15a762f | 2613 | |
f42f2447 FB |
2614 | while (left > 0) { |
2615 | union dwc3_event event; | |
b15a762f | 2616 | |
f42f2447 | 2617 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2618 | |
f42f2447 | 2619 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2620 | |
f42f2447 FB |
2621 | /* |
2622 | * FIXME we wrap around correctly to the next entry as | |
2623 | * almost all entries are 4 bytes in size. There is one | |
2624 | * entry which has 12 bytes which is a regular entry | |
2625 | * followed by 8 bytes data. ATM I don't know how | |
2626 | * things are organized if we get next to the a | |
2627 | * boundary so I worry about that once we try to handle | |
2628 | * that. | |
2629 | */ | |
2630 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2631 | left -= 4; | |
b15a762f | 2632 | |
f42f2447 FB |
2633 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); |
2634 | } | |
b15a762f | 2635 | |
f42f2447 FB |
2636 | evt->count = 0; |
2637 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2638 | ret = IRQ_HANDLED; | |
b15a762f | 2639 | |
f42f2447 FB |
2640 | /* Unmask interrupt */ |
2641 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2642 | reg &= ~DWC3_GEVNTSIZ_INTMASK; | |
2643 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
b15a762f | 2644 | |
f42f2447 FB |
2645 | return ret; |
2646 | } | |
e8adfc30 | 2647 | |
f42f2447 FB |
2648 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) |
2649 | { | |
2650 | struct dwc3 *dwc = _dwc; | |
e5f68b4a | 2651 | unsigned long flags; |
f42f2447 FB |
2652 | irqreturn_t ret = IRQ_NONE; |
2653 | int i; | |
2654 | ||
e5f68b4a | 2655 | spin_lock_irqsave(&dwc->lock, flags); |
f42f2447 FB |
2656 | |
2657 | for (i = 0; i < dwc->num_event_buffers; i++) | |
2658 | ret |= dwc3_process_event_buf(dwc, i); | |
b15a762f | 2659 | |
e5f68b4a | 2660 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2661 | |
2662 | return ret; | |
2663 | } | |
2664 | ||
7f97aa98 | 2665 | static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) |
72246da4 FB |
2666 | { |
2667 | struct dwc3_event_buffer *evt; | |
72246da4 | 2668 | u32 count; |
e8adfc30 | 2669 | u32 reg; |
72246da4 | 2670 | |
b15a762f FB |
2671 | evt = dwc->ev_buffs[buf]; |
2672 | ||
72246da4 FB |
2673 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); |
2674 | count &= DWC3_GEVNTCOUNT_MASK; | |
2675 | if (!count) | |
2676 | return IRQ_NONE; | |
2677 | ||
b15a762f FB |
2678 | evt->count = count; |
2679 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2680 | |
e8adfc30 FB |
2681 | /* Mask interrupt */ |
2682 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); | |
2683 | reg |= DWC3_GEVNTSIZ_INTMASK; | |
2684 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); | |
2685 | ||
b15a762f | 2686 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2687 | } |
2688 | ||
2689 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2690 | { | |
2691 | struct dwc3 *dwc = _dwc; | |
2692 | int i; | |
2693 | irqreturn_t ret = IRQ_NONE; | |
2694 | ||
9f622b2a | 2695 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2696 | irqreturn_t status; |
2697 | ||
7f97aa98 | 2698 | status = dwc3_check_event_buf(dwc, i); |
b15a762f | 2699 | if (status == IRQ_WAKE_THREAD) |
72246da4 FB |
2700 | ret = status; |
2701 | } | |
2702 | ||
72246da4 FB |
2703 | return ret; |
2704 | } | |
2705 | ||
2706 | /** | |
2707 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2708 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2709 | * |
2710 | * Returns 0 on success otherwise negative errno. | |
2711 | */ | |
41ac7b3a | 2712 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2713 | { |
72246da4 | 2714 | int ret; |
72246da4 FB |
2715 | |
2716 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2717 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2718 | if (!dwc->ctrl_req) { | |
2719 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2720 | ret = -ENOMEM; | |
2721 | goto err0; | |
2722 | } | |
2723 | ||
2abd9d5f | 2724 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2725 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2726 | if (!dwc->ep0_trb) { | |
2727 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2728 | ret = -ENOMEM; | |
2729 | goto err1; | |
2730 | } | |
2731 | ||
3ef35faf | 2732 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2733 | if (!dwc->setup_buf) { |
72246da4 FB |
2734 | ret = -ENOMEM; |
2735 | goto err2; | |
2736 | } | |
2737 | ||
5812b1c2 | 2738 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2739 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2740 | GFP_KERNEL); | |
5812b1c2 FB |
2741 | if (!dwc->ep0_bounce) { |
2742 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2743 | ret = -ENOMEM; | |
2744 | goto err3; | |
2745 | } | |
2746 | ||
72246da4 | 2747 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 2748 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 2749 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2750 | dwc->gadget.name = "dwc3-gadget"; |
2751 | ||
b9e51b2b BM |
2752 | /* |
2753 | * FIXME We might be setting max_speed to <SUPER, however versions | |
2754 | * <2.20a of dwc3 have an issue with metastability (documented | |
2755 | * elsewhere in this driver) which tells us we can't set max speed to | |
2756 | * anything lower than SUPER. | |
2757 | * | |
2758 | * Because gadget.max_speed is only used by composite.c and function | |
2759 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
2760 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
2761 | * together with our BOS descriptor as that could confuse host into | |
2762 | * thinking we can handle super speed. | |
2763 | * | |
2764 | * Note that, in fact, we won't even support GetBOS requests when speed | |
2765 | * is less than super speed because we don't have means, yet, to tell | |
2766 | * composite.c that we are USB 2.0 + LPM ECN. | |
2767 | */ | |
2768 | if (dwc->revision < DWC3_REVISION_220A) | |
2769 | dwc3_trace(trace_dwc3_gadget, | |
2770 | "Changing max_speed on rev %08x\n", | |
2771 | dwc->revision); | |
2772 | ||
2773 | dwc->gadget.max_speed = dwc->maximum_speed; | |
2774 | ||
a4b9d94b DC |
2775 | /* |
2776 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
2777 | * on ep out. | |
2778 | */ | |
2779 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
2780 | ||
72246da4 FB |
2781 | /* |
2782 | * REVISIT: Here we should clear all pending IRQs to be | |
2783 | * sure we're starting from a well known location. | |
2784 | */ | |
2785 | ||
2786 | ret = dwc3_gadget_init_endpoints(dwc); | |
2787 | if (ret) | |
5812b1c2 | 2788 | goto err4; |
72246da4 | 2789 | |
72246da4 FB |
2790 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
2791 | if (ret) { | |
2792 | dev_err(dwc->dev, "failed to register udc\n"); | |
e1f80467 | 2793 | goto err4; |
72246da4 FB |
2794 | } |
2795 | ||
2796 | return 0; | |
2797 | ||
5812b1c2 | 2798 | err4: |
e1f80467 | 2799 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
2800 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2801 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2802 | |
72246da4 | 2803 | err3: |
0fc9a1be | 2804 | kfree(dwc->setup_buf); |
72246da4 FB |
2805 | |
2806 | err2: | |
2807 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2808 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2809 | ||
2810 | err1: | |
2811 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2812 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2813 | ||
2814 | err0: | |
2815 | return ret; | |
2816 | } | |
2817 | ||
7415f17c FB |
2818 | /* -------------------------------------------------------------------------- */ |
2819 | ||
72246da4 FB |
2820 | void dwc3_gadget_exit(struct dwc3 *dwc) |
2821 | { | |
72246da4 | 2822 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 2823 | |
72246da4 FB |
2824 | dwc3_gadget_free_endpoints(dwc); |
2825 | ||
3ef35faf FB |
2826 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2827 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2828 | |
0fc9a1be | 2829 | kfree(dwc->setup_buf); |
72246da4 FB |
2830 | |
2831 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2832 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2833 | ||
2834 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2835 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 2836 | } |
7415f17c | 2837 | |
0b0231aa | 2838 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 2839 | { |
7b2a0368 | 2840 | if (dwc->pullups_connected) { |
7415f17c | 2841 | dwc3_gadget_disable_irq(dwc); |
7b2a0368 FB |
2842 | dwc3_gadget_run_stop(dwc, true, true); |
2843 | } | |
7415f17c | 2844 | |
7415f17c FB |
2845 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
2846 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
2847 | ||
2848 | dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2849 | ||
2850 | return 0; | |
2851 | } | |
2852 | ||
2853 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
2854 | { | |
2855 | struct dwc3_ep *dep; | |
2856 | int ret; | |
2857 | ||
2858 | /* Start with SuperSpeed Default */ | |
2859 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
2860 | ||
2861 | dep = dwc->eps[0]; | |
265b70a7 PZ |
2862 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2863 | false); | |
7415f17c FB |
2864 | if (ret) |
2865 | goto err0; | |
2866 | ||
2867 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2868 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
2869 | false); | |
7415f17c FB |
2870 | if (ret) |
2871 | goto err1; | |
2872 | ||
2873 | /* begin to receive SETUP packets */ | |
2874 | dwc->ep0state = EP0_SETUP_PHASE; | |
2875 | dwc3_ep0_out_start(dwc); | |
2876 | ||
2877 | dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); | |
2878 | ||
0b0231aa FB |
2879 | if (dwc->pullups_connected) { |
2880 | dwc3_gadget_enable_irq(dwc); | |
2881 | dwc3_gadget_run_stop(dwc, true, false); | |
2882 | } | |
2883 | ||
7415f17c FB |
2884 | return 0; |
2885 | ||
2886 | err1: | |
2887 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
2888 | ||
2889 | err0: | |
2890 | return ret; | |
2891 | } |