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bfad65ee | 1 | /* |
72246da4 FB |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd | 38 | /** |
bfad65ee | 39 | * dwc3_gadget_set_test_mode - enables usb2 test modes |
04a9bfcd FB |
40 | * @dwc: pointer to our context structure |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
bfad65ee FB |
43 | * Caller should take care of locking. This function will return 0 on |
44 | * success or -EINVAL if wrong Test Selector is passed. | |
04a9bfcd FB |
45 | */ |
46 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
47 | { | |
48 | u32 reg; | |
49 | ||
50 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
51 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
52 | ||
53 | switch (mode) { | |
54 | case TEST_J: | |
55 | case TEST_K: | |
56 | case TEST_SE0_NAK: | |
57 | case TEST_PACKET: | |
58 | case TEST_FORCE_EN: | |
59 | reg |= mode << 1; | |
60 | break; | |
61 | default: | |
62 | return -EINVAL; | |
63 | } | |
64 | ||
65 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
911f1f88 | 70 | /** |
bfad65ee | 71 | * dwc3_gadget_get_link_state - gets current state of usb link |
911f1f88 PZ |
72 | * @dwc: pointer to our context structure |
73 | * | |
74 | * Caller should take care of locking. This function will | |
75 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
76 | */ | |
77 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
78 | { | |
79 | u32 reg; | |
80 | ||
81 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
82 | ||
83 | return DWC3_DSTS_USBLNKST(reg); | |
84 | } | |
85 | ||
8598bde7 | 86 | /** |
bfad65ee | 87 | * dwc3_gadget_set_link_state - sets usb link to a particular state |
8598bde7 FB |
88 | * @dwc: pointer to our context structure |
89 | * @state: the state to put link into | |
90 | * | |
91 | * Caller should take care of locking. This function will | |
aee63e3c | 92 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
93 | */ |
94 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
95 | { | |
aee63e3c | 96 | int retries = 10000; |
8598bde7 FB |
97 | u32 reg; |
98 | ||
802fde98 PZ |
99 | /* |
100 | * Wait until device controller is ready. Only applies to 1.94a and | |
101 | * later RTL. | |
102 | */ | |
103 | if (dwc->revision >= DWC3_REVISION_194A) { | |
104 | while (--retries) { | |
105 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
106 | if (reg & DWC3_DSTS_DCNRD) | |
107 | udelay(5); | |
108 | else | |
109 | break; | |
110 | } | |
111 | ||
112 | if (retries <= 0) | |
113 | return -ETIMEDOUT; | |
114 | } | |
115 | ||
8598bde7 FB |
116 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
117 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
118 | ||
119 | /* set requested state */ | |
120 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
121 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
122 | ||
802fde98 PZ |
123 | /* |
124 | * The following code is racy when called from dwc3_gadget_wakeup, | |
125 | * and is not needed, at least on newer versions | |
126 | */ | |
127 | if (dwc->revision >= DWC3_REVISION_194A) | |
128 | return 0; | |
129 | ||
8598bde7 | 130 | /* wait for a change in DSTS */ |
aed430e5 | 131 | retries = 10000; |
8598bde7 FB |
132 | while (--retries) { |
133 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
134 | ||
8598bde7 FB |
135 | if (DWC3_DSTS_USBLNKST(reg) == state) |
136 | return 0; | |
137 | ||
aee63e3c | 138 | udelay(5); |
8598bde7 FB |
139 | } |
140 | ||
8598bde7 FB |
141 | return -ETIMEDOUT; |
142 | } | |
143 | ||
dca0119c | 144 | /** |
bfad65ee FB |
145 | * dwc3_ep_inc_trb - increment a trb index. |
146 | * @index: Pointer to the TRB index to increment. | |
dca0119c JY |
147 | * |
148 | * The index should never point to the link TRB. After incrementing, | |
149 | * if it is point to the link TRB, wrap around to the beginning. The | |
150 | * link TRB is always at the last TRB entry. | |
151 | */ | |
152 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 153 | { |
dca0119c JY |
154 | (*index)++; |
155 | if (*index == (DWC3_TRB_NUM - 1)) | |
156 | *index = 0; | |
ef966b9d | 157 | } |
457e84b6 | 158 | |
bfad65ee FB |
159 | /** |
160 | * dwc3_ep_inc_enq - increment endpoint's enqueue pointer | |
161 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
162 | */ | |
dca0119c | 163 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 164 | { |
dca0119c | 165 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 166 | } |
457e84b6 | 167 | |
bfad65ee FB |
168 | /** |
169 | * dwc3_ep_inc_deq - increment endpoint's dequeue pointer | |
170 | * @dep: The endpoint whose enqueue pointer we're incrementing | |
171 | */ | |
dca0119c | 172 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 173 | { |
dca0119c | 174 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
175 | } |
176 | ||
bfad65ee FB |
177 | /** |
178 | * dwc3_gadget_giveback - call struct usb_request's ->complete callback | |
179 | * @dep: The endpoint to whom the request belongs to | |
180 | * @req: The request we're giving back | |
181 | * @status: completion code for the request | |
182 | * | |
183 | * Must be called with controller's lock held and interrupts disabled. This | |
184 | * function will unmap @req and call its ->complete() callback to notify upper | |
185 | * layers that it has completed. | |
186 | */ | |
72246da4 FB |
187 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
188 | int status) | |
189 | { | |
190 | struct dwc3 *dwc = dep->dwc; | |
191 | ||
737f1ae2 | 192 | req->started = false; |
72246da4 | 193 | list_del(&req->list); |
eeb720fb | 194 | req->trb = NULL; |
e62c5bc5 | 195 | req->remaining = 0; |
72246da4 FB |
196 | |
197 | if (req->request.status == -EINPROGRESS) | |
198 | req->request.status = status; | |
199 | ||
4199c5f8 FB |
200 | usb_gadget_unmap_request_by_dev(dwc->sysdev, |
201 | &req->request, req->direction); | |
72246da4 | 202 | |
2c4cbe6e | 203 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
204 | |
205 | spin_unlock(&dwc->lock); | |
304f7e5e | 206 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 | 207 | spin_lock(&dwc->lock); |
fc8bb91b FB |
208 | |
209 | if (dep->number > 1) | |
210 | pm_runtime_put(dwc->dev); | |
72246da4 FB |
211 | } |
212 | ||
bfad65ee FB |
213 | /** |
214 | * dwc3_send_gadget_generic_command - issue a generic command for the controller | |
215 | * @dwc: pointer to the controller context | |
216 | * @cmd: the command to be issued | |
217 | * @param: command parameter | |
218 | * | |
219 | * Caller should take care of locking. Issue @cmd with a given @param to @dwc | |
220 | * and wait for its completion. | |
221 | */ | |
3ece0ec4 | 222 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
223 | { |
224 | u32 timeout = 500; | |
71f7e702 | 225 | int status = 0; |
0fe886cd | 226 | int ret = 0; |
b09bb642 FB |
227 | u32 reg; |
228 | ||
229 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
230 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
231 | ||
232 | do { | |
233 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
234 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
235 | status = DWC3_DGCMD_STATUS(reg); |
236 | if (status) | |
0fe886cd FB |
237 | ret = -EINVAL; |
238 | break; | |
b09bb642 | 239 | } |
e3aee486 | 240 | } while (--timeout); |
0fe886cd FB |
241 | |
242 | if (!timeout) { | |
0fe886cd | 243 | ret = -ETIMEDOUT; |
71f7e702 | 244 | status = -ETIMEDOUT; |
0fe886cd FB |
245 | } |
246 | ||
71f7e702 FB |
247 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
248 | ||
0fe886cd | 249 | return ret; |
b09bb642 FB |
250 | } |
251 | ||
c36d8e94 FB |
252 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
253 | ||
bfad65ee FB |
254 | /** |
255 | * dwc3_send_gadget_ep_cmd - issue an endpoint command | |
256 | * @dep: the endpoint to which the command is going to be issued | |
257 | * @cmd: the command to be issued | |
258 | * @params: parameters to the command | |
259 | * | |
260 | * Caller should handle locking. This function will issue @cmd with given | |
261 | * @params to @dep and wait for its completion. | |
262 | */ | |
2cd4718d FB |
263 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
264 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 265 | { |
8897a761 | 266 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 267 | struct dwc3 *dwc = dep->dwc; |
61d58242 | 268 | u32 timeout = 500; |
72246da4 FB |
269 | u32 reg; |
270 | ||
0933df15 | 271 | int cmd_status = 0; |
2b0f11df | 272 | int susphy = false; |
c0ca324d | 273 | int ret = -EINVAL; |
72246da4 | 274 | |
2b0f11df FB |
275 | /* |
276 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
277 | * we're issuing an endpoint command, we must check if | |
278 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
279 | * | |
280 | * We will also set SUSPHY bit to what it was before returning as stated | |
281 | * by the same section on Synopsys databook. | |
282 | */ | |
ab2a92e7 FB |
283 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
284 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
285 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
286 | susphy = true; | |
287 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
288 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
289 | } | |
2b0f11df FB |
290 | } |
291 | ||
5999914f | 292 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
293 | int needs_wakeup; |
294 | ||
295 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
296 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
297 | dwc->link_state == DWC3_LINK_STATE_U3); | |
298 | ||
299 | if (unlikely(needs_wakeup)) { | |
300 | ret = __dwc3_gadget_wakeup(dwc); | |
301 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
302 | ret); | |
303 | } | |
304 | } | |
305 | ||
2eb88016 FB |
306 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
307 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
308 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 309 | |
8897a761 FB |
310 | /* |
311 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
312 | * not relying on XferNotReady, we can make use of a special "No | |
313 | * Response Update Transfer" command where we should clear both CmdAct | |
314 | * and CmdIOC bits. | |
315 | * | |
316 | * With this, we don't need to wait for command completion and can | |
317 | * straight away issue further commands to the endpoint. | |
318 | * | |
319 | * NOTICE: We're making an assumption that control endpoints will never | |
320 | * make use of Update Transfer command. This is a safe assumption | |
321 | * because we can never have more than one request at a time with | |
322 | * Control Endpoints. If anybody changes that assumption, this chunk | |
323 | * needs to be updated accordingly. | |
324 | */ | |
325 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
326 | !usb_endpoint_xfer_isoc(desc)) | |
327 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
328 | else | |
329 | cmd |= DWC3_DEPCMD_CMDACT; | |
330 | ||
331 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 332 | do { |
2eb88016 | 333 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 334 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 335 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 336 | |
7b9cc7a2 KL |
337 | switch (cmd_status) { |
338 | case 0: | |
339 | ret = 0; | |
340 | break; | |
341 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
7b9cc7a2 | 342 | ret = -EINVAL; |
c0ca324d | 343 | break; |
7b9cc7a2 KL |
344 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
345 | /* | |
346 | * SW issues START TRANSFER command to | |
347 | * isochronous ep with future frame interval. If | |
348 | * future interval time has already passed when | |
349 | * core receives the command, it will respond | |
350 | * with an error status of 'Bus Expiry'. | |
351 | * | |
352 | * Instead of always returning -EINVAL, let's | |
353 | * give a hint to the gadget driver that this is | |
354 | * the case by returning -EAGAIN. | |
355 | */ | |
7b9cc7a2 KL |
356 | ret = -EAGAIN; |
357 | break; | |
358 | default: | |
359 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
360 | } | |
361 | ||
c0ca324d | 362 | break; |
72246da4 | 363 | } |
f6bb225b | 364 | } while (--timeout); |
72246da4 | 365 | |
f6bb225b | 366 | if (timeout == 0) { |
f6bb225b | 367 | ret = -ETIMEDOUT; |
0933df15 | 368 | cmd_status = -ETIMEDOUT; |
f6bb225b | 369 | } |
c0ca324d | 370 | |
0933df15 FB |
371 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
372 | ||
6cb2e4e3 FB |
373 | if (ret == 0) { |
374 | switch (DWC3_DEPCMD_CMD(cmd)) { | |
375 | case DWC3_DEPCMD_STARTTRANSFER: | |
376 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
377 | break; | |
378 | case DWC3_DEPCMD_ENDTRANSFER: | |
379 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
380 | break; | |
381 | default: | |
382 | /* nothing */ | |
383 | break; | |
384 | } | |
385 | } | |
386 | ||
2b0f11df FB |
387 | if (unlikely(susphy)) { |
388 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
389 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
390 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
391 | } | |
392 | ||
c0ca324d | 393 | return ret; |
72246da4 FB |
394 | } |
395 | ||
50c763f8 JY |
396 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
397 | { | |
398 | struct dwc3 *dwc = dep->dwc; | |
399 | struct dwc3_gadget_ep_cmd_params params; | |
400 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
401 | ||
402 | /* | |
403 | * As of core revision 2.60a the recommended programming model | |
404 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
405 | * command for IN endpoints. This is to prevent an issue where | |
406 | * some (non-compliant) hosts may not send ACK TPs for pending | |
407 | * IN transfers due to a mishandled error condition. Synopsys | |
408 | * STAR 9000614252. | |
409 | */ | |
5e6c88d2 LB |
410 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
411 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
412 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
413 | ||
414 | memset(¶ms, 0, sizeof(params)); | |
415 | ||
2cd4718d | 416 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
417 | } |
418 | ||
72246da4 | 419 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 420 | struct dwc3_trb *trb) |
72246da4 | 421 | { |
c439ef87 | 422 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
423 | |
424 | return dep->trb_pool_dma + offset; | |
425 | } | |
426 | ||
427 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
428 | { | |
429 | struct dwc3 *dwc = dep->dwc; | |
430 | ||
431 | if (dep->trb_pool) | |
432 | return 0; | |
433 | ||
d64ff406 | 434 | dep->trb_pool = dma_alloc_coherent(dwc->sysdev, |
72246da4 FB |
435 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
436 | &dep->trb_pool_dma, GFP_KERNEL); | |
437 | if (!dep->trb_pool) { | |
438 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
439 | dep->name); | |
440 | return -ENOMEM; | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
447 | { | |
448 | struct dwc3 *dwc = dep->dwc; | |
449 | ||
d64ff406 | 450 | dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, |
72246da4 FB |
451 | dep->trb_pool, dep->trb_pool_dma); |
452 | ||
453 | dep->trb_pool = NULL; | |
454 | dep->trb_pool_dma = 0; | |
455 | } | |
456 | ||
c4509601 JY |
457 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
458 | ||
459 | /** | |
bfad65ee | 460 | * dwc3_gadget_start_config - configure ep resources |
c4509601 JY |
461 | * @dwc: pointer to our controller context structure |
462 | * @dep: endpoint that is being enabled | |
463 | * | |
bfad65ee FB |
464 | * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's |
465 | * completion, it will set Transfer Resource for all available endpoints. | |
c4509601 | 466 | * |
bfad65ee FB |
467 | * The assignment of transfer resources cannot perfectly follow the data book |
468 | * due to the fact that the controller driver does not have all knowledge of the | |
469 | * configuration in advance. It is given this information piecemeal by the | |
470 | * composite gadget framework after every SET_CONFIGURATION and | |
471 | * SET_INTERFACE. Trying to follow the databook programming model in this | |
472 | * scenario can cause errors. For two reasons: | |
c4509601 | 473 | * |
bfad65ee FB |
474 | * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every |
475 | * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is | |
476 | * incorrect in the scenario of multiple interfaces. | |
477 | * | |
478 | * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new | |
c4509601 JY |
479 | * endpoint on alt setting (8.1.6). |
480 | * | |
481 | * The following simplified method is used instead: | |
482 | * | |
bfad65ee FB |
483 | * All hardware endpoints can be assigned a transfer resource and this setting |
484 | * will stay persistent until either a core reset or hibernation. So whenever we | |
485 | * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do | |
486 | * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are | |
c4509601 JY |
487 | * guaranteed that there are as many transfer resources as endpoints. |
488 | * | |
bfad65ee FB |
489 | * This function is called for each endpoint when it is being enabled but is |
490 | * triggered only when called for EP0-out, which always happens first, and which | |
491 | * should only happen in one of the above conditions. | |
c4509601 | 492 | */ |
72246da4 FB |
493 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
494 | { | |
495 | struct dwc3_gadget_ep_cmd_params params; | |
496 | u32 cmd; | |
c4509601 JY |
497 | int i; |
498 | int ret; | |
499 | ||
500 | if (dep->number) | |
501 | return 0; | |
72246da4 FB |
502 | |
503 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 504 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 505 | |
2cd4718d | 506 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
507 | if (ret) |
508 | return ret; | |
509 | ||
510 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
511 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 512 | |
c4509601 JY |
513 | if (!dep) |
514 | continue; | |
515 | ||
516 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
517 | if (ret) | |
518 | return ret; | |
72246da4 FB |
519 | } |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
21e64bf2 | 525 | bool modify, bool restore) |
72246da4 | 526 | { |
39ebb05c JY |
527 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
528 | const struct usb_endpoint_descriptor *desc; | |
72246da4 FB |
529 | struct dwc3_gadget_ep_cmd_params params; |
530 | ||
21e64bf2 FB |
531 | if (dev_WARN_ONCE(dwc->dev, modify && restore, |
532 | "Can't modify and restore\n")) | |
533 | return -EINVAL; | |
534 | ||
39ebb05c JY |
535 | comp_desc = dep->endpoint.comp_desc; |
536 | desc = dep->endpoint.desc; | |
537 | ||
72246da4 FB |
538 | memset(¶ms, 0x00, sizeof(params)); |
539 | ||
dc1c70a7 | 540 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
541 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
542 | ||
543 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 544 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 545 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 546 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 547 | } |
72246da4 | 548 | |
21e64bf2 FB |
549 | if (modify) { |
550 | params.param0 |= DWC3_DEPCFG_ACTION_MODIFY; | |
551 | } else if (restore) { | |
265b70a7 PZ |
552 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; |
553 | params.param2 |= dep->saved_state; | |
21e64bf2 FB |
554 | } else { |
555 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; | |
265b70a7 PZ |
556 | } |
557 | ||
4bc48c97 FB |
558 | if (usb_endpoint_xfer_control(desc)) |
559 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
560 | |
561 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
562 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 563 | |
18b7ede5 | 564 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
565 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
566 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
567 | dep->stream_capable = true; |
568 | } | |
569 | ||
0b93a4c8 | 570 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 571 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
572 | |
573 | /* | |
574 | * We are doing 1:1 mapping for endpoints, meaning | |
575 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
576 | * so on. We consider the direction bit as part of the physical | |
577 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
578 | */ | |
dc1c70a7 | 579 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
580 | |
581 | /* | |
582 | * We must use the lower 16 TX FIFOs even though | |
583 | * HW might have more | |
584 | */ | |
585 | if (dep->direction) | |
dc1c70a7 | 586 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
587 | |
588 | if (desc->bInterval) { | |
dc1c70a7 | 589 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
590 | dep->interval = 1 << (desc->bInterval - 1); |
591 | } | |
592 | ||
2cd4718d | 593 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
594 | } |
595 | ||
596 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
597 | { | |
598 | struct dwc3_gadget_ep_cmd_params params; | |
599 | ||
600 | memset(¶ms, 0x00, sizeof(params)); | |
601 | ||
dc1c70a7 | 602 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 | 603 | |
2cd4718d FB |
604 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, |
605 | ¶ms); | |
72246da4 FB |
606 | } |
607 | ||
608 | /** | |
bfad65ee | 609 | * __dwc3_gadget_ep_enable - initializes a hw endpoint |
72246da4 | 610 | * @dep: endpoint to be initialized |
bfad65ee FB |
611 | * @modify: if true, modify existing endpoint configuration |
612 | * @restore: if true, restore endpoint configuration from scratch buffer | |
72246da4 | 613 | * |
bfad65ee FB |
614 | * Caller should take care of locking. Execute all necessary commands to |
615 | * initialize a HW endpoint so it can be used by a gadget driver. | |
72246da4 FB |
616 | */ |
617 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
21e64bf2 | 618 | bool modify, bool restore) |
72246da4 | 619 | { |
39ebb05c | 620 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
72246da4 | 621 | struct dwc3 *dwc = dep->dwc; |
39ebb05c | 622 | |
72246da4 | 623 | u32 reg; |
b09e99ee | 624 | int ret; |
72246da4 FB |
625 | |
626 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
627 | ret = dwc3_gadget_start_config(dwc, dep); | |
628 | if (ret) | |
629 | return ret; | |
630 | } | |
631 | ||
39ebb05c | 632 | ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore); |
72246da4 FB |
633 | if (ret) |
634 | return ret; | |
635 | ||
636 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
637 | struct dwc3_trb *trb_st_hw; |
638 | struct dwc3_trb *trb_link; | |
72246da4 | 639 | |
72246da4 FB |
640 | dep->type = usb_endpoint_type(desc); |
641 | dep->flags |= DWC3_EP_ENABLED; | |
76a638f8 | 642 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
643 | |
644 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
645 | reg |= DWC3_DALEPENA_EP(dep->number); | |
646 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
647 | ||
76a638f8 BW |
648 | init_waitqueue_head(&dep->wait_end_transfer); |
649 | ||
36b68aae | 650 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 651 | goto out; |
72246da4 | 652 | |
0d25744a JY |
653 | /* Initialize the TRB ring */ |
654 | dep->trb_dequeue = 0; | |
655 | dep->trb_enqueue = 0; | |
656 | memset(dep->trb_pool, 0, | |
657 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
658 | ||
36b68aae | 659 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
660 | trb_st_hw = &dep->trb_pool[0]; |
661 | ||
f6bafc6a | 662 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
663 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
664 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
665 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
666 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
667 | } |
668 | ||
a97ea994 FB |
669 | /* |
670 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
671 | * Response Update Transfer command. | |
672 | */ | |
673 | if (usb_endpoint_xfer_bulk(desc)) { | |
674 | struct dwc3_gadget_ep_cmd_params params; | |
675 | struct dwc3_trb *trb; | |
676 | dma_addr_t trb_dma; | |
677 | u32 cmd; | |
678 | ||
679 | memset(¶ms, 0, sizeof(params)); | |
680 | trb = &dep->trb_pool[0]; | |
681 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
682 | ||
683 | params.param0 = upper_32_bits(trb_dma); | |
684 | params.param1 = lower_32_bits(trb_dma); | |
685 | ||
686 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
687 | ||
688 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
689 | if (ret < 0) | |
690 | return ret; | |
691 | ||
692 | dep->flags |= DWC3_EP_BUSY; | |
693 | ||
694 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); | |
695 | WARN_ON_ONCE(!dep->resource_index); | |
696 | } | |
697 | ||
2870e501 FB |
698 | |
699 | out: | |
700 | trace_dwc3_gadget_ep_enable(dep); | |
701 | ||
72246da4 FB |
702 | return 0; |
703 | } | |
704 | ||
b992e681 | 705 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 706 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
707 | { |
708 | struct dwc3_request *req; | |
709 | ||
0e146028 | 710 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 711 | |
0e146028 FB |
712 | /* - giveback all requests to gadget driver */ |
713 | while (!list_empty(&dep->started_list)) { | |
714 | req = next_request(&dep->started_list); | |
1591633e | 715 | |
0e146028 | 716 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
717 | } |
718 | ||
aa3342c8 FB |
719 | while (!list_empty(&dep->pending_list)) { |
720 | req = next_request(&dep->pending_list); | |
72246da4 | 721 | |
624407f9 | 722 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 723 | } |
72246da4 FB |
724 | } |
725 | ||
726 | /** | |
bfad65ee | 727 | * __dwc3_gadget_ep_disable - disables a hw endpoint |
72246da4 FB |
728 | * @dep: the endpoint to disable |
729 | * | |
bfad65ee FB |
730 | * This function undoes what __dwc3_gadget_ep_enable did and also removes |
731 | * requests which are currently being processed by the hardware and those which | |
732 | * are not yet scheduled. | |
733 | * | |
624407f9 | 734 | * Caller should take care of locking. |
72246da4 | 735 | */ |
72246da4 FB |
736 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
737 | { | |
738 | struct dwc3 *dwc = dep->dwc; | |
739 | u32 reg; | |
740 | ||
2870e501 | 741 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 742 | |
624407f9 | 743 | dwc3_remove_requests(dwc, dep); |
72246da4 | 744 | |
687ef981 FB |
745 | /* make sure HW endpoint isn't stalled */ |
746 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 747 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 748 | |
72246da4 FB |
749 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
750 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
751 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
752 | ||
879631aa | 753 | dep->stream_capable = false; |
72246da4 | 754 | dep->type = 0; |
76a638f8 | 755 | dep->flags &= DWC3_EP_END_TRANSFER_PENDING; |
72246da4 | 756 | |
39ebb05c JY |
757 | /* Clear out the ep descriptors for non-ep0 */ |
758 | if (dep->number > 1) { | |
759 | dep->endpoint.comp_desc = NULL; | |
760 | dep->endpoint.desc = NULL; | |
761 | } | |
762 | ||
72246da4 FB |
763 | return 0; |
764 | } | |
765 | ||
766 | /* -------------------------------------------------------------------------- */ | |
767 | ||
768 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
769 | const struct usb_endpoint_descriptor *desc) | |
770 | { | |
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
775 | { | |
776 | return -EINVAL; | |
777 | } | |
778 | ||
779 | /* -------------------------------------------------------------------------- */ | |
780 | ||
781 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
782 | const struct usb_endpoint_descriptor *desc) | |
783 | { | |
784 | struct dwc3_ep *dep; | |
785 | struct dwc3 *dwc; | |
786 | unsigned long flags; | |
787 | int ret; | |
788 | ||
789 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
790 | pr_debug("dwc3: invalid parameters\n"); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | if (!desc->wMaxPacketSize) { | |
795 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | dep = to_dwc3_ep(ep); | |
800 | dwc = dep->dwc; | |
801 | ||
95ca961c FB |
802 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
803 | "%s is already enabled\n", | |
804 | dep->name)) | |
c6f83f38 | 805 | return 0; |
c6f83f38 | 806 | |
72246da4 | 807 | spin_lock_irqsave(&dwc->lock, flags); |
39ebb05c | 808 | ret = __dwc3_gadget_ep_enable(dep, false, false); |
72246da4 FB |
809 | spin_unlock_irqrestore(&dwc->lock, flags); |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
814 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
815 | { | |
816 | struct dwc3_ep *dep; | |
817 | struct dwc3 *dwc; | |
818 | unsigned long flags; | |
819 | int ret; | |
820 | ||
821 | if (!ep) { | |
822 | pr_debug("dwc3: invalid parameters\n"); | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | dep = to_dwc3_ep(ep); | |
827 | dwc = dep->dwc; | |
828 | ||
95ca961c FB |
829 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
830 | "%s is already disabled\n", | |
831 | dep->name)) | |
72246da4 | 832 | return 0; |
72246da4 | 833 | |
72246da4 FB |
834 | spin_lock_irqsave(&dwc->lock, flags); |
835 | ret = __dwc3_gadget_ep_disable(dep); | |
836 | spin_unlock_irqrestore(&dwc->lock, flags); | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
841 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
842 | gfp_t gfp_flags) | |
843 | { | |
844 | struct dwc3_request *req; | |
845 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
846 | |
847 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 848 | if (!req) |
72246da4 | 849 | return NULL; |
72246da4 FB |
850 | |
851 | req->epnum = dep->number; | |
852 | req->dep = dep; | |
72246da4 | 853 | |
68d34c8a FB |
854 | dep->allocated_requests++; |
855 | ||
2c4cbe6e FB |
856 | trace_dwc3_alloc_request(req); |
857 | ||
72246da4 FB |
858 | return &req->request; |
859 | } | |
860 | ||
861 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
862 | struct usb_request *request) | |
863 | { | |
864 | struct dwc3_request *req = to_dwc3_request(request); | |
68d34c8a | 865 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
72246da4 | 866 | |
68d34c8a | 867 | dep->allocated_requests--; |
2c4cbe6e | 868 | trace_dwc3_free_request(req); |
72246da4 FB |
869 | kfree(req); |
870 | } | |
871 | ||
2c78c029 FB |
872 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep); |
873 | ||
e49d3cf4 FB |
874 | static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, |
875 | dma_addr_t dma, unsigned length, unsigned chain, unsigned node, | |
876 | unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt) | |
c71fc37c | 877 | { |
6b9018d4 FB |
878 | struct dwc3 *dwc = dep->dwc; |
879 | struct usb_gadget *gadget = &dwc->gadget; | |
880 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 881 | |
ef966b9d | 882 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 883 | |
f6bafc6a FB |
884 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
885 | trb->bpl = lower_32_bits(dma); | |
886 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 887 | |
16e78db7 | 888 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 889 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 890 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
891 | break; |
892 | ||
893 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 894 | if (!node) { |
e5ba5ec8 | 895 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 FB |
896 | |
897 | if (speed == USB_SPEED_HIGH) { | |
898 | struct usb_ep *ep = &dep->endpoint; | |
899 | trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1); | |
900 | } | |
901 | } else { | |
e5ba5ec8 | 902 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 903 | } |
ca4d44ea FB |
904 | |
905 | /* always enable Interrupt on Missed ISOC */ | |
906 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
907 | break; |
908 | ||
909 | case USB_ENDPOINT_XFER_BULK: | |
910 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 911 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
912 | break; |
913 | default: | |
914 | /* | |
915 | * This is only possible with faulty memory because we | |
916 | * checked it already :) | |
917 | */ | |
0a695d4c FB |
918 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
919 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
920 | } |
921 | ||
ca4d44ea | 922 | /* always enable Continue on Short Packet */ |
c9508c8c | 923 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
58f29034 | 924 | trb->ctrl |= DWC3_TRB_CTRL_CSP; |
f3af3651 | 925 | |
e49d3cf4 | 926 | if (short_not_ok) |
c9508c8c FB |
927 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
928 | } | |
929 | ||
e49d3cf4 | 930 | if ((!no_interrupt && !chain) || |
2c78c029 | 931 | (dwc3_calc_trbs_left(dep) == 0)) |
c9508c8c | 932 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 933 | |
e5ba5ec8 PA |
934 | if (chain) |
935 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
936 | ||
16e78db7 | 937 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
e49d3cf4 | 938 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); |
c71fc37c | 939 | |
f6bafc6a | 940 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
941 | |
942 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
943 | } |
944 | ||
e49d3cf4 FB |
945 | /** |
946 | * dwc3_prepare_one_trb - setup one TRB from one request | |
947 | * @dep: endpoint for which this request is prepared | |
948 | * @req: dwc3_request pointer | |
949 | * @chain: should this TRB be chained to the next? | |
950 | * @node: only for isochronous endpoints. First TRB needs different type. | |
951 | */ | |
952 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, | |
953 | struct dwc3_request *req, unsigned chain, unsigned node) | |
954 | { | |
955 | struct dwc3_trb *trb; | |
956 | unsigned length = req->request.length; | |
957 | unsigned stream_id = req->request.stream_id; | |
958 | unsigned short_not_ok = req->request.short_not_ok; | |
959 | unsigned no_interrupt = req->request.no_interrupt; | |
960 | dma_addr_t dma = req->request.dma; | |
961 | ||
962 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
963 | ||
964 | if (!req->trb) { | |
965 | dwc3_gadget_move_started_request(req); | |
966 | req->trb = trb; | |
967 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
968 | dep->queued_requests++; | |
969 | } | |
970 | ||
971 | __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, | |
972 | stream_id, short_not_ok, no_interrupt); | |
973 | } | |
974 | ||
361572b5 | 975 | /** |
bfad65ee | 976 | * dwc3_ep_prev_trb - returns the previous TRB in the ring |
361572b5 JY |
977 | * @dep: The endpoint with the TRB ring |
978 | * @index: The index of the current TRB in the ring | |
979 | * | |
980 | * Returns the TRB prior to the one pointed to by the index. If the | |
981 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
982 | * the one just before that. | |
983 | */ | |
984 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
985 | { | |
45438a0c | 986 | u8 tmp = index; |
361572b5 | 987 | |
45438a0c FB |
988 | if (!tmp) |
989 | tmp = DWC3_TRB_NUM - 1; | |
361572b5 | 990 | |
45438a0c | 991 | return &dep->trb_pool[tmp - 1]; |
361572b5 JY |
992 | } |
993 | ||
c4233573 FB |
994 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) |
995 | { | |
996 | struct dwc3_trb *tmp; | |
32db3d94 | 997 | u8 trbs_left; |
c4233573 FB |
998 | |
999 | /* | |
1000 | * If enqueue & dequeue are equal than it is either full or empty. | |
1001 | * | |
1002 | * One way to know for sure is if the TRB right before us has HWO bit | |
1003 | * set or not. If it has, then we're definitely full and can't fit any | |
1004 | * more transfers in our ring. | |
1005 | */ | |
1006 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
361572b5 | 1007 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); |
202adafe | 1008 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) |
361572b5 | 1009 | return 0; |
c4233573 FB |
1010 | |
1011 | return DWC3_TRB_NUM - 1; | |
1012 | } | |
1013 | ||
9d7aba77 | 1014 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; |
3de2685f | 1015 | trbs_left &= (DWC3_TRB_NUM - 1); |
32db3d94 | 1016 | |
9d7aba77 JY |
1017 | if (dep->trb_dequeue < dep->trb_enqueue) |
1018 | trbs_left--; | |
1019 | ||
32db3d94 | 1020 | return trbs_left; |
c4233573 FB |
1021 | } |
1022 | ||
5ee85d89 | 1023 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 1024 | struct dwc3_request *req) |
5ee85d89 | 1025 | { |
1f512119 | 1026 | struct scatterlist *sg = req->sg; |
5ee85d89 | 1027 | struct scatterlist *s; |
5ee85d89 FB |
1028 | int i; |
1029 | ||
1f512119 | 1030 | for_each_sg(sg, s, req->num_pending_sgs, i) { |
c6267a51 FB |
1031 | unsigned int length = req->request.length; |
1032 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1033 | unsigned int rem = length % maxp; | |
5ee85d89 FB |
1034 | unsigned chain = true; |
1035 | ||
4bc48c97 | 1036 | if (sg_is_last(s)) |
5ee85d89 FB |
1037 | chain = false; |
1038 | ||
c6267a51 FB |
1039 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { |
1040 | struct dwc3 *dwc = dep->dwc; | |
1041 | struct dwc3_trb *trb; | |
1042 | ||
1043 | req->unaligned = true; | |
1044 | ||
1045 | /* prepare normal TRB */ | |
1046 | dwc3_prepare_one_trb(dep, req, true, i); | |
1047 | ||
1048 | /* Now prepare one extra TRB to align transfer size */ | |
1049 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1050 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, | |
1051 | maxp - rem, false, 0, | |
1052 | req->request.stream_id, | |
1053 | req->request.short_not_ok, | |
1054 | req->request.no_interrupt); | |
1055 | } else { | |
1056 | dwc3_prepare_one_trb(dep, req, chain, i); | |
1057 | } | |
5ee85d89 | 1058 | |
7ae7df49 | 1059 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
1060 | break; |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 1065 | struct dwc3_request *req) |
5ee85d89 | 1066 | { |
c6267a51 FB |
1067 | unsigned int length = req->request.length; |
1068 | unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); | |
1069 | unsigned int rem = length % maxp; | |
1070 | ||
1071 | if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) { | |
1072 | struct dwc3 *dwc = dep->dwc; | |
1073 | struct dwc3_trb *trb; | |
1074 | ||
1075 | req->unaligned = true; | |
1076 | ||
1077 | /* prepare normal TRB */ | |
1078 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1079 | ||
1080 | /* Now prepare one extra TRB to align transfer size */ | |
1081 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1082 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, | |
1083 | false, 0, req->request.stream_id, | |
1084 | req->request.short_not_ok, | |
1085 | req->request.no_interrupt); | |
d6e5a549 FB |
1086 | } else if (req->request.zero && req->request.length && |
1087 | (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) { | |
1088 | struct dwc3 *dwc = dep->dwc; | |
1089 | struct dwc3_trb *trb; | |
1090 | ||
1091 | req->zero = true; | |
1092 | ||
1093 | /* prepare normal TRB */ | |
1094 | dwc3_prepare_one_trb(dep, req, true, 0); | |
1095 | ||
1096 | /* Now prepare one extra TRB to handle ZLP */ | |
1097 | trb = &dep->trb_pool[dep->trb_enqueue]; | |
1098 | __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, | |
1099 | false, 0, req->request.stream_id, | |
1100 | req->request.short_not_ok, | |
1101 | req->request.no_interrupt); | |
c6267a51 FB |
1102 | } else { |
1103 | dwc3_prepare_one_trb(dep, req, false, 0); | |
1104 | } | |
5ee85d89 FB |
1105 | } |
1106 | ||
72246da4 FB |
1107 | /* |
1108 | * dwc3_prepare_trbs - setup TRBs from requests | |
1109 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1110 | * |
1d046793 PZ |
1111 | * The function goes through the requests list and sets up TRBs for the |
1112 | * transfers. The function returns once there are no more TRBs available or | |
1113 | * it runs out of requests. | |
72246da4 | 1114 | */ |
c4233573 | 1115 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1116 | { |
68e823e2 | 1117 | struct dwc3_request *req, *n; |
72246da4 FB |
1118 | |
1119 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1120 | ||
7ae7df49 | 1121 | if (!dwc3_calc_trbs_left(dep)) |
89bc856e | 1122 | return; |
72246da4 | 1123 | |
d86c5a67 FB |
1124 | /* |
1125 | * We can get in a situation where there's a request in the started list | |
1126 | * but there weren't enough TRBs to fully kick it in the first time | |
1127 | * around, so it has been waiting for more TRBs to be freed up. | |
1128 | * | |
1129 | * In that case, we should check if we have a request with pending_sgs | |
1130 | * in the started list and prepare TRBs for that request first, | |
1131 | * otherwise we will prepare TRBs completely out of order and that will | |
1132 | * break things. | |
1133 | */ | |
1134 | list_for_each_entry(req, &dep->started_list, list) { | |
1135 | if (req->num_pending_sgs > 0) | |
1136 | dwc3_prepare_one_trb_sg(dep, req); | |
1137 | ||
1138 | if (!dwc3_calc_trbs_left(dep)) | |
1139 | return; | |
1140 | } | |
1141 | ||
aa3342c8 | 1142 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
cdb55b39 FB |
1143 | struct dwc3 *dwc = dep->dwc; |
1144 | int ret; | |
1145 | ||
1146 | ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, | |
1147 | dep->direction); | |
1148 | if (ret) | |
1149 | return; | |
1150 | ||
1151 | req->sg = req->request.sg; | |
1152 | req->num_pending_sgs = req->request.num_mapped_sgs; | |
1153 | ||
1f512119 | 1154 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1155 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1156 | else |
7ae7df49 | 1157 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1158 | |
7ae7df49 | 1159 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1160 | return; |
72246da4 | 1161 | } |
72246da4 FB |
1162 | } |
1163 | ||
4fae2e3e | 1164 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) |
72246da4 FB |
1165 | { |
1166 | struct dwc3_gadget_ep_cmd_params params; | |
1167 | struct dwc3_request *req; | |
4fae2e3e | 1168 | int starting; |
72246da4 FB |
1169 | int ret; |
1170 | u32 cmd; | |
1171 | ||
4fae2e3e | 1172 | starting = !(dep->flags & DWC3_EP_BUSY); |
72246da4 | 1173 | |
4fae2e3e FB |
1174 | dwc3_prepare_trbs(dep); |
1175 | req = next_request(&dep->started_list); | |
72246da4 FB |
1176 | if (!req) { |
1177 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1182 | |
4fae2e3e | 1183 | if (starting) { |
1877d6c9 PA |
1184 | params.param0 = upper_32_bits(req->trb_dma); |
1185 | params.param1 = lower_32_bits(req->trb_dma); | |
b6b1c6db FB |
1186 | cmd = DWC3_DEPCMD_STARTTRANSFER | |
1187 | DWC3_DEPCMD_PARAM(cmd_param); | |
1877d6c9 | 1188 | } else { |
b6b1c6db FB |
1189 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1190 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1191 | } |
72246da4 | 1192 | |
2cd4718d | 1193 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1194 | if (ret < 0) { |
72246da4 FB |
1195 | /* |
1196 | * FIXME we need to iterate over the list of requests | |
1197 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1198 | * requests instead of what we do now. |
72246da4 | 1199 | */ |
ce3fc8b3 JD |
1200 | if (req->trb) |
1201 | memset(req->trb, 0, sizeof(struct dwc3_trb)); | |
8ab89da4 | 1202 | dep->queued_requests--; |
15b8d933 | 1203 | dwc3_gadget_giveback(dep, req, ret); |
72246da4 FB |
1204 | return ret; |
1205 | } | |
1206 | ||
1207 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1208 | |
4fae2e3e | 1209 | if (starting) { |
2eb88016 | 1210 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
b4996a86 | 1211 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1212 | } |
25b8ff68 | 1213 | |
72246da4 FB |
1214 | return 0; |
1215 | } | |
1216 | ||
6cb2e4e3 FB |
1217 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1218 | { | |
1219 | u32 reg; | |
1220 | ||
1221 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1222 | return DWC3_DSTS_SOFFN(reg); | |
1223 | } | |
1224 | ||
d6d6ec7b PA |
1225 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1226 | struct dwc3_ep *dep, u32 cur_uf) | |
1227 | { | |
1228 | u32 uf; | |
1229 | ||
aa3342c8 | 1230 | if (list_empty(&dep->pending_list)) { |
5eb30ced | 1231 | dev_info(dwc->dev, "%s: ran out of requests\n", |
73815280 | 1232 | dep->name); |
f4a53c55 | 1233 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1234 | return; |
1235 | } | |
1236 | ||
af771d73 JY |
1237 | /* |
1238 | * Schedule the first trb for one interval in the future or at | |
1239 | * least 4 microframes. | |
1240 | */ | |
1241 | uf = cur_uf + max_t(u32, 4, dep->interval); | |
d6d6ec7b | 1242 | |
4fae2e3e | 1243 | __dwc3_gadget_kick_transfer(dep, uf); |
d6d6ec7b PA |
1244 | } |
1245 | ||
1246 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1247 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1248 | { | |
1249 | u32 cur_uf, mask; | |
1250 | ||
1251 | mask = ~(dep->interval - 1); | |
1252 | cur_uf = event->parameters & mask; | |
1253 | ||
1254 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1255 | } | |
1256 | ||
72246da4 FB |
1257 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1258 | { | |
0fc9a1be | 1259 | struct dwc3 *dwc = dep->dwc; |
cdb55b39 | 1260 | int ret = 0; |
0fc9a1be | 1261 | |
bb423984 | 1262 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1263 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1264 | dep->name); | |
bb423984 FB |
1265 | return -ESHUTDOWN; |
1266 | } | |
1267 | ||
04fb365c FB |
1268 | if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", |
1269 | &req->request, req->dep->name)) | |
bb423984 | 1270 | return -EINVAL; |
bb423984 | 1271 | |
fc8bb91b FB |
1272 | pm_runtime_get(dwc->dev); |
1273 | ||
72246da4 FB |
1274 | req->request.actual = 0; |
1275 | req->request.status = -EINPROGRESS; | |
1276 | req->direction = dep->direction; | |
1277 | req->epnum = dep->number; | |
1278 | ||
fe84f522 FB |
1279 | trace_dwc3_ep_queue(req); |
1280 | ||
aa3342c8 | 1281 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1282 | |
d889c23c FB |
1283 | /* |
1284 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1285 | * wait for a XferNotReady event so we will know what's the current | |
1286 | * (micro-)frame number. | |
1287 | * | |
1288 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1289 | * errors which will force us issue EndTransfer command. | |
1290 | */ | |
1291 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
6cb2e4e3 FB |
1292 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
1293 | if (dep->flags & DWC3_EP_TRANSFER_STARTED) { | |
1294 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
1295 | dep->flags = DWC3_EP_ENABLED; | |
1296 | } else { | |
1297 | u32 cur_uf; | |
1298 | ||
1299 | cur_uf = __dwc3_gadget_get_frame(dwc); | |
1300 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
87aba106 | 1301 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; |
6cb2e4e3 | 1302 | } |
08a36b54 FB |
1303 | } |
1304 | return 0; | |
a0925324 | 1305 | } |
72246da4 | 1306 | |
594e121f FB |
1307 | if (!dwc3_calc_trbs_left(dep)) |
1308 | return 0; | |
b997ada5 | 1309 | |
08a36b54 | 1310 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
a8f32817 FB |
1311 | if (ret == -EBUSY) |
1312 | ret = 0; | |
1313 | ||
1314 | return ret; | |
72246da4 FB |
1315 | } |
1316 | ||
1317 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1318 | gfp_t gfp_flags) | |
1319 | { | |
1320 | struct dwc3_request *req = to_dwc3_request(request); | |
1321 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1322 | struct dwc3 *dwc = dep->dwc; | |
1323 | ||
1324 | unsigned long flags; | |
1325 | ||
1326 | int ret; | |
1327 | ||
fdee4eba | 1328 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1329 | ret = __dwc3_gadget_ep_queue(dep, req); |
1330 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1331 | ||
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1336 | struct usb_request *request) | |
1337 | { | |
1338 | struct dwc3_request *req = to_dwc3_request(request); | |
1339 | struct dwc3_request *r = NULL; | |
1340 | ||
1341 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1342 | struct dwc3 *dwc = dep->dwc; | |
1343 | ||
1344 | unsigned long flags; | |
1345 | int ret = 0; | |
1346 | ||
2c4cbe6e FB |
1347 | trace_dwc3_ep_dequeue(req); |
1348 | ||
72246da4 FB |
1349 | spin_lock_irqsave(&dwc->lock, flags); |
1350 | ||
aa3342c8 | 1351 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1352 | if (r == req) |
1353 | break; | |
1354 | } | |
1355 | ||
1356 | if (r != req) { | |
aa3342c8 | 1357 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1358 | if (r == req) |
1359 | break; | |
1360 | } | |
1361 | if (r == req) { | |
1362 | /* wait until it is processed */ | |
b992e681 | 1363 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cf3113d8 FB |
1364 | |
1365 | /* | |
1366 | * If request was already started, this means we had to | |
1367 | * stop the transfer. With that we also need to ignore | |
1368 | * all TRBs used by the request, however TRBs can only | |
1369 | * be modified after completion of END_TRANSFER | |
1370 | * command. So what we do here is that we wait for | |
1371 | * END_TRANSFER completion and only after that, we jump | |
1372 | * over TRBs by clearing HWO and incrementing dequeue | |
1373 | * pointer. | |
1374 | * | |
1375 | * Note that we have 2 possible types of transfers here: | |
1376 | * | |
1377 | * i) Linear buffer request | |
1378 | * ii) SG-list based request | |
1379 | * | |
1380 | * SG-list based requests will have r->num_pending_sgs | |
1381 | * set to a valid number (> 0). Linear requests, | |
1382 | * normally use a single TRB. | |
1383 | * | |
1384 | * For each of these two cases, if r->unaligned flag is | |
1385 | * set, one extra TRB has been used to align transfer | |
1386 | * size to wMaxPacketSize. | |
1387 | * | |
1388 | * All of these cases need to be taken into | |
1389 | * consideration so we don't mess up our TRB ring | |
1390 | * pointers. | |
1391 | */ | |
1392 | wait_event_lock_irq(dep->wait_end_transfer, | |
1393 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING), | |
1394 | dwc->lock); | |
1395 | ||
1396 | if (!r->trb) | |
1397 | goto out1; | |
1398 | ||
1399 | if (r->num_pending_sgs) { | |
1400 | struct dwc3_trb *trb; | |
1401 | int i = 0; | |
1402 | ||
1403 | for (i = 0; i < r->num_pending_sgs; i++) { | |
1404 | trb = r->trb + i; | |
1405 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1406 | dwc3_ep_inc_deq(dep); | |
1407 | } | |
1408 | ||
d6e5a549 | 1409 | if (r->unaligned || r->zero) { |
cf3113d8 FB |
1410 | trb = r->trb + r->num_pending_sgs + 1; |
1411 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1412 | dwc3_ep_inc_deq(dep); | |
1413 | } | |
1414 | } else { | |
1415 | struct dwc3_trb *trb = r->trb; | |
1416 | ||
1417 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1418 | dwc3_ep_inc_deq(dep); | |
1419 | ||
d6e5a549 | 1420 | if (r->unaligned || r->zero) { |
cf3113d8 FB |
1421 | trb = r->trb + 1; |
1422 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
1423 | dwc3_ep_inc_deq(dep); | |
1424 | } | |
1425 | } | |
e8d4e8be | 1426 | goto out1; |
72246da4 | 1427 | } |
04fb365c | 1428 | dev_err(dwc->dev, "request %pK was not queued to %s\n", |
72246da4 FB |
1429 | request, ep->name); |
1430 | ret = -EINVAL; | |
1431 | goto out0; | |
1432 | } | |
1433 | ||
e8d4e8be | 1434 | out1: |
72246da4 | 1435 | /* giveback the request */ |
cf3113d8 | 1436 | dep->queued_requests--; |
72246da4 FB |
1437 | dwc3_gadget_giveback(dep, req, -ECONNRESET); |
1438 | ||
1439 | out0: | |
1440 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1441 | ||
1442 | return ret; | |
1443 | } | |
1444 | ||
7a608559 | 1445 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1446 | { |
1447 | struct dwc3_gadget_ep_cmd_params params; | |
1448 | struct dwc3 *dwc = dep->dwc; | |
1449 | int ret; | |
1450 | ||
5ad02fb8 FB |
1451 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1452 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1453 | return -EINVAL; | |
1454 | } | |
1455 | ||
72246da4 FB |
1456 | memset(¶ms, 0x00, sizeof(params)); |
1457 | ||
1458 | if (value) { | |
69450c4d FB |
1459 | struct dwc3_trb *trb; |
1460 | ||
1461 | unsigned transfer_in_flight; | |
1462 | unsigned started; | |
1463 | ||
ffb80fc6 FB |
1464 | if (dep->flags & DWC3_EP_STALL) |
1465 | return 0; | |
1466 | ||
69450c4d FB |
1467 | if (dep->number > 1) |
1468 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1469 | else | |
1470 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1471 | ||
1472 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1473 | started = !list_empty(&dep->started_list); | |
1474 | ||
1475 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1476 | (!dep->direction && started))) { | |
7a608559 FB |
1477 | return -EAGAIN; |
1478 | } | |
1479 | ||
2cd4718d FB |
1480 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1481 | ¶ms); | |
72246da4 | 1482 | if (ret) |
3f89204b | 1483 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1484 | dep->name); |
1485 | else | |
1486 | dep->flags |= DWC3_EP_STALL; | |
1487 | } else { | |
ffb80fc6 FB |
1488 | if (!(dep->flags & DWC3_EP_STALL)) |
1489 | return 0; | |
2cd4718d | 1490 | |
50c763f8 | 1491 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1492 | if (ret) |
3f89204b | 1493 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1494 | dep->name); |
1495 | else | |
a535d81c | 1496 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1497 | } |
5275455a | 1498 | |
72246da4 FB |
1499 | return ret; |
1500 | } | |
1501 | ||
1502 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1503 | { | |
1504 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1505 | struct dwc3 *dwc = dep->dwc; | |
1506 | ||
1507 | unsigned long flags; | |
1508 | ||
1509 | int ret; | |
1510 | ||
1511 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1512 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1513 | spin_unlock_irqrestore(&dwc->lock, flags); |
1514 | ||
1515 | return ret; | |
1516 | } | |
1517 | ||
1518 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1519 | { | |
1520 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1521 | struct dwc3 *dwc = dep->dwc; |
1522 | unsigned long flags; | |
95aa4e8d | 1523 | int ret; |
72246da4 | 1524 | |
249a4569 | 1525 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1526 | dep->flags |= DWC3_EP_WEDGE; |
1527 | ||
08f0d966 | 1528 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1529 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1530 | else |
7a608559 | 1531 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1532 | spin_unlock_irqrestore(&dwc->lock, flags); |
1533 | ||
1534 | return ret; | |
72246da4 FB |
1535 | } |
1536 | ||
1537 | /* -------------------------------------------------------------------------- */ | |
1538 | ||
1539 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1540 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1541 | .bDescriptorType = USB_DT_ENDPOINT, | |
1542 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1543 | }; | |
1544 | ||
1545 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1546 | .enable = dwc3_gadget_ep0_enable, | |
1547 | .disable = dwc3_gadget_ep0_disable, | |
1548 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1549 | .free_request = dwc3_gadget_ep_free_request, | |
1550 | .queue = dwc3_gadget_ep0_queue, | |
1551 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1552 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1553 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1554 | }; | |
1555 | ||
1556 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1557 | .enable = dwc3_gadget_ep_enable, | |
1558 | .disable = dwc3_gadget_ep_disable, | |
1559 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1560 | .free_request = dwc3_gadget_ep_free_request, | |
1561 | .queue = dwc3_gadget_ep_queue, | |
1562 | .dequeue = dwc3_gadget_ep_dequeue, | |
1563 | .set_halt = dwc3_gadget_ep_set_halt, | |
1564 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1565 | }; | |
1566 | ||
1567 | /* -------------------------------------------------------------------------- */ | |
1568 | ||
1569 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1570 | { | |
1571 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1572 | |
6cb2e4e3 | 1573 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1574 | } |
1575 | ||
218ef7b6 | 1576 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1577 | { |
d6011f6f | 1578 | int retries; |
72246da4 | 1579 | |
218ef7b6 | 1580 | int ret; |
72246da4 FB |
1581 | u32 reg; |
1582 | ||
72246da4 FB |
1583 | u8 link_state; |
1584 | u8 speed; | |
1585 | ||
72246da4 FB |
1586 | /* |
1587 | * According to the Databook Remote wakeup request should | |
1588 | * be issued only when the device is in early suspend state. | |
1589 | * | |
1590 | * We can check that via USB Link State bits in DSTS register. | |
1591 | */ | |
1592 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1593 | ||
1594 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c | 1595 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
5eb30ced | 1596 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) |
6b742899 | 1597 | return 0; |
72246da4 FB |
1598 | |
1599 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1600 | ||
1601 | switch (link_state) { | |
1602 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1603 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1604 | break; | |
1605 | default: | |
218ef7b6 | 1606 | return -EINVAL; |
72246da4 FB |
1607 | } |
1608 | ||
8598bde7 FB |
1609 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1610 | if (ret < 0) { | |
1611 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1612 | return ret; |
8598bde7 | 1613 | } |
72246da4 | 1614 | |
802fde98 PZ |
1615 | /* Recent versions do this automatically */ |
1616 | if (dwc->revision < DWC3_REVISION_194A) { | |
1617 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1618 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1619 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1620 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1621 | } | |
72246da4 | 1622 | |
1d046793 | 1623 | /* poll until Link State changes to ON */ |
d6011f6f | 1624 | retries = 20000; |
72246da4 | 1625 | |
d6011f6f | 1626 | while (retries--) { |
72246da4 FB |
1627 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1628 | ||
1629 | /* in HS, means ON */ | |
1630 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1631 | break; | |
1632 | } | |
1633 | ||
1634 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1635 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1636 | return -EINVAL; |
72246da4 FB |
1637 | } |
1638 | ||
218ef7b6 FB |
1639 | return 0; |
1640 | } | |
1641 | ||
1642 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1643 | { | |
1644 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1645 | unsigned long flags; | |
1646 | int ret; | |
1647 | ||
1648 | spin_lock_irqsave(&dwc->lock, flags); | |
1649 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1650 | spin_unlock_irqrestore(&dwc->lock, flags); |
1651 | ||
1652 | return ret; | |
1653 | } | |
1654 | ||
1655 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1656 | int is_selfpowered) | |
1657 | { | |
1658 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1659 | unsigned long flags; |
72246da4 | 1660 | |
249a4569 | 1661 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1662 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1663 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1664 | |
1665 | return 0; | |
1666 | } | |
1667 | ||
7b2a0368 | 1668 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1669 | { |
1670 | u32 reg; | |
61d58242 | 1671 | u32 timeout = 500; |
72246da4 | 1672 | |
fc8bb91b FB |
1673 | if (pm_runtime_suspended(dwc->dev)) |
1674 | return 0; | |
1675 | ||
72246da4 | 1676 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1677 | if (is_on) { |
802fde98 PZ |
1678 | if (dwc->revision <= DWC3_REVISION_187A) { |
1679 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1680 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1681 | } | |
1682 | ||
1683 | if (dwc->revision >= DWC3_REVISION_194A) | |
1684 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1685 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1686 | |
1687 | if (dwc->has_hibernation) | |
1688 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1689 | ||
9fcb3bd8 | 1690 | dwc->pullups_connected = true; |
8db7ed15 | 1691 | } else { |
72246da4 | 1692 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1693 | |
1694 | if (dwc->has_hibernation && !suspend) | |
1695 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1696 | ||
9fcb3bd8 | 1697 | dwc->pullups_connected = false; |
8db7ed15 | 1698 | } |
72246da4 FB |
1699 | |
1700 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1701 | ||
1702 | do { | |
1703 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1704 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1705 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1706 | |
1707 | if (!timeout) | |
1708 | return -ETIMEDOUT; | |
72246da4 | 1709 | |
6f17f74b | 1710 | return 0; |
72246da4 FB |
1711 | } |
1712 | ||
1713 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1714 | { | |
1715 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1716 | unsigned long flags; | |
6f17f74b | 1717 | int ret; |
72246da4 FB |
1718 | |
1719 | is_on = !!is_on; | |
1720 | ||
bb014736 BW |
1721 | /* |
1722 | * Per databook, when we want to stop the gadget, if a control transfer | |
1723 | * is still in process, complete it and get the core into setup phase. | |
1724 | */ | |
1725 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1726 | reinit_completion(&dwc->ep0_in_setup); | |
1727 | ||
1728 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1729 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1730 | if (ret == 0) { | |
1731 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1732 | return -ETIMEDOUT; | |
1733 | } | |
1734 | } | |
1735 | ||
72246da4 | 1736 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1737 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1738 | spin_unlock_irqrestore(&dwc->lock, flags); |
1739 | ||
6f17f74b | 1740 | return ret; |
72246da4 FB |
1741 | } |
1742 | ||
8698e2ac FB |
1743 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1744 | { | |
1745 | u32 reg; | |
1746 | ||
1747 | /* Enable all but Start and End of Frame IRQs */ | |
1748 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1749 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1750 | DWC3_DEVTEN_CMDCMPLTEN | | |
1751 | DWC3_DEVTEN_ERRTICERREN | | |
1752 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1753 | DWC3_DEVTEN_CONNECTDONEEN | |
1754 | DWC3_DEVTEN_USBRSTEN | | |
1755 | DWC3_DEVTEN_DISCONNEVTEN); | |
1756 | ||
799e9dc8 FB |
1757 | if (dwc->revision < DWC3_REVISION_250A) |
1758 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1759 | ||
8698e2ac FB |
1760 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1761 | } | |
1762 | ||
1763 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1764 | { | |
1765 | /* mask all interrupts */ | |
1766 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1767 | } | |
1768 | ||
1769 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1770 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1771 | |
4e99472b | 1772 | /** |
bfad65ee FB |
1773 | * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG |
1774 | * @dwc: pointer to our context structure | |
4e99472b FB |
1775 | * |
1776 | * The following looks like complex but it's actually very simple. In order to | |
1777 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1778 | * gonna use RxFIFO size. | |
1779 | * | |
1780 | * To calculate RxFIFO size we need two numbers: | |
1781 | * MDWIDTH = size, in bits, of the internal memory bus | |
1782 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1783 | * | |
1784 | * Given these two numbers, the formula is simple: | |
1785 | * | |
1786 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1787 | * | |
1788 | * 24 bytes is for 3x SETUP packets | |
1789 | * 16 bytes is a clock domain crossing tolerance | |
1790 | * | |
1791 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1792 | */ | |
1793 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1794 | { | |
1795 | u32 ram2_depth; | |
1796 | u32 mdwidth; | |
1797 | u32 nump; | |
1798 | u32 reg; | |
1799 | ||
1800 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1801 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1802 | ||
1803 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1804 | nump = min_t(u32, nump, 16); | |
1805 | ||
1806 | /* update NumP */ | |
1807 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1808 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1809 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1810 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1811 | } | |
1812 | ||
d7be2952 | 1813 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1814 | { |
72246da4 | 1815 | struct dwc3_ep *dep; |
72246da4 FB |
1816 | int ret = 0; |
1817 | u32 reg; | |
1818 | ||
cf40b86b JY |
1819 | /* |
1820 | * Use IMOD if enabled via dwc->imod_interval. Otherwise, if | |
1821 | * the core supports IMOD, disable it. | |
1822 | */ | |
1823 | if (dwc->imod_interval) { | |
1824 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
1825 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
1826 | } else if (dwc3_has_imod(dwc)) { | |
1827 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); | |
1828 | } | |
1829 | ||
72246da4 FB |
1830 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1831 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b | 1832 | |
bfad65ee | 1833 | /* |
07e7f47b FB |
1834 | * WORKAROUND: DWC3 revision < 2.20a have an issue |
1835 | * which would cause metastability state on Run/Stop | |
1836 | * bit if we try to force the IP to USB2-only mode. | |
1837 | * | |
1838 | * Because of that, we cannot configure the IP to any | |
1839 | * speed other than the SuperSpeed | |
1840 | * | |
1841 | * Refers to: | |
1842 | * | |
1843 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1844 | * USB 2.0 Mode | |
1845 | */ | |
f7e846f0 | 1846 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1847 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1848 | } else { |
1849 | switch (dwc->maximum_speed) { | |
1850 | case USB_SPEED_LOW: | |
2da9ad76 | 1851 | reg |= DWC3_DCFG_LOWSPEED; |
f7e846f0 FB |
1852 | break; |
1853 | case USB_SPEED_FULL: | |
9418ee15 | 1854 | reg |= DWC3_DCFG_FULLSPEED; |
f7e846f0 FB |
1855 | break; |
1856 | case USB_SPEED_HIGH: | |
2da9ad76 | 1857 | reg |= DWC3_DCFG_HIGHSPEED; |
f7e846f0 | 1858 | break; |
7580862b | 1859 | case USB_SPEED_SUPER_PLUS: |
2da9ad76 | 1860 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; |
7580862b | 1861 | break; |
f7e846f0 | 1862 | default: |
77966eb8 JY |
1863 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1864 | dwc->maximum_speed); | |
1865 | /* fall through */ | |
1866 | case USB_SPEED_SUPER: | |
1867 | reg |= DWC3_DCFG_SUPERSPEED; | |
1868 | break; | |
f7e846f0 FB |
1869 | } |
1870 | } | |
72246da4 FB |
1871 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1872 | ||
2a58f9c1 FB |
1873 | /* |
1874 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1875 | * field instead of letting dwc3 itself calculate that automatically. | |
1876 | * | |
1877 | * This way, we maximize the chances that we'll be able to get several | |
1878 | * bursts of data without going through any sort of endpoint throttling. | |
1879 | */ | |
1880 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1881 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1882 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1883 | ||
4e99472b FB |
1884 | dwc3_gadget_setup_nump(dwc); |
1885 | ||
72246da4 FB |
1886 | /* Start with SuperSpeed Default */ |
1887 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1888 | ||
1889 | dep = dwc->eps[0]; | |
39ebb05c | 1890 | ret = __dwc3_gadget_ep_enable(dep, false, false); |
72246da4 FB |
1891 | if (ret) { |
1892 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1893 | goto err0; |
72246da4 FB |
1894 | } |
1895 | ||
1896 | dep = dwc->eps[1]; | |
39ebb05c | 1897 | ret = __dwc3_gadget_ep_enable(dep, false, false); |
72246da4 FB |
1898 | if (ret) { |
1899 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1900 | goto err1; |
72246da4 FB |
1901 | } |
1902 | ||
1903 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1904 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1905 | dwc3_ep0_out_start(dwc); |
1906 | ||
8698e2ac FB |
1907 | dwc3_gadget_enable_irq(dwc); |
1908 | ||
72246da4 FB |
1909 | return 0; |
1910 | ||
b0d7ffd4 | 1911 | err1: |
d7be2952 | 1912 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1913 | |
1914 | err0: | |
72246da4 FB |
1915 | return ret; |
1916 | } | |
1917 | ||
d7be2952 FB |
1918 | static int dwc3_gadget_start(struct usb_gadget *g, |
1919 | struct usb_gadget_driver *driver) | |
72246da4 FB |
1920 | { |
1921 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1922 | unsigned long flags; | |
d7be2952 | 1923 | int ret = 0; |
8698e2ac | 1924 | int irq; |
72246da4 | 1925 | |
9522def4 | 1926 | irq = dwc->irq_gadget; |
d7be2952 FB |
1927 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
1928 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1929 | if (ret) { | |
1930 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1931 | irq, ret); | |
1932 | goto err0; | |
1933 | } | |
1934 | ||
72246da4 | 1935 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
1936 | if (dwc->gadget_driver) { |
1937 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1938 | dwc->gadget.name, | |
1939 | dwc->gadget_driver->driver.name); | |
1940 | ret = -EBUSY; | |
1941 | goto err1; | |
1942 | } | |
1943 | ||
1944 | dwc->gadget_driver = driver; | |
1945 | ||
fc8bb91b FB |
1946 | if (pm_runtime_active(dwc->dev)) |
1947 | __dwc3_gadget_start(dwc); | |
1948 | ||
d7be2952 FB |
1949 | spin_unlock_irqrestore(&dwc->lock, flags); |
1950 | ||
1951 | return 0; | |
1952 | ||
1953 | err1: | |
1954 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1955 | free_irq(irq, dwc); | |
1956 | ||
1957 | err0: | |
1958 | return ret; | |
1959 | } | |
72246da4 | 1960 | |
d7be2952 FB |
1961 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
1962 | { | |
8698e2ac | 1963 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1964 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1965 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 1966 | } |
72246da4 | 1967 | |
d7be2952 FB |
1968 | static int dwc3_gadget_stop(struct usb_gadget *g) |
1969 | { | |
1970 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1971 | unsigned long flags; | |
76a638f8 | 1972 | int epnum; |
72246da4 | 1973 | |
d7be2952 | 1974 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
1975 | |
1976 | if (pm_runtime_suspended(dwc->dev)) | |
1977 | goto out; | |
1978 | ||
d7be2952 | 1979 | __dwc3_gadget_stop(dwc); |
76a638f8 BW |
1980 | |
1981 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1982 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
1983 | ||
1984 | if (!dep) | |
1985 | continue; | |
1986 | ||
1987 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1988 | continue; | |
1989 | ||
1990 | wait_event_lock_irq(dep->wait_end_transfer, | |
1991 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING), | |
1992 | dwc->lock); | |
1993 | } | |
1994 | ||
1995 | out: | |
d7be2952 | 1996 | dwc->gadget_driver = NULL; |
72246da4 FB |
1997 | spin_unlock_irqrestore(&dwc->lock, flags); |
1998 | ||
3f308d17 | 1999 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 2000 | |
72246da4 FB |
2001 | return 0; |
2002 | } | |
802fde98 | 2003 | |
72246da4 FB |
2004 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
2005 | .get_frame = dwc3_gadget_get_frame, | |
2006 | .wakeup = dwc3_gadget_wakeup, | |
2007 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
2008 | .pullup = dwc3_gadget_pullup, | |
2009 | .udc_start = dwc3_gadget_start, | |
2010 | .udc_stop = dwc3_gadget_stop, | |
2011 | }; | |
2012 | ||
2013 | /* -------------------------------------------------------------------------- */ | |
2014 | ||
f3bcfc7e | 2015 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num) |
72246da4 FB |
2016 | { |
2017 | struct dwc3_ep *dep; | |
47d3946e | 2018 | u8 epnum; |
72246da4 | 2019 | |
f3bcfc7e BD |
2020 | INIT_LIST_HEAD(&dwc->gadget.ep_list); |
2021 | ||
47d3946e BD |
2022 | for (epnum = 0; epnum < num; epnum++) { |
2023 | bool direction = epnum & 1; | |
72246da4 | 2024 | |
72246da4 | 2025 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 2026 | if (!dep) |
72246da4 | 2027 | return -ENOMEM; |
72246da4 FB |
2028 | |
2029 | dep->dwc = dwc; | |
2030 | dep->number = epnum; | |
47d3946e | 2031 | dep->direction = direction; |
2eb88016 | 2032 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); |
72246da4 FB |
2033 | dwc->eps[epnum] = dep; |
2034 | ||
2035 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
47d3946e | 2036 | direction ? "in" : "out"); |
6a1e3ef4 | 2037 | |
72246da4 | 2038 | dep->endpoint.name = dep->name; |
39ebb05c JY |
2039 | |
2040 | if (!(dep->number > 1)) { | |
2041 | dep->endpoint.desc = &dwc3_gadget_ep0_desc; | |
2042 | dep->endpoint.comp_desc = NULL; | |
2043 | } | |
2044 | ||
74674cbf | 2045 | spin_lock_init(&dep->lock); |
72246da4 FB |
2046 | |
2047 | if (epnum == 0 || epnum == 1) { | |
e117e742 | 2048 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 2049 | dep->endpoint.maxburst = 1; |
72246da4 FB |
2050 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
2051 | if (!epnum) | |
2052 | dwc->gadget.ep0 = &dep->endpoint; | |
28781789 FB |
2053 | } else if (direction) { |
2054 | int mdwidth; | |
2055 | int size; | |
2056 | int ret; | |
2057 | int num; | |
2058 | ||
2059 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
2060 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
2061 | mdwidth /= 8; | |
2062 | ||
47d3946e | 2063 | size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1)); |
28781789 FB |
2064 | size = DWC3_GTXFIFOSIZ_TXFDEF(size); |
2065 | ||
2066 | /* FIFO Depth is in MDWDITH bytes. Multiply */ | |
2067 | size *= mdwidth; | |
2068 | ||
2069 | num = size / 1024; | |
2070 | if (num == 0) | |
2071 | num = 1; | |
2072 | ||
2073 | /* | |
2074 | * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for | |
2075 | * internal overhead. We don't really know how these are used, | |
2076 | * but documentation say it exists. | |
2077 | */ | |
2078 | size -= mdwidth * (num + 1); | |
2079 | size /= num; | |
2080 | ||
2081 | usb_ep_set_maxpacket_limit(&dep->endpoint, size); | |
2082 | ||
2083 | dep->endpoint.max_streams = 15; | |
2084 | dep->endpoint.ops = &dwc3_gadget_ep_ops; | |
2085 | list_add_tail(&dep->endpoint.ep_list, | |
2086 | &dwc->gadget.ep_list); | |
2087 | ||
2088 | ret = dwc3_alloc_trb_pool(dep); | |
2089 | if (ret) | |
2090 | return ret; | |
72246da4 FB |
2091 | } else { |
2092 | int ret; | |
2093 | ||
e117e742 | 2094 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 2095 | dep->endpoint.max_streams = 15; |
72246da4 FB |
2096 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
2097 | list_add_tail(&dep->endpoint.ep_list, | |
2098 | &dwc->gadget.ep_list); | |
2099 | ||
2100 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 2101 | if (ret) |
72246da4 | 2102 | return ret; |
72246da4 | 2103 | } |
25b8ff68 | 2104 | |
a474d3b7 RB |
2105 | if (epnum == 0 || epnum == 1) { |
2106 | dep->endpoint.caps.type_control = true; | |
2107 | } else { | |
2108 | dep->endpoint.caps.type_iso = true; | |
2109 | dep->endpoint.caps.type_bulk = true; | |
2110 | dep->endpoint.caps.type_int = true; | |
2111 | } | |
2112 | ||
47d3946e | 2113 | dep->endpoint.caps.dir_in = direction; |
a474d3b7 RB |
2114 | dep->endpoint.caps.dir_out = !direction; |
2115 | ||
aa3342c8 FB |
2116 | INIT_LIST_HEAD(&dep->pending_list); |
2117 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
2118 | } |
2119 | ||
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
2124 | { | |
2125 | struct dwc3_ep *dep; | |
2126 | u8 epnum; | |
2127 | ||
2128 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2129 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2130 | if (!dep) |
2131 | continue; | |
5bf8fae3 GC |
2132 | /* |
2133 | * Physical endpoints 0 and 1 are special; they form the | |
2134 | * bi-directional USB endpoint 0. | |
2135 | * | |
2136 | * For those two physical endpoints, we don't allocate a TRB | |
2137 | * pool nor do we add them the endpoints list. Due to that, we | |
2138 | * shouldn't do these two operations otherwise we would end up | |
2139 | * with all sorts of bugs when removing dwc3.ko. | |
2140 | */ | |
2141 | if (epnum != 0 && epnum != 1) { | |
2142 | dwc3_free_trb_pool(dep); | |
72246da4 | 2143 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 2144 | } |
72246da4 FB |
2145 | |
2146 | kfree(dep); | |
2147 | } | |
2148 | } | |
2149 | ||
72246da4 | 2150 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 2151 | |
e5ba5ec8 PA |
2152 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
2153 | struct dwc3_request *req, struct dwc3_trb *trb, | |
e5b36ae2 FB |
2154 | const struct dwc3_event_depevt *event, int status, |
2155 | int chain) | |
72246da4 | 2156 | { |
72246da4 FB |
2157 | unsigned int count; |
2158 | unsigned int s_pkt = 0; | |
d6d6ec7b | 2159 | unsigned int trb_status; |
72246da4 | 2160 | |
dc55c67e | 2161 | dwc3_ep_inc_deq(dep); |
a9c3ca5f FB |
2162 | |
2163 | if (req->trb == trb) | |
2164 | dep->queued_requests--; | |
2165 | ||
2c4cbe6e FB |
2166 | trace_dwc3_complete_trb(dep, trb); |
2167 | ||
e5b36ae2 FB |
2168 | /* |
2169 | * If we're in the middle of series of chained TRBs and we | |
2170 | * receive a short transfer along the way, DWC3 will skip | |
2171 | * through all TRBs including the last TRB in the chain (the | |
2172 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2173 | * bit and SW has to do it manually. | |
2174 | * | |
2175 | * We're going to do that here to avoid problems of HW trying | |
2176 | * to use bogus TRBs for transfers. | |
2177 | */ | |
2178 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2179 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2180 | ||
c6267a51 FB |
2181 | /* |
2182 | * If we're dealing with unaligned size OUT transfer, we will be left | |
2183 | * with one TRB pending in the ring. We need to manually clear HWO bit | |
2184 | * from that TRB. | |
2185 | */ | |
d6e5a549 | 2186 | if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) { |
c6267a51 FB |
2187 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
2188 | return 1; | |
2189 | } | |
2190 | ||
e5ba5ec8 | 2191 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2192 | req->remaining += count; |
e5ba5ec8 | 2193 | |
35b2719e FB |
2194 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
2195 | return 1; | |
2196 | ||
e5ba5ec8 PA |
2197 | if (dep->direction) { |
2198 | if (count) { | |
2199 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
2200 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
e5ba5ec8 PA |
2201 | /* |
2202 | * If missed isoc occurred and there is | |
2203 | * no request queued then issue END | |
2204 | * TRANSFER, so that core generates | |
2205 | * next xfernotready and we will issue | |
2206 | * a fresh START TRANSFER. | |
2207 | * If there are still queued request | |
2208 | * then wait, do not issue either END | |
2209 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 2210 | * request in pending_list during |
e5ba5ec8 PA |
2211 | * giveback.If any future queued request |
2212 | * is successfully transferred then we | |
2213 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 2214 | * request in the pending_list. |
e5ba5ec8 PA |
2215 | */ |
2216 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
2217 | } else { | |
2218 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
2219 | dep->name); | |
2220 | status = -ECONNRESET; | |
2221 | } | |
2222 | } else { | |
2223 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
2224 | } | |
2225 | } else { | |
2226 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
2227 | s_pkt = 1; | |
2228 | } | |
2229 | ||
7c705dfe | 2230 | if (s_pkt && !chain) |
e5ba5ec8 | 2231 | return 1; |
f99f53f2 | 2232 | |
e5ba5ec8 PA |
2233 | if ((event->status & DEPEVT_STATUS_IOC) && |
2234 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2235 | return 1; | |
f99f53f2 | 2236 | |
e5ba5ec8 PA |
2237 | return 0; |
2238 | } | |
2239 | ||
2240 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
2241 | const struct dwc3_event_depevt *event, int status) | |
2242 | { | |
31162af4 | 2243 | struct dwc3_request *req, *n; |
e5ba5ec8 | 2244 | struct dwc3_trb *trb; |
d6e10bf2 | 2245 | bool ioc = false; |
e62c5bc5 | 2246 | int ret = 0; |
e5ba5ec8 | 2247 | |
31162af4 | 2248 | list_for_each_entry_safe(req, n, &dep->started_list, list) { |
1f512119 | 2249 | unsigned length; |
e5b36ae2 FB |
2250 | int chain; |
2251 | ||
1f512119 FB |
2252 | length = req->request.length; |
2253 | chain = req->num_pending_sgs > 0; | |
31162af4 | 2254 | if (chain) { |
1f512119 | 2255 | struct scatterlist *sg = req->sg; |
31162af4 | 2256 | struct scatterlist *s; |
1f512119 | 2257 | unsigned int pending = req->num_pending_sgs; |
31162af4 | 2258 | unsigned int i; |
c7de5734 | 2259 | |
1f512119 | 2260 | for_each_sg(sg, s, pending, i) { |
31162af4 | 2261 | trb = &dep->trb_pool[dep->trb_dequeue]; |
31162af4 | 2262 | |
7282c4ef FB |
2263 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) |
2264 | break; | |
2265 | ||
1f512119 FB |
2266 | req->sg = sg_next(s); |
2267 | req->num_pending_sgs--; | |
2268 | ||
31162af4 FB |
2269 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
2270 | event, status, chain); | |
1f512119 FB |
2271 | if (ret) |
2272 | break; | |
31162af4 FB |
2273 | } |
2274 | } else { | |
737f1ae2 | 2275 | trb = &dep->trb_pool[dep->trb_dequeue]; |
d115d705 | 2276 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
e5b36ae2 | 2277 | event, status, chain); |
31162af4 | 2278 | } |
d115d705 | 2279 | |
d6e5a549 | 2280 | if (req->unaligned || req->zero) { |
c6267a51 FB |
2281 | trb = &dep->trb_pool[dep->trb_dequeue]; |
2282 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, | |
2283 | event, status, false); | |
2284 | req->unaligned = false; | |
d6e5a549 | 2285 | req->zero = false; |
c6267a51 FB |
2286 | } |
2287 | ||
e62c5bc5 | 2288 | req->request.actual = length - req->remaining; |
1f512119 | 2289 | |
ff377ae4 | 2290 | if ((req->request.actual < length) && req->num_pending_sgs) |
1f512119 FB |
2291 | return __dwc3_gadget_kick_transfer(dep, 0); |
2292 | ||
d115d705 | 2293 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 | 2294 | |
d6e10bf2 AB |
2295 | if (ret) { |
2296 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2297 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2298 | ioc = true; | |
72246da4 | 2299 | break; |
d6e10bf2 | 2300 | } |
31162af4 | 2301 | } |
72246da4 | 2302 | |
4cb42217 FB |
2303 | /* |
2304 | * Our endpoint might get disabled by another thread during | |
2305 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2306 | * early on so DWC3_EP_BUSY flag gets cleared | |
2307 | */ | |
2308 | if (!dep->endpoint.desc) | |
2309 | return 1; | |
2310 | ||
cdc359dd | 2311 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
2312 | list_empty(&dep->started_list)) { |
2313 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
2314 | /* |
2315 | * If there is no entry in request list then do | |
2316 | * not issue END TRANSFER now. Just set PENDING | |
2317 | * flag, so that END TRANSFER is issued when an | |
2318 | * entry is added into request list. | |
2319 | */ | |
2320 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2321 | } else { | |
b992e681 | 2322 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
2323 | dep->flags = DWC3_EP_ENABLED; |
2324 | } | |
7efea86c PA |
2325 | return 1; |
2326 | } | |
2327 | ||
d6e10bf2 AB |
2328 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc) |
2329 | return 0; | |
2330 | ||
72246da4 FB |
2331 | return 1; |
2332 | } | |
2333 | ||
2334 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 2335 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
2336 | { |
2337 | unsigned status = 0; | |
2338 | int clean_busy; | |
e18b7975 FB |
2339 | u32 is_xfer_complete; |
2340 | ||
2341 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
2342 | |
2343 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2344 | status = -ECONNRESET; | |
2345 | ||
1d046793 | 2346 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
4cb42217 | 2347 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || |
e18b7975 | 2348 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) |
72246da4 | 2349 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2350 | |
2351 | /* | |
2352 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2353 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2354 | */ | |
2355 | if (dwc->revision < DWC3_REVISION_183A) { | |
2356 | u32 reg; | |
2357 | int i; | |
2358 | ||
2359 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2360 | dep = dwc->eps[i]; |
fae2b904 FB |
2361 | |
2362 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2363 | continue; | |
2364 | ||
aa3342c8 | 2365 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2366 | return; |
2367 | } | |
2368 | ||
2369 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2370 | reg |= dwc->u1u2; | |
2371 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2372 | ||
2373 | dwc->u1u2 = 0; | |
2374 | } | |
8a1a9c9e | 2375 | |
4cb42217 FB |
2376 | /* |
2377 | * Our endpoint might get disabled by another thread during | |
2378 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2379 | * early on so DWC3_EP_BUSY flag gets cleared | |
2380 | */ | |
2381 | if (!dep->endpoint.desc) | |
2382 | return; | |
2383 | ||
e6e709b7 | 2384 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2385 | int ret; |
2386 | ||
4fae2e3e | 2387 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
8a1a9c9e FB |
2388 | if (!ret || ret == -EBUSY) |
2389 | return; | |
2390 | } | |
72246da4 FB |
2391 | } |
2392 | ||
72246da4 FB |
2393 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2394 | const struct dwc3_event_depevt *event) | |
2395 | { | |
2396 | struct dwc3_ep *dep; | |
2397 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2398 | u8 cmd; |
72246da4 FB |
2399 | |
2400 | dep = dwc->eps[epnum]; | |
2401 | ||
d7fd41c6 JD |
2402 | if (!(dep->flags & DWC3_EP_ENABLED)) { |
2403 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
2404 | return; | |
2405 | ||
2406 | /* Handle only EPCMDCMPLT when EP disabled */ | |
2407 | if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) | |
2408 | return; | |
2409 | } | |
3336abb5 | 2410 | |
72246da4 FB |
2411 | if (epnum == 0 || epnum == 1) { |
2412 | dwc3_ep0_interrupt(dwc, event); | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | switch (event->endpoint_event) { | |
2417 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2418 | dep->resource_index = 0; |
c2df85ca | 2419 | |
16e78db7 | 2420 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8566cd1a | 2421 | dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n"); |
72246da4 FB |
2422 | return; |
2423 | } | |
2424 | ||
029d97ff | 2425 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2426 | break; |
2427 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2428 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2429 | break; |
2430 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2431 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2432 | dwc3_gadget_start_isoc(dwc, dep, event); |
2433 | } else { | |
2434 | int ret; | |
2435 | ||
4fae2e3e | 2436 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
72246da4 FB |
2437 | if (!ret || ret == -EBUSY) |
2438 | return; | |
72246da4 FB |
2439 | } |
2440 | ||
879631aa FB |
2441 | break; |
2442 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2443 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2444 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2445 | dep->name); | |
2446 | return; | |
2447 | } | |
72246da4 | 2448 | break; |
72246da4 | 2449 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2450 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2451 | ||
2452 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
2453 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
2454 | wake_up(&dep->wait_end_transfer); | |
2455 | } | |
2456 | break; | |
2457 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
72246da4 FB |
2458 | break; |
2459 | } | |
2460 | } | |
2461 | ||
2462 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2463 | { | |
2464 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2465 | spin_unlock(&dwc->lock); | |
2466 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2467 | spin_lock(&dwc->lock); | |
2468 | } | |
2469 | } | |
2470 | ||
bc5ba2e0 FB |
2471 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2472 | { | |
73a30bfc | 2473 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2474 | spin_unlock(&dwc->lock); |
2475 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2476 | spin_lock(&dwc->lock); | |
2477 | } | |
2478 | } | |
2479 | ||
2480 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2481 | { | |
73a30bfc | 2482 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2483 | spin_unlock(&dwc->lock); |
2484 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2485 | spin_lock(&dwc->lock); |
8e74475b FB |
2486 | } |
2487 | } | |
2488 | ||
2489 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2490 | { | |
2491 | if (!dwc->gadget_driver) | |
2492 | return; | |
2493 | ||
2494 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2495 | spin_unlock(&dwc->lock); | |
2496 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2497 | spin_lock(&dwc->lock); |
2498 | } | |
2499 | } | |
2500 | ||
b992e681 | 2501 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2502 | { |
2503 | struct dwc3_ep *dep; | |
2504 | struct dwc3_gadget_ep_cmd_params params; | |
2505 | u32 cmd; | |
2506 | int ret; | |
2507 | ||
2508 | dep = dwc->eps[epnum]; | |
2509 | ||
76a638f8 BW |
2510 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || |
2511 | !dep->resource_index) | |
3daf74d7 PA |
2512 | return; |
2513 | ||
57911504 PA |
2514 | /* |
2515 | * NOTICE: We are violating what the Databook says about the | |
2516 | * EndTransfer command. Ideally we would _always_ wait for the | |
2517 | * EndTransfer Command Completion IRQ, but that's causing too | |
2518 | * much trouble synchronizing between us and gadget driver. | |
2519 | * | |
2520 | * We have discussed this with the IP Provider and it was | |
2521 | * suggested to giveback all requests here, but give HW some | |
2522 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2523 | * an arbitrary 100us delay for that. |
57911504 PA |
2524 | * |
2525 | * Note also that a similar handling was tested by Synopsys | |
2526 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2527 | * In short, what we're doing is: | |
2528 | * | |
2529 | * - Issue EndTransfer WITH CMDIOC bit set | |
2530 | * - Wait 100us | |
06281d46 JY |
2531 | * |
2532 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2533 | * supports a mode to work around the above limitation. The | |
2534 | * software can poll the CMDACT bit in the DEPCMD register | |
2535 | * after issuing a EndTransfer command. This mode is enabled | |
2536 | * by writing GUCTL2[14]. This polling is already done in the | |
2537 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2538 | * enabled, the EndTransfer command will have completed upon | |
2539 | * returning from this function and we don't need to delay for | |
2540 | * 100us. | |
2541 | * | |
2542 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2543 | */ |
2544 | ||
3daf74d7 | 2545 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2546 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2547 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2548 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2549 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2550 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2551 | WARN_ON_ONCE(ret); |
b4996a86 | 2552 | dep->resource_index = 0; |
041d81f4 | 2553 | dep->flags &= ~DWC3_EP_BUSY; |
06281d46 | 2554 | |
76a638f8 BW |
2555 | if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) { |
2556 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
06281d46 | 2557 | udelay(100); |
76a638f8 | 2558 | } |
72246da4 FB |
2559 | } |
2560 | ||
72246da4 FB |
2561 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2562 | { | |
2563 | u32 epnum; | |
2564 | ||
2565 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2566 | struct dwc3_ep *dep; | |
72246da4 FB |
2567 | int ret; |
2568 | ||
2569 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2570 | if (!dep) |
2571 | continue; | |
72246da4 FB |
2572 | |
2573 | if (!(dep->flags & DWC3_EP_STALL)) | |
2574 | continue; | |
2575 | ||
2576 | dep->flags &= ~DWC3_EP_STALL; | |
2577 | ||
50c763f8 | 2578 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2579 | WARN_ON_ONCE(ret); |
2580 | } | |
2581 | } | |
2582 | ||
2583 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2584 | { | |
c4430a26 FB |
2585 | int reg; |
2586 | ||
72246da4 FB |
2587 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2588 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2589 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2590 | ||
2591 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2592 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2593 | |
72246da4 FB |
2594 | dwc3_disconnect_gadget(dwc); |
2595 | ||
2596 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2597 | dwc->setup_packet_pending = false; |
06a374ed | 2598 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2599 | |
2600 | dwc->connected = false; | |
72246da4 FB |
2601 | } |
2602 | ||
72246da4 FB |
2603 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2604 | { | |
2605 | u32 reg; | |
2606 | ||
fc8bb91b FB |
2607 | dwc->connected = true; |
2608 | ||
df62df56 FB |
2609 | /* |
2610 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2611 | * would cause a missing Disconnect Event if there's a | |
2612 | * pending Setup Packet in the FIFO. | |
2613 | * | |
2614 | * There's no suggested workaround on the official Bug | |
2615 | * report, which states that "unless the driver/application | |
2616 | * is doing any special handling of a disconnect event, | |
2617 | * there is no functional issue". | |
2618 | * | |
2619 | * Unfortunately, it turns out that we _do_ some special | |
2620 | * handling of a disconnect event, namely complete all | |
2621 | * pending transfers, notify gadget driver of the | |
2622 | * disconnection, and so on. | |
2623 | * | |
2624 | * Our suggested workaround is to follow the Disconnect | |
2625 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2626 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2627 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2628 | * same endpoint. |
2629 | * | |
2630 | * Refers to: | |
2631 | * | |
2632 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2633 | * generated if setup packet pending in FIFO | |
2634 | */ | |
2635 | if (dwc->revision < DWC3_REVISION_188A) { | |
2636 | if (dwc->setup_packet_pending) | |
2637 | dwc3_gadget_disconnect_interrupt(dwc); | |
2638 | } | |
2639 | ||
8e74475b | 2640 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2641 | |
2642 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2643 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2644 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2645 | dwc->test_mode = false; |
72246da4 FB |
2646 | dwc3_clear_stall_all_ep(dwc); |
2647 | ||
2648 | /* Reset device address to zero */ | |
2649 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2650 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2651 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2652 | } |
2653 | ||
72246da4 FB |
2654 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2655 | { | |
72246da4 FB |
2656 | struct dwc3_ep *dep; |
2657 | int ret; | |
2658 | u32 reg; | |
2659 | u8 speed; | |
2660 | ||
72246da4 FB |
2661 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2662 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2663 | dwc->speed = speed; | |
2664 | ||
5fb6fdaf JY |
2665 | /* |
2666 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2667 | * each time on Connect Done. | |
2668 | * | |
2669 | * Currently we always use the reset value. If any platform | |
2670 | * wants to set this to a different value, we need to add a | |
2671 | * setting and update GCTL.RAMCLKSEL here. | |
2672 | */ | |
72246da4 FB |
2673 | |
2674 | switch (speed) { | |
2da9ad76 | 2675 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2676 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2677 | dwc->gadget.ep0->maxpacket = 512; | |
2678 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2679 | break; | |
2da9ad76 | 2680 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2681 | /* |
2682 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2683 | * would cause a missing USB3 Reset event. | |
2684 | * | |
2685 | * In such situations, we should force a USB3 Reset | |
2686 | * event by calling our dwc3_gadget_reset_interrupt() | |
2687 | * routine. | |
2688 | * | |
2689 | * Refers to: | |
2690 | * | |
2691 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2692 | * not be generated always when the link enters poll | |
2693 | */ | |
2694 | if (dwc->revision < DWC3_REVISION_190A) | |
2695 | dwc3_gadget_reset_interrupt(dwc); | |
2696 | ||
72246da4 FB |
2697 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2698 | dwc->gadget.ep0->maxpacket = 512; | |
2699 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2700 | break; | |
2da9ad76 | 2701 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2702 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2703 | dwc->gadget.ep0->maxpacket = 64; | |
2704 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2705 | break; | |
9418ee15 | 2706 | case DWC3_DSTS_FULLSPEED: |
72246da4 FB |
2707 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2708 | dwc->gadget.ep0->maxpacket = 64; | |
2709 | dwc->gadget.speed = USB_SPEED_FULL; | |
2710 | break; | |
2da9ad76 | 2711 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2712 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
2713 | dwc->gadget.ep0->maxpacket = 8; | |
2714 | dwc->gadget.speed = USB_SPEED_LOW; | |
2715 | break; | |
2716 | } | |
2717 | ||
2b758350 PA |
2718 | /* Enable USB2 LPM Capability */ |
2719 | ||
ee5cd41c | 2720 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
2721 | (speed != DWC3_DSTS_SUPERSPEED) && |
2722 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2723 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2724 | reg |= DWC3_DCFG_LPM_CAP; | |
2725 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2726 | ||
2727 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2728 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2729 | ||
460d098c | 2730 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2731 | |
80caf7d2 HR |
2732 | /* |
2733 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2734 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2735 | * BESL value in the LPM token is less than or equal to LPM | |
2736 | * NYET threshold. | |
2737 | */ | |
2738 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2739 | && dwc->has_lpm_erratum, | |
9165dabb | 2740 | "LPM Erratum not available on dwc3 revisions < 2.40a\n"); |
80caf7d2 HR |
2741 | |
2742 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2743 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2744 | ||
356363bf FB |
2745 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2746 | } else { | |
2747 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2748 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2749 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2750 | } | |
2751 | ||
72246da4 | 2752 | dep = dwc->eps[0]; |
39ebb05c | 2753 | ret = __dwc3_gadget_ep_enable(dep, true, false); |
72246da4 FB |
2754 | if (ret) { |
2755 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2756 | return; | |
2757 | } | |
2758 | ||
2759 | dep = dwc->eps[1]; | |
39ebb05c | 2760 | ret = __dwc3_gadget_ep_enable(dep, true, false); |
72246da4 FB |
2761 | if (ret) { |
2762 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2763 | return; | |
2764 | } | |
2765 | ||
2766 | /* | |
2767 | * Configure PHY via GUSB3PIPECTLn if required. | |
2768 | * | |
2769 | * Update GTXFIFOSIZn | |
2770 | * | |
2771 | * In both cases reset values should be sufficient. | |
2772 | */ | |
2773 | } | |
2774 | ||
2775 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2776 | { | |
72246da4 FB |
2777 | /* |
2778 | * TODO take core out of low power mode when that's | |
2779 | * implemented. | |
2780 | */ | |
2781 | ||
ad14d4e0 JL |
2782 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2783 | spin_unlock(&dwc->lock); | |
2784 | dwc->gadget_driver->resume(&dwc->gadget); | |
2785 | spin_lock(&dwc->lock); | |
2786 | } | |
72246da4 FB |
2787 | } |
2788 | ||
2789 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2790 | unsigned int evtinfo) | |
2791 | { | |
fae2b904 | 2792 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2793 | unsigned int pwropt; |
2794 | ||
2795 | /* | |
2796 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2797 | * Hibernation mode enabled which would show up when device detects | |
2798 | * host-initiated U3 exit. | |
2799 | * | |
2800 | * In that case, device will generate a Link State Change Interrupt | |
2801 | * from U3 to RESUME which is only necessary if Hibernation is | |
2802 | * configured in. | |
2803 | * | |
2804 | * There are no functional changes due to such spurious event and we | |
2805 | * just need to ignore it. | |
2806 | * | |
2807 | * Refers to: | |
2808 | * | |
2809 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2810 | * operational mode | |
2811 | */ | |
2812 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2813 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2814 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2815 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2816 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
2817 | return; |
2818 | } | |
2819 | } | |
fae2b904 FB |
2820 | |
2821 | /* | |
2822 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2823 | * on the link partner, the USB session might do multiple entry/exit | |
2824 | * of low power states before a transfer takes place. | |
2825 | * | |
2826 | * Due to this problem, we might experience lower throughput. The | |
2827 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2828 | * transitioning from U1/U2 to U0 and enable those bits again | |
2829 | * after a transfer completes and there are no pending transfers | |
2830 | * on any of the enabled endpoints. | |
2831 | * | |
2832 | * This is the first half of that workaround. | |
2833 | * | |
2834 | * Refers to: | |
2835 | * | |
2836 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2837 | * core send LGO_Ux entering U0 | |
2838 | */ | |
2839 | if (dwc->revision < DWC3_REVISION_183A) { | |
2840 | if (next == DWC3_LINK_STATE_U0) { | |
2841 | u32 u1u2; | |
2842 | u32 reg; | |
2843 | ||
2844 | switch (dwc->link_state) { | |
2845 | case DWC3_LINK_STATE_U1: | |
2846 | case DWC3_LINK_STATE_U2: | |
2847 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2848 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2849 | | DWC3_DCTL_ACCEPTU2ENA | |
2850 | | DWC3_DCTL_INITU1ENA | |
2851 | | DWC3_DCTL_ACCEPTU1ENA); | |
2852 | ||
2853 | if (!dwc->u1u2) | |
2854 | dwc->u1u2 = reg & u1u2; | |
2855 | ||
2856 | reg &= ~u1u2; | |
2857 | ||
2858 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2859 | break; | |
2860 | default: | |
2861 | /* do nothing */ | |
2862 | break; | |
2863 | } | |
2864 | } | |
2865 | } | |
2866 | ||
bc5ba2e0 FB |
2867 | switch (next) { |
2868 | case DWC3_LINK_STATE_U1: | |
2869 | if (dwc->speed == USB_SPEED_SUPER) | |
2870 | dwc3_suspend_gadget(dwc); | |
2871 | break; | |
2872 | case DWC3_LINK_STATE_U2: | |
2873 | case DWC3_LINK_STATE_U3: | |
2874 | dwc3_suspend_gadget(dwc); | |
2875 | break; | |
2876 | case DWC3_LINK_STATE_RESUME: | |
2877 | dwc3_resume_gadget(dwc); | |
2878 | break; | |
2879 | default: | |
2880 | /* do nothing */ | |
2881 | break; | |
2882 | } | |
2883 | ||
e57ebc1d | 2884 | dwc->link_state = next; |
72246da4 FB |
2885 | } |
2886 | ||
72704f87 BW |
2887 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
2888 | unsigned int evtinfo) | |
2889 | { | |
2890 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
2891 | ||
2892 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
2893 | dwc3_suspend_gadget(dwc); | |
2894 | ||
2895 | dwc->link_state = next; | |
2896 | } | |
2897 | ||
e1dadd3b FB |
2898 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2899 | unsigned int evtinfo) | |
2900 | { | |
2901 | unsigned int is_ss = evtinfo & BIT(4); | |
2902 | ||
bfad65ee | 2903 | /* |
e1dadd3b FB |
2904 | * WORKAROUND: DWC3 revison 2.20a with hibernation support |
2905 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2906 | * randomly. | |
2907 | * | |
2908 | * Because of this issue, core could generate bogus hibernation | |
2909 | * events which SW needs to ignore. | |
2910 | * | |
2911 | * Refers to: | |
2912 | * | |
2913 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2914 | * Device Fallback from SuperSpeed | |
2915 | */ | |
2916 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2917 | return; | |
2918 | ||
2919 | /* enter hibernation here */ | |
2920 | } | |
2921 | ||
72246da4 FB |
2922 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2923 | const struct dwc3_event_devt *event) | |
2924 | { | |
2925 | switch (event->type) { | |
2926 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2927 | dwc3_gadget_disconnect_interrupt(dwc); | |
2928 | break; | |
2929 | case DWC3_DEVICE_EVENT_RESET: | |
2930 | dwc3_gadget_reset_interrupt(dwc); | |
2931 | break; | |
2932 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2933 | dwc3_gadget_conndone_interrupt(dwc); | |
2934 | break; | |
2935 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2936 | dwc3_gadget_wakeup_interrupt(dwc); | |
2937 | break; | |
e1dadd3b FB |
2938 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2939 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2940 | "unexpected hibernation event\n")) | |
2941 | break; | |
2942 | ||
2943 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2944 | break; | |
72246da4 FB |
2945 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2946 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2947 | break; | |
2948 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 2949 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 2950 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
2951 | /* |
2952 | * Ignore suspend event until the gadget enters into | |
2953 | * USB_STATE_CONFIGURED state. | |
2954 | */ | |
2955 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
2956 | dwc3_gadget_suspend_interrupt(dwc, | |
2957 | event->event_info); | |
2958 | } | |
72246da4 FB |
2959 | break; |
2960 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 2961 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 2962 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 2963 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
2964 | break; |
2965 | default: | |
e9f2aa87 | 2966 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2967 | } |
2968 | } | |
2969 | ||
2970 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2971 | const union dwc3_event *event) | |
2972 | { | |
43c96be1 | 2973 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 2974 | |
72246da4 FB |
2975 | /* Endpoint IRQ, handle it and return early */ |
2976 | if (event->type.is_devspec == 0) { | |
2977 | /* depevt */ | |
2978 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2979 | } | |
2980 | ||
2981 | switch (event->type.type) { | |
2982 | case DWC3_EVENT_TYPE_DEV: | |
2983 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2984 | break; | |
2985 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2986 | default: | |
2987 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2988 | } | |
2989 | } | |
2990 | ||
dea520a4 | 2991 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2992 | { |
dea520a4 | 2993 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2994 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2995 | int left; |
e8adfc30 | 2996 | u32 reg; |
b15a762f | 2997 | |
f42f2447 | 2998 | left = evt->count; |
b15a762f | 2999 | |
f42f2447 FB |
3000 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
3001 | return IRQ_NONE; | |
b15a762f | 3002 | |
f42f2447 FB |
3003 | while (left > 0) { |
3004 | union dwc3_event event; | |
b15a762f | 3005 | |
ebbb2d59 | 3006 | event.raw = *(u32 *) (evt->cache + evt->lpos); |
b15a762f | 3007 | |
f42f2447 | 3008 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 3009 | |
f42f2447 FB |
3010 | /* |
3011 | * FIXME we wrap around correctly to the next entry as | |
3012 | * almost all entries are 4 bytes in size. There is one | |
3013 | * entry which has 12 bytes which is a regular entry | |
3014 | * followed by 8 bytes data. ATM I don't know how | |
3015 | * things are organized if we get next to the a | |
3016 | * boundary so I worry about that once we try to handle | |
3017 | * that. | |
3018 | */ | |
caefe6c7 | 3019 | evt->lpos = (evt->lpos + 4) % evt->length; |
f42f2447 | 3020 | left -= 4; |
f42f2447 | 3021 | } |
b15a762f | 3022 | |
f42f2447 FB |
3023 | evt->count = 0; |
3024 | evt->flags &= ~DWC3_EVENT_PENDING; | |
3025 | ret = IRQ_HANDLED; | |
b15a762f | 3026 | |
f42f2447 | 3027 | /* Unmask interrupt */ |
660e9bde | 3028 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 3029 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3030 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 3031 | |
cf40b86b JY |
3032 | if (dwc->imod_interval) { |
3033 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); | |
3034 | dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); | |
3035 | } | |
3036 | ||
f42f2447 FB |
3037 | return ret; |
3038 | } | |
e8adfc30 | 3039 | |
dea520a4 | 3040 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 3041 | { |
dea520a4 FB |
3042 | struct dwc3_event_buffer *evt = _evt; |
3043 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 3044 | unsigned long flags; |
f42f2447 | 3045 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 3046 | |
e5f68b4a | 3047 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 3048 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 3049 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
3050 | |
3051 | return ret; | |
3052 | } | |
3053 | ||
dea520a4 | 3054 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 3055 | { |
dea520a4 | 3056 | struct dwc3 *dwc = evt->dwc; |
ebbb2d59 | 3057 | u32 amount; |
72246da4 | 3058 | u32 count; |
e8adfc30 | 3059 | u32 reg; |
72246da4 | 3060 | |
fc8bb91b FB |
3061 | if (pm_runtime_suspended(dwc->dev)) { |
3062 | pm_runtime_get(dwc->dev); | |
3063 | disable_irq_nosync(dwc->irq_gadget); | |
3064 | dwc->pending_events = true; | |
3065 | return IRQ_HANDLED; | |
3066 | } | |
3067 | ||
660e9bde | 3068 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
3069 | count &= DWC3_GEVNTCOUNT_MASK; |
3070 | if (!count) | |
3071 | return IRQ_NONE; | |
3072 | ||
b15a762f FB |
3073 | evt->count = count; |
3074 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 3075 | |
e8adfc30 | 3076 | /* Mask interrupt */ |
660e9bde | 3077 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 3078 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 3079 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 3080 | |
ebbb2d59 JY |
3081 | amount = min(count, evt->length - evt->lpos); |
3082 | memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); | |
3083 | ||
3084 | if (amount < count) | |
3085 | memcpy(evt->cache, evt->buf, count - amount); | |
3086 | ||
65aca320 JY |
3087 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); |
3088 | ||
b15a762f | 3089 | return IRQ_WAKE_THREAD; |
72246da4 FB |
3090 | } |
3091 | ||
dea520a4 | 3092 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 3093 | { |
dea520a4 | 3094 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 3095 | |
dea520a4 | 3096 | return dwc3_check_event_buf(evt); |
72246da4 FB |
3097 | } |
3098 | ||
6db3812e FB |
3099 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
3100 | { | |
3101 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
3102 | int irq; | |
3103 | ||
3104 | irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); | |
3105 | if (irq > 0) | |
3106 | goto out; | |
3107 | ||
3108 | if (irq == -EPROBE_DEFER) | |
3109 | goto out; | |
3110 | ||
3111 | irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); | |
3112 | if (irq > 0) | |
3113 | goto out; | |
3114 | ||
3115 | if (irq == -EPROBE_DEFER) | |
3116 | goto out; | |
3117 | ||
3118 | irq = platform_get_irq(dwc3_pdev, 0); | |
3119 | if (irq > 0) | |
3120 | goto out; | |
3121 | ||
3122 | if (irq != -EPROBE_DEFER) | |
3123 | dev_err(dwc->dev, "missing peripheral IRQ\n"); | |
3124 | ||
3125 | if (!irq) | |
3126 | irq = -EINVAL; | |
3127 | ||
3128 | out: | |
3129 | return irq; | |
3130 | } | |
3131 | ||
72246da4 | 3132 | /** |
bfad65ee | 3133 | * dwc3_gadget_init - initializes gadget related registers |
1d046793 | 3134 | * @dwc: pointer to our controller context structure |
72246da4 FB |
3135 | * |
3136 | * Returns 0 on success otherwise negative errno. | |
3137 | */ | |
41ac7b3a | 3138 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 3139 | { |
6db3812e FB |
3140 | int ret; |
3141 | int irq; | |
9522def4 | 3142 | |
6db3812e FB |
3143 | irq = dwc3_gadget_get_irq(dwc); |
3144 | if (irq < 0) { | |
3145 | ret = irq; | |
3146 | goto err0; | |
9522def4 RQ |
3147 | } |
3148 | ||
3149 | dwc->irq_gadget = irq; | |
72246da4 | 3150 | |
d64ff406 AB |
3151 | dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, |
3152 | sizeof(*dwc->ep0_trb) * 2, | |
3153 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
72246da4 FB |
3154 | if (!dwc->ep0_trb) { |
3155 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
3156 | ret = -ENOMEM; | |
7d5e650a | 3157 | goto err0; |
72246da4 FB |
3158 | } |
3159 | ||
4199c5f8 | 3160 | dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); |
72246da4 | 3161 | if (!dwc->setup_buf) { |
72246da4 | 3162 | ret = -ENOMEM; |
7d5e650a | 3163 | goto err1; |
72246da4 FB |
3164 | } |
3165 | ||
905dc04e FB |
3166 | dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, |
3167 | &dwc->bounce_addr, GFP_KERNEL); | |
3168 | if (!dwc->bounce) { | |
3169 | ret = -ENOMEM; | |
d6e5a549 | 3170 | goto err2; |
905dc04e FB |
3171 | } |
3172 | ||
bb014736 BW |
3173 | init_completion(&dwc->ep0_in_setup); |
3174 | ||
72246da4 | 3175 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3176 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3177 | dwc->gadget.sg_supported = true; |
72246da4 | 3178 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 3179 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 3180 | |
b9e51b2b BM |
3181 | /* |
3182 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3183 | * <2.20a of dwc3 have an issue with metastability (documented | |
3184 | * elsewhere in this driver) which tells us we can't set max speed to | |
3185 | * anything lower than SUPER. | |
3186 | * | |
3187 | * Because gadget.max_speed is only used by composite.c and function | |
3188 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3189 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3190 | * together with our BOS descriptor as that could confuse host into | |
3191 | * thinking we can handle super speed. | |
3192 | * | |
3193 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3194 | * is less than super speed because we don't have means, yet, to tell | |
3195 | * composite.c that we are USB 2.0 + LPM ECN. | |
3196 | */ | |
3197 | if (dwc->revision < DWC3_REVISION_220A) | |
5eb30ced | 3198 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3199 | dwc->revision); |
3200 | ||
3201 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3202 | ||
72246da4 FB |
3203 | /* |
3204 | * REVISIT: Here we should clear all pending IRQs to be | |
3205 | * sure we're starting from a well known location. | |
3206 | */ | |
3207 | ||
f3bcfc7e | 3208 | ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); |
72246da4 | 3209 | if (ret) |
d6e5a549 | 3210 | goto err3; |
72246da4 | 3211 | |
72246da4 FB |
3212 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3213 | if (ret) { | |
3214 | dev_err(dwc->dev, "failed to register udc\n"); | |
d6e5a549 | 3215 | goto err4; |
72246da4 FB |
3216 | } |
3217 | ||
3218 | return 0; | |
3219 | ||
7d5e650a | 3220 | err4: |
d6e5a549 | 3221 | dwc3_gadget_free_endpoints(dwc); |
04c03d10 | 3222 | |
7d5e650a | 3223 | err3: |
d6e5a549 FB |
3224 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
3225 | dwc->bounce_addr); | |
5812b1c2 | 3226 | |
7d5e650a | 3227 | err2: |
0fc9a1be | 3228 | kfree(dwc->setup_buf); |
72246da4 | 3229 | |
7d5e650a | 3230 | err1: |
d64ff406 | 3231 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3232 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3233 | ||
72246da4 FB |
3234 | err0: |
3235 | return ret; | |
3236 | } | |
3237 | ||
7415f17c FB |
3238 | /* -------------------------------------------------------------------------- */ |
3239 | ||
72246da4 FB |
3240 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3241 | { | |
72246da4 | 3242 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3243 | dwc3_gadget_free_endpoints(dwc); |
905dc04e | 3244 | dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, |
d6e5a549 | 3245 | dwc->bounce_addr); |
0fc9a1be | 3246 | kfree(dwc->setup_buf); |
d64ff406 | 3247 | dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, |
d6e5a549 | 3248 | dwc->ep0_trb, dwc->ep0_trb_addr); |
72246da4 | 3249 | } |
7415f17c | 3250 | |
0b0231aa | 3251 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3252 | { |
9772b47a RQ |
3253 | if (!dwc->gadget_driver) |
3254 | return 0; | |
3255 | ||
1551e35e | 3256 | dwc3_gadget_run_stop(dwc, false, false); |
9f8a67b6 FB |
3257 | dwc3_disconnect_gadget(dwc); |
3258 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3259 | |
3260 | return 0; | |
3261 | } | |
3262 | ||
3263 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3264 | { | |
7415f17c FB |
3265 | int ret; |
3266 | ||
9772b47a RQ |
3267 | if (!dwc->gadget_driver) |
3268 | return 0; | |
3269 | ||
9f8a67b6 FB |
3270 | ret = __dwc3_gadget_start(dwc); |
3271 | if (ret < 0) | |
7415f17c FB |
3272 | goto err0; |
3273 | ||
9f8a67b6 FB |
3274 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3275 | if (ret < 0) | |
7415f17c FB |
3276 | goto err1; |
3277 | ||
7415f17c FB |
3278 | return 0; |
3279 | ||
3280 | err1: | |
9f8a67b6 | 3281 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3282 | |
3283 | err0: | |
3284 | return ret; | |
3285 | } | |
fc8bb91b FB |
3286 | |
3287 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3288 | { | |
3289 | if (dwc->pending_events) { | |
3290 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3291 | dwc->pending_events = false; | |
3292 | enable_irq(dwc->irq_gadget); | |
3293 | } | |
3294 | } |