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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
8598bde7 FB |
142 | return -ETIMEDOUT; |
143 | } | |
144 | ||
dca0119c JY |
145 | /** |
146 | * dwc3_ep_inc_trb() - Increment a TRB index. | |
147 | * @index - Pointer to the TRB index to increment. | |
148 | * | |
149 | * The index should never point to the link TRB. After incrementing, | |
150 | * if it is point to the link TRB, wrap around to the beginning. The | |
151 | * link TRB is always at the last TRB entry. | |
152 | */ | |
153 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 154 | { |
dca0119c JY |
155 | (*index)++; |
156 | if (*index == (DWC3_TRB_NUM - 1)) | |
157 | *index = 0; | |
ef966b9d | 158 | } |
457e84b6 | 159 | |
dca0119c | 160 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 161 | { |
dca0119c | 162 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 163 | } |
457e84b6 | 164 | |
dca0119c | 165 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 166 | { |
dca0119c | 167 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
168 | } |
169 | ||
72246da4 FB |
170 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
171 | int status) | |
172 | { | |
173 | struct dwc3 *dwc = dep->dwc; | |
174 | ||
737f1ae2 | 175 | req->started = false; |
72246da4 | 176 | list_del(&req->list); |
eeb720fb | 177 | req->trb = NULL; |
e62c5bc5 | 178 | req->remaining = 0; |
72246da4 FB |
179 | |
180 | if (req->request.status == -EINPROGRESS) | |
181 | req->request.status = status; | |
182 | ||
0416e494 PA |
183 | if (dwc->ep0_bounced && dep->number == 0) |
184 | dwc->ep0_bounced = false; | |
185 | else | |
186 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
187 | req->direction); | |
72246da4 | 188 | |
2c4cbe6e | 189 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
190 | |
191 | spin_unlock(&dwc->lock); | |
304f7e5e | 192 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 | 193 | spin_lock(&dwc->lock); |
fc8bb91b FB |
194 | |
195 | if (dep->number > 1) | |
196 | pm_runtime_put(dwc->dev); | |
72246da4 FB |
197 | } |
198 | ||
3ece0ec4 | 199 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
200 | { |
201 | u32 timeout = 500; | |
71f7e702 | 202 | int status = 0; |
0fe886cd | 203 | int ret = 0; |
b09bb642 FB |
204 | u32 reg; |
205 | ||
206 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
207 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
208 | ||
209 | do { | |
210 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
211 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
212 | status = DWC3_DGCMD_STATUS(reg); |
213 | if (status) | |
0fe886cd FB |
214 | ret = -EINVAL; |
215 | break; | |
b09bb642 | 216 | } |
0fe886cd FB |
217 | } while (timeout--); |
218 | ||
219 | if (!timeout) { | |
0fe886cd | 220 | ret = -ETIMEDOUT; |
71f7e702 | 221 | status = -ETIMEDOUT; |
0fe886cd FB |
222 | } |
223 | ||
71f7e702 FB |
224 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
225 | ||
0fe886cd | 226 | return ret; |
b09bb642 FB |
227 | } |
228 | ||
c36d8e94 FB |
229 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
230 | ||
2cd4718d FB |
231 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
232 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 233 | { |
8897a761 | 234 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 235 | struct dwc3 *dwc = dep->dwc; |
61d58242 | 236 | u32 timeout = 500; |
72246da4 FB |
237 | u32 reg; |
238 | ||
0933df15 | 239 | int cmd_status = 0; |
2b0f11df | 240 | int susphy = false; |
c0ca324d | 241 | int ret = -EINVAL; |
72246da4 | 242 | |
2b0f11df FB |
243 | /* |
244 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
245 | * we're issuing an endpoint command, we must check if | |
246 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
247 | * | |
248 | * We will also set SUSPHY bit to what it was before returning as stated | |
249 | * by the same section on Synopsys databook. | |
250 | */ | |
ab2a92e7 FB |
251 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
252 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
253 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
254 | susphy = true; | |
255 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
256 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
257 | } | |
2b0f11df FB |
258 | } |
259 | ||
5999914f | 260 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
261 | int needs_wakeup; |
262 | ||
263 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
264 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
265 | dwc->link_state == DWC3_LINK_STATE_U3); | |
266 | ||
267 | if (unlikely(needs_wakeup)) { | |
268 | ret = __dwc3_gadget_wakeup(dwc); | |
269 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
270 | ret); | |
271 | } | |
272 | } | |
273 | ||
2eb88016 FB |
274 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
275 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
276 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 277 | |
8897a761 FB |
278 | /* |
279 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
280 | * not relying on XferNotReady, we can make use of a special "No | |
281 | * Response Update Transfer" command where we should clear both CmdAct | |
282 | * and CmdIOC bits. | |
283 | * | |
284 | * With this, we don't need to wait for command completion and can | |
285 | * straight away issue further commands to the endpoint. | |
286 | * | |
287 | * NOTICE: We're making an assumption that control endpoints will never | |
288 | * make use of Update Transfer command. This is a safe assumption | |
289 | * because we can never have more than one request at a time with | |
290 | * Control Endpoints. If anybody changes that assumption, this chunk | |
291 | * needs to be updated accordingly. | |
292 | */ | |
293 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
294 | !usb_endpoint_xfer_isoc(desc)) | |
295 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
296 | else | |
297 | cmd |= DWC3_DEPCMD_CMDACT; | |
298 | ||
299 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 300 | do { |
2eb88016 | 301 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 302 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 303 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 304 | |
7b9cc7a2 KL |
305 | switch (cmd_status) { |
306 | case 0: | |
307 | ret = 0; | |
308 | break; | |
309 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
7b9cc7a2 | 310 | ret = -EINVAL; |
c0ca324d | 311 | break; |
7b9cc7a2 KL |
312 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
313 | /* | |
314 | * SW issues START TRANSFER command to | |
315 | * isochronous ep with future frame interval. If | |
316 | * future interval time has already passed when | |
317 | * core receives the command, it will respond | |
318 | * with an error status of 'Bus Expiry'. | |
319 | * | |
320 | * Instead of always returning -EINVAL, let's | |
321 | * give a hint to the gadget driver that this is | |
322 | * the case by returning -EAGAIN. | |
323 | */ | |
7b9cc7a2 KL |
324 | ret = -EAGAIN; |
325 | break; | |
326 | default: | |
327 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
328 | } | |
329 | ||
c0ca324d | 330 | break; |
72246da4 | 331 | } |
f6bb225b | 332 | } while (--timeout); |
72246da4 | 333 | |
f6bb225b | 334 | if (timeout == 0) { |
f6bb225b | 335 | ret = -ETIMEDOUT; |
0933df15 | 336 | cmd_status = -ETIMEDOUT; |
f6bb225b | 337 | } |
c0ca324d | 338 | |
0933df15 FB |
339 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
340 | ||
6cb2e4e3 FB |
341 | if (ret == 0) { |
342 | switch (DWC3_DEPCMD_CMD(cmd)) { | |
343 | case DWC3_DEPCMD_STARTTRANSFER: | |
344 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
345 | break; | |
346 | case DWC3_DEPCMD_ENDTRANSFER: | |
347 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
348 | break; | |
349 | default: | |
350 | /* nothing */ | |
351 | break; | |
352 | } | |
353 | } | |
354 | ||
2b0f11df FB |
355 | if (unlikely(susphy)) { |
356 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
357 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
358 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
359 | } | |
360 | ||
c0ca324d | 361 | return ret; |
72246da4 FB |
362 | } |
363 | ||
50c763f8 JY |
364 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
365 | { | |
366 | struct dwc3 *dwc = dep->dwc; | |
367 | struct dwc3_gadget_ep_cmd_params params; | |
368 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
369 | ||
370 | /* | |
371 | * As of core revision 2.60a the recommended programming model | |
372 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
373 | * command for IN endpoints. This is to prevent an issue where | |
374 | * some (non-compliant) hosts may not send ACK TPs for pending | |
375 | * IN transfers due to a mishandled error condition. Synopsys | |
376 | * STAR 9000614252. | |
377 | */ | |
5e6c88d2 LB |
378 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
379 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
380 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
381 | ||
382 | memset(¶ms, 0, sizeof(params)); | |
383 | ||
2cd4718d | 384 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
385 | } |
386 | ||
72246da4 | 387 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 388 | struct dwc3_trb *trb) |
72246da4 | 389 | { |
c439ef87 | 390 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
391 | |
392 | return dep->trb_pool_dma + offset; | |
393 | } | |
394 | ||
395 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
396 | { | |
397 | struct dwc3 *dwc = dep->dwc; | |
398 | ||
399 | if (dep->trb_pool) | |
400 | return 0; | |
401 | ||
72246da4 FB |
402 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
403 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
404 | &dep->trb_pool_dma, GFP_KERNEL); | |
405 | if (!dep->trb_pool) { | |
406 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
407 | dep->name); | |
408 | return -ENOMEM; | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
415 | { | |
416 | struct dwc3 *dwc = dep->dwc; | |
417 | ||
418 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
419 | dep->trb_pool, dep->trb_pool_dma); | |
420 | ||
421 | dep->trb_pool = NULL; | |
422 | dep->trb_pool_dma = 0; | |
423 | } | |
424 | ||
c4509601 JY |
425 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
426 | ||
427 | /** | |
428 | * dwc3_gadget_start_config - Configure EP resources | |
429 | * @dwc: pointer to our controller context structure | |
430 | * @dep: endpoint that is being enabled | |
431 | * | |
432 | * The assignment of transfer resources cannot perfectly follow the | |
433 | * data book due to the fact that the controller driver does not have | |
434 | * all knowledge of the configuration in advance. It is given this | |
435 | * information piecemeal by the composite gadget framework after every | |
436 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
437 | * programming model in this scenario can cause errors. For two | |
438 | * reasons: | |
439 | * | |
440 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
441 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
442 | * multiple interfaces. | |
443 | * | |
444 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
445 | * endpoint on alt setting (8.1.6). | |
446 | * | |
447 | * The following simplified method is used instead: | |
448 | * | |
449 | * All hardware endpoints can be assigned a transfer resource and this | |
450 | * setting will stay persistent until either a core reset or | |
451 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
452 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
453 | * guaranteed that there are as many transfer resources as endpoints. | |
454 | * | |
455 | * This function is called for each endpoint when it is being enabled | |
456 | * but is triggered only when called for EP0-out, which always happens | |
457 | * first, and which should only happen in one of the above conditions. | |
458 | */ | |
72246da4 FB |
459 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
460 | { | |
461 | struct dwc3_gadget_ep_cmd_params params; | |
462 | u32 cmd; | |
c4509601 JY |
463 | int i; |
464 | int ret; | |
465 | ||
466 | if (dep->number) | |
467 | return 0; | |
72246da4 FB |
468 | |
469 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 470 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 471 | |
2cd4718d | 472 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
473 | if (ret) |
474 | return ret; | |
475 | ||
476 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
477 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 478 | |
c4509601 JY |
479 | if (!dep) |
480 | continue; | |
481 | ||
482 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
483 | if (ret) | |
484 | return ret; | |
72246da4 FB |
485 | } |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 491 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 492 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
21e64bf2 | 493 | bool modify, bool restore) |
72246da4 FB |
494 | { |
495 | struct dwc3_gadget_ep_cmd_params params; | |
496 | ||
21e64bf2 FB |
497 | if (dev_WARN_ONCE(dwc->dev, modify && restore, |
498 | "Can't modify and restore\n")) | |
499 | return -EINVAL; | |
500 | ||
72246da4 FB |
501 | memset(¶ms, 0x00, sizeof(params)); |
502 | ||
dc1c70a7 | 503 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
504 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
505 | ||
506 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 507 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 508 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 509 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 510 | } |
72246da4 | 511 | |
21e64bf2 FB |
512 | if (modify) { |
513 | params.param0 |= DWC3_DEPCFG_ACTION_MODIFY; | |
514 | } else if (restore) { | |
265b70a7 PZ |
515 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; |
516 | params.param2 |= dep->saved_state; | |
21e64bf2 FB |
517 | } else { |
518 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; | |
265b70a7 PZ |
519 | } |
520 | ||
4bc48c97 FB |
521 | if (usb_endpoint_xfer_control(desc)) |
522 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
523 | |
524 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
525 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 526 | |
18b7ede5 | 527 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
528 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
529 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
530 | dep->stream_capable = true; |
531 | } | |
532 | ||
0b93a4c8 | 533 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 534 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
535 | |
536 | /* | |
537 | * We are doing 1:1 mapping for endpoints, meaning | |
538 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
539 | * so on. We consider the direction bit as part of the physical | |
540 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
541 | */ | |
dc1c70a7 | 542 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
543 | |
544 | /* | |
545 | * We must use the lower 16 TX FIFOs even though | |
546 | * HW might have more | |
547 | */ | |
548 | if (dep->direction) | |
dc1c70a7 | 549 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
550 | |
551 | if (desc->bInterval) { | |
dc1c70a7 | 552 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
553 | dep->interval = 1 << (desc->bInterval - 1); |
554 | } | |
555 | ||
2cd4718d | 556 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
557 | } |
558 | ||
559 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
560 | { | |
561 | struct dwc3_gadget_ep_cmd_params params; | |
562 | ||
563 | memset(¶ms, 0x00, sizeof(params)); | |
564 | ||
dc1c70a7 | 565 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 | 566 | |
2cd4718d FB |
567 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, |
568 | ¶ms); | |
72246da4 FB |
569 | } |
570 | ||
571 | /** | |
572 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
573 | * @dep: endpoint to be initialized | |
574 | * @desc: USB Endpoint Descriptor | |
575 | * | |
576 | * Caller should take care of locking | |
577 | */ | |
578 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 579 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 580 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
21e64bf2 | 581 | bool modify, bool restore) |
72246da4 FB |
582 | { |
583 | struct dwc3 *dwc = dep->dwc; | |
584 | u32 reg; | |
b09e99ee | 585 | int ret; |
72246da4 FB |
586 | |
587 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
588 | ret = dwc3_gadget_start_config(dwc, dep); | |
589 | if (ret) | |
590 | return ret; | |
591 | } | |
592 | ||
21e64bf2 | 593 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify, |
265b70a7 | 594 | restore); |
72246da4 FB |
595 | if (ret) |
596 | return ret; | |
597 | ||
598 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
599 | struct dwc3_trb *trb_st_hw; |
600 | struct dwc3_trb *trb_link; | |
72246da4 | 601 | |
16e78db7 | 602 | dep->endpoint.desc = desc; |
c90bfaec | 603 | dep->comp_desc = comp_desc; |
72246da4 FB |
604 | dep->type = usb_endpoint_type(desc); |
605 | dep->flags |= DWC3_EP_ENABLED; | |
76a638f8 | 606 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
607 | |
608 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
609 | reg |= DWC3_DALEPENA_EP(dep->number); | |
610 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
611 | ||
76a638f8 BW |
612 | init_waitqueue_head(&dep->wait_end_transfer); |
613 | ||
36b68aae | 614 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 615 | goto out; |
72246da4 | 616 | |
0d25744a JY |
617 | /* Initialize the TRB ring */ |
618 | dep->trb_dequeue = 0; | |
619 | dep->trb_enqueue = 0; | |
620 | memset(dep->trb_pool, 0, | |
621 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
622 | ||
36b68aae | 623 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
624 | trb_st_hw = &dep->trb_pool[0]; |
625 | ||
f6bafc6a | 626 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
627 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
628 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
629 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
630 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
631 | } |
632 | ||
a97ea994 FB |
633 | /* |
634 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
635 | * Response Update Transfer command. | |
636 | */ | |
637 | if (usb_endpoint_xfer_bulk(desc)) { | |
638 | struct dwc3_gadget_ep_cmd_params params; | |
639 | struct dwc3_trb *trb; | |
640 | dma_addr_t trb_dma; | |
641 | u32 cmd; | |
642 | ||
643 | memset(¶ms, 0, sizeof(params)); | |
644 | trb = &dep->trb_pool[0]; | |
645 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
646 | ||
647 | params.param0 = upper_32_bits(trb_dma); | |
648 | params.param1 = lower_32_bits(trb_dma); | |
649 | ||
650 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
651 | ||
652 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
653 | if (ret < 0) | |
654 | return ret; | |
655 | ||
656 | dep->flags |= DWC3_EP_BUSY; | |
657 | ||
658 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); | |
659 | WARN_ON_ONCE(!dep->resource_index); | |
660 | } | |
661 | ||
2870e501 FB |
662 | |
663 | out: | |
664 | trace_dwc3_gadget_ep_enable(dep); | |
665 | ||
72246da4 FB |
666 | return 0; |
667 | } | |
668 | ||
b992e681 | 669 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 670 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
671 | { |
672 | struct dwc3_request *req; | |
673 | ||
0e146028 | 674 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 675 | |
0e146028 FB |
676 | /* - giveback all requests to gadget driver */ |
677 | while (!list_empty(&dep->started_list)) { | |
678 | req = next_request(&dep->started_list); | |
1591633e | 679 | |
0e146028 | 680 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
681 | } |
682 | ||
aa3342c8 FB |
683 | while (!list_empty(&dep->pending_list)) { |
684 | req = next_request(&dep->pending_list); | |
72246da4 | 685 | |
624407f9 | 686 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 687 | } |
72246da4 FB |
688 | } |
689 | ||
690 | /** | |
691 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
692 | * @dep: the endpoint to disable | |
693 | * | |
624407f9 SAS |
694 | * This function also removes requests which are currently processed ny the |
695 | * hardware and those which are not yet scheduled. | |
696 | * Caller should take care of locking. | |
72246da4 | 697 | */ |
72246da4 FB |
698 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
699 | { | |
700 | struct dwc3 *dwc = dep->dwc; | |
701 | u32 reg; | |
702 | ||
2870e501 | 703 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 704 | |
624407f9 | 705 | dwc3_remove_requests(dwc, dep); |
72246da4 | 706 | |
687ef981 FB |
707 | /* make sure HW endpoint isn't stalled */ |
708 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 709 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 710 | |
72246da4 FB |
711 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
712 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
713 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
714 | ||
879631aa | 715 | dep->stream_capable = false; |
f9c56cdd | 716 | dep->endpoint.desc = NULL; |
c90bfaec | 717 | dep->comp_desc = NULL; |
72246da4 | 718 | dep->type = 0; |
76a638f8 | 719 | dep->flags &= DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
720 | |
721 | return 0; | |
722 | } | |
723 | ||
724 | /* -------------------------------------------------------------------------- */ | |
725 | ||
726 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
727 | const struct usb_endpoint_descriptor *desc) | |
728 | { | |
729 | return -EINVAL; | |
730 | } | |
731 | ||
732 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
733 | { | |
734 | return -EINVAL; | |
735 | } | |
736 | ||
737 | /* -------------------------------------------------------------------------- */ | |
738 | ||
739 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
740 | const struct usb_endpoint_descriptor *desc) | |
741 | { | |
742 | struct dwc3_ep *dep; | |
743 | struct dwc3 *dwc; | |
744 | unsigned long flags; | |
745 | int ret; | |
746 | ||
747 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
748 | pr_debug("dwc3: invalid parameters\n"); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | if (!desc->wMaxPacketSize) { | |
753 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
754 | return -EINVAL; | |
755 | } | |
756 | ||
757 | dep = to_dwc3_ep(ep); | |
758 | dwc = dep->dwc; | |
759 | ||
95ca961c FB |
760 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
761 | "%s is already enabled\n", | |
762 | dep->name)) | |
c6f83f38 | 763 | return 0; |
c6f83f38 | 764 | |
72246da4 | 765 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 766 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
767 | spin_unlock_irqrestore(&dwc->lock, flags); |
768 | ||
769 | return ret; | |
770 | } | |
771 | ||
772 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
773 | { | |
774 | struct dwc3_ep *dep; | |
775 | struct dwc3 *dwc; | |
776 | unsigned long flags; | |
777 | int ret; | |
778 | ||
779 | if (!ep) { | |
780 | pr_debug("dwc3: invalid parameters\n"); | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | dep = to_dwc3_ep(ep); | |
785 | dwc = dep->dwc; | |
786 | ||
95ca961c FB |
787 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
788 | "%s is already disabled\n", | |
789 | dep->name)) | |
72246da4 | 790 | return 0; |
72246da4 | 791 | |
72246da4 FB |
792 | spin_lock_irqsave(&dwc->lock, flags); |
793 | ret = __dwc3_gadget_ep_disable(dep); | |
794 | spin_unlock_irqrestore(&dwc->lock, flags); | |
795 | ||
796 | return ret; | |
797 | } | |
798 | ||
799 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
800 | gfp_t gfp_flags) | |
801 | { | |
802 | struct dwc3_request *req; | |
803 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
804 | |
805 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 806 | if (!req) |
72246da4 | 807 | return NULL; |
72246da4 FB |
808 | |
809 | req->epnum = dep->number; | |
810 | req->dep = dep; | |
72246da4 | 811 | |
68d34c8a FB |
812 | dep->allocated_requests++; |
813 | ||
2c4cbe6e FB |
814 | trace_dwc3_alloc_request(req); |
815 | ||
72246da4 FB |
816 | return &req->request; |
817 | } | |
818 | ||
819 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
820 | struct usb_request *request) | |
821 | { | |
822 | struct dwc3_request *req = to_dwc3_request(request); | |
68d34c8a | 823 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
72246da4 | 824 | |
68d34c8a | 825 | dep->allocated_requests--; |
2c4cbe6e | 826 | trace_dwc3_free_request(req); |
72246da4 FB |
827 | kfree(req); |
828 | } | |
829 | ||
2c78c029 FB |
830 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep); |
831 | ||
c71fc37c FB |
832 | /** |
833 | * dwc3_prepare_one_trb - setup one TRB from one request | |
834 | * @dep: endpoint for which this request is prepared | |
835 | * @req: dwc3_request pointer | |
836 | */ | |
68e823e2 | 837 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 838 | struct dwc3_request *req, dma_addr_t dma, |
4bc48c97 | 839 | unsigned length, unsigned chain, unsigned node) |
c71fc37c | 840 | { |
f6bafc6a | 841 | struct dwc3_trb *trb; |
6b9018d4 FB |
842 | struct dwc3 *dwc = dep->dwc; |
843 | struct usb_gadget *gadget = &dwc->gadget; | |
844 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 845 | |
4faf7550 | 846 | trb = &dep->trb_pool[dep->trb_enqueue]; |
c71fc37c | 847 | |
eeb720fb | 848 | if (!req->trb) { |
aa3342c8 | 849 | dwc3_gadget_move_started_request(req); |
f6bafc6a FB |
850 | req->trb = trb; |
851 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
a9c3ca5f | 852 | dep->queued_requests++; |
eeb720fb | 853 | } |
c71fc37c | 854 | |
ef966b9d | 855 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 856 | |
f6bafc6a FB |
857 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
858 | trb->bpl = lower_32_bits(dma); | |
859 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 860 | |
16e78db7 | 861 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 862 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 863 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
864 | break; |
865 | ||
866 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 867 | if (!node) { |
e5ba5ec8 | 868 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 FB |
869 | |
870 | if (speed == USB_SPEED_HIGH) { | |
871 | struct usb_ep *ep = &dep->endpoint; | |
872 | trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1); | |
873 | } | |
874 | } else { | |
e5ba5ec8 | 875 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 876 | } |
ca4d44ea FB |
877 | |
878 | /* always enable Interrupt on Missed ISOC */ | |
879 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
880 | break; |
881 | ||
882 | case USB_ENDPOINT_XFER_BULK: | |
883 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 884 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
885 | break; |
886 | default: | |
887 | /* | |
888 | * This is only possible with faulty memory because we | |
889 | * checked it already :) | |
890 | */ | |
0a695d4c FB |
891 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
892 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
893 | } |
894 | ||
ca4d44ea | 895 | /* always enable Continue on Short Packet */ |
c9508c8c | 896 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
58f29034 | 897 | trb->ctrl |= DWC3_TRB_CTRL_CSP; |
f3af3651 | 898 | |
c9508c8c FB |
899 | if (req->request.short_not_ok) |
900 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
901 | } | |
902 | ||
2c78c029 FB |
903 | if ((!req->request.no_interrupt && !chain) || |
904 | (dwc3_calc_trbs_left(dep) == 0)) | |
c9508c8c | 905 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 906 | |
e5ba5ec8 PA |
907 | if (chain) |
908 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
909 | ||
16e78db7 | 910 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 911 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 912 | |
f6bafc6a | 913 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
914 | |
915 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
916 | } |
917 | ||
361572b5 JY |
918 | /** |
919 | * dwc3_ep_prev_trb() - Returns the previous TRB in the ring | |
920 | * @dep: The endpoint with the TRB ring | |
921 | * @index: The index of the current TRB in the ring | |
922 | * | |
923 | * Returns the TRB prior to the one pointed to by the index. If the | |
924 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
925 | * the one just before that. | |
926 | */ | |
927 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
928 | { | |
45438a0c | 929 | u8 tmp = index; |
361572b5 | 930 | |
45438a0c FB |
931 | if (!tmp) |
932 | tmp = DWC3_TRB_NUM - 1; | |
361572b5 | 933 | |
45438a0c | 934 | return &dep->trb_pool[tmp - 1]; |
361572b5 JY |
935 | } |
936 | ||
c4233573 FB |
937 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) |
938 | { | |
939 | struct dwc3_trb *tmp; | |
32db3d94 | 940 | u8 trbs_left; |
c4233573 FB |
941 | |
942 | /* | |
943 | * If enqueue & dequeue are equal than it is either full or empty. | |
944 | * | |
945 | * One way to know for sure is if the TRB right before us has HWO bit | |
946 | * set or not. If it has, then we're definitely full and can't fit any | |
947 | * more transfers in our ring. | |
948 | */ | |
949 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
361572b5 JY |
950 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); |
951 | if (tmp->ctrl & DWC3_TRB_CTRL_HWO) | |
952 | return 0; | |
c4233573 FB |
953 | |
954 | return DWC3_TRB_NUM - 1; | |
955 | } | |
956 | ||
9d7aba77 | 957 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; |
3de2685f | 958 | trbs_left &= (DWC3_TRB_NUM - 1); |
32db3d94 | 959 | |
9d7aba77 JY |
960 | if (dep->trb_dequeue < dep->trb_enqueue) |
961 | trbs_left--; | |
962 | ||
32db3d94 | 963 | return trbs_left; |
c4233573 FB |
964 | } |
965 | ||
5ee85d89 | 966 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 967 | struct dwc3_request *req) |
5ee85d89 | 968 | { |
1f512119 | 969 | struct scatterlist *sg = req->sg; |
5ee85d89 | 970 | struct scatterlist *s; |
5ee85d89 FB |
971 | unsigned int length; |
972 | dma_addr_t dma; | |
973 | int i; | |
974 | ||
1f512119 | 975 | for_each_sg(sg, s, req->num_pending_sgs, i) { |
5ee85d89 FB |
976 | unsigned chain = true; |
977 | ||
978 | length = sg_dma_len(s); | |
979 | dma = sg_dma_address(s); | |
980 | ||
4bc48c97 | 981 | if (sg_is_last(s)) |
5ee85d89 FB |
982 | chain = false; |
983 | ||
984 | dwc3_prepare_one_trb(dep, req, dma, length, | |
4bc48c97 | 985 | chain, i); |
5ee85d89 | 986 | |
7ae7df49 | 987 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
988 | break; |
989 | } | |
990 | } | |
991 | ||
992 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 993 | struct dwc3_request *req) |
5ee85d89 | 994 | { |
5ee85d89 FB |
995 | unsigned int length; |
996 | dma_addr_t dma; | |
997 | ||
998 | dma = req->request.dma; | |
999 | length = req->request.length; | |
1000 | ||
5ee85d89 | 1001 | dwc3_prepare_one_trb(dep, req, dma, length, |
4bc48c97 | 1002 | false, 0); |
5ee85d89 FB |
1003 | } |
1004 | ||
72246da4 FB |
1005 | /* |
1006 | * dwc3_prepare_trbs - setup TRBs from requests | |
1007 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1008 | * |
1d046793 PZ |
1009 | * The function goes through the requests list and sets up TRBs for the |
1010 | * transfers. The function returns once there are no more TRBs available or | |
1011 | * it runs out of requests. | |
72246da4 | 1012 | */ |
c4233573 | 1013 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1014 | { |
68e823e2 | 1015 | struct dwc3_request *req, *n; |
72246da4 FB |
1016 | |
1017 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1018 | ||
7ae7df49 | 1019 | if (!dwc3_calc_trbs_left(dep)) |
89bc856e | 1020 | return; |
72246da4 | 1021 | |
d86c5a67 FB |
1022 | /* |
1023 | * We can get in a situation where there's a request in the started list | |
1024 | * but there weren't enough TRBs to fully kick it in the first time | |
1025 | * around, so it has been waiting for more TRBs to be freed up. | |
1026 | * | |
1027 | * In that case, we should check if we have a request with pending_sgs | |
1028 | * in the started list and prepare TRBs for that request first, | |
1029 | * otherwise we will prepare TRBs completely out of order and that will | |
1030 | * break things. | |
1031 | */ | |
1032 | list_for_each_entry(req, &dep->started_list, list) { | |
1033 | if (req->num_pending_sgs > 0) | |
1034 | dwc3_prepare_one_trb_sg(dep, req); | |
1035 | ||
1036 | if (!dwc3_calc_trbs_left(dep)) | |
1037 | return; | |
1038 | } | |
1039 | ||
aa3342c8 | 1040 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
1f512119 | 1041 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1042 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1043 | else |
7ae7df49 | 1044 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1045 | |
7ae7df49 | 1046 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1047 | return; |
72246da4 | 1048 | } |
72246da4 FB |
1049 | } |
1050 | ||
4fae2e3e | 1051 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) |
72246da4 FB |
1052 | { |
1053 | struct dwc3_gadget_ep_cmd_params params; | |
1054 | struct dwc3_request *req; | |
4fae2e3e | 1055 | int starting; |
72246da4 FB |
1056 | int ret; |
1057 | u32 cmd; | |
1058 | ||
4fae2e3e | 1059 | starting = !(dep->flags & DWC3_EP_BUSY); |
72246da4 | 1060 | |
4fae2e3e FB |
1061 | dwc3_prepare_trbs(dep); |
1062 | req = next_request(&dep->started_list); | |
72246da4 FB |
1063 | if (!req) { |
1064 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1069 | |
4fae2e3e | 1070 | if (starting) { |
1877d6c9 PA |
1071 | params.param0 = upper_32_bits(req->trb_dma); |
1072 | params.param1 = lower_32_bits(req->trb_dma); | |
b6b1c6db FB |
1073 | cmd = DWC3_DEPCMD_STARTTRANSFER | |
1074 | DWC3_DEPCMD_PARAM(cmd_param); | |
1877d6c9 | 1075 | } else { |
b6b1c6db FB |
1076 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1077 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1078 | } |
72246da4 | 1079 | |
2cd4718d | 1080 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1081 | if (ret < 0) { |
72246da4 FB |
1082 | /* |
1083 | * FIXME we need to iterate over the list of requests | |
1084 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1085 | * requests instead of what we do now. |
72246da4 | 1086 | */ |
ce3fc8b3 JD |
1087 | if (req->trb) |
1088 | memset(req->trb, 0, sizeof(struct dwc3_trb)); | |
8ab89da4 | 1089 | dep->queued_requests--; |
15b8d933 | 1090 | dwc3_gadget_giveback(dep, req, ret); |
72246da4 FB |
1091 | return ret; |
1092 | } | |
1093 | ||
1094 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1095 | |
4fae2e3e | 1096 | if (starting) { |
2eb88016 | 1097 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
b4996a86 | 1098 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1099 | } |
25b8ff68 | 1100 | |
72246da4 FB |
1101 | return 0; |
1102 | } | |
1103 | ||
6cb2e4e3 FB |
1104 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1105 | { | |
1106 | u32 reg; | |
1107 | ||
1108 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1109 | return DWC3_DSTS_SOFFN(reg); | |
1110 | } | |
1111 | ||
d6d6ec7b PA |
1112 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1113 | struct dwc3_ep *dep, u32 cur_uf) | |
1114 | { | |
1115 | u32 uf; | |
1116 | ||
aa3342c8 | 1117 | if (list_empty(&dep->pending_list)) { |
5eb30ced | 1118 | dev_info(dwc->dev, "%s: ran out of requests\n", |
73815280 | 1119 | dep->name); |
f4a53c55 | 1120 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1121 | return; |
1122 | } | |
1123 | ||
1124 | /* 4 micro frames in the future */ | |
1125 | uf = cur_uf + dep->interval * 4; | |
1126 | ||
4fae2e3e | 1127 | __dwc3_gadget_kick_transfer(dep, uf); |
d6d6ec7b PA |
1128 | } |
1129 | ||
1130 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1131 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1132 | { | |
1133 | u32 cur_uf, mask; | |
1134 | ||
1135 | mask = ~(dep->interval - 1); | |
1136 | cur_uf = event->parameters & mask; | |
1137 | ||
1138 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1139 | } | |
1140 | ||
72246da4 FB |
1141 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1142 | { | |
0fc9a1be FB |
1143 | struct dwc3 *dwc = dep->dwc; |
1144 | int ret; | |
1145 | ||
bb423984 | 1146 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1147 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1148 | dep->name); | |
bb423984 FB |
1149 | return -ESHUTDOWN; |
1150 | } | |
1151 | ||
1152 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1153 | &req->request, req->dep->name)) { | |
5eb30ced FB |
1154 | dev_err(dwc->dev, "%s: request %p belongs to '%s'\n", |
1155 | dep->name, &req->request, req->dep->name); | |
bb423984 FB |
1156 | return -EINVAL; |
1157 | } | |
1158 | ||
fc8bb91b FB |
1159 | pm_runtime_get(dwc->dev); |
1160 | ||
72246da4 FB |
1161 | req->request.actual = 0; |
1162 | req->request.status = -EINPROGRESS; | |
1163 | req->direction = dep->direction; | |
1164 | req->epnum = dep->number; | |
1165 | ||
fe84f522 FB |
1166 | trace_dwc3_ep_queue(req); |
1167 | ||
0fc9a1be FB |
1168 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1169 | dep->direction); | |
1170 | if (ret) | |
1171 | return ret; | |
1172 | ||
1f512119 FB |
1173 | req->sg = req->request.sg; |
1174 | req->num_pending_sgs = req->request.num_mapped_sgs; | |
89185916 | 1175 | |
aa3342c8 | 1176 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1177 | |
d889c23c FB |
1178 | /* |
1179 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1180 | * wait for a XferNotReady event so we will know what's the current | |
1181 | * (micro-)frame number. | |
1182 | * | |
1183 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1184 | * errors which will force us issue EndTransfer command. | |
1185 | */ | |
1186 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
6cb2e4e3 FB |
1187 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
1188 | if (dep->flags & DWC3_EP_TRANSFER_STARTED) { | |
1189 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
1190 | dep->flags = DWC3_EP_ENABLED; | |
1191 | } else { | |
1192 | u32 cur_uf; | |
1193 | ||
1194 | cur_uf = __dwc3_gadget_get_frame(dwc); | |
1195 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1196 | } | |
08a36b54 FB |
1197 | } |
1198 | return 0; | |
a0925324 | 1199 | } |
72246da4 | 1200 | |
594e121f FB |
1201 | if (!dwc3_calc_trbs_left(dep)) |
1202 | return 0; | |
b997ada5 | 1203 | |
08a36b54 | 1204 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
a8f32817 FB |
1205 | if (ret == -EBUSY) |
1206 | ret = 0; | |
1207 | ||
1208 | return ret; | |
72246da4 FB |
1209 | } |
1210 | ||
04c03d10 FB |
1211 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, |
1212 | struct usb_request *request) | |
1213 | { | |
1214 | dwc3_gadget_ep_free_request(ep, request); | |
1215 | } | |
1216 | ||
1217 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1218 | { | |
1219 | struct dwc3_request *req; | |
1220 | struct usb_request *request; | |
1221 | struct usb_ep *ep = &dep->endpoint; | |
1222 | ||
04c03d10 FB |
1223 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); |
1224 | if (!request) | |
1225 | return -ENOMEM; | |
1226 | ||
1227 | request->length = 0; | |
1228 | request->buf = dwc->zlp_buf; | |
1229 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1230 | ||
1231 | req = to_dwc3_request(request); | |
1232 | ||
1233 | return __dwc3_gadget_ep_queue(dep, req); | |
1234 | } | |
1235 | ||
72246da4 FB |
1236 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, |
1237 | gfp_t gfp_flags) | |
1238 | { | |
1239 | struct dwc3_request *req = to_dwc3_request(request); | |
1240 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1241 | struct dwc3 *dwc = dep->dwc; | |
1242 | ||
1243 | unsigned long flags; | |
1244 | ||
1245 | int ret; | |
1246 | ||
fdee4eba | 1247 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1248 | ret = __dwc3_gadget_ep_queue(dep, req); |
04c03d10 FB |
1249 | |
1250 | /* | |
1251 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1252 | * setting request->zero, instead of doing magic, we will just queue an | |
1253 | * extra usb_request ourselves so that it gets handled the same way as | |
1254 | * any other request. | |
1255 | */ | |
d9261898 JY |
1256 | if (ret == 0 && request->zero && request->length && |
1257 | (request->length % ep->maxpacket == 0)) | |
04c03d10 FB |
1258 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); |
1259 | ||
72246da4 FB |
1260 | spin_unlock_irqrestore(&dwc->lock, flags); |
1261 | ||
1262 | return ret; | |
1263 | } | |
1264 | ||
1265 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1266 | struct usb_request *request) | |
1267 | { | |
1268 | struct dwc3_request *req = to_dwc3_request(request); | |
1269 | struct dwc3_request *r = NULL; | |
1270 | ||
1271 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1272 | struct dwc3 *dwc = dep->dwc; | |
1273 | ||
1274 | unsigned long flags; | |
1275 | int ret = 0; | |
1276 | ||
2c4cbe6e FB |
1277 | trace_dwc3_ep_dequeue(req); |
1278 | ||
72246da4 FB |
1279 | spin_lock_irqsave(&dwc->lock, flags); |
1280 | ||
aa3342c8 | 1281 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1282 | if (r == req) |
1283 | break; | |
1284 | } | |
1285 | ||
1286 | if (r != req) { | |
aa3342c8 | 1287 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1288 | if (r == req) |
1289 | break; | |
1290 | } | |
1291 | if (r == req) { | |
1292 | /* wait until it is processed */ | |
b992e681 | 1293 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1294 | goto out1; |
72246da4 FB |
1295 | } |
1296 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1297 | request, ep->name); | |
1298 | ret = -EINVAL; | |
1299 | goto out0; | |
1300 | } | |
1301 | ||
e8d4e8be | 1302 | out1: |
72246da4 FB |
1303 | /* giveback the request */ |
1304 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1305 | ||
1306 | out0: | |
1307 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1308 | ||
1309 | return ret; | |
1310 | } | |
1311 | ||
7a608559 | 1312 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1313 | { |
1314 | struct dwc3_gadget_ep_cmd_params params; | |
1315 | struct dwc3 *dwc = dep->dwc; | |
1316 | int ret; | |
1317 | ||
5ad02fb8 FB |
1318 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1319 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1320 | return -EINVAL; | |
1321 | } | |
1322 | ||
72246da4 FB |
1323 | memset(¶ms, 0x00, sizeof(params)); |
1324 | ||
1325 | if (value) { | |
69450c4d FB |
1326 | struct dwc3_trb *trb; |
1327 | ||
1328 | unsigned transfer_in_flight; | |
1329 | unsigned started; | |
1330 | ||
1331 | if (dep->number > 1) | |
1332 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1333 | else | |
1334 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1335 | ||
1336 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1337 | started = !list_empty(&dep->started_list); | |
1338 | ||
1339 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1340 | (!dep->direction && started))) { | |
7a608559 FB |
1341 | return -EAGAIN; |
1342 | } | |
1343 | ||
2cd4718d FB |
1344 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1345 | ¶ms); | |
72246da4 | 1346 | if (ret) |
3f89204b | 1347 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1348 | dep->name); |
1349 | else | |
1350 | dep->flags |= DWC3_EP_STALL; | |
1351 | } else { | |
2cd4718d | 1352 | |
50c763f8 | 1353 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1354 | if (ret) |
3f89204b | 1355 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1356 | dep->name); |
1357 | else | |
a535d81c | 1358 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1359 | } |
5275455a | 1360 | |
72246da4 FB |
1361 | return ret; |
1362 | } | |
1363 | ||
1364 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1365 | { | |
1366 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1367 | struct dwc3 *dwc = dep->dwc; | |
1368 | ||
1369 | unsigned long flags; | |
1370 | ||
1371 | int ret; | |
1372 | ||
1373 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1374 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1375 | spin_unlock_irqrestore(&dwc->lock, flags); |
1376 | ||
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1381 | { | |
1382 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1383 | struct dwc3 *dwc = dep->dwc; |
1384 | unsigned long flags; | |
95aa4e8d | 1385 | int ret; |
72246da4 | 1386 | |
249a4569 | 1387 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1388 | dep->flags |= DWC3_EP_WEDGE; |
1389 | ||
08f0d966 | 1390 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1391 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1392 | else |
7a608559 | 1393 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1394 | spin_unlock_irqrestore(&dwc->lock, flags); |
1395 | ||
1396 | return ret; | |
72246da4 FB |
1397 | } |
1398 | ||
1399 | /* -------------------------------------------------------------------------- */ | |
1400 | ||
1401 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1402 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1403 | .bDescriptorType = USB_DT_ENDPOINT, | |
1404 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1405 | }; | |
1406 | ||
1407 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1408 | .enable = dwc3_gadget_ep0_enable, | |
1409 | .disable = dwc3_gadget_ep0_disable, | |
1410 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1411 | .free_request = dwc3_gadget_ep_free_request, | |
1412 | .queue = dwc3_gadget_ep0_queue, | |
1413 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1414 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1415 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1416 | }; | |
1417 | ||
1418 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1419 | .enable = dwc3_gadget_ep_enable, | |
1420 | .disable = dwc3_gadget_ep_disable, | |
1421 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1422 | .free_request = dwc3_gadget_ep_free_request, | |
1423 | .queue = dwc3_gadget_ep_queue, | |
1424 | .dequeue = dwc3_gadget_ep_dequeue, | |
1425 | .set_halt = dwc3_gadget_ep_set_halt, | |
1426 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1427 | }; | |
1428 | ||
1429 | /* -------------------------------------------------------------------------- */ | |
1430 | ||
1431 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1432 | { | |
1433 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1434 | |
6cb2e4e3 | 1435 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1436 | } |
1437 | ||
218ef7b6 | 1438 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1439 | { |
d6011f6f | 1440 | int retries; |
72246da4 | 1441 | |
218ef7b6 | 1442 | int ret; |
72246da4 FB |
1443 | u32 reg; |
1444 | ||
72246da4 FB |
1445 | u8 link_state; |
1446 | u8 speed; | |
1447 | ||
72246da4 FB |
1448 | /* |
1449 | * According to the Databook Remote wakeup request should | |
1450 | * be issued only when the device is in early suspend state. | |
1451 | * | |
1452 | * We can check that via USB Link State bits in DSTS register. | |
1453 | */ | |
1454 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1455 | ||
1456 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c | 1457 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
5eb30ced | 1458 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) |
6b742899 | 1459 | return 0; |
72246da4 FB |
1460 | |
1461 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1462 | ||
1463 | switch (link_state) { | |
1464 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1465 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1466 | break; | |
1467 | default: | |
218ef7b6 | 1468 | return -EINVAL; |
72246da4 FB |
1469 | } |
1470 | ||
8598bde7 FB |
1471 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1472 | if (ret < 0) { | |
1473 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1474 | return ret; |
8598bde7 | 1475 | } |
72246da4 | 1476 | |
802fde98 PZ |
1477 | /* Recent versions do this automatically */ |
1478 | if (dwc->revision < DWC3_REVISION_194A) { | |
1479 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1480 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1481 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1482 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1483 | } | |
72246da4 | 1484 | |
1d046793 | 1485 | /* poll until Link State changes to ON */ |
d6011f6f | 1486 | retries = 20000; |
72246da4 | 1487 | |
d6011f6f | 1488 | while (retries--) { |
72246da4 FB |
1489 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1490 | ||
1491 | /* in HS, means ON */ | |
1492 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1493 | break; | |
1494 | } | |
1495 | ||
1496 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1497 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1498 | return -EINVAL; |
72246da4 FB |
1499 | } |
1500 | ||
218ef7b6 FB |
1501 | return 0; |
1502 | } | |
1503 | ||
1504 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1505 | { | |
1506 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1507 | unsigned long flags; | |
1508 | int ret; | |
1509 | ||
1510 | spin_lock_irqsave(&dwc->lock, flags); | |
1511 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1512 | spin_unlock_irqrestore(&dwc->lock, flags); |
1513 | ||
1514 | return ret; | |
1515 | } | |
1516 | ||
1517 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1518 | int is_selfpowered) | |
1519 | { | |
1520 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1521 | unsigned long flags; |
72246da4 | 1522 | |
249a4569 | 1523 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1524 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1525 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1526 | |
1527 | return 0; | |
1528 | } | |
1529 | ||
7b2a0368 | 1530 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1531 | { |
1532 | u32 reg; | |
61d58242 | 1533 | u32 timeout = 500; |
72246da4 | 1534 | |
fc8bb91b FB |
1535 | if (pm_runtime_suspended(dwc->dev)) |
1536 | return 0; | |
1537 | ||
72246da4 | 1538 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1539 | if (is_on) { |
802fde98 PZ |
1540 | if (dwc->revision <= DWC3_REVISION_187A) { |
1541 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1542 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1543 | } | |
1544 | ||
1545 | if (dwc->revision >= DWC3_REVISION_194A) | |
1546 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1547 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1548 | |
1549 | if (dwc->has_hibernation) | |
1550 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1551 | ||
9fcb3bd8 | 1552 | dwc->pullups_connected = true; |
8db7ed15 | 1553 | } else { |
72246da4 | 1554 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1555 | |
1556 | if (dwc->has_hibernation && !suspend) | |
1557 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1558 | ||
9fcb3bd8 | 1559 | dwc->pullups_connected = false; |
8db7ed15 | 1560 | } |
72246da4 FB |
1561 | |
1562 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1563 | ||
1564 | do { | |
1565 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1566 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1567 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1568 | |
1569 | if (!timeout) | |
1570 | return -ETIMEDOUT; | |
72246da4 | 1571 | |
6f17f74b | 1572 | return 0; |
72246da4 FB |
1573 | } |
1574 | ||
1575 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1576 | { | |
1577 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1578 | unsigned long flags; | |
6f17f74b | 1579 | int ret; |
72246da4 FB |
1580 | |
1581 | is_on = !!is_on; | |
1582 | ||
bb014736 BW |
1583 | /* |
1584 | * Per databook, when we want to stop the gadget, if a control transfer | |
1585 | * is still in process, complete it and get the core into setup phase. | |
1586 | */ | |
1587 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1588 | reinit_completion(&dwc->ep0_in_setup); | |
1589 | ||
1590 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1591 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1592 | if (ret == 0) { | |
1593 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1594 | return -ETIMEDOUT; | |
1595 | } | |
1596 | } | |
1597 | ||
72246da4 | 1598 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1599 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1600 | spin_unlock_irqrestore(&dwc->lock, flags); |
1601 | ||
6f17f74b | 1602 | return ret; |
72246da4 FB |
1603 | } |
1604 | ||
8698e2ac FB |
1605 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1606 | { | |
1607 | u32 reg; | |
1608 | ||
1609 | /* Enable all but Start and End of Frame IRQs */ | |
1610 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1611 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1612 | DWC3_DEVTEN_CMDCMPLTEN | | |
1613 | DWC3_DEVTEN_ERRTICERREN | | |
1614 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1615 | DWC3_DEVTEN_CONNECTDONEEN | |
1616 | DWC3_DEVTEN_USBRSTEN | | |
1617 | DWC3_DEVTEN_DISCONNEVTEN); | |
1618 | ||
799e9dc8 FB |
1619 | if (dwc->revision < DWC3_REVISION_250A) |
1620 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1621 | ||
8698e2ac FB |
1622 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1623 | } | |
1624 | ||
1625 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1626 | { | |
1627 | /* mask all interrupts */ | |
1628 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1629 | } | |
1630 | ||
1631 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1632 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1633 | |
4e99472b FB |
1634 | /** |
1635 | * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG | |
1636 | * dwc: pointer to our context structure | |
1637 | * | |
1638 | * The following looks like complex but it's actually very simple. In order to | |
1639 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1640 | * gonna use RxFIFO size. | |
1641 | * | |
1642 | * To calculate RxFIFO size we need two numbers: | |
1643 | * MDWIDTH = size, in bits, of the internal memory bus | |
1644 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1645 | * | |
1646 | * Given these two numbers, the formula is simple: | |
1647 | * | |
1648 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1649 | * | |
1650 | * 24 bytes is for 3x SETUP packets | |
1651 | * 16 bytes is a clock domain crossing tolerance | |
1652 | * | |
1653 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1654 | */ | |
1655 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1656 | { | |
1657 | u32 ram2_depth; | |
1658 | u32 mdwidth; | |
1659 | u32 nump; | |
1660 | u32 reg; | |
1661 | ||
1662 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1663 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1664 | ||
1665 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1666 | nump = min_t(u32, nump, 16); | |
1667 | ||
1668 | /* update NumP */ | |
1669 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1670 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1671 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1672 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1673 | } | |
1674 | ||
d7be2952 | 1675 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1676 | { |
72246da4 | 1677 | struct dwc3_ep *dep; |
72246da4 FB |
1678 | int ret = 0; |
1679 | u32 reg; | |
1680 | ||
72246da4 FB |
1681 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1682 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1683 | |
1684 | /** | |
1685 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1686 | * which would cause metastability state on Run/Stop | |
1687 | * bit if we try to force the IP to USB2-only mode. | |
1688 | * | |
1689 | * Because of that, we cannot configure the IP to any | |
1690 | * speed other than the SuperSpeed | |
1691 | * | |
1692 | * Refers to: | |
1693 | * | |
1694 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1695 | * USB 2.0 Mode | |
1696 | */ | |
f7e846f0 | 1697 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1698 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1699 | } else { |
1700 | switch (dwc->maximum_speed) { | |
1701 | case USB_SPEED_LOW: | |
2da9ad76 | 1702 | reg |= DWC3_DCFG_LOWSPEED; |
f7e846f0 FB |
1703 | break; |
1704 | case USB_SPEED_FULL: | |
2da9ad76 | 1705 | reg |= DWC3_DCFG_FULLSPEED1; |
f7e846f0 FB |
1706 | break; |
1707 | case USB_SPEED_HIGH: | |
2da9ad76 | 1708 | reg |= DWC3_DCFG_HIGHSPEED; |
f7e846f0 | 1709 | break; |
7580862b | 1710 | case USB_SPEED_SUPER_PLUS: |
2da9ad76 | 1711 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; |
7580862b | 1712 | break; |
f7e846f0 | 1713 | default: |
77966eb8 JY |
1714 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1715 | dwc->maximum_speed); | |
1716 | /* fall through */ | |
1717 | case USB_SPEED_SUPER: | |
1718 | reg |= DWC3_DCFG_SUPERSPEED; | |
1719 | break; | |
f7e846f0 FB |
1720 | } |
1721 | } | |
72246da4 FB |
1722 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1723 | ||
2a58f9c1 FB |
1724 | /* |
1725 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1726 | * field instead of letting dwc3 itself calculate that automatically. | |
1727 | * | |
1728 | * This way, we maximize the chances that we'll be able to get several | |
1729 | * bursts of data without going through any sort of endpoint throttling. | |
1730 | */ | |
1731 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1732 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1733 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1734 | ||
4e99472b FB |
1735 | dwc3_gadget_setup_nump(dwc); |
1736 | ||
72246da4 FB |
1737 | /* Start with SuperSpeed Default */ |
1738 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1739 | ||
1740 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1741 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1742 | false); | |
72246da4 FB |
1743 | if (ret) { |
1744 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1745 | goto err0; |
72246da4 FB |
1746 | } |
1747 | ||
1748 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1749 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1750 | false); | |
72246da4 FB |
1751 | if (ret) { |
1752 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1753 | goto err1; |
72246da4 FB |
1754 | } |
1755 | ||
1756 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1757 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1758 | dwc3_ep0_out_start(dwc); |
1759 | ||
8698e2ac FB |
1760 | dwc3_gadget_enable_irq(dwc); |
1761 | ||
72246da4 FB |
1762 | return 0; |
1763 | ||
b0d7ffd4 | 1764 | err1: |
d7be2952 | 1765 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1766 | |
1767 | err0: | |
72246da4 FB |
1768 | return ret; |
1769 | } | |
1770 | ||
d7be2952 FB |
1771 | static int dwc3_gadget_start(struct usb_gadget *g, |
1772 | struct usb_gadget_driver *driver) | |
72246da4 FB |
1773 | { |
1774 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1775 | unsigned long flags; | |
d7be2952 | 1776 | int ret = 0; |
8698e2ac | 1777 | int irq; |
72246da4 | 1778 | |
9522def4 | 1779 | irq = dwc->irq_gadget; |
d7be2952 FB |
1780 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
1781 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1782 | if (ret) { | |
1783 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1784 | irq, ret); | |
1785 | goto err0; | |
1786 | } | |
1787 | ||
72246da4 | 1788 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
1789 | if (dwc->gadget_driver) { |
1790 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1791 | dwc->gadget.name, | |
1792 | dwc->gadget_driver->driver.name); | |
1793 | ret = -EBUSY; | |
1794 | goto err1; | |
1795 | } | |
1796 | ||
1797 | dwc->gadget_driver = driver; | |
1798 | ||
fc8bb91b FB |
1799 | if (pm_runtime_active(dwc->dev)) |
1800 | __dwc3_gadget_start(dwc); | |
1801 | ||
d7be2952 FB |
1802 | spin_unlock_irqrestore(&dwc->lock, flags); |
1803 | ||
1804 | return 0; | |
1805 | ||
1806 | err1: | |
1807 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1808 | free_irq(irq, dwc); | |
1809 | ||
1810 | err0: | |
1811 | return ret; | |
1812 | } | |
72246da4 | 1813 | |
d7be2952 FB |
1814 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
1815 | { | |
8698e2ac | 1816 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1817 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1818 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 1819 | } |
72246da4 | 1820 | |
d7be2952 FB |
1821 | static int dwc3_gadget_stop(struct usb_gadget *g) |
1822 | { | |
1823 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1824 | unsigned long flags; | |
76a638f8 | 1825 | int epnum; |
72246da4 | 1826 | |
d7be2952 | 1827 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
1828 | |
1829 | if (pm_runtime_suspended(dwc->dev)) | |
1830 | goto out; | |
1831 | ||
d7be2952 | 1832 | __dwc3_gadget_stop(dwc); |
76a638f8 BW |
1833 | |
1834 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1835 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
1836 | ||
1837 | if (!dep) | |
1838 | continue; | |
1839 | ||
1840 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1841 | continue; | |
1842 | ||
1843 | wait_event_lock_irq(dep->wait_end_transfer, | |
1844 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING), | |
1845 | dwc->lock); | |
1846 | } | |
1847 | ||
1848 | out: | |
d7be2952 | 1849 | dwc->gadget_driver = NULL; |
72246da4 FB |
1850 | spin_unlock_irqrestore(&dwc->lock, flags); |
1851 | ||
3f308d17 | 1852 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 1853 | |
72246da4 FB |
1854 | return 0; |
1855 | } | |
802fde98 | 1856 | |
72246da4 FB |
1857 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1858 | .get_frame = dwc3_gadget_get_frame, | |
1859 | .wakeup = dwc3_gadget_wakeup, | |
1860 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1861 | .pullup = dwc3_gadget_pullup, | |
1862 | .udc_start = dwc3_gadget_start, | |
1863 | .udc_stop = dwc3_gadget_stop, | |
1864 | }; | |
1865 | ||
1866 | /* -------------------------------------------------------------------------- */ | |
1867 | ||
6a1e3ef4 FB |
1868 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1869 | u8 num, u32 direction) | |
72246da4 FB |
1870 | { |
1871 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1872 | u8 i; |
72246da4 | 1873 | |
6a1e3ef4 | 1874 | for (i = 0; i < num; i++) { |
d07fa665 | 1875 | u8 epnum = (i << 1) | (direction ? 1 : 0); |
72246da4 | 1876 | |
72246da4 | 1877 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1878 | if (!dep) |
72246da4 | 1879 | return -ENOMEM; |
72246da4 FB |
1880 | |
1881 | dep->dwc = dwc; | |
1882 | dep->number = epnum; | |
9aa62ae4 | 1883 | dep->direction = !!direction; |
2eb88016 | 1884 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); |
72246da4 FB |
1885 | dwc->eps[epnum] = dep; |
1886 | ||
1887 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1888 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1889 | |
72246da4 | 1890 | dep->endpoint.name = dep->name; |
74674cbf | 1891 | spin_lock_init(&dep->lock); |
72246da4 FB |
1892 | |
1893 | if (epnum == 0 || epnum == 1) { | |
e117e742 | 1894 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1895 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1896 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1897 | if (!epnum) | |
1898 | dwc->gadget.ep0 = &dep->endpoint; | |
1899 | } else { | |
1900 | int ret; | |
1901 | ||
e117e742 | 1902 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1903 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1904 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1905 | list_add_tail(&dep->endpoint.ep_list, | |
1906 | &dwc->gadget.ep_list); | |
1907 | ||
1908 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1909 | if (ret) |
72246da4 | 1910 | return ret; |
72246da4 | 1911 | } |
25b8ff68 | 1912 | |
a474d3b7 RB |
1913 | if (epnum == 0 || epnum == 1) { |
1914 | dep->endpoint.caps.type_control = true; | |
1915 | } else { | |
1916 | dep->endpoint.caps.type_iso = true; | |
1917 | dep->endpoint.caps.type_bulk = true; | |
1918 | dep->endpoint.caps.type_int = true; | |
1919 | } | |
1920 | ||
1921 | dep->endpoint.caps.dir_in = !!direction; | |
1922 | dep->endpoint.caps.dir_out = !direction; | |
1923 | ||
aa3342c8 FB |
1924 | INIT_LIST_HEAD(&dep->pending_list); |
1925 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
1926 | } |
1927 | ||
1928 | return 0; | |
1929 | } | |
1930 | ||
6a1e3ef4 FB |
1931 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1932 | { | |
1933 | int ret; | |
1934 | ||
1935 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1936 | ||
1937 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1938 | if (ret < 0) { | |
5eb30ced | 1939 | dev_err(dwc->dev, "failed to initialize OUT endpoints\n"); |
6a1e3ef4 FB |
1940 | return ret; |
1941 | } | |
1942 | ||
1943 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1944 | if (ret < 0) { | |
5eb30ced | 1945 | dev_err(dwc->dev, "failed to initialize IN endpoints\n"); |
6a1e3ef4 FB |
1946 | return ret; |
1947 | } | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
72246da4 FB |
1952 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1953 | { | |
1954 | struct dwc3_ep *dep; | |
1955 | u8 epnum; | |
1956 | ||
1957 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1958 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1959 | if (!dep) |
1960 | continue; | |
5bf8fae3 GC |
1961 | /* |
1962 | * Physical endpoints 0 and 1 are special; they form the | |
1963 | * bi-directional USB endpoint 0. | |
1964 | * | |
1965 | * For those two physical endpoints, we don't allocate a TRB | |
1966 | * pool nor do we add them the endpoints list. Due to that, we | |
1967 | * shouldn't do these two operations otherwise we would end up | |
1968 | * with all sorts of bugs when removing dwc3.ko. | |
1969 | */ | |
1970 | if (epnum != 0 && epnum != 1) { | |
1971 | dwc3_free_trb_pool(dep); | |
72246da4 | 1972 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1973 | } |
72246da4 FB |
1974 | |
1975 | kfree(dep); | |
1976 | } | |
1977 | } | |
1978 | ||
72246da4 | 1979 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1980 | |
e5ba5ec8 PA |
1981 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1982 | struct dwc3_request *req, struct dwc3_trb *trb, | |
e5b36ae2 FB |
1983 | const struct dwc3_event_depevt *event, int status, |
1984 | int chain) | |
72246da4 | 1985 | { |
72246da4 FB |
1986 | unsigned int count; |
1987 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1988 | unsigned int trb_status; |
72246da4 | 1989 | |
dc55c67e | 1990 | dwc3_ep_inc_deq(dep); |
a9c3ca5f FB |
1991 | |
1992 | if (req->trb == trb) | |
1993 | dep->queued_requests--; | |
1994 | ||
2c4cbe6e FB |
1995 | trace_dwc3_complete_trb(dep, trb); |
1996 | ||
e5b36ae2 FB |
1997 | /* |
1998 | * If we're in the middle of series of chained TRBs and we | |
1999 | * receive a short transfer along the way, DWC3 will skip | |
2000 | * through all TRBs including the last TRB in the chain (the | |
2001 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2002 | * bit and SW has to do it manually. | |
2003 | * | |
2004 | * We're going to do that here to avoid problems of HW trying | |
2005 | * to use bogus TRBs for transfers. | |
2006 | */ | |
2007 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2008 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2009 | ||
e5ba5ec8 | 2010 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
a0ad85ae | 2011 | return 1; |
e5b36ae2 | 2012 | |
e5ba5ec8 | 2013 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2014 | req->remaining += count; |
e5ba5ec8 PA |
2015 | |
2016 | if (dep->direction) { | |
2017 | if (count) { | |
2018 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
2019 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
e5ba5ec8 PA |
2020 | /* |
2021 | * If missed isoc occurred and there is | |
2022 | * no request queued then issue END | |
2023 | * TRANSFER, so that core generates | |
2024 | * next xfernotready and we will issue | |
2025 | * a fresh START TRANSFER. | |
2026 | * If there are still queued request | |
2027 | * then wait, do not issue either END | |
2028 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 2029 | * request in pending_list during |
e5ba5ec8 PA |
2030 | * giveback.If any future queued request |
2031 | * is successfully transferred then we | |
2032 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 2033 | * request in the pending_list. |
e5ba5ec8 PA |
2034 | */ |
2035 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
2036 | } else { | |
2037 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
2038 | dep->name); | |
2039 | status = -ECONNRESET; | |
2040 | } | |
2041 | } else { | |
2042 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
2043 | } | |
2044 | } else { | |
2045 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
2046 | s_pkt = 1; | |
2047 | } | |
2048 | ||
7c705dfe | 2049 | if (s_pkt && !chain) |
e5ba5ec8 | 2050 | return 1; |
f99f53f2 | 2051 | |
e5ba5ec8 PA |
2052 | if ((event->status & DEPEVT_STATUS_IOC) && |
2053 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2054 | return 1; | |
f99f53f2 | 2055 | |
e5ba5ec8 PA |
2056 | return 0; |
2057 | } | |
2058 | ||
2059 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
2060 | const struct dwc3_event_depevt *event, int status) | |
2061 | { | |
31162af4 | 2062 | struct dwc3_request *req, *n; |
e5ba5ec8 | 2063 | struct dwc3_trb *trb; |
d6e10bf2 | 2064 | bool ioc = false; |
e62c5bc5 | 2065 | int ret = 0; |
e5ba5ec8 | 2066 | |
31162af4 | 2067 | list_for_each_entry_safe(req, n, &dep->started_list, list) { |
1f512119 | 2068 | unsigned length; |
e5b36ae2 FB |
2069 | int chain; |
2070 | ||
1f512119 FB |
2071 | length = req->request.length; |
2072 | chain = req->num_pending_sgs > 0; | |
31162af4 | 2073 | if (chain) { |
1f512119 | 2074 | struct scatterlist *sg = req->sg; |
31162af4 | 2075 | struct scatterlist *s; |
1f512119 | 2076 | unsigned int pending = req->num_pending_sgs; |
31162af4 | 2077 | unsigned int i; |
c7de5734 | 2078 | |
1f512119 | 2079 | for_each_sg(sg, s, pending, i) { |
31162af4 | 2080 | trb = &dep->trb_pool[dep->trb_dequeue]; |
31162af4 | 2081 | |
7282c4ef FB |
2082 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) |
2083 | break; | |
2084 | ||
1f512119 FB |
2085 | req->sg = sg_next(s); |
2086 | req->num_pending_sgs--; | |
2087 | ||
31162af4 FB |
2088 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
2089 | event, status, chain); | |
1f512119 FB |
2090 | if (ret) |
2091 | break; | |
31162af4 FB |
2092 | } |
2093 | } else { | |
737f1ae2 | 2094 | trb = &dep->trb_pool[dep->trb_dequeue]; |
d115d705 | 2095 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
e5b36ae2 | 2096 | event, status, chain); |
31162af4 | 2097 | } |
d115d705 | 2098 | |
e62c5bc5 | 2099 | req->request.actual = length - req->remaining; |
1f512119 | 2100 | |
ff377ae4 | 2101 | if ((req->request.actual < length) && req->num_pending_sgs) |
1f512119 FB |
2102 | return __dwc3_gadget_kick_transfer(dep, 0); |
2103 | ||
d115d705 | 2104 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 | 2105 | |
d6e10bf2 AB |
2106 | if (ret) { |
2107 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2108 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2109 | ioc = true; | |
72246da4 | 2110 | break; |
d6e10bf2 | 2111 | } |
31162af4 | 2112 | } |
72246da4 | 2113 | |
4cb42217 FB |
2114 | /* |
2115 | * Our endpoint might get disabled by another thread during | |
2116 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2117 | * early on so DWC3_EP_BUSY flag gets cleared | |
2118 | */ | |
2119 | if (!dep->endpoint.desc) | |
2120 | return 1; | |
2121 | ||
cdc359dd | 2122 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
2123 | list_empty(&dep->started_list)) { |
2124 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
2125 | /* |
2126 | * If there is no entry in request list then do | |
2127 | * not issue END TRANSFER now. Just set PENDING | |
2128 | * flag, so that END TRANSFER is issued when an | |
2129 | * entry is added into request list. | |
2130 | */ | |
2131 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2132 | } else { | |
b992e681 | 2133 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
2134 | dep->flags = DWC3_EP_ENABLED; |
2135 | } | |
7efea86c PA |
2136 | return 1; |
2137 | } | |
2138 | ||
d6e10bf2 AB |
2139 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc) |
2140 | return 0; | |
2141 | ||
72246da4 FB |
2142 | return 1; |
2143 | } | |
2144 | ||
2145 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 2146 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
2147 | { |
2148 | unsigned status = 0; | |
2149 | int clean_busy; | |
e18b7975 FB |
2150 | u32 is_xfer_complete; |
2151 | ||
2152 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
2153 | |
2154 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2155 | status = -ECONNRESET; | |
2156 | ||
1d046793 | 2157 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
4cb42217 | 2158 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || |
e18b7975 | 2159 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) |
72246da4 | 2160 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2161 | |
2162 | /* | |
2163 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2164 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2165 | */ | |
2166 | if (dwc->revision < DWC3_REVISION_183A) { | |
2167 | u32 reg; | |
2168 | int i; | |
2169 | ||
2170 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2171 | dep = dwc->eps[i]; |
fae2b904 FB |
2172 | |
2173 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2174 | continue; | |
2175 | ||
aa3342c8 | 2176 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2177 | return; |
2178 | } | |
2179 | ||
2180 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2181 | reg |= dwc->u1u2; | |
2182 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2183 | ||
2184 | dwc->u1u2 = 0; | |
2185 | } | |
8a1a9c9e | 2186 | |
4cb42217 FB |
2187 | /* |
2188 | * Our endpoint might get disabled by another thread during | |
2189 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2190 | * early on so DWC3_EP_BUSY flag gets cleared | |
2191 | */ | |
2192 | if (!dep->endpoint.desc) | |
2193 | return; | |
2194 | ||
e6e709b7 | 2195 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2196 | int ret; |
2197 | ||
4fae2e3e | 2198 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
8a1a9c9e FB |
2199 | if (!ret || ret == -EBUSY) |
2200 | return; | |
2201 | } | |
72246da4 FB |
2202 | } |
2203 | ||
72246da4 FB |
2204 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2205 | const struct dwc3_event_depevt *event) | |
2206 | { | |
2207 | struct dwc3_ep *dep; | |
2208 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2209 | u8 cmd; |
72246da4 FB |
2210 | |
2211 | dep = dwc->eps[epnum]; | |
2212 | ||
76a638f8 BW |
2213 | if (!(dep->flags & DWC3_EP_ENABLED) && |
2214 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3336abb5 FB |
2215 | return; |
2216 | ||
72246da4 FB |
2217 | if (epnum == 0 || epnum == 1) { |
2218 | dwc3_ep0_interrupt(dwc, event); | |
2219 | return; | |
2220 | } | |
2221 | ||
2222 | switch (event->endpoint_event) { | |
2223 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2224 | dep->resource_index = 0; |
c2df85ca | 2225 | |
16e78db7 | 2226 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8566cd1a | 2227 | dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n"); |
72246da4 FB |
2228 | return; |
2229 | } | |
2230 | ||
029d97ff | 2231 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2232 | break; |
2233 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2234 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2235 | break; |
2236 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2237 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2238 | dwc3_gadget_start_isoc(dwc, dep, event); |
2239 | } else { | |
2240 | int ret; | |
2241 | ||
4fae2e3e | 2242 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
72246da4 FB |
2243 | if (!ret || ret == -EBUSY) |
2244 | return; | |
72246da4 FB |
2245 | } |
2246 | ||
879631aa FB |
2247 | break; |
2248 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2249 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2250 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2251 | dep->name); | |
2252 | return; | |
2253 | } | |
72246da4 | 2254 | break; |
72246da4 | 2255 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2256 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2257 | ||
2258 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
2259 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
2260 | wake_up(&dep->wait_end_transfer); | |
2261 | } | |
2262 | break; | |
2263 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
72246da4 FB |
2264 | break; |
2265 | } | |
2266 | } | |
2267 | ||
2268 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2269 | { | |
2270 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2271 | spin_unlock(&dwc->lock); | |
2272 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2273 | spin_lock(&dwc->lock); | |
2274 | } | |
2275 | } | |
2276 | ||
bc5ba2e0 FB |
2277 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2278 | { | |
73a30bfc | 2279 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2280 | spin_unlock(&dwc->lock); |
2281 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2282 | spin_lock(&dwc->lock); | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2287 | { | |
73a30bfc | 2288 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2289 | spin_unlock(&dwc->lock); |
2290 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2291 | spin_lock(&dwc->lock); |
8e74475b FB |
2292 | } |
2293 | } | |
2294 | ||
2295 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2296 | { | |
2297 | if (!dwc->gadget_driver) | |
2298 | return; | |
2299 | ||
2300 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2301 | spin_unlock(&dwc->lock); | |
2302 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2303 | spin_lock(&dwc->lock); |
2304 | } | |
2305 | } | |
2306 | ||
b992e681 | 2307 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2308 | { |
2309 | struct dwc3_ep *dep; | |
2310 | struct dwc3_gadget_ep_cmd_params params; | |
2311 | u32 cmd; | |
2312 | int ret; | |
2313 | ||
2314 | dep = dwc->eps[epnum]; | |
2315 | ||
76a638f8 BW |
2316 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || |
2317 | !dep->resource_index) | |
3daf74d7 PA |
2318 | return; |
2319 | ||
57911504 PA |
2320 | /* |
2321 | * NOTICE: We are violating what the Databook says about the | |
2322 | * EndTransfer command. Ideally we would _always_ wait for the | |
2323 | * EndTransfer Command Completion IRQ, but that's causing too | |
2324 | * much trouble synchronizing between us and gadget driver. | |
2325 | * | |
2326 | * We have discussed this with the IP Provider and it was | |
2327 | * suggested to giveback all requests here, but give HW some | |
2328 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2329 | * an arbitrary 100us delay for that. |
57911504 PA |
2330 | * |
2331 | * Note also that a similar handling was tested by Synopsys | |
2332 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2333 | * In short, what we're doing is: | |
2334 | * | |
2335 | * - Issue EndTransfer WITH CMDIOC bit set | |
2336 | * - Wait 100us | |
06281d46 JY |
2337 | * |
2338 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2339 | * supports a mode to work around the above limitation. The | |
2340 | * software can poll the CMDACT bit in the DEPCMD register | |
2341 | * after issuing a EndTransfer command. This mode is enabled | |
2342 | * by writing GUCTL2[14]. This polling is already done in the | |
2343 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2344 | * enabled, the EndTransfer command will have completed upon | |
2345 | * returning from this function and we don't need to delay for | |
2346 | * 100us. | |
2347 | * | |
2348 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2349 | */ |
2350 | ||
3daf74d7 | 2351 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2352 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2353 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2354 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2355 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2356 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2357 | WARN_ON_ONCE(ret); |
b4996a86 | 2358 | dep->resource_index = 0; |
041d81f4 | 2359 | dep->flags &= ~DWC3_EP_BUSY; |
06281d46 | 2360 | |
76a638f8 BW |
2361 | if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) { |
2362 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
06281d46 | 2363 | udelay(100); |
76a638f8 | 2364 | } |
72246da4 FB |
2365 | } |
2366 | ||
72246da4 FB |
2367 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2368 | { | |
2369 | u32 epnum; | |
2370 | ||
2371 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2372 | struct dwc3_ep *dep; | |
72246da4 FB |
2373 | int ret; |
2374 | ||
2375 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2376 | if (!dep) |
2377 | continue; | |
72246da4 FB |
2378 | |
2379 | if (!(dep->flags & DWC3_EP_STALL)) | |
2380 | continue; | |
2381 | ||
2382 | dep->flags &= ~DWC3_EP_STALL; | |
2383 | ||
50c763f8 | 2384 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2385 | WARN_ON_ONCE(ret); |
2386 | } | |
2387 | } | |
2388 | ||
2389 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2390 | { | |
c4430a26 FB |
2391 | int reg; |
2392 | ||
72246da4 FB |
2393 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2394 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2395 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2396 | ||
2397 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2398 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2399 | |
72246da4 FB |
2400 | dwc3_disconnect_gadget(dwc); |
2401 | ||
2402 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2403 | dwc->setup_packet_pending = false; |
06a374ed | 2404 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2405 | |
2406 | dwc->connected = false; | |
72246da4 FB |
2407 | } |
2408 | ||
72246da4 FB |
2409 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2410 | { | |
2411 | u32 reg; | |
2412 | ||
fc8bb91b FB |
2413 | dwc->connected = true; |
2414 | ||
df62df56 FB |
2415 | /* |
2416 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2417 | * would cause a missing Disconnect Event if there's a | |
2418 | * pending Setup Packet in the FIFO. | |
2419 | * | |
2420 | * There's no suggested workaround on the official Bug | |
2421 | * report, which states that "unless the driver/application | |
2422 | * is doing any special handling of a disconnect event, | |
2423 | * there is no functional issue". | |
2424 | * | |
2425 | * Unfortunately, it turns out that we _do_ some special | |
2426 | * handling of a disconnect event, namely complete all | |
2427 | * pending transfers, notify gadget driver of the | |
2428 | * disconnection, and so on. | |
2429 | * | |
2430 | * Our suggested workaround is to follow the Disconnect | |
2431 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2432 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2433 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2434 | * same endpoint. |
2435 | * | |
2436 | * Refers to: | |
2437 | * | |
2438 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2439 | * generated if setup packet pending in FIFO | |
2440 | */ | |
2441 | if (dwc->revision < DWC3_REVISION_188A) { | |
2442 | if (dwc->setup_packet_pending) | |
2443 | dwc3_gadget_disconnect_interrupt(dwc); | |
2444 | } | |
2445 | ||
8e74475b | 2446 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2447 | |
2448 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2449 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2450 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2451 | dwc->test_mode = false; |
72246da4 FB |
2452 | dwc3_clear_stall_all_ep(dwc); |
2453 | ||
2454 | /* Reset device address to zero */ | |
2455 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2456 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2457 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2458 | } |
2459 | ||
2460 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2461 | { | |
2462 | u32 reg; | |
2463 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2464 | ||
2465 | /* | |
2466 | * We change the clock only at SS but I dunno why I would want to do | |
2467 | * this. Maybe it becomes part of the power saving plan. | |
2468 | */ | |
2469 | ||
ee5cd41c JY |
2470 | if ((speed != DWC3_DSTS_SUPERSPEED) && |
2471 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
72246da4 FB |
2472 | return; |
2473 | ||
2474 | /* | |
2475 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2476 | * each time on Connect Done. | |
2477 | */ | |
2478 | if (!usb30_clock) | |
2479 | return; | |
2480 | ||
2481 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2482 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2483 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2484 | } | |
2485 | ||
72246da4 FB |
2486 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2487 | { | |
72246da4 FB |
2488 | struct dwc3_ep *dep; |
2489 | int ret; | |
2490 | u32 reg; | |
2491 | u8 speed; | |
2492 | ||
72246da4 FB |
2493 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2494 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2495 | dwc->speed = speed; | |
2496 | ||
2497 | dwc3_update_ram_clk_sel(dwc, speed); | |
2498 | ||
2499 | switch (speed) { | |
2da9ad76 | 2500 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2501 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2502 | dwc->gadget.ep0->maxpacket = 512; | |
2503 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2504 | break; | |
2da9ad76 | 2505 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2506 | /* |
2507 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2508 | * would cause a missing USB3 Reset event. | |
2509 | * | |
2510 | * In such situations, we should force a USB3 Reset | |
2511 | * event by calling our dwc3_gadget_reset_interrupt() | |
2512 | * routine. | |
2513 | * | |
2514 | * Refers to: | |
2515 | * | |
2516 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2517 | * not be generated always when the link enters poll | |
2518 | */ | |
2519 | if (dwc->revision < DWC3_REVISION_190A) | |
2520 | dwc3_gadget_reset_interrupt(dwc); | |
2521 | ||
72246da4 FB |
2522 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2523 | dwc->gadget.ep0->maxpacket = 512; | |
2524 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2525 | break; | |
2da9ad76 | 2526 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2527 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2528 | dwc->gadget.ep0->maxpacket = 64; | |
2529 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2530 | break; | |
2da9ad76 JY |
2531 | case DWC3_DSTS_FULLSPEED2: |
2532 | case DWC3_DSTS_FULLSPEED1: | |
72246da4 FB |
2533 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2534 | dwc->gadget.ep0->maxpacket = 64; | |
2535 | dwc->gadget.speed = USB_SPEED_FULL; | |
2536 | break; | |
2da9ad76 | 2537 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2538 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
2539 | dwc->gadget.ep0->maxpacket = 8; | |
2540 | dwc->gadget.speed = USB_SPEED_LOW; | |
2541 | break; | |
2542 | } | |
2543 | ||
2b758350 PA |
2544 | /* Enable USB2 LPM Capability */ |
2545 | ||
ee5cd41c | 2546 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
2547 | (speed != DWC3_DSTS_SUPERSPEED) && |
2548 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2549 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2550 | reg |= DWC3_DCFG_LPM_CAP; | |
2551 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2552 | ||
2553 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2554 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2555 | ||
460d098c | 2556 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2557 | |
80caf7d2 HR |
2558 | /* |
2559 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2560 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2561 | * BESL value in the LPM token is less than or equal to LPM | |
2562 | * NYET threshold. | |
2563 | */ | |
2564 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2565 | && dwc->has_lpm_erratum, | |
2566 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2567 | ||
2568 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2569 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2570 | ||
356363bf FB |
2571 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2572 | } else { | |
2573 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2574 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2575 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2576 | } | |
2577 | ||
72246da4 | 2578 | dep = dwc->eps[0]; |
265b70a7 PZ |
2579 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2580 | false); | |
72246da4 FB |
2581 | if (ret) { |
2582 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2583 | return; | |
2584 | } | |
2585 | ||
2586 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2587 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2588 | false); | |
72246da4 FB |
2589 | if (ret) { |
2590 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2591 | return; | |
2592 | } | |
2593 | ||
2594 | /* | |
2595 | * Configure PHY via GUSB3PIPECTLn if required. | |
2596 | * | |
2597 | * Update GTXFIFOSIZn | |
2598 | * | |
2599 | * In both cases reset values should be sufficient. | |
2600 | */ | |
2601 | } | |
2602 | ||
2603 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2604 | { | |
72246da4 FB |
2605 | /* |
2606 | * TODO take core out of low power mode when that's | |
2607 | * implemented. | |
2608 | */ | |
2609 | ||
ad14d4e0 JL |
2610 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2611 | spin_unlock(&dwc->lock); | |
2612 | dwc->gadget_driver->resume(&dwc->gadget); | |
2613 | spin_lock(&dwc->lock); | |
2614 | } | |
72246da4 FB |
2615 | } |
2616 | ||
2617 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2618 | unsigned int evtinfo) | |
2619 | { | |
fae2b904 | 2620 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2621 | unsigned int pwropt; |
2622 | ||
2623 | /* | |
2624 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2625 | * Hibernation mode enabled which would show up when device detects | |
2626 | * host-initiated U3 exit. | |
2627 | * | |
2628 | * In that case, device will generate a Link State Change Interrupt | |
2629 | * from U3 to RESUME which is only necessary if Hibernation is | |
2630 | * configured in. | |
2631 | * | |
2632 | * There are no functional changes due to such spurious event and we | |
2633 | * just need to ignore it. | |
2634 | * | |
2635 | * Refers to: | |
2636 | * | |
2637 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2638 | * operational mode | |
2639 | */ | |
2640 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2641 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2642 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2643 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2644 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
2645 | return; |
2646 | } | |
2647 | } | |
fae2b904 FB |
2648 | |
2649 | /* | |
2650 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2651 | * on the link partner, the USB session might do multiple entry/exit | |
2652 | * of low power states before a transfer takes place. | |
2653 | * | |
2654 | * Due to this problem, we might experience lower throughput. The | |
2655 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2656 | * transitioning from U1/U2 to U0 and enable those bits again | |
2657 | * after a transfer completes and there are no pending transfers | |
2658 | * on any of the enabled endpoints. | |
2659 | * | |
2660 | * This is the first half of that workaround. | |
2661 | * | |
2662 | * Refers to: | |
2663 | * | |
2664 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2665 | * core send LGO_Ux entering U0 | |
2666 | */ | |
2667 | if (dwc->revision < DWC3_REVISION_183A) { | |
2668 | if (next == DWC3_LINK_STATE_U0) { | |
2669 | u32 u1u2; | |
2670 | u32 reg; | |
2671 | ||
2672 | switch (dwc->link_state) { | |
2673 | case DWC3_LINK_STATE_U1: | |
2674 | case DWC3_LINK_STATE_U2: | |
2675 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2676 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2677 | | DWC3_DCTL_ACCEPTU2ENA | |
2678 | | DWC3_DCTL_INITU1ENA | |
2679 | | DWC3_DCTL_ACCEPTU1ENA); | |
2680 | ||
2681 | if (!dwc->u1u2) | |
2682 | dwc->u1u2 = reg & u1u2; | |
2683 | ||
2684 | reg &= ~u1u2; | |
2685 | ||
2686 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2687 | break; | |
2688 | default: | |
2689 | /* do nothing */ | |
2690 | break; | |
2691 | } | |
2692 | } | |
2693 | } | |
2694 | ||
bc5ba2e0 FB |
2695 | switch (next) { |
2696 | case DWC3_LINK_STATE_U1: | |
2697 | if (dwc->speed == USB_SPEED_SUPER) | |
2698 | dwc3_suspend_gadget(dwc); | |
2699 | break; | |
2700 | case DWC3_LINK_STATE_U2: | |
2701 | case DWC3_LINK_STATE_U3: | |
2702 | dwc3_suspend_gadget(dwc); | |
2703 | break; | |
2704 | case DWC3_LINK_STATE_RESUME: | |
2705 | dwc3_resume_gadget(dwc); | |
2706 | break; | |
2707 | default: | |
2708 | /* do nothing */ | |
2709 | break; | |
2710 | } | |
2711 | ||
e57ebc1d | 2712 | dwc->link_state = next; |
72246da4 FB |
2713 | } |
2714 | ||
72704f87 BW |
2715 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
2716 | unsigned int evtinfo) | |
2717 | { | |
2718 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
2719 | ||
2720 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
2721 | dwc3_suspend_gadget(dwc); | |
2722 | ||
2723 | dwc->link_state = next; | |
2724 | } | |
2725 | ||
e1dadd3b FB |
2726 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2727 | unsigned int evtinfo) | |
2728 | { | |
2729 | unsigned int is_ss = evtinfo & BIT(4); | |
2730 | ||
2731 | /** | |
2732 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2733 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2734 | * randomly. | |
2735 | * | |
2736 | * Because of this issue, core could generate bogus hibernation | |
2737 | * events which SW needs to ignore. | |
2738 | * | |
2739 | * Refers to: | |
2740 | * | |
2741 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2742 | * Device Fallback from SuperSpeed | |
2743 | */ | |
2744 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2745 | return; | |
2746 | ||
2747 | /* enter hibernation here */ | |
2748 | } | |
2749 | ||
72246da4 FB |
2750 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2751 | const struct dwc3_event_devt *event) | |
2752 | { | |
2753 | switch (event->type) { | |
2754 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2755 | dwc3_gadget_disconnect_interrupt(dwc); | |
2756 | break; | |
2757 | case DWC3_DEVICE_EVENT_RESET: | |
2758 | dwc3_gadget_reset_interrupt(dwc); | |
2759 | break; | |
2760 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2761 | dwc3_gadget_conndone_interrupt(dwc); | |
2762 | break; | |
2763 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2764 | dwc3_gadget_wakeup_interrupt(dwc); | |
2765 | break; | |
e1dadd3b FB |
2766 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2767 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2768 | "unexpected hibernation event\n")) | |
2769 | break; | |
2770 | ||
2771 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2772 | break; | |
72246da4 FB |
2773 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2774 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2775 | break; | |
2776 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 2777 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 2778 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
2779 | /* |
2780 | * Ignore suspend event until the gadget enters into | |
2781 | * USB_STATE_CONFIGURED state. | |
2782 | */ | |
2783 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
2784 | dwc3_gadget_suspend_interrupt(dwc, | |
2785 | event->event_info); | |
2786 | } | |
72246da4 FB |
2787 | break; |
2788 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 2789 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 2790 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 2791 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
2792 | break; |
2793 | default: | |
e9f2aa87 | 2794 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2795 | } |
2796 | } | |
2797 | ||
2798 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2799 | const union dwc3_event *event) | |
2800 | { | |
43c96be1 | 2801 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 2802 | |
72246da4 FB |
2803 | /* Endpoint IRQ, handle it and return early */ |
2804 | if (event->type.is_devspec == 0) { | |
2805 | /* depevt */ | |
2806 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2807 | } | |
2808 | ||
2809 | switch (event->type.type) { | |
2810 | case DWC3_EVENT_TYPE_DEV: | |
2811 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2812 | break; | |
2813 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2814 | default: | |
2815 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2816 | } | |
2817 | } | |
2818 | ||
dea520a4 | 2819 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2820 | { |
dea520a4 | 2821 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2822 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2823 | int left; |
e8adfc30 | 2824 | u32 reg; |
b15a762f | 2825 | |
f42f2447 | 2826 | left = evt->count; |
b15a762f | 2827 | |
f42f2447 FB |
2828 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2829 | return IRQ_NONE; | |
b15a762f | 2830 | |
f42f2447 FB |
2831 | while (left > 0) { |
2832 | union dwc3_event event; | |
b15a762f | 2833 | |
f42f2447 | 2834 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2835 | |
f42f2447 | 2836 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2837 | |
f42f2447 FB |
2838 | /* |
2839 | * FIXME we wrap around correctly to the next entry as | |
2840 | * almost all entries are 4 bytes in size. There is one | |
2841 | * entry which has 12 bytes which is a regular entry | |
2842 | * followed by 8 bytes data. ATM I don't know how | |
2843 | * things are organized if we get next to the a | |
2844 | * boundary so I worry about that once we try to handle | |
2845 | * that. | |
2846 | */ | |
2847 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2848 | left -= 4; | |
b15a762f | 2849 | |
660e9bde | 2850 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); |
f42f2447 | 2851 | } |
b15a762f | 2852 | |
f42f2447 FB |
2853 | evt->count = 0; |
2854 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2855 | ret = IRQ_HANDLED; | |
b15a762f | 2856 | |
f42f2447 | 2857 | /* Unmask interrupt */ |
660e9bde | 2858 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 2859 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2860 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 2861 | |
f42f2447 FB |
2862 | return ret; |
2863 | } | |
e8adfc30 | 2864 | |
dea520a4 | 2865 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 2866 | { |
dea520a4 FB |
2867 | struct dwc3_event_buffer *evt = _evt; |
2868 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 2869 | unsigned long flags; |
f42f2447 | 2870 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2871 | |
e5f68b4a | 2872 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 2873 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 2874 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2875 | |
2876 | return ret; | |
2877 | } | |
2878 | ||
dea520a4 | 2879 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 2880 | { |
dea520a4 | 2881 | struct dwc3 *dwc = evt->dwc; |
72246da4 | 2882 | u32 count; |
e8adfc30 | 2883 | u32 reg; |
72246da4 | 2884 | |
fc8bb91b FB |
2885 | if (pm_runtime_suspended(dwc->dev)) { |
2886 | pm_runtime_get(dwc->dev); | |
2887 | disable_irq_nosync(dwc->irq_gadget); | |
2888 | dwc->pending_events = true; | |
2889 | return IRQ_HANDLED; | |
2890 | } | |
2891 | ||
660e9bde | 2892 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
2893 | count &= DWC3_GEVNTCOUNT_MASK; |
2894 | if (!count) | |
2895 | return IRQ_NONE; | |
2896 | ||
b15a762f FB |
2897 | evt->count = count; |
2898 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2899 | |
e8adfc30 | 2900 | /* Mask interrupt */ |
660e9bde | 2901 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 2902 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2903 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 2904 | |
b15a762f | 2905 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2906 | } |
2907 | ||
dea520a4 | 2908 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 2909 | { |
dea520a4 | 2910 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 2911 | |
dea520a4 | 2912 | return dwc3_check_event_buf(evt); |
72246da4 FB |
2913 | } |
2914 | ||
6db3812e FB |
2915 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
2916 | { | |
2917 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
2918 | int irq; | |
2919 | ||
2920 | irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); | |
2921 | if (irq > 0) | |
2922 | goto out; | |
2923 | ||
2924 | if (irq == -EPROBE_DEFER) | |
2925 | goto out; | |
2926 | ||
2927 | irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); | |
2928 | if (irq > 0) | |
2929 | goto out; | |
2930 | ||
2931 | if (irq == -EPROBE_DEFER) | |
2932 | goto out; | |
2933 | ||
2934 | irq = platform_get_irq(dwc3_pdev, 0); | |
2935 | if (irq > 0) | |
2936 | goto out; | |
2937 | ||
2938 | if (irq != -EPROBE_DEFER) | |
2939 | dev_err(dwc->dev, "missing peripheral IRQ\n"); | |
2940 | ||
2941 | if (!irq) | |
2942 | irq = -EINVAL; | |
2943 | ||
2944 | out: | |
2945 | return irq; | |
2946 | } | |
2947 | ||
72246da4 FB |
2948 | /** |
2949 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2950 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2951 | * |
2952 | * Returns 0 on success otherwise negative errno. | |
2953 | */ | |
41ac7b3a | 2954 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2955 | { |
6db3812e FB |
2956 | int ret; |
2957 | int irq; | |
9522def4 | 2958 | |
6db3812e FB |
2959 | irq = dwc3_gadget_get_irq(dwc); |
2960 | if (irq < 0) { | |
2961 | ret = irq; | |
2962 | goto err0; | |
9522def4 RQ |
2963 | } |
2964 | ||
2965 | dwc->irq_gadget = irq; | |
72246da4 FB |
2966 | |
2967 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2968 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2969 | if (!dwc->ctrl_req) { | |
2970 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2971 | ret = -ENOMEM; | |
2972 | goto err0; | |
2973 | } | |
2974 | ||
2abd9d5f | 2975 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2976 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2977 | if (!dwc->ep0_trb) { | |
2978 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2979 | ret = -ENOMEM; | |
2980 | goto err1; | |
2981 | } | |
2982 | ||
3ef35faf | 2983 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2984 | if (!dwc->setup_buf) { |
72246da4 FB |
2985 | ret = -ENOMEM; |
2986 | goto err2; | |
2987 | } | |
2988 | ||
5812b1c2 | 2989 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2990 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2991 | GFP_KERNEL); | |
5812b1c2 FB |
2992 | if (!dwc->ep0_bounce) { |
2993 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2994 | ret = -ENOMEM; | |
2995 | goto err3; | |
2996 | } | |
2997 | ||
04c03d10 FB |
2998 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); |
2999 | if (!dwc->zlp_buf) { | |
3000 | ret = -ENOMEM; | |
3001 | goto err4; | |
3002 | } | |
3003 | ||
bb014736 BW |
3004 | init_completion(&dwc->ep0_in_setup); |
3005 | ||
72246da4 | 3006 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3007 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3008 | dwc->gadget.sg_supported = true; |
72246da4 | 3009 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 3010 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 3011 | |
b9e51b2b BM |
3012 | /* |
3013 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3014 | * <2.20a of dwc3 have an issue with metastability (documented | |
3015 | * elsewhere in this driver) which tells us we can't set max speed to | |
3016 | * anything lower than SUPER. | |
3017 | * | |
3018 | * Because gadget.max_speed is only used by composite.c and function | |
3019 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3020 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3021 | * together with our BOS descriptor as that could confuse host into | |
3022 | * thinking we can handle super speed. | |
3023 | * | |
3024 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3025 | * is less than super speed because we don't have means, yet, to tell | |
3026 | * composite.c that we are USB 2.0 + LPM ECN. | |
3027 | */ | |
3028 | if (dwc->revision < DWC3_REVISION_220A) | |
5eb30ced | 3029 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3030 | dwc->revision); |
3031 | ||
3032 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3033 | ||
a4b9d94b DC |
3034 | /* |
3035 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
3036 | * on ep out. | |
3037 | */ | |
3038 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
3039 | ||
72246da4 FB |
3040 | /* |
3041 | * REVISIT: Here we should clear all pending IRQs to be | |
3042 | * sure we're starting from a well known location. | |
3043 | */ | |
3044 | ||
3045 | ret = dwc3_gadget_init_endpoints(dwc); | |
3046 | if (ret) | |
04c03d10 | 3047 | goto err5; |
72246da4 | 3048 | |
72246da4 FB |
3049 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3050 | if (ret) { | |
3051 | dev_err(dwc->dev, "failed to register udc\n"); | |
04c03d10 | 3052 | goto err5; |
72246da4 FB |
3053 | } |
3054 | ||
3055 | return 0; | |
3056 | ||
04c03d10 FB |
3057 | err5: |
3058 | kfree(dwc->zlp_buf); | |
3059 | ||
5812b1c2 | 3060 | err4: |
e1f80467 | 3061 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
3062 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
3063 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 3064 | |
72246da4 | 3065 | err3: |
0fc9a1be | 3066 | kfree(dwc->setup_buf); |
72246da4 FB |
3067 | |
3068 | err2: | |
51fbc7c0 | 3069 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3070 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3071 | ||
3072 | err1: | |
3073 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
3074 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
3075 | ||
3076 | err0: | |
3077 | return ret; | |
3078 | } | |
3079 | ||
7415f17c FB |
3080 | /* -------------------------------------------------------------------------- */ |
3081 | ||
72246da4 FB |
3082 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3083 | { | |
72246da4 | 3084 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3085 | |
72246da4 FB |
3086 | dwc3_gadget_free_endpoints(dwc); |
3087 | ||
3ef35faf FB |
3088 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
3089 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 3090 | |
0fc9a1be | 3091 | kfree(dwc->setup_buf); |
04c03d10 | 3092 | kfree(dwc->zlp_buf); |
72246da4 | 3093 | |
51fbc7c0 | 3094 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3095 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3096 | ||
3097 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
3098 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 3099 | } |
7415f17c | 3100 | |
0b0231aa | 3101 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3102 | { |
9f8a67b6 FB |
3103 | int ret; |
3104 | ||
9772b47a RQ |
3105 | if (!dwc->gadget_driver) |
3106 | return 0; | |
3107 | ||
9f8a67b6 FB |
3108 | ret = dwc3_gadget_run_stop(dwc, false, false); |
3109 | if (ret < 0) | |
3110 | return ret; | |
7415f17c | 3111 | |
9f8a67b6 FB |
3112 | dwc3_disconnect_gadget(dwc); |
3113 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3114 | |
3115 | return 0; | |
3116 | } | |
3117 | ||
3118 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3119 | { | |
7415f17c FB |
3120 | int ret; |
3121 | ||
9772b47a RQ |
3122 | if (!dwc->gadget_driver) |
3123 | return 0; | |
3124 | ||
9f8a67b6 FB |
3125 | ret = __dwc3_gadget_start(dwc); |
3126 | if (ret < 0) | |
7415f17c FB |
3127 | goto err0; |
3128 | ||
9f8a67b6 FB |
3129 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3130 | if (ret < 0) | |
7415f17c FB |
3131 | goto err1; |
3132 | ||
7415f17c FB |
3133 | return 0; |
3134 | ||
3135 | err1: | |
9f8a67b6 | 3136 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3137 | |
3138 | err0: | |
3139 | return ret; | |
3140 | } | |
fc8bb91b FB |
3141 | |
3142 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3143 | { | |
3144 | if (dwc->pending_events) { | |
3145 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3146 | dwc->pending_events = false; | |
3147 | enable_irq(dwc->irq_gadget); | |
3148 | } | |
3149 | } |