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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 FB |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | ||
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | ||
80977dc9 | 33 | #include "debug.h" |
72246da4 FB |
34 | #include "core.h" |
35 | #include "gadget.h" | |
36 | #include "io.h" | |
37 | ||
04a9bfcd FB |
38 | /** |
39 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
40 | * @dwc: pointer to our context structure | |
41 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
42 | * | |
43 | * Caller should take care of locking. This function will | |
44 | * return 0 on success or -EINVAL if wrong Test Selector | |
45 | * is passed | |
46 | */ | |
47 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
48 | { | |
49 | u32 reg; | |
50 | ||
51 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
52 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
53 | ||
54 | switch (mode) { | |
55 | case TEST_J: | |
56 | case TEST_K: | |
57 | case TEST_SE0_NAK: | |
58 | case TEST_PACKET: | |
59 | case TEST_FORCE_EN: | |
60 | reg |= mode << 1; | |
61 | break; | |
62 | default: | |
63 | return -EINVAL; | |
64 | } | |
65 | ||
66 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
911f1f88 PZ |
71 | /** |
72 | * dwc3_gadget_get_link_state - Gets current state of USB Link | |
73 | * @dwc: pointer to our context structure | |
74 | * | |
75 | * Caller should take care of locking. This function will | |
76 | * return the link state on success (>= 0) or -ETIMEDOUT. | |
77 | */ | |
78 | int dwc3_gadget_get_link_state(struct dwc3 *dwc) | |
79 | { | |
80 | u32 reg; | |
81 | ||
82 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
83 | ||
84 | return DWC3_DSTS_USBLNKST(reg); | |
85 | } | |
86 | ||
8598bde7 FB |
87 | /** |
88 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
89 | * @dwc: pointer to our context structure | |
90 | * @state: the state to put link into | |
91 | * | |
92 | * Caller should take care of locking. This function will | |
aee63e3c | 93 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
94 | */ |
95 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
96 | { | |
aee63e3c | 97 | int retries = 10000; |
8598bde7 FB |
98 | u32 reg; |
99 | ||
802fde98 PZ |
100 | /* |
101 | * Wait until device controller is ready. Only applies to 1.94a and | |
102 | * later RTL. | |
103 | */ | |
104 | if (dwc->revision >= DWC3_REVISION_194A) { | |
105 | while (--retries) { | |
106 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
107 | if (reg & DWC3_DSTS_DCNRD) | |
108 | udelay(5); | |
109 | else | |
110 | break; | |
111 | } | |
112 | ||
113 | if (retries <= 0) | |
114 | return -ETIMEDOUT; | |
115 | } | |
116 | ||
8598bde7 FB |
117 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
118 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
119 | ||
120 | /* set requested state */ | |
121 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
122 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
123 | ||
802fde98 PZ |
124 | /* |
125 | * The following code is racy when called from dwc3_gadget_wakeup, | |
126 | * and is not needed, at least on newer versions | |
127 | */ | |
128 | if (dwc->revision >= DWC3_REVISION_194A) | |
129 | return 0; | |
130 | ||
8598bde7 | 131 | /* wait for a change in DSTS */ |
aed430e5 | 132 | retries = 10000; |
8598bde7 FB |
133 | while (--retries) { |
134 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
135 | ||
8598bde7 FB |
136 | if (DWC3_DSTS_USBLNKST(reg) == state) |
137 | return 0; | |
138 | ||
aee63e3c | 139 | udelay(5); |
8598bde7 FB |
140 | } |
141 | ||
8598bde7 FB |
142 | return -ETIMEDOUT; |
143 | } | |
144 | ||
dca0119c JY |
145 | /** |
146 | * dwc3_ep_inc_trb() - Increment a TRB index. | |
147 | * @index - Pointer to the TRB index to increment. | |
148 | * | |
149 | * The index should never point to the link TRB. After incrementing, | |
150 | * if it is point to the link TRB, wrap around to the beginning. The | |
151 | * link TRB is always at the last TRB entry. | |
152 | */ | |
153 | static void dwc3_ep_inc_trb(u8 *index) | |
457e84b6 | 154 | { |
dca0119c JY |
155 | (*index)++; |
156 | if (*index == (DWC3_TRB_NUM - 1)) | |
157 | *index = 0; | |
ef966b9d | 158 | } |
457e84b6 | 159 | |
dca0119c | 160 | static void dwc3_ep_inc_enq(struct dwc3_ep *dep) |
ef966b9d | 161 | { |
dca0119c | 162 | dwc3_ep_inc_trb(&dep->trb_enqueue); |
ef966b9d | 163 | } |
457e84b6 | 164 | |
dca0119c | 165 | static void dwc3_ep_inc_deq(struct dwc3_ep *dep) |
ef966b9d | 166 | { |
dca0119c | 167 | dwc3_ep_inc_trb(&dep->trb_dequeue); |
457e84b6 FB |
168 | } |
169 | ||
72246da4 FB |
170 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
171 | int status) | |
172 | { | |
173 | struct dwc3 *dwc = dep->dwc; | |
174 | ||
737f1ae2 | 175 | req->started = false; |
72246da4 | 176 | list_del(&req->list); |
eeb720fb | 177 | req->trb = NULL; |
e62c5bc5 | 178 | req->remaining = 0; |
72246da4 FB |
179 | |
180 | if (req->request.status == -EINPROGRESS) | |
181 | req->request.status = status; | |
182 | ||
0416e494 PA |
183 | if (dwc->ep0_bounced && dep->number == 0) |
184 | dwc->ep0_bounced = false; | |
185 | else | |
186 | usb_gadget_unmap_request(&dwc->gadget, &req->request, | |
187 | req->direction); | |
72246da4 | 188 | |
2c4cbe6e | 189 | trace_dwc3_gadget_giveback(req); |
72246da4 FB |
190 | |
191 | spin_unlock(&dwc->lock); | |
304f7e5e | 192 | usb_gadget_giveback_request(&dep->endpoint, &req->request); |
72246da4 | 193 | spin_lock(&dwc->lock); |
fc8bb91b FB |
194 | |
195 | if (dep->number > 1) | |
196 | pm_runtime_put(dwc->dev); | |
72246da4 FB |
197 | } |
198 | ||
3ece0ec4 | 199 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) |
b09bb642 FB |
200 | { |
201 | u32 timeout = 500; | |
71f7e702 | 202 | int status = 0; |
0fe886cd | 203 | int ret = 0; |
b09bb642 FB |
204 | u32 reg; |
205 | ||
206 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
207 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
208 | ||
209 | do { | |
210 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
211 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
71f7e702 FB |
212 | status = DWC3_DGCMD_STATUS(reg); |
213 | if (status) | |
0fe886cd FB |
214 | ret = -EINVAL; |
215 | break; | |
b09bb642 | 216 | } |
e3aee486 | 217 | } while (--timeout); |
0fe886cd FB |
218 | |
219 | if (!timeout) { | |
0fe886cd | 220 | ret = -ETIMEDOUT; |
71f7e702 | 221 | status = -ETIMEDOUT; |
0fe886cd FB |
222 | } |
223 | ||
71f7e702 FB |
224 | trace_dwc3_gadget_generic_cmd(cmd, param, status); |
225 | ||
0fe886cd | 226 | return ret; |
b09bb642 FB |
227 | } |
228 | ||
c36d8e94 FB |
229 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc); |
230 | ||
2cd4718d FB |
231 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
232 | struct dwc3_gadget_ep_cmd_params *params) | |
72246da4 | 233 | { |
8897a761 | 234 | const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; |
2cd4718d | 235 | struct dwc3 *dwc = dep->dwc; |
61d58242 | 236 | u32 timeout = 500; |
72246da4 FB |
237 | u32 reg; |
238 | ||
0933df15 | 239 | int cmd_status = 0; |
2b0f11df | 240 | int susphy = false; |
c0ca324d | 241 | int ret = -EINVAL; |
72246da4 | 242 | |
2b0f11df FB |
243 | /* |
244 | * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if | |
245 | * we're issuing an endpoint command, we must check if | |
246 | * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it. | |
247 | * | |
248 | * We will also set SUSPHY bit to what it was before returning as stated | |
249 | * by the same section on Synopsys databook. | |
250 | */ | |
ab2a92e7 FB |
251 | if (dwc->gadget.speed <= USB_SPEED_HIGH) { |
252 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
253 | if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { | |
254 | susphy = true; | |
255 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
256 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
257 | } | |
2b0f11df FB |
258 | } |
259 | ||
5999914f | 260 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { |
c36d8e94 FB |
261 | int needs_wakeup; |
262 | ||
263 | needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || | |
264 | dwc->link_state == DWC3_LINK_STATE_U2 || | |
265 | dwc->link_state == DWC3_LINK_STATE_U3); | |
266 | ||
267 | if (unlikely(needs_wakeup)) { | |
268 | ret = __dwc3_gadget_wakeup(dwc); | |
269 | dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", | |
270 | ret); | |
271 | } | |
272 | } | |
273 | ||
2eb88016 FB |
274 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); |
275 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); | |
276 | dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); | |
72246da4 | 277 | |
8897a761 FB |
278 | /* |
279 | * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're | |
280 | * not relying on XferNotReady, we can make use of a special "No | |
281 | * Response Update Transfer" command where we should clear both CmdAct | |
282 | * and CmdIOC bits. | |
283 | * | |
284 | * With this, we don't need to wait for command completion and can | |
285 | * straight away issue further commands to the endpoint. | |
286 | * | |
287 | * NOTICE: We're making an assumption that control endpoints will never | |
288 | * make use of Update Transfer command. This is a safe assumption | |
289 | * because we can never have more than one request at a time with | |
290 | * Control Endpoints. If anybody changes that assumption, this chunk | |
291 | * needs to be updated accordingly. | |
292 | */ | |
293 | if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && | |
294 | !usb_endpoint_xfer_isoc(desc)) | |
295 | cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); | |
296 | else | |
297 | cmd |= DWC3_DEPCMD_CMDACT; | |
298 | ||
299 | dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); | |
72246da4 | 300 | do { |
2eb88016 | 301 | reg = dwc3_readl(dep->regs, DWC3_DEPCMD); |
72246da4 | 302 | if (!(reg & DWC3_DEPCMD_CMDACT)) { |
0933df15 | 303 | cmd_status = DWC3_DEPCMD_STATUS(reg); |
7b9cc7a2 | 304 | |
7b9cc7a2 KL |
305 | switch (cmd_status) { |
306 | case 0: | |
307 | ret = 0; | |
308 | break; | |
309 | case DEPEVT_TRANSFER_NO_RESOURCE: | |
7b9cc7a2 | 310 | ret = -EINVAL; |
c0ca324d | 311 | break; |
7b9cc7a2 KL |
312 | case DEPEVT_TRANSFER_BUS_EXPIRY: |
313 | /* | |
314 | * SW issues START TRANSFER command to | |
315 | * isochronous ep with future frame interval. If | |
316 | * future interval time has already passed when | |
317 | * core receives the command, it will respond | |
318 | * with an error status of 'Bus Expiry'. | |
319 | * | |
320 | * Instead of always returning -EINVAL, let's | |
321 | * give a hint to the gadget driver that this is | |
322 | * the case by returning -EAGAIN. | |
323 | */ | |
7b9cc7a2 KL |
324 | ret = -EAGAIN; |
325 | break; | |
326 | default: | |
327 | dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); | |
328 | } | |
329 | ||
c0ca324d | 330 | break; |
72246da4 | 331 | } |
f6bb225b | 332 | } while (--timeout); |
72246da4 | 333 | |
f6bb225b | 334 | if (timeout == 0) { |
f6bb225b | 335 | ret = -ETIMEDOUT; |
0933df15 | 336 | cmd_status = -ETIMEDOUT; |
f6bb225b | 337 | } |
c0ca324d | 338 | |
0933df15 FB |
339 | trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); |
340 | ||
6cb2e4e3 FB |
341 | if (ret == 0) { |
342 | switch (DWC3_DEPCMD_CMD(cmd)) { | |
343 | case DWC3_DEPCMD_STARTTRANSFER: | |
344 | dep->flags |= DWC3_EP_TRANSFER_STARTED; | |
345 | break; | |
346 | case DWC3_DEPCMD_ENDTRANSFER: | |
347 | dep->flags &= ~DWC3_EP_TRANSFER_STARTED; | |
348 | break; | |
349 | default: | |
350 | /* nothing */ | |
351 | break; | |
352 | } | |
353 | } | |
354 | ||
2b0f11df FB |
355 | if (unlikely(susphy)) { |
356 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
357 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
358 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
359 | } | |
360 | ||
c0ca324d | 361 | return ret; |
72246da4 FB |
362 | } |
363 | ||
50c763f8 JY |
364 | static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) |
365 | { | |
366 | struct dwc3 *dwc = dep->dwc; | |
367 | struct dwc3_gadget_ep_cmd_params params; | |
368 | u32 cmd = DWC3_DEPCMD_CLEARSTALL; | |
369 | ||
370 | /* | |
371 | * As of core revision 2.60a the recommended programming model | |
372 | * is to set the ClearPendIN bit when issuing a Clear Stall EP | |
373 | * command for IN endpoints. This is to prevent an issue where | |
374 | * some (non-compliant) hosts may not send ACK TPs for pending | |
375 | * IN transfers due to a mishandled error condition. Synopsys | |
376 | * STAR 9000614252. | |
377 | */ | |
5e6c88d2 LB |
378 | if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && |
379 | (dwc->gadget.speed >= USB_SPEED_SUPER)) | |
50c763f8 JY |
380 | cmd |= DWC3_DEPCMD_CLEARPENDIN; |
381 | ||
382 | memset(¶ms, 0, sizeof(params)); | |
383 | ||
2cd4718d | 384 | return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
50c763f8 JY |
385 | } |
386 | ||
72246da4 | 387 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, |
f6bafc6a | 388 | struct dwc3_trb *trb) |
72246da4 | 389 | { |
c439ef87 | 390 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
391 | |
392 | return dep->trb_pool_dma + offset; | |
393 | } | |
394 | ||
395 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
396 | { | |
397 | struct dwc3 *dwc = dep->dwc; | |
398 | ||
399 | if (dep->trb_pool) | |
400 | return 0; | |
401 | ||
72246da4 FB |
402 | dep->trb_pool = dma_alloc_coherent(dwc->dev, |
403 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
404 | &dep->trb_pool_dma, GFP_KERNEL); | |
405 | if (!dep->trb_pool) { | |
406 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
407 | dep->name); | |
408 | return -ENOMEM; | |
409 | } | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
415 | { | |
416 | struct dwc3 *dwc = dep->dwc; | |
417 | ||
418 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
419 | dep->trb_pool, dep->trb_pool_dma); | |
420 | ||
421 | dep->trb_pool = NULL; | |
422 | dep->trb_pool_dma = 0; | |
423 | } | |
424 | ||
c4509601 JY |
425 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep); |
426 | ||
427 | /** | |
428 | * dwc3_gadget_start_config - Configure EP resources | |
429 | * @dwc: pointer to our controller context structure | |
430 | * @dep: endpoint that is being enabled | |
431 | * | |
432 | * The assignment of transfer resources cannot perfectly follow the | |
433 | * data book due to the fact that the controller driver does not have | |
434 | * all knowledge of the configuration in advance. It is given this | |
435 | * information piecemeal by the composite gadget framework after every | |
436 | * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook | |
437 | * programming model in this scenario can cause errors. For two | |
438 | * reasons: | |
439 | * | |
440 | * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION | |
441 | * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of | |
442 | * multiple interfaces. | |
443 | * | |
444 | * 2) The databook does not mention doing more DEPXFERCFG for new | |
445 | * endpoint on alt setting (8.1.6). | |
446 | * | |
447 | * The following simplified method is used instead: | |
448 | * | |
449 | * All hardware endpoints can be assigned a transfer resource and this | |
450 | * setting will stay persistent until either a core reset or | |
451 | * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and | |
452 | * do DEPXFERCFG for every hardware endpoint as well. We are | |
453 | * guaranteed that there are as many transfer resources as endpoints. | |
454 | * | |
455 | * This function is called for each endpoint when it is being enabled | |
456 | * but is triggered only when called for EP0-out, which always happens | |
457 | * first, and which should only happen in one of the above conditions. | |
458 | */ | |
72246da4 FB |
459 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) |
460 | { | |
461 | struct dwc3_gadget_ep_cmd_params params; | |
462 | u32 cmd; | |
c4509601 JY |
463 | int i; |
464 | int ret; | |
465 | ||
466 | if (dep->number) | |
467 | return 0; | |
72246da4 FB |
468 | |
469 | memset(¶ms, 0x00, sizeof(params)); | |
c4509601 | 470 | cmd = DWC3_DEPCMD_DEPSTARTCFG; |
72246da4 | 471 | |
2cd4718d | 472 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
c4509601 JY |
473 | if (ret) |
474 | return ret; | |
475 | ||
476 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
477 | struct dwc3_ep *dep = dwc->eps[i]; | |
72246da4 | 478 | |
c4509601 JY |
479 | if (!dep) |
480 | continue; | |
481 | ||
482 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
483 | if (ret) | |
484 | return ret; | |
72246da4 FB |
485 | } |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec | 491 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 492 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
21e64bf2 | 493 | bool modify, bool restore) |
72246da4 FB |
494 | { |
495 | struct dwc3_gadget_ep_cmd_params params; | |
496 | ||
21e64bf2 FB |
497 | if (dev_WARN_ONCE(dwc->dev, modify && restore, |
498 | "Can't modify and restore\n")) | |
499 | return -EINVAL; | |
500 | ||
72246da4 FB |
501 | memset(¶ms, 0x00, sizeof(params)); |
502 | ||
dc1c70a7 | 503 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
d2e9a13a CP |
504 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); |
505 | ||
506 | /* Burst size is only needed in SuperSpeed mode */ | |
ee5cd41c | 507 | if (dwc->gadget.speed >= USB_SPEED_SUPER) { |
676e3497 | 508 | u32 burst = dep->endpoint.maxburst; |
676e3497 | 509 | params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); |
d2e9a13a | 510 | } |
72246da4 | 511 | |
21e64bf2 FB |
512 | if (modify) { |
513 | params.param0 |= DWC3_DEPCFG_ACTION_MODIFY; | |
514 | } else if (restore) { | |
265b70a7 PZ |
515 | params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; |
516 | params.param2 |= dep->saved_state; | |
21e64bf2 FB |
517 | } else { |
518 | params.param0 |= DWC3_DEPCFG_ACTION_INIT; | |
265b70a7 PZ |
519 | } |
520 | ||
4bc48c97 FB |
521 | if (usb_endpoint_xfer_control(desc)) |
522 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; | |
13fa2e69 FB |
523 | |
524 | if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) | |
525 | params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 526 | |
18b7ede5 | 527 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
528 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
529 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
530 | dep->stream_capable = true; |
531 | } | |
532 | ||
0b93a4c8 | 533 | if (!usb_endpoint_xfer_control(desc)) |
dc1c70a7 | 534 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
535 | |
536 | /* | |
537 | * We are doing 1:1 mapping for endpoints, meaning | |
538 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
539 | * so on. We consider the direction bit as part of the physical | |
540 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
541 | */ | |
dc1c70a7 | 542 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
543 | |
544 | /* | |
545 | * We must use the lower 16 TX FIFOs even though | |
546 | * HW might have more | |
547 | */ | |
548 | if (dep->direction) | |
dc1c70a7 | 549 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
550 | |
551 | if (desc->bInterval) { | |
dc1c70a7 | 552 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
553 | dep->interval = 1 << (desc->bInterval - 1); |
554 | } | |
555 | ||
2cd4718d | 556 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); |
72246da4 FB |
557 | } |
558 | ||
559 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
560 | { | |
561 | struct dwc3_gadget_ep_cmd_params params; | |
562 | ||
563 | memset(¶ms, 0x00, sizeof(params)); | |
564 | ||
dc1c70a7 | 565 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 | 566 | |
2cd4718d FB |
567 | return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, |
568 | ¶ms); | |
72246da4 FB |
569 | } |
570 | ||
571 | /** | |
572 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
573 | * @dep: endpoint to be initialized | |
574 | * @desc: USB Endpoint Descriptor | |
575 | * | |
576 | * Caller should take care of locking | |
577 | */ | |
578 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec | 579 | const struct usb_endpoint_descriptor *desc, |
4b345c9a | 580 | const struct usb_ss_ep_comp_descriptor *comp_desc, |
21e64bf2 | 581 | bool modify, bool restore) |
72246da4 FB |
582 | { |
583 | struct dwc3 *dwc = dep->dwc; | |
584 | u32 reg; | |
b09e99ee | 585 | int ret; |
72246da4 FB |
586 | |
587 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
588 | ret = dwc3_gadget_start_config(dwc, dep); | |
589 | if (ret) | |
590 | return ret; | |
591 | } | |
592 | ||
21e64bf2 | 593 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify, |
265b70a7 | 594 | restore); |
72246da4 FB |
595 | if (ret) |
596 | return ret; | |
597 | ||
598 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
599 | struct dwc3_trb *trb_st_hw; |
600 | struct dwc3_trb *trb_link; | |
72246da4 | 601 | |
16e78db7 | 602 | dep->endpoint.desc = desc; |
c90bfaec | 603 | dep->comp_desc = comp_desc; |
72246da4 FB |
604 | dep->type = usb_endpoint_type(desc); |
605 | dep->flags |= DWC3_EP_ENABLED; | |
76a638f8 | 606 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
607 | |
608 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
609 | reg |= DWC3_DALEPENA_EP(dep->number); | |
610 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
611 | ||
76a638f8 BW |
612 | init_waitqueue_head(&dep->wait_end_transfer); |
613 | ||
36b68aae | 614 | if (usb_endpoint_xfer_control(desc)) |
2870e501 | 615 | goto out; |
72246da4 | 616 | |
0d25744a JY |
617 | /* Initialize the TRB ring */ |
618 | dep->trb_dequeue = 0; | |
619 | dep->trb_enqueue = 0; | |
620 | memset(dep->trb_pool, 0, | |
621 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM); | |
622 | ||
36b68aae | 623 | /* Link TRB. The HWO bit is never reset */ |
72246da4 FB |
624 | trb_st_hw = &dep->trb_pool[0]; |
625 | ||
f6bafc6a | 626 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
f6bafc6a FB |
627 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
628 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
629 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
630 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
631 | } |
632 | ||
a97ea994 FB |
633 | /* |
634 | * Issue StartTransfer here with no-op TRB so we can always rely on No | |
635 | * Response Update Transfer command. | |
636 | */ | |
637 | if (usb_endpoint_xfer_bulk(desc)) { | |
638 | struct dwc3_gadget_ep_cmd_params params; | |
639 | struct dwc3_trb *trb; | |
640 | dma_addr_t trb_dma; | |
641 | u32 cmd; | |
642 | ||
643 | memset(¶ms, 0, sizeof(params)); | |
644 | trb = &dep->trb_pool[0]; | |
645 | trb_dma = dwc3_trb_dma_offset(dep, trb); | |
646 | ||
647 | params.param0 = upper_32_bits(trb_dma); | |
648 | params.param1 = lower_32_bits(trb_dma); | |
649 | ||
650 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
651 | ||
652 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); | |
653 | if (ret < 0) | |
654 | return ret; | |
655 | ||
656 | dep->flags |= DWC3_EP_BUSY; | |
657 | ||
658 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); | |
659 | WARN_ON_ONCE(!dep->resource_index); | |
660 | } | |
661 | ||
2870e501 FB |
662 | |
663 | out: | |
664 | trace_dwc3_gadget_ep_enable(dep); | |
665 | ||
72246da4 FB |
666 | return 0; |
667 | } | |
668 | ||
b992e681 | 669 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); |
624407f9 | 670 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) |
72246da4 FB |
671 | { |
672 | struct dwc3_request *req; | |
673 | ||
0e146028 | 674 | dwc3_stop_active_transfer(dwc, dep->number, true); |
624407f9 | 675 | |
0e146028 FB |
676 | /* - giveback all requests to gadget driver */ |
677 | while (!list_empty(&dep->started_list)) { | |
678 | req = next_request(&dep->started_list); | |
1591633e | 679 | |
0e146028 | 680 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
ea53b882 FB |
681 | } |
682 | ||
aa3342c8 FB |
683 | while (!list_empty(&dep->pending_list)) { |
684 | req = next_request(&dep->pending_list); | |
72246da4 | 685 | |
624407f9 | 686 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 687 | } |
72246da4 FB |
688 | } |
689 | ||
690 | /** | |
691 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
692 | * @dep: the endpoint to disable | |
693 | * | |
624407f9 SAS |
694 | * This function also removes requests which are currently processed ny the |
695 | * hardware and those which are not yet scheduled. | |
696 | * Caller should take care of locking. | |
72246da4 | 697 | */ |
72246da4 FB |
698 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
699 | { | |
700 | struct dwc3 *dwc = dep->dwc; | |
701 | u32 reg; | |
702 | ||
2870e501 | 703 | trace_dwc3_gadget_ep_disable(dep); |
7eaeac5c | 704 | |
624407f9 | 705 | dwc3_remove_requests(dwc, dep); |
72246da4 | 706 | |
687ef981 FB |
707 | /* make sure HW endpoint isn't stalled */ |
708 | if (dep->flags & DWC3_EP_STALL) | |
7a608559 | 709 | __dwc3_gadget_ep_set_halt(dep, 0, false); |
687ef981 | 710 | |
72246da4 FB |
711 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); |
712 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
713 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
714 | ||
879631aa | 715 | dep->stream_capable = false; |
f9c56cdd | 716 | dep->endpoint.desc = NULL; |
c90bfaec | 717 | dep->comp_desc = NULL; |
72246da4 | 718 | dep->type = 0; |
76a638f8 | 719 | dep->flags &= DWC3_EP_END_TRANSFER_PENDING; |
72246da4 FB |
720 | |
721 | return 0; | |
722 | } | |
723 | ||
724 | /* -------------------------------------------------------------------------- */ | |
725 | ||
726 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
727 | const struct usb_endpoint_descriptor *desc) | |
728 | { | |
729 | return -EINVAL; | |
730 | } | |
731 | ||
732 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
733 | { | |
734 | return -EINVAL; | |
735 | } | |
736 | ||
737 | /* -------------------------------------------------------------------------- */ | |
738 | ||
739 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
740 | const struct usb_endpoint_descriptor *desc) | |
741 | { | |
742 | struct dwc3_ep *dep; | |
743 | struct dwc3 *dwc; | |
744 | unsigned long flags; | |
745 | int ret; | |
746 | ||
747 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
748 | pr_debug("dwc3: invalid parameters\n"); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | if (!desc->wMaxPacketSize) { | |
753 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
754 | return -EINVAL; | |
755 | } | |
756 | ||
757 | dep = to_dwc3_ep(ep); | |
758 | dwc = dep->dwc; | |
759 | ||
95ca961c FB |
760 | if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, |
761 | "%s is already enabled\n", | |
762 | dep->name)) | |
c6f83f38 | 763 | return 0; |
c6f83f38 | 764 | |
72246da4 | 765 | spin_lock_irqsave(&dwc->lock, flags); |
265b70a7 | 766 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); |
72246da4 FB |
767 | spin_unlock_irqrestore(&dwc->lock, flags); |
768 | ||
769 | return ret; | |
770 | } | |
771 | ||
772 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
773 | { | |
774 | struct dwc3_ep *dep; | |
775 | struct dwc3 *dwc; | |
776 | unsigned long flags; | |
777 | int ret; | |
778 | ||
779 | if (!ep) { | |
780 | pr_debug("dwc3: invalid parameters\n"); | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | dep = to_dwc3_ep(ep); | |
785 | dwc = dep->dwc; | |
786 | ||
95ca961c FB |
787 | if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), |
788 | "%s is already disabled\n", | |
789 | dep->name)) | |
72246da4 | 790 | return 0; |
72246da4 | 791 | |
72246da4 FB |
792 | spin_lock_irqsave(&dwc->lock, flags); |
793 | ret = __dwc3_gadget_ep_disable(dep); | |
794 | spin_unlock_irqrestore(&dwc->lock, flags); | |
795 | ||
796 | return ret; | |
797 | } | |
798 | ||
799 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
800 | gfp_t gfp_flags) | |
801 | { | |
802 | struct dwc3_request *req; | |
803 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
72246da4 FB |
804 | |
805 | req = kzalloc(sizeof(*req), gfp_flags); | |
734d5a53 | 806 | if (!req) |
72246da4 | 807 | return NULL; |
72246da4 FB |
808 | |
809 | req->epnum = dep->number; | |
810 | req->dep = dep; | |
72246da4 | 811 | |
68d34c8a FB |
812 | dep->allocated_requests++; |
813 | ||
2c4cbe6e FB |
814 | trace_dwc3_alloc_request(req); |
815 | ||
72246da4 FB |
816 | return &req->request; |
817 | } | |
818 | ||
819 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
820 | struct usb_request *request) | |
821 | { | |
822 | struct dwc3_request *req = to_dwc3_request(request); | |
68d34c8a | 823 | struct dwc3_ep *dep = to_dwc3_ep(ep); |
72246da4 | 824 | |
68d34c8a | 825 | dep->allocated_requests--; |
2c4cbe6e | 826 | trace_dwc3_free_request(req); |
72246da4 FB |
827 | kfree(req); |
828 | } | |
829 | ||
2c78c029 FB |
830 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep); |
831 | ||
c71fc37c FB |
832 | /** |
833 | * dwc3_prepare_one_trb - setup one TRB from one request | |
834 | * @dep: endpoint for which this request is prepared | |
835 | * @req: dwc3_request pointer | |
836 | */ | |
68e823e2 | 837 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb | 838 | struct dwc3_request *req, dma_addr_t dma, |
4bc48c97 | 839 | unsigned length, unsigned chain, unsigned node) |
c71fc37c | 840 | { |
f6bafc6a | 841 | struct dwc3_trb *trb; |
6b9018d4 FB |
842 | struct dwc3 *dwc = dep->dwc; |
843 | struct usb_gadget *gadget = &dwc->gadget; | |
844 | enum usb_device_speed speed = gadget->speed; | |
c71fc37c | 845 | |
4faf7550 | 846 | trb = &dep->trb_pool[dep->trb_enqueue]; |
c71fc37c | 847 | |
eeb720fb | 848 | if (!req->trb) { |
aa3342c8 | 849 | dwc3_gadget_move_started_request(req); |
f6bafc6a FB |
850 | req->trb = trb; |
851 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
a9c3ca5f | 852 | dep->queued_requests++; |
eeb720fb | 853 | } |
c71fc37c | 854 | |
ef966b9d | 855 | dwc3_ep_inc_enq(dep); |
e5ba5ec8 | 856 | |
f6bafc6a FB |
857 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
858 | trb->bpl = lower_32_bits(dma); | |
859 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 860 | |
16e78db7 | 861 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 862 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 863 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
864 | break; |
865 | ||
866 | case USB_ENDPOINT_XFER_ISOC: | |
6b9018d4 | 867 | if (!node) { |
e5ba5ec8 | 868 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
6b9018d4 FB |
869 | |
870 | if (speed == USB_SPEED_HIGH) { | |
871 | struct usb_ep *ep = &dep->endpoint; | |
872 | trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1); | |
873 | } | |
874 | } else { | |
e5ba5ec8 | 875 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; |
6b9018d4 | 876 | } |
ca4d44ea FB |
877 | |
878 | /* always enable Interrupt on Missed ISOC */ | |
879 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
c71fc37c FB |
880 | break; |
881 | ||
882 | case USB_ENDPOINT_XFER_BULK: | |
883 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 884 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
885 | break; |
886 | default: | |
887 | /* | |
888 | * This is only possible with faulty memory because we | |
889 | * checked it already :) | |
890 | */ | |
0a695d4c FB |
891 | dev_WARN(dwc->dev, "Unknown endpoint type %d\n", |
892 | usb_endpoint_type(dep->endpoint.desc)); | |
c71fc37c FB |
893 | } |
894 | ||
ca4d44ea | 895 | /* always enable Continue on Short Packet */ |
c9508c8c | 896 | if (usb_endpoint_dir_out(dep->endpoint.desc)) { |
58f29034 | 897 | trb->ctrl |= DWC3_TRB_CTRL_CSP; |
f3af3651 | 898 | |
c9508c8c FB |
899 | if (req->request.short_not_ok) |
900 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; | |
901 | } | |
902 | ||
2c78c029 FB |
903 | if ((!req->request.no_interrupt && !chain) || |
904 | (dwc3_calc_trbs_left(dep) == 0)) | |
c9508c8c | 905 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
f3af3651 | 906 | |
e5ba5ec8 PA |
907 | if (chain) |
908 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
909 | ||
16e78db7 | 910 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 911 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 912 | |
f6bafc6a | 913 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
2c4cbe6e FB |
914 | |
915 | trace_dwc3_prepare_trb(dep, trb); | |
c71fc37c FB |
916 | } |
917 | ||
361572b5 JY |
918 | /** |
919 | * dwc3_ep_prev_trb() - Returns the previous TRB in the ring | |
920 | * @dep: The endpoint with the TRB ring | |
921 | * @index: The index of the current TRB in the ring | |
922 | * | |
923 | * Returns the TRB prior to the one pointed to by the index. If the | |
924 | * index is 0, we will wrap backwards, skip the link TRB, and return | |
925 | * the one just before that. | |
926 | */ | |
927 | static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) | |
928 | { | |
45438a0c | 929 | u8 tmp = index; |
361572b5 | 930 | |
45438a0c FB |
931 | if (!tmp) |
932 | tmp = DWC3_TRB_NUM - 1; | |
361572b5 | 933 | |
45438a0c | 934 | return &dep->trb_pool[tmp - 1]; |
361572b5 JY |
935 | } |
936 | ||
c4233573 FB |
937 | static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) |
938 | { | |
939 | struct dwc3_trb *tmp; | |
f2694a93 | 940 | struct dwc3 *dwc = dep->dwc; |
32db3d94 | 941 | u8 trbs_left; |
c4233573 FB |
942 | |
943 | /* | |
944 | * If enqueue & dequeue are equal than it is either full or empty. | |
945 | * | |
946 | * One way to know for sure is if the TRB right before us has HWO bit | |
947 | * set or not. If it has, then we're definitely full and can't fit any | |
948 | * more transfers in our ring. | |
949 | */ | |
950 | if (dep->trb_enqueue == dep->trb_dequeue) { | |
361572b5 | 951 | tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); |
f2694a93 JD |
952 | if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO, |
953 | "%s No TRBS left\n", dep->name)) | |
361572b5 | 954 | return 0; |
c4233573 FB |
955 | |
956 | return DWC3_TRB_NUM - 1; | |
957 | } | |
958 | ||
9d7aba77 | 959 | trbs_left = dep->trb_dequeue - dep->trb_enqueue; |
3de2685f | 960 | trbs_left &= (DWC3_TRB_NUM - 1); |
32db3d94 | 961 | |
9d7aba77 JY |
962 | if (dep->trb_dequeue < dep->trb_enqueue) |
963 | trbs_left--; | |
964 | ||
32db3d94 | 965 | return trbs_left; |
c4233573 FB |
966 | } |
967 | ||
5ee85d89 | 968 | static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, |
7ae7df49 | 969 | struct dwc3_request *req) |
5ee85d89 | 970 | { |
1f512119 | 971 | struct scatterlist *sg = req->sg; |
5ee85d89 | 972 | struct scatterlist *s; |
5ee85d89 FB |
973 | unsigned int length; |
974 | dma_addr_t dma; | |
975 | int i; | |
976 | ||
1f512119 | 977 | for_each_sg(sg, s, req->num_pending_sgs, i) { |
5ee85d89 FB |
978 | unsigned chain = true; |
979 | ||
980 | length = sg_dma_len(s); | |
981 | dma = sg_dma_address(s); | |
982 | ||
4bc48c97 | 983 | if (sg_is_last(s)) |
5ee85d89 FB |
984 | chain = false; |
985 | ||
986 | dwc3_prepare_one_trb(dep, req, dma, length, | |
4bc48c97 | 987 | chain, i); |
5ee85d89 | 988 | |
7ae7df49 | 989 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 FB |
990 | break; |
991 | } | |
992 | } | |
993 | ||
994 | static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, | |
7ae7df49 | 995 | struct dwc3_request *req) |
5ee85d89 | 996 | { |
5ee85d89 FB |
997 | unsigned int length; |
998 | dma_addr_t dma; | |
999 | ||
1000 | dma = req->request.dma; | |
1001 | length = req->request.length; | |
1002 | ||
5ee85d89 | 1003 | dwc3_prepare_one_trb(dep, req, dma, length, |
4bc48c97 | 1004 | false, 0); |
5ee85d89 FB |
1005 | } |
1006 | ||
72246da4 FB |
1007 | /* |
1008 | * dwc3_prepare_trbs - setup TRBs from requests | |
1009 | * @dep: endpoint for which requests are being prepared | |
72246da4 | 1010 | * |
1d046793 PZ |
1011 | * The function goes through the requests list and sets up TRBs for the |
1012 | * transfers. The function returns once there are no more TRBs available or | |
1013 | * it runs out of requests. | |
72246da4 | 1014 | */ |
c4233573 | 1015 | static void dwc3_prepare_trbs(struct dwc3_ep *dep) |
72246da4 | 1016 | { |
68e823e2 | 1017 | struct dwc3_request *req, *n; |
72246da4 FB |
1018 | |
1019 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
1020 | ||
7ae7df49 | 1021 | if (!dwc3_calc_trbs_left(dep)) |
89bc856e | 1022 | return; |
72246da4 | 1023 | |
d86c5a67 FB |
1024 | /* |
1025 | * We can get in a situation where there's a request in the started list | |
1026 | * but there weren't enough TRBs to fully kick it in the first time | |
1027 | * around, so it has been waiting for more TRBs to be freed up. | |
1028 | * | |
1029 | * In that case, we should check if we have a request with pending_sgs | |
1030 | * in the started list and prepare TRBs for that request first, | |
1031 | * otherwise we will prepare TRBs completely out of order and that will | |
1032 | * break things. | |
1033 | */ | |
1034 | list_for_each_entry(req, &dep->started_list, list) { | |
1035 | if (req->num_pending_sgs > 0) | |
1036 | dwc3_prepare_one_trb_sg(dep, req); | |
1037 | ||
1038 | if (!dwc3_calc_trbs_left(dep)) | |
1039 | return; | |
1040 | } | |
1041 | ||
aa3342c8 | 1042 | list_for_each_entry_safe(req, n, &dep->pending_list, list) { |
1f512119 | 1043 | if (req->num_pending_sgs > 0) |
7ae7df49 | 1044 | dwc3_prepare_one_trb_sg(dep, req); |
5ee85d89 | 1045 | else |
7ae7df49 | 1046 | dwc3_prepare_one_trb_linear(dep, req); |
72246da4 | 1047 | |
7ae7df49 | 1048 | if (!dwc3_calc_trbs_left(dep)) |
5ee85d89 | 1049 | return; |
72246da4 | 1050 | } |
72246da4 FB |
1051 | } |
1052 | ||
4fae2e3e | 1053 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param) |
72246da4 FB |
1054 | { |
1055 | struct dwc3_gadget_ep_cmd_params params; | |
1056 | struct dwc3_request *req; | |
4fae2e3e | 1057 | int starting; |
72246da4 FB |
1058 | int ret; |
1059 | u32 cmd; | |
1060 | ||
4fae2e3e | 1061 | starting = !(dep->flags & DWC3_EP_BUSY); |
72246da4 | 1062 | |
4fae2e3e FB |
1063 | dwc3_prepare_trbs(dep); |
1064 | req = next_request(&dep->started_list); | |
72246da4 FB |
1065 | if (!req) { |
1066 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | memset(¶ms, 0, sizeof(params)); | |
72246da4 | 1071 | |
4fae2e3e | 1072 | if (starting) { |
1877d6c9 PA |
1073 | params.param0 = upper_32_bits(req->trb_dma); |
1074 | params.param1 = lower_32_bits(req->trb_dma); | |
b6b1c6db FB |
1075 | cmd = DWC3_DEPCMD_STARTTRANSFER | |
1076 | DWC3_DEPCMD_PARAM(cmd_param); | |
1877d6c9 | 1077 | } else { |
b6b1c6db FB |
1078 | cmd = DWC3_DEPCMD_UPDATETRANSFER | |
1079 | DWC3_DEPCMD_PARAM(dep->resource_index); | |
1877d6c9 | 1080 | } |
72246da4 | 1081 | |
2cd4718d | 1082 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
72246da4 | 1083 | if (ret < 0) { |
72246da4 FB |
1084 | /* |
1085 | * FIXME we need to iterate over the list of requests | |
1086 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 1087 | * requests instead of what we do now. |
72246da4 | 1088 | */ |
ce3fc8b3 JD |
1089 | if (req->trb) |
1090 | memset(req->trb, 0, sizeof(struct dwc3_trb)); | |
8ab89da4 | 1091 | dep->queued_requests--; |
15b8d933 | 1092 | dwc3_gadget_giveback(dep, req, ret); |
72246da4 FB |
1093 | return ret; |
1094 | } | |
1095 | ||
1096 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 1097 | |
4fae2e3e | 1098 | if (starting) { |
2eb88016 | 1099 | dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); |
b4996a86 | 1100 | WARN_ON_ONCE(!dep->resource_index); |
f898ae09 | 1101 | } |
25b8ff68 | 1102 | |
72246da4 FB |
1103 | return 0; |
1104 | } | |
1105 | ||
6cb2e4e3 FB |
1106 | static int __dwc3_gadget_get_frame(struct dwc3 *dwc) |
1107 | { | |
1108 | u32 reg; | |
1109 | ||
1110 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1111 | return DWC3_DSTS_SOFFN(reg); | |
1112 | } | |
1113 | ||
d6d6ec7b PA |
1114 | static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, |
1115 | struct dwc3_ep *dep, u32 cur_uf) | |
1116 | { | |
1117 | u32 uf; | |
1118 | ||
aa3342c8 | 1119 | if (list_empty(&dep->pending_list)) { |
5eb30ced | 1120 | dev_info(dwc->dev, "%s: ran out of requests\n", |
73815280 | 1121 | dep->name); |
f4a53c55 | 1122 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
d6d6ec7b PA |
1123 | return; |
1124 | } | |
1125 | ||
1126 | /* 4 micro frames in the future */ | |
1127 | uf = cur_uf + dep->interval * 4; | |
1128 | ||
4fae2e3e | 1129 | __dwc3_gadget_kick_transfer(dep, uf); |
d6d6ec7b PA |
1130 | } |
1131 | ||
1132 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1133 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1134 | { | |
1135 | u32 cur_uf, mask; | |
1136 | ||
1137 | mask = ~(dep->interval - 1); | |
1138 | cur_uf = event->parameters & mask; | |
1139 | ||
1140 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
1141 | } | |
1142 | ||
72246da4 FB |
1143 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) |
1144 | { | |
0fc9a1be FB |
1145 | struct dwc3 *dwc = dep->dwc; |
1146 | int ret; | |
1147 | ||
bb423984 | 1148 | if (!dep->endpoint.desc) { |
5eb30ced FB |
1149 | dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
1150 | dep->name); | |
bb423984 FB |
1151 | return -ESHUTDOWN; |
1152 | } | |
1153 | ||
1154 | if (WARN(req->dep != dep, "request %p belongs to '%s'\n", | |
1155 | &req->request, req->dep->name)) { | |
5eb30ced FB |
1156 | dev_err(dwc->dev, "%s: request %p belongs to '%s'\n", |
1157 | dep->name, &req->request, req->dep->name); | |
bb423984 FB |
1158 | return -EINVAL; |
1159 | } | |
1160 | ||
fc8bb91b FB |
1161 | pm_runtime_get(dwc->dev); |
1162 | ||
72246da4 FB |
1163 | req->request.actual = 0; |
1164 | req->request.status = -EINPROGRESS; | |
1165 | req->direction = dep->direction; | |
1166 | req->epnum = dep->number; | |
1167 | ||
fe84f522 FB |
1168 | trace_dwc3_ep_queue(req); |
1169 | ||
0fc9a1be FB |
1170 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1171 | dep->direction); | |
1172 | if (ret) | |
1173 | return ret; | |
1174 | ||
1f512119 FB |
1175 | req->sg = req->request.sg; |
1176 | req->num_pending_sgs = req->request.num_mapped_sgs; | |
89185916 | 1177 | |
aa3342c8 | 1178 | list_add_tail(&req->list, &dep->pending_list); |
72246da4 | 1179 | |
d889c23c FB |
1180 | /* |
1181 | * NOTICE: Isochronous endpoints should NEVER be prestarted. We must | |
1182 | * wait for a XferNotReady event so we will know what's the current | |
1183 | * (micro-)frame number. | |
1184 | * | |
1185 | * Without this trick, we are very, very likely gonna get Bus Expiry | |
1186 | * errors which will force us issue EndTransfer command. | |
1187 | */ | |
1188 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { | |
6cb2e4e3 FB |
1189 | if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { |
1190 | if (dep->flags & DWC3_EP_TRANSFER_STARTED) { | |
1191 | dwc3_stop_active_transfer(dwc, dep->number, true); | |
1192 | dep->flags = DWC3_EP_ENABLED; | |
1193 | } else { | |
1194 | u32 cur_uf; | |
1195 | ||
1196 | cur_uf = __dwc3_gadget_get_frame(dwc); | |
1197 | __dwc3_gadget_start_isoc(dwc, dep, cur_uf); | |
87aba106 | 1198 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; |
6cb2e4e3 | 1199 | } |
08a36b54 FB |
1200 | } |
1201 | return 0; | |
a0925324 | 1202 | } |
72246da4 | 1203 | |
594e121f FB |
1204 | if (!dwc3_calc_trbs_left(dep)) |
1205 | return 0; | |
b997ada5 | 1206 | |
08a36b54 | 1207 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
a8f32817 FB |
1208 | if (ret == -EBUSY) |
1209 | ret = 0; | |
1210 | ||
1211 | return ret; | |
72246da4 FB |
1212 | } |
1213 | ||
04c03d10 FB |
1214 | static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep, |
1215 | struct usb_request *request) | |
1216 | { | |
1217 | dwc3_gadget_ep_free_request(ep, request); | |
1218 | } | |
1219 | ||
1220 | static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep) | |
1221 | { | |
1222 | struct dwc3_request *req; | |
1223 | struct usb_request *request; | |
1224 | struct usb_ep *ep = &dep->endpoint; | |
1225 | ||
04c03d10 FB |
1226 | request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC); |
1227 | if (!request) | |
1228 | return -ENOMEM; | |
1229 | ||
1230 | request->length = 0; | |
1231 | request->buf = dwc->zlp_buf; | |
1232 | request->complete = __dwc3_gadget_ep_zlp_complete; | |
1233 | ||
1234 | req = to_dwc3_request(request); | |
1235 | ||
1236 | return __dwc3_gadget_ep_queue(dep, req); | |
1237 | } | |
1238 | ||
72246da4 FB |
1239 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, |
1240 | gfp_t gfp_flags) | |
1241 | { | |
1242 | struct dwc3_request *req = to_dwc3_request(request); | |
1243 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1244 | struct dwc3 *dwc = dep->dwc; | |
1245 | ||
1246 | unsigned long flags; | |
1247 | ||
1248 | int ret; | |
1249 | ||
fdee4eba | 1250 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1251 | ret = __dwc3_gadget_ep_queue(dep, req); |
04c03d10 FB |
1252 | |
1253 | /* | |
1254 | * Okay, here's the thing, if gadget driver has requested for a ZLP by | |
1255 | * setting request->zero, instead of doing magic, we will just queue an | |
1256 | * extra usb_request ourselves so that it gets handled the same way as | |
1257 | * any other request. | |
1258 | */ | |
d9261898 JY |
1259 | if (ret == 0 && request->zero && request->length && |
1260 | (request->length % ep->maxpacket == 0)) | |
04c03d10 FB |
1261 | ret = __dwc3_gadget_ep_queue_zlp(dwc, dep); |
1262 | ||
72246da4 FB |
1263 | spin_unlock_irqrestore(&dwc->lock, flags); |
1264 | ||
1265 | return ret; | |
1266 | } | |
1267 | ||
1268 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1269 | struct usb_request *request) | |
1270 | { | |
1271 | struct dwc3_request *req = to_dwc3_request(request); | |
1272 | struct dwc3_request *r = NULL; | |
1273 | ||
1274 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1275 | struct dwc3 *dwc = dep->dwc; | |
1276 | ||
1277 | unsigned long flags; | |
1278 | int ret = 0; | |
1279 | ||
2c4cbe6e FB |
1280 | trace_dwc3_ep_dequeue(req); |
1281 | ||
72246da4 FB |
1282 | spin_lock_irqsave(&dwc->lock, flags); |
1283 | ||
aa3342c8 | 1284 | list_for_each_entry(r, &dep->pending_list, list) { |
72246da4 FB |
1285 | if (r == req) |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | if (r != req) { | |
aa3342c8 | 1290 | list_for_each_entry(r, &dep->started_list, list) { |
72246da4 FB |
1291 | if (r == req) |
1292 | break; | |
1293 | } | |
1294 | if (r == req) { | |
1295 | /* wait until it is processed */ | |
b992e681 | 1296 | dwc3_stop_active_transfer(dwc, dep->number, true); |
e8d4e8be | 1297 | goto out1; |
72246da4 FB |
1298 | } |
1299 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1300 | request, ep->name); | |
1301 | ret = -EINVAL; | |
1302 | goto out0; | |
1303 | } | |
1304 | ||
e8d4e8be | 1305 | out1: |
72246da4 FB |
1306 | /* giveback the request */ |
1307 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1308 | ||
1309 | out0: | |
1310 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1311 | ||
1312 | return ret; | |
1313 | } | |
1314 | ||
7a608559 | 1315 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) |
72246da4 FB |
1316 | { |
1317 | struct dwc3_gadget_ep_cmd_params params; | |
1318 | struct dwc3 *dwc = dep->dwc; | |
1319 | int ret; | |
1320 | ||
5ad02fb8 FB |
1321 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
1322 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); | |
1323 | return -EINVAL; | |
1324 | } | |
1325 | ||
72246da4 FB |
1326 | memset(¶ms, 0x00, sizeof(params)); |
1327 | ||
1328 | if (value) { | |
69450c4d FB |
1329 | struct dwc3_trb *trb; |
1330 | ||
1331 | unsigned transfer_in_flight; | |
1332 | unsigned started; | |
1333 | ||
1334 | if (dep->number > 1) | |
1335 | trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); | |
1336 | else | |
1337 | trb = &dwc->ep0_trb[dep->trb_enqueue]; | |
1338 | ||
1339 | transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; | |
1340 | started = !list_empty(&dep->started_list); | |
1341 | ||
1342 | if (!protocol && ((dep->direction && transfer_in_flight) || | |
1343 | (!dep->direction && started))) { | |
7a608559 FB |
1344 | return -EAGAIN; |
1345 | } | |
1346 | ||
2cd4718d FB |
1347 | ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, |
1348 | ¶ms); | |
72246da4 | 1349 | if (ret) |
3f89204b | 1350 | dev_err(dwc->dev, "failed to set STALL on %s\n", |
72246da4 FB |
1351 | dep->name); |
1352 | else | |
1353 | dep->flags |= DWC3_EP_STALL; | |
1354 | } else { | |
2cd4718d | 1355 | |
50c763f8 | 1356 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 | 1357 | if (ret) |
3f89204b | 1358 | dev_err(dwc->dev, "failed to clear STALL on %s\n", |
72246da4 FB |
1359 | dep->name); |
1360 | else | |
a535d81c | 1361 | dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); |
72246da4 | 1362 | } |
5275455a | 1363 | |
72246da4 FB |
1364 | return ret; |
1365 | } | |
1366 | ||
1367 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1368 | { | |
1369 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1370 | struct dwc3 *dwc = dep->dwc; | |
1371 | ||
1372 | unsigned long flags; | |
1373 | ||
1374 | int ret; | |
1375 | ||
1376 | spin_lock_irqsave(&dwc->lock, flags); | |
7a608559 | 1377 | ret = __dwc3_gadget_ep_set_halt(dep, value, false); |
72246da4 FB |
1378 | spin_unlock_irqrestore(&dwc->lock, flags); |
1379 | ||
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1384 | { | |
1385 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1386 | struct dwc3 *dwc = dep->dwc; |
1387 | unsigned long flags; | |
95aa4e8d | 1388 | int ret; |
72246da4 | 1389 | |
249a4569 | 1390 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 FB |
1391 | dep->flags |= DWC3_EP_WEDGE; |
1392 | ||
08f0d966 | 1393 | if (dep->number == 0 || dep->number == 1) |
95aa4e8d | 1394 | ret = __dwc3_gadget_ep0_set_halt(ep, 1); |
08f0d966 | 1395 | else |
7a608559 | 1396 | ret = __dwc3_gadget_ep_set_halt(dep, 1, false); |
95aa4e8d FB |
1397 | spin_unlock_irqrestore(&dwc->lock, flags); |
1398 | ||
1399 | return ret; | |
72246da4 FB |
1400 | } |
1401 | ||
1402 | /* -------------------------------------------------------------------------- */ | |
1403 | ||
1404 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1405 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1406 | .bDescriptorType = USB_DT_ENDPOINT, | |
1407 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1408 | }; | |
1409 | ||
1410 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1411 | .enable = dwc3_gadget_ep0_enable, | |
1412 | .disable = dwc3_gadget_ep0_disable, | |
1413 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1414 | .free_request = dwc3_gadget_ep_free_request, | |
1415 | .queue = dwc3_gadget_ep0_queue, | |
1416 | .dequeue = dwc3_gadget_ep_dequeue, | |
08f0d966 | 1417 | .set_halt = dwc3_gadget_ep0_set_halt, |
72246da4 FB |
1418 | .set_wedge = dwc3_gadget_ep_set_wedge, |
1419 | }; | |
1420 | ||
1421 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1422 | .enable = dwc3_gadget_ep_enable, | |
1423 | .disable = dwc3_gadget_ep_disable, | |
1424 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1425 | .free_request = dwc3_gadget_ep_free_request, | |
1426 | .queue = dwc3_gadget_ep_queue, | |
1427 | .dequeue = dwc3_gadget_ep_dequeue, | |
1428 | .set_halt = dwc3_gadget_ep_set_halt, | |
1429 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1430 | }; | |
1431 | ||
1432 | /* -------------------------------------------------------------------------- */ | |
1433 | ||
1434 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1435 | { | |
1436 | struct dwc3 *dwc = gadget_to_dwc(g); | |
72246da4 | 1437 | |
6cb2e4e3 | 1438 | return __dwc3_gadget_get_frame(dwc); |
72246da4 FB |
1439 | } |
1440 | ||
218ef7b6 | 1441 | static int __dwc3_gadget_wakeup(struct dwc3 *dwc) |
72246da4 | 1442 | { |
d6011f6f | 1443 | int retries; |
72246da4 | 1444 | |
218ef7b6 | 1445 | int ret; |
72246da4 FB |
1446 | u32 reg; |
1447 | ||
72246da4 FB |
1448 | u8 link_state; |
1449 | u8 speed; | |
1450 | ||
72246da4 FB |
1451 | /* |
1452 | * According to the Databook Remote wakeup request should | |
1453 | * be issued only when the device is in early suspend state. | |
1454 | * | |
1455 | * We can check that via USB Link State bits in DSTS register. | |
1456 | */ | |
1457 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1458 | ||
1459 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
ee5cd41c | 1460 | if ((speed == DWC3_DSTS_SUPERSPEED) || |
5eb30ced | 1461 | (speed == DWC3_DSTS_SUPERSPEED_PLUS)) |
6b742899 | 1462 | return 0; |
72246da4 FB |
1463 | |
1464 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1465 | ||
1466 | switch (link_state) { | |
1467 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1468 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1469 | break; | |
1470 | default: | |
218ef7b6 | 1471 | return -EINVAL; |
72246da4 FB |
1472 | } |
1473 | ||
8598bde7 FB |
1474 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1475 | if (ret < 0) { | |
1476 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
218ef7b6 | 1477 | return ret; |
8598bde7 | 1478 | } |
72246da4 | 1479 | |
802fde98 PZ |
1480 | /* Recent versions do this automatically */ |
1481 | if (dwc->revision < DWC3_REVISION_194A) { | |
1482 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1483 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1484 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1485 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1486 | } | |
72246da4 | 1487 | |
1d046793 | 1488 | /* poll until Link State changes to ON */ |
d6011f6f | 1489 | retries = 20000; |
72246da4 | 1490 | |
d6011f6f | 1491 | while (retries--) { |
72246da4 FB |
1492 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1493 | ||
1494 | /* in HS, means ON */ | |
1495 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1500 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
218ef7b6 | 1501 | return -EINVAL; |
72246da4 FB |
1502 | } |
1503 | ||
218ef7b6 FB |
1504 | return 0; |
1505 | } | |
1506 | ||
1507 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1508 | { | |
1509 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1510 | unsigned long flags; | |
1511 | int ret; | |
1512 | ||
1513 | spin_lock_irqsave(&dwc->lock, flags); | |
1514 | ret = __dwc3_gadget_wakeup(dwc); | |
72246da4 FB |
1515 | spin_unlock_irqrestore(&dwc->lock, flags); |
1516 | ||
1517 | return ret; | |
1518 | } | |
1519 | ||
1520 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1521 | int is_selfpowered) | |
1522 | { | |
1523 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1524 | unsigned long flags; |
72246da4 | 1525 | |
249a4569 | 1526 | spin_lock_irqsave(&dwc->lock, flags); |
bcdea503 | 1527 | g->is_selfpowered = !!is_selfpowered; |
249a4569 | 1528 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1529 | |
1530 | return 0; | |
1531 | } | |
1532 | ||
7b2a0368 | 1533 | static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) |
72246da4 FB |
1534 | { |
1535 | u32 reg; | |
61d58242 | 1536 | u32 timeout = 500; |
72246da4 | 1537 | |
fc8bb91b FB |
1538 | if (pm_runtime_suspended(dwc->dev)) |
1539 | return 0; | |
1540 | ||
72246da4 | 1541 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
8db7ed15 | 1542 | if (is_on) { |
802fde98 PZ |
1543 | if (dwc->revision <= DWC3_REVISION_187A) { |
1544 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1545 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1546 | } | |
1547 | ||
1548 | if (dwc->revision >= DWC3_REVISION_194A) | |
1549 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1550 | reg |= DWC3_DCTL_RUN_STOP; | |
7b2a0368 FB |
1551 | |
1552 | if (dwc->has_hibernation) | |
1553 | reg |= DWC3_DCTL_KEEP_CONNECT; | |
1554 | ||
9fcb3bd8 | 1555 | dwc->pullups_connected = true; |
8db7ed15 | 1556 | } else { |
72246da4 | 1557 | reg &= ~DWC3_DCTL_RUN_STOP; |
7b2a0368 FB |
1558 | |
1559 | if (dwc->has_hibernation && !suspend) | |
1560 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1561 | ||
9fcb3bd8 | 1562 | dwc->pullups_connected = false; |
8db7ed15 | 1563 | } |
72246da4 FB |
1564 | |
1565 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1566 | ||
1567 | do { | |
1568 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
b6d4e16e FB |
1569 | reg &= DWC3_DSTS_DEVCTRLHLT; |
1570 | } while (--timeout && !(!is_on ^ !reg)); | |
f2df679b FB |
1571 | |
1572 | if (!timeout) | |
1573 | return -ETIMEDOUT; | |
72246da4 | 1574 | |
6f17f74b | 1575 | return 0; |
72246da4 FB |
1576 | } |
1577 | ||
1578 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1579 | { | |
1580 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1581 | unsigned long flags; | |
6f17f74b | 1582 | int ret; |
72246da4 FB |
1583 | |
1584 | is_on = !!is_on; | |
1585 | ||
bb014736 BW |
1586 | /* |
1587 | * Per databook, when we want to stop the gadget, if a control transfer | |
1588 | * is still in process, complete it and get the core into setup phase. | |
1589 | */ | |
1590 | if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { | |
1591 | reinit_completion(&dwc->ep0_in_setup); | |
1592 | ||
1593 | ret = wait_for_completion_timeout(&dwc->ep0_in_setup, | |
1594 | msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); | |
1595 | if (ret == 0) { | |
1596 | dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); | |
1597 | return -ETIMEDOUT; | |
1598 | } | |
1599 | } | |
1600 | ||
72246da4 | 1601 | spin_lock_irqsave(&dwc->lock, flags); |
7b2a0368 | 1602 | ret = dwc3_gadget_run_stop(dwc, is_on, false); |
72246da4 FB |
1603 | spin_unlock_irqrestore(&dwc->lock, flags); |
1604 | ||
6f17f74b | 1605 | return ret; |
72246da4 FB |
1606 | } |
1607 | ||
8698e2ac FB |
1608 | static void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
1609 | { | |
1610 | u32 reg; | |
1611 | ||
1612 | /* Enable all but Start and End of Frame IRQs */ | |
1613 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
1614 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
1615 | DWC3_DEVTEN_CMDCMPLTEN | | |
1616 | DWC3_DEVTEN_ERRTICERREN | | |
1617 | DWC3_DEVTEN_WKUPEVTEN | | |
8698e2ac FB |
1618 | DWC3_DEVTEN_CONNECTDONEEN | |
1619 | DWC3_DEVTEN_USBRSTEN | | |
1620 | DWC3_DEVTEN_DISCONNEVTEN); | |
1621 | ||
799e9dc8 FB |
1622 | if (dwc->revision < DWC3_REVISION_250A) |
1623 | reg |= DWC3_DEVTEN_ULSTCNGEN; | |
1624 | ||
8698e2ac FB |
1625 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); |
1626 | } | |
1627 | ||
1628 | static void dwc3_gadget_disable_irq(struct dwc3 *dwc) | |
1629 | { | |
1630 | /* mask all interrupts */ | |
1631 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
1632 | } | |
1633 | ||
1634 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc); | |
b15a762f | 1635 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); |
8698e2ac | 1636 | |
4e99472b FB |
1637 | /** |
1638 | * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG | |
1639 | * dwc: pointer to our context structure | |
1640 | * | |
1641 | * The following looks like complex but it's actually very simple. In order to | |
1642 | * calculate the number of packets we can burst at once on OUT transfers, we're | |
1643 | * gonna use RxFIFO size. | |
1644 | * | |
1645 | * To calculate RxFIFO size we need two numbers: | |
1646 | * MDWIDTH = size, in bits, of the internal memory bus | |
1647 | * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) | |
1648 | * | |
1649 | * Given these two numbers, the formula is simple: | |
1650 | * | |
1651 | * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; | |
1652 | * | |
1653 | * 24 bytes is for 3x SETUP packets | |
1654 | * 16 bytes is a clock domain crossing tolerance | |
1655 | * | |
1656 | * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; | |
1657 | */ | |
1658 | static void dwc3_gadget_setup_nump(struct dwc3 *dwc) | |
1659 | { | |
1660 | u32 ram2_depth; | |
1661 | u32 mdwidth; | |
1662 | u32 nump; | |
1663 | u32 reg; | |
1664 | ||
1665 | ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); | |
1666 | mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); | |
1667 | ||
1668 | nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; | |
1669 | nump = min_t(u32, nump, 16); | |
1670 | ||
1671 | /* update NumP */ | |
1672 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1673 | reg &= ~DWC3_DCFG_NUMP_MASK; | |
1674 | reg |= nump << DWC3_DCFG_NUMP_SHIFT; | |
1675 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
1676 | } | |
1677 | ||
d7be2952 | 1678 | static int __dwc3_gadget_start(struct dwc3 *dwc) |
72246da4 | 1679 | { |
72246da4 | 1680 | struct dwc3_ep *dep; |
72246da4 FB |
1681 | int ret = 0; |
1682 | u32 reg; | |
1683 | ||
72246da4 FB |
1684 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1685 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1686 | |
1687 | /** | |
1688 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1689 | * which would cause metastability state on Run/Stop | |
1690 | * bit if we try to force the IP to USB2-only mode. | |
1691 | * | |
1692 | * Because of that, we cannot configure the IP to any | |
1693 | * speed other than the SuperSpeed | |
1694 | * | |
1695 | * Refers to: | |
1696 | * | |
1697 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1698 | * USB 2.0 Mode | |
1699 | */ | |
f7e846f0 | 1700 | if (dwc->revision < DWC3_REVISION_220A) { |
07e7f47b | 1701 | reg |= DWC3_DCFG_SUPERSPEED; |
f7e846f0 FB |
1702 | } else { |
1703 | switch (dwc->maximum_speed) { | |
1704 | case USB_SPEED_LOW: | |
2da9ad76 | 1705 | reg |= DWC3_DCFG_LOWSPEED; |
f7e846f0 FB |
1706 | break; |
1707 | case USB_SPEED_FULL: | |
2da9ad76 | 1708 | reg |= DWC3_DCFG_FULLSPEED1; |
f7e846f0 FB |
1709 | break; |
1710 | case USB_SPEED_HIGH: | |
2da9ad76 | 1711 | reg |= DWC3_DCFG_HIGHSPEED; |
f7e846f0 | 1712 | break; |
7580862b | 1713 | case USB_SPEED_SUPER_PLUS: |
2da9ad76 | 1714 | reg |= DWC3_DCFG_SUPERSPEED_PLUS; |
7580862b | 1715 | break; |
f7e846f0 | 1716 | default: |
77966eb8 JY |
1717 | dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n", |
1718 | dwc->maximum_speed); | |
1719 | /* fall through */ | |
1720 | case USB_SPEED_SUPER: | |
1721 | reg |= DWC3_DCFG_SUPERSPEED; | |
1722 | break; | |
f7e846f0 FB |
1723 | } |
1724 | } | |
72246da4 FB |
1725 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1726 | ||
2a58f9c1 FB |
1727 | /* |
1728 | * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP | |
1729 | * field instead of letting dwc3 itself calculate that automatically. | |
1730 | * | |
1731 | * This way, we maximize the chances that we'll be able to get several | |
1732 | * bursts of data without going through any sort of endpoint throttling. | |
1733 | */ | |
1734 | reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); | |
1735 | reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; | |
1736 | dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); | |
1737 | ||
4e99472b FB |
1738 | dwc3_gadget_setup_nump(dwc); |
1739 | ||
72246da4 FB |
1740 | /* Start with SuperSpeed Default */ |
1741 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1742 | ||
1743 | dep = dwc->eps[0]; | |
265b70a7 PZ |
1744 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1745 | false); | |
72246da4 FB |
1746 | if (ret) { |
1747 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1748 | goto err0; |
72246da4 FB |
1749 | } |
1750 | ||
1751 | dep = dwc->eps[1]; | |
265b70a7 PZ |
1752 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, |
1753 | false); | |
72246da4 FB |
1754 | if (ret) { |
1755 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
d7be2952 | 1756 | goto err1; |
72246da4 FB |
1757 | } |
1758 | ||
1759 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1760 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1761 | dwc3_ep0_out_start(dwc); |
1762 | ||
8698e2ac FB |
1763 | dwc3_gadget_enable_irq(dwc); |
1764 | ||
72246da4 FB |
1765 | return 0; |
1766 | ||
b0d7ffd4 | 1767 | err1: |
d7be2952 | 1768 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
b0d7ffd4 FB |
1769 | |
1770 | err0: | |
72246da4 FB |
1771 | return ret; |
1772 | } | |
1773 | ||
d7be2952 FB |
1774 | static int dwc3_gadget_start(struct usb_gadget *g, |
1775 | struct usb_gadget_driver *driver) | |
72246da4 FB |
1776 | { |
1777 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1778 | unsigned long flags; | |
d7be2952 | 1779 | int ret = 0; |
8698e2ac | 1780 | int irq; |
72246da4 | 1781 | |
9522def4 | 1782 | irq = dwc->irq_gadget; |
d7be2952 FB |
1783 | ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, |
1784 | IRQF_SHARED, "dwc3", dwc->ev_buf); | |
1785 | if (ret) { | |
1786 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
1787 | irq, ret); | |
1788 | goto err0; | |
1789 | } | |
1790 | ||
72246da4 | 1791 | spin_lock_irqsave(&dwc->lock, flags); |
d7be2952 FB |
1792 | if (dwc->gadget_driver) { |
1793 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1794 | dwc->gadget.name, | |
1795 | dwc->gadget_driver->driver.name); | |
1796 | ret = -EBUSY; | |
1797 | goto err1; | |
1798 | } | |
1799 | ||
1800 | dwc->gadget_driver = driver; | |
1801 | ||
fc8bb91b FB |
1802 | if (pm_runtime_active(dwc->dev)) |
1803 | __dwc3_gadget_start(dwc); | |
1804 | ||
d7be2952 FB |
1805 | spin_unlock_irqrestore(&dwc->lock, flags); |
1806 | ||
1807 | return 0; | |
1808 | ||
1809 | err1: | |
1810 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1811 | free_irq(irq, dwc); | |
1812 | ||
1813 | err0: | |
1814 | return ret; | |
1815 | } | |
72246da4 | 1816 | |
d7be2952 FB |
1817 | static void __dwc3_gadget_stop(struct dwc3 *dwc) |
1818 | { | |
8698e2ac | 1819 | dwc3_gadget_disable_irq(dwc); |
72246da4 FB |
1820 | __dwc3_gadget_ep_disable(dwc->eps[0]); |
1821 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
d7be2952 | 1822 | } |
72246da4 | 1823 | |
d7be2952 FB |
1824 | static int dwc3_gadget_stop(struct usb_gadget *g) |
1825 | { | |
1826 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1827 | unsigned long flags; | |
76a638f8 | 1828 | int epnum; |
72246da4 | 1829 | |
d7be2952 | 1830 | spin_lock_irqsave(&dwc->lock, flags); |
76a638f8 BW |
1831 | |
1832 | if (pm_runtime_suspended(dwc->dev)) | |
1833 | goto out; | |
1834 | ||
d7be2952 | 1835 | __dwc3_gadget_stop(dwc); |
76a638f8 BW |
1836 | |
1837 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1838 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
1839 | ||
1840 | if (!dep) | |
1841 | continue; | |
1842 | ||
1843 | if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
1844 | continue; | |
1845 | ||
1846 | wait_event_lock_irq(dep->wait_end_transfer, | |
1847 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING), | |
1848 | dwc->lock); | |
1849 | } | |
1850 | ||
1851 | out: | |
d7be2952 | 1852 | dwc->gadget_driver = NULL; |
72246da4 FB |
1853 | spin_unlock_irqrestore(&dwc->lock, flags); |
1854 | ||
3f308d17 | 1855 | free_irq(dwc->irq_gadget, dwc->ev_buf); |
b0d7ffd4 | 1856 | |
72246da4 FB |
1857 | return 0; |
1858 | } | |
802fde98 | 1859 | |
72246da4 FB |
1860 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1861 | .get_frame = dwc3_gadget_get_frame, | |
1862 | .wakeup = dwc3_gadget_wakeup, | |
1863 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1864 | .pullup = dwc3_gadget_pullup, | |
1865 | .udc_start = dwc3_gadget_start, | |
1866 | .udc_stop = dwc3_gadget_stop, | |
1867 | }; | |
1868 | ||
1869 | /* -------------------------------------------------------------------------- */ | |
1870 | ||
6a1e3ef4 FB |
1871 | static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, |
1872 | u8 num, u32 direction) | |
72246da4 FB |
1873 | { |
1874 | struct dwc3_ep *dep; | |
6a1e3ef4 | 1875 | u8 i; |
72246da4 | 1876 | |
6a1e3ef4 | 1877 | for (i = 0; i < num; i++) { |
d07fa665 | 1878 | u8 epnum = (i << 1) | (direction ? 1 : 0); |
72246da4 | 1879 | |
72246da4 | 1880 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); |
734d5a53 | 1881 | if (!dep) |
72246da4 | 1882 | return -ENOMEM; |
72246da4 FB |
1883 | |
1884 | dep->dwc = dwc; | |
1885 | dep->number = epnum; | |
9aa62ae4 | 1886 | dep->direction = !!direction; |
2eb88016 | 1887 | dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); |
72246da4 FB |
1888 | dwc->eps[epnum] = dep; |
1889 | ||
1890 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1891 | (epnum & 1) ? "in" : "out"); | |
6a1e3ef4 | 1892 | |
72246da4 | 1893 | dep->endpoint.name = dep->name; |
74674cbf | 1894 | spin_lock_init(&dep->lock); |
72246da4 FB |
1895 | |
1896 | if (epnum == 0 || epnum == 1) { | |
e117e742 | 1897 | usb_ep_set_maxpacket_limit(&dep->endpoint, 512); |
6048e4c6 | 1898 | dep->endpoint.maxburst = 1; |
72246da4 FB |
1899 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; |
1900 | if (!epnum) | |
1901 | dwc->gadget.ep0 = &dep->endpoint; | |
1902 | } else { | |
1903 | int ret; | |
1904 | ||
e117e742 | 1905 | usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); |
12d36c16 | 1906 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1907 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1908 | list_add_tail(&dep->endpoint.ep_list, | |
1909 | &dwc->gadget.ep_list); | |
1910 | ||
1911 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1912 | if (ret) |
72246da4 | 1913 | return ret; |
72246da4 | 1914 | } |
25b8ff68 | 1915 | |
a474d3b7 RB |
1916 | if (epnum == 0 || epnum == 1) { |
1917 | dep->endpoint.caps.type_control = true; | |
1918 | } else { | |
1919 | dep->endpoint.caps.type_iso = true; | |
1920 | dep->endpoint.caps.type_bulk = true; | |
1921 | dep->endpoint.caps.type_int = true; | |
1922 | } | |
1923 | ||
1924 | dep->endpoint.caps.dir_in = !!direction; | |
1925 | dep->endpoint.caps.dir_out = !direction; | |
1926 | ||
aa3342c8 FB |
1927 | INIT_LIST_HEAD(&dep->pending_list); |
1928 | INIT_LIST_HEAD(&dep->started_list); | |
72246da4 FB |
1929 | } |
1930 | ||
1931 | return 0; | |
1932 | } | |
1933 | ||
6a1e3ef4 FB |
1934 | static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) |
1935 | { | |
1936 | int ret; | |
1937 | ||
1938 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1939 | ||
1940 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); | |
1941 | if (ret < 0) { | |
5eb30ced | 1942 | dev_err(dwc->dev, "failed to initialize OUT endpoints\n"); |
6a1e3ef4 FB |
1943 | return ret; |
1944 | } | |
1945 | ||
1946 | ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); | |
1947 | if (ret < 0) { | |
5eb30ced | 1948 | dev_err(dwc->dev, "failed to initialize IN endpoints\n"); |
6a1e3ef4 FB |
1949 | return ret; |
1950 | } | |
1951 | ||
1952 | return 0; | |
1953 | } | |
1954 | ||
72246da4 FB |
1955 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) |
1956 | { | |
1957 | struct dwc3_ep *dep; | |
1958 | u8 epnum; | |
1959 | ||
1960 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1961 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
1962 | if (!dep) |
1963 | continue; | |
5bf8fae3 GC |
1964 | /* |
1965 | * Physical endpoints 0 and 1 are special; they form the | |
1966 | * bi-directional USB endpoint 0. | |
1967 | * | |
1968 | * For those two physical endpoints, we don't allocate a TRB | |
1969 | * pool nor do we add them the endpoints list. Due to that, we | |
1970 | * shouldn't do these two operations otherwise we would end up | |
1971 | * with all sorts of bugs when removing dwc3.ko. | |
1972 | */ | |
1973 | if (epnum != 0 && epnum != 1) { | |
1974 | dwc3_free_trb_pool(dep); | |
72246da4 | 1975 | list_del(&dep->endpoint.ep_list); |
5bf8fae3 | 1976 | } |
72246da4 FB |
1977 | |
1978 | kfree(dep); | |
1979 | } | |
1980 | } | |
1981 | ||
72246da4 | 1982 | /* -------------------------------------------------------------------------- */ |
e5caff68 | 1983 | |
e5ba5ec8 PA |
1984 | static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, |
1985 | struct dwc3_request *req, struct dwc3_trb *trb, | |
e5b36ae2 FB |
1986 | const struct dwc3_event_depevt *event, int status, |
1987 | int chain) | |
72246da4 | 1988 | { |
72246da4 FB |
1989 | unsigned int count; |
1990 | unsigned int s_pkt = 0; | |
d6d6ec7b | 1991 | unsigned int trb_status; |
72246da4 | 1992 | |
dc55c67e | 1993 | dwc3_ep_inc_deq(dep); |
a9c3ca5f FB |
1994 | |
1995 | if (req->trb == trb) | |
1996 | dep->queued_requests--; | |
1997 | ||
2c4cbe6e FB |
1998 | trace_dwc3_complete_trb(dep, trb); |
1999 | ||
e5b36ae2 FB |
2000 | /* |
2001 | * If we're in the middle of series of chained TRBs and we | |
2002 | * receive a short transfer along the way, DWC3 will skip | |
2003 | * through all TRBs including the last TRB in the chain (the | |
2004 | * where CHN bit is zero. DWC3 will also avoid clearing HWO | |
2005 | * bit and SW has to do it manually. | |
2006 | * | |
2007 | * We're going to do that here to avoid problems of HW trying | |
2008 | * to use bogus TRBs for transfers. | |
2009 | */ | |
2010 | if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) | |
2011 | trb->ctrl &= ~DWC3_TRB_CTRL_HWO; | |
2012 | ||
e5ba5ec8 | 2013 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
a0ad85ae | 2014 | return 1; |
e5b36ae2 | 2015 | |
e5ba5ec8 | 2016 | count = trb->size & DWC3_TRB_SIZE_MASK; |
e62c5bc5 | 2017 | req->remaining += count; |
e5ba5ec8 PA |
2018 | |
2019 | if (dep->direction) { | |
2020 | if (count) { | |
2021 | trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); | |
2022 | if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { | |
e5ba5ec8 PA |
2023 | /* |
2024 | * If missed isoc occurred and there is | |
2025 | * no request queued then issue END | |
2026 | * TRANSFER, so that core generates | |
2027 | * next xfernotready and we will issue | |
2028 | * a fresh START TRANSFER. | |
2029 | * If there are still queued request | |
2030 | * then wait, do not issue either END | |
2031 | * or UPDATE TRANSFER, just attach next | |
aa3342c8 | 2032 | * request in pending_list during |
e5ba5ec8 PA |
2033 | * giveback.If any future queued request |
2034 | * is successfully transferred then we | |
2035 | * will issue UPDATE TRANSFER for all | |
aa3342c8 | 2036 | * request in the pending_list. |
e5ba5ec8 PA |
2037 | */ |
2038 | dep->flags |= DWC3_EP_MISSED_ISOC; | |
2039 | } else { | |
2040 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
2041 | dep->name); | |
2042 | status = -ECONNRESET; | |
2043 | } | |
2044 | } else { | |
2045 | dep->flags &= ~DWC3_EP_MISSED_ISOC; | |
2046 | } | |
2047 | } else { | |
2048 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
2049 | s_pkt = 1; | |
2050 | } | |
2051 | ||
7c705dfe | 2052 | if (s_pkt && !chain) |
e5ba5ec8 | 2053 | return 1; |
f99f53f2 | 2054 | |
e5ba5ec8 PA |
2055 | if ((event->status & DEPEVT_STATUS_IOC) && |
2056 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2057 | return 1; | |
f99f53f2 | 2058 | |
e5ba5ec8 PA |
2059 | return 0; |
2060 | } | |
2061 | ||
2062 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
2063 | const struct dwc3_event_depevt *event, int status) | |
2064 | { | |
31162af4 | 2065 | struct dwc3_request *req, *n; |
e5ba5ec8 | 2066 | struct dwc3_trb *trb; |
d6e10bf2 | 2067 | bool ioc = false; |
e62c5bc5 | 2068 | int ret = 0; |
e5ba5ec8 | 2069 | |
31162af4 | 2070 | list_for_each_entry_safe(req, n, &dep->started_list, list) { |
1f512119 | 2071 | unsigned length; |
e5b36ae2 FB |
2072 | int chain; |
2073 | ||
1f512119 FB |
2074 | length = req->request.length; |
2075 | chain = req->num_pending_sgs > 0; | |
31162af4 | 2076 | if (chain) { |
1f512119 | 2077 | struct scatterlist *sg = req->sg; |
31162af4 | 2078 | struct scatterlist *s; |
1f512119 | 2079 | unsigned int pending = req->num_pending_sgs; |
31162af4 | 2080 | unsigned int i; |
c7de5734 | 2081 | |
1f512119 | 2082 | for_each_sg(sg, s, pending, i) { |
31162af4 | 2083 | trb = &dep->trb_pool[dep->trb_dequeue]; |
31162af4 | 2084 | |
7282c4ef FB |
2085 | if (trb->ctrl & DWC3_TRB_CTRL_HWO) |
2086 | break; | |
2087 | ||
1f512119 FB |
2088 | req->sg = sg_next(s); |
2089 | req->num_pending_sgs--; | |
2090 | ||
31162af4 FB |
2091 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
2092 | event, status, chain); | |
1f512119 FB |
2093 | if (ret) |
2094 | break; | |
31162af4 FB |
2095 | } |
2096 | } else { | |
737f1ae2 | 2097 | trb = &dep->trb_pool[dep->trb_dequeue]; |
d115d705 | 2098 | ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, |
e5b36ae2 | 2099 | event, status, chain); |
31162af4 | 2100 | } |
d115d705 | 2101 | |
e62c5bc5 | 2102 | req->request.actual = length - req->remaining; |
1f512119 | 2103 | |
ff377ae4 | 2104 | if ((req->request.actual < length) && req->num_pending_sgs) |
1f512119 FB |
2105 | return __dwc3_gadget_kick_transfer(dep, 0); |
2106 | ||
d115d705 | 2107 | dwc3_gadget_giveback(dep, req, status); |
e5ba5ec8 | 2108 | |
d6e10bf2 AB |
2109 | if (ret) { |
2110 | if ((event->status & DEPEVT_STATUS_IOC) && | |
2111 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
2112 | ioc = true; | |
72246da4 | 2113 | break; |
d6e10bf2 | 2114 | } |
31162af4 | 2115 | } |
72246da4 | 2116 | |
4cb42217 FB |
2117 | /* |
2118 | * Our endpoint might get disabled by another thread during | |
2119 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2120 | * early on so DWC3_EP_BUSY flag gets cleared | |
2121 | */ | |
2122 | if (!dep->endpoint.desc) | |
2123 | return 1; | |
2124 | ||
cdc359dd | 2125 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
aa3342c8 FB |
2126 | list_empty(&dep->started_list)) { |
2127 | if (list_empty(&dep->pending_list)) { | |
cdc359dd PA |
2128 | /* |
2129 | * If there is no entry in request list then do | |
2130 | * not issue END TRANSFER now. Just set PENDING | |
2131 | * flag, so that END TRANSFER is issued when an | |
2132 | * entry is added into request list. | |
2133 | */ | |
2134 | dep->flags = DWC3_EP_PENDING_REQUEST; | |
2135 | } else { | |
b992e681 | 2136 | dwc3_stop_active_transfer(dwc, dep->number, true); |
cdc359dd PA |
2137 | dep->flags = DWC3_EP_ENABLED; |
2138 | } | |
7efea86c PA |
2139 | return 1; |
2140 | } | |
2141 | ||
d6e10bf2 AB |
2142 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc) |
2143 | return 0; | |
2144 | ||
72246da4 FB |
2145 | return 1; |
2146 | } | |
2147 | ||
2148 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
029d97ff | 2149 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) |
72246da4 FB |
2150 | { |
2151 | unsigned status = 0; | |
2152 | int clean_busy; | |
e18b7975 FB |
2153 | u32 is_xfer_complete; |
2154 | ||
2155 | is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE); | |
72246da4 FB |
2156 | |
2157 | if (event->status & DEPEVT_STATUS_BUSERR) | |
2158 | status = -ECONNRESET; | |
2159 | ||
1d046793 | 2160 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
4cb42217 | 2161 | if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || |
e18b7975 | 2162 | usb_endpoint_xfer_isoc(dep->endpoint.desc))) |
72246da4 | 2163 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
2164 | |
2165 | /* | |
2166 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
2167 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
2168 | */ | |
2169 | if (dwc->revision < DWC3_REVISION_183A) { | |
2170 | u32 reg; | |
2171 | int i; | |
2172 | ||
2173 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
348e026f | 2174 | dep = dwc->eps[i]; |
fae2b904 FB |
2175 | |
2176 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
2177 | continue; | |
2178 | ||
aa3342c8 | 2179 | if (!list_empty(&dep->started_list)) |
fae2b904 FB |
2180 | return; |
2181 | } | |
2182 | ||
2183 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2184 | reg |= dwc->u1u2; | |
2185 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2186 | ||
2187 | dwc->u1u2 = 0; | |
2188 | } | |
8a1a9c9e | 2189 | |
4cb42217 FB |
2190 | /* |
2191 | * Our endpoint might get disabled by another thread during | |
2192 | * dwc3_gadget_giveback(). If that happens, we're just gonna return 1 | |
2193 | * early on so DWC3_EP_BUSY flag gets cleared | |
2194 | */ | |
2195 | if (!dep->endpoint.desc) | |
2196 | return; | |
2197 | ||
e6e709b7 | 2198 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8a1a9c9e FB |
2199 | int ret; |
2200 | ||
4fae2e3e | 2201 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
8a1a9c9e FB |
2202 | if (!ret || ret == -EBUSY) |
2203 | return; | |
2204 | } | |
72246da4 FB |
2205 | } |
2206 | ||
72246da4 FB |
2207 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, |
2208 | const struct dwc3_event_depevt *event) | |
2209 | { | |
2210 | struct dwc3_ep *dep; | |
2211 | u8 epnum = event->endpoint_number; | |
76a638f8 | 2212 | u8 cmd; |
72246da4 FB |
2213 | |
2214 | dep = dwc->eps[epnum]; | |
2215 | ||
76a638f8 BW |
2216 | if (!(dep->flags & DWC3_EP_ENABLED) && |
2217 | !(dep->flags & DWC3_EP_END_TRANSFER_PENDING)) | |
3336abb5 FB |
2218 | return; |
2219 | ||
72246da4 FB |
2220 | if (epnum == 0 || epnum == 1) { |
2221 | dwc3_ep0_interrupt(dwc, event); | |
2222 | return; | |
2223 | } | |
2224 | ||
2225 | switch (event->endpoint_event) { | |
2226 | case DWC3_DEPEVT_XFERCOMPLETE: | |
b4996a86 | 2227 | dep->resource_index = 0; |
c2df85ca | 2228 | |
16e78db7 | 2229 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8566cd1a | 2230 | dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n"); |
72246da4 FB |
2231 | return; |
2232 | } | |
2233 | ||
029d97ff | 2234 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2235 | break; |
2236 | case DWC3_DEPEVT_XFERINPROGRESS: | |
029d97ff | 2237 | dwc3_endpoint_transfer_complete(dwc, dep, event); |
72246da4 FB |
2238 | break; |
2239 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 2240 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
2241 | dwc3_gadget_start_isoc(dwc, dep, event); |
2242 | } else { | |
2243 | int ret; | |
2244 | ||
4fae2e3e | 2245 | ret = __dwc3_gadget_kick_transfer(dep, 0); |
72246da4 FB |
2246 | if (!ret || ret == -EBUSY) |
2247 | return; | |
72246da4 FB |
2248 | } |
2249 | ||
879631aa FB |
2250 | break; |
2251 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 2252 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
2253 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
2254 | dep->name); | |
2255 | return; | |
2256 | } | |
72246da4 | 2257 | break; |
72246da4 | 2258 | case DWC3_DEPEVT_EPCMDCMPLT: |
76a638f8 BW |
2259 | cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
2260 | ||
2261 | if (cmd == DWC3_DEPCMD_ENDTRANSFER) { | |
2262 | dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; | |
2263 | wake_up(&dep->wait_end_transfer); | |
2264 | } | |
2265 | break; | |
2266 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
72246da4 FB |
2267 | break; |
2268 | } | |
2269 | } | |
2270 | ||
2271 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
2272 | { | |
2273 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
2274 | spin_unlock(&dwc->lock); | |
2275 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
2276 | spin_lock(&dwc->lock); | |
2277 | } | |
2278 | } | |
2279 | ||
bc5ba2e0 FB |
2280 | static void dwc3_suspend_gadget(struct dwc3 *dwc) |
2281 | { | |
73a30bfc | 2282 | if (dwc->gadget_driver && dwc->gadget_driver->suspend) { |
bc5ba2e0 FB |
2283 | spin_unlock(&dwc->lock); |
2284 | dwc->gadget_driver->suspend(&dwc->gadget); | |
2285 | spin_lock(&dwc->lock); | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | static void dwc3_resume_gadget(struct dwc3 *dwc) | |
2290 | { | |
73a30bfc | 2291 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
bc5ba2e0 FB |
2292 | spin_unlock(&dwc->lock); |
2293 | dwc->gadget_driver->resume(&dwc->gadget); | |
5c7b3b02 | 2294 | spin_lock(&dwc->lock); |
8e74475b FB |
2295 | } |
2296 | } | |
2297 | ||
2298 | static void dwc3_reset_gadget(struct dwc3 *dwc) | |
2299 | { | |
2300 | if (!dwc->gadget_driver) | |
2301 | return; | |
2302 | ||
2303 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { | |
2304 | spin_unlock(&dwc->lock); | |
2305 | usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); | |
bc5ba2e0 FB |
2306 | spin_lock(&dwc->lock); |
2307 | } | |
2308 | } | |
2309 | ||
b992e681 | 2310 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) |
72246da4 FB |
2311 | { |
2312 | struct dwc3_ep *dep; | |
2313 | struct dwc3_gadget_ep_cmd_params params; | |
2314 | u32 cmd; | |
2315 | int ret; | |
2316 | ||
2317 | dep = dwc->eps[epnum]; | |
2318 | ||
76a638f8 BW |
2319 | if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || |
2320 | !dep->resource_index) | |
3daf74d7 PA |
2321 | return; |
2322 | ||
57911504 PA |
2323 | /* |
2324 | * NOTICE: We are violating what the Databook says about the | |
2325 | * EndTransfer command. Ideally we would _always_ wait for the | |
2326 | * EndTransfer Command Completion IRQ, but that's causing too | |
2327 | * much trouble synchronizing between us and gadget driver. | |
2328 | * | |
2329 | * We have discussed this with the IP Provider and it was | |
2330 | * suggested to giveback all requests here, but give HW some | |
2331 | * extra time to synchronize with the interconnect. We're using | |
dc93b41a | 2332 | * an arbitrary 100us delay for that. |
57911504 PA |
2333 | * |
2334 | * Note also that a similar handling was tested by Synopsys | |
2335 | * (thanks a lot Paul) and nothing bad has come out of it. | |
2336 | * In short, what we're doing is: | |
2337 | * | |
2338 | * - Issue EndTransfer WITH CMDIOC bit set | |
2339 | * - Wait 100us | |
06281d46 JY |
2340 | * |
2341 | * As of IP version 3.10a of the DWC_usb3 IP, the controller | |
2342 | * supports a mode to work around the above limitation. The | |
2343 | * software can poll the CMDACT bit in the DEPCMD register | |
2344 | * after issuing a EndTransfer command. This mode is enabled | |
2345 | * by writing GUCTL2[14]. This polling is already done in the | |
2346 | * dwc3_send_gadget_ep_cmd() function so if the mode is | |
2347 | * enabled, the EndTransfer command will have completed upon | |
2348 | * returning from this function and we don't need to delay for | |
2349 | * 100us. | |
2350 | * | |
2351 | * This mode is NOT available on the DWC_usb31 IP. | |
57911504 PA |
2352 | */ |
2353 | ||
3daf74d7 | 2354 | cmd = DWC3_DEPCMD_ENDTRANSFER; |
b992e681 PZ |
2355 | cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; |
2356 | cmd |= DWC3_DEPCMD_CMDIOC; | |
b4996a86 | 2357 | cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
3daf74d7 | 2358 | memset(¶ms, 0, sizeof(params)); |
2cd4718d | 2359 | ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
3daf74d7 | 2360 | WARN_ON_ONCE(ret); |
b4996a86 | 2361 | dep->resource_index = 0; |
041d81f4 | 2362 | dep->flags &= ~DWC3_EP_BUSY; |
06281d46 | 2363 | |
76a638f8 BW |
2364 | if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) { |
2365 | dep->flags |= DWC3_EP_END_TRANSFER_PENDING; | |
06281d46 | 2366 | udelay(100); |
76a638f8 | 2367 | } |
72246da4 FB |
2368 | } |
2369 | ||
72246da4 FB |
2370 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) |
2371 | { | |
2372 | u32 epnum; | |
2373 | ||
2374 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
2375 | struct dwc3_ep *dep; | |
72246da4 FB |
2376 | int ret; |
2377 | ||
2378 | dep = dwc->eps[epnum]; | |
6a1e3ef4 FB |
2379 | if (!dep) |
2380 | continue; | |
72246da4 FB |
2381 | |
2382 | if (!(dep->flags & DWC3_EP_STALL)) | |
2383 | continue; | |
2384 | ||
2385 | dep->flags &= ~DWC3_EP_STALL; | |
2386 | ||
50c763f8 | 2387 | ret = dwc3_send_clear_stall_ep_cmd(dep); |
72246da4 FB |
2388 | WARN_ON_ONCE(ret); |
2389 | } | |
2390 | } | |
2391 | ||
2392 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
2393 | { | |
c4430a26 FB |
2394 | int reg; |
2395 | ||
72246da4 FB |
2396 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
2397 | reg &= ~DWC3_DCTL_INITU1ENA; | |
2398 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2399 | ||
2400 | reg &= ~DWC3_DCTL_INITU2ENA; | |
2401 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
72246da4 | 2402 | |
72246da4 FB |
2403 | dwc3_disconnect_gadget(dwc); |
2404 | ||
2405 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 2406 | dwc->setup_packet_pending = false; |
06a374ed | 2407 | usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); |
fc8bb91b FB |
2408 | |
2409 | dwc->connected = false; | |
72246da4 FB |
2410 | } |
2411 | ||
72246da4 FB |
2412 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) |
2413 | { | |
2414 | u32 reg; | |
2415 | ||
fc8bb91b FB |
2416 | dwc->connected = true; |
2417 | ||
df62df56 FB |
2418 | /* |
2419 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
2420 | * would cause a missing Disconnect Event if there's a | |
2421 | * pending Setup Packet in the FIFO. | |
2422 | * | |
2423 | * There's no suggested workaround on the official Bug | |
2424 | * report, which states that "unless the driver/application | |
2425 | * is doing any special handling of a disconnect event, | |
2426 | * there is no functional issue". | |
2427 | * | |
2428 | * Unfortunately, it turns out that we _do_ some special | |
2429 | * handling of a disconnect event, namely complete all | |
2430 | * pending transfers, notify gadget driver of the | |
2431 | * disconnection, and so on. | |
2432 | * | |
2433 | * Our suggested workaround is to follow the Disconnect | |
2434 | * Event steps here, instead, based on a setup_packet_pending | |
b5d335e5 FB |
2435 | * flag. Such flag gets set whenever we have a SETUP_PENDING |
2436 | * status for EP0 TRBs and gets cleared on XferComplete for the | |
df62df56 FB |
2437 | * same endpoint. |
2438 | * | |
2439 | * Refers to: | |
2440 | * | |
2441 | * STAR#9000466709: RTL: Device : Disconnect event not | |
2442 | * generated if setup packet pending in FIFO | |
2443 | */ | |
2444 | if (dwc->revision < DWC3_REVISION_188A) { | |
2445 | if (dwc->setup_packet_pending) | |
2446 | dwc3_gadget_disconnect_interrupt(dwc); | |
2447 | } | |
2448 | ||
8e74475b | 2449 | dwc3_reset_gadget(dwc); |
72246da4 FB |
2450 | |
2451 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2452 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
2453 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
3b637367 | 2454 | dwc->test_mode = false; |
72246da4 FB |
2455 | dwc3_clear_stall_all_ep(dwc); |
2456 | ||
2457 | /* Reset device address to zero */ | |
2458 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2459 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2460 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2461 | } |
2462 | ||
2463 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2464 | { | |
2465 | u32 reg; | |
2466 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2467 | ||
2468 | /* | |
2469 | * We change the clock only at SS but I dunno why I would want to do | |
2470 | * this. Maybe it becomes part of the power saving plan. | |
2471 | */ | |
2472 | ||
ee5cd41c JY |
2473 | if ((speed != DWC3_DSTS_SUPERSPEED) && |
2474 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) | |
72246da4 FB |
2475 | return; |
2476 | ||
2477 | /* | |
2478 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2479 | * each time on Connect Done. | |
2480 | */ | |
2481 | if (!usb30_clock) | |
2482 | return; | |
2483 | ||
2484 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2485 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2486 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2487 | } | |
2488 | ||
72246da4 FB |
2489 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) |
2490 | { | |
72246da4 FB |
2491 | struct dwc3_ep *dep; |
2492 | int ret; | |
2493 | u32 reg; | |
2494 | u8 speed; | |
2495 | ||
72246da4 FB |
2496 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2497 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2498 | dwc->speed = speed; | |
2499 | ||
2500 | dwc3_update_ram_clk_sel(dwc, speed); | |
2501 | ||
2502 | switch (speed) { | |
2da9ad76 | 2503 | case DWC3_DSTS_SUPERSPEED_PLUS: |
7580862b JY |
2504 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2505 | dwc->gadget.ep0->maxpacket = 512; | |
2506 | dwc->gadget.speed = USB_SPEED_SUPER_PLUS; | |
2507 | break; | |
2da9ad76 | 2508 | case DWC3_DSTS_SUPERSPEED: |
05870c5b FB |
2509 | /* |
2510 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2511 | * would cause a missing USB3 Reset event. | |
2512 | * | |
2513 | * In such situations, we should force a USB3 Reset | |
2514 | * event by calling our dwc3_gadget_reset_interrupt() | |
2515 | * routine. | |
2516 | * | |
2517 | * Refers to: | |
2518 | * | |
2519 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2520 | * not be generated always when the link enters poll | |
2521 | */ | |
2522 | if (dwc->revision < DWC3_REVISION_190A) | |
2523 | dwc3_gadget_reset_interrupt(dwc); | |
2524 | ||
72246da4 FB |
2525 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2526 | dwc->gadget.ep0->maxpacket = 512; | |
2527 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2528 | break; | |
2da9ad76 | 2529 | case DWC3_DSTS_HIGHSPEED: |
72246da4 FB |
2530 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2531 | dwc->gadget.ep0->maxpacket = 64; | |
2532 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2533 | break; | |
2da9ad76 JY |
2534 | case DWC3_DSTS_FULLSPEED2: |
2535 | case DWC3_DSTS_FULLSPEED1: | |
72246da4 FB |
2536 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); |
2537 | dwc->gadget.ep0->maxpacket = 64; | |
2538 | dwc->gadget.speed = USB_SPEED_FULL; | |
2539 | break; | |
2da9ad76 | 2540 | case DWC3_DSTS_LOWSPEED: |
72246da4 FB |
2541 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); |
2542 | dwc->gadget.ep0->maxpacket = 8; | |
2543 | dwc->gadget.speed = USB_SPEED_LOW; | |
2544 | break; | |
2545 | } | |
2546 | ||
2b758350 PA |
2547 | /* Enable USB2 LPM Capability */ |
2548 | ||
ee5cd41c | 2549 | if ((dwc->revision > DWC3_REVISION_194A) && |
2da9ad76 JY |
2550 | (speed != DWC3_DSTS_SUPERSPEED) && |
2551 | (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { | |
2b758350 PA |
2552 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2553 | reg |= DWC3_DCFG_LPM_CAP; | |
2554 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2555 | ||
2556 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2557 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2558 | ||
460d098c | 2559 | reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); |
2b758350 | 2560 | |
80caf7d2 HR |
2561 | /* |
2562 | * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and | |
2563 | * DCFG.LPMCap is set, core responses with an ACK and the | |
2564 | * BESL value in the LPM token is less than or equal to LPM | |
2565 | * NYET threshold. | |
2566 | */ | |
2567 | WARN_ONCE(dwc->revision < DWC3_REVISION_240A | |
2568 | && dwc->has_lpm_erratum, | |
2569 | "LPM Erratum not available on dwc3 revisisions < 2.40a\n"); | |
2570 | ||
2571 | if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) | |
2572 | reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold); | |
2573 | ||
356363bf FB |
2574 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2575 | } else { | |
2576 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2577 | reg &= ~DWC3_DCTL_HIRD_THRES_MASK; | |
2b758350 PA |
2578 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
2579 | } | |
2580 | ||
72246da4 | 2581 | dep = dwc->eps[0]; |
265b70a7 PZ |
2582 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2583 | false); | |
72246da4 FB |
2584 | if (ret) { |
2585 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2586 | return; | |
2587 | } | |
2588 | ||
2589 | dep = dwc->eps[1]; | |
265b70a7 PZ |
2590 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, |
2591 | false); | |
72246da4 FB |
2592 | if (ret) { |
2593 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2594 | return; | |
2595 | } | |
2596 | ||
2597 | /* | |
2598 | * Configure PHY via GUSB3PIPECTLn if required. | |
2599 | * | |
2600 | * Update GTXFIFOSIZn | |
2601 | * | |
2602 | * In both cases reset values should be sufficient. | |
2603 | */ | |
2604 | } | |
2605 | ||
2606 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2607 | { | |
72246da4 FB |
2608 | /* |
2609 | * TODO take core out of low power mode when that's | |
2610 | * implemented. | |
2611 | */ | |
2612 | ||
ad14d4e0 JL |
2613 | if (dwc->gadget_driver && dwc->gadget_driver->resume) { |
2614 | spin_unlock(&dwc->lock); | |
2615 | dwc->gadget_driver->resume(&dwc->gadget); | |
2616 | spin_lock(&dwc->lock); | |
2617 | } | |
72246da4 FB |
2618 | } |
2619 | ||
2620 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2621 | unsigned int evtinfo) | |
2622 | { | |
fae2b904 | 2623 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
0b0cc1cd FB |
2624 | unsigned int pwropt; |
2625 | ||
2626 | /* | |
2627 | * WORKAROUND: DWC3 < 2.50a have an issue when configured without | |
2628 | * Hibernation mode enabled which would show up when device detects | |
2629 | * host-initiated U3 exit. | |
2630 | * | |
2631 | * In that case, device will generate a Link State Change Interrupt | |
2632 | * from U3 to RESUME which is only necessary if Hibernation is | |
2633 | * configured in. | |
2634 | * | |
2635 | * There are no functional changes due to such spurious event and we | |
2636 | * just need to ignore it. | |
2637 | * | |
2638 | * Refers to: | |
2639 | * | |
2640 | * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation | |
2641 | * operational mode | |
2642 | */ | |
2643 | pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); | |
2644 | if ((dwc->revision < DWC3_REVISION_250A) && | |
2645 | (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { | |
2646 | if ((dwc->link_state == DWC3_LINK_STATE_U3) && | |
2647 | (next == DWC3_LINK_STATE_RESUME)) { | |
0b0cc1cd FB |
2648 | return; |
2649 | } | |
2650 | } | |
fae2b904 FB |
2651 | |
2652 | /* | |
2653 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2654 | * on the link partner, the USB session might do multiple entry/exit | |
2655 | * of low power states before a transfer takes place. | |
2656 | * | |
2657 | * Due to this problem, we might experience lower throughput. The | |
2658 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2659 | * transitioning from U1/U2 to U0 and enable those bits again | |
2660 | * after a transfer completes and there are no pending transfers | |
2661 | * on any of the enabled endpoints. | |
2662 | * | |
2663 | * This is the first half of that workaround. | |
2664 | * | |
2665 | * Refers to: | |
2666 | * | |
2667 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2668 | * core send LGO_Ux entering U0 | |
2669 | */ | |
2670 | if (dwc->revision < DWC3_REVISION_183A) { | |
2671 | if (next == DWC3_LINK_STATE_U0) { | |
2672 | u32 u1u2; | |
2673 | u32 reg; | |
2674 | ||
2675 | switch (dwc->link_state) { | |
2676 | case DWC3_LINK_STATE_U1: | |
2677 | case DWC3_LINK_STATE_U2: | |
2678 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2679 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2680 | | DWC3_DCTL_ACCEPTU2ENA | |
2681 | | DWC3_DCTL_INITU1ENA | |
2682 | | DWC3_DCTL_ACCEPTU1ENA); | |
2683 | ||
2684 | if (!dwc->u1u2) | |
2685 | dwc->u1u2 = reg & u1u2; | |
2686 | ||
2687 | reg &= ~u1u2; | |
2688 | ||
2689 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2690 | break; | |
2691 | default: | |
2692 | /* do nothing */ | |
2693 | break; | |
2694 | } | |
2695 | } | |
2696 | } | |
2697 | ||
bc5ba2e0 FB |
2698 | switch (next) { |
2699 | case DWC3_LINK_STATE_U1: | |
2700 | if (dwc->speed == USB_SPEED_SUPER) | |
2701 | dwc3_suspend_gadget(dwc); | |
2702 | break; | |
2703 | case DWC3_LINK_STATE_U2: | |
2704 | case DWC3_LINK_STATE_U3: | |
2705 | dwc3_suspend_gadget(dwc); | |
2706 | break; | |
2707 | case DWC3_LINK_STATE_RESUME: | |
2708 | dwc3_resume_gadget(dwc); | |
2709 | break; | |
2710 | default: | |
2711 | /* do nothing */ | |
2712 | break; | |
2713 | } | |
2714 | ||
e57ebc1d | 2715 | dwc->link_state = next; |
72246da4 FB |
2716 | } |
2717 | ||
72704f87 BW |
2718 | static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, |
2719 | unsigned int evtinfo) | |
2720 | { | |
2721 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; | |
2722 | ||
2723 | if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) | |
2724 | dwc3_suspend_gadget(dwc); | |
2725 | ||
2726 | dwc->link_state = next; | |
2727 | } | |
2728 | ||
e1dadd3b FB |
2729 | static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, |
2730 | unsigned int evtinfo) | |
2731 | { | |
2732 | unsigned int is_ss = evtinfo & BIT(4); | |
2733 | ||
2734 | /** | |
2735 | * WORKAROUND: DWC3 revison 2.20a with hibernation support | |
2736 | * have a known issue which can cause USB CV TD.9.23 to fail | |
2737 | * randomly. | |
2738 | * | |
2739 | * Because of this issue, core could generate bogus hibernation | |
2740 | * events which SW needs to ignore. | |
2741 | * | |
2742 | * Refers to: | |
2743 | * | |
2744 | * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 | |
2745 | * Device Fallback from SuperSpeed | |
2746 | */ | |
2747 | if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) | |
2748 | return; | |
2749 | ||
2750 | /* enter hibernation here */ | |
2751 | } | |
2752 | ||
72246da4 FB |
2753 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, |
2754 | const struct dwc3_event_devt *event) | |
2755 | { | |
2756 | switch (event->type) { | |
2757 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2758 | dwc3_gadget_disconnect_interrupt(dwc); | |
2759 | break; | |
2760 | case DWC3_DEVICE_EVENT_RESET: | |
2761 | dwc3_gadget_reset_interrupt(dwc); | |
2762 | break; | |
2763 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2764 | dwc3_gadget_conndone_interrupt(dwc); | |
2765 | break; | |
2766 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2767 | dwc3_gadget_wakeup_interrupt(dwc); | |
2768 | break; | |
e1dadd3b FB |
2769 | case DWC3_DEVICE_EVENT_HIBER_REQ: |
2770 | if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, | |
2771 | "unexpected hibernation event\n")) | |
2772 | break; | |
2773 | ||
2774 | dwc3_gadget_hibernation_interrupt(dwc, event->event_info); | |
2775 | break; | |
72246da4 FB |
2776 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: |
2777 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2778 | break; | |
2779 | case DWC3_DEVICE_EVENT_EOPF: | |
72704f87 | 2780 | /* It changed to be suspend event for version 2.30a and above */ |
5eb30ced | 2781 | if (dwc->revision >= DWC3_REVISION_230A) { |
72704f87 BW |
2782 | /* |
2783 | * Ignore suspend event until the gadget enters into | |
2784 | * USB_STATE_CONFIGURED state. | |
2785 | */ | |
2786 | if (dwc->gadget.state >= USB_STATE_CONFIGURED) | |
2787 | dwc3_gadget_suspend_interrupt(dwc, | |
2788 | event->event_info); | |
2789 | } | |
72246da4 FB |
2790 | break; |
2791 | case DWC3_DEVICE_EVENT_SOF: | |
72246da4 | 2792 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: |
72246da4 | 2793 | case DWC3_DEVICE_EVENT_CMD_CMPL: |
72246da4 | 2794 | case DWC3_DEVICE_EVENT_OVERFLOW: |
72246da4 FB |
2795 | break; |
2796 | default: | |
e9f2aa87 | 2797 | dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); |
72246da4 FB |
2798 | } |
2799 | } | |
2800 | ||
2801 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2802 | const union dwc3_event *event) | |
2803 | { | |
43c96be1 | 2804 | trace_dwc3_event(event->raw, dwc); |
2c4cbe6e | 2805 | |
72246da4 FB |
2806 | /* Endpoint IRQ, handle it and return early */ |
2807 | if (event->type.is_devspec == 0) { | |
2808 | /* depevt */ | |
2809 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2810 | } | |
2811 | ||
2812 | switch (event->type.type) { | |
2813 | case DWC3_EVENT_TYPE_DEV: | |
2814 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2815 | break; | |
2816 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2817 | default: | |
2818 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2819 | } | |
2820 | } | |
2821 | ||
dea520a4 | 2822 | static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) |
b15a762f | 2823 | { |
dea520a4 | 2824 | struct dwc3 *dwc = evt->dwc; |
b15a762f | 2825 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2826 | int left; |
e8adfc30 | 2827 | u32 reg; |
b15a762f | 2828 | |
f42f2447 | 2829 | left = evt->count; |
b15a762f | 2830 | |
f42f2447 FB |
2831 | if (!(evt->flags & DWC3_EVENT_PENDING)) |
2832 | return IRQ_NONE; | |
b15a762f | 2833 | |
f42f2447 FB |
2834 | while (left > 0) { |
2835 | union dwc3_event event; | |
b15a762f | 2836 | |
f42f2447 | 2837 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
b15a762f | 2838 | |
f42f2447 | 2839 | dwc3_process_event_entry(dwc, &event); |
b15a762f | 2840 | |
f42f2447 FB |
2841 | /* |
2842 | * FIXME we wrap around correctly to the next entry as | |
2843 | * almost all entries are 4 bytes in size. There is one | |
2844 | * entry which has 12 bytes which is a regular entry | |
2845 | * followed by 8 bytes data. ATM I don't know how | |
2846 | * things are organized if we get next to the a | |
2847 | * boundary so I worry about that once we try to handle | |
2848 | * that. | |
2849 | */ | |
2850 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2851 | left -= 4; | |
b15a762f | 2852 | |
660e9bde | 2853 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); |
f42f2447 | 2854 | } |
b15a762f | 2855 | |
f42f2447 FB |
2856 | evt->count = 0; |
2857 | evt->flags &= ~DWC3_EVENT_PENDING; | |
2858 | ret = IRQ_HANDLED; | |
b15a762f | 2859 | |
f42f2447 | 2860 | /* Unmask interrupt */ |
660e9bde | 2861 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
f42f2447 | 2862 | reg &= ~DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2863 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
b15a762f | 2864 | |
f42f2447 FB |
2865 | return ret; |
2866 | } | |
e8adfc30 | 2867 | |
dea520a4 | 2868 | static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) |
f42f2447 | 2869 | { |
dea520a4 FB |
2870 | struct dwc3_event_buffer *evt = _evt; |
2871 | struct dwc3 *dwc = evt->dwc; | |
e5f68b4a | 2872 | unsigned long flags; |
f42f2447 | 2873 | irqreturn_t ret = IRQ_NONE; |
f42f2447 | 2874 | |
e5f68b4a | 2875 | spin_lock_irqsave(&dwc->lock, flags); |
dea520a4 | 2876 | ret = dwc3_process_event_buf(evt); |
e5f68b4a | 2877 | spin_unlock_irqrestore(&dwc->lock, flags); |
b15a762f FB |
2878 | |
2879 | return ret; | |
2880 | } | |
2881 | ||
dea520a4 | 2882 | static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) |
72246da4 | 2883 | { |
dea520a4 | 2884 | struct dwc3 *dwc = evt->dwc; |
72246da4 | 2885 | u32 count; |
e8adfc30 | 2886 | u32 reg; |
72246da4 | 2887 | |
fc8bb91b FB |
2888 | if (pm_runtime_suspended(dwc->dev)) { |
2889 | pm_runtime_get(dwc->dev); | |
2890 | disable_irq_nosync(dwc->irq_gadget); | |
2891 | dwc->pending_events = true; | |
2892 | return IRQ_HANDLED; | |
2893 | } | |
2894 | ||
660e9bde | 2895 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); |
72246da4 FB |
2896 | count &= DWC3_GEVNTCOUNT_MASK; |
2897 | if (!count) | |
2898 | return IRQ_NONE; | |
2899 | ||
b15a762f FB |
2900 | evt->count = count; |
2901 | evt->flags |= DWC3_EVENT_PENDING; | |
72246da4 | 2902 | |
e8adfc30 | 2903 | /* Mask interrupt */ |
660e9bde | 2904 | reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); |
e8adfc30 | 2905 | reg |= DWC3_GEVNTSIZ_INTMASK; |
660e9bde | 2906 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); |
e8adfc30 | 2907 | |
b15a762f | 2908 | return IRQ_WAKE_THREAD; |
72246da4 FB |
2909 | } |
2910 | ||
dea520a4 | 2911 | static irqreturn_t dwc3_interrupt(int irq, void *_evt) |
72246da4 | 2912 | { |
dea520a4 | 2913 | struct dwc3_event_buffer *evt = _evt; |
72246da4 | 2914 | |
dea520a4 | 2915 | return dwc3_check_event_buf(evt); |
72246da4 FB |
2916 | } |
2917 | ||
6db3812e FB |
2918 | static int dwc3_gadget_get_irq(struct dwc3 *dwc) |
2919 | { | |
2920 | struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); | |
2921 | int irq; | |
2922 | ||
2923 | irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); | |
2924 | if (irq > 0) | |
2925 | goto out; | |
2926 | ||
2927 | if (irq == -EPROBE_DEFER) | |
2928 | goto out; | |
2929 | ||
2930 | irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); | |
2931 | if (irq > 0) | |
2932 | goto out; | |
2933 | ||
2934 | if (irq == -EPROBE_DEFER) | |
2935 | goto out; | |
2936 | ||
2937 | irq = platform_get_irq(dwc3_pdev, 0); | |
2938 | if (irq > 0) | |
2939 | goto out; | |
2940 | ||
2941 | if (irq != -EPROBE_DEFER) | |
2942 | dev_err(dwc->dev, "missing peripheral IRQ\n"); | |
2943 | ||
2944 | if (!irq) | |
2945 | irq = -EINVAL; | |
2946 | ||
2947 | out: | |
2948 | return irq; | |
2949 | } | |
2950 | ||
72246da4 FB |
2951 | /** |
2952 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2953 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2954 | * |
2955 | * Returns 0 on success otherwise negative errno. | |
2956 | */ | |
41ac7b3a | 2957 | int dwc3_gadget_init(struct dwc3 *dwc) |
72246da4 | 2958 | { |
6db3812e FB |
2959 | int ret; |
2960 | int irq; | |
9522def4 | 2961 | |
6db3812e FB |
2962 | irq = dwc3_gadget_get_irq(dwc); |
2963 | if (irq < 0) { | |
2964 | ret = irq; | |
2965 | goto err0; | |
9522def4 RQ |
2966 | } |
2967 | ||
2968 | dwc->irq_gadget = irq; | |
72246da4 FB |
2969 | |
2970 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2971 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2972 | if (!dwc->ctrl_req) { | |
2973 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2974 | ret = -ENOMEM; | |
2975 | goto err0; | |
2976 | } | |
2977 | ||
2abd9d5f | 2978 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
2979 | &dwc->ep0_trb_addr, GFP_KERNEL); |
2980 | if (!dwc->ep0_trb) { | |
2981 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2982 | ret = -ENOMEM; | |
2983 | goto err1; | |
2984 | } | |
2985 | ||
3ef35faf | 2986 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 | 2987 | if (!dwc->setup_buf) { |
72246da4 FB |
2988 | ret = -ENOMEM; |
2989 | goto err2; | |
2990 | } | |
2991 | ||
5812b1c2 | 2992 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2993 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2994 | GFP_KERNEL); | |
5812b1c2 FB |
2995 | if (!dwc->ep0_bounce) { |
2996 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2997 | ret = -ENOMEM; | |
2998 | goto err3; | |
2999 | } | |
3000 | ||
04c03d10 FB |
3001 | dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL); |
3002 | if (!dwc->zlp_buf) { | |
3003 | ret = -ENOMEM; | |
3004 | goto err4; | |
3005 | } | |
3006 | ||
bb014736 BW |
3007 | init_completion(&dwc->ep0_in_setup); |
3008 | ||
72246da4 | 3009 | dwc->gadget.ops = &dwc3_gadget_ops; |
72246da4 | 3010 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
eeb720fb | 3011 | dwc->gadget.sg_supported = true; |
72246da4 | 3012 | dwc->gadget.name = "dwc3-gadget"; |
6a4290cc | 3013 | dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; |
72246da4 | 3014 | |
b9e51b2b BM |
3015 | /* |
3016 | * FIXME We might be setting max_speed to <SUPER, however versions | |
3017 | * <2.20a of dwc3 have an issue with metastability (documented | |
3018 | * elsewhere in this driver) which tells us we can't set max speed to | |
3019 | * anything lower than SUPER. | |
3020 | * | |
3021 | * Because gadget.max_speed is only used by composite.c and function | |
3022 | * drivers (i.e. it won't go into dwc3's registers) we are allowing this | |
3023 | * to happen so we avoid sending SuperSpeed Capability descriptor | |
3024 | * together with our BOS descriptor as that could confuse host into | |
3025 | * thinking we can handle super speed. | |
3026 | * | |
3027 | * Note that, in fact, we won't even support GetBOS requests when speed | |
3028 | * is less than super speed because we don't have means, yet, to tell | |
3029 | * composite.c that we are USB 2.0 + LPM ECN. | |
3030 | */ | |
3031 | if (dwc->revision < DWC3_REVISION_220A) | |
5eb30ced | 3032 | dev_info(dwc->dev, "changing max_speed on rev %08x\n", |
b9e51b2b BM |
3033 | dwc->revision); |
3034 | ||
3035 | dwc->gadget.max_speed = dwc->maximum_speed; | |
3036 | ||
a4b9d94b DC |
3037 | /* |
3038 | * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize | |
3039 | * on ep out. | |
3040 | */ | |
3041 | dwc->gadget.quirk_ep_out_aligned_size = true; | |
3042 | ||
72246da4 FB |
3043 | /* |
3044 | * REVISIT: Here we should clear all pending IRQs to be | |
3045 | * sure we're starting from a well known location. | |
3046 | */ | |
3047 | ||
3048 | ret = dwc3_gadget_init_endpoints(dwc); | |
3049 | if (ret) | |
04c03d10 | 3050 | goto err5; |
72246da4 | 3051 | |
72246da4 FB |
3052 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); |
3053 | if (ret) { | |
3054 | dev_err(dwc->dev, "failed to register udc\n"); | |
04c03d10 | 3055 | goto err5; |
72246da4 FB |
3056 | } |
3057 | ||
3058 | return 0; | |
3059 | ||
04c03d10 FB |
3060 | err5: |
3061 | kfree(dwc->zlp_buf); | |
3062 | ||
5812b1c2 | 3063 | err4: |
e1f80467 | 3064 | dwc3_gadget_free_endpoints(dwc); |
3ef35faf FB |
3065 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
3066 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 3067 | |
72246da4 | 3068 | err3: |
0fc9a1be | 3069 | kfree(dwc->setup_buf); |
72246da4 FB |
3070 | |
3071 | err2: | |
51fbc7c0 | 3072 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3073 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3074 | ||
3075 | err1: | |
3076 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
3077 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
3078 | ||
3079 | err0: | |
3080 | return ret; | |
3081 | } | |
3082 | ||
7415f17c FB |
3083 | /* -------------------------------------------------------------------------- */ |
3084 | ||
72246da4 FB |
3085 | void dwc3_gadget_exit(struct dwc3 *dwc) |
3086 | { | |
72246da4 | 3087 | usb_del_gadget_udc(&dwc->gadget); |
72246da4 | 3088 | |
72246da4 FB |
3089 | dwc3_gadget_free_endpoints(dwc); |
3090 | ||
3ef35faf FB |
3091 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
3092 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 3093 | |
0fc9a1be | 3094 | kfree(dwc->setup_buf); |
04c03d10 | 3095 | kfree(dwc->zlp_buf); |
72246da4 | 3096 | |
51fbc7c0 | 3097 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2, |
72246da4 FB |
3098 | dwc->ep0_trb, dwc->ep0_trb_addr); |
3099 | ||
3100 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
3101 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
72246da4 | 3102 | } |
7415f17c | 3103 | |
0b0231aa | 3104 | int dwc3_gadget_suspend(struct dwc3 *dwc) |
7415f17c | 3105 | { |
9f8a67b6 FB |
3106 | int ret; |
3107 | ||
9772b47a RQ |
3108 | if (!dwc->gadget_driver) |
3109 | return 0; | |
3110 | ||
9f8a67b6 FB |
3111 | ret = dwc3_gadget_run_stop(dwc, false, false); |
3112 | if (ret < 0) | |
3113 | return ret; | |
7415f17c | 3114 | |
9f8a67b6 FB |
3115 | dwc3_disconnect_gadget(dwc); |
3116 | __dwc3_gadget_stop(dwc); | |
7415f17c FB |
3117 | |
3118 | return 0; | |
3119 | } | |
3120 | ||
3121 | int dwc3_gadget_resume(struct dwc3 *dwc) | |
3122 | { | |
7415f17c FB |
3123 | int ret; |
3124 | ||
9772b47a RQ |
3125 | if (!dwc->gadget_driver) |
3126 | return 0; | |
3127 | ||
9f8a67b6 FB |
3128 | ret = __dwc3_gadget_start(dwc); |
3129 | if (ret < 0) | |
7415f17c FB |
3130 | goto err0; |
3131 | ||
9f8a67b6 FB |
3132 | ret = dwc3_gadget_run_stop(dwc, true, false); |
3133 | if (ret < 0) | |
7415f17c FB |
3134 | goto err1; |
3135 | ||
7415f17c FB |
3136 | return 0; |
3137 | ||
3138 | err1: | |
9f8a67b6 | 3139 | __dwc3_gadget_stop(dwc); |
7415f17c FB |
3140 | |
3141 | err0: | |
3142 | return ret; | |
3143 | } | |
fc8bb91b FB |
3144 | |
3145 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc) | |
3146 | { | |
3147 | if (dwc->pending_events) { | |
3148 | dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); | |
3149 | dwc->pending_events = false; | |
3150 | enable_irq(dwc->irq_gadget); | |
3151 | } | |
3152 | } |