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[mirror_ubuntu-jammy-kernel.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
4199c5f8
FB		 183 usb_gadget_unmap_request_by_dev(dwc->sysdev,
184 &req->request, req->direction);
72246da4 185
2c4cbe6e 186 trace_dwc3_gadget_giveback(req);
72246da4
FB		 187
188 spin_unlock(&dwc->lock);
304f7e5e 189 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 190 spin_lock(&dwc->lock);
fc8bb91b
FB		 191
192 if (dep->number > 1)
193 pm_runtime_put(dwc->dev);
72246da4
FB		 194}
195
3ece0ec4 196int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 197{
198 u32 timeout = 500;
71f7e702 199 int status = 0;
0fe886cd 200 int ret = 0;
b09bb642
FB		 201 u32 reg;
202
203 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
204 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
205
206 do {
207 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
208 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 209 status = DWC3_DGCMD_STATUS(reg);
210 if (status)
0fe886cd
FB		 211 ret = -EINVAL;
212 break;
b09bb642 213 }
e3aee486 214 } while (--timeout);
0fe886cd
FB		 215
216 if (!timeout) {
0fe886cd 217 ret = -ETIMEDOUT;
71f7e702 218 status = -ETIMEDOUT;
0fe886cd
FB		 219 }
220
71f7e702
FB		 221 trace_dwc3_gadget_generic_cmd(cmd, param, status);
222
0fe886cd 223 return ret;
b09bb642
FB		 224}
225
c36d8e94
FB		 226static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
227
2cd4718d
FB		 228int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
229 struct dwc3_gadget_ep_cmd_params *params)
72246da4 230{
8897a761 231 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 232 struct dwc3 *dwc = dep->dwc;
61d58242 233 u32 timeout = 500;
72246da4
FB		 234 u32 reg;
235
0933df15 236 int cmd_status = 0;
2b0f11df 237 int susphy = false;
c0ca324d 238 int ret = -EINVAL;
72246da4 239
2b0f11df
FB		 240 /*
241 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
242 * we're issuing an endpoint command, we must check if
243 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
244 *
245 * We will also set SUSPHY bit to what it was before returning as stated
246 * by the same section on Synopsys databook.
247 */
ab2a92e7
FB		 248 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
249 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
250 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
251 susphy = true;
252 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
253 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
254 }
2b0f11df
FB		 255 }
256
5999914f 257 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 258 int needs_wakeup;
259
260 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
261 dwc->link_state == DWC3_LINK_STATE_U2 ||
262 dwc->link_state == DWC3_LINK_STATE_U3);
263
264 if (unlikely(needs_wakeup)) {
265 ret = __dwc3_gadget_wakeup(dwc);
266 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
267 ret);
268 }
269 }
270
2eb88016
FB		 271 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
272 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
273 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 274
8897a761
FB		 275 /*
276 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
277 * not relying on XferNotReady, we can make use of a special "No
278 * Response Update Transfer" command where we should clear both CmdAct
279 * and CmdIOC bits.
280 *
281 * With this, we don't need to wait for command completion and can
282 * straight away issue further commands to the endpoint.
283 *
284 * NOTICE: We're making an assumption that control endpoints will never
285 * make use of Update Transfer command. This is a safe assumption
286 * because we can never have more than one request at a time with
287 * Control Endpoints. If anybody changes that assumption, this chunk
288 * needs to be updated accordingly.
289 */
290 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
291 !usb_endpoint_xfer_isoc(desc))
292 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
293 else
294 cmd |= DWC3_DEPCMD_CMDACT;
295
296 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 297 do {
2eb88016 298 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 299 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 300 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 301
7b9cc7a2
KL		 302 switch (cmd_status) {
303 case 0:
304 ret = 0;
305 break;
306 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 307 ret = -EINVAL;
c0ca324d 308 break;
7b9cc7a2
KL		 309 case DEPEVT_TRANSFER_BUS_EXPIRY:
310 /*
311 * SW issues START TRANSFER command to
312 * isochronous ep with future frame interval. If
313 * future interval time has already passed when
314 * core receives the command, it will respond
315 * with an error status of 'Bus Expiry'.
316 *
317 * Instead of always returning -EINVAL, let's
318 * give a hint to the gadget driver that this is
319 * the case by returning -EAGAIN.
320 */
7b9cc7a2
KL		 321 ret = -EAGAIN;
322 break;
323 default:
324 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
325 }
326
c0ca324d 327 break;
72246da4 328 }
f6bb225b 329 } while (--timeout);
72246da4 330
f6bb225b 331 if (timeout == 0) {
f6bb225b 332 ret = -ETIMEDOUT;
0933df15 333 cmd_status = -ETIMEDOUT;
f6bb225b 334 }
c0ca324d 335
0933df15
FB		 336 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
337
6cb2e4e3
FB		 338 if (ret == 0) {
339 switch (DWC3_DEPCMD_CMD(cmd)) {
340 case DWC3_DEPCMD_STARTTRANSFER:
341 dep->flags |= DWC3_EP_TRANSFER_STARTED;
342 break;
343 case DWC3_DEPCMD_ENDTRANSFER:
344 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
345 break;
346 default:
347 /* nothing */
348 break;
349 }
350 }
351
2b0f11df
FB		 352 if (unlikely(susphy)) {
353 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
354 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
355 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
356 }
357
c0ca324d 358 return ret;
72246da4
FB		 359}
360
50c763f8
JY		 361static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
362{
363 struct dwc3 *dwc = dep->dwc;
364 struct dwc3_gadget_ep_cmd_params params;
365 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
366
367 /*
368 * As of core revision 2.60a the recommended programming model
369 * is to set the ClearPendIN bit when issuing a Clear Stall EP
370 * command for IN endpoints. This is to prevent an issue where
371 * some (non-compliant) hosts may not send ACK TPs for pending
372 * IN transfers due to a mishandled error condition. Synopsys
373 * STAR 9000614252.
374 */
5e6c88d2
LB		 375 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
376 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 377 cmd |= DWC3_DEPCMD_CLEARPENDIN;
378
379 memset(&params, 0, sizeof(params));
380
2cd4718d 381 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 382}
383
72246da4 384static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 385 struct dwc3_trb *trb)
72246da4 386{
c439ef87 387 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 388
389 return dep->trb_pool_dma + offset;
390}
391
392static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
393{
394 struct dwc3 *dwc = dep->dwc;
395
396 if (dep->trb_pool)
397 return 0;
398
d64ff406 399 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 400 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
401 &dep->trb_pool_dma, GFP_KERNEL);
402 if (!dep->trb_pool) {
403 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
404 dep->name);
405 return -ENOMEM;
406 }
407
408 return 0;
409}
410
411static void dwc3_free_trb_pool(struct dwc3_ep *dep)
412{
413 struct dwc3 *dwc = dep->dwc;
414
d64ff406 415 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 416 dep->trb_pool, dep->trb_pool_dma);
417
418 dep->trb_pool = NULL;
419 dep->trb_pool_dma = 0;
420}
421
c4509601
JY		 422static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
423
424/**
425 * dwc3_gadget_start_config - Configure EP resources
426 * @dwc: pointer to our controller context structure
427 * @dep: endpoint that is being enabled
428 *
429 * The assignment of transfer resources cannot perfectly follow the
430 * data book due to the fact that the controller driver does not have
431 * all knowledge of the configuration in advance. It is given this
432 * information piecemeal by the composite gadget framework after every
433 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
434 * programming model in this scenario can cause errors. For two
435 * reasons:
436 *
437 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
438 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
439 * multiple interfaces.
440 *
441 * 2) The databook does not mention doing more DEPXFERCFG for new
442 * endpoint on alt setting (8.1.6).
443 *
444 * The following simplified method is used instead:
445 *
446 * All hardware endpoints can be assigned a transfer resource and this
447 * setting will stay persistent until either a core reset or
448 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
449 * do DEPXFERCFG for every hardware endpoint as well. We are
450 * guaranteed that there are as many transfer resources as endpoints.
451 *
452 * This function is called for each endpoint when it is being enabled
453 * but is triggered only when called for EP0-out, which always happens
454 * first, and which should only happen in one of the above conditions.
455 */
72246da4
FB		 456static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459 u32 cmd;
c4509601
JY		 460 int i;
461 int ret;
462
463 if (dep->number)
464 return 0;
72246da4
FB		 465
466 memset(&params, 0x00, sizeof(params));
c4509601 467 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 468
2cd4718d 469 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 470 if (ret)
471 return ret;
472
473 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
474 struct dwc3_ep *dep = dwc->eps[i];
72246da4 475
c4509601
JY		 476 if (!dep)
477 continue;
478
479 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
480 if (ret)
481 return ret;
72246da4
FB		 482 }
483
484 return 0;
485}
486
487static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 488 bool modify, bool restore)
72246da4 489{
39ebb05c
JY		 490 const struct usb_ss_ep_comp_descriptor *comp_desc;
491 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 492 struct dwc3_gadget_ep_cmd_params params;
493
21e64bf2
FB		 494 if (dev_WARN_ONCE(dwc->dev, modify && restore,
495 "Can't modify and restore\n"))
496 return -EINVAL;
497
39ebb05c
JY		 498 comp_desc = dep->endpoint.comp_desc;
499 desc = dep->endpoint.desc;
500
72246da4
FB		 501 memset(&params, 0x00, sizeof(params));
502
dc1c70a7 503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
505
506 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 507 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 508 u32 burst = dep->endpoint.maxburst;
676e3497 509 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 510 }
72246da4 511
21e64bf2
FB		 512 if (modify) {
513 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
514 } else if (restore) {
265b70a7
PZ		 515 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
516 params.param2 |= dep->saved_state;
21e64bf2
FB		 517 } else {
518 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 519 }
520
4bc48c97
FB		 521 if (usb_endpoint_xfer_control(desc))
522 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 523
524 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
525 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 526
18b7ede5 527 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 528 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
529 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 530 dep->stream_capable = true;
531 }
532
0b93a4c8 533 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 534 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 535
536 /*
537 * We are doing 1:1 mapping for endpoints, meaning
538 * Physical Endpoints 2 maps to Logical Endpoint 2 and
539 * so on. We consider the direction bit as part of the physical
540 * endpoint number. So USB endpoint 0x81 is 0x03.
541 */
dc1c70a7 542 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 543
544 /*
545 * We must use the lower 16 TX FIFOs even though
546 * HW might have more
547 */
548 if (dep->direction)
dc1c70a7 549 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 550
551 if (desc->bInterval) {
dc1c70a7 552 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 553 dep->interval = 1 << (desc->bInterval - 1);
554 }
555
2cd4718d 556 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 557}
558
559static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
560{
561 struct dwc3_gadget_ep_cmd_params params;
562
563 memset(&params, 0x00, sizeof(params));
564
dc1c70a7 565 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 566
2cd4718d
FB		 567 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
568 &params);
72246da4
FB		 569}
570
571/**
572 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
573 * @dep: endpoint to be initialized
574 * @desc: USB Endpoint Descriptor
575 *
576 * Caller should take care of locking
577 */
578static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 579 bool modify, bool restore)
72246da4 580{
39ebb05c 581 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 582 struct dwc3 *dwc = dep->dwc;
39ebb05c 583
72246da4 584 u32 reg;
b09e99ee 585 int ret;
72246da4
FB		 586
587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
589 if (ret)
590 return ret;
591 }
592
39ebb05c 593 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 594 if (ret)
595 return ret;
596
597 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 598 struct dwc3_trb *trb_st_hw;
599 struct dwc3_trb *trb_link;
72246da4 600
72246da4
FB		 601 dep->type = usb_endpoint_type(desc);
602 dep->flags |= DWC3_EP_ENABLED;
76a638f8 603 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 604
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg |= DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
608
76a638f8
BW		 609 init_waitqueue_head(&dep->wait_end_transfer);
610
36b68aae 611 if (usb_endpoint_xfer_control(desc))
2870e501 612 goto out;
72246da4 613
0d25744a
JY		 614 /* Initialize the TRB ring */
615 dep->trb_dequeue = 0;
616 dep->trb_enqueue = 0;
617 memset(dep->trb_pool, 0,
618 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
619
36b68aae 620 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 621 trb_st_hw = &dep->trb_pool[0];
622
f6bafc6a 623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 624 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
625 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
627 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 628 }
629
a97ea994
FB		 630 /*
631 * Issue StartTransfer here with no-op TRB so we can always rely on No
632 * Response Update Transfer command.
633 */
634 if (usb_endpoint_xfer_bulk(desc)) {
635 struct dwc3_gadget_ep_cmd_params params;
636 struct dwc3_trb *trb;
637 dma_addr_t trb_dma;
638 u32 cmd;
639
640 memset(&params, 0, sizeof(params));
641 trb = &dep->trb_pool[0];
642 trb_dma = dwc3_trb_dma_offset(dep, trb);
643
644 params.param0 = upper_32_bits(trb_dma);
645 params.param1 = lower_32_bits(trb_dma);
646
647 cmd = DWC3_DEPCMD_STARTTRANSFER;
648
649 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
650 if (ret < 0)
651 return ret;
652
653 dep->flags |= DWC3_EP_BUSY;
654
655 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
656 WARN_ON_ONCE(!dep->resource_index);
657 }
658
2870e501
FB		 659
660out:
661 trace_dwc3_gadget_ep_enable(dep);
662
72246da4
FB		 663 return 0;
664}
665
b992e681 666static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 667static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 668{
669 struct dwc3_request *req;
670
0e146028 671 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 672
0e146028
FB		 673 /* - giveback all requests to gadget driver */
674 while (!list_empty(&dep->started_list)) {
675 req = next_request(&dep->started_list);
1591633e 676
0e146028 677 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 678 }
679
aa3342c8
FB		 680 while (!list_empty(&dep->pending_list)) {
681 req = next_request(&dep->pending_list);
72246da4 682
624407f9 683 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 684 }
72246da4
FB		 685}
686
687/**
688 * __dwc3_gadget_ep_disable - Disables a HW endpoint
689 * @dep: the endpoint to disable
690 *
624407f9
SAS		 691 * This function also removes requests which are currently processed ny the
692 * hardware and those which are not yet scheduled.
693 * Caller should take care of locking.
72246da4 694 */
72246da4
FB		 695static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
696{
697 struct dwc3 *dwc = dep->dwc;
698 u32 reg;
699
2870e501 700 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 701
624407f9 702 dwc3_remove_requests(dwc, dep);
72246da4 703
687ef981
FB		 704 /* make sure HW endpoint isn't stalled */
705 if (dep->flags & DWC3_EP_STALL)
7a608559 706 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 707
72246da4
FB		 708 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
709 reg &= ~DWC3_DALEPENA_EP(dep->number);
710 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
711
879631aa 712 dep->stream_capable = false;
72246da4 713 dep->type = 0;
76a638f8 714 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 715
39ebb05c
JY		 716 /* Clear out the ep descriptors for non-ep0 */
717 if (dep->number > 1) {
718 dep->endpoint.comp_desc = NULL;
719 dep->endpoint.desc = NULL;
720 }
721
72246da4
FB		 722 return 0;
723}
724
725/* -------------------------------------------------------------------------- */
726
727static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
728 const struct usb_endpoint_descriptor *desc)
729{
730 return -EINVAL;
731}
732
733static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
734{
735 return -EINVAL;
736}
737
738/* -------------------------------------------------------------------------- */
739
740static int dwc3_gadget_ep_enable(struct usb_ep *ep,
741 const struct usb_endpoint_descriptor *desc)
742{
743 struct dwc3_ep *dep;
744 struct dwc3 *dwc;
745 unsigned long flags;
746 int ret;
747
748 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
749 pr_debug("dwc3: invalid parameters\n");
750 return -EINVAL;
751 }
752
753 if (!desc->wMaxPacketSize) {
754 pr_debug("dwc3: missing wMaxPacketSize\n");
755 return -EINVAL;
756 }
757
758 dep = to_dwc3_ep(ep);
759 dwc = dep->dwc;
760
95ca961c
FB		 761 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
762 "%s is already enabled\n",
763 dep->name))
c6f83f38 764 return 0;
c6f83f38 765
72246da4 766 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 767 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 768 spin_unlock_irqrestore(&dwc->lock, flags);
769
770 return ret;
771}
772
773static int dwc3_gadget_ep_disable(struct usb_ep *ep)
774{
775 struct dwc3_ep *dep;
776 struct dwc3 *dwc;
777 unsigned long flags;
778 int ret;
779
780 if (!ep) {
781 pr_debug("dwc3: invalid parameters\n");
782 return -EINVAL;
783 }
784
785 dep = to_dwc3_ep(ep);
786 dwc = dep->dwc;
787
95ca961c
FB		 788 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
789 "%s is already disabled\n",
790 dep->name))
72246da4 791 return 0;
72246da4 792
72246da4
FB		 793 spin_lock_irqsave(&dwc->lock, flags);
794 ret = __dwc3_gadget_ep_disable(dep);
795 spin_unlock_irqrestore(&dwc->lock, flags);
796
797 return ret;
798}
799
800static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
801 gfp_t gfp_flags)
802{
803 struct dwc3_request *req;
804 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 805
806 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 807 if (!req)
72246da4 808 return NULL;
72246da4
FB		 809
810 req->epnum = dep->number;
811 req->dep = dep;
72246da4 812
68d34c8a
FB		 813 dep->allocated_requests++;
814
2c4cbe6e
FB		 815 trace_dwc3_alloc_request(req);
816
72246da4
FB		 817 return &req->request;
818}
819
820static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
821 struct usb_request *request)
822{
823 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 824 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 825
68d34c8a 826 dep->allocated_requests--;
2c4cbe6e 827 trace_dwc3_free_request(req);
72246da4
FB		 828 kfree(req);
829}
830
2c78c029
FB		 831static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
832
e49d3cf4
FB		 833static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
834 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
835 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 836{
6b9018d4
FB		 837 struct dwc3 *dwc = dep->dwc;
838 struct usb_gadget *gadget = &dwc->gadget;
839 enum usb_device_speed speed = gadget->speed;
c71fc37c 840
ef966b9d 841 dwc3_ep_inc_enq(dep);
e5ba5ec8 842
f6bafc6a
FB		 843 trb->size = DWC3_TRB_SIZE_LENGTH(length);
844 trb->bpl = lower_32_bits(dma);
845 trb->bph = upper_32_bits(dma);
c71fc37c 846
16e78db7 847 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 848 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 849 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 850 break;
851
852 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 853 if (!node) {
e5ba5ec8 854 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 855
856 if (speed == USB_SPEED_HIGH) {
857 struct usb_ep *ep = &dep->endpoint;
858 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
859 }
860 } else {
e5ba5ec8 861 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 862 }
ca4d44ea
FB		 863
864 /* always enable Interrupt on Missed ISOC */
865 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 866 break;
867
868 case USB_ENDPOINT_XFER_BULK:
869 case USB_ENDPOINT_XFER_INT:
f6bafc6a 870 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 871 break;
872 default:
873 /*
874 * This is only possible with faulty memory because we
875 * checked it already :)
876 */
0a695d4c
FB		 877 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
878 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 879 }
880
ca4d44ea 881 /* always enable Continue on Short Packet */
c9508c8c 882 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 883 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 884
e49d3cf4 885 if (short_not_ok)
c9508c8c
FB		 886 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
887 }
888
e49d3cf4 889 if ((!no_interrupt && !chain) ||
2c78c029 890 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 891 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 892
e5ba5ec8
PA		 893 if (chain)
894 trb->ctrl |= DWC3_TRB_CTRL_CHN;
895
16e78db7 896 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 897 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 898
f6bafc6a 899 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 900
901 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 902}
903
e49d3cf4
FB		 904/**
905 * dwc3_prepare_one_trb - setup one TRB from one request
906 * @dep: endpoint for which this request is prepared
907 * @req: dwc3_request pointer
908 * @chain: should this TRB be chained to the next?
909 * @node: only for isochronous endpoints. First TRB needs different type.
910 */
911static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
912 struct dwc3_request *req, unsigned chain, unsigned node)
913{
914 struct dwc3_trb *trb;
915 unsigned length = req->request.length;
916 unsigned stream_id = req->request.stream_id;
917 unsigned short_not_ok = req->request.short_not_ok;
918 unsigned no_interrupt = req->request.no_interrupt;
919 dma_addr_t dma = req->request.dma;
920
921 trb = &dep->trb_pool[dep->trb_enqueue];
922
923 if (!req->trb) {
924 dwc3_gadget_move_started_request(req);
925 req->trb = trb;
926 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
927 dep->queued_requests++;
928 }
929
930 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
931 stream_id, short_not_ok, no_interrupt);
932}
933
361572b5
JY		 934/**
935 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
936 * @dep: The endpoint with the TRB ring
937 * @index: The index of the current TRB in the ring
938 *
939 * Returns the TRB prior to the one pointed to by the index. If the
940 * index is 0, we will wrap backwards, skip the link TRB, and return
941 * the one just before that.
942 */
943static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
944{
45438a0c 945 u8 tmp = index;
361572b5 946
45438a0c
FB		 947 if (!tmp)
948 tmp = DWC3_TRB_NUM - 1;
361572b5 949
45438a0c 950 return &dep->trb_pool[tmp - 1];
361572b5
JY		 951}
952
c4233573
FB		 953static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
954{
955 struct dwc3_trb *tmp;
f2694a93 956 struct dwc3 *dwc = dep->dwc;
32db3d94 957 u8 trbs_left;
c4233573
FB		 958
959 /*
960 * If enqueue & dequeue are equal than it is either full or empty.
961 *
962 * One way to know for sure is if the TRB right before us has HWO bit
963 * set or not. If it has, then we're definitely full and can't fit any
964 * more transfers in our ring.
965 */
966 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 967 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 968 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
969 "%s No TRBS left\n", dep->name))
361572b5 970 return 0;
c4233573
FB		 971
972 return DWC3_TRB_NUM - 1;
973 }
974
9d7aba77 975 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 976 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 977
9d7aba77
JY		 978 if (dep->trb_dequeue < dep->trb_enqueue)
979 trbs_left--;
980
32db3d94 981 return trbs_left;
c4233573
FB		 982}
983
5ee85d89 984static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 985 struct dwc3_request *req)
5ee85d89 986{
1f512119 987 struct scatterlist *sg = req->sg;
5ee85d89 988 struct scatterlist *s;
5ee85d89
FB		 989 int i;
990
1f512119 991 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 992 unsigned int length = req->request.length;
993 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
994 unsigned int rem = length % maxp;
5ee85d89
FB		 995 unsigned chain = true;
996
4bc48c97 997 if (sg_is_last(s))
5ee85d89
FB		 998 chain = false;
999
c6267a51
FB		 1000 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1001 struct dwc3 *dwc = dep->dwc;
1002 struct dwc3_trb *trb;
1003
1004 req->unaligned = true;
1005
1006 /* prepare normal TRB */
1007 dwc3_prepare_one_trb(dep, req, true, i);
1008
1009 /* Now prepare one extra TRB to align transfer size */
1010 trb = &dep->trb_pool[dep->trb_enqueue];
1011 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1012 maxp - rem, false, 0,
1013 req->request.stream_id,
1014 req->request.short_not_ok,
1015 req->request.no_interrupt);
1016 } else {
1017 dwc3_prepare_one_trb(dep, req, chain, i);
1018 }
5ee85d89 1019
7ae7df49 1020 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1021 break;
1022 }
1023}
1024
1025static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1026 struct dwc3_request *req)
5ee85d89 1027{
c6267a51
FB		 1028 unsigned int length = req->request.length;
1029 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1030 unsigned int rem = length % maxp;
1031
1032 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1033 struct dwc3 *dwc = dep->dwc;
1034 struct dwc3_trb *trb;
1035
1036 req->unaligned = true;
1037
1038 /* prepare normal TRB */
1039 dwc3_prepare_one_trb(dep, req, true, 0);
1040
1041 /* Now prepare one extra TRB to align transfer size */
1042 trb = &dep->trb_pool[dep->trb_enqueue];
1043 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1044 false, 0, req->request.stream_id,
1045 req->request.short_not_ok,
1046 req->request.no_interrupt);
d6e5a549
FB		 1047 } else if (req->request.zero && req->request.length &&
1048 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1049 struct dwc3 *dwc = dep->dwc;
1050 struct dwc3_trb *trb;
1051
1052 req->zero = true;
1053
1054 /* prepare normal TRB */
1055 dwc3_prepare_one_trb(dep, req, true, 0);
1056
1057 /* Now prepare one extra TRB to handle ZLP */
1058 trb = &dep->trb_pool[dep->trb_enqueue];
1059 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1060 false, 0, req->request.stream_id,
1061 req->request.short_not_ok,
1062 req->request.no_interrupt);
c6267a51
FB		 1063 } else {
1064 dwc3_prepare_one_trb(dep, req, false, 0);
1065 }
5ee85d89
FB		 1066}
1067
72246da4
FB		 1068/*
1069 * dwc3_prepare_trbs - setup TRBs from requests
1070 * @dep: endpoint for which requests are being prepared
72246da4 1071 *
1d046793
PZ		 1072 * The function goes through the requests list and sets up TRBs for the
1073 * transfers. The function returns once there are no more TRBs available or
1074 * it runs out of requests.
72246da4 1075 */
c4233573 1076static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1077{
68e823e2 1078 struct dwc3_request *req, *n;
72246da4
FB		 1079
1080 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1081
7ae7df49 1082 if (!dwc3_calc_trbs_left(dep))
89bc856e 1083 return;
72246da4 1084
d86c5a67
FB		 1085 /*
1086 * We can get in a situation where there's a request in the started list
1087 * but there weren't enough TRBs to fully kick it in the first time
1088 * around, so it has been waiting for more TRBs to be freed up.
1089 *
1090 * In that case, we should check if we have a request with pending_sgs
1091 * in the started list and prepare TRBs for that request first,
1092 * otherwise we will prepare TRBs completely out of order and that will
1093 * break things.
1094 */
1095 list_for_each_entry(req, &dep->started_list, list) {
1096 if (req->num_pending_sgs > 0)
1097 dwc3_prepare_one_trb_sg(dep, req);
1098
1099 if (!dwc3_calc_trbs_left(dep))
1100 return;
1101 }
1102
aa3342c8 1103 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1104 if (req->num_pending_sgs > 0)
7ae7df49 1105 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1106 else
7ae7df49 1107 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1108
7ae7df49 1109 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1110 return;
72246da4 1111 }
72246da4
FB		 1112}
1113
4fae2e3e 1114static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1115{
1116 struct dwc3_gadget_ep_cmd_params params;
1117 struct dwc3_request *req;
4fae2e3e 1118 int starting;
72246da4
FB		 1119 int ret;
1120 u32 cmd;
1121
4fae2e3e 1122 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1123
4fae2e3e
FB		 1124 dwc3_prepare_trbs(dep);
1125 req = next_request(&dep->started_list);
72246da4
FB		 1126 if (!req) {
1127 dep->flags |= DWC3_EP_PENDING_REQUEST;
1128 return 0;
1129 }
1130
1131 memset(&params, 0, sizeof(params));
72246da4 1132
4fae2e3e 1133 if (starting) {
1877d6c9
PA		 1134 params.param0 = upper_32_bits(req->trb_dma);
1135 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1136 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1138 } else {
b6b1c6db
FB		 1139 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1141 }
72246da4 1142
2cd4718d 1143 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1144 if (ret < 0) {
72246da4
FB		 1145 /*
1146 * FIXME we need to iterate over the list of requests
1147 * here and stop, unmap, free and del each of the linked
1d046793 1148 * requests instead of what we do now.
72246da4 1149 */
ce3fc8b3
JD		 1150 if (req->trb)
1151 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1152 dep->queued_requests--;
15b8d933 1153 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1154 return ret;
1155 }
1156
1157 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1158
4fae2e3e 1159 if (starting) {
2eb88016 1160 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1161 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1162 }
25b8ff68 1163
72246da4
FB		 1164 return 0;
1165}
1166
6cb2e4e3
FB		 1167static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1168{
1169 u32 reg;
1170
1171 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172 return DWC3_DSTS_SOFFN(reg);
1173}
1174
d6d6ec7b
PA		 1175static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176 struct dwc3_ep *dep, u32 cur_uf)
1177{
1178 u32 uf;
1179
aa3342c8 1180 if (list_empty(&dep->pending_list)) {
5eb30ced 1181 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1182 dep->name);
f4a53c55 1183 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1184 return;
1185 }
1186
af771d73
JY		 1187 /*
1188 * Schedule the first trb for one interval in the future or at
1189 * least 4 microframes.
1190 */
1191 uf = cur_uf + max_t(u32, 4, dep->interval);
d6d6ec7b 1192
4fae2e3e 1193 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1194}
1195
1196static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1197 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1198{
1199 u32 cur_uf, mask;
1200
1201 mask = ~(dep->interval - 1);
1202 cur_uf = event->parameters & mask;
1203
1204 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1205}
1206
72246da4
FB		 1207static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1208{
0fc9a1be
FB		 1209 struct dwc3 *dwc = dep->dwc;
1210 int ret;
1211
bb423984 1212 if (!dep->endpoint.desc) {
5eb30ced
FB		 1213 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1214 dep->name);
bb423984
FB		 1215 return -ESHUTDOWN;
1216 }
1217
1218 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1219 &req->request, req->dep->name)) {
5eb30ced
FB		 1220 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1221 dep->name, &req->request, req->dep->name);
bb423984
FB		 1222 return -EINVAL;
1223 }
1224
fc8bb91b
FB		 1225 pm_runtime_get(dwc->dev);
1226
72246da4
FB		 1227 req->request.actual = 0;
1228 req->request.status = -EINPROGRESS;
1229 req->direction = dep->direction;
1230 req->epnum = dep->number;
1231
fe84f522
FB		 1232 trace_dwc3_ep_queue(req);
1233
d64ff406
AB		 1234 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1235 dep->direction);
0fc9a1be
FB		 1236 if (ret)
1237 return ret;
1238
1f512119
FB		 1239 req->sg = req->request.sg;
1240 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1241
aa3342c8 1242 list_add_tail(&req->list, &dep->pending_list);
72246da4 1243
d889c23c
FB		 1244 /*
1245 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1246 * wait for a XferNotReady event so we will know what's the current
1247 * (micro-)frame number.
1248 *
1249 * Without this trick, we are very, very likely gonna get Bus Expiry
1250 * errors which will force us issue EndTransfer command.
1251 */
1252 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1253 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1254 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1255 dwc3_stop_active_transfer(dwc, dep->number, true);
1256 dep->flags = DWC3_EP_ENABLED;
1257 } else {
1258 u32 cur_uf;
1259
1260 cur_uf = __dwc3_gadget_get_frame(dwc);
1261 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1262 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1263 }
f1d6826c 1264 return 0;
08a36b54 1265 }
f1d6826c
RQ		 1266
1267 if ((dep->flags & DWC3_EP_BUSY) &&
1268 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1269 WARN_ON_ONCE(!dep->resource_index);
1270 ret = __dwc3_gadget_kick_transfer(dep,
1271 dep->resource_index);
1272 }
1273
1274 goto out;
a0925324 1275 }
72246da4 1276
594e121f
FB		 1277 if (!dwc3_calc_trbs_left(dep))
1278 return 0;
b997ada5 1279
08a36b54 1280 ret = __dwc3_gadget_kick_transfer(dep, 0);
f1d6826c 1281out:
a8f32817
FB		 1282 if (ret == -EBUSY)
1283 ret = 0;
1284
1285 return ret;
72246da4
FB		 1286}
1287
1288static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1289 gfp_t gfp_flags)
1290{
1291 struct dwc3_request *req = to_dwc3_request(request);
1292 struct dwc3_ep *dep = to_dwc3_ep(ep);
1293 struct dwc3 *dwc = dep->dwc;
1294
1295 unsigned long flags;
1296
1297 int ret;
1298
fdee4eba 1299 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1300 ret = __dwc3_gadget_ep_queue(dep, req);
1301 spin_unlock_irqrestore(&dwc->lock, flags);
1302
1303 return ret;
1304}
1305
1306static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1307 struct usb_request *request)
1308{
1309 struct dwc3_request *req = to_dwc3_request(request);
1310 struct dwc3_request *r = NULL;
1311
1312 struct dwc3_ep *dep = to_dwc3_ep(ep);
1313 struct dwc3 *dwc = dep->dwc;
1314
1315 unsigned long flags;
1316 int ret = 0;
1317
2c4cbe6e
FB		 1318 trace_dwc3_ep_dequeue(req);
1319
72246da4
FB		 1320 spin_lock_irqsave(&dwc->lock, flags);
1321
aa3342c8 1322 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1323 if (r == req)
1324 break;
1325 }
1326
1327 if (r != req) {
aa3342c8 1328 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1329 if (r == req)
1330 break;
1331 }
1332 if (r == req) {
1333 /* wait until it is processed */
b992e681 1334 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1335
1336 /*
1337 * If request was already started, this means we had to
1338 * stop the transfer. With that we also need to ignore
1339 * all TRBs used by the request, however TRBs can only
1340 * be modified after completion of END_TRANSFER
1341 * command. So what we do here is that we wait for
1342 * END_TRANSFER completion and only after that, we jump
1343 * over TRBs by clearing HWO and incrementing dequeue
1344 * pointer.
1345 *
1346 * Note that we have 2 possible types of transfers here:
1347 *
1348 * i) Linear buffer request
1349 * ii) SG-list based request
1350 *
1351 * SG-list based requests will have r->num_pending_sgs
1352 * set to a valid number (> 0). Linear requests,
1353 * normally use a single TRB.
1354 *
1355 * For each of these two cases, if r->unaligned flag is
1356 * set, one extra TRB has been used to align transfer
1357 * size to wMaxPacketSize.
1358 *
1359 * All of these cases need to be taken into
1360 * consideration so we don't mess up our TRB ring
1361 * pointers.
1362 */
1363 wait_event_lock_irq(dep->wait_end_transfer,
1364 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1365 dwc->lock);
1366
1367 if (!r->trb)
1368 goto out1;
1369
1370 if (r->num_pending_sgs) {
1371 struct dwc3_trb *trb;
1372 int i = 0;
1373
1374 for (i = 0; i < r->num_pending_sgs; i++) {
1375 trb = r->trb + i;
1376 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1377 dwc3_ep_inc_deq(dep);
1378 }
1379
d6e5a549 1380 if (r->unaligned || r->zero) {
cf3113d8
FB		 1381 trb = r->trb + r->num_pending_sgs + 1;
1382 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1383 dwc3_ep_inc_deq(dep);
1384 }
1385 } else {
1386 struct dwc3_trb *trb = r->trb;
1387
1388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1389 dwc3_ep_inc_deq(dep);
1390
d6e5a549 1391 if (r->unaligned || r->zero) {
cf3113d8
FB		 1392 trb = r->trb + 1;
1393 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1394 dwc3_ep_inc_deq(dep);
1395 }
1396 }
e8d4e8be 1397 goto out1;
72246da4
FB		 1398 }
1399 dev_err(dwc->dev, "request %p was not queued to %s\n",
1400 request, ep->name);
1401 ret = -EINVAL;
1402 goto out0;
1403 }
1404
e8d4e8be 1405out1:
72246da4 1406 /* giveback the request */
cf3113d8 1407 dep->queued_requests--;
72246da4
FB		 1408 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1409
1410out0:
1411 spin_unlock_irqrestore(&dwc->lock, flags);
1412
1413 return ret;
1414}
1415
7a608559 1416int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1417{
1418 struct dwc3_gadget_ep_cmd_params params;
1419 struct dwc3 *dwc = dep->dwc;
1420 int ret;
1421
5ad02fb8
FB		 1422 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1423 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1424 return -EINVAL;
1425 }
1426
72246da4
FB		 1427 memset(&params, 0x00, sizeof(params));
1428
1429 if (value) {
69450c4d
FB		 1430 struct dwc3_trb *trb;
1431
1432 unsigned transfer_in_flight;
1433 unsigned started;
1434
ffb80fc6
FB		 1435 if (dep->flags & DWC3_EP_STALL)
1436 return 0;
1437
69450c4d
FB		 1438 if (dep->number > 1)
1439 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1440 else
1441 trb = &dwc->ep0_trb[dep->trb_enqueue];
1442
1443 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1444 started = !list_empty(&dep->started_list);
1445
1446 if (!protocol && ((dep->direction && transfer_in_flight) ||
1447 (!dep->direction && started))) {
7a608559
FB		 1448 return -EAGAIN;
1449 }
1450
2cd4718d
FB		 1451 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1452 &params);
72246da4 1453 if (ret)
3f89204b 1454 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1455 dep->name);
1456 else
1457 dep->flags |= DWC3_EP_STALL;
1458 } else {
ffb80fc6
FB		 1459 if (!(dep->flags & DWC3_EP_STALL))
1460 return 0;
2cd4718d 1461
50c763f8 1462 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1463 if (ret)
3f89204b 1464 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1465 dep->name);
1466 else
a535d81c 1467 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1468 }
5275455a 1469
72246da4
FB		 1470 return ret;
1471}
1472
1473static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1474{
1475 struct dwc3_ep *dep = to_dwc3_ep(ep);
1476 struct dwc3 *dwc = dep->dwc;
1477
1478 unsigned long flags;
1479
1480 int ret;
1481
1482 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1483 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1484 spin_unlock_irqrestore(&dwc->lock, flags);
1485
1486 return ret;
1487}
1488
1489static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1490{
1491 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1492 struct dwc3 *dwc = dep->dwc;
1493 unsigned long flags;
95aa4e8d 1494 int ret;
72246da4 1495
249a4569 1496 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1497 dep->flags |= DWC3_EP_WEDGE;
1498
08f0d966 1499 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1500 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1501 else
7a608559 1502 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1503 spin_unlock_irqrestore(&dwc->lock, flags);
1504
1505 return ret;
72246da4
FB		 1506}
1507
1508/* -------------------------------------------------------------------------- */
1509
1510static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1511 .bLength = USB_DT_ENDPOINT_SIZE,
1512 .bDescriptorType = USB_DT_ENDPOINT,
1513 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1514};
1515
1516static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1517 .enable = dwc3_gadget_ep0_enable,
1518 .disable = dwc3_gadget_ep0_disable,
1519 .alloc_request = dwc3_gadget_ep_alloc_request,
1520 .free_request = dwc3_gadget_ep_free_request,
1521 .queue = dwc3_gadget_ep0_queue,
1522 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1523 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1524 .set_wedge = dwc3_gadget_ep_set_wedge,
1525};
1526
1527static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1528 .enable = dwc3_gadget_ep_enable,
1529 .disable = dwc3_gadget_ep_disable,
1530 .alloc_request = dwc3_gadget_ep_alloc_request,
1531 .free_request = dwc3_gadget_ep_free_request,
1532 .queue = dwc3_gadget_ep_queue,
1533 .dequeue = dwc3_gadget_ep_dequeue,
1534 .set_halt = dwc3_gadget_ep_set_halt,
1535 .set_wedge = dwc3_gadget_ep_set_wedge,
1536};
1537
1538/* -------------------------------------------------------------------------- */
1539
1540static int dwc3_gadget_get_frame(struct usb_gadget *g)
1541{
1542 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1543
6cb2e4e3 1544 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1545}
1546
218ef7b6 1547static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1548{
d6011f6f 1549 int retries;
72246da4 1550
218ef7b6 1551 int ret;
72246da4
FB		 1552 u32 reg;
1553
72246da4
FB		 1554 u8 link_state;
1555 u8 speed;
1556
72246da4
FB		 1557 /*
1558 * According to the Databook Remote wakeup request should
1559 * be issued only when the device is in early suspend state.
1560 *
1561 * We can check that via USB Link State bits in DSTS register.
1562 */
1563 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1564
1565 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1566 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1567 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1568 return 0;
72246da4
FB		 1569
1570 link_state = DWC3_DSTS_USBLNKST(reg);
1571
1572 switch (link_state) {
1573 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1574 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1575 break;
1576 default:
218ef7b6 1577 return -EINVAL;
72246da4
FB		 1578 }
1579
8598bde7
FB		 1580 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1581 if (ret < 0) {
1582 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1583 return ret;
8598bde7 1584 }
72246da4 1585
802fde98
PZ		 1586 /* Recent versions do this automatically */
1587 if (dwc->revision < DWC3_REVISION_194A) {
1588 /* write zeroes to Link Change Request */
fcc023c7 1589 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1590 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1591 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1592 }
72246da4 1593
1d046793 1594 /* poll until Link State changes to ON */
d6011f6f 1595 retries = 20000;
72246da4 1596
d6011f6f 1597 while (retries--) {
72246da4
FB		 1598 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1599
1600 /* in HS, means ON */
1601 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1602 break;
1603 }
1604
1605 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1606 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1607 return -EINVAL;
72246da4
FB		 1608 }
1609
218ef7b6
FB		 1610 return 0;
1611}
1612
1613static int dwc3_gadget_wakeup(struct usb_gadget *g)
1614{
1615 struct dwc3 *dwc = gadget_to_dwc(g);
1616 unsigned long flags;
1617 int ret;
1618
1619 spin_lock_irqsave(&dwc->lock, flags);
1620 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1621 spin_unlock_irqrestore(&dwc->lock, flags);
1622
1623 return ret;
1624}
1625
1626static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1627 int is_selfpowered)
1628{
1629 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1630 unsigned long flags;
72246da4 1631
249a4569 1632 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1633 g->is_selfpowered = !!is_selfpowered;
249a4569 1634 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1635
1636 return 0;
1637}
1638
7b2a0368 1639static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1640{
1641 u32 reg;
61d58242 1642 u32 timeout = 500;
72246da4 1643
fc8bb91b
FB		 1644 if (pm_runtime_suspended(dwc->dev))
1645 return 0;
1646
72246da4 1647 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1648 if (is_on) {
802fde98
PZ		 1649 if (dwc->revision <= DWC3_REVISION_187A) {
1650 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1651 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1652 }
1653
1654 if (dwc->revision >= DWC3_REVISION_194A)
1655 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1656 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1657
1658 if (dwc->has_hibernation)
1659 reg |= DWC3_DCTL_KEEP_CONNECT;
1660
9fcb3bd8 1661 dwc->pullups_connected = true;
8db7ed15 1662 } else {
72246da4 1663 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1664
1665 if (dwc->has_hibernation && !suspend)
1666 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1667
9fcb3bd8 1668 dwc->pullups_connected = false;
8db7ed15 1669 }
72246da4
FB		 1670
1671 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1672
1673 do {
1674 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1675 reg &= DWC3_DSTS_DEVCTRLHLT;
1676 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1677
1678 if (!timeout)
1679 return -ETIMEDOUT;
72246da4 1680
6f17f74b 1681 return 0;
72246da4
FB		 1682}
1683
1684static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1685{
1686 struct dwc3 *dwc = gadget_to_dwc(g);
1687 unsigned long flags;
6f17f74b 1688 int ret;
72246da4
FB		 1689
1690 is_on = !!is_on;
1691
bb014736
BW		 1692 /*
1693 * Per databook, when we want to stop the gadget, if a control transfer
1694 * is still in process, complete it and get the core into setup phase.
1695 */
1696 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1697 reinit_completion(&dwc->ep0_in_setup);
1698
1699 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1700 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1701 if (ret == 0) {
1702 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1703 return -ETIMEDOUT;
1704 }
1705 }
1706
72246da4 1707 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1708 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1709 spin_unlock_irqrestore(&dwc->lock, flags);
1710
6f17f74b 1711 return ret;
72246da4
FB		 1712}
1713
8698e2ac
FB		 1714static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1715{
1716 u32 reg;
1717
1718 /* Enable all but Start and End of Frame IRQs */
1719 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1720 DWC3_DEVTEN_EVNTOVERFLOWEN |
1721 DWC3_DEVTEN_CMDCMPLTEN |
1722 DWC3_DEVTEN_ERRTICERREN |
1723 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1724 DWC3_DEVTEN_CONNECTDONEEN |
1725 DWC3_DEVTEN_USBRSTEN |
1726 DWC3_DEVTEN_DISCONNEVTEN);
1727
799e9dc8
FB		 1728 if (dwc->revision < DWC3_REVISION_250A)
1729 reg |= DWC3_DEVTEN_ULSTCNGEN;
1730
8698e2ac
FB		 1731 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1732}
1733
1734static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1735{
1736 /* mask all interrupts */
1737 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1738}
1739
1740static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1741static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1742
4e99472b
FB		 1743/**
1744 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1745 * dwc: pointer to our context structure
1746 *
1747 * The following looks like complex but it's actually very simple. In order to
1748 * calculate the number of packets we can burst at once on OUT transfers, we're
1749 * gonna use RxFIFO size.
1750 *
1751 * To calculate RxFIFO size we need two numbers:
1752 * MDWIDTH = size, in bits, of the internal memory bus
1753 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1754 *
1755 * Given these two numbers, the formula is simple:
1756 *
1757 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1758 *
1759 * 24 bytes is for 3x SETUP packets
1760 * 16 bytes is a clock domain crossing tolerance
1761 *
1762 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1763 */
1764static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1765{
1766 u32 ram2_depth;
1767 u32 mdwidth;
1768 u32 nump;
1769 u32 reg;
1770
1771 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1772 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1773
1774 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1775 nump = min_t(u32, nump, 16);
1776
1777 /* update NumP */
1778 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1779 reg &= ~DWC3_DCFG_NUMP_MASK;
1780 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1781 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1782}
1783
d7be2952 1784static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1785{
72246da4 1786 struct dwc3_ep *dep;
72246da4
FB		 1787 int ret = 0;
1788 u32 reg;
1789
cf40b86b
JY		 1790 /*
1791 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1792 * the core supports IMOD, disable it.
1793 */
1794 if (dwc->imod_interval) {
1795 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1796 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1797 } else if (dwc3_has_imod(dwc)) {
1798 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1799 }
1800
72246da4
FB		 1801 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1802 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1803
1804 /**
1805 * WORKAROUND: DWC3 revision < 2.20a have an issue
1806 * which would cause metastability state on Run/Stop
1807 * bit if we try to force the IP to USB2-only mode.
1808 *
1809 * Because of that, we cannot configure the IP to any
1810 * speed other than the SuperSpeed
1811 *
1812 * Refers to:
1813 *
1814 * STAR#9000525659: Clock Domain Crossing on DCTL in
1815 * USB 2.0 Mode
1816 */
f7e846f0 1817 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1818 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1819 } else {
1820 switch (dwc->maximum_speed) {
1821 case USB_SPEED_LOW:
2da9ad76 1822 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1823 break;
1824 case USB_SPEED_FULL:
9418ee15 1825 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1826 break;
1827 case USB_SPEED_HIGH:
2da9ad76 1828 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1829 break;
7580862b 1830 case USB_SPEED_SUPER_PLUS:
2da9ad76 1831 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1832 break;
f7e846f0 1833 default:
77966eb8
JY		 1834 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1835 dwc->maximum_speed);
1836 /* fall through */
1837 case USB_SPEED_SUPER:
1838 reg |= DWC3_DCFG_SUPERSPEED;
1839 break;
f7e846f0
FB		 1840 }
1841 }
72246da4
FB		 1842 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1843
2a58f9c1
FB		 1844 /*
1845 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1846 * field instead of letting dwc3 itself calculate that automatically.
1847 *
1848 * This way, we maximize the chances that we'll be able to get several
1849 * bursts of data without going through any sort of endpoint throttling.
1850 */
1851 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1852 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1853 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1854
4e99472b
FB		 1855 dwc3_gadget_setup_nump(dwc);
1856
72246da4
FB		 1857 /* Start with SuperSpeed Default */
1858 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1859
1860 dep = dwc->eps[0];
39ebb05c 1861 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1862 if (ret) {
1863 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1864 goto err0;
72246da4
FB		 1865 }
1866
1867 dep = dwc->eps[1];
39ebb05c 1868 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1869 if (ret) {
1870 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1871 goto err1;
72246da4
FB		 1872 }
1873
1874 /* begin to receive SETUP packets */
c7fcdeb2 1875 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1876 dwc3_ep0_out_start(dwc);
1877
8698e2ac
FB		 1878 dwc3_gadget_enable_irq(dwc);
1879
72246da4
FB		 1880 return 0;
1881
b0d7ffd4 1882err1:
d7be2952 1883 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1884
1885err0:
72246da4
FB		 1886 return ret;
1887}
1888
d7be2952
FB		 1889static int dwc3_gadget_start(struct usb_gadget *g,
1890 struct usb_gadget_driver *driver)
72246da4
FB		 1891{
1892 struct dwc3 *dwc = gadget_to_dwc(g);
1893 unsigned long flags;
d7be2952 1894 int ret = 0;
8698e2ac 1895 int irq;
72246da4 1896
9522def4 1897 irq = dwc->irq_gadget;
d7be2952
FB		 1898 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1899 IRQF_SHARED, "dwc3", dwc->ev_buf);
1900 if (ret) {
1901 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1902 irq, ret);
1903 goto err0;
1904 }
1905
72246da4 1906 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1907 if (dwc->gadget_driver) {
1908 dev_err(dwc->dev, "%s is already bound to %s\n",
1909 dwc->gadget.name,
1910 dwc->gadget_driver->driver.name);
1911 ret = -EBUSY;
1912 goto err1;
1913 }
1914
1915 dwc->gadget_driver = driver;
1916
fc8bb91b
FB		 1917 if (pm_runtime_active(dwc->dev))
1918 __dwc3_gadget_start(dwc);
1919
d7be2952
FB		 1920 spin_unlock_irqrestore(&dwc->lock, flags);
1921
1922 return 0;
1923
1924err1:
1925 spin_unlock_irqrestore(&dwc->lock, flags);
1926 free_irq(irq, dwc);
1927
1928err0:
1929 return ret;
1930}
72246da4 1931
d7be2952
FB		 1932static void __dwc3_gadget_stop(struct dwc3 *dwc)
1933{
8698e2ac 1934 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1935 __dwc3_gadget_ep_disable(dwc->eps[0]);
1936 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1937}
72246da4 1938
d7be2952
FB		 1939static int dwc3_gadget_stop(struct usb_gadget *g)
1940{
1941 struct dwc3 *dwc = gadget_to_dwc(g);
1942 unsigned long flags;
76a638f8 1943 int epnum;
72246da4 1944
d7be2952 1945 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1946
1947 if (pm_runtime_suspended(dwc->dev))
1948 goto out;
1949
d7be2952 1950 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1951
1952 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1953 struct dwc3_ep *dep = dwc->eps[epnum];
1954
1955 if (!dep)
1956 continue;
1957
1958 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1959 continue;
1960
1961 wait_event_lock_irq(dep->wait_end_transfer,
1962 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1963 dwc->lock);
1964 }
1965
1966out:
d7be2952 1967 dwc->gadget_driver = NULL;
72246da4
FB		 1968 spin_unlock_irqrestore(&dwc->lock, flags);
1969
3f308d17 1970 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1971
72246da4
FB		 1972 return 0;
1973}
802fde98 1974
72246da4
FB		 1975static const struct usb_gadget_ops dwc3_gadget_ops = {
1976 .get_frame = dwc3_gadget_get_frame,
1977 .wakeup = dwc3_gadget_wakeup,
1978 .set_selfpowered = dwc3_gadget_set_selfpowered,
1979 .pullup = dwc3_gadget_pullup,
1980 .udc_start = dwc3_gadget_start,
1981 .udc_stop = dwc3_gadget_stop,
1982};
1983
1984/* -------------------------------------------------------------------------- */
1985
f3bcfc7e 1986static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
72246da4
FB		 1987{
1988 struct dwc3_ep *dep;
47d3946e 1989 u8 epnum;
72246da4 1990
f3bcfc7e
BD		 1991 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1992
47d3946e
BD		 1993 for (epnum = 0; epnum < num; epnum++) {
1994 bool direction = epnum & 1;
72246da4 1995
72246da4 1996 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1997 if (!dep)
72246da4 1998 return -ENOMEM;
72246da4
FB		 1999
2000 dep->dwc = dwc;
2001 dep->number = epnum;
47d3946e 2002 dep->direction = direction;
2eb88016 2003 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 2004 dwc->eps[epnum] = dep;
2005
2006 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
47d3946e 2007 direction ? "in" : "out");
6a1e3ef4 2008
72246da4 2009 dep->endpoint.name = dep->name;
39ebb05c
JY		 2010
2011 if (!(dep->number > 1)) {
2012 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2013 dep->endpoint.comp_desc = NULL;
2014 }
2015
74674cbf 2016 spin_lock_init(&dep->lock);
72246da4
FB		 2017
2018 if (epnum == 0 || epnum == 1) {
e117e742 2019 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2020 dep->endpoint.maxburst = 1;
72246da4
FB		 2021 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2022 if (!epnum)
2023 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2024 } else if (direction) {
2025 int mdwidth;
2026 int size;
2027 int ret;
2028 int num;
2029
2030 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2031 /* MDWIDTH is represented in bits, we need it in bytes */
2032 mdwidth /= 8;
2033
47d3946e 2034 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
28781789
FB		 2035 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2036
2037 /* FIFO Depth is in MDWDITH bytes. Multiply */
2038 size *= mdwidth;
2039
2040 num = size / 1024;
2041 if (num == 0)
2042 num = 1;
2043
2044 /*
2045 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2046 * internal overhead. We don't really know how these are used,
2047 * but documentation say it exists.
2048 */
2049 size -= mdwidth * (num + 1);
2050 size /= num;
2051
2052 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2053
2054 dep->endpoint.max_streams = 15;
2055 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2056 list_add_tail(&dep->endpoint.ep_list,
2057 &dwc->gadget.ep_list);
2058
2059 ret = dwc3_alloc_trb_pool(dep);
2060 if (ret)
2061 return ret;
72246da4
FB		 2062 } else {
2063 int ret;
2064
e117e742 2065 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2066 dep->endpoint.max_streams = 15;
72246da4
FB		 2067 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2068 list_add_tail(&dep->endpoint.ep_list,
2069 &dwc->gadget.ep_list);
2070
2071 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2072 if (ret)
72246da4 2073 return ret;
72246da4 2074 }
25b8ff68 2075
a474d3b7
RB		 2076 if (epnum == 0 || epnum == 1) {
2077 dep->endpoint.caps.type_control = true;
2078 } else {
2079 dep->endpoint.caps.type_iso = true;
2080 dep->endpoint.caps.type_bulk = true;
2081 dep->endpoint.caps.type_int = true;
2082 }
2083
47d3946e 2084 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2085 dep->endpoint.caps.dir_out = !direction;
2086
aa3342c8
FB		 2087 INIT_LIST_HEAD(&dep->pending_list);
2088 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2089 }
2090
2091 return 0;
2092}
2093
2094static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2095{
2096 struct dwc3_ep *dep;
2097 u8 epnum;
2098
2099 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2100 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2101 if (!dep)
2102 continue;
5bf8fae3
GC		 2103 /*
2104 * Physical endpoints 0 and 1 are special; they form the
2105 * bi-directional USB endpoint 0.
2106 *
2107 * For those two physical endpoints, we don't allocate a TRB
2108 * pool nor do we add them the endpoints list. Due to that, we
2109 * shouldn't do these two operations otherwise we would end up
2110 * with all sorts of bugs when removing dwc3.ko.
2111 */
2112 if (epnum != 0 && epnum != 1) {
2113 dwc3_free_trb_pool(dep);
72246da4 2114 list_del(&dep->endpoint.ep_list);
5bf8fae3 2115 }
72246da4
FB		 2116
2117 kfree(dep);
2118 }
2119}
2120
72246da4 2121/* -------------------------------------------------------------------------- */
e5caff68 2122
e5ba5ec8
PA		 2123static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2124 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2125 const struct dwc3_event_depevt *event, int status,
2126 int chain)
72246da4 2127{
72246da4
FB		 2128 unsigned int count;
2129 unsigned int s_pkt = 0;
d6d6ec7b 2130 unsigned int trb_status;
72246da4 2131
dc55c67e 2132 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2133
2134 if (req->trb == trb)
2135 dep->queued_requests--;
2136
2c4cbe6e
FB		 2137 trace_dwc3_complete_trb(dep, trb);
2138
e5b36ae2
FB		 2139 /*
2140 * If we're in the middle of series of chained TRBs and we
2141 * receive a short transfer along the way, DWC3 will skip
2142 * through all TRBs including the last TRB in the chain (the
2143 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2144 * bit and SW has to do it manually.
2145 *
2146 * We're going to do that here to avoid problems of HW trying
2147 * to use bogus TRBs for transfers.
2148 */
2149 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2150 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2151
c6267a51
FB		 2152 /*
2153 * If we're dealing with unaligned size OUT transfer, we will be left
2154 * with one TRB pending in the ring. We need to manually clear HWO bit
2155 * from that TRB.
2156 */
d6e5a549 2157 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
c6267a51
FB		 2158 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2159 return 1;
2160 }
2161
e5ba5ec8 2162 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2163 req->remaining += count;
e5ba5ec8 2164
35b2719e
FB		 2165 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2166 return 1;
2167
e5ba5ec8
PA		 2168 if (dep->direction) {
2169 if (count) {
2170 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2171 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2172 /*
2173 * If missed isoc occurred and there is
2174 * no request queued then issue END
2175 * TRANSFER, so that core generates
2176 * next xfernotready and we will issue
2177 * a fresh START TRANSFER.
2178 * If there are still queued request
2179 * then wait, do not issue either END
2180 * or UPDATE TRANSFER, just attach next
aa3342c8 2181 * request in pending_list during
e5ba5ec8
PA		 2182 * giveback.If any future queued request
2183 * is successfully transferred then we
2184 * will issue UPDATE TRANSFER for all
aa3342c8 2185 * request in the pending_list.
e5ba5ec8
PA		 2186 */
2187 dep->flags |= DWC3_EP_MISSED_ISOC;
2188 } else {
2189 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2190 dep->name);
2191 status = -ECONNRESET;
2192 }
2193 } else {
2194 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2195 }
2196 } else {
2197 if (count && (event->status & DEPEVT_STATUS_SHORT))
2198 s_pkt = 1;
2199 }
2200
7c705dfe 2201 if (s_pkt && !chain)
e5ba5ec8 2202 return 1;
f99f53f2 2203
e5ba5ec8
PA		 2204 if ((event->status & DEPEVT_STATUS_IOC) &&
2205 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2206 return 1;
f99f53f2 2207
e5ba5ec8
PA		 2208 return 0;
2209}
2210
2211static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2212 const struct dwc3_event_depevt *event, int status)
2213{
31162af4 2214 struct dwc3_request *req, *n;
e5ba5ec8 2215 struct dwc3_trb *trb;
d6e10bf2 2216 bool ioc = false;
e62c5bc5 2217 int ret = 0;
e5ba5ec8 2218
31162af4 2219 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2220 unsigned length;
e5b36ae2
FB		 2221 int chain;
2222
1f512119
FB		 2223 length = req->request.length;
2224 chain = req->num_pending_sgs > 0;
31162af4 2225 if (chain) {
1f512119 2226 struct scatterlist *sg = req->sg;
31162af4 2227 struct scatterlist *s;
1f512119 2228 unsigned int pending = req->num_pending_sgs;
31162af4 2229 unsigned int i;
c7de5734 2230
1f512119 2231 for_each_sg(sg, s, pending, i) {
31162af4 2232 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2233
7282c4ef
FB		 2234 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2235 break;
2236
1f512119
FB		 2237 req->sg = sg_next(s);
2238 req->num_pending_sgs--;
2239
31162af4
FB		 2240 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2241 event, status, chain);
1f512119
FB		 2242 if (ret)
2243 break;
31162af4
FB		 2244 }
2245 } else {
737f1ae2 2246 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2247 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2248 event, status, chain);
31162af4 2249 }
d115d705 2250
d6e5a549 2251 if (req->unaligned || req->zero) {
c6267a51
FB		 2252 trb = &dep->trb_pool[dep->trb_dequeue];
2253 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2254 event, status, false);
2255 req->unaligned = false;
d6e5a549 2256 req->zero = false;
c6267a51
FB		 2257 }
2258
e62c5bc5 2259 req->request.actual = length - req->remaining;
1f512119 2260
ff377ae4 2261 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2262 return __dwc3_gadget_kick_transfer(dep, 0);
2263
d115d705 2264 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2265
d6e10bf2
AB		 2266 if (ret) {
2267 if ((event->status & DEPEVT_STATUS_IOC) &&
2268 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2269 ioc = true;
72246da4 2270 break;
d6e10bf2 2271 }
31162af4 2272 }
72246da4 2273
4cb42217
FB		 2274 /*
2275 * Our endpoint might get disabled by another thread during
2276 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2277 * early on so DWC3_EP_BUSY flag gets cleared
2278 */
2279 if (!dep->endpoint.desc)
2280 return 1;
2281
cdc359dd 2282 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2283 list_empty(&dep->started_list)) {
2284 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2285 /*
2286 * If there is no entry in request list then do
2287 * not issue END TRANSFER now. Just set PENDING
2288 * flag, so that END TRANSFER is issued when an
2289 * entry is added into request list.
2290 */
2291 dep->flags = DWC3_EP_PENDING_REQUEST;
2292 } else {
b992e681 2293 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2294 dep->flags = DWC3_EP_ENABLED;
2295 }
7efea86c
PA		 2296 return 1;
2297 }
2298
d6e10bf2
AB		 2299 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2300 return 0;
2301
72246da4
FB		 2302 return 1;
2303}
2304
2305static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2306 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2307{
2308 unsigned status = 0;
2309 int clean_busy;
e18b7975
FB		 2310 u32 is_xfer_complete;
2311
2312 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2313
2314 if (event->status & DEPEVT_STATUS_BUSERR)
2315 status = -ECONNRESET;
2316
1d046793 2317 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2318 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2319 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2320 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2321
2322 /*
2323 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2324 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2325 */
2326 if (dwc->revision < DWC3_REVISION_183A) {
2327 u32 reg;
2328 int i;
2329
2330 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2331 dep = dwc->eps[i];
fae2b904
FB		 2332
2333 if (!(dep->flags & DWC3_EP_ENABLED))
2334 continue;
2335
aa3342c8 2336 if (!list_empty(&dep->started_list))
fae2b904
FB		 2337 return;
2338 }
2339
2340 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2341 reg |= dwc->u1u2;
2342 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2343
2344 dwc->u1u2 = 0;
2345 }
8a1a9c9e 2346
4cb42217
FB		 2347 /*
2348 * Our endpoint might get disabled by another thread during
2349 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2350 * early on so DWC3_EP_BUSY flag gets cleared
2351 */
2352 if (!dep->endpoint.desc)
2353 return;
2354
e6e709b7 2355 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2356 int ret;
2357
4fae2e3e 2358 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2359 if (!ret || ret == -EBUSY)
2360 return;
2361 }
72246da4
FB		 2362}
2363
72246da4
FB		 2364static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2365 const struct dwc3_event_depevt *event)
2366{
2367 struct dwc3_ep *dep;
2368 u8 epnum = event->endpoint_number;
76a638f8 2369 u8 cmd;
72246da4
FB		 2370
2371 dep = dwc->eps[epnum];
2372
d7fd41c6
JD		 2373 if (!(dep->flags & DWC3_EP_ENABLED)) {
2374 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2375 return;
2376
2377 /* Handle only EPCMDCMPLT when EP disabled */
2378 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2379 return;
2380 }
3336abb5 2381
72246da4
FB		 2382 if (epnum == 0 || epnum == 1) {
2383 dwc3_ep0_interrupt(dwc, event);
2384 return;
2385 }
2386
2387 switch (event->endpoint_event) {
2388 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2389 dep->resource_index = 0;
c2df85ca 2390
16e78db7 2391 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2392 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2393 return;
2394 }
2395
029d97ff 2396 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2397 break;
2398 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2399 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2400 break;
2401 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2402 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2403 dwc3_gadget_start_isoc(dwc, dep, event);
2404 } else {
2405 int ret;
2406
4fae2e3e 2407 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2408 if (!ret || ret == -EBUSY)
2409 return;
72246da4
FB		 2410 }
2411
879631aa
FB		 2412 break;
2413 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2414 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2415 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2416 dep->name);
2417 return;
2418 }
72246da4 2419 break;
72246da4 2420 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2421 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2422
2423 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2424 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2425 wake_up(&dep->wait_end_transfer);
2426 }
2427 break;
2428 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2429 break;
2430 }
2431}
2432
2433static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2434{
2435 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2436 spin_unlock(&dwc->lock);
2437 dwc->gadget_driver->disconnect(&dwc->gadget);
2438 spin_lock(&dwc->lock);
2439 }
2440}
2441
bc5ba2e0
FB		 2442static void dwc3_suspend_gadget(struct dwc3 *dwc)
2443{
73a30bfc 2444 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2445 spin_unlock(&dwc->lock);
2446 dwc->gadget_driver->suspend(&dwc->gadget);
2447 spin_lock(&dwc->lock);
2448 }
2449}
2450
2451static void dwc3_resume_gadget(struct dwc3 *dwc)
2452{
73a30bfc 2453 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2454 spin_unlock(&dwc->lock);
2455 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2456 spin_lock(&dwc->lock);
8e74475b
FB		 2457 }
2458}
2459
2460static void dwc3_reset_gadget(struct dwc3 *dwc)
2461{
2462 if (!dwc->gadget_driver)
2463 return;
2464
2465 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2466 spin_unlock(&dwc->lock);
2467 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2468 spin_lock(&dwc->lock);
2469 }
2470}
2471
b992e681 2472static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2473{
2474 struct dwc3_ep *dep;
2475 struct dwc3_gadget_ep_cmd_params params;
2476 u32 cmd;
2477 int ret;
2478
2479 dep = dwc->eps[epnum];
2480
76a638f8
BW		 2481 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2482 !dep->resource_index)
3daf74d7
PA		 2483 return;
2484
57911504
PA		 2485 /*
2486 * NOTICE: We are violating what the Databook says about the
2487 * EndTransfer command. Ideally we would _always_ wait for the
2488 * EndTransfer Command Completion IRQ, but that's causing too
2489 * much trouble synchronizing between us and gadget driver.
2490 *
2491 * We have discussed this with the IP Provider and it was
2492 * suggested to giveback all requests here, but give HW some
2493 * extra time to synchronize with the interconnect. We're using
dc93b41a 2494 * an arbitrary 100us delay for that.
57911504
PA		 2495 *
2496 * Note also that a similar handling was tested by Synopsys
2497 * (thanks a lot Paul) and nothing bad has come out of it.
2498 * In short, what we're doing is:
2499 *
2500 * - Issue EndTransfer WITH CMDIOC bit set
2501 * - Wait 100us
06281d46
JY		 2502 *
2503 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2504 * supports a mode to work around the above limitation. The
2505 * software can poll the CMDACT bit in the DEPCMD register
2506 * after issuing a EndTransfer command. This mode is enabled
2507 * by writing GUCTL2[14]. This polling is already done in the
2508 * dwc3_send_gadget_ep_cmd() function so if the mode is
2509 * enabled, the EndTransfer command will have completed upon
2510 * returning from this function and we don't need to delay for
2511 * 100us.
2512 *
2513 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2514 */
2515
3daf74d7 2516 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2517 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2518 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2519 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2520 memset(&params, 0, sizeof(params));
2cd4718d 2521 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2522 WARN_ON_ONCE(ret);
b4996a86 2523 dep->resource_index = 0;
041d81f4 2524 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2525
76a638f8
BW		 2526 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2527 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2528 udelay(100);
76a638f8 2529 }
72246da4
FB		 2530}
2531
72246da4
FB		 2532static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2533{
2534 u32 epnum;
2535
2536 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2537 struct dwc3_ep *dep;
72246da4
FB		 2538 int ret;
2539
2540 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2541 if (!dep)
2542 continue;
72246da4
FB		 2543
2544 if (!(dep->flags & DWC3_EP_STALL))
2545 continue;
2546
2547 dep->flags &= ~DWC3_EP_STALL;
2548
50c763f8 2549 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2550 WARN_ON_ONCE(ret);
2551 }
2552}
2553
2554static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2555{
c4430a26
FB		 2556 int reg;
2557
72246da4
FB		 2558 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2559 reg &= ~DWC3_DCTL_INITU1ENA;
2560 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2561
2562 reg &= ~DWC3_DCTL_INITU2ENA;
2563 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2564
72246da4
FB		 2565 dwc3_disconnect_gadget(dwc);
2566
2567 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2568 dwc->setup_packet_pending = false;
06a374ed 2569 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2570
2571 dwc->connected = false;
72246da4
FB		 2572}
2573
72246da4
FB		 2574static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2575{
2576 u32 reg;
2577
fc8bb91b
FB		 2578 dwc->connected = true;
2579
df62df56
FB		 2580 /*
2581 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2582 * would cause a missing Disconnect Event if there's a
2583 * pending Setup Packet in the FIFO.
2584 *
2585 * There's no suggested workaround on the official Bug
2586 * report, which states that "unless the driver/application
2587 * is doing any special handling of a disconnect event,
2588 * there is no functional issue".
2589 *
2590 * Unfortunately, it turns out that we _do_ some special
2591 * handling of a disconnect event, namely complete all
2592 * pending transfers, notify gadget driver of the
2593 * disconnection, and so on.
2594 *
2595 * Our suggested workaround is to follow the Disconnect
2596 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2597 * flag. Such flag gets set whenever we have a SETUP_PENDING
2598 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2599 * same endpoint.
2600 *
2601 * Refers to:
2602 *
2603 * STAR#9000466709: RTL: Device : Disconnect event not
2604 * generated if setup packet pending in FIFO
2605 */
2606 if (dwc->revision < DWC3_REVISION_188A) {
2607 if (dwc->setup_packet_pending)
2608 dwc3_gadget_disconnect_interrupt(dwc);
2609 }
2610
8e74475b 2611 dwc3_reset_gadget(dwc);
72246da4
FB		 2612
2613 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2614 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2615 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2616 dwc->test_mode = false;
72246da4
FB		 2617 dwc3_clear_stall_all_ep(dwc);
2618
2619 /* Reset device address to zero */
2620 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2621 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2622 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2623}
2624
72246da4
FB		 2625static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2626{
72246da4
FB		 2627 struct dwc3_ep *dep;
2628 int ret;
2629 u32 reg;
2630 u8 speed;
2631
72246da4
FB		 2632 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2633 speed = reg & DWC3_DSTS_CONNECTSPD;
2634 dwc->speed = speed;
2635
5fb6fdaf
JY		 2636 /*
2637 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2638 * each time on Connect Done.
2639 *
2640 * Currently we always use the reset value. If any platform
2641 * wants to set this to a different value, we need to add a
2642 * setting and update GCTL.RAMCLKSEL here.
2643 */
72246da4
FB		 2644
2645 switch (speed) {
2da9ad76 2646 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2647 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2648 dwc->gadget.ep0->maxpacket = 512;
2649 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2650 break;
2da9ad76 2651 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2652 /*
2653 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2654 * would cause a missing USB3 Reset event.
2655 *
2656 * In such situations, we should force a USB3 Reset
2657 * event by calling our dwc3_gadget_reset_interrupt()
2658 * routine.
2659 *
2660 * Refers to:
2661 *
2662 * STAR#9000483510: RTL: SS : USB3 reset event may
2663 * not be generated always when the link enters poll
2664 */
2665 if (dwc->revision < DWC3_REVISION_190A)
2666 dwc3_gadget_reset_interrupt(dwc);
2667
72246da4
FB		 2668 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2669 dwc->gadget.ep0->maxpacket = 512;
2670 dwc->gadget.speed = USB_SPEED_SUPER;
2671 break;
2da9ad76 2672 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2673 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2674 dwc->gadget.ep0->maxpacket = 64;
2675 dwc->gadget.speed = USB_SPEED_HIGH;
2676 break;
9418ee15 2677 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2678 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2679 dwc->gadget.ep0->maxpacket = 64;
2680 dwc->gadget.speed = USB_SPEED_FULL;
2681 break;
2da9ad76 2682 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2683 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2684 dwc->gadget.ep0->maxpacket = 8;
2685 dwc->gadget.speed = USB_SPEED_LOW;
2686 break;
2687 }
2688
2b758350
PA		 2689 /* Enable USB2 LPM Capability */
2690
ee5cd41c 2691 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2692 (speed != DWC3_DSTS_SUPERSPEED) &&
2693 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2694 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2695 reg |= DWC3_DCFG_LPM_CAP;
2696 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2697
2698 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2699 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2700
460d098c 2701 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2702
80caf7d2
HR		 2703 /*
2704 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2705 * DCFG.LPMCap is set, core responses with an ACK and the
2706 * BESL value in the LPM token is less than or equal to LPM
2707 * NYET threshold.
2708 */
2709 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2710 && dwc->has_lpm_erratum,
9165dabb 2711 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2712
2713 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2714 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2715
356363bf
FB		 2716 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2717 } else {
2718 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2719 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2720 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2721 }
2722
72246da4 2723 dep = dwc->eps[0];
39ebb05c 2724 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2725 if (ret) {
2726 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2727 return;
2728 }
2729
2730 dep = dwc->eps[1];
39ebb05c 2731 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2732 if (ret) {
2733 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2734 return;
2735 }
2736
2737 /*
2738 * Configure PHY via GUSB3PIPECTLn if required.
2739 *
2740 * Update GTXFIFOSIZn
2741 *
2742 * In both cases reset values should be sufficient.
2743 */
2744}
2745
2746static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2747{
72246da4
FB		 2748 /*
2749 * TODO take core out of low power mode when that's
2750 * implemented.
2751 */
2752
ad14d4e0
JL		 2753 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2754 spin_unlock(&dwc->lock);
2755 dwc->gadget_driver->resume(&dwc->gadget);
2756 spin_lock(&dwc->lock);
2757 }
72246da4
FB		 2758}
2759
2760static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2761 unsigned int evtinfo)
2762{
fae2b904 2763 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2764 unsigned int pwropt;
2765
2766 /*
2767 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2768 * Hibernation mode enabled which would show up when device detects
2769 * host-initiated U3 exit.
2770 *
2771 * In that case, device will generate a Link State Change Interrupt
2772 * from U3 to RESUME which is only necessary if Hibernation is
2773 * configured in.
2774 *
2775 * There are no functional changes due to such spurious event and we
2776 * just need to ignore it.
2777 *
2778 * Refers to:
2779 *
2780 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2781 * operational mode
2782 */
2783 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2784 if ((dwc->revision < DWC3_REVISION_250A) &&
2785 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2786 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2787 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2788 return;
2789 }
2790 }
fae2b904
FB		 2791
2792 /*
2793 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2794 * on the link partner, the USB session might do multiple entry/exit
2795 * of low power states before a transfer takes place.
2796 *
2797 * Due to this problem, we might experience lower throughput. The
2798 * suggested workaround is to disable DCTL[12:9] bits if we're
2799 * transitioning from U1/U2 to U0 and enable those bits again
2800 * after a transfer completes and there are no pending transfers
2801 * on any of the enabled endpoints.
2802 *
2803 * This is the first half of that workaround.
2804 *
2805 * Refers to:
2806 *
2807 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2808 * core send LGO_Ux entering U0
2809 */
2810 if (dwc->revision < DWC3_REVISION_183A) {
2811 if (next == DWC3_LINK_STATE_U0) {
2812 u32 u1u2;
2813 u32 reg;
2814
2815 switch (dwc->link_state) {
2816 case DWC3_LINK_STATE_U1:
2817 case DWC3_LINK_STATE_U2:
2818 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2819 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2820 | DWC3_DCTL_ACCEPTU2ENA
2821 | DWC3_DCTL_INITU1ENA
2822 | DWC3_DCTL_ACCEPTU1ENA);
2823
2824 if (!dwc->u1u2)
2825 dwc->u1u2 = reg & u1u2;
2826
2827 reg &= ~u1u2;
2828
2829 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2830 break;
2831 default:
2832 /* do nothing */
2833 break;
2834 }
2835 }
2836 }
2837
bc5ba2e0
FB		 2838 switch (next) {
2839 case DWC3_LINK_STATE_U1:
2840 if (dwc->speed == USB_SPEED_SUPER)
2841 dwc3_suspend_gadget(dwc);
2842 break;
2843 case DWC3_LINK_STATE_U2:
2844 case DWC3_LINK_STATE_U3:
2845 dwc3_suspend_gadget(dwc);
2846 break;
2847 case DWC3_LINK_STATE_RESUME:
2848 dwc3_resume_gadget(dwc);
2849 break;
2850 default:
2851 /* do nothing */
2852 break;
2853 }
2854
e57ebc1d 2855 dwc->link_state = next;
72246da4
FB		 2856}
2857
72704f87
BW		 2858static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2859 unsigned int evtinfo)
2860{
2861 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2862
2863 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2864 dwc3_suspend_gadget(dwc);
2865
2866 dwc->link_state = next;
2867}
2868
e1dadd3b
FB		 2869static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2870 unsigned int evtinfo)
2871{
2872 unsigned int is_ss = evtinfo & BIT(4);
2873
2874 /**
2875 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2876 * have a known issue which can cause USB CV TD.9.23 to fail
2877 * randomly.
2878 *
2879 * Because of this issue, core could generate bogus hibernation
2880 * events which SW needs to ignore.
2881 *
2882 * Refers to:
2883 *
2884 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2885 * Device Fallback from SuperSpeed
2886 */
2887 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2888 return;
2889
2890 /* enter hibernation here */
2891}
2892
72246da4
FB		 2893static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2894 const struct dwc3_event_devt *event)
2895{
2896 switch (event->type) {
2897 case DWC3_DEVICE_EVENT_DISCONNECT:
2898 dwc3_gadget_disconnect_interrupt(dwc);
2899 break;
2900 case DWC3_DEVICE_EVENT_RESET:
2901 dwc3_gadget_reset_interrupt(dwc);
2902 break;
2903 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2904 dwc3_gadget_conndone_interrupt(dwc);
2905 break;
2906 case DWC3_DEVICE_EVENT_WAKEUP:
2907 dwc3_gadget_wakeup_interrupt(dwc);
2908 break;
e1dadd3b
FB		 2909 case DWC3_DEVICE_EVENT_HIBER_REQ:
2910 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2911 "unexpected hibernation event\n"))
2912 break;
2913
2914 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2915 break;
72246da4
FB		 2916 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2917 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2918 break;
2919 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2920 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2921 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2922 /*
2923 * Ignore suspend event until the gadget enters into
2924 * USB_STATE_CONFIGURED state.
2925 */
2926 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2927 dwc3_gadget_suspend_interrupt(dwc,
2928 event->event_info);
2929 }
72246da4
FB		 2930 break;
2931 case DWC3_DEVICE_EVENT_SOF:
72246da4 2932 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2933 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2934 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2935 break;
2936 default:
e9f2aa87 2937 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2938 }
2939}
2940
2941static void dwc3_process_event_entry(struct dwc3 *dwc,
2942 const union dwc3_event *event)
2943{
43c96be1 2944 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2945
72246da4
FB		 2946 /* Endpoint IRQ, handle it and return early */
2947 if (event->type.is_devspec == 0) {
2948 /* depevt */
2949 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2950 }
2951
2952 switch (event->type.type) {
2953 case DWC3_EVENT_TYPE_DEV:
2954 dwc3_gadget_interrupt(dwc, &event->devt);
2955 break;
2956 /* REVISIT what to do with Carkit and I2C events ? */
2957 default:
2958 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2959 }
2960}
2961
dea520a4 2962static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2963{
dea520a4 2964 struct dwc3 *dwc = evt->dwc;
b15a762f 2965 irqreturn_t ret = IRQ_NONE;
f42f2447 2966 int left;
e8adfc30 2967 u32 reg;
b15a762f 2968
f42f2447 2969 left = evt->count;
b15a762f 2970
f42f2447
FB		 2971 if (!(evt->flags & DWC3_EVENT_PENDING))
2972 return IRQ_NONE;
b15a762f 2973
f42f2447
FB		 2974 while (left > 0) {
2975 union dwc3_event event;
b15a762f 2976
ebbb2d59 2977 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2978
f42f2447 2979 dwc3_process_event_entry(dwc, &event);
b15a762f 2980
f42f2447
FB		 2981 /*
2982 * FIXME we wrap around correctly to the next entry as
2983 * almost all entries are 4 bytes in size. There is one
2984 * entry which has 12 bytes which is a regular entry
2985 * followed by 8 bytes data. ATM I don't know how
2986 * things are organized if we get next to the a
2987 * boundary so I worry about that once we try to handle
2988 * that.
2989 */
caefe6c7 2990 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2991 left -= 4;
f42f2447 2992 }
b15a762f 2993
f42f2447
FB		 2994 evt->count = 0;
2995 evt->flags &= ~DWC3_EVENT_PENDING;
2996 ret = IRQ_HANDLED;
b15a762f 2997
f42f2447 2998 /* Unmask interrupt */
660e9bde 2999 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 3000 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 3001 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 3002
cf40b86b
JY		 3003 if (dwc->imod_interval) {
3004 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3005 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3006 }
3007
f42f2447
FB		 3008 return ret;
3009}
e8adfc30 3010
dea520a4 3011static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3012{
dea520a4
FB		 3013 struct dwc3_event_buffer *evt = _evt;
3014 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3015 unsigned long flags;
f42f2447 3016 irqreturn_t ret = IRQ_NONE;
f42f2447 3017
e5f68b4a 3018 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3019 ret = dwc3_process_event_buf(evt);
e5f68b4a 3020 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3021
3022 return ret;
3023}
3024
dea520a4 3025static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3026{
dea520a4 3027 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3028 u32 amount;
72246da4 3029 u32 count;
e8adfc30 3030 u32 reg;
72246da4 3031
fc8bb91b
FB		 3032 if (pm_runtime_suspended(dwc->dev)) {
3033 pm_runtime_get(dwc->dev);
3034 disable_irq_nosync(dwc->irq_gadget);
3035 dwc->pending_events = true;
3036 return IRQ_HANDLED;
3037 }
3038
d325a1de
TN		 3039 /*
3040 * With PCIe legacy interrupt, test shows that top-half irq handler can
3041 * be called again after HW interrupt deassertion. Check if bottom-half
3042 * irq event handler completes before caching new event to prevent
3043 * losing events.
3044 */
3045 if (evt->flags & DWC3_EVENT_PENDING)
3046 return IRQ_HANDLED;
3047
660e9bde 3048 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3049 count &= DWC3_GEVNTCOUNT_MASK;
3050 if (!count)
3051 return IRQ_NONE;
3052
b15a762f
FB		 3053 evt->count = count;
3054 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3055
e8adfc30 3056 /* Mask interrupt */
660e9bde 3057 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3058 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3059 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3060
ebbb2d59
JY		 3061 amount = min(count, evt->length - evt->lpos);
3062 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3063
3064 if (amount < count)
3065 memcpy(evt->cache, evt->buf, count - amount);
3066
65aca320
JY		 3067 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3068
b15a762f 3069 return IRQ_WAKE_THREAD;
72246da4
FB		 3070}
3071
dea520a4 3072static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3073{
dea520a4 3074 struct dwc3_event_buffer *evt = _evt;
72246da4 3075
dea520a4 3076 return dwc3_check_event_buf(evt);
72246da4
FB		 3077}
3078
6db3812e
FB		 3079static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3080{
3081 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3082 int irq;
3083
3084 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3085 if (irq > 0)
3086 goto out;
3087
3088 if (irq == -EPROBE_DEFER)
3089 goto out;
3090
3091 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3092 if (irq > 0)
3093 goto out;
3094
3095 if (irq == -EPROBE_DEFER)
3096 goto out;
3097
3098 irq = platform_get_irq(dwc3_pdev, 0);
3099 if (irq > 0)
3100 goto out;
3101
3102 if (irq != -EPROBE_DEFER)
3103 dev_err(dwc->dev, "missing peripheral IRQ\n");
3104
3105 if (!irq)
3106 irq = -EINVAL;
3107
3108out:
3109 return irq;
3110}
3111
72246da4
FB		 3112/**
3113 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3114 * @dwc: pointer to our controller context structure
72246da4
FB		 3115 *
3116 * Returns 0 on success otherwise negative errno.
3117 */
41ac7b3a 3118int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3119{
6db3812e
FB		 3120 int ret;
3121 int irq;
9522def4 3122
6db3812e
FB		 3123 irq = dwc3_gadget_get_irq(dwc);
3124 if (irq < 0) {
3125 ret = irq;
3126 goto err0;
9522def4
RQ		 3127 }
3128
3129 dwc->irq_gadget = irq;
72246da4 3130
d64ff406
AB		 3131 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3132 sizeof(*dwc->ep0_trb) * 2,
3133 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3134 if (!dwc->ep0_trb) {
3135 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3136 ret = -ENOMEM;
7d5e650a 3137 goto err0;
72246da4
FB		 3138 }
3139
4199c5f8 3140 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
72246da4 3141 if (!dwc->setup_buf) {
72246da4 3142 ret = -ENOMEM;
7d5e650a 3143 goto err1;
72246da4
FB		 3144 }
3145
905dc04e
FB		 3146 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3147 &dwc->bounce_addr, GFP_KERNEL);
3148 if (!dwc->bounce) {
3149 ret = -ENOMEM;
d6e5a549 3150 goto err2;
905dc04e
FB		 3151 }
3152
bb014736
BW		 3153 init_completion(&dwc->ep0_in_setup);
3154
72246da4 3155 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3156 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3157 dwc->gadget.sg_supported = true;
72246da4 3158 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3159 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3160
b9e51b2b
BM		 3161 /*
3162 * FIXME We might be setting max_speed to <SUPER, however versions
3163 * <2.20a of dwc3 have an issue with metastability (documented
3164 * elsewhere in this driver) which tells us we can't set max speed to
3165 * anything lower than SUPER.
3166 *
3167 * Because gadget.max_speed is only used by composite.c and function
3168 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3169 * to happen so we avoid sending SuperSpeed Capability descriptor
3170 * together with our BOS descriptor as that could confuse host into
3171 * thinking we can handle super speed.
3172 *
3173 * Note that, in fact, we won't even support GetBOS requests when speed
3174 * is less than super speed because we don't have means, yet, to tell
3175 * composite.c that we are USB 2.0 + LPM ECN.
3176 */
3177 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3178 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3179 dwc->revision);
3180
3181 dwc->gadget.max_speed = dwc->maximum_speed;
3182
72246da4
FB		 3183 /*
3184 * REVISIT: Here we should clear all pending IRQs to be
3185 * sure we're starting from a well known location.
3186 */
3187
f3bcfc7e 3188 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3189 if (ret)
d6e5a549 3190 goto err3;
72246da4 3191
72246da4
FB		 3192 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3193 if (ret) {
3194 dev_err(dwc->dev, "failed to register udc\n");
d6e5a549 3195 goto err4;
72246da4
FB		 3196 }
3197
3198 return 0;
3199
7d5e650a 3200err4:
d6e5a549 3201 dwc3_gadget_free_endpoints(dwc);
04c03d10 3202
7d5e650a 3203err3:
d6e5a549
FB		 3204 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3205 dwc->bounce_addr);
5812b1c2 3206
7d5e650a 3207err2:
0fc9a1be 3208 kfree(dwc->setup_buf);
72246da4 3209
7d5e650a 3210err1:
d64ff406 3211 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3212 dwc->ep0_trb, dwc->ep0_trb_addr);
3213
72246da4
FB		 3214err0:
3215 return ret;
3216}
3217
7415f17c
FB		 3218/* -------------------------------------------------------------------------- */
3219
72246da4
FB		 3220void dwc3_gadget_exit(struct dwc3 *dwc)
3221{
72246da4 3222 usb_del_gadget_udc(&dwc->gadget);
72246da4 3223 dwc3_gadget_free_endpoints(dwc);
905dc04e 3224 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
d6e5a549 3225 dwc->bounce_addr);
0fc9a1be 3226 kfree(dwc->setup_buf);
d64ff406 3227 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
d6e5a549 3228 dwc->ep0_trb, dwc->ep0_trb_addr);
72246da4 3229}
7415f17c 3230
0b0231aa 3231int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3232{
9772b47a
RQ		 3233 if (!dwc->gadget_driver)
3234 return 0;
3235
1551e35e 3236 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3237 dwc3_disconnect_gadget(dwc);
3238 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3239
3240 return 0;
3241}
3242
3243int dwc3_gadget_resume(struct dwc3 *dwc)
3244{
7415f17c
FB		 3245 int ret;
3246
9772b47a
RQ		 3247 if (!dwc->gadget_driver)
3248 return 0;
3249
9f8a67b6
FB		 3250 ret = __dwc3_gadget_start(dwc);
3251 if (ret < 0)
7415f17c
FB		 3252 goto err0;
3253
9f8a67b6
FB		 3254 ret = dwc3_gadget_run_stop(dwc, true, false);
3255 if (ret < 0)
7415f17c
FB		 3256 goto err1;
3257
7415f17c
FB		 3258 return 0;
3259
3260err1:
9f8a67b6 3261 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3262
3263err0:
3264 return ret;
3265}
fc8bb91b
FB		 3266
3267void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3268{
3269 if (dwc->pending_events) {
3270 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3271 dwc->pending_events = false;
3272 enable_irq(dwc->irq_gadget);
3273 }
3274}
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