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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/platform_device.h> | |
44 | #include <linux/pm_runtime.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/list.h> | |
48 | #include <linux/dma-mapping.h> | |
49 | ||
50 | #include <linux/usb/ch9.h> | |
51 | #include <linux/usb/gadget.h> | |
52 | ||
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
04a9bfcd FB |
57 | /** |
58 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
59 | * @dwc: pointer to our context structure | |
60 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
61 | * | |
62 | * Caller should take care of locking. This function will | |
63 | * return 0 on success or -EINVAL if wrong Test Selector | |
64 | * is passed | |
65 | */ | |
66 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
67 | { | |
68 | u32 reg; | |
69 | ||
70 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
71 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
72 | ||
73 | switch (mode) { | |
74 | case TEST_J: | |
75 | case TEST_K: | |
76 | case TEST_SE0_NAK: | |
77 | case TEST_PACKET: | |
78 | case TEST_FORCE_EN: | |
79 | reg |= mode << 1; | |
80 | break; | |
81 | default: | |
82 | return -EINVAL; | |
83 | } | |
84 | ||
85 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
8598bde7 FB |
90 | /** |
91 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
92 | * @dwc: pointer to our context structure | |
93 | * @state: the state to put link into | |
94 | * | |
95 | * Caller should take care of locking. This function will | |
aee63e3c | 96 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
97 | */ |
98 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
99 | { | |
aee63e3c | 100 | int retries = 10000; |
8598bde7 FB |
101 | u32 reg; |
102 | ||
802fde98 PZ |
103 | /* |
104 | * Wait until device controller is ready. Only applies to 1.94a and | |
105 | * later RTL. | |
106 | */ | |
107 | if (dwc->revision >= DWC3_REVISION_194A) { | |
108 | while (--retries) { | |
109 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
110 | if (reg & DWC3_DSTS_DCNRD) | |
111 | udelay(5); | |
112 | else | |
113 | break; | |
114 | } | |
115 | ||
116 | if (retries <= 0) | |
117 | return -ETIMEDOUT; | |
118 | } | |
119 | ||
8598bde7 FB |
120 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
121 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
122 | ||
123 | /* set requested state */ | |
124 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
125 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
126 | ||
802fde98 PZ |
127 | /* |
128 | * The following code is racy when called from dwc3_gadget_wakeup, | |
129 | * and is not needed, at least on newer versions | |
130 | */ | |
131 | if (dwc->revision >= DWC3_REVISION_194A) | |
132 | return 0; | |
133 | ||
8598bde7 | 134 | /* wait for a change in DSTS */ |
aed430e5 | 135 | retries = 10000; |
8598bde7 FB |
136 | while (--retries) { |
137 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
138 | ||
8598bde7 FB |
139 | if (DWC3_DSTS_USBLNKST(reg) == state) |
140 | return 0; | |
141 | ||
aee63e3c | 142 | udelay(5); |
8598bde7 FB |
143 | } |
144 | ||
145 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
146 | ||
147 | return -ETIMEDOUT; | |
148 | } | |
149 | ||
457e84b6 FB |
150 | /** |
151 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
152 | * @dwc: pointer to our context structure | |
153 | * | |
154 | * This function will a best effort FIFO allocation in order | |
155 | * to improve FIFO usage and throughput, while still allowing | |
156 | * us to enable as many endpoints as possible. | |
157 | * | |
158 | * Keep in mind that this operation will be highly dependent | |
159 | * on the configured size for RAM1 - which contains TxFifo -, | |
160 | * the amount of endpoints enabled on coreConsultant tool, and | |
161 | * the width of the Master Bus. | |
162 | * | |
163 | * In the ideal world, we would always be able to satisfy the | |
164 | * following equation: | |
165 | * | |
166 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
167 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
168 | * | |
169 | * Unfortunately, due to many variables that's not always the case. | |
170 | */ | |
171 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
172 | { | |
173 | int last_fifo_depth = 0; | |
174 | int ram1_depth; | |
175 | int fifo_size; | |
176 | int mdwidth; | |
177 | int num; | |
178 | ||
179 | if (!dwc->needs_fifo_resize) | |
180 | return 0; | |
181 | ||
182 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
183 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
184 | ||
185 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
186 | mdwidth >>= 3; | |
187 | ||
188 | /* | |
189 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
190 | * for each enabled endpoint, later patches will come to | |
191 | * improve this algorithm so that we better use the internal | |
192 | * FIFO space | |
193 | */ | |
194 | for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { | |
195 | struct dwc3_ep *dep = dwc->eps[num]; | |
196 | int fifo_number = dep->number >> 1; | |
2e81c36a | 197 | int mult = 1; |
457e84b6 FB |
198 | int tmp; |
199 | ||
200 | if (!(dep->number & 1)) | |
201 | continue; | |
202 | ||
203 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
204 | continue; | |
205 | ||
16e78db7 IS |
206 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
207 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
208 | mult = 3; |
209 | ||
210 | /* | |
211 | * REVISIT: the following assumes we will always have enough | |
212 | * space available on the FIFO RAM for all possible use cases. | |
213 | * Make sure that's true somehow and change FIFO allocation | |
214 | * accordingly. | |
215 | * | |
216 | * If we have Bulk or Isochronous endpoints, we want | |
217 | * them to be able to be very, very fast. So we're giving | |
218 | * those endpoints a fifo_size which is enough for 3 full | |
219 | * packets | |
220 | */ | |
221 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
222 | tmp += mdwidth; |
223 | ||
224 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 225 | |
457e84b6 FB |
226 | fifo_size |= (last_fifo_depth << 16); |
227 | ||
228 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
229 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
230 | ||
231 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), | |
232 | fifo_size); | |
233 | ||
234 | last_fifo_depth += (fifo_size & 0xffff); | |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
72246da4 FB |
240 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
241 | int status) | |
242 | { | |
243 | struct dwc3 *dwc = dep->dwc; | |
244 | ||
245 | if (req->queued) { | |
eeb720fb FB |
246 | if (req->request.num_mapped_sgs) |
247 | dep->busy_slot += req->request.num_mapped_sgs; | |
248 | else | |
249 | dep->busy_slot++; | |
250 | ||
72246da4 FB |
251 | /* |
252 | * Skip LINK TRB. We can't use req->trb and check for | |
253 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we just | |
254 | * completed (not the LINK TRB). | |
255 | */ | |
256 | if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
16e78db7 | 257 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
72246da4 FB |
258 | dep->busy_slot++; |
259 | } | |
260 | list_del(&req->list); | |
eeb720fb | 261 | req->trb = NULL; |
72246da4 FB |
262 | |
263 | if (req->request.status == -EINPROGRESS) | |
264 | req->request.status = status; | |
265 | ||
0fc9a1be FB |
266 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
267 | req->direction); | |
72246da4 FB |
268 | |
269 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
270 | req, dep->name, req->request.actual, | |
271 | req->request.length, status); | |
272 | ||
273 | spin_unlock(&dwc->lock); | |
0fc9a1be | 274 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
275 | spin_lock(&dwc->lock); |
276 | } | |
277 | ||
278 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
279 | { | |
280 | switch (cmd) { | |
281 | case DWC3_DEPCMD_DEPSTARTCFG: | |
282 | return "Start New Configuration"; | |
283 | case DWC3_DEPCMD_ENDTRANSFER: | |
284 | return "End Transfer"; | |
285 | case DWC3_DEPCMD_UPDATETRANSFER: | |
286 | return "Update Transfer"; | |
287 | case DWC3_DEPCMD_STARTTRANSFER: | |
288 | return "Start Transfer"; | |
289 | case DWC3_DEPCMD_CLEARSTALL: | |
290 | return "Clear Stall"; | |
291 | case DWC3_DEPCMD_SETSTALL: | |
292 | return "Set Stall"; | |
802fde98 PZ |
293 | case DWC3_DEPCMD_GETEPSTATE: |
294 | return "Get Endpoint State"; | |
72246da4 FB |
295 | case DWC3_DEPCMD_SETTRANSFRESOURCE: |
296 | return "Set Endpoint Transfer Resource"; | |
297 | case DWC3_DEPCMD_SETEPCONFIG: | |
298 | return "Set Endpoint Configuration"; | |
299 | default: | |
300 | return "UNKNOWN command"; | |
301 | } | |
302 | } | |
303 | ||
b09bb642 FB |
304 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
305 | { | |
306 | u32 timeout = 500; | |
307 | u32 reg; | |
308 | ||
309 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
310 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
311 | ||
312 | do { | |
313 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
314 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
315 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
316 | DWC3_DGCMD_STATUS(reg)); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | /* | |
321 | * We can't sleep here, because it's also called from | |
322 | * interrupt context. | |
323 | */ | |
324 | timeout--; | |
325 | if (!timeout) | |
326 | return -ETIMEDOUT; | |
327 | udelay(1); | |
328 | } while (1); | |
329 | } | |
330 | ||
72246da4 FB |
331 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
332 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
333 | { | |
334 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 335 | u32 timeout = 500; |
72246da4 FB |
336 | u32 reg; |
337 | ||
338 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", | |
339 | dep->name, | |
dc1c70a7 FB |
340 | dwc3_gadget_ep_cmd_string(cmd), params->param0, |
341 | params->param1, params->param2); | |
72246da4 | 342 | |
dc1c70a7 FB |
343 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
344 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
345 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
346 | |
347 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
348 | do { | |
349 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
350 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
351 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
352 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
353 | return 0; |
354 | } | |
355 | ||
356 | /* | |
72246da4 FB |
357 | * We can't sleep here, because it is also called from |
358 | * interrupt context. | |
359 | */ | |
360 | timeout--; | |
361 | if (!timeout) | |
362 | return -ETIMEDOUT; | |
363 | ||
61d58242 | 364 | udelay(1); |
72246da4 FB |
365 | } while (1); |
366 | } | |
367 | ||
368 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 369 | struct dwc3_trb *trb) |
72246da4 | 370 | { |
c439ef87 | 371 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
372 | |
373 | return dep->trb_pool_dma + offset; | |
374 | } | |
375 | ||
376 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
377 | { | |
378 | struct dwc3 *dwc = dep->dwc; | |
379 | ||
380 | if (dep->trb_pool) | |
381 | return 0; | |
382 | ||
383 | if (dep->number == 0 || dep->number == 1) | |
384 | return 0; | |
385 | ||
386 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
387 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
388 | &dep->trb_pool_dma, GFP_KERNEL); | |
389 | if (!dep->trb_pool) { | |
390 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
391 | dep->name); | |
392 | return -ENOMEM; | |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
399 | { | |
400 | struct dwc3 *dwc = dep->dwc; | |
401 | ||
402 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
403 | dep->trb_pool, dep->trb_pool_dma); | |
404 | ||
405 | dep->trb_pool = NULL; | |
406 | dep->trb_pool_dma = 0; | |
407 | } | |
408 | ||
409 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
410 | { | |
411 | struct dwc3_gadget_ep_cmd_params params; | |
412 | u32 cmd; | |
413 | ||
414 | memset(¶ms, 0x00, sizeof(params)); | |
415 | ||
416 | if (dep->number != 1) { | |
417 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
418 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
419 | if (dep->number > 1) { |
420 | if (dwc->start_config_issued) | |
421 | return 0; | |
422 | dwc->start_config_issued = true; | |
72246da4 | 423 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 424 | } |
72246da4 FB |
425 | |
426 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec FB |
433 | const struct usb_endpoint_descriptor *desc, |
434 | const struct usb_ss_ep_comp_descriptor *comp_desc) | |
72246da4 FB |
435 | { |
436 | struct dwc3_gadget_ep_cmd_params params; | |
437 | ||
438 | memset(¶ms, 0x00, sizeof(params)); | |
439 | ||
dc1c70a7 FB |
440 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
441 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) | |
442 | | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); | |
72246da4 | 443 | |
dc1c70a7 FB |
444 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
445 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 446 | |
18b7ede5 | 447 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
448 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
449 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
450 | dep->stream_capable = true; |
451 | } | |
452 | ||
72246da4 | 453 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 454 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
455 | |
456 | /* | |
457 | * We are doing 1:1 mapping for endpoints, meaning | |
458 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
459 | * so on. We consider the direction bit as part of the physical | |
460 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
461 | */ | |
dc1c70a7 | 462 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
463 | |
464 | /* | |
465 | * We must use the lower 16 TX FIFOs even though | |
466 | * HW might have more | |
467 | */ | |
468 | if (dep->direction) | |
dc1c70a7 | 469 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
470 | |
471 | if (desc->bInterval) { | |
dc1c70a7 | 472 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
473 | dep->interval = 1 << (desc->bInterval - 1); |
474 | } | |
475 | ||
476 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
477 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
478 | } | |
479 | ||
480 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
481 | { | |
482 | struct dwc3_gadget_ep_cmd_params params; | |
483 | ||
484 | memset(¶ms, 0x00, sizeof(params)); | |
485 | ||
dc1c70a7 | 486 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
487 | |
488 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
489 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
490 | } | |
491 | ||
492 | /** | |
493 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
494 | * @dep: endpoint to be initialized | |
495 | * @desc: USB Endpoint Descriptor | |
496 | * | |
497 | * Caller should take care of locking | |
498 | */ | |
499 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec FB |
500 | const struct usb_endpoint_descriptor *desc, |
501 | const struct usb_ss_ep_comp_descriptor *comp_desc) | |
72246da4 FB |
502 | { |
503 | struct dwc3 *dwc = dep->dwc; | |
504 | u32 reg; | |
505 | int ret = -ENOMEM; | |
506 | ||
507 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
508 | ret = dwc3_gadget_start_config(dwc, dep); | |
509 | if (ret) | |
510 | return ret; | |
511 | } | |
512 | ||
c90bfaec | 513 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); |
72246da4 FB |
514 | if (ret) |
515 | return ret; | |
516 | ||
517 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
518 | struct dwc3_trb *trb_st_hw; |
519 | struct dwc3_trb *trb_link; | |
72246da4 FB |
520 | |
521 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
522 | if (ret) | |
523 | return ret; | |
524 | ||
16e78db7 | 525 | dep->endpoint.desc = desc; |
c90bfaec | 526 | dep->comp_desc = comp_desc; |
72246da4 FB |
527 | dep->type = usb_endpoint_type(desc); |
528 | dep->flags |= DWC3_EP_ENABLED; | |
529 | ||
530 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
531 | reg |= DWC3_DALEPENA_EP(dep->number); | |
532 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
533 | ||
534 | if (!usb_endpoint_xfer_isoc(desc)) | |
535 | return 0; | |
536 | ||
537 | memset(&trb_link, 0, sizeof(trb_link)); | |
538 | ||
1d046793 | 539 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
540 | trb_st_hw = &dep->trb_pool[0]; |
541 | ||
f6bafc6a | 542 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
72246da4 | 543 | |
f6bafc6a FB |
544 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
545 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
546 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
547 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
548 | } |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
624407f9 SAS |
553 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); |
554 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) | |
72246da4 FB |
555 | { |
556 | struct dwc3_request *req; | |
557 | ||
624407f9 SAS |
558 | if (!list_empty(&dep->req_queued)) |
559 | dwc3_stop_active_transfer(dwc, dep->number); | |
560 | ||
72246da4 FB |
561 | while (!list_empty(&dep->request_list)) { |
562 | req = next_request(&dep->request_list); | |
563 | ||
624407f9 | 564 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 565 | } |
72246da4 FB |
566 | } |
567 | ||
568 | /** | |
569 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
570 | * @dep: the endpoint to disable | |
571 | * | |
624407f9 SAS |
572 | * This function also removes requests which are currently processed ny the |
573 | * hardware and those which are not yet scheduled. | |
574 | * Caller should take care of locking. | |
72246da4 | 575 | */ |
72246da4 FB |
576 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
577 | { | |
578 | struct dwc3 *dwc = dep->dwc; | |
579 | u32 reg; | |
580 | ||
624407f9 | 581 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
582 | |
583 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
584 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
585 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
586 | ||
879631aa | 587 | dep->stream_capable = false; |
f9c56cdd | 588 | dep->endpoint.desc = NULL; |
c90bfaec | 589 | dep->comp_desc = NULL; |
72246da4 | 590 | dep->type = 0; |
879631aa | 591 | dep->flags = 0; |
72246da4 FB |
592 | |
593 | return 0; | |
594 | } | |
595 | ||
596 | /* -------------------------------------------------------------------------- */ | |
597 | ||
598 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
599 | const struct usb_endpoint_descriptor *desc) | |
600 | { | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
605 | { | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
609 | /* -------------------------------------------------------------------------- */ | |
610 | ||
611 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
612 | const struct usb_endpoint_descriptor *desc) | |
613 | { | |
614 | struct dwc3_ep *dep; | |
615 | struct dwc3 *dwc; | |
616 | unsigned long flags; | |
617 | int ret; | |
618 | ||
619 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
620 | pr_debug("dwc3: invalid parameters\n"); | |
621 | return -EINVAL; | |
622 | } | |
623 | ||
624 | if (!desc->wMaxPacketSize) { | |
625 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
626 | return -EINVAL; | |
627 | } | |
628 | ||
629 | dep = to_dwc3_ep(ep); | |
630 | dwc = dep->dwc; | |
631 | ||
632 | switch (usb_endpoint_type(desc)) { | |
633 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 634 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
635 | break; |
636 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 637 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
638 | break; |
639 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 640 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
641 | break; |
642 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 643 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
644 | break; |
645 | default: | |
646 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
647 | } | |
648 | ||
649 | if (dep->flags & DWC3_EP_ENABLED) { | |
650 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
651 | dep->name); | |
652 | return 0; | |
653 | } | |
654 | ||
655 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); | |
656 | ||
657 | spin_lock_irqsave(&dwc->lock, flags); | |
c90bfaec | 658 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); |
72246da4 FB |
659 | spin_unlock_irqrestore(&dwc->lock, flags); |
660 | ||
661 | return ret; | |
662 | } | |
663 | ||
664 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
665 | { | |
666 | struct dwc3_ep *dep; | |
667 | struct dwc3 *dwc; | |
668 | unsigned long flags; | |
669 | int ret; | |
670 | ||
671 | if (!ep) { | |
672 | pr_debug("dwc3: invalid parameters\n"); | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
676 | dep = to_dwc3_ep(ep); | |
677 | dwc = dep->dwc; | |
678 | ||
679 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
680 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
681 | dep->name); | |
682 | return 0; | |
683 | } | |
684 | ||
685 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
686 | dep->number >> 1, | |
687 | (dep->number & 1) ? "in" : "out"); | |
688 | ||
689 | spin_lock_irqsave(&dwc->lock, flags); | |
690 | ret = __dwc3_gadget_ep_disable(dep); | |
691 | spin_unlock_irqrestore(&dwc->lock, flags); | |
692 | ||
693 | return ret; | |
694 | } | |
695 | ||
696 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
697 | gfp_t gfp_flags) | |
698 | { | |
699 | struct dwc3_request *req; | |
700 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
701 | struct dwc3 *dwc = dep->dwc; | |
702 | ||
703 | req = kzalloc(sizeof(*req), gfp_flags); | |
704 | if (!req) { | |
705 | dev_err(dwc->dev, "not enough memory\n"); | |
706 | return NULL; | |
707 | } | |
708 | ||
709 | req->epnum = dep->number; | |
710 | req->dep = dep; | |
72246da4 FB |
711 | |
712 | return &req->request; | |
713 | } | |
714 | ||
715 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
716 | struct usb_request *request) | |
717 | { | |
718 | struct dwc3_request *req = to_dwc3_request(request); | |
719 | ||
720 | kfree(req); | |
721 | } | |
722 | ||
c71fc37c FB |
723 | /** |
724 | * dwc3_prepare_one_trb - setup one TRB from one request | |
725 | * @dep: endpoint for which this request is prepared | |
726 | * @req: dwc3_request pointer | |
727 | */ | |
68e823e2 | 728 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb FB |
729 | struct dwc3_request *req, dma_addr_t dma, |
730 | unsigned length, unsigned last, unsigned chain) | |
c71fc37c | 731 | { |
eeb720fb | 732 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 733 | struct dwc3_trb *trb; |
c71fc37c FB |
734 | |
735 | unsigned int cur_slot; | |
736 | ||
eeb720fb FB |
737 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
738 | dep->name, req, (unsigned long long) dma, | |
739 | length, last ? " last" : "", | |
740 | chain ? " chain" : ""); | |
741 | ||
f6bafc6a | 742 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; |
c71fc37c FB |
743 | cur_slot = dep->free_slot; |
744 | dep->free_slot++; | |
745 | ||
746 | /* Skip the LINK-TRB on ISOC */ | |
747 | if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
16e78db7 | 748 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 749 | return; |
c71fc37c | 750 | |
eeb720fb FB |
751 | if (!req->trb) { |
752 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
753 | req->trb = trb; |
754 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
eeb720fb | 755 | } |
c71fc37c | 756 | |
f6bafc6a FB |
757 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
758 | trb->bpl = lower_32_bits(dma); | |
759 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 760 | |
16e78db7 | 761 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 762 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 763 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
764 | break; |
765 | ||
766 | case USB_ENDPOINT_XFER_ISOC: | |
f6bafc6a | 767 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
c71fc37c FB |
768 | |
769 | /* IOC every DWC3_TRB_NUM / 4 so we can refill */ | |
770 | if (!(cur_slot % (DWC3_TRB_NUM / 4))) | |
f6bafc6a | 771 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
c71fc37c FB |
772 | break; |
773 | ||
774 | case USB_ENDPOINT_XFER_BULK: | |
775 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 776 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
777 | break; |
778 | default: | |
779 | /* | |
780 | * This is only possible with faulty memory because we | |
781 | * checked it already :) | |
782 | */ | |
783 | BUG(); | |
784 | } | |
785 | ||
16e78db7 | 786 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
787 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
788 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
789 | } else { | |
790 | if (chain) | |
791 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
792 | ||
793 | if (last) | |
794 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
795 | } | |
c71fc37c | 796 | |
16e78db7 | 797 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 798 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 799 | |
f6bafc6a | 800 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
801 | } |
802 | ||
72246da4 FB |
803 | /* |
804 | * dwc3_prepare_trbs - setup TRBs from requests | |
805 | * @dep: endpoint for which requests are being prepared | |
806 | * @starting: true if the endpoint is idle and no requests are queued. | |
807 | * | |
1d046793 PZ |
808 | * The function goes through the requests list and sets up TRBs for the |
809 | * transfers. The function returns once there are no more TRBs available or | |
810 | * it runs out of requests. | |
72246da4 | 811 | */ |
68e823e2 | 812 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 813 | { |
68e823e2 | 814 | struct dwc3_request *req, *n; |
72246da4 | 815 | u32 trbs_left; |
8d62cd65 | 816 | u32 max; |
c71fc37c | 817 | unsigned int last_one = 0; |
72246da4 FB |
818 | |
819 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
820 | ||
821 | /* the first request must not be queued */ | |
822 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 823 | |
8d62cd65 | 824 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 825 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
826 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
827 | if (trbs_left > max) | |
828 | trbs_left = max; | |
829 | } | |
830 | ||
72246da4 | 831 | /* |
1d046793 PZ |
832 | * If busy & slot are equal than it is either full or empty. If we are |
833 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
834 | * full and don't do anything |
835 | */ | |
836 | if (!trbs_left) { | |
837 | if (!starting) | |
68e823e2 | 838 | return; |
72246da4 FB |
839 | trbs_left = DWC3_TRB_NUM; |
840 | /* | |
841 | * In case we start from scratch, we queue the ISOC requests | |
842 | * starting from slot 1. This is done because we use ring | |
843 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 844 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
845 | * after the first request so we start at slot 1 and have |
846 | * 7 requests proceed before we hit the first IOC. | |
847 | * Other transfer types don't use the ring buffer and are | |
848 | * processed from the first TRB until the last one. Since we | |
849 | * don't wrap around we have to start at the beginning. | |
850 | */ | |
16e78db7 | 851 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
852 | dep->busy_slot = 1; |
853 | dep->free_slot = 1; | |
854 | } else { | |
855 | dep->busy_slot = 0; | |
856 | dep->free_slot = 0; | |
857 | } | |
858 | } | |
859 | ||
860 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 861 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 862 | return; |
72246da4 FB |
863 | |
864 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
865 | unsigned length; |
866 | dma_addr_t dma; | |
72246da4 | 867 | |
eeb720fb FB |
868 | if (req->request.num_mapped_sgs > 0) { |
869 | struct usb_request *request = &req->request; | |
870 | struct scatterlist *sg = request->sg; | |
871 | struct scatterlist *s; | |
872 | int i; | |
72246da4 | 873 | |
eeb720fb FB |
874 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
875 | unsigned chain = true; | |
72246da4 | 876 | |
eeb720fb FB |
877 | length = sg_dma_len(s); |
878 | dma = sg_dma_address(s); | |
72246da4 | 879 | |
1d046793 PZ |
880 | if (i == (request->num_mapped_sgs - 1) || |
881 | sg_is_last(s)) { | |
eeb720fb FB |
882 | last_one = true; |
883 | chain = false; | |
884 | } | |
72246da4 | 885 | |
eeb720fb FB |
886 | trbs_left--; |
887 | if (!trbs_left) | |
888 | last_one = true; | |
72246da4 | 889 | |
eeb720fb FB |
890 | if (last_one) |
891 | chain = false; | |
72246da4 | 892 | |
eeb720fb FB |
893 | dwc3_prepare_one_trb(dep, req, dma, length, |
894 | last_one, chain); | |
72246da4 | 895 | |
eeb720fb FB |
896 | if (last_one) |
897 | break; | |
898 | } | |
72246da4 | 899 | } else { |
eeb720fb FB |
900 | dma = req->request.dma; |
901 | length = req->request.length; | |
902 | trbs_left--; | |
72246da4 | 903 | |
eeb720fb FB |
904 | if (!trbs_left) |
905 | last_one = 1; | |
879631aa | 906 | |
eeb720fb FB |
907 | /* Is this the last request? */ |
908 | if (list_is_last(&req->list, &dep->request_list)) | |
909 | last_one = 1; | |
72246da4 | 910 | |
eeb720fb FB |
911 | dwc3_prepare_one_trb(dep, req, dma, length, |
912 | last_one, false); | |
72246da4 | 913 | |
eeb720fb FB |
914 | if (last_one) |
915 | break; | |
72246da4 | 916 | } |
72246da4 | 917 | } |
72246da4 FB |
918 | } |
919 | ||
920 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
921 | int start_new) | |
922 | { | |
923 | struct dwc3_gadget_ep_cmd_params params; | |
924 | struct dwc3_request *req; | |
925 | struct dwc3 *dwc = dep->dwc; | |
926 | int ret; | |
927 | u32 cmd; | |
928 | ||
929 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
930 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
931 | return -EBUSY; | |
932 | } | |
933 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
934 | ||
935 | /* | |
936 | * If we are getting here after a short-out-packet we don't enqueue any | |
937 | * new requests as we try to set the IOC bit only on the last request. | |
938 | */ | |
939 | if (start_new) { | |
940 | if (list_empty(&dep->req_queued)) | |
941 | dwc3_prepare_trbs(dep, start_new); | |
942 | ||
943 | /* req points to the first request which will be sent */ | |
944 | req = next_request(&dep->req_queued); | |
945 | } else { | |
68e823e2 FB |
946 | dwc3_prepare_trbs(dep, start_new); |
947 | ||
72246da4 | 948 | /* |
1d046793 | 949 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 950 | */ |
68e823e2 | 951 | req = next_request(&dep->req_queued); |
72246da4 FB |
952 | } |
953 | if (!req) { | |
954 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
955 | return 0; | |
956 | } | |
957 | ||
958 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
959 | params.param0 = upper_32_bits(req->trb_dma); |
960 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 FB |
961 | |
962 | if (start_new) | |
963 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
964 | else | |
965 | cmd = DWC3_DEPCMD_UPDATETRANSFER; | |
966 | ||
967 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
968 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
969 | if (ret < 0) { | |
970 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
971 | ||
972 | /* | |
973 | * FIXME we need to iterate over the list of requests | |
974 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 975 | * requests instead of what we do now. |
72246da4 | 976 | */ |
0fc9a1be FB |
977 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
978 | req->direction); | |
72246da4 FB |
979 | list_del(&req->list); |
980 | return ret; | |
981 | } | |
982 | ||
983 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 984 | |
f898ae09 PZ |
985 | if (start_new) { |
986 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, | |
987 | dep->number); | |
988 | WARN_ON_ONCE(!dep->res_trans_idx); | |
989 | } | |
25b8ff68 | 990 | |
72246da4 FB |
991 | return 0; |
992 | } | |
993 | ||
994 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) | |
995 | { | |
0fc9a1be FB |
996 | struct dwc3 *dwc = dep->dwc; |
997 | int ret; | |
998 | ||
72246da4 FB |
999 | req->request.actual = 0; |
1000 | req->request.status = -EINPROGRESS; | |
1001 | req->direction = dep->direction; | |
1002 | req->epnum = dep->number; | |
1003 | ||
1004 | /* | |
1005 | * We only add to our list of requests now and | |
1006 | * start consuming the list once we get XferNotReady | |
1007 | * IRQ. | |
1008 | * | |
1009 | * That way, we avoid doing anything that we don't need | |
1010 | * to do now and defer it until the point we receive a | |
1011 | * particular token from the Host side. | |
1012 | * | |
1013 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 1014 | * many NAKs. |
72246da4 | 1015 | */ |
0fc9a1be FB |
1016 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
1017 | dep->direction); | |
1018 | if (ret) | |
1019 | return ret; | |
1020 | ||
72246da4 FB |
1021 | list_add_tail(&req->list, &dep->request_list); |
1022 | ||
23063b37 | 1023 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY)) |
f898ae09 PZ |
1024 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
1025 | ||
72246da4 | 1026 | /* |
f898ae09 | 1027 | * There are two special cases: |
72246da4 | 1028 | * |
f898ae09 PZ |
1029 | * 1. XferNotReady with empty list of requests. We need to kick the |
1030 | * transfer here in that situation, otherwise we will be NAKing | |
1031 | * forever. If we get XferNotReady before gadget driver has a | |
1032 | * chance to queue a request, we will ACK the IRQ but won't be | |
1033 | * able to receive the data until the next request is queued. | |
1034 | * The following code is handling exactly that. | |
72246da4 | 1035 | * |
f898ae09 PZ |
1036 | * 2. XferInProgress on Isoc EP with an active transfer. We need to |
1037 | * kick the transfer here after queuing a request, otherwise the | |
1038 | * core may not see the modified TRB(s). | |
72246da4 FB |
1039 | */ |
1040 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f898ae09 PZ |
1041 | int ret; |
1042 | int start_trans = 1; | |
1043 | u8 trans_idx = dep->res_trans_idx; | |
72246da4 | 1044 | |
16e78db7 | 1045 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
f898ae09 | 1046 | (dep->flags & DWC3_EP_BUSY)) { |
72246da4 | 1047 | start_trans = 0; |
f898ae09 PZ |
1048 | WARN_ON_ONCE(!trans_idx); |
1049 | } else { | |
1050 | trans_idx = 0; | |
1051 | } | |
72246da4 | 1052 | |
f898ae09 | 1053 | ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans); |
72246da4 FB |
1054 | if (ret && ret != -EBUSY) { |
1055 | struct dwc3 *dwc = dep->dwc; | |
1056 | ||
1057 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1058 | dep->name); | |
1059 | } | |
a0925324 | 1060 | } |
72246da4 FB |
1061 | |
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1066 | gfp_t gfp_flags) | |
1067 | { | |
1068 | struct dwc3_request *req = to_dwc3_request(request); | |
1069 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1070 | struct dwc3 *dwc = dep->dwc; | |
1071 | ||
1072 | unsigned long flags; | |
1073 | ||
1074 | int ret; | |
1075 | ||
16e78db7 | 1076 | if (!dep->endpoint.desc) { |
72246da4 FB |
1077 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1078 | request, ep->name); | |
1079 | return -ESHUTDOWN; | |
1080 | } | |
1081 | ||
1082 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1083 | request, ep->name, request->length); | |
1084 | ||
1085 | spin_lock_irqsave(&dwc->lock, flags); | |
1086 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1087 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1088 | ||
1089 | return ret; | |
1090 | } | |
1091 | ||
1092 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1093 | struct usb_request *request) | |
1094 | { | |
1095 | struct dwc3_request *req = to_dwc3_request(request); | |
1096 | struct dwc3_request *r = NULL; | |
1097 | ||
1098 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1099 | struct dwc3 *dwc = dep->dwc; | |
1100 | ||
1101 | unsigned long flags; | |
1102 | int ret = 0; | |
1103 | ||
1104 | spin_lock_irqsave(&dwc->lock, flags); | |
1105 | ||
1106 | list_for_each_entry(r, &dep->request_list, list) { | |
1107 | if (r == req) | |
1108 | break; | |
1109 | } | |
1110 | ||
1111 | if (r != req) { | |
1112 | list_for_each_entry(r, &dep->req_queued, list) { | |
1113 | if (r == req) | |
1114 | break; | |
1115 | } | |
1116 | if (r == req) { | |
1117 | /* wait until it is processed */ | |
1118 | dwc3_stop_active_transfer(dwc, dep->number); | |
1119 | goto out0; | |
1120 | } | |
1121 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1122 | request, ep->name); | |
1123 | ret = -EINVAL; | |
1124 | goto out0; | |
1125 | } | |
1126 | ||
1127 | /* giveback the request */ | |
1128 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1129 | ||
1130 | out0: | |
1131 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1132 | ||
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) | |
1137 | { | |
1138 | struct dwc3_gadget_ep_cmd_params params; | |
1139 | struct dwc3 *dwc = dep->dwc; | |
1140 | int ret; | |
1141 | ||
1142 | memset(¶ms, 0x00, sizeof(params)); | |
1143 | ||
1144 | if (value) { | |
0b7836a9 FB |
1145 | if (dep->number == 0 || dep->number == 1) { |
1146 | /* | |
1147 | * Whenever EP0 is stalled, we will restart | |
1148 | * the state machine, thus moving back to | |
1149 | * Setup Phase | |
1150 | */ | |
1151 | dwc->ep0state = EP0_SETUP_PHASE; | |
1152 | } | |
72246da4 FB |
1153 | |
1154 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1155 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1156 | if (ret) | |
1157 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1158 | value ? "set" : "clear", | |
1159 | dep->name); | |
1160 | else | |
1161 | dep->flags |= DWC3_EP_STALL; | |
1162 | } else { | |
5275455a PZ |
1163 | if (dep->flags & DWC3_EP_WEDGE) |
1164 | return 0; | |
1165 | ||
72246da4 FB |
1166 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1167 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1168 | if (ret) | |
1169 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1170 | value ? "set" : "clear", | |
1171 | dep->name); | |
1172 | else | |
1173 | dep->flags &= ~DWC3_EP_STALL; | |
1174 | } | |
5275455a | 1175 | |
72246da4 FB |
1176 | return ret; |
1177 | } | |
1178 | ||
1179 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1180 | { | |
1181 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1182 | struct dwc3 *dwc = dep->dwc; | |
1183 | ||
1184 | unsigned long flags; | |
1185 | ||
1186 | int ret; | |
1187 | ||
1188 | spin_lock_irqsave(&dwc->lock, flags); | |
1189 | ||
16e78db7 | 1190 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1191 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1192 | ret = -EINVAL; | |
1193 | goto out; | |
1194 | } | |
1195 | ||
1196 | ret = __dwc3_gadget_ep_set_halt(dep, value); | |
1197 | out: | |
1198 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1199 | ||
1200 | return ret; | |
1201 | } | |
1202 | ||
1203 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1204 | { | |
1205 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1206 | struct dwc3 *dwc = dep->dwc; |
1207 | unsigned long flags; | |
72246da4 | 1208 | |
249a4569 | 1209 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1210 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1211 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1212 | |
5275455a | 1213 | return dwc3_gadget_ep_set_halt(ep, 1); |
72246da4 FB |
1214 | } |
1215 | ||
1216 | /* -------------------------------------------------------------------------- */ | |
1217 | ||
1218 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1219 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1220 | .bDescriptorType = USB_DT_ENDPOINT, | |
1221 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1222 | }; | |
1223 | ||
1224 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1225 | .enable = dwc3_gadget_ep0_enable, | |
1226 | .disable = dwc3_gadget_ep0_disable, | |
1227 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1228 | .free_request = dwc3_gadget_ep_free_request, | |
1229 | .queue = dwc3_gadget_ep0_queue, | |
1230 | .dequeue = dwc3_gadget_ep_dequeue, | |
1231 | .set_halt = dwc3_gadget_ep_set_halt, | |
1232 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1233 | }; | |
1234 | ||
1235 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1236 | .enable = dwc3_gadget_ep_enable, | |
1237 | .disable = dwc3_gadget_ep_disable, | |
1238 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1239 | .free_request = dwc3_gadget_ep_free_request, | |
1240 | .queue = dwc3_gadget_ep_queue, | |
1241 | .dequeue = dwc3_gadget_ep_dequeue, | |
1242 | .set_halt = dwc3_gadget_ep_set_halt, | |
1243 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1244 | }; | |
1245 | ||
1246 | /* -------------------------------------------------------------------------- */ | |
1247 | ||
1248 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1249 | { | |
1250 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1251 | u32 reg; | |
1252 | ||
1253 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1254 | return DWC3_DSTS_SOFFN(reg); | |
1255 | } | |
1256 | ||
1257 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1258 | { | |
1259 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1260 | ||
1261 | unsigned long timeout; | |
1262 | unsigned long flags; | |
1263 | ||
1264 | u32 reg; | |
1265 | ||
1266 | int ret = 0; | |
1267 | ||
1268 | u8 link_state; | |
1269 | u8 speed; | |
1270 | ||
1271 | spin_lock_irqsave(&dwc->lock, flags); | |
1272 | ||
1273 | /* | |
1274 | * According to the Databook Remote wakeup request should | |
1275 | * be issued only when the device is in early suspend state. | |
1276 | * | |
1277 | * We can check that via USB Link State bits in DSTS register. | |
1278 | */ | |
1279 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1280 | ||
1281 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1282 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1283 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1284 | ret = -EINVAL; | |
1285 | goto out; | |
1286 | } | |
1287 | ||
1288 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1289 | ||
1290 | switch (link_state) { | |
1291 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1292 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1293 | break; | |
1294 | default: | |
1295 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1296 | link_state); | |
1297 | ret = -EINVAL; | |
1298 | goto out; | |
1299 | } | |
1300 | ||
8598bde7 FB |
1301 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1302 | if (ret < 0) { | |
1303 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1304 | goto out; | |
1305 | } | |
72246da4 | 1306 | |
802fde98 PZ |
1307 | /* Recent versions do this automatically */ |
1308 | if (dwc->revision < DWC3_REVISION_194A) { | |
1309 | /* write zeroes to Link Change Request */ | |
fcc023c7 | 1310 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
802fde98 PZ |
1311 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; |
1312 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1313 | } | |
72246da4 | 1314 | |
1d046793 | 1315 | /* poll until Link State changes to ON */ |
72246da4 FB |
1316 | timeout = jiffies + msecs_to_jiffies(100); |
1317 | ||
1d046793 | 1318 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1319 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1320 | ||
1321 | /* in HS, means ON */ | |
1322 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1323 | break; | |
1324 | } | |
1325 | ||
1326 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1327 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1328 | ret = -EINVAL; | |
1329 | } | |
1330 | ||
1331 | out: | |
1332 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1333 | ||
1334 | return ret; | |
1335 | } | |
1336 | ||
1337 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1338 | int is_selfpowered) | |
1339 | { | |
1340 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1341 | unsigned long flags; |
72246da4 | 1342 | |
249a4569 | 1343 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1344 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1345 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) | |
1351 | { | |
1352 | u32 reg; | |
61d58242 | 1353 | u32 timeout = 500; |
72246da4 FB |
1354 | |
1355 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 | 1356 | if (is_on) { |
802fde98 PZ |
1357 | if (dwc->revision <= DWC3_REVISION_187A) { |
1358 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1359 | reg |= DWC3_DCTL_TRGTULST_RX_DET; | |
1360 | } | |
1361 | ||
1362 | if (dwc->revision >= DWC3_REVISION_194A) | |
1363 | reg &= ~DWC3_DCTL_KEEP_CONNECT; | |
1364 | reg |= DWC3_DCTL_RUN_STOP; | |
8db7ed15 | 1365 | } else { |
72246da4 | 1366 | reg &= ~DWC3_DCTL_RUN_STOP; |
8db7ed15 | 1367 | } |
72246da4 FB |
1368 | |
1369 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1370 | ||
1371 | do { | |
1372 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1373 | if (is_on) { | |
1374 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1375 | break; | |
1376 | } else { | |
1377 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1378 | break; | |
1379 | } | |
72246da4 FB |
1380 | timeout--; |
1381 | if (!timeout) | |
1382 | break; | |
61d58242 | 1383 | udelay(1); |
72246da4 FB |
1384 | } while (1); |
1385 | ||
1386 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1387 | dwc->gadget_driver | |
1388 | ? dwc->gadget_driver->function : "no-function", | |
1389 | is_on ? "connect" : "disconnect"); | |
1390 | } | |
1391 | ||
1392 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1393 | { | |
1394 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1395 | unsigned long flags; | |
1396 | ||
1397 | is_on = !!is_on; | |
1398 | ||
1399 | spin_lock_irqsave(&dwc->lock, flags); | |
1400 | dwc3_gadget_run_stop(dwc, is_on); | |
1401 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static int dwc3_gadget_start(struct usb_gadget *g, | |
1407 | struct usb_gadget_driver *driver) | |
1408 | { | |
1409 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1410 | struct dwc3_ep *dep; | |
1411 | unsigned long flags; | |
1412 | int ret = 0; | |
1413 | u32 reg; | |
1414 | ||
1415 | spin_lock_irqsave(&dwc->lock, flags); | |
1416 | ||
1417 | if (dwc->gadget_driver) { | |
1418 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1419 | dwc->gadget.name, | |
1420 | dwc->gadget_driver->driver.name); | |
1421 | ret = -EBUSY; | |
1422 | goto err0; | |
1423 | } | |
1424 | ||
1425 | dwc->gadget_driver = driver; | |
1426 | dwc->gadget.dev.driver = &driver->driver; | |
1427 | ||
72246da4 FB |
1428 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1429 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1430 | |
1431 | /** | |
1432 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1433 | * which would cause metastability state on Run/Stop | |
1434 | * bit if we try to force the IP to USB2-only mode. | |
1435 | * | |
1436 | * Because of that, we cannot configure the IP to any | |
1437 | * speed other than the SuperSpeed | |
1438 | * | |
1439 | * Refers to: | |
1440 | * | |
1441 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1442 | * USB 2.0 Mode | |
1443 | */ | |
1444 | if (dwc->revision < DWC3_REVISION_220A) | |
1445 | reg |= DWC3_DCFG_SUPERSPEED; | |
1446 | else | |
1447 | reg |= dwc->maximum_speed; | |
72246da4 FB |
1448 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1449 | ||
b23c8439 PZ |
1450 | dwc->start_config_issued = false; |
1451 | ||
72246da4 FB |
1452 | /* Start with SuperSpeed Default */ |
1453 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1454 | ||
1455 | dep = dwc->eps[0]; | |
c90bfaec | 1456 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
1457 | if (ret) { |
1458 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1459 | goto err0; | |
1460 | } | |
1461 | ||
1462 | dep = dwc->eps[1]; | |
c90bfaec | 1463 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
1464 | if (ret) { |
1465 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1466 | goto err1; | |
1467 | } | |
1468 | ||
1469 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1470 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1471 | dwc3_ep0_out_start(dwc); |
1472 | ||
1473 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1474 | ||
1475 | return 0; | |
1476 | ||
1477 | err1: | |
1478 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1479 | ||
1480 | err0: | |
1481 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1482 | ||
1483 | return ret; | |
1484 | } | |
1485 | ||
1486 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1487 | struct usb_gadget_driver *driver) | |
1488 | { | |
1489 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1490 | unsigned long flags; | |
1491 | ||
1492 | spin_lock_irqsave(&dwc->lock, flags); | |
1493 | ||
1494 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1495 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1496 | ||
1497 | dwc->gadget_driver = NULL; | |
1498 | dwc->gadget.dev.driver = NULL; | |
1499 | ||
1500 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1501 | ||
1502 | return 0; | |
1503 | } | |
802fde98 | 1504 | |
72246da4 FB |
1505 | static const struct usb_gadget_ops dwc3_gadget_ops = { |
1506 | .get_frame = dwc3_gadget_get_frame, | |
1507 | .wakeup = dwc3_gadget_wakeup, | |
1508 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1509 | .pullup = dwc3_gadget_pullup, | |
1510 | .udc_start = dwc3_gadget_start, | |
1511 | .udc_stop = dwc3_gadget_stop, | |
1512 | }; | |
1513 | ||
1514 | /* -------------------------------------------------------------------------- */ | |
1515 | ||
1516 | static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) | |
1517 | { | |
1518 | struct dwc3_ep *dep; | |
1519 | u8 epnum; | |
1520 | ||
1521 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1522 | ||
1523 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1524 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); | |
1525 | if (!dep) { | |
1526 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1527 | epnum); | |
1528 | return -ENOMEM; | |
1529 | } | |
1530 | ||
1531 | dep->dwc = dwc; | |
1532 | dep->number = epnum; | |
1533 | dwc->eps[epnum] = dep; | |
1534 | ||
1535 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1536 | (epnum & 1) ? "in" : "out"); | |
1537 | dep->endpoint.name = dep->name; | |
1538 | dep->direction = (epnum & 1); | |
1539 | ||
1540 | if (epnum == 0 || epnum == 1) { | |
1541 | dep->endpoint.maxpacket = 512; | |
1542 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
1543 | if (!epnum) | |
1544 | dwc->gadget.ep0 = &dep->endpoint; | |
1545 | } else { | |
1546 | int ret; | |
1547 | ||
1548 | dep->endpoint.maxpacket = 1024; | |
12d36c16 | 1549 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1550 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1551 | list_add_tail(&dep->endpoint.ep_list, | |
1552 | &dwc->gadget.ep_list); | |
1553 | ||
1554 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1555 | if (ret) |
72246da4 | 1556 | return ret; |
72246da4 | 1557 | } |
25b8ff68 | 1558 | |
72246da4 FB |
1559 | INIT_LIST_HEAD(&dep->request_list); |
1560 | INIT_LIST_HEAD(&dep->req_queued); | |
1561 | } | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
1566 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
1567 | { | |
1568 | struct dwc3_ep *dep; | |
1569 | u8 epnum; | |
1570 | ||
1571 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1572 | dep = dwc->eps[epnum]; | |
1573 | dwc3_free_trb_pool(dep); | |
1574 | ||
1575 | if (epnum != 0 && epnum != 1) | |
1576 | list_del(&dep->endpoint.ep_list); | |
1577 | ||
1578 | kfree(dep); | |
1579 | } | |
1580 | } | |
1581 | ||
1582 | static void dwc3_gadget_release(struct device *dev) | |
1583 | { | |
1584 | dev_dbg(dev, "%s\n", __func__); | |
1585 | } | |
1586 | ||
1587 | /* -------------------------------------------------------------------------- */ | |
1588 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1589 | const struct dwc3_event_depevt *event, int status) | |
1590 | { | |
1591 | struct dwc3_request *req; | |
f6bafc6a | 1592 | struct dwc3_trb *trb; |
72246da4 FB |
1593 | unsigned int count; |
1594 | unsigned int s_pkt = 0; | |
1595 | ||
1596 | do { | |
1597 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1598 | if (!req) { |
1599 | WARN_ON_ONCE(1); | |
1600 | return 1; | |
1601 | } | |
72246da4 | 1602 | |
f6bafc6a | 1603 | trb = req->trb; |
72246da4 | 1604 | |
f6bafc6a | 1605 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
0d2f4758 SAS |
1606 | /* |
1607 | * We continue despite the error. There is not much we | |
1d046793 PZ |
1608 | * can do. If we don't clean it up we loop forever. If |
1609 | * we skip the TRB then it gets overwritten after a | |
1610 | * while since we use them in a ring buffer. A BUG() | |
1611 | * would help. Lets hope that if this occurs, someone | |
0d2f4758 SAS |
1612 | * fixes the root cause instead of looking away :) |
1613 | */ | |
72246da4 FB |
1614 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", |
1615 | dep->name, req->trb); | |
f6bafc6a | 1616 | count = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 FB |
1617 | |
1618 | if (dep->direction) { | |
1619 | if (count) { | |
1620 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1621 | dep->name); | |
1622 | status = -ECONNRESET; | |
1623 | } | |
1624 | } else { | |
1625 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1626 | s_pkt = 1; | |
1627 | } | |
1628 | ||
1629 | /* | |
1630 | * We assume here we will always receive the entire data block | |
1631 | * which we should receive. Meaning, if we program RX to | |
1632 | * receive 4K but we receive only 2K, we assume that's all we | |
1633 | * should receive and we simply bounce the request back to the | |
1634 | * gadget driver for further processing. | |
1635 | */ | |
1636 | req->request.actual += req->request.length - count; | |
1637 | dwc3_gadget_giveback(dep, req, status); | |
1638 | if (s_pkt) | |
1639 | break; | |
f6bafc6a FB |
1640 | if ((event->status & DEPEVT_STATUS_LST) && |
1641 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
72246da4 | 1642 | break; |
f6bafc6a FB |
1643 | if ((event->status & DEPEVT_STATUS_IOC) && |
1644 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
72246da4 FB |
1645 | break; |
1646 | } while (1); | |
1647 | ||
f6bafc6a FB |
1648 | if ((event->status & DEPEVT_STATUS_IOC) && |
1649 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
72246da4 FB |
1650 | return 0; |
1651 | return 1; | |
1652 | } | |
1653 | ||
1654 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
1655 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event, | |
1656 | int start_new) | |
1657 | { | |
1658 | unsigned status = 0; | |
1659 | int clean_busy; | |
1660 | ||
1661 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1662 | status = -ECONNRESET; | |
1663 | ||
1d046793 | 1664 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1665 | if (clean_busy) |
72246da4 | 1666 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1667 | |
1668 | /* | |
1669 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1670 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1671 | */ | |
1672 | if (dwc->revision < DWC3_REVISION_183A) { | |
1673 | u32 reg; | |
1674 | int i; | |
1675 | ||
1676 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
1677 | struct dwc3_ep *dep = dwc->eps[i]; | |
1678 | ||
1679 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1680 | continue; | |
1681 | ||
1682 | if (!list_empty(&dep->req_queued)) | |
1683 | return; | |
1684 | } | |
1685 | ||
1686 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1687 | reg |= dwc->u1u2; | |
1688 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1689 | ||
1690 | dwc->u1u2 = 0; | |
1691 | } | |
72246da4 FB |
1692 | } |
1693 | ||
1694 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1695 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1696 | { | |
9bafa56c | 1697 | u32 uf, mask; |
72246da4 FB |
1698 | |
1699 | if (list_empty(&dep->request_list)) { | |
1700 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1701 | dep->name); | |
1702 | return; | |
1703 | } | |
1704 | ||
9bafa56c PZ |
1705 | mask = ~(dep->interval - 1); |
1706 | uf = event->parameters & mask; | |
1707 | /* 4 micro frames in the future */ | |
1708 | uf += dep->interval * 4; | |
72246da4 FB |
1709 | |
1710 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1711 | } | |
1712 | ||
1713 | static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, | |
1714 | const struct dwc3_event_depevt *event) | |
1715 | { | |
1716 | struct dwc3 *dwc = dep->dwc; | |
1717 | struct dwc3_event_depevt mod_ev = *event; | |
1718 | ||
1719 | /* | |
1d046793 PZ |
1720 | * We were asked to remove one request. It is possible that this |
1721 | * request and a few others were started together and have the same | |
72246da4 FB |
1722 | * transfer index. Since we stopped the complete endpoint we don't |
1723 | * know how many requests were already completed (and not yet) | |
1724 | * reported and how could be done (later). We purge them all until | |
1725 | * the end of the list. | |
1726 | */ | |
1727 | mod_ev.status = DEPEVT_STATUS_LST; | |
1728 | dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); | |
1729 | dep->flags &= ~DWC3_EP_BUSY; | |
1d046793 | 1730 | /* pending requests are ignored and are queued on XferNotReady */ |
72246da4 FB |
1731 | } |
1732 | ||
1733 | static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, | |
1734 | const struct dwc3_event_depevt *event) | |
1735 | { | |
1736 | u32 param = event->parameters; | |
1737 | u32 cmd_type = (param >> 8) & ((1 << 5) - 1); | |
1738 | ||
1739 | switch (cmd_type) { | |
1740 | case DWC3_DEPCMD_ENDTRANSFER: | |
1741 | dwc3_process_ep_cmd_complete(dep, event); | |
1742 | break; | |
1743 | case DWC3_DEPCMD_STARTTRANSFER: | |
1744 | dep->res_trans_idx = param & 0x7f; | |
1745 | break; | |
1746 | default: | |
1747 | printk(KERN_ERR "%s() unknown /unexpected type: %d\n", | |
1748 | __func__, cmd_type); | |
1749 | break; | |
1750 | }; | |
1751 | } | |
1752 | ||
1753 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, | |
1754 | const struct dwc3_event_depevt *event) | |
1755 | { | |
1756 | struct dwc3_ep *dep; | |
1757 | u8 epnum = event->endpoint_number; | |
1758 | ||
1759 | dep = dwc->eps[epnum]; | |
1760 | ||
1761 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, | |
1762 | dwc3_ep_event_string(event->endpoint_event)); | |
1763 | ||
1764 | if (epnum == 0 || epnum == 1) { | |
1765 | dwc3_ep0_interrupt(dwc, event); | |
1766 | return; | |
1767 | } | |
1768 | ||
1769 | switch (event->endpoint_event) { | |
1770 | case DWC3_DEPEVT_XFERCOMPLETE: | |
c2df85ca PZ |
1771 | dep->res_trans_idx = 0; |
1772 | ||
16e78db7 | 1773 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1774 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
1775 | dep->name); | |
1776 | return; | |
1777 | } | |
1778 | ||
1779 | dwc3_endpoint_transfer_complete(dwc, dep, event, 1); | |
1780 | break; | |
1781 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 1782 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1783 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
1784 | dep->name); | |
1785 | return; | |
1786 | } | |
1787 | ||
1788 | dwc3_endpoint_transfer_complete(dwc, dep, event, 0); | |
1789 | break; | |
1790 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 1791 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1792 | dwc3_gadget_start_isoc(dwc, dep, event); |
1793 | } else { | |
1794 | int ret; | |
1795 | ||
1796 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
1797 | dep->name, event->status & |
1798 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
1799 | ? "Transfer Active" |
1800 | : "Transfer Not Active"); | |
1801 | ||
1802 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
1803 | if (!ret || ret == -EBUSY) | |
1804 | return; | |
1805 | ||
1806 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1807 | dep->name); | |
1808 | } | |
1809 | ||
879631aa FB |
1810 | break; |
1811 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 1812 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
1813 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
1814 | dep->name); | |
1815 | return; | |
1816 | } | |
1817 | ||
1818 | switch (event->status) { | |
1819 | case DEPEVT_STREAMEVT_FOUND: | |
1820 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
1821 | event->parameters); | |
1822 | ||
1823 | break; | |
1824 | case DEPEVT_STREAMEVT_NOTFOUND: | |
1825 | /* FALLTHROUGH */ | |
1826 | default: | |
1827 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
1828 | } | |
72246da4 FB |
1829 | break; |
1830 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1831 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
1832 | break; | |
72246da4 FB |
1833 | case DWC3_DEPEVT_EPCMDCMPLT: |
1834 | dwc3_ep_cmd_compl(dep, event); | |
1835 | break; | |
1836 | } | |
1837 | } | |
1838 | ||
1839 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
1840 | { | |
1841 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
1842 | spin_unlock(&dwc->lock); | |
1843 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
1844 | spin_lock(&dwc->lock); | |
1845 | } | |
1846 | } | |
1847 | ||
1848 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) | |
1849 | { | |
1850 | struct dwc3_ep *dep; | |
1851 | struct dwc3_gadget_ep_cmd_params params; | |
1852 | u32 cmd; | |
1853 | int ret; | |
1854 | ||
1855 | dep = dwc->eps[epnum]; | |
1856 | ||
624407f9 | 1857 | WARN_ON(!dep->res_trans_idx); |
72246da4 FB |
1858 | if (dep->res_trans_idx) { |
1859 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
1860 | cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; | |
1861 | cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); | |
1862 | memset(¶ms, 0, sizeof(params)); | |
1863 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
1864 | WARN_ON_ONCE(ret); | |
a1ae9be5 | 1865 | dep->res_trans_idx = 0; |
72246da4 FB |
1866 | } |
1867 | } | |
1868 | ||
1869 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
1870 | { | |
1871 | u32 epnum; | |
1872 | ||
1873 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1874 | struct dwc3_ep *dep; | |
1875 | ||
1876 | dep = dwc->eps[epnum]; | |
1877 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1878 | continue; | |
1879 | ||
624407f9 | 1880 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
1881 | } |
1882 | } | |
1883 | ||
1884 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
1885 | { | |
1886 | u32 epnum; | |
1887 | ||
1888 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1889 | struct dwc3_ep *dep; | |
1890 | struct dwc3_gadget_ep_cmd_params params; | |
1891 | int ret; | |
1892 | ||
1893 | dep = dwc->eps[epnum]; | |
1894 | ||
1895 | if (!(dep->flags & DWC3_EP_STALL)) | |
1896 | continue; | |
1897 | ||
1898 | dep->flags &= ~DWC3_EP_STALL; | |
1899 | ||
1900 | memset(¶ms, 0, sizeof(params)); | |
1901 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1902 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1903 | WARN_ON_ONCE(ret); | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
1908 | { | |
1909 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
1910 | #if 0 | |
1911 | XXX | |
1912 | U1/U2 is powersave optimization. Skip it for now. Anyway we need to | |
1913 | enable it before we can disable it. | |
1914 | ||
1915 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1916 | reg &= ~DWC3_DCTL_INITU1ENA; | |
1917 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1918 | ||
1919 | reg &= ~DWC3_DCTL_INITU2ENA; | |
1920 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1921 | #endif | |
1922 | ||
1923 | dwc3_stop_active_transfers(dwc); | |
1924 | dwc3_disconnect_gadget(dwc); | |
b23c8439 | 1925 | dwc->start_config_issued = false; |
72246da4 FB |
1926 | |
1927 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 1928 | dwc->setup_packet_pending = false; |
72246da4 FB |
1929 | } |
1930 | ||
d7a46a8d | 1931 | static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) |
72246da4 FB |
1932 | { |
1933 | u32 reg; | |
1934 | ||
1935 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
1936 | ||
d7a46a8d | 1937 | if (suspend) |
72246da4 | 1938 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; |
d7a46a8d PZ |
1939 | else |
1940 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; | |
72246da4 FB |
1941 | |
1942 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
1943 | } | |
1944 | ||
d7a46a8d | 1945 | static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) |
72246da4 FB |
1946 | { |
1947 | u32 reg; | |
1948 | ||
1949 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1950 | ||
d7a46a8d | 1951 | if (suspend) |
72246da4 | 1952 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; |
d7a46a8d PZ |
1953 | else |
1954 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
72246da4 FB |
1955 | |
1956 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1957 | } | |
1958 | ||
1959 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) | |
1960 | { | |
1961 | u32 reg; | |
1962 | ||
1963 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
1964 | ||
df62df56 FB |
1965 | /* |
1966 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
1967 | * would cause a missing Disconnect Event if there's a | |
1968 | * pending Setup Packet in the FIFO. | |
1969 | * | |
1970 | * There's no suggested workaround on the official Bug | |
1971 | * report, which states that "unless the driver/application | |
1972 | * is doing any special handling of a disconnect event, | |
1973 | * there is no functional issue". | |
1974 | * | |
1975 | * Unfortunately, it turns out that we _do_ some special | |
1976 | * handling of a disconnect event, namely complete all | |
1977 | * pending transfers, notify gadget driver of the | |
1978 | * disconnection, and so on. | |
1979 | * | |
1980 | * Our suggested workaround is to follow the Disconnect | |
1981 | * Event steps here, instead, based on a setup_packet_pending | |
1982 | * flag. Such flag gets set whenever we have a XferNotReady | |
1983 | * event on EP0 and gets cleared on XferComplete for the | |
1984 | * same endpoint. | |
1985 | * | |
1986 | * Refers to: | |
1987 | * | |
1988 | * STAR#9000466709: RTL: Device : Disconnect event not | |
1989 | * generated if setup packet pending in FIFO | |
1990 | */ | |
1991 | if (dwc->revision < DWC3_REVISION_188A) { | |
1992 | if (dwc->setup_packet_pending) | |
1993 | dwc3_gadget_disconnect_interrupt(dwc); | |
1994 | } | |
1995 | ||
961906ed FB |
1996 | /* after reset -> Default State */ |
1997 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
1998 | ||
802fde98 PZ |
1999 | /* Recent versions support automatic phy suspend and don't need this */ |
2000 | if (dwc->revision < DWC3_REVISION_194A) { | |
2001 | /* Resume PHYs */ | |
2002 | dwc3_gadget_usb2_phy_suspend(dwc, false); | |
2003 | dwc3_gadget_usb3_phy_suspend(dwc, false); | |
2004 | } | |
72246da4 FB |
2005 | |
2006 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) | |
2007 | dwc3_disconnect_gadget(dwc); | |
2008 | ||
2009 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2010 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
e6a3b5e2 | 2011 | reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); |
72246da4 | 2012 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
3b637367 | 2013 | dwc->test_mode = false; |
72246da4 FB |
2014 | |
2015 | dwc3_stop_active_transfers(dwc); | |
2016 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 2017 | dwc->start_config_issued = false; |
72246da4 FB |
2018 | |
2019 | /* Reset device address to zero */ | |
2020 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2021 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
2022 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
2023 | } |
2024 | ||
2025 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
2026 | { | |
2027 | u32 reg; | |
2028 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
2029 | ||
2030 | /* | |
2031 | * We change the clock only at SS but I dunno why I would want to do | |
2032 | * this. Maybe it becomes part of the power saving plan. | |
2033 | */ | |
2034 | ||
2035 | if (speed != DWC3_DSTS_SUPERSPEED) | |
2036 | return; | |
2037 | ||
2038 | /* | |
2039 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2040 | * each time on Connect Done. | |
2041 | */ | |
2042 | if (!usb30_clock) | |
2043 | return; | |
2044 | ||
2045 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2046 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2047 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2048 | } | |
2049 | ||
d7a46a8d | 2050 | static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) |
72246da4 FB |
2051 | { |
2052 | switch (speed) { | |
2053 | case USB_SPEED_SUPER: | |
d7a46a8d | 2054 | dwc3_gadget_usb2_phy_suspend(dwc, true); |
72246da4 FB |
2055 | break; |
2056 | case USB_SPEED_HIGH: | |
2057 | case USB_SPEED_FULL: | |
2058 | case USB_SPEED_LOW: | |
d7a46a8d | 2059 | dwc3_gadget_usb3_phy_suspend(dwc, true); |
72246da4 FB |
2060 | break; |
2061 | } | |
2062 | } | |
2063 | ||
2064 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) | |
2065 | { | |
2066 | struct dwc3_gadget_ep_cmd_params params; | |
2067 | struct dwc3_ep *dep; | |
2068 | int ret; | |
2069 | u32 reg; | |
2070 | u8 speed; | |
2071 | ||
2072 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2073 | ||
2074 | memset(¶ms, 0x00, sizeof(params)); | |
2075 | ||
72246da4 FB |
2076 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2077 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2078 | dwc->speed = speed; | |
2079 | ||
2080 | dwc3_update_ram_clk_sel(dwc, speed); | |
2081 | ||
2082 | switch (speed) { | |
2083 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2084 | /* |
2085 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2086 | * would cause a missing USB3 Reset event. | |
2087 | * | |
2088 | * In such situations, we should force a USB3 Reset | |
2089 | * event by calling our dwc3_gadget_reset_interrupt() | |
2090 | * routine. | |
2091 | * | |
2092 | * Refers to: | |
2093 | * | |
2094 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2095 | * not be generated always when the link enters poll | |
2096 | */ | |
2097 | if (dwc->revision < DWC3_REVISION_190A) | |
2098 | dwc3_gadget_reset_interrupt(dwc); | |
2099 | ||
72246da4 FB |
2100 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2101 | dwc->gadget.ep0->maxpacket = 512; | |
2102 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2103 | break; | |
2104 | case DWC3_DCFG_HIGHSPEED: | |
2105 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2106 | dwc->gadget.ep0->maxpacket = 64; | |
2107 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2108 | break; | |
2109 | case DWC3_DCFG_FULLSPEED2: | |
2110 | case DWC3_DCFG_FULLSPEED1: | |
2111 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2112 | dwc->gadget.ep0->maxpacket = 64; | |
2113 | dwc->gadget.speed = USB_SPEED_FULL; | |
2114 | break; | |
2115 | case DWC3_DCFG_LOWSPEED: | |
2116 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2117 | dwc->gadget.ep0->maxpacket = 8; | |
2118 | dwc->gadget.speed = USB_SPEED_LOW; | |
2119 | break; | |
2120 | } | |
2121 | ||
802fde98 PZ |
2122 | /* Recent versions support automatic phy suspend and don't need this */ |
2123 | if (dwc->revision < DWC3_REVISION_194A) { | |
2124 | /* Suspend unneeded PHY */ | |
2125 | dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); | |
2126 | } | |
72246da4 FB |
2127 | |
2128 | dep = dwc->eps[0]; | |
c90bfaec | 2129 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
2130 | if (ret) { |
2131 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2132 | return; | |
2133 | } | |
2134 | ||
2135 | dep = dwc->eps[1]; | |
c90bfaec | 2136 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
2137 | if (ret) { |
2138 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2139 | return; | |
2140 | } | |
2141 | ||
2142 | /* | |
2143 | * Configure PHY via GUSB3PIPECTLn if required. | |
2144 | * | |
2145 | * Update GTXFIFOSIZn | |
2146 | * | |
2147 | * In both cases reset values should be sufficient. | |
2148 | */ | |
2149 | } | |
2150 | ||
2151 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2152 | { | |
2153 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2154 | ||
2155 | /* | |
2156 | * TODO take core out of low power mode when that's | |
2157 | * implemented. | |
2158 | */ | |
2159 | ||
2160 | dwc->gadget_driver->resume(&dwc->gadget); | |
2161 | } | |
2162 | ||
2163 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2164 | unsigned int evtinfo) | |
2165 | { | |
fae2b904 FB |
2166 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
2167 | ||
2168 | /* | |
2169 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2170 | * on the link partner, the USB session might do multiple entry/exit | |
2171 | * of low power states before a transfer takes place. | |
2172 | * | |
2173 | * Due to this problem, we might experience lower throughput. The | |
2174 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2175 | * transitioning from U1/U2 to U0 and enable those bits again | |
2176 | * after a transfer completes and there are no pending transfers | |
2177 | * on any of the enabled endpoints. | |
2178 | * | |
2179 | * This is the first half of that workaround. | |
2180 | * | |
2181 | * Refers to: | |
2182 | * | |
2183 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2184 | * core send LGO_Ux entering U0 | |
2185 | */ | |
2186 | if (dwc->revision < DWC3_REVISION_183A) { | |
2187 | if (next == DWC3_LINK_STATE_U0) { | |
2188 | u32 u1u2; | |
2189 | u32 reg; | |
2190 | ||
2191 | switch (dwc->link_state) { | |
2192 | case DWC3_LINK_STATE_U1: | |
2193 | case DWC3_LINK_STATE_U2: | |
2194 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2195 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2196 | | DWC3_DCTL_ACCEPTU2ENA | |
2197 | | DWC3_DCTL_INITU1ENA | |
2198 | | DWC3_DCTL_ACCEPTU1ENA); | |
2199 | ||
2200 | if (!dwc->u1u2) | |
2201 | dwc->u1u2 = reg & u1u2; | |
2202 | ||
2203 | reg &= ~u1u2; | |
2204 | ||
2205 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2206 | break; | |
2207 | default: | |
2208 | /* do nothing */ | |
2209 | break; | |
2210 | } | |
2211 | } | |
2212 | } | |
2213 | ||
2214 | dwc->link_state = next; | |
019ac832 FB |
2215 | |
2216 | dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); | |
72246da4 FB |
2217 | } |
2218 | ||
2219 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, | |
2220 | const struct dwc3_event_devt *event) | |
2221 | { | |
2222 | switch (event->type) { | |
2223 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2224 | dwc3_gadget_disconnect_interrupt(dwc); | |
2225 | break; | |
2226 | case DWC3_DEVICE_EVENT_RESET: | |
2227 | dwc3_gadget_reset_interrupt(dwc); | |
2228 | break; | |
2229 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2230 | dwc3_gadget_conndone_interrupt(dwc); | |
2231 | break; | |
2232 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2233 | dwc3_gadget_wakeup_interrupt(dwc); | |
2234 | break; | |
2235 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: | |
2236 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2237 | break; | |
2238 | case DWC3_DEVICE_EVENT_EOPF: | |
2239 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2240 | break; | |
2241 | case DWC3_DEVICE_EVENT_SOF: | |
2242 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2243 | break; | |
2244 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2245 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2246 | break; | |
2247 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2248 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2249 | break; | |
2250 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2251 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2252 | break; | |
2253 | default: | |
2254 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2255 | } | |
2256 | } | |
2257 | ||
2258 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2259 | const union dwc3_event *event) | |
2260 | { | |
2261 | /* Endpoint IRQ, handle it and return early */ | |
2262 | if (event->type.is_devspec == 0) { | |
2263 | /* depevt */ | |
2264 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2265 | } | |
2266 | ||
2267 | switch (event->type.type) { | |
2268 | case DWC3_EVENT_TYPE_DEV: | |
2269 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2270 | break; | |
2271 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2272 | default: | |
2273 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2274 | } | |
2275 | } | |
2276 | ||
2277 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) | |
2278 | { | |
2279 | struct dwc3_event_buffer *evt; | |
2280 | int left; | |
2281 | u32 count; | |
2282 | ||
2283 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); | |
2284 | count &= DWC3_GEVNTCOUNT_MASK; | |
2285 | if (!count) | |
2286 | return IRQ_NONE; | |
2287 | ||
2288 | evt = dwc->ev_buffs[buf]; | |
2289 | left = count; | |
2290 | ||
2291 | while (left > 0) { | |
2292 | union dwc3_event event; | |
2293 | ||
d70d8442 FB |
2294 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
2295 | ||
72246da4 FB |
2296 | dwc3_process_event_entry(dwc, &event); |
2297 | /* | |
2298 | * XXX we wrap around correctly to the next entry as almost all | |
2299 | * entries are 4 bytes in size. There is one entry which has 12 | |
2300 | * bytes which is a regular entry followed by 8 bytes data. ATM | |
2301 | * I don't know how things are organized if were get next to the | |
2302 | * a boundary so I worry about that once we try to handle that. | |
2303 | */ | |
2304 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2305 | left -= 4; | |
2306 | ||
2307 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); | |
2308 | } | |
2309 | ||
2310 | return IRQ_HANDLED; | |
2311 | } | |
2312 | ||
2313 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2314 | { | |
2315 | struct dwc3 *dwc = _dwc; | |
2316 | int i; | |
2317 | irqreturn_t ret = IRQ_NONE; | |
2318 | ||
2319 | spin_lock(&dwc->lock); | |
2320 | ||
9f622b2a | 2321 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2322 | irqreturn_t status; |
2323 | ||
2324 | status = dwc3_process_event_buf(dwc, i); | |
2325 | if (status == IRQ_HANDLED) | |
2326 | ret = status; | |
2327 | } | |
2328 | ||
2329 | spin_unlock(&dwc->lock); | |
2330 | ||
2331 | return ret; | |
2332 | } | |
2333 | ||
2334 | /** | |
2335 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2336 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2337 | * |
2338 | * Returns 0 on success otherwise negative errno. | |
2339 | */ | |
2340 | int __devinit dwc3_gadget_init(struct dwc3 *dwc) | |
2341 | { | |
2342 | u32 reg; | |
2343 | int ret; | |
2344 | int irq; | |
2345 | ||
2346 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2347 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2348 | if (!dwc->ctrl_req) { | |
2349 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2350 | ret = -ENOMEM; | |
2351 | goto err0; | |
2352 | } | |
2353 | ||
2354 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2355 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2356 | if (!dwc->ep0_trb) { | |
2357 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2358 | ret = -ENOMEM; | |
2359 | goto err1; | |
2360 | } | |
2361 | ||
3ef35faf | 2362 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2363 | if (!dwc->setup_buf) { |
2364 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2365 | ret = -ENOMEM; | |
2366 | goto err2; | |
2367 | } | |
2368 | ||
5812b1c2 | 2369 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2370 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2371 | GFP_KERNEL); | |
5812b1c2 FB |
2372 | if (!dwc->ep0_bounce) { |
2373 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2374 | ret = -ENOMEM; | |
2375 | goto err3; | |
2376 | } | |
2377 | ||
72246da4 FB |
2378 | dev_set_name(&dwc->gadget.dev, "gadget"); |
2379 | ||
2380 | dwc->gadget.ops = &dwc3_gadget_ops; | |
d327ab5b | 2381 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 FB |
2382 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
2383 | dwc->gadget.dev.parent = dwc->dev; | |
eeb720fb | 2384 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2385 | |
2386 | dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); | |
2387 | ||
2388 | dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; | |
2389 | dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; | |
2390 | dwc->gadget.dev.release = dwc3_gadget_release; | |
2391 | dwc->gadget.name = "dwc3-gadget"; | |
2392 | ||
2393 | /* | |
2394 | * REVISIT: Here we should clear all pending IRQs to be | |
2395 | * sure we're starting from a well known location. | |
2396 | */ | |
2397 | ||
2398 | ret = dwc3_gadget_init_endpoints(dwc); | |
2399 | if (ret) | |
5812b1c2 | 2400 | goto err4; |
72246da4 FB |
2401 | |
2402 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); | |
2403 | ||
2404 | ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, | |
2405 | "dwc3", dwc); | |
2406 | if (ret) { | |
2407 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2408 | irq, ret); | |
5812b1c2 | 2409 | goto err5; |
72246da4 FB |
2410 | } |
2411 | ||
e6a3b5e2 SAS |
2412 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2413 | reg |= DWC3_DCFG_LPM_CAP; | |
2414 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2415 | ||
2416 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2417 | reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA; | |
2418 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2419 | ||
72246da4 FB |
2420 | /* Enable all but Start and End of Frame IRQs */ |
2421 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
2422 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
2423 | DWC3_DEVTEN_CMDCMPLTEN | | |
2424 | DWC3_DEVTEN_ERRTICERREN | | |
2425 | DWC3_DEVTEN_WKUPEVTEN | | |
2426 | DWC3_DEVTEN_ULSTCNGEN | | |
2427 | DWC3_DEVTEN_CONNECTDONEEN | | |
2428 | DWC3_DEVTEN_USBRSTEN | | |
2429 | DWC3_DEVTEN_DISCONNEVTEN); | |
2430 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
2431 | ||
802fde98 PZ |
2432 | /* Enable USB2 LPM and automatic phy suspend only on recent versions */ |
2433 | if (dwc->revision >= DWC3_REVISION_194A) { | |
2434 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
2435 | reg |= DWC3_DCFG_LPM_CAP; | |
2436 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2437 | ||
2438 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2439 | reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); | |
2440 | ||
2441 | /* TODO: This should be configurable */ | |
2442 | reg |= DWC3_DCTL_HIRD_THRES(31); | |
2443 | ||
2444 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2445 | ||
2446 | dwc3_gadget_usb2_phy_suspend(dwc, true); | |
2447 | dwc3_gadget_usb3_phy_suspend(dwc, true); | |
2448 | } | |
2449 | ||
72246da4 FB |
2450 | ret = device_register(&dwc->gadget.dev); |
2451 | if (ret) { | |
2452 | dev_err(dwc->dev, "failed to register gadget device\n"); | |
2453 | put_device(&dwc->gadget.dev); | |
5812b1c2 | 2454 | goto err6; |
72246da4 FB |
2455 | } |
2456 | ||
2457 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); | |
2458 | if (ret) { | |
2459 | dev_err(dwc->dev, "failed to register udc\n"); | |
5812b1c2 | 2460 | goto err7; |
72246da4 FB |
2461 | } |
2462 | ||
2463 | return 0; | |
2464 | ||
5812b1c2 | 2465 | err7: |
72246da4 FB |
2466 | device_unregister(&dwc->gadget.dev); |
2467 | ||
5812b1c2 | 2468 | err6: |
72246da4 FB |
2469 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); |
2470 | free_irq(irq, dwc); | |
2471 | ||
5812b1c2 | 2472 | err5: |
72246da4 FB |
2473 | dwc3_gadget_free_endpoints(dwc); |
2474 | ||
5812b1c2 | 2475 | err4: |
3ef35faf FB |
2476 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2477 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2478 | |
72246da4 | 2479 | err3: |
0fc9a1be | 2480 | kfree(dwc->setup_buf); |
72246da4 FB |
2481 | |
2482 | err2: | |
2483 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2484 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2485 | ||
2486 | err1: | |
2487 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2488 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2489 | ||
2490 | err0: | |
2491 | return ret; | |
2492 | } | |
2493 | ||
2494 | void dwc3_gadget_exit(struct dwc3 *dwc) | |
2495 | { | |
2496 | int irq; | |
72246da4 FB |
2497 | |
2498 | usb_del_gadget_udc(&dwc->gadget); | |
2499 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); | |
2500 | ||
2501 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2502 | free_irq(irq, dwc); | |
2503 | ||
72246da4 FB |
2504 | dwc3_gadget_free_endpoints(dwc); |
2505 | ||
3ef35faf FB |
2506 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2507 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2508 | |
0fc9a1be | 2509 | kfree(dwc->setup_buf); |
72246da4 FB |
2510 | |
2511 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2512 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2513 | ||
2514 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2515 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2516 | ||
2517 | device_unregister(&dwc->gadget.dev); | |
2518 | } |