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bae4bd84 DB |
1 | /* |
2 | * at91_udc -- driver for at91-series USB peripheral controller | |
3 | * | |
4 | * Copyright (C) 2004 by Thomas Rathbone | |
5 | * Copyright (C) 2005 by HP Labs | |
6 | * Copyright (C) 2005 by David Brownell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
bae4bd84 DB |
12 | */ |
13 | ||
f3db6e82 | 14 | #undef VERBOSE_DEBUG |
bae4bd84 DB |
15 | #undef PACKET_TRACE |
16 | ||
bae4bd84 DB |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/ioport.h> | |
bae4bd84 | 22 | #include <linux/slab.h> |
bae4bd84 DB |
23 | #include <linux/errno.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/proc_fs.h> | |
eed39366 | 28 | #include <linux/prefetch.h> |
bae4bd84 | 29 | #include <linux/clk.h> |
5f848137 | 30 | #include <linux/usb/ch9.h> |
9454a57a | 31 | #include <linux/usb/gadget.h> |
b38b03b3 | 32 | #include <linux/prefetch.h> |
bae4bd84 DB |
33 | |
34 | #include <asm/byteorder.h> | |
a09e64fb | 35 | #include <mach/hardware.h> |
bae4bd84 DB |
36 | #include <asm/io.h> |
37 | #include <asm/irq.h> | |
38 | #include <asm/system.h> | |
f3db6e82 | 39 | #include <asm/gpio.h> |
bae4bd84 | 40 | |
a09e64fb RK |
41 | #include <mach/board.h> |
42 | #include <mach/cpu.h> | |
43 | #include <mach/at91sam9261_matrix.h> | |
bae4bd84 DB |
44 | |
45 | #include "at91_udc.h" | |
46 | ||
47 | ||
48 | /* | |
49 | * This controller is simple and PIO-only. It's used in many AT91-series | |
8b2e7668 DB |
50 | * full speed USB controllers, including the at91rm9200 (arm920T, with MMU), |
51 | * at91sam926x (arm926ejs, with MMU), and several no-mmu versions. | |
bae4bd84 DB |
52 | * |
53 | * This driver expects the board has been wired with two GPIOs suppporting | |
54 | * a VBUS sensing IRQ, and a D+ pullup. (They may be omitted, but the | |
8b2e7668 DB |
55 | * testing hasn't covered such cases.) |
56 | * | |
57 | * The pullup is most important (so it's integrated on sam926x parts). It | |
bae4bd84 | 58 | * provides software control over whether the host enumerates the device. |
8b2e7668 | 59 | * |
bae4bd84 DB |
60 | * The VBUS sensing helps during enumeration, and allows both USB clocks |
61 | * (and the transceiver) to stay gated off until they're necessary, saving | |
8b2e7668 DB |
62 | * power. During USB suspend, the 48 MHz clock is gated off in hardware; |
63 | * it may also be gated off by software during some Linux sleep states. | |
bae4bd84 DB |
64 | */ |
65 | ||
8b2e7668 | 66 | #define DRIVER_VERSION "3 May 2006" |
bae4bd84 DB |
67 | |
68 | static const char driver_name [] = "at91_udc"; | |
69 | static const char ep0name[] = "ep0"; | |
70 | ||
4037242c | 71 | #define VBUS_POLL_TIMEOUT msecs_to_jiffies(1000) |
bae4bd84 | 72 | |
4f4c5e36 HH |
73 | #define at91_udp_read(udc, reg) \ |
74 | __raw_readl((udc)->udp_baseaddr + (reg)) | |
75 | #define at91_udp_write(udc, reg, val) \ | |
76 | __raw_writel((val), (udc)->udp_baseaddr + (reg)) | |
bae4bd84 DB |
77 | |
78 | /*-------------------------------------------------------------------------*/ | |
79 | ||
80 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
81 | ||
82 | #include <linux/seq_file.h> | |
83 | ||
84 | static const char debug_filename[] = "driver/udc"; | |
85 | ||
86 | #define FOURBITS "%s%s%s%s" | |
87 | #define EIGHTBITS FOURBITS FOURBITS | |
88 | ||
89 | static void proc_ep_show(struct seq_file *s, struct at91_ep *ep) | |
90 | { | |
91 | static char *types[] = { | |
92 | "control", "out-iso", "out-bulk", "out-int", | |
93 | "BOGUS", "in-iso", "in-bulk", "in-int"}; | |
94 | ||
95 | u32 csr; | |
96 | struct at91_request *req; | |
97 | unsigned long flags; | |
4f4c5e36 | 98 | struct at91_udc *udc = ep->udc; |
bae4bd84 | 99 | |
4f4c5e36 | 100 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
101 | |
102 | csr = __raw_readl(ep->creg); | |
103 | ||
104 | /* NOTE: not collecting per-endpoint irq statistics... */ | |
105 | ||
106 | seq_printf(s, "\n"); | |
107 | seq_printf(s, "%s, maxpacket %d %s%s %s%s\n", | |
108 | ep->ep.name, ep->ep.maxpacket, | |
109 | ep->is_in ? "in" : "out", | |
110 | ep->is_iso ? " iso" : "", | |
111 | ep->is_pingpong | |
112 | ? (ep->fifo_bank ? "pong" : "ping") | |
113 | : "", | |
114 | ep->stopped ? " stopped" : ""); | |
115 | seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", | |
116 | csr, | |
117 | (csr & 0x07ff0000) >> 16, | |
118 | (csr & (1 << 15)) ? "enabled" : "disabled", | |
119 | (csr & (1 << 11)) ? "DATA1" : "DATA0", | |
120 | types[(csr & 0x700) >> 8], | |
121 | ||
122 | /* iff type is control then print current direction */ | |
123 | (!(csr & 0x700)) | |
124 | ? ((csr & (1 << 7)) ? " IN" : " OUT") | |
125 | : "", | |
126 | (csr & (1 << 6)) ? " rxdatabk1" : "", | |
127 | (csr & (1 << 5)) ? " forcestall" : "", | |
128 | (csr & (1 << 4)) ? " txpktrdy" : "", | |
129 | ||
130 | (csr & (1 << 3)) ? " stallsent" : "", | |
131 | (csr & (1 << 2)) ? " rxsetup" : "", | |
132 | (csr & (1 << 1)) ? " rxdatabk0" : "", | |
133 | (csr & (1 << 0)) ? " txcomp" : ""); | |
134 | if (list_empty (&ep->queue)) | |
135 | seq_printf(s, "\t(queue empty)\n"); | |
136 | ||
137 | else list_for_each_entry (req, &ep->queue, queue) { | |
138 | unsigned length = req->req.actual; | |
139 | ||
140 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
141 | &req->req, length, | |
142 | req->req.length, req->req.buf); | |
143 | } | |
4f4c5e36 | 144 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
145 | } |
146 | ||
147 | static void proc_irq_show(struct seq_file *s, const char *label, u32 mask) | |
148 | { | |
149 | int i; | |
150 | ||
151 | seq_printf(s, "%s %04x:%s%s" FOURBITS, label, mask, | |
152 | (mask & (1 << 13)) ? " wakeup" : "", | |
153 | (mask & (1 << 12)) ? " endbusres" : "", | |
154 | ||
155 | (mask & (1 << 11)) ? " sofint" : "", | |
156 | (mask & (1 << 10)) ? " extrsm" : "", | |
157 | (mask & (1 << 9)) ? " rxrsm" : "", | |
158 | (mask & (1 << 8)) ? " rxsusp" : ""); | |
159 | for (i = 0; i < 8; i++) { | |
160 | if (mask & (1 << i)) | |
161 | seq_printf(s, " ep%d", i); | |
162 | } | |
163 | seq_printf(s, "\n"); | |
164 | } | |
165 | ||
166 | static int proc_udc_show(struct seq_file *s, void *unused) | |
167 | { | |
168 | struct at91_udc *udc = s->private; | |
169 | struct at91_ep *ep; | |
170 | u32 tmp; | |
171 | ||
172 | seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); | |
173 | ||
174 | seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", | |
175 | udc->vbus ? "present" : "off", | |
176 | udc->enabled | |
177 | ? (udc->vbus ? "active" : "enabled") | |
178 | : "disabled", | |
179 | udc->selfpowered ? "self" : "VBUS", | |
180 | udc->suspended ? ", suspended" : "", | |
181 | udc->driver ? udc->driver->driver.name : "(none)"); | |
182 | ||
183 | /* don't access registers when interface isn't clocked */ | |
184 | if (!udc->clocked) { | |
185 | seq_printf(s, "(not clocked)\n"); | |
186 | return 0; | |
187 | } | |
188 | ||
ffd3326b | 189 | tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM); |
bae4bd84 DB |
190 | seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp, |
191 | (tmp & AT91_UDP_FRM_OK) ? " ok" : "", | |
192 | (tmp & AT91_UDP_FRM_ERR) ? " err" : "", | |
193 | (tmp & AT91_UDP_NUM)); | |
194 | ||
ffd3326b | 195 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
196 | seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp, |
197 | (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "", | |
198 | (tmp & AT91_UDP_RSMINPR) ? " rsminpr" : "", | |
199 | (tmp & AT91_UDP_ESR) ? " esr" : "", | |
200 | (tmp & AT91_UDP_CONFG) ? " confg" : "", | |
201 | (tmp & AT91_UDP_FADDEN) ? " fadden" : ""); | |
202 | ||
ffd3326b | 203 | tmp = at91_udp_read(udc, AT91_UDP_FADDR); |
bae4bd84 DB |
204 | seq_printf(s, "faddr %03x:%s fadd=%d\n", tmp, |
205 | (tmp & AT91_UDP_FEN) ? " fen" : "", | |
206 | (tmp & AT91_UDP_FADD)); | |
207 | ||
ffd3326b AV |
208 | proc_irq_show(s, "imr ", at91_udp_read(udc, AT91_UDP_IMR)); |
209 | proc_irq_show(s, "isr ", at91_udp_read(udc, AT91_UDP_ISR)); | |
bae4bd84 DB |
210 | |
211 | if (udc->enabled && udc->vbus) { | |
212 | proc_ep_show(s, &udc->ep[0]); | |
213 | list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { | |
214 | if (ep->desc) | |
215 | proc_ep_show(s, ep); | |
216 | } | |
217 | } | |
218 | return 0; | |
219 | } | |
220 | ||
221 | static int proc_udc_open(struct inode *inode, struct file *file) | |
222 | { | |
223 | return single_open(file, proc_udc_show, PDE(inode)->data); | |
224 | } | |
225 | ||
066202dd | 226 | static const struct file_operations proc_ops = { |
cdefa185 | 227 | .owner = THIS_MODULE, |
bae4bd84 DB |
228 | .open = proc_udc_open, |
229 | .read = seq_read, | |
230 | .llseek = seq_lseek, | |
231 | .release = single_release, | |
232 | }; | |
233 | ||
234 | static void create_debug_file(struct at91_udc *udc) | |
235 | { | |
cdefa185 | 236 | udc->pde = proc_create_data(debug_filename, 0, NULL, &proc_ops, udc); |
bae4bd84 DB |
237 | } |
238 | ||
239 | static void remove_debug_file(struct at91_udc *udc) | |
240 | { | |
241 | if (udc->pde) | |
242 | remove_proc_entry(debug_filename, NULL); | |
243 | } | |
244 | ||
245 | #else | |
246 | ||
247 | static inline void create_debug_file(struct at91_udc *udc) {} | |
248 | static inline void remove_debug_file(struct at91_udc *udc) {} | |
249 | ||
250 | #endif | |
251 | ||
252 | ||
253 | /*-------------------------------------------------------------------------*/ | |
254 | ||
255 | static void done(struct at91_ep *ep, struct at91_request *req, int status) | |
256 | { | |
257 | unsigned stopped = ep->stopped; | |
ffd3326b | 258 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
259 | |
260 | list_del_init(&req->queue); | |
261 | if (req->req.status == -EINPROGRESS) | |
262 | req->req.status = status; | |
263 | else | |
264 | status = req->req.status; | |
265 | if (status && status != -ESHUTDOWN) | |
266 | VDBG("%s done %p, status %d\n", ep->ep.name, req, status); | |
267 | ||
268 | ep->stopped = 1; | |
4f4c5e36 | 269 | spin_unlock(&udc->lock); |
bae4bd84 | 270 | req->req.complete(&ep->ep, &req->req); |
4f4c5e36 | 271 | spin_lock(&udc->lock); |
bae4bd84 DB |
272 | ep->stopped = stopped; |
273 | ||
274 | /* ep0 is always ready; other endpoints need a non-empty queue */ | |
275 | if (list_empty(&ep->queue) && ep->int_mask != (1 << 0)) | |
ffd3326b | 276 | at91_udp_write(udc, AT91_UDP_IDR, ep->int_mask); |
bae4bd84 DB |
277 | } |
278 | ||
279 | /*-------------------------------------------------------------------------*/ | |
280 | ||
281 | /* bits indicating OUT fifo has data ready */ | |
282 | #define RX_DATA_READY (AT91_UDP_RX_DATA_BK0 | AT91_UDP_RX_DATA_BK1) | |
283 | ||
284 | /* | |
285 | * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write | |
286 | * back most of the value you just read (because of side effects, including | |
287 | * bits that may change after reading and before writing). | |
288 | * | |
289 | * Except when changing a specific bit, always write values which: | |
290 | * - clear SET_FX bits (setting them could change something) | |
291 | * - set CLR_FX bits (clearing them could change something) | |
292 | * | |
293 | * There are also state bits like FORCESTALL, EPEDS, DIR, and EPTYPE | |
294 | * that shouldn't normally be changed. | |
8b2e7668 DB |
295 | * |
296 | * NOTE at91sam9260 docs mention synch between UDPCK and MCK clock domains, | |
297 | * implying a need to wait for one write to complete (test relevant bits) | |
298 | * before starting the next write. This shouldn't be an issue given how | |
299 | * infrequently we write, except maybe for write-then-read idioms. | |
bae4bd84 DB |
300 | */ |
301 | #define SET_FX (AT91_UDP_TXPKTRDY) | |
8b2e7668 DB |
302 | #define CLR_FX (RX_DATA_READY | AT91_UDP_RXSETUP \ |
303 | | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP) | |
bae4bd84 DB |
304 | |
305 | /* pull OUT packet data from the endpoint's fifo */ | |
306 | static int read_fifo (struct at91_ep *ep, struct at91_request *req) | |
307 | { | |
308 | u32 __iomem *creg = ep->creg; | |
309 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
310 | u32 csr; | |
311 | u8 *buf; | |
312 | unsigned int count, bufferspace, is_done; | |
313 | ||
314 | buf = req->req.buf + req->req.actual; | |
315 | bufferspace = req->req.length - req->req.actual; | |
316 | ||
317 | /* | |
318 | * there might be nothing to read if ep_queue() calls us, | |
319 | * or if we already emptied both pingpong buffers | |
320 | */ | |
321 | rescan: | |
322 | csr = __raw_readl(creg); | |
323 | if ((csr & RX_DATA_READY) == 0) | |
324 | return 0; | |
325 | ||
326 | count = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
327 | if (count > ep->ep.maxpacket) | |
328 | count = ep->ep.maxpacket; | |
329 | if (count > bufferspace) { | |
330 | DBG("%s buffer overflow\n", ep->ep.name); | |
331 | req->req.status = -EOVERFLOW; | |
332 | count = bufferspace; | |
333 | } | |
334 | __raw_readsb(dreg, buf, count); | |
335 | ||
336 | /* release and swap pingpong mem bank */ | |
337 | csr |= CLR_FX; | |
338 | if (ep->is_pingpong) { | |
339 | if (ep->fifo_bank == 0) { | |
340 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
341 | ep->fifo_bank = 1; | |
342 | } else { | |
343 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); | |
344 | ep->fifo_bank = 0; | |
345 | } | |
346 | } else | |
347 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
348 | __raw_writel(csr, creg); | |
349 | ||
350 | req->req.actual += count; | |
351 | is_done = (count < ep->ep.maxpacket); | |
352 | if (count == bufferspace) | |
353 | is_done = 1; | |
354 | ||
355 | PACKET("%s %p out/%d%s\n", ep->ep.name, &req->req, count, | |
356 | is_done ? " (done)" : ""); | |
357 | ||
358 | /* | |
359 | * avoid extra trips through IRQ logic for packets already in | |
360 | * the fifo ... maybe preventing an extra (expensive) OUT-NAK | |
361 | */ | |
362 | if (is_done) | |
363 | done(ep, req, 0); | |
364 | else if (ep->is_pingpong) { | |
76225374 HH |
365 | /* |
366 | * One dummy read to delay the code because of a HW glitch: | |
367 | * CSR returns bad RXCOUNT when read too soon after updating | |
368 | * RX_DATA_BK flags. | |
369 | */ | |
370 | csr = __raw_readl(creg); | |
371 | ||
bae4bd84 DB |
372 | bufferspace -= count; |
373 | buf += count; | |
374 | goto rescan; | |
375 | } | |
376 | ||
377 | return is_done; | |
378 | } | |
379 | ||
380 | /* load fifo for an IN packet */ | |
381 | static int write_fifo(struct at91_ep *ep, struct at91_request *req) | |
382 | { | |
383 | u32 __iomem *creg = ep->creg; | |
384 | u32 csr = __raw_readl(creg); | |
385 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
386 | unsigned total, count, is_last; | |
3cf27234 | 387 | u8 *buf; |
bae4bd84 DB |
388 | |
389 | /* | |
390 | * TODO: allow for writing two packets to the fifo ... that'll | |
391 | * reduce the amount of IN-NAKing, but probably won't affect | |
392 | * throughput much. (Unlike preventing OUT-NAKing!) | |
393 | */ | |
394 | ||
395 | /* | |
396 | * If ep_queue() calls us, the queue is empty and possibly in | |
397 | * odd states like TXCOMP not yet cleared (we do it, saving at | |
398 | * least one IRQ) or the fifo not yet being free. Those aren't | |
399 | * issues normally (IRQ handler fast path). | |
400 | */ | |
401 | if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { | |
402 | if (csr & AT91_UDP_TXCOMP) { | |
403 | csr |= CLR_FX; | |
404 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
405 | __raw_writel(csr, creg); | |
406 | csr = __raw_readl(creg); | |
407 | } | |
408 | if (csr & AT91_UDP_TXPKTRDY) | |
409 | return 0; | |
410 | } | |
411 | ||
3cf27234 DB |
412 | buf = req->req.buf + req->req.actual; |
413 | prefetch(buf); | |
bae4bd84 DB |
414 | total = req->req.length - req->req.actual; |
415 | if (ep->ep.maxpacket < total) { | |
416 | count = ep->ep.maxpacket; | |
417 | is_last = 0; | |
418 | } else { | |
419 | count = total; | |
420 | is_last = (count < ep->ep.maxpacket) || !req->req.zero; | |
421 | } | |
422 | ||
423 | /* | |
424 | * Write the packet, maybe it's a ZLP. | |
425 | * | |
426 | * NOTE: incrementing req->actual before we receive the ACK means | |
427 | * gadget driver IN bytecounts can be wrong in fault cases. That's | |
428 | * fixable with PIO drivers like this one (save "count" here, and | |
429 | * do the increment later on TX irq), but not for most DMA hardware. | |
430 | * | |
431 | * So all gadget drivers must accept that potential error. Some | |
432 | * hardware supports precise fifo status reporting, letting them | |
433 | * recover when the actual bytecount matters (e.g. for USB Test | |
434 | * and Measurement Class devices). | |
435 | */ | |
3cf27234 | 436 | __raw_writesb(dreg, buf, count); |
bae4bd84 DB |
437 | csr &= ~SET_FX; |
438 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
439 | __raw_writel(csr, creg); | |
440 | req->req.actual += count; | |
441 | ||
442 | PACKET("%s %p in/%d%s\n", ep->ep.name, &req->req, count, | |
443 | is_last ? " (done)" : ""); | |
444 | if (is_last) | |
445 | done(ep, req, 0); | |
446 | return is_last; | |
447 | } | |
448 | ||
449 | static void nuke(struct at91_ep *ep, int status) | |
450 | { | |
451 | struct at91_request *req; | |
452 | ||
1a8060d9 | 453 | /* terminate any request in the queue */ |
bae4bd84 DB |
454 | ep->stopped = 1; |
455 | if (list_empty(&ep->queue)) | |
456 | return; | |
457 | ||
441b62c1 | 458 | VDBG("%s %s\n", __func__, ep->ep.name); |
bae4bd84 DB |
459 | while (!list_empty(&ep->queue)) { |
460 | req = list_entry(ep->queue.next, struct at91_request, queue); | |
461 | done(ep, req, status); | |
462 | } | |
463 | } | |
464 | ||
465 | /*-------------------------------------------------------------------------*/ | |
466 | ||
8b2e7668 DB |
467 | static int at91_ep_enable(struct usb_ep *_ep, |
468 | const struct usb_endpoint_descriptor *desc) | |
bae4bd84 DB |
469 | { |
470 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
4f4c5e36 | 471 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
472 | u16 maxpacket; |
473 | u32 tmp; | |
474 | unsigned long flags; | |
475 | ||
476 | if (!_ep || !ep | |
477 | || !desc || ep->desc | |
478 | || _ep->name == ep0name | |
479 | || desc->bDescriptorType != USB_DT_ENDPOINT | |
29cc8897 | 480 | || (maxpacket = usb_endpoint_maxp(desc)) == 0 |
bae4bd84 DB |
481 | || maxpacket > ep->maxpacket) { |
482 | DBG("bad ep or descriptor\n"); | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
4f4c5e36 | 486 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
487 | DBG("bogus device state\n"); |
488 | return -ESHUTDOWN; | |
489 | } | |
490 | ||
81c8d8d2 | 491 | tmp = usb_endpoint_type(desc); |
bae4bd84 DB |
492 | switch (tmp) { |
493 | case USB_ENDPOINT_XFER_CONTROL: | |
494 | DBG("only one control endpoint\n"); | |
495 | return -EINVAL; | |
496 | case USB_ENDPOINT_XFER_INT: | |
497 | if (maxpacket > 64) | |
498 | goto bogus_max; | |
499 | break; | |
500 | case USB_ENDPOINT_XFER_BULK: | |
501 | switch (maxpacket) { | |
502 | case 8: | |
503 | case 16: | |
504 | case 32: | |
505 | case 64: | |
506 | goto ok; | |
507 | } | |
508 | bogus_max: | |
509 | DBG("bogus maxpacket %d\n", maxpacket); | |
510 | return -EINVAL; | |
511 | case USB_ENDPOINT_XFER_ISOC: | |
512 | if (!ep->is_pingpong) { | |
513 | DBG("iso requires double buffering\n"); | |
514 | return -EINVAL; | |
515 | } | |
516 | break; | |
517 | } | |
518 | ||
519 | ok: | |
4f4c5e36 | 520 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
521 | |
522 | /* initialize endpoint to match this descriptor */ | |
81c8d8d2 | 523 | ep->is_in = usb_endpoint_dir_in(desc); |
bae4bd84 DB |
524 | ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC); |
525 | ep->stopped = 0; | |
526 | if (ep->is_in) | |
527 | tmp |= 0x04; | |
528 | tmp <<= 8; | |
529 | tmp |= AT91_UDP_EPEDS; | |
530 | __raw_writel(tmp, ep->creg); | |
531 | ||
532 | ep->desc = desc; | |
533 | ep->ep.maxpacket = maxpacket; | |
534 | ||
535 | /* | |
536 | * reset/init endpoint fifo. NOTE: leaves fifo_bank alone, | |
537 | * since endpoint resets don't reset hw pingpong state. | |
538 | */ | |
4f4c5e36 HH |
539 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
540 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 | 541 | |
4f4c5e36 | 542 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
543 | return 0; |
544 | } | |
545 | ||
546 | static int at91_ep_disable (struct usb_ep * _ep) | |
547 | { | |
548 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 549 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
550 | unsigned long flags; |
551 | ||
552 | if (ep == &ep->udc->ep[0]) | |
553 | return -EINVAL; | |
554 | ||
4f4c5e36 | 555 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
556 | |
557 | nuke(ep, -ESHUTDOWN); | |
558 | ||
559 | /* restore the endpoint's pristine config */ | |
560 | ep->desc = NULL; | |
561 | ep->ep.maxpacket = ep->maxpacket; | |
562 | ||
563 | /* reset fifos and endpoint */ | |
564 | if (ep->udc->clocked) { | |
ffd3326b AV |
565 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
566 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
567 | __raw_writel(0, ep->creg); |
568 | } | |
569 | ||
4f4c5e36 | 570 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
571 | return 0; |
572 | } | |
573 | ||
574 | /* | |
575 | * this is a PIO-only driver, so there's nothing | |
576 | * interesting for request or buffer allocation. | |
577 | */ | |
578 | ||
8b2e7668 | 579 | static struct usb_request * |
f3db6e82 | 580 | at91_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) |
bae4bd84 DB |
581 | { |
582 | struct at91_request *req; | |
583 | ||
cd861280 | 584 | req = kzalloc(sizeof (struct at91_request), gfp_flags); |
bae4bd84 DB |
585 | if (!req) |
586 | return NULL; | |
587 | ||
588 | INIT_LIST_HEAD(&req->queue); | |
589 | return &req->req; | |
590 | } | |
591 | ||
592 | static void at91_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
593 | { | |
594 | struct at91_request *req; | |
595 | ||
596 | req = container_of(_req, struct at91_request, req); | |
597 | BUG_ON(!list_empty(&req->queue)); | |
598 | kfree(req); | |
599 | } | |
600 | ||
bae4bd84 DB |
601 | static int at91_ep_queue(struct usb_ep *_ep, |
602 | struct usb_request *_req, gfp_t gfp_flags) | |
603 | { | |
604 | struct at91_request *req; | |
605 | struct at91_ep *ep; | |
4f4c5e36 | 606 | struct at91_udc *udc; |
bae4bd84 DB |
607 | int status; |
608 | unsigned long flags; | |
609 | ||
610 | req = container_of(_req, struct at91_request, req); | |
611 | ep = container_of(_ep, struct at91_ep, ep); | |
612 | ||
613 | if (!_req || !_req->complete | |
614 | || !_req->buf || !list_empty(&req->queue)) { | |
615 | DBG("invalid request\n"); | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
619 | if (!_ep || (!ep->desc && ep->ep.name != ep0name)) { | |
620 | DBG("invalid ep\n"); | |
621 | return -EINVAL; | |
622 | } | |
623 | ||
4f4c5e36 | 624 | udc = ep->udc; |
bae4bd84 | 625 | |
4f4c5e36 | 626 | if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
627 | DBG("invalid device\n"); |
628 | return -EINVAL; | |
629 | } | |
630 | ||
631 | _req->status = -EINPROGRESS; | |
632 | _req->actual = 0; | |
633 | ||
4f4c5e36 | 634 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
635 | |
636 | /* try to kickstart any empty and idle queue */ | |
637 | if (list_empty(&ep->queue) && !ep->stopped) { | |
638 | int is_ep0; | |
639 | ||
640 | /* | |
641 | * If this control request has a non-empty DATA stage, this | |
642 | * will start that stage. It works just like a non-control | |
643 | * request (until the status stage starts, maybe early). | |
644 | * | |
645 | * If the data stage is empty, then this starts a successful | |
646 | * IN/STATUS stage. (Unsuccessful ones use set_halt.) | |
647 | */ | |
648 | is_ep0 = (ep->ep.name == ep0name); | |
649 | if (is_ep0) { | |
650 | u32 tmp; | |
651 | ||
4f4c5e36 | 652 | if (!udc->req_pending) { |
bae4bd84 DB |
653 | status = -EINVAL; |
654 | goto done; | |
655 | } | |
656 | ||
657 | /* | |
658 | * defer changing CONFG until after the gadget driver | |
659 | * reconfigures the endpoints. | |
660 | */ | |
4f4c5e36 HH |
661 | if (udc->wait_for_config_ack) { |
662 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); | |
bae4bd84 DB |
663 | tmp ^= AT91_UDP_CONFG; |
664 | VDBG("toggle config\n"); | |
4f4c5e36 | 665 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
666 | } |
667 | if (req->req.length == 0) { | |
668 | ep0_in_status: | |
669 | PACKET("ep0 in/status\n"); | |
670 | status = 0; | |
671 | tmp = __raw_readl(ep->creg); | |
672 | tmp &= ~SET_FX; | |
673 | tmp |= CLR_FX | AT91_UDP_TXPKTRDY; | |
674 | __raw_writel(tmp, ep->creg); | |
4f4c5e36 | 675 | udc->req_pending = 0; |
bae4bd84 DB |
676 | goto done; |
677 | } | |
678 | } | |
679 | ||
680 | if (ep->is_in) | |
681 | status = write_fifo(ep, req); | |
682 | else { | |
683 | status = read_fifo(ep, req); | |
684 | ||
685 | /* IN/STATUS stage is otherwise triggered by irq */ | |
686 | if (status && is_ep0) | |
687 | goto ep0_in_status; | |
688 | } | |
689 | } else | |
690 | status = 0; | |
691 | ||
692 | if (req && !status) { | |
693 | list_add_tail (&req->queue, &ep->queue); | |
4f4c5e36 | 694 | at91_udp_write(udc, AT91_UDP_IER, ep->int_mask); |
bae4bd84 DB |
695 | } |
696 | done: | |
4f4c5e36 | 697 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
698 | return (status < 0) ? status : 0; |
699 | } | |
700 | ||
701 | static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
702 | { | |
4f4c5e36 | 703 | struct at91_ep *ep; |
bae4bd84 | 704 | struct at91_request *req; |
4f4c5e36 HH |
705 | unsigned long flags; |
706 | struct at91_udc *udc; | |
bae4bd84 DB |
707 | |
708 | ep = container_of(_ep, struct at91_ep, ep); | |
709 | if (!_ep || ep->ep.name == ep0name) | |
710 | return -EINVAL; | |
711 | ||
4f4c5e36 HH |
712 | udc = ep->udc; |
713 | ||
714 | spin_lock_irqsave(&udc->lock, flags); | |
715 | ||
bae4bd84 DB |
716 | /* make sure it's actually queued on this endpoint */ |
717 | list_for_each_entry (req, &ep->queue, queue) { | |
718 | if (&req->req == _req) | |
719 | break; | |
720 | } | |
4f4c5e36 HH |
721 | if (&req->req != _req) { |
722 | spin_unlock_irqrestore(&udc->lock, flags); | |
bae4bd84 | 723 | return -EINVAL; |
4f4c5e36 | 724 | } |
bae4bd84 DB |
725 | |
726 | done(ep, req, -ECONNRESET); | |
4f4c5e36 | 727 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
728 | return 0; |
729 | } | |
730 | ||
731 | static int at91_ep_set_halt(struct usb_ep *_ep, int value) | |
732 | { | |
733 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 734 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
735 | u32 __iomem *creg; |
736 | u32 csr; | |
737 | unsigned long flags; | |
738 | int status = 0; | |
739 | ||
740 | if (!_ep || ep->is_iso || !ep->udc->clocked) | |
741 | return -EINVAL; | |
742 | ||
743 | creg = ep->creg; | |
4f4c5e36 | 744 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
745 | |
746 | csr = __raw_readl(creg); | |
747 | ||
748 | /* | |
749 | * fail with still-busy IN endpoints, ensuring correct sequencing | |
750 | * of data tx then stall. note that the fifo rx bytecount isn't | |
751 | * completely accurate as a tx bytecount. | |
752 | */ | |
753 | if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) | |
754 | status = -EAGAIN; | |
755 | else { | |
756 | csr |= CLR_FX; | |
757 | csr &= ~SET_FX; | |
758 | if (value) { | |
759 | csr |= AT91_UDP_FORCESTALL; | |
760 | VDBG("halt %s\n", ep->ep.name); | |
761 | } else { | |
ffd3326b AV |
762 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
763 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
764 | csr &= ~AT91_UDP_FORCESTALL; |
765 | } | |
766 | __raw_writel(csr, creg); | |
767 | } | |
768 | ||
4f4c5e36 | 769 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
770 | return status; |
771 | } | |
772 | ||
398acce7 | 773 | static const struct usb_ep_ops at91_ep_ops = { |
bae4bd84 DB |
774 | .enable = at91_ep_enable, |
775 | .disable = at91_ep_disable, | |
776 | .alloc_request = at91_ep_alloc_request, | |
777 | .free_request = at91_ep_free_request, | |
bae4bd84 DB |
778 | .queue = at91_ep_queue, |
779 | .dequeue = at91_ep_dequeue, | |
780 | .set_halt = at91_ep_set_halt, | |
1a8060d9 | 781 | /* there's only imprecise fifo status reporting */ |
bae4bd84 DB |
782 | }; |
783 | ||
784 | /*-------------------------------------------------------------------------*/ | |
785 | ||
786 | static int at91_get_frame(struct usb_gadget *gadget) | |
787 | { | |
ffd3326b AV |
788 | struct at91_udc *udc = to_udc(gadget); |
789 | ||
bae4bd84 DB |
790 | if (!to_udc(gadget)->clocked) |
791 | return -EINVAL; | |
ffd3326b | 792 | return at91_udp_read(udc, AT91_UDP_FRM_NUM) & AT91_UDP_NUM; |
bae4bd84 DB |
793 | } |
794 | ||
795 | static int at91_wakeup(struct usb_gadget *gadget) | |
796 | { | |
797 | struct at91_udc *udc = to_udc(gadget); | |
798 | u32 glbstate; | |
799 | int status = -EINVAL; | |
800 | unsigned long flags; | |
801 | ||
441b62c1 | 802 | DBG("%s\n", __func__ ); |
4f4c5e36 | 803 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
804 | |
805 | if (!udc->clocked || !udc->suspended) | |
806 | goto done; | |
807 | ||
808 | /* NOTE: some "early versions" handle ESR differently ... */ | |
809 | ||
ffd3326b | 810 | glbstate = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
811 | if (!(glbstate & AT91_UDP_ESR)) |
812 | goto done; | |
813 | glbstate |= AT91_UDP_ESR; | |
ffd3326b | 814 | at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate); |
bae4bd84 DB |
815 | |
816 | done: | |
4f4c5e36 | 817 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
818 | return status; |
819 | } | |
820 | ||
25985edc | 821 | /* reinit == restore initial software state */ |
bae4bd84 DB |
822 | static void udc_reinit(struct at91_udc *udc) |
823 | { | |
824 | u32 i; | |
825 | ||
826 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
827 | INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); | |
828 | ||
829 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
830 | struct at91_ep *ep = &udc->ep[i]; | |
831 | ||
832 | if (i != 0) | |
833 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
834 | ep->desc = NULL; | |
835 | ep->stopped = 0; | |
836 | ep->fifo_bank = 0; | |
837 | ep->ep.maxpacket = ep->maxpacket; | |
ffd3326b | 838 | ep->creg = (void __iomem *) udc->udp_baseaddr + AT91_UDP_CSR(i); |
1a8060d9 | 839 | /* initialize one queue per endpoint */ |
bae4bd84 DB |
840 | INIT_LIST_HEAD(&ep->queue); |
841 | } | |
842 | } | |
843 | ||
844 | static void stop_activity(struct at91_udc *udc) | |
845 | { | |
846 | struct usb_gadget_driver *driver = udc->driver; | |
847 | int i; | |
848 | ||
849 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
850 | driver = NULL; | |
851 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
8b2e7668 | 852 | udc->suspended = 0; |
bae4bd84 DB |
853 | |
854 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
855 | struct at91_ep *ep = &udc->ep[i]; | |
856 | ep->stopped = 1; | |
857 | nuke(ep, -ESHUTDOWN); | |
858 | } | |
4f4c5e36 HH |
859 | if (driver) { |
860 | spin_unlock(&udc->lock); | |
bae4bd84 | 861 | driver->disconnect(&udc->gadget); |
4f4c5e36 HH |
862 | spin_lock(&udc->lock); |
863 | } | |
bae4bd84 DB |
864 | |
865 | udc_reinit(udc); | |
866 | } | |
867 | ||
868 | static void clk_on(struct at91_udc *udc) | |
869 | { | |
870 | if (udc->clocked) | |
871 | return; | |
872 | udc->clocked = 1; | |
873 | clk_enable(udc->iclk); | |
874 | clk_enable(udc->fclk); | |
875 | } | |
876 | ||
877 | static void clk_off(struct at91_udc *udc) | |
878 | { | |
879 | if (!udc->clocked) | |
880 | return; | |
881 | udc->clocked = 0; | |
882 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
bae4bd84 | 883 | clk_disable(udc->fclk); |
8b2e7668 | 884 | clk_disable(udc->iclk); |
bae4bd84 DB |
885 | } |
886 | ||
887 | /* | |
888 | * activate/deactivate link with host; minimize power usage for | |
889 | * inactive links by cutting clocks and transceiver power. | |
890 | */ | |
891 | static void pullup(struct at91_udc *udc, int is_on) | |
892 | { | |
f3db6e82 DB |
893 | int active = !udc->board.pullup_active_low; |
894 | ||
bae4bd84 DB |
895 | if (!udc->enabled || !udc->vbus) |
896 | is_on = 0; | |
897 | DBG("%sactive\n", is_on ? "" : "in"); | |
ffd3326b | 898 | |
bae4bd84 DB |
899 | if (is_on) { |
900 | clk_on(udc); | |
08cbc706 | 901 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); |
ffd3326b | 902 | at91_udp_write(udc, AT91_UDP_TXVC, 0); |
29ba4b53 | 903 | if (cpu_is_at91rm9200()) |
f3db6e82 | 904 | gpio_set_value(udc->board.pullup_pin, active); |
61352667 | 905 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
29ba4b53 AV |
906 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
907 | ||
908 | txvc |= AT91_UDP_TXVC_PUON; | |
909 | at91_udp_write(udc, AT91_UDP_TXVC, txvc); | |
23f6d914 | 910 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
29ba4b53 AV |
911 | u32 usbpucr; |
912 | ||
913 | usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR); | |
914 | usbpucr |= AT91_MATRIX_USBPUCR_PUON; | |
915 | at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr); | |
916 | } | |
ffd3326b | 917 | } else { |
bae4bd84 | 918 | stop_activity(udc); |
08cbc706 | 919 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
ffd3326b | 920 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
29ba4b53 | 921 | if (cpu_is_at91rm9200()) |
f3db6e82 | 922 | gpio_set_value(udc->board.pullup_pin, !active); |
61352667 | 923 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
29ba4b53 AV |
924 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
925 | ||
926 | txvc &= ~AT91_UDP_TXVC_PUON; | |
927 | at91_udp_write(udc, AT91_UDP_TXVC, txvc); | |
23f6d914 | 928 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
29ba4b53 AV |
929 | u32 usbpucr; |
930 | ||
931 | usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR); | |
932 | usbpucr &= ~AT91_MATRIX_USBPUCR_PUON; | |
933 | at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr); | |
934 | } | |
bae4bd84 | 935 | clk_off(udc); |
bae4bd84 DB |
936 | } |
937 | } | |
938 | ||
939 | /* vbus is here! turn everything on that's ready */ | |
940 | static int at91_vbus_session(struct usb_gadget *gadget, int is_active) | |
941 | { | |
942 | struct at91_udc *udc = to_udc(gadget); | |
943 | unsigned long flags; | |
944 | ||
1a8060d9 | 945 | /* VDBG("vbus %s\n", is_active ? "on" : "off"); */ |
4f4c5e36 | 946 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 947 | udc->vbus = (is_active != 0); |
bfb7fb79 WK |
948 | if (udc->driver) |
949 | pullup(udc, is_active); | |
950 | else | |
951 | pullup(udc, 0); | |
4f4c5e36 | 952 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
953 | return 0; |
954 | } | |
955 | ||
956 | static int at91_pullup(struct usb_gadget *gadget, int is_on) | |
957 | { | |
958 | struct at91_udc *udc = to_udc(gadget); | |
959 | unsigned long flags; | |
960 | ||
4f4c5e36 | 961 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
962 | udc->enabled = is_on = !!is_on; |
963 | pullup(udc, is_on); | |
4f4c5e36 | 964 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
965 | return 0; |
966 | } | |
967 | ||
968 | static int at91_set_selfpowered(struct usb_gadget *gadget, int is_on) | |
969 | { | |
970 | struct at91_udc *udc = to_udc(gadget); | |
971 | unsigned long flags; | |
972 | ||
4f4c5e36 | 973 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 974 | udc->selfpowered = (is_on != 0); |
4f4c5e36 | 975 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
976 | return 0; |
977 | } | |
978 | ||
0f91349b SAS |
979 | static int at91_start(struct usb_gadget_driver *driver, |
980 | int (*bind)(struct usb_gadget *)); | |
981 | static int at91_stop(struct usb_gadget_driver *driver); | |
982 | ||
bae4bd84 DB |
983 | static const struct usb_gadget_ops at91_udc_ops = { |
984 | .get_frame = at91_get_frame, | |
985 | .wakeup = at91_wakeup, | |
986 | .set_selfpowered = at91_set_selfpowered, | |
987 | .vbus_session = at91_vbus_session, | |
988 | .pullup = at91_pullup, | |
0f91349b SAS |
989 | .start = at91_start, |
990 | .stop = at91_stop, | |
bae4bd84 DB |
991 | |
992 | /* | |
993 | * VBUS-powered devices may also also want to support bigger | |
994 | * power budgets after an appropriate SET_CONFIGURATION. | |
995 | */ | |
1a8060d9 | 996 | /* .vbus_power = at91_vbus_power, */ |
bae4bd84 DB |
997 | }; |
998 | ||
999 | /*-------------------------------------------------------------------------*/ | |
1000 | ||
1001 | static int handle_ep(struct at91_ep *ep) | |
1002 | { | |
1003 | struct at91_request *req; | |
1004 | u32 __iomem *creg = ep->creg; | |
1005 | u32 csr = __raw_readl(creg); | |
1006 | ||
1007 | if (!list_empty(&ep->queue)) | |
1008 | req = list_entry(ep->queue.next, | |
1009 | struct at91_request, queue); | |
1010 | else | |
1011 | req = NULL; | |
1012 | ||
1013 | if (ep->is_in) { | |
1014 | if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { | |
1015 | csr |= CLR_FX; | |
1016 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); | |
1017 | __raw_writel(csr, creg); | |
1018 | } | |
1019 | if (req) | |
1020 | return write_fifo(ep, req); | |
1021 | ||
1022 | } else { | |
1023 | if (csr & AT91_UDP_STALLSENT) { | |
1024 | /* STALLSENT bit == ISOERR */ | |
1025 | if (ep->is_iso && req) | |
1026 | req->req.status = -EILSEQ; | |
1027 | csr |= CLR_FX; | |
1028 | csr &= ~(SET_FX | AT91_UDP_STALLSENT); | |
1029 | __raw_writel(csr, creg); | |
1030 | csr = __raw_readl(creg); | |
1031 | } | |
1032 | if (req && (csr & RX_DATA_READY)) | |
1033 | return read_fifo(ep, req); | |
1034 | } | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | union setup { | |
1039 | u8 raw[8]; | |
1040 | struct usb_ctrlrequest r; | |
1041 | }; | |
1042 | ||
1043 | static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) | |
1044 | { | |
1045 | u32 __iomem *creg = ep->creg; | |
1046 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
1047 | unsigned rxcount, i = 0; | |
1048 | u32 tmp; | |
1049 | union setup pkt; | |
1050 | int status = 0; | |
1051 | ||
1052 | /* read and ack SETUP; hard-fail for bogus packets */ | |
1053 | rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
1054 | if (likely(rxcount == 8)) { | |
1055 | while (rxcount--) | |
1056 | pkt.raw[i++] = __raw_readb(dreg); | |
1057 | if (pkt.r.bRequestType & USB_DIR_IN) { | |
1058 | csr |= AT91_UDP_DIR; | |
1059 | ep->is_in = 1; | |
1060 | } else { | |
1061 | csr &= ~AT91_UDP_DIR; | |
1062 | ep->is_in = 0; | |
1063 | } | |
1064 | } else { | |
1a8060d9 | 1065 | /* REVISIT this happens sometimes under load; why?? */ |
bae4bd84 DB |
1066 | ERR("SETUP len %d, csr %08x\n", rxcount, csr); |
1067 | status = -EINVAL; | |
1068 | } | |
1069 | csr |= CLR_FX; | |
1070 | csr &= ~(SET_FX | AT91_UDP_RXSETUP); | |
1071 | __raw_writel(csr, creg); | |
1072 | udc->wait_for_addr_ack = 0; | |
1073 | udc->wait_for_config_ack = 0; | |
1074 | ep->stopped = 0; | |
1075 | if (unlikely(status != 0)) | |
1076 | goto stall; | |
1077 | ||
1078 | #define w_index le16_to_cpu(pkt.r.wIndex) | |
1079 | #define w_value le16_to_cpu(pkt.r.wValue) | |
1080 | #define w_length le16_to_cpu(pkt.r.wLength) | |
1081 | ||
1082 | VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1083 | pkt.r.bRequestType, pkt.r.bRequest, | |
1084 | w_value, w_index, w_length); | |
1085 | ||
1086 | /* | |
1087 | * A few standard requests get handled here, ones that touch | |
1088 | * hardware ... notably for device and endpoint features. | |
1089 | */ | |
1090 | udc->req_pending = 1; | |
1091 | csr = __raw_readl(creg); | |
1092 | csr |= CLR_FX; | |
1093 | csr &= ~SET_FX; | |
1094 | switch ((pkt.r.bRequestType << 8) | pkt.r.bRequest) { | |
1095 | ||
1096 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1097 | | USB_REQ_SET_ADDRESS: | |
1098 | __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); | |
1099 | udc->addr = w_value; | |
1100 | udc->wait_for_addr_ack = 1; | |
1101 | udc->req_pending = 0; | |
1102 | /* FADDR is set later, when we ack host STATUS */ | |
1103 | return; | |
1104 | ||
1105 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1106 | | USB_REQ_SET_CONFIGURATION: | |
ffd3326b | 1107 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_CONFG; |
bae4bd84 DB |
1108 | if (pkt.r.wValue) |
1109 | udc->wait_for_config_ack = (tmp == 0); | |
1110 | else | |
1111 | udc->wait_for_config_ack = (tmp != 0); | |
1112 | if (udc->wait_for_config_ack) | |
1113 | VDBG("wait for config\n"); | |
1114 | /* CONFG is toggled later, if gadget driver succeeds */ | |
1115 | break; | |
1116 | ||
1117 | /* | |
1118 | * Hosts may set or clear remote wakeup status, and | |
1119 | * devices may report they're VBUS powered. | |
1120 | */ | |
1121 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1122 | | USB_REQ_GET_STATUS: | |
1123 | tmp = (udc->selfpowered << USB_DEVICE_SELF_POWERED); | |
ffd3326b | 1124 | if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR) |
bae4bd84 DB |
1125 | tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP); |
1126 | PACKET("get device status\n"); | |
1127 | __raw_writeb(tmp, dreg); | |
1128 | __raw_writeb(0, dreg); | |
1129 | goto write_in; | |
1130 | /* then STATUS starts later, automatically */ | |
1131 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1132 | | USB_REQ_SET_FEATURE: | |
1133 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1134 | goto stall; | |
ffd3326b | 1135 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1136 | tmp |= AT91_UDP_ESR; |
ffd3326b | 1137 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1138 | goto succeed; |
1139 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1140 | | USB_REQ_CLEAR_FEATURE: | |
1141 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1142 | goto stall; | |
ffd3326b | 1143 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1144 | tmp &= ~AT91_UDP_ESR; |
ffd3326b | 1145 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1146 | goto succeed; |
1147 | ||
1148 | /* | |
1149 | * Interfaces have no feature settings; this is pretty useless. | |
1150 | * we won't even insist the interface exists... | |
1151 | */ | |
1152 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1153 | | USB_REQ_GET_STATUS: | |
1154 | PACKET("get interface status\n"); | |
1155 | __raw_writeb(0, dreg); | |
1156 | __raw_writeb(0, dreg); | |
1157 | goto write_in; | |
1158 | /* then STATUS starts later, automatically */ | |
1159 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1160 | | USB_REQ_SET_FEATURE: | |
1161 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1162 | | USB_REQ_CLEAR_FEATURE: | |
1163 | goto stall; | |
1164 | ||
1165 | /* | |
1166 | * Hosts may clear bulk/intr endpoint halt after the gadget | |
1167 | * driver sets it (not widely used); or set it (for testing) | |
1168 | */ | |
1169 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1170 | | USB_REQ_GET_STATUS: | |
1171 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1172 | ep = &udc->ep[tmp]; | |
1440e096 | 1173 | if (tmp >= NUM_ENDPOINTS || (tmp && !ep->desc)) |
bae4bd84 DB |
1174 | goto stall; |
1175 | ||
1176 | if (tmp) { | |
1177 | if ((w_index & USB_DIR_IN)) { | |
1178 | if (!ep->is_in) | |
1179 | goto stall; | |
1180 | } else if (ep->is_in) | |
1181 | goto stall; | |
1182 | } | |
1183 | PACKET("get %s status\n", ep->ep.name); | |
1184 | if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL) | |
1185 | tmp = (1 << USB_ENDPOINT_HALT); | |
1186 | else | |
1187 | tmp = 0; | |
1188 | __raw_writeb(tmp, dreg); | |
1189 | __raw_writeb(0, dreg); | |
1190 | goto write_in; | |
1191 | /* then STATUS starts later, automatically */ | |
1192 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1193 | | USB_REQ_SET_FEATURE: | |
1194 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1195 | ep = &udc->ep[tmp]; | |
1440e096 | 1196 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 DB |
1197 | goto stall; |
1198 | if (!ep->desc || ep->is_iso) | |
1199 | goto stall; | |
1200 | if ((w_index & USB_DIR_IN)) { | |
1201 | if (!ep->is_in) | |
1202 | goto stall; | |
1203 | } else if (ep->is_in) | |
1204 | goto stall; | |
1205 | ||
1206 | tmp = __raw_readl(ep->creg); | |
1207 | tmp &= ~SET_FX; | |
1208 | tmp |= CLR_FX | AT91_UDP_FORCESTALL; | |
1209 | __raw_writel(tmp, ep->creg); | |
1210 | goto succeed; | |
1211 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1212 | | USB_REQ_CLEAR_FEATURE: | |
1213 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1214 | ep = &udc->ep[tmp]; | |
1440e096 | 1215 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 DB |
1216 | goto stall; |
1217 | if (tmp == 0) | |
1218 | goto succeed; | |
1219 | if (!ep->desc || ep->is_iso) | |
1220 | goto stall; | |
1221 | if ((w_index & USB_DIR_IN)) { | |
1222 | if (!ep->is_in) | |
1223 | goto stall; | |
1224 | } else if (ep->is_in) | |
1225 | goto stall; | |
1226 | ||
ffd3326b AV |
1227 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
1228 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
1229 | tmp = __raw_readl(ep->creg); |
1230 | tmp |= CLR_FX; | |
1231 | tmp &= ~(SET_FX | AT91_UDP_FORCESTALL); | |
1232 | __raw_writel(tmp, ep->creg); | |
1233 | if (!list_empty(&ep->queue)) | |
1234 | handle_ep(ep); | |
1235 | goto succeed; | |
1236 | } | |
1237 | ||
1238 | #undef w_value | |
1239 | #undef w_index | |
1240 | #undef w_length | |
1241 | ||
1242 | /* pass request up to the gadget driver */ | |
4f4c5e36 HH |
1243 | if (udc->driver) { |
1244 | spin_unlock(&udc->lock); | |
bfb7fb79 | 1245 | status = udc->driver->setup(&udc->gadget, &pkt.r); |
4f4c5e36 HH |
1246 | spin_lock(&udc->lock); |
1247 | } | |
bfb7fb79 WK |
1248 | else |
1249 | status = -ENODEV; | |
bae4bd84 DB |
1250 | if (status < 0) { |
1251 | stall: | |
1252 | VDBG("req %02x.%02x protocol STALL; stat %d\n", | |
1253 | pkt.r.bRequestType, pkt.r.bRequest, status); | |
1254 | csr |= AT91_UDP_FORCESTALL; | |
1255 | __raw_writel(csr, creg); | |
1256 | udc->req_pending = 0; | |
1257 | } | |
1258 | return; | |
1259 | ||
1260 | succeed: | |
1261 | /* immediate successful (IN) STATUS after zero length DATA */ | |
1262 | PACKET("ep0 in/status\n"); | |
1263 | write_in: | |
1264 | csr |= AT91_UDP_TXPKTRDY; | |
1265 | __raw_writel(csr, creg); | |
1266 | udc->req_pending = 0; | |
bae4bd84 DB |
1267 | } |
1268 | ||
1269 | static void handle_ep0(struct at91_udc *udc) | |
1270 | { | |
1271 | struct at91_ep *ep0 = &udc->ep[0]; | |
1272 | u32 __iomem *creg = ep0->creg; | |
1273 | u32 csr = __raw_readl(creg); | |
1274 | struct at91_request *req; | |
1275 | ||
1276 | if (unlikely(csr & AT91_UDP_STALLSENT)) { | |
1277 | nuke(ep0, -EPROTO); | |
1278 | udc->req_pending = 0; | |
1279 | csr |= CLR_FX; | |
1280 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); | |
1281 | __raw_writel(csr, creg); | |
1282 | VDBG("ep0 stalled\n"); | |
1283 | csr = __raw_readl(creg); | |
1284 | } | |
1285 | if (csr & AT91_UDP_RXSETUP) { | |
1286 | nuke(ep0, 0); | |
1287 | udc->req_pending = 0; | |
1288 | handle_setup(udc, ep0, csr); | |
1289 | return; | |
1290 | } | |
1291 | ||
1292 | if (list_empty(&ep0->queue)) | |
1293 | req = NULL; | |
1294 | else | |
1295 | req = list_entry(ep0->queue.next, struct at91_request, queue); | |
1296 | ||
1297 | /* host ACKed an IN packet that we sent */ | |
1298 | if (csr & AT91_UDP_TXCOMP) { | |
1299 | csr |= CLR_FX; | |
1300 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
1301 | ||
1302 | /* write more IN DATA? */ | |
1303 | if (req && ep0->is_in) { | |
1304 | if (handle_ep(ep0)) | |
1305 | udc->req_pending = 0; | |
1306 | ||
1307 | /* | |
1308 | * Ack after: | |
1309 | * - last IN DATA packet (including GET_STATUS) | |
1310 | * - IN/STATUS for OUT DATA | |
1311 | * - IN/STATUS for any zero-length DATA stage | |
1312 | * except for the IN DATA case, the host should send | |
1313 | * an OUT status later, which we'll ack. | |
1314 | */ | |
1315 | } else { | |
1316 | udc->req_pending = 0; | |
1317 | __raw_writel(csr, creg); | |
1318 | ||
1319 | /* | |
1320 | * SET_ADDRESS takes effect only after the STATUS | |
1321 | * (to the original address) gets acked. | |
1322 | */ | |
1323 | if (udc->wait_for_addr_ack) { | |
1324 | u32 tmp; | |
1325 | ||
ffd3326b | 1326 | at91_udp_write(udc, AT91_UDP_FADDR, |
8b2e7668 | 1327 | AT91_UDP_FEN | udc->addr); |
ffd3326b | 1328 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
1329 | tmp &= ~AT91_UDP_FADDEN; |
1330 | if (udc->addr) | |
1331 | tmp |= AT91_UDP_FADDEN; | |
ffd3326b | 1332 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1333 | |
1334 | udc->wait_for_addr_ack = 0; | |
1335 | VDBG("address %d\n", udc->addr); | |
1336 | } | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /* OUT packet arrived ... */ | |
1341 | else if (csr & AT91_UDP_RX_DATA_BK0) { | |
1342 | csr |= CLR_FX; | |
1343 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
1344 | ||
1345 | /* OUT DATA stage */ | |
1346 | if (!ep0->is_in) { | |
1347 | if (req) { | |
1348 | if (handle_ep(ep0)) { | |
1349 | /* send IN/STATUS */ | |
1350 | PACKET("ep0 in/status\n"); | |
1351 | csr = __raw_readl(creg); | |
1352 | csr &= ~SET_FX; | |
1353 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
1354 | __raw_writel(csr, creg); | |
1355 | udc->req_pending = 0; | |
1356 | } | |
1357 | } else if (udc->req_pending) { | |
1358 | /* | |
1359 | * AT91 hardware has a hard time with this | |
1360 | * "deferred response" mode for control-OUT | |
1361 | * transfers. (For control-IN it's fine.) | |
1362 | * | |
1363 | * The normal solution leaves OUT data in the | |
1364 | * fifo until the gadget driver is ready. | |
1365 | * We couldn't do that here without disabling | |
1366 | * the IRQ that tells about SETUP packets, | |
1367 | * e.g. when the host gets impatient... | |
1368 | * | |
1369 | * Working around it by copying into a buffer | |
1370 | * would almost be a non-deferred response, | |
1371 | * except that it wouldn't permit reliable | |
1372 | * stalling of the request. Instead, demand | |
1373 | * that gadget drivers not use this mode. | |
1374 | */ | |
1375 | DBG("no control-OUT deferred responses!\n"); | |
1376 | __raw_writel(csr | AT91_UDP_FORCESTALL, creg); | |
1377 | udc->req_pending = 0; | |
1378 | } | |
1379 | ||
1380 | /* STATUS stage for control-IN; ack. */ | |
1381 | } else { | |
1382 | PACKET("ep0 out/status ACK\n"); | |
1383 | __raw_writel(csr, creg); | |
1384 | ||
1385 | /* "early" status stage */ | |
1386 | if (req) | |
1387 | done(ep0, req, 0); | |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | ||
7d12e780 | 1392 | static irqreturn_t at91_udc_irq (int irq, void *_udc) |
bae4bd84 DB |
1393 | { |
1394 | struct at91_udc *udc = _udc; | |
1395 | u32 rescans = 5; | |
c6c35237 | 1396 | int disable_clock = 0; |
4f4c5e36 HH |
1397 | unsigned long flags; |
1398 | ||
1399 | spin_lock_irqsave(&udc->lock, flags); | |
c6c35237 HH |
1400 | |
1401 | if (!udc->clocked) { | |
1402 | clk_on(udc); | |
1403 | disable_clock = 1; | |
1404 | } | |
bae4bd84 DB |
1405 | |
1406 | while (rescans--) { | |
8b2e7668 | 1407 | u32 status; |
bae4bd84 | 1408 | |
ffd3326b AV |
1409 | status = at91_udp_read(udc, AT91_UDP_ISR) |
1410 | & at91_udp_read(udc, AT91_UDP_IMR); | |
bae4bd84 DB |
1411 | if (!status) |
1412 | break; | |
1413 | ||
1414 | /* USB reset irq: not maskable */ | |
1415 | if (status & AT91_UDP_ENDBUSRES) { | |
ffd3326b AV |
1416 | at91_udp_write(udc, AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS); |
1417 | at91_udp_write(udc, AT91_UDP_IER, MINIMUS_INTERRUPTUS); | |
bae4bd84 | 1418 | /* Atmel code clears this irq twice */ |
ffd3326b AV |
1419 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); |
1420 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); | |
bae4bd84 DB |
1421 | VDBG("end bus reset\n"); |
1422 | udc->addr = 0; | |
1423 | stop_activity(udc); | |
1424 | ||
1425 | /* enable ep0 */ | |
ffd3326b | 1426 | at91_udp_write(udc, AT91_UDP_CSR(0), |
8b2e7668 | 1427 | AT91_UDP_EPEDS | AT91_UDP_EPTYPE_CTRL); |
bae4bd84 DB |
1428 | udc->gadget.speed = USB_SPEED_FULL; |
1429 | udc->suspended = 0; | |
ffd3326b | 1430 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_EP(0)); |
bae4bd84 DB |
1431 | |
1432 | /* | |
1433 | * NOTE: this driver keeps clocks off unless the | |
8b2e7668 DB |
1434 | * USB host is present. That saves power, but for |
1435 | * boards that don't support VBUS detection, both | |
1436 | * clocks need to be active most of the time. | |
bae4bd84 DB |
1437 | */ |
1438 | ||
1439 | /* host initiated suspend (3+ms bus idle) */ | |
1440 | } else if (status & AT91_UDP_RXSUSP) { | |
ffd3326b AV |
1441 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXSUSP); |
1442 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXRSM); | |
1443 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXSUSP); | |
1a8060d9 | 1444 | /* VDBG("bus suspend\n"); */ |
bae4bd84 DB |
1445 | if (udc->suspended) |
1446 | continue; | |
1447 | udc->suspended = 1; | |
1448 | ||
1449 | /* | |
1450 | * NOTE: when suspending a VBUS-powered device, the | |
1451 | * gadget driver should switch into slow clock mode | |
1452 | * and then into standby to avoid drawing more than | |
1453 | * 500uA power (2500uA for some high-power configs). | |
1454 | */ | |
4f4c5e36 HH |
1455 | if (udc->driver && udc->driver->suspend) { |
1456 | spin_unlock(&udc->lock); | |
bae4bd84 | 1457 | udc->driver->suspend(&udc->gadget); |
4f4c5e36 HH |
1458 | spin_lock(&udc->lock); |
1459 | } | |
bae4bd84 DB |
1460 | |
1461 | /* host initiated resume */ | |
1462 | } else if (status & AT91_UDP_RXRSM) { | |
ffd3326b AV |
1463 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
1464 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXSUSP); | |
1465 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); | |
1a8060d9 | 1466 | /* VDBG("bus resume\n"); */ |
bae4bd84 DB |
1467 | if (!udc->suspended) |
1468 | continue; | |
1469 | udc->suspended = 0; | |
1470 | ||
1471 | /* | |
1472 | * NOTE: for a VBUS-powered device, the gadget driver | |
1473 | * would normally want to switch out of slow clock | |
1474 | * mode into normal mode. | |
1475 | */ | |
4f4c5e36 HH |
1476 | if (udc->driver && udc->driver->resume) { |
1477 | spin_unlock(&udc->lock); | |
bae4bd84 | 1478 | udc->driver->resume(&udc->gadget); |
4f4c5e36 HH |
1479 | spin_lock(&udc->lock); |
1480 | } | |
bae4bd84 DB |
1481 | |
1482 | /* endpoint IRQs are cleared by handling them */ | |
1483 | } else { | |
1484 | int i; | |
1485 | unsigned mask = 1; | |
1486 | struct at91_ep *ep = &udc->ep[1]; | |
1487 | ||
1488 | if (status & mask) | |
1489 | handle_ep0(udc); | |
1490 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
1491 | mask <<= 1; | |
1492 | if (status & mask) | |
1493 | handle_ep(ep); | |
1494 | ep++; | |
1495 | } | |
1496 | } | |
1497 | } | |
1498 | ||
c6c35237 HH |
1499 | if (disable_clock) |
1500 | clk_off(udc); | |
1501 | ||
4f4c5e36 HH |
1502 | spin_unlock_irqrestore(&udc->lock, flags); |
1503 | ||
bae4bd84 DB |
1504 | return IRQ_HANDLED; |
1505 | } | |
1506 | ||
1507 | /*-------------------------------------------------------------------------*/ | |
1508 | ||
8b2e7668 DB |
1509 | static void nop_release(struct device *dev) |
1510 | { | |
1511 | /* nothing to free */ | |
1512 | } | |
1513 | ||
bae4bd84 DB |
1514 | static struct at91_udc controller = { |
1515 | .gadget = { | |
8b2e7668 DB |
1516 | .ops = &at91_udc_ops, |
1517 | .ep0 = &controller.ep[0].ep, | |
1518 | .name = driver_name, | |
1519 | .dev = { | |
c682b170 | 1520 | .init_name = "gadget", |
8b2e7668 | 1521 | .release = nop_release, |
bae4bd84 DB |
1522 | } |
1523 | }, | |
1524 | .ep[0] = { | |
1525 | .ep = { | |
1526 | .name = ep0name, | |
1527 | .ops = &at91_ep_ops, | |
1528 | }, | |
1529 | .udc = &controller, | |
1530 | .maxpacket = 8, | |
bae4bd84 DB |
1531 | .int_mask = 1 << 0, |
1532 | }, | |
1533 | .ep[1] = { | |
1534 | .ep = { | |
1535 | .name = "ep1", | |
1536 | .ops = &at91_ep_ops, | |
1537 | }, | |
1538 | .udc = &controller, | |
1539 | .is_pingpong = 1, | |
1540 | .maxpacket = 64, | |
bae4bd84 DB |
1541 | .int_mask = 1 << 1, |
1542 | }, | |
1543 | .ep[2] = { | |
1544 | .ep = { | |
1545 | .name = "ep2", | |
1546 | .ops = &at91_ep_ops, | |
1547 | }, | |
1548 | .udc = &controller, | |
1549 | .is_pingpong = 1, | |
1550 | .maxpacket = 64, | |
bae4bd84 DB |
1551 | .int_mask = 1 << 2, |
1552 | }, | |
1553 | .ep[3] = { | |
1554 | .ep = { | |
1555 | /* could actually do bulk too */ | |
1556 | .name = "ep3-int", | |
1557 | .ops = &at91_ep_ops, | |
1558 | }, | |
1559 | .udc = &controller, | |
1560 | .maxpacket = 8, | |
bae4bd84 DB |
1561 | .int_mask = 1 << 3, |
1562 | }, | |
1563 | .ep[4] = { | |
1564 | .ep = { | |
1565 | .name = "ep4", | |
1566 | .ops = &at91_ep_ops, | |
1567 | }, | |
1568 | .udc = &controller, | |
1569 | .is_pingpong = 1, | |
1570 | .maxpacket = 256, | |
bae4bd84 DB |
1571 | .int_mask = 1 << 4, |
1572 | }, | |
1573 | .ep[5] = { | |
1574 | .ep = { | |
1575 | .name = "ep5", | |
1576 | .ops = &at91_ep_ops, | |
1577 | }, | |
1578 | .udc = &controller, | |
1579 | .is_pingpong = 1, | |
1580 | .maxpacket = 256, | |
bae4bd84 DB |
1581 | .int_mask = 1 << 5, |
1582 | }, | |
8b2e7668 | 1583 | /* ep6 and ep7 are also reserved (custom silicon might use them) */ |
bae4bd84 DB |
1584 | }; |
1585 | ||
4037242c RM |
1586 | static void at91_vbus_update(struct at91_udc *udc, unsigned value) |
1587 | { | |
1588 | value ^= udc->board.vbus_active_low; | |
1589 | if (value != udc->vbus) | |
1590 | at91_vbus_session(&udc->gadget, value); | |
1591 | } | |
1592 | ||
7d12e780 | 1593 | static irqreturn_t at91_vbus_irq(int irq, void *_udc) |
bae4bd84 DB |
1594 | { |
1595 | struct at91_udc *udc = _udc; | |
bae4bd84 DB |
1596 | |
1597 | /* vbus needs at least brief debouncing */ | |
1598 | udelay(10); | |
4037242c | 1599 | at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin)); |
bae4bd84 DB |
1600 | |
1601 | return IRQ_HANDLED; | |
1602 | } | |
1603 | ||
4037242c RM |
1604 | static void at91_vbus_timer_work(struct work_struct *work) |
1605 | { | |
1606 | struct at91_udc *udc = container_of(work, struct at91_udc, | |
1607 | vbus_timer_work); | |
1608 | ||
1609 | at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin)); | |
1610 | ||
1611 | if (!timer_pending(&udc->vbus_timer)) | |
1612 | mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); | |
1613 | } | |
1614 | ||
1615 | static void at91_vbus_timer(unsigned long data) | |
1616 | { | |
1617 | struct at91_udc *udc = (struct at91_udc *)data; | |
1618 | ||
1619 | /* | |
1620 | * If we are polling vbus it is likely that the gpio is on an | |
1621 | * bus such as i2c or spi which may sleep, so schedule some work | |
1622 | * to read the vbus gpio | |
1623 | */ | |
1624 | if (!work_pending(&udc->vbus_timer_work)) | |
1625 | schedule_work(&udc->vbus_timer_work); | |
1626 | } | |
1627 | ||
0f91349b | 1628 | static int at91_start(struct usb_gadget_driver *driver, |
b0fca50f | 1629 | int (*bind)(struct usb_gadget *)) |
bae4bd84 DB |
1630 | { |
1631 | struct at91_udc *udc = &controller; | |
1632 | int retval; | |
4f4c5e36 | 1633 | unsigned long flags; |
bae4bd84 DB |
1634 | |
1635 | if (!driver | |
7177aed4 | 1636 | || driver->max_speed < USB_SPEED_FULL |
b0fca50f | 1637 | || !bind |
bae4bd84 DB |
1638 | || !driver->setup) { |
1639 | DBG("bad parameter.\n"); | |
1640 | return -EINVAL; | |
1641 | } | |
1642 | ||
1643 | if (udc->driver) { | |
1644 | DBG("UDC already has a gadget driver\n"); | |
1645 | return -EBUSY; | |
1646 | } | |
1647 | ||
1648 | udc->driver = driver; | |
1649 | udc->gadget.dev.driver = &driver->driver; | |
839214ae | 1650 | dev_set_drvdata(&udc->gadget.dev, &driver->driver); |
bae4bd84 DB |
1651 | udc->enabled = 1; |
1652 | udc->selfpowered = 1; | |
1653 | ||
b0fca50f | 1654 | retval = bind(&udc->gadget); |
bae4bd84 | 1655 | if (retval) { |
b0fca50f | 1656 | DBG("bind() returned %d\n", retval); |
bae4bd84 | 1657 | udc->driver = NULL; |
943c4419 | 1658 | udc->gadget.dev.driver = NULL; |
839214ae | 1659 | dev_set_drvdata(&udc->gadget.dev, NULL); |
943c4419 WK |
1660 | udc->enabled = 0; |
1661 | udc->selfpowered = 0; | |
bae4bd84 DB |
1662 | return retval; |
1663 | } | |
1664 | ||
4f4c5e36 | 1665 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1666 | pullup(udc, 1); |
4f4c5e36 | 1667 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
1668 | |
1669 | DBG("bound to %s\n", driver->driver.name); | |
1670 | return 0; | |
1671 | } | |
bae4bd84 | 1672 | |
0f91349b | 1673 | static int at91_stop(struct usb_gadget_driver *driver) |
bae4bd84 DB |
1674 | { |
1675 | struct at91_udc *udc = &controller; | |
4f4c5e36 | 1676 | unsigned long flags; |
bae4bd84 | 1677 | |
6bea476c | 1678 | if (!driver || driver != udc->driver || !driver->unbind) |
bae4bd84 DB |
1679 | return -EINVAL; |
1680 | ||
4f4c5e36 | 1681 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1682 | udc->enabled = 0; |
ffd3326b | 1683 | at91_udp_write(udc, AT91_UDP_IDR, ~0); |
bae4bd84 | 1684 | pullup(udc, 0); |
4f4c5e36 | 1685 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
1686 | |
1687 | driver->unbind(&udc->gadget); | |
eb0be47d | 1688 | udc->gadget.dev.driver = NULL; |
839214ae | 1689 | dev_set_drvdata(&udc->gadget.dev, NULL); |
bae4bd84 DB |
1690 | udc->driver = NULL; |
1691 | ||
1692 | DBG("unbound from %s\n", driver->driver.name); | |
1693 | return 0; | |
1694 | } | |
bae4bd84 DB |
1695 | |
1696 | /*-------------------------------------------------------------------------*/ | |
1697 | ||
1698 | static void at91udc_shutdown(struct platform_device *dev) | |
1699 | { | |
4f4c5e36 HH |
1700 | struct at91_udc *udc = platform_get_drvdata(dev); |
1701 | unsigned long flags; | |
1702 | ||
bae4bd84 | 1703 | /* force disconnect on reboot */ |
4f4c5e36 | 1704 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1705 | pullup(platform_get_drvdata(dev), 0); |
4f4c5e36 | 1706 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
1707 | } |
1708 | ||
398acce7 | 1709 | static int __init at91udc_probe(struct platform_device *pdev) |
bae4bd84 DB |
1710 | { |
1711 | struct device *dev = &pdev->dev; | |
1712 | struct at91_udc *udc; | |
1713 | int retval; | |
ffd3326b | 1714 | struct resource *res; |
bae4bd84 DB |
1715 | |
1716 | if (!dev->platform_data) { | |
1717 | /* small (so we copy it) but critical! */ | |
1718 | DBG("missing platform_data\n"); | |
1719 | return -ENODEV; | |
1720 | } | |
1721 | ||
8b2e7668 | 1722 | if (pdev->num_resources != 2) { |
f3db6e82 | 1723 | DBG("invalid num_resources\n"); |
8b2e7668 DB |
1724 | return -ENODEV; |
1725 | } | |
1726 | if ((pdev->resource[0].flags != IORESOURCE_MEM) | |
1727 | || (pdev->resource[1].flags != IORESOURCE_IRQ)) { | |
f3db6e82 | 1728 | DBG("invalid resource type\n"); |
8b2e7668 DB |
1729 | return -ENODEV; |
1730 | } | |
1731 | ||
ffd3326b AV |
1732 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1733 | if (!res) | |
1734 | return -ENXIO; | |
1735 | ||
d8bb0fd2 | 1736 | if (!request_mem_region(res->start, resource_size(res), driver_name)) { |
bae4bd84 DB |
1737 | DBG("someone's using UDC memory\n"); |
1738 | return -EBUSY; | |
1739 | } | |
1740 | ||
1741 | /* init software state */ | |
1742 | udc = &controller; | |
1743 | udc->gadget.dev.parent = dev; | |
1744 | udc->board = *(struct at91_udc_data *) dev->platform_data; | |
1745 | udc->pdev = pdev; | |
bae4bd84 | 1746 | udc->enabled = 0; |
4f4c5e36 | 1747 | spin_lock_init(&udc->lock); |
bae4bd84 | 1748 | |
f3db6e82 DB |
1749 | /* rm9200 needs manual D+ pullup; off by default */ |
1750 | if (cpu_is_at91rm9200()) { | |
3285e0ec | 1751 | if (gpio_is_valid(udc->board.pullup_pin)) { |
f3db6e82 DB |
1752 | DBG("no D+ pullup?\n"); |
1753 | retval = -ENODEV; | |
1754 | goto fail0; | |
1755 | } | |
1756 | retval = gpio_request(udc->board.pullup_pin, "udc_pullup"); | |
1757 | if (retval) { | |
1758 | DBG("D+ pullup is busy\n"); | |
1759 | goto fail0; | |
1760 | } | |
1761 | gpio_direction_output(udc->board.pullup_pin, | |
1762 | udc->board.pullup_active_low); | |
1763 | } | |
1764 | ||
bb24280f | 1765 | /* newer chips have more FIFO memory than rm9200 */ |
bf1f0a05 | 1766 | if (cpu_is_at91sam9260() || cpu_is_at91sam9g20()) { |
bb24280f DB |
1767 | udc->ep[0].maxpacket = 64; |
1768 | udc->ep[3].maxpacket = 64; | |
1769 | udc->ep[4].maxpacket = 512; | |
1770 | udc->ep[5].maxpacket = 512; | |
23f6d914 | 1771 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
bb24280f DB |
1772 | udc->ep[3].maxpacket = 64; |
1773 | } else if (cpu_is_at91sam9263()) { | |
1774 | udc->ep[0].maxpacket = 64; | |
1775 | udc->ep[3].maxpacket = 64; | |
1776 | } | |
1777 | ||
d8bb0fd2 | 1778 | udc->udp_baseaddr = ioremap(res->start, resource_size(res)); |
ffd3326b | 1779 | if (!udc->udp_baseaddr) { |
f3db6e82 DB |
1780 | retval = -ENOMEM; |
1781 | goto fail0a; | |
ffd3326b AV |
1782 | } |
1783 | ||
1784 | udc_reinit(udc); | |
1785 | ||
bae4bd84 DB |
1786 | /* get interface and function clocks */ |
1787 | udc->iclk = clk_get(dev, "udc_clk"); | |
1788 | udc->fclk = clk_get(dev, "udpck"); | |
1789 | if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) { | |
1790 | DBG("clocks missing\n"); | |
29ba4b53 | 1791 | retval = -ENODEV; |
f3db6e82 DB |
1792 | /* NOTE: we "know" here that refcounts on these are NOPs */ |
1793 | goto fail0b; | |
bae4bd84 DB |
1794 | } |
1795 | ||
1796 | retval = device_register(&udc->gadget.dev); | |
8ab10400 RR |
1797 | if (retval < 0) { |
1798 | put_device(&udc->gadget.dev); | |
f3db6e82 | 1799 | goto fail0b; |
8ab10400 | 1800 | } |
bae4bd84 | 1801 | |
8b2e7668 DB |
1802 | /* don't do anything until we have both gadget driver and VBUS */ |
1803 | clk_enable(udc->iclk); | |
ffd3326b AV |
1804 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
1805 | at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff); | |
29ba4b53 AV |
1806 | /* Clear all pending interrupts - UDP may be used by bootloader. */ |
1807 | at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff); | |
8b2e7668 | 1808 | clk_disable(udc->iclk); |
bae4bd84 DB |
1809 | |
1810 | /* request UDC and maybe VBUS irqs */ | |
8b2e7668 | 1811 | udc->udp_irq = platform_get_irq(pdev, 0); |
f3db6e82 | 1812 | retval = request_irq(udc->udp_irq, at91_udc_irq, |
b5dd18d8 | 1813 | 0, driver_name, udc); |
f3db6e82 | 1814 | if (retval < 0) { |
8b2e7668 | 1815 | DBG("request irq %d failed\n", udc->udp_irq); |
bae4bd84 DB |
1816 | goto fail1; |
1817 | } | |
3285e0ec | 1818 | if (gpio_is_valid(udc->board.vbus_pin)) { |
f3db6e82 DB |
1819 | retval = gpio_request(udc->board.vbus_pin, "udc_vbus"); |
1820 | if (retval < 0) { | |
1821 | DBG("request vbus pin failed\n"); | |
1822 | goto fail2; | |
1823 | } | |
1824 | gpio_direction_input(udc->board.vbus_pin); | |
1825 | ||
29ba4b53 AV |
1826 | /* |
1827 | * Get the initial state of VBUS - we cannot expect | |
1828 | * a pending interrupt. | |
1829 | */ | |
4037242c RM |
1830 | udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin) ^ |
1831 | udc->board.vbus_active_low; | |
1832 | ||
1833 | if (udc->board.vbus_polled) { | |
1834 | INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work); | |
1835 | setup_timer(&udc->vbus_timer, at91_vbus_timer, | |
1836 | (unsigned long)udc); | |
1837 | mod_timer(&udc->vbus_timer, | |
1838 | jiffies + VBUS_POLL_TIMEOUT); | |
1839 | } else { | |
1840 | if (request_irq(udc->board.vbus_pin, at91_vbus_irq, | |
b5dd18d8 | 1841 | 0, driver_name, udc)) { |
4037242c RM |
1842 | DBG("request vbus irq %d failed\n", |
1843 | udc->board.vbus_pin); | |
1844 | retval = -EBUSY; | |
1845 | goto fail3; | |
1846 | } | |
bae4bd84 DB |
1847 | } |
1848 | } else { | |
1849 | DBG("no VBUS detection, assuming always-on\n"); | |
1850 | udc->vbus = 1; | |
1851 | } | |
0f91349b SAS |
1852 | retval = usb_add_gadget_udc(dev, &udc->gadget); |
1853 | if (retval) | |
1854 | goto fail4; | |
bae4bd84 | 1855 | dev_set_drvdata(dev, udc); |
8b2e7668 | 1856 | device_init_wakeup(dev, 1); |
bae4bd84 DB |
1857 | create_debug_file(udc); |
1858 | ||
1859 | INFO("%s version %s\n", driver_name, DRIVER_VERSION); | |
1860 | return 0; | |
0f91349b | 1861 | fail4: |
3285e0ec | 1862 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled) |
0f91349b | 1863 | free_irq(udc->board.vbus_pin, udc); |
f3db6e82 | 1864 | fail3: |
3285e0ec | 1865 | if (gpio_is_valid(udc->board.vbus_pin)) |
f3db6e82 DB |
1866 | gpio_free(udc->board.vbus_pin); |
1867 | fail2: | |
1868 | free_irq(udc->udp_irq, udc); | |
bae4bd84 DB |
1869 | fail1: |
1870 | device_unregister(&udc->gadget.dev); | |
f3db6e82 DB |
1871 | fail0b: |
1872 | iounmap(udc->udp_baseaddr); | |
1873 | fail0a: | |
1874 | if (cpu_is_at91rm9200()) | |
1875 | gpio_free(udc->board.pullup_pin); | |
bae4bd84 | 1876 | fail0: |
d8bb0fd2 | 1877 | release_mem_region(res->start, resource_size(res)); |
bae4bd84 DB |
1878 | DBG("%s probe failed, %d\n", driver_name, retval); |
1879 | return retval; | |
1880 | } | |
1881 | ||
398acce7 | 1882 | static int __exit at91udc_remove(struct platform_device *pdev) |
bae4bd84 | 1883 | { |
8b2e7668 | 1884 | struct at91_udc *udc = platform_get_drvdata(pdev); |
ffd3326b | 1885 | struct resource *res; |
4f4c5e36 | 1886 | unsigned long flags; |
bae4bd84 DB |
1887 | |
1888 | DBG("remove\n"); | |
1889 | ||
0f91349b | 1890 | usb_del_gadget_udc(&udc->gadget); |
6bea476c DB |
1891 | if (udc->driver) |
1892 | return -EBUSY; | |
bae4bd84 | 1893 | |
4f4c5e36 | 1894 | spin_lock_irqsave(&udc->lock, flags); |
6bea476c | 1895 | pullup(udc, 0); |
4f4c5e36 | 1896 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 | 1897 | |
8b2e7668 | 1898 | device_init_wakeup(&pdev->dev, 0); |
bae4bd84 | 1899 | remove_debug_file(udc); |
3285e0ec | 1900 | if (gpio_is_valid(udc->board.vbus_pin)) { |
bae4bd84 | 1901 | free_irq(udc->board.vbus_pin, udc); |
f3db6e82 DB |
1902 | gpio_free(udc->board.vbus_pin); |
1903 | } | |
8b2e7668 | 1904 | free_irq(udc->udp_irq, udc); |
bae4bd84 | 1905 | device_unregister(&udc->gadget.dev); |
ffd3326b AV |
1906 | |
1907 | iounmap(udc->udp_baseaddr); | |
f3db6e82 DB |
1908 | |
1909 | if (cpu_is_at91rm9200()) | |
1910 | gpio_free(udc->board.pullup_pin); | |
1911 | ||
ffd3326b | 1912 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
d8bb0fd2 | 1913 | release_mem_region(res->start, resource_size(res)); |
bae4bd84 DB |
1914 | |
1915 | clk_put(udc->iclk); | |
1916 | clk_put(udc->fclk); | |
1917 | ||
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | #ifdef CONFIG_PM | |
8b2e7668 | 1922 | static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) |
bae4bd84 | 1923 | { |
8b2e7668 DB |
1924 | struct at91_udc *udc = platform_get_drvdata(pdev); |
1925 | int wake = udc->driver && device_may_wakeup(&pdev->dev); | |
4f4c5e36 | 1926 | unsigned long flags; |
bae4bd84 | 1927 | |
8b2e7668 DB |
1928 | /* Unless we can act normally to the host (letting it wake us up |
1929 | * whenever it has work for us) force disconnect. Wakeup requires | |
1930 | * PLLB for USB events (signaling for reset, wakeup, or incoming | |
1931 | * tokens) and VBUS irqs (on systems which support them). | |
bae4bd84 | 1932 | */ |
8b2e7668 DB |
1933 | if ((!udc->suspended && udc->addr) |
1934 | || !wake | |
1935 | || at91_suspend_entering_slow_clock()) { | |
4f4c5e36 | 1936 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1937 | pullup(udc, 0); |
66e56ce7 | 1938 | wake = 0; |
4f4c5e36 | 1939 | spin_unlock_irqrestore(&udc->lock, flags); |
8b2e7668 DB |
1940 | } else |
1941 | enable_irq_wake(udc->udp_irq); | |
1942 | ||
66e56ce7 | 1943 | udc->active_suspend = wake; |
3285e0ec | 1944 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && wake) |
66e56ce7 | 1945 | enable_irq_wake(udc->board.vbus_pin); |
bae4bd84 DB |
1946 | return 0; |
1947 | } | |
1948 | ||
8b2e7668 | 1949 | static int at91udc_resume(struct platform_device *pdev) |
bae4bd84 | 1950 | { |
8b2e7668 | 1951 | struct at91_udc *udc = platform_get_drvdata(pdev); |
4f4c5e36 | 1952 | unsigned long flags; |
bae4bd84 | 1953 | |
3285e0ec | 1954 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && |
4037242c | 1955 | udc->active_suspend) |
66e56ce7 DB |
1956 | disable_irq_wake(udc->board.vbus_pin); |
1957 | ||
bae4bd84 | 1958 | /* maybe reconnect to host; if so, clocks on */ |
66e56ce7 DB |
1959 | if (udc->active_suspend) |
1960 | disable_irq_wake(udc->udp_irq); | |
4f4c5e36 HH |
1961 | else { |
1962 | spin_lock_irqsave(&udc->lock, flags); | |
66e56ce7 | 1963 | pullup(udc, 1); |
4f4c5e36 HH |
1964 | spin_unlock_irqrestore(&udc->lock, flags); |
1965 | } | |
bae4bd84 DB |
1966 | return 0; |
1967 | } | |
1968 | #else | |
1969 | #define at91udc_suspend NULL | |
1970 | #define at91udc_resume NULL | |
1971 | #endif | |
1972 | ||
dee497df | 1973 | static struct platform_driver at91_udc_driver = { |
398acce7 | 1974 | .remove = __exit_p(at91udc_remove), |
bae4bd84 DB |
1975 | .shutdown = at91udc_shutdown, |
1976 | .suspend = at91udc_suspend, | |
8b2e7668 | 1977 | .resume = at91udc_resume, |
bae4bd84 DB |
1978 | .driver = { |
1979 | .name = (char *) driver_name, | |
1980 | .owner = THIS_MODULE, | |
1981 | }, | |
1982 | }; | |
1983 | ||
398acce7 | 1984 | static int __init udc_init_module(void) |
bae4bd84 | 1985 | { |
dee497df | 1986 | return platform_driver_probe(&at91_udc_driver, at91udc_probe); |
bae4bd84 DB |
1987 | } |
1988 | module_init(udc_init_module); | |
1989 | ||
398acce7 | 1990 | static void __exit udc_exit_module(void) |
bae4bd84 | 1991 | { |
dee497df | 1992 | platform_driver_unregister(&at91_udc_driver); |
bae4bd84 DB |
1993 | } |
1994 | module_exit(udc_exit_module); | |
1995 | ||
8b2e7668 | 1996 | MODULE_DESCRIPTION("AT91 udc driver"); |
bae4bd84 DB |
1997 | MODULE_AUTHOR("Thomas Rathbone, David Brownell"); |
1998 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 1999 | MODULE_ALIAS("platform:at91_udc"); |