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b504882d LY |
1 | /* |
2 | * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved. | |
3 | * | |
4 | * Author: Li Yang <leoli@freescale.com> | |
5 | * Jiang Bo <tanya.jiang@freescale.com> | |
6 | * | |
7 | * Description: | |
8 | * Freescale high-speed USB SOC DR module device controller driver. | |
9 | * This can be found on MPC8349E/MPC8313E cpus. | |
10 | * The driver is previously named as mpc_udc. Based on bare board | |
11 | * code from Dave Liu and Shlomi Gridish. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #undef VERBOSE | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/proc_fs.h> | |
34 | #include <linux/mm.h> | |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/device.h> | |
37 | #include <linux/usb/ch9.h> | |
38 | #include <linux/usb_gadget.h> | |
39 | #include <linux/usb/otg.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/platform_device.h> | |
42 | #include <linux/fsl_devices.h> | |
43 | #include <linux/dmapool.h> | |
44 | ||
45 | #include <asm/byteorder.h> | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/system.h> | |
49 | #include <asm/unaligned.h> | |
50 | #include <asm/dma.h> | |
51 | #include <asm/cacheflush.h> | |
52 | ||
53 | #include "fsl_usb2_udc.h" | |
54 | ||
55 | #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver" | |
56 | #define DRIVER_AUTHOR "Li Yang/Jiang Bo" | |
57 | #define DRIVER_VERSION "Apr 20, 2007" | |
58 | ||
59 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) | |
60 | ||
61 | static const char driver_name[] = "fsl-usb2-udc"; | |
62 | static const char driver_desc[] = DRIVER_DESC; | |
63 | ||
64 | volatile static struct usb_dr_device *dr_regs = NULL; | |
65 | volatile static struct usb_sys_interface *usb_sys_regs = NULL; | |
66 | ||
67 | /* it is initialized in probe() */ | |
68 | static struct fsl_udc *udc_controller = NULL; | |
69 | ||
70 | static const struct usb_endpoint_descriptor | |
71 | fsl_ep0_desc = { | |
72 | .bLength = USB_DT_ENDPOINT_SIZE, | |
73 | .bDescriptorType = USB_DT_ENDPOINT, | |
74 | .bEndpointAddress = 0, | |
75 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
76 | .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, | |
77 | }; | |
78 | ||
79 | static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state); | |
80 | static int fsl_udc_resume(struct platform_device *pdev); | |
81 | static void fsl_ep_fifo_flush(struct usb_ep *_ep); | |
82 | ||
83 | #ifdef CONFIG_PPC32 | |
84 | #define fsl_readl(addr) in_le32(addr) | |
85 | #define fsl_writel(addr, val32) out_le32(val32, addr) | |
86 | #else | |
87 | #define fsl_readl(addr) readl(addr) | |
88 | #define fsl_writel(addr, val32) writel(addr, val32) | |
89 | #endif | |
90 | ||
91 | /******************************************************************** | |
92 | * Internal Used Function | |
93 | ********************************************************************/ | |
94 | /*----------------------------------------------------------------- | |
95 | * done() - retire a request; caller blocked irqs | |
96 | * @status : request status to be set, only works when | |
97 | * request is still in progress. | |
98 | *--------------------------------------------------------------*/ | |
99 | static void done(struct fsl_ep *ep, struct fsl_req *req, int status) | |
100 | { | |
101 | struct fsl_udc *udc = NULL; | |
102 | unsigned char stopped = ep->stopped; | |
103 | struct ep_td_struct *curr_td, *next_td; | |
104 | int j; | |
105 | ||
106 | udc = (struct fsl_udc *)ep->udc; | |
107 | /* Removed the req from fsl_ep->queue */ | |
108 | list_del_init(&req->queue); | |
109 | ||
110 | /* req.status should be set as -EINPROGRESS in ep_queue() */ | |
111 | if (req->req.status == -EINPROGRESS) | |
112 | req->req.status = status; | |
113 | else | |
114 | status = req->req.status; | |
115 | ||
116 | /* Free dtd for the request */ | |
117 | next_td = req->head; | |
118 | for (j = 0; j < req->dtd_count; j++) { | |
119 | curr_td = next_td; | |
120 | if (j != req->dtd_count - 1) { | |
121 | next_td = curr_td->next_td_virt; | |
122 | } | |
123 | dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); | |
124 | } | |
125 | ||
126 | if (req->mapped) { | |
127 | dma_unmap_single(ep->udc->gadget.dev.parent, | |
128 | req->req.dma, req->req.length, | |
129 | ep_is_in(ep) | |
130 | ? DMA_TO_DEVICE | |
131 | : DMA_FROM_DEVICE); | |
132 | req->req.dma = DMA_ADDR_INVALID; | |
133 | req->mapped = 0; | |
134 | } else | |
135 | dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, | |
136 | req->req.dma, req->req.length, | |
137 | ep_is_in(ep) | |
138 | ? DMA_TO_DEVICE | |
139 | : DMA_FROM_DEVICE); | |
140 | ||
141 | if (status && (status != -ESHUTDOWN)) | |
142 | VDBG("complete %s req %p stat %d len %u/%u", | |
143 | ep->ep.name, &req->req, status, | |
144 | req->req.actual, req->req.length); | |
145 | ||
146 | ep->stopped = 1; | |
147 | ||
148 | spin_unlock(&ep->udc->lock); | |
149 | /* complete() is from gadget layer, | |
150 | * eg fsg->bulk_in_complete() */ | |
151 | if (req->req.complete) | |
152 | req->req.complete(&ep->ep, &req->req); | |
153 | ||
154 | spin_lock(&ep->udc->lock); | |
155 | ep->stopped = stopped; | |
156 | } | |
157 | ||
158 | /*----------------------------------------------------------------- | |
159 | * nuke(): delete all requests related to this ep | |
160 | * called with spinlock held | |
161 | *--------------------------------------------------------------*/ | |
162 | static void nuke(struct fsl_ep *ep, int status) | |
163 | { | |
164 | ep->stopped = 1; | |
165 | ||
166 | /* Flush fifo */ | |
167 | fsl_ep_fifo_flush(&ep->ep); | |
168 | ||
169 | /* Whether this eq has request linked */ | |
170 | while (!list_empty(&ep->queue)) { | |
171 | struct fsl_req *req = NULL; | |
172 | ||
173 | req = list_entry(ep->queue.next, struct fsl_req, queue); | |
174 | done(ep, req, status); | |
175 | } | |
176 | } | |
177 | ||
178 | /*------------------------------------------------------------------ | |
179 | Internal Hardware related function | |
180 | ------------------------------------------------------------------*/ | |
181 | ||
182 | static int dr_controller_setup(struct fsl_udc *udc) | |
183 | { | |
184 | unsigned int tmp = 0, portctrl = 0, ctrl = 0; | |
185 | unsigned long timeout; | |
186 | #define FSL_UDC_RESET_TIMEOUT 1000 | |
187 | ||
188 | /* before here, make sure dr_regs has been initialized */ | |
189 | if (!udc) | |
190 | return -EINVAL; | |
191 | ||
192 | /* Stop and reset the usb controller */ | |
193 | tmp = fsl_readl(&dr_regs->usbcmd); | |
194 | tmp &= ~USB_CMD_RUN_STOP; | |
195 | fsl_writel(tmp, &dr_regs->usbcmd); | |
196 | ||
197 | tmp = fsl_readl(&dr_regs->usbcmd); | |
198 | tmp |= USB_CMD_CTRL_RESET; | |
199 | fsl_writel(tmp, &dr_regs->usbcmd); | |
200 | ||
201 | /* Wait for reset to complete */ | |
202 | timeout = jiffies + FSL_UDC_RESET_TIMEOUT; | |
203 | while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { | |
204 | if (time_after(jiffies, timeout)) { | |
205 | ERR("udc reset timeout! \n"); | |
206 | return -ETIMEDOUT; | |
207 | } | |
208 | cpu_relax(); | |
209 | } | |
210 | ||
211 | /* Set the controller as device mode */ | |
212 | tmp = fsl_readl(&dr_regs->usbmode); | |
213 | tmp |= USB_MODE_CTRL_MODE_DEVICE; | |
214 | /* Disable Setup Lockout */ | |
215 | tmp |= USB_MODE_SETUP_LOCK_OFF; | |
216 | fsl_writel(tmp, &dr_regs->usbmode); | |
217 | ||
218 | /* Clear the setup status */ | |
219 | fsl_writel(0, &dr_regs->usbsts); | |
220 | ||
221 | tmp = udc->ep_qh_dma; | |
222 | tmp &= USB_EP_LIST_ADDRESS_MASK; | |
223 | fsl_writel(tmp, &dr_regs->endpointlistaddr); | |
224 | ||
225 | VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", | |
226 | (int)udc->ep_qh, (int)tmp, | |
227 | fsl_readl(&dr_regs->endpointlistaddr)); | |
228 | ||
229 | /* Config PHY interface */ | |
230 | portctrl = fsl_readl(&dr_regs->portsc1); | |
fcbd9639 | 231 | portctrl &= ~(PORTSCX_PHY_TYPE_SEL & PORTSCX_PORT_WIDTH); |
b504882d LY |
232 | switch (udc->phy_mode) { |
233 | case FSL_USB2_PHY_ULPI: | |
234 | portctrl |= PORTSCX_PTS_ULPI; | |
235 | break; | |
b504882d | 236 | case FSL_USB2_PHY_UTMI_WIDE: |
fcbd9639 LY |
237 | portctrl |= PORTSCX_PTW_16BIT; |
238 | /* fall through */ | |
239 | case FSL_USB2_PHY_UTMI: | |
b504882d LY |
240 | portctrl |= PORTSCX_PTS_UTMI; |
241 | break; | |
242 | case FSL_USB2_PHY_SERIAL: | |
243 | portctrl |= PORTSCX_PTS_FSLS; | |
244 | break; | |
245 | default: | |
246 | return -EINVAL; | |
247 | } | |
248 | fsl_writel(portctrl, &dr_regs->portsc1); | |
249 | ||
250 | /* Config control enable i/o output, cpu endian register */ | |
251 | ctrl = __raw_readl(&usb_sys_regs->control); | |
252 | ctrl |= USB_CTRL_IOENB; | |
253 | __raw_writel(ctrl, &usb_sys_regs->control); | |
254 | ||
255 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
256 | /* Turn on cache snooping hardware, since some PowerPC platforms | |
257 | * wholly rely on hardware to deal with cache coherent. */ | |
258 | ||
259 | /* Setup Snooping for all the 4GB space */ | |
260 | tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ | |
261 | __raw_writel(tmp, &usb_sys_regs->snoop1); | |
262 | tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ | |
263 | __raw_writel(tmp, &usb_sys_regs->snoop2); | |
264 | #endif | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | /* Enable DR irq and set controller to run state */ | |
270 | static void dr_controller_run(struct fsl_udc *udc) | |
271 | { | |
272 | u32 temp; | |
273 | ||
274 | /* Enable DR irq reg */ | |
275 | temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN | |
276 | | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN | |
277 | | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; | |
278 | ||
279 | fsl_writel(temp, &dr_regs->usbintr); | |
280 | ||
281 | /* Clear stopped bit */ | |
282 | udc->stopped = 0; | |
283 | ||
284 | /* Set the controller as device mode */ | |
285 | temp = fsl_readl(&dr_regs->usbmode); | |
286 | temp |= USB_MODE_CTRL_MODE_DEVICE; | |
287 | fsl_writel(temp, &dr_regs->usbmode); | |
288 | ||
289 | /* Set controller to Run */ | |
290 | temp = fsl_readl(&dr_regs->usbcmd); | |
291 | temp |= USB_CMD_RUN_STOP; | |
292 | fsl_writel(temp, &dr_regs->usbcmd); | |
293 | ||
294 | return; | |
295 | } | |
296 | ||
297 | static void dr_controller_stop(struct fsl_udc *udc) | |
298 | { | |
299 | unsigned int tmp; | |
300 | ||
301 | /* disable all INTR */ | |
302 | fsl_writel(0, &dr_regs->usbintr); | |
303 | ||
304 | /* Set stopped bit for isr */ | |
305 | udc->stopped = 1; | |
306 | ||
307 | /* disable IO output */ | |
308 | /* usb_sys_regs->control = 0; */ | |
309 | ||
310 | /* set controller to Stop */ | |
311 | tmp = fsl_readl(&dr_regs->usbcmd); | |
312 | tmp &= ~USB_CMD_RUN_STOP; | |
313 | fsl_writel(tmp, &dr_regs->usbcmd); | |
314 | ||
315 | return; | |
316 | } | |
317 | ||
318 | void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type) | |
319 | { | |
320 | unsigned int tmp_epctrl = 0; | |
321 | ||
322 | tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
323 | if (dir) { | |
324 | if (ep_num) | |
325 | tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; | |
326 | tmp_epctrl |= EPCTRL_TX_ENABLE; | |
327 | tmp_epctrl |= ((unsigned int)(ep_type) | |
328 | << EPCTRL_TX_EP_TYPE_SHIFT); | |
329 | } else { | |
330 | if (ep_num) | |
331 | tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; | |
332 | tmp_epctrl |= EPCTRL_RX_ENABLE; | |
333 | tmp_epctrl |= ((unsigned int)(ep_type) | |
334 | << EPCTRL_RX_EP_TYPE_SHIFT); | |
335 | } | |
336 | ||
337 | fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); | |
338 | } | |
339 | ||
340 | static void | |
341 | dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) | |
342 | { | |
343 | u32 tmp_epctrl = 0; | |
344 | ||
345 | tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
346 | ||
347 | if (value) { | |
348 | /* set the stall bit */ | |
349 | if (dir) | |
350 | tmp_epctrl |= EPCTRL_TX_EP_STALL; | |
351 | else | |
352 | tmp_epctrl |= EPCTRL_RX_EP_STALL; | |
353 | } else { | |
354 | /* clear the stall bit and reset data toggle */ | |
355 | if (dir) { | |
356 | tmp_epctrl &= ~EPCTRL_TX_EP_STALL; | |
357 | tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; | |
358 | } else { | |
359 | tmp_epctrl &= ~EPCTRL_RX_EP_STALL; | |
360 | tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; | |
361 | } | |
362 | } | |
363 | fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); | |
364 | } | |
365 | ||
366 | /* Get stall status of a specific ep | |
367 | Return: 0: not stalled; 1:stalled */ | |
368 | static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) | |
369 | { | |
370 | u32 epctrl; | |
371 | ||
372 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
373 | if (dir) | |
374 | return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; | |
375 | else | |
376 | return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; | |
377 | } | |
378 | ||
379 | /******************************************************************** | |
380 | Internal Structure Build up functions | |
381 | ********************************************************************/ | |
382 | ||
383 | /*------------------------------------------------------------------ | |
384 | * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH | |
385 | * @zlt: Zero Length Termination Select (1: disable; 0: enable) | |
386 | * @mult: Mult field | |
387 | ------------------------------------------------------------------*/ | |
388 | static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, | |
389 | unsigned char dir, unsigned char ep_type, | |
390 | unsigned int max_pkt_len, | |
391 | unsigned int zlt, unsigned char mult) | |
392 | { | |
393 | struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; | |
394 | unsigned int tmp = 0; | |
395 | ||
396 | /* set the Endpoint Capabilites in QH */ | |
397 | switch (ep_type) { | |
398 | case USB_ENDPOINT_XFER_CONTROL: | |
399 | /* Interrupt On Setup (IOS). for control ep */ | |
400 | tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) | |
401 | | EP_QUEUE_HEAD_IOS; | |
402 | break; | |
403 | case USB_ENDPOINT_XFER_ISOC: | |
404 | tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) | |
405 | | (mult << EP_QUEUE_HEAD_MULT_POS); | |
406 | break; | |
407 | case USB_ENDPOINT_XFER_BULK: | |
408 | case USB_ENDPOINT_XFER_INT: | |
409 | tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; | |
410 | break; | |
411 | default: | |
412 | VDBG("error ep type is %d", ep_type); | |
413 | return; | |
414 | } | |
415 | if (zlt) | |
416 | tmp |= EP_QUEUE_HEAD_ZLT_SEL; | |
417 | p_QH->max_pkt_length = cpu_to_le32(tmp); | |
418 | ||
419 | return; | |
420 | } | |
421 | ||
422 | /* Setup qh structure and ep register for ep0. */ | |
423 | static void ep0_setup(struct fsl_udc *udc) | |
424 | { | |
425 | /* the intialization of an ep includes: fields in QH, Regs, | |
426 | * fsl_ep struct */ | |
427 | struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, | |
428 | USB_MAX_CTRL_PAYLOAD, 0, 0); | |
429 | struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, | |
430 | USB_MAX_CTRL_PAYLOAD, 0, 0); | |
431 | dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); | |
432 | dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); | |
433 | ||
434 | return; | |
435 | ||
436 | } | |
437 | ||
438 | /*********************************************************************** | |
439 | Endpoint Management Functions | |
440 | ***********************************************************************/ | |
441 | ||
442 | /*------------------------------------------------------------------------- | |
443 | * when configurations are set, or when interface settings change | |
444 | * for example the do_set_interface() in gadget layer, | |
445 | * the driver will enable or disable the relevant endpoints | |
446 | * ep0 doesn't use this routine. It is always enabled. | |
447 | -------------------------------------------------------------------------*/ | |
448 | static int fsl_ep_enable(struct usb_ep *_ep, | |
449 | const struct usb_endpoint_descriptor *desc) | |
450 | { | |
451 | struct fsl_udc *udc = NULL; | |
452 | struct fsl_ep *ep = NULL; | |
453 | unsigned short max = 0; | |
454 | unsigned char mult = 0, zlt; | |
455 | int retval = -EINVAL; | |
456 | unsigned long flags = 0; | |
457 | ||
458 | ep = container_of(_ep, struct fsl_ep, ep); | |
459 | ||
460 | /* catch various bogus parameters */ | |
461 | if (!_ep || !desc || ep->desc | |
462 | || (desc->bDescriptorType != USB_DT_ENDPOINT)) | |
463 | return -EINVAL; | |
464 | ||
465 | udc = ep->udc; | |
466 | ||
467 | if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) | |
468 | return -ESHUTDOWN; | |
469 | ||
470 | max = le16_to_cpu(desc->wMaxPacketSize); | |
471 | ||
472 | /* Disable automatic zlp generation. Driver is reponsible to indicate | |
473 | * explicitly through req->req.zero. This is needed to enable multi-td | |
474 | * request. */ | |
475 | zlt = 1; | |
476 | ||
477 | /* Assume the max packet size from gadget is always correct */ | |
478 | switch (desc->bmAttributes & 0x03) { | |
479 | case USB_ENDPOINT_XFER_CONTROL: | |
480 | case USB_ENDPOINT_XFER_BULK: | |
481 | case USB_ENDPOINT_XFER_INT: | |
482 | /* mult = 0. Execute N Transactions as demonstrated by | |
483 | * the USB variable length packet protocol where N is | |
484 | * computed using the Maximum Packet Length (dQH) and | |
485 | * the Total Bytes field (dTD) */ | |
486 | mult = 0; | |
487 | break; | |
488 | case USB_ENDPOINT_XFER_ISOC: | |
489 | /* Calculate transactions needed for high bandwidth iso */ | |
490 | mult = (unsigned char)(1 + ((max >> 11) & 0x03)); | |
491 | max = max & 0x8ff; /* bit 0~10 */ | |
492 | /* 3 transactions at most */ | |
493 | if (mult > 3) | |
494 | goto en_done; | |
495 | break; | |
496 | default: | |
497 | goto en_done; | |
498 | } | |
499 | ||
500 | spin_lock_irqsave(&udc->lock, flags); | |
501 | ep->ep.maxpacket = max; | |
502 | ep->desc = desc; | |
503 | ep->stopped = 0; | |
504 | ||
505 | /* Controller related setup */ | |
506 | /* Init EPx Queue Head (Ep Capabilites field in QH | |
507 | * according to max, zlt, mult) */ | |
508 | struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), | |
509 | (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) | |
510 | ? USB_SEND : USB_RECV), | |
511 | (unsigned char) (desc->bmAttributes | |
512 | & USB_ENDPOINT_XFERTYPE_MASK), | |
513 | max, zlt, mult); | |
514 | ||
515 | /* Init endpoint ctrl register */ | |
516 | dr_ep_setup((unsigned char) ep_index(ep), | |
517 | (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) | |
518 | ? USB_SEND : USB_RECV), | |
519 | (unsigned char) (desc->bmAttributes | |
520 | & USB_ENDPOINT_XFERTYPE_MASK)); | |
521 | ||
522 | spin_unlock_irqrestore(&udc->lock, flags); | |
523 | retval = 0; | |
524 | ||
525 | VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name, | |
526 | ep->desc->bEndpointAddress & 0x0f, | |
527 | (desc->bEndpointAddress & USB_DIR_IN) | |
528 | ? "in" : "out", max); | |
529 | en_done: | |
530 | return retval; | |
531 | } | |
532 | ||
533 | /*--------------------------------------------------------------------- | |
534 | * @ep : the ep being unconfigured. May not be ep0 | |
535 | * Any pending and uncomplete req will complete with status (-ESHUTDOWN) | |
536 | *---------------------------------------------------------------------*/ | |
537 | static int fsl_ep_disable(struct usb_ep *_ep) | |
538 | { | |
539 | struct fsl_udc *udc = NULL; | |
540 | struct fsl_ep *ep = NULL; | |
541 | unsigned long flags = 0; | |
542 | u32 epctrl; | |
543 | int ep_num; | |
544 | ||
545 | ep = container_of(_ep, struct fsl_ep, ep); | |
546 | if (!_ep || !ep->desc) { | |
547 | VDBG("%s not enabled", _ep ? ep->ep.name : NULL); | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
551 | /* disable ep on controller */ | |
552 | ep_num = ep_index(ep); | |
553 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
554 | if (ep_is_in(ep)) | |
555 | epctrl &= ~EPCTRL_TX_ENABLE; | |
556 | else | |
557 | epctrl &= ~EPCTRL_RX_ENABLE; | |
558 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); | |
559 | ||
560 | udc = (struct fsl_udc *)ep->udc; | |
561 | spin_lock_irqsave(&udc->lock, flags); | |
562 | ||
563 | /* nuke all pending requests (does flush) */ | |
564 | nuke(ep, -ESHUTDOWN); | |
565 | ||
566 | ep->desc = 0; | |
567 | ep->stopped = 1; | |
568 | spin_unlock_irqrestore(&udc->lock, flags); | |
569 | ||
570 | VDBG("disabled %s OK", _ep->name); | |
571 | return 0; | |
572 | } | |
573 | ||
574 | /*--------------------------------------------------------------------- | |
575 | * allocate a request object used by this endpoint | |
576 | * the main operation is to insert the req->queue to the eq->queue | |
577 | * Returns the request, or null if one could not be allocated | |
578 | *---------------------------------------------------------------------*/ | |
579 | static struct usb_request * | |
580 | fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) | |
581 | { | |
582 | struct fsl_req *req = NULL; | |
583 | ||
584 | req = kzalloc(sizeof *req, gfp_flags); | |
585 | if (!req) | |
586 | return NULL; | |
587 | ||
588 | req->req.dma = DMA_ADDR_INVALID; | |
589 | INIT_LIST_HEAD(&req->queue); | |
590 | ||
591 | return &req->req; | |
592 | } | |
593 | ||
594 | static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
595 | { | |
596 | struct fsl_req *req = NULL; | |
597 | ||
598 | req = container_of(_req, struct fsl_req, req); | |
599 | ||
600 | if (_req) | |
601 | kfree(req); | |
602 | } | |
603 | ||
604 | /*------------------------------------------------------------------ | |
605 | * Allocate an I/O buffer | |
606 | *---------------------------------------------------------------------*/ | |
607 | static void *fsl_alloc_buffer(struct usb_ep *_ep, unsigned bytes, | |
608 | dma_addr_t *dma, gfp_t gfp_flags) | |
609 | { | |
610 | struct fsl_ep *ep; | |
611 | ||
612 | if (!_ep) | |
613 | return NULL; | |
614 | ||
615 | ep = container_of(_ep, struct fsl_ep, ep); | |
616 | ||
617 | return dma_alloc_coherent(ep->udc->gadget.dev.parent, | |
618 | bytes, dma, gfp_flags); | |
619 | } | |
620 | ||
621 | /*------------------------------------------------------------------ | |
622 | * frees an i/o buffer | |
623 | *---------------------------------------------------------------------*/ | |
624 | static void fsl_free_buffer(struct usb_ep *_ep, void *buf, | |
625 | dma_addr_t dma, unsigned bytes) | |
626 | { | |
627 | struct fsl_ep *ep; | |
628 | ||
629 | if (!_ep) | |
fcbd9639 | 630 | return; |
b504882d LY |
631 | |
632 | ep = container_of(_ep, struct fsl_ep, ep); | |
633 | ||
634 | dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma); | |
635 | } | |
636 | ||
637 | /*-------------------------------------------------------------------------*/ | |
638 | static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) | |
639 | { | |
640 | int i = ep_index(ep) * 2 + ep_is_in(ep); | |
641 | u32 temp, bitmask, tmp_stat; | |
642 | struct ep_queue_head *dQH = &ep->udc->ep_qh[i]; | |
643 | ||
644 | /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); | |
645 | VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ | |
646 | ||
647 | bitmask = ep_is_in(ep) | |
648 | ? (1 << (ep_index(ep) + 16)) | |
649 | : (1 << (ep_index(ep))); | |
650 | ||
651 | /* check if the pipe is empty */ | |
652 | if (!(list_empty(&ep->queue))) { | |
653 | /* Add td to the end */ | |
654 | struct fsl_req *lastreq; | |
655 | lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); | |
656 | lastreq->tail->next_td_ptr = | |
657 | cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK); | |
658 | /* Read prime bit, if 1 goto done */ | |
659 | if (fsl_readl(&dr_regs->endpointprime) & bitmask) | |
660 | goto out; | |
661 | ||
662 | do { | |
663 | /* Set ATDTW bit in USBCMD */ | |
664 | temp = fsl_readl(&dr_regs->usbcmd); | |
665 | fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); | |
666 | ||
667 | /* Read correct status bit */ | |
668 | tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; | |
669 | ||
670 | } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); | |
671 | ||
672 | /* Write ATDTW bit to 0 */ | |
673 | temp = fsl_readl(&dr_regs->usbcmd); | |
674 | fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); | |
675 | ||
676 | if (tmp_stat) | |
677 | goto out; | |
678 | } | |
679 | ||
680 | /* Write dQH next pointer and terminate bit to 0 */ | |
681 | temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; | |
682 | dQH->next_dtd_ptr = cpu_to_le32(temp); | |
683 | ||
684 | /* Clear active and halt bit */ | |
685 | temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE | |
686 | | EP_QUEUE_HEAD_STATUS_HALT)); | |
687 | dQH->size_ioc_int_sts &= temp; | |
688 | ||
689 | /* Prime endpoint by writing 1 to ENDPTPRIME */ | |
690 | temp = ep_is_in(ep) | |
691 | ? (1 << (ep_index(ep) + 16)) | |
692 | : (1 << (ep_index(ep))); | |
693 | fsl_writel(temp, &dr_regs->endpointprime); | |
694 | out: | |
695 | return 0; | |
696 | } | |
697 | ||
698 | /* Fill in the dTD structure | |
699 | * @req: request that the transfer belongs to | |
700 | * @length: return actually data length of the dTD | |
701 | * @dma: return dma address of the dTD | |
702 | * @is_last: return flag if it is the last dTD of the request | |
703 | * return: pointer to the built dTD */ | |
704 | static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, | |
705 | dma_addr_t *dma, int *is_last) | |
706 | { | |
707 | u32 swap_temp; | |
708 | struct ep_td_struct *dtd; | |
709 | ||
710 | /* how big will this transfer be? */ | |
711 | *length = min(req->req.length - req->req.actual, | |
712 | (unsigned)EP_MAX_LENGTH_TRANSFER); | |
713 | ||
714 | dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma); | |
715 | if (dtd == NULL) | |
716 | return dtd; | |
717 | ||
718 | dtd->td_dma = *dma; | |
719 | /* Clear reserved field */ | |
720 | swap_temp = cpu_to_le32(dtd->size_ioc_sts); | |
721 | swap_temp &= ~DTD_RESERVED_FIELDS; | |
722 | dtd->size_ioc_sts = cpu_to_le32(swap_temp); | |
723 | ||
724 | /* Init all of buffer page pointers */ | |
725 | swap_temp = (u32) (req->req.dma + req->req.actual); | |
726 | dtd->buff_ptr0 = cpu_to_le32(swap_temp); | |
727 | dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000); | |
728 | dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000); | |
729 | dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000); | |
730 | dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000); | |
731 | ||
732 | req->req.actual += *length; | |
733 | ||
734 | /* zlp is needed if req->req.zero is set */ | |
735 | if (req->req.zero) { | |
736 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) | |
737 | *is_last = 1; | |
738 | else | |
739 | *is_last = 0; | |
740 | } else if (req->req.length == req->req.actual) | |
741 | *is_last = 1; | |
742 | else | |
743 | *is_last = 0; | |
744 | ||
745 | if ((*is_last) == 0) | |
746 | VDBG("multi-dtd request!\n"); | |
747 | /* Fill in the transfer size; set active bit */ | |
748 | swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); | |
749 | ||
750 | /* Enable interrupt for the last dtd of a request */ | |
751 | if (*is_last && !req->req.no_interrupt) | |
752 | swap_temp |= DTD_IOC; | |
753 | ||
754 | dtd->size_ioc_sts = cpu_to_le32(swap_temp); | |
755 | ||
756 | mb(); | |
757 | ||
758 | VDBG("length = %d address= 0x%x", *length, (int)*dma); | |
759 | ||
760 | return dtd; | |
761 | } | |
762 | ||
763 | /* Generate dtd chain for a request */ | |
764 | static int fsl_req_to_dtd(struct fsl_req *req) | |
765 | { | |
766 | unsigned count; | |
767 | int is_last; | |
768 | int is_first =1; | |
769 | struct ep_td_struct *last_dtd = NULL, *dtd; | |
770 | dma_addr_t dma; | |
771 | ||
772 | do { | |
773 | dtd = fsl_build_dtd(req, &count, &dma, &is_last); | |
774 | if (dtd == NULL) | |
775 | return -ENOMEM; | |
776 | ||
777 | if (is_first) { | |
778 | is_first = 0; | |
779 | req->head = dtd; | |
780 | } else { | |
781 | last_dtd->next_td_ptr = cpu_to_le32(dma); | |
782 | last_dtd->next_td_virt = dtd; | |
783 | } | |
784 | last_dtd = dtd; | |
785 | ||
786 | req->dtd_count++; | |
787 | } while (!is_last); | |
788 | ||
789 | dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE); | |
790 | ||
791 | req->tail = dtd; | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | /* queues (submits) an I/O request to an endpoint */ | |
797 | static int | |
798 | fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |
799 | { | |
800 | struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); | |
801 | struct fsl_req *req = container_of(_req, struct fsl_req, req); | |
802 | struct fsl_udc *udc; | |
803 | unsigned long flags; | |
804 | int is_iso = 0; | |
805 | ||
806 | /* catch various bogus parameters */ | |
807 | if (!_req || !req->req.complete || !req->req.buf | |
808 | || !list_empty(&req->queue)) { | |
809 | VDBG("%s, bad params\n", __FUNCTION__); | |
810 | return -EINVAL; | |
811 | } | |
812 | if (!_ep || (!ep->desc && ep_index(ep))) { | |
813 | VDBG("%s, bad ep\n", __FUNCTION__); | |
814 | return -EINVAL; | |
815 | } | |
816 | if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
817 | if (req->req.length > ep->ep.maxpacket) | |
818 | return -EMSGSIZE; | |
819 | is_iso = 1; | |
820 | } | |
821 | ||
822 | udc = ep->udc; | |
823 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) | |
824 | return -ESHUTDOWN; | |
825 | ||
826 | req->ep = ep; | |
827 | ||
828 | /* map virtual address to hardware */ | |
829 | if (req->req.dma == DMA_ADDR_INVALID) { | |
830 | req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, | |
831 | req->req.buf, | |
832 | req->req.length, ep_is_in(ep) | |
833 | ? DMA_TO_DEVICE | |
834 | : DMA_FROM_DEVICE); | |
835 | req->mapped = 1; | |
836 | } else { | |
837 | dma_sync_single_for_device(ep->udc->gadget.dev.parent, | |
838 | req->req.dma, req->req.length, | |
839 | ep_is_in(ep) | |
840 | ? DMA_TO_DEVICE | |
841 | : DMA_FROM_DEVICE); | |
842 | req->mapped = 0; | |
843 | } | |
844 | ||
845 | req->req.status = -EINPROGRESS; | |
846 | req->req.actual = 0; | |
847 | req->dtd_count = 0; | |
848 | ||
849 | spin_lock_irqsave(&udc->lock, flags); | |
850 | ||
851 | /* build dtds and push them to device queue */ | |
852 | if (!fsl_req_to_dtd(req)) { | |
853 | fsl_queue_td(ep, req); | |
854 | } else { | |
855 | spin_unlock_irqrestore(&udc->lock, flags); | |
856 | return -ENOMEM; | |
857 | } | |
858 | ||
859 | /* Update ep0 state */ | |
860 | if ((ep_index(ep) == 0)) | |
861 | udc->ep0_state = DATA_STATE_XMIT; | |
862 | ||
863 | /* irq handler advances the queue */ | |
864 | if (req != NULL) | |
865 | list_add_tail(&req->queue, &ep->queue); | |
866 | spin_unlock_irqrestore(&udc->lock, flags); | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | /* dequeues (cancels, unlinks) an I/O request from an endpoint */ | |
872 | static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
873 | { | |
874 | struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); | |
875 | struct fsl_req *req; | |
876 | unsigned long flags; | |
877 | int ep_num, stopped, ret = 0; | |
878 | u32 epctrl; | |
879 | ||
880 | if (!_ep || !_req) | |
881 | return -EINVAL; | |
882 | ||
883 | spin_lock_irqsave(&ep->udc->lock, flags); | |
884 | stopped = ep->stopped; | |
885 | ||
886 | /* Stop the ep before we deal with the queue */ | |
887 | ep->stopped = 1; | |
888 | ep_num = ep_index(ep); | |
889 | epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
890 | if (ep_is_in(ep)) | |
891 | epctrl &= ~EPCTRL_TX_ENABLE; | |
892 | else | |
893 | epctrl &= ~EPCTRL_RX_ENABLE; | |
894 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); | |
895 | ||
896 | /* make sure it's actually queued on this endpoint */ | |
897 | list_for_each_entry(req, &ep->queue, queue) { | |
898 | if (&req->req == _req) | |
899 | break; | |
900 | } | |
901 | if (&req->req != _req) { | |
902 | ret = -EINVAL; | |
903 | goto out; | |
904 | } | |
905 | ||
906 | /* The request is in progress, or completed but not dequeued */ | |
907 | if (ep->queue.next == &req->queue) { | |
908 | _req->status = -ECONNRESET; | |
909 | fsl_ep_fifo_flush(_ep); /* flush current transfer */ | |
910 | ||
911 | /* The request isn't the last request in this ep queue */ | |
912 | if (req->queue.next != &ep->queue) { | |
913 | struct ep_queue_head *qh; | |
914 | struct fsl_req *next_req; | |
915 | ||
916 | qh = ep->qh; | |
917 | next_req = list_entry(req->queue.next, struct fsl_req, | |
918 | queue); | |
919 | ||
920 | /* Point the QH to the first TD of next request */ | |
921 | fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr); | |
922 | } | |
923 | ||
924 | /* The request hasn't been processed, patch up the TD chain */ | |
925 | } else { | |
926 | struct fsl_req *prev_req; | |
927 | ||
928 | prev_req = list_entry(req->queue.prev, struct fsl_req, queue); | |
929 | fsl_writel(fsl_readl(&req->tail->next_td_ptr), | |
930 | &prev_req->tail->next_td_ptr); | |
931 | ||
932 | } | |
933 | ||
934 | done(ep, req, -ECONNRESET); | |
935 | ||
936 | /* Enable EP */ | |
937 | out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); | |
938 | if (ep_is_in(ep)) | |
939 | epctrl |= EPCTRL_TX_ENABLE; | |
940 | else | |
941 | epctrl |= EPCTRL_RX_ENABLE; | |
942 | fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); | |
943 | ep->stopped = stopped; | |
944 | ||
945 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
946 | return ret; | |
947 | } | |
948 | ||
949 | /*-------------------------------------------------------------------------*/ | |
950 | ||
951 | /*----------------------------------------------------------------- | |
952 | * modify the endpoint halt feature | |
953 | * @ep: the non-isochronous endpoint being stalled | |
954 | * @value: 1--set halt 0--clear halt | |
955 | * Returns zero, or a negative error code. | |
956 | *----------------------------------------------------------------*/ | |
957 | static int fsl_ep_set_halt(struct usb_ep *_ep, int value) | |
958 | { | |
959 | struct fsl_ep *ep = NULL; | |
960 | unsigned long flags = 0; | |
961 | int status = -EOPNOTSUPP; /* operation not supported */ | |
962 | unsigned char ep_dir = 0, ep_num = 0; | |
963 | struct fsl_udc *udc = NULL; | |
964 | ||
965 | ep = container_of(_ep, struct fsl_ep, ep); | |
966 | udc = ep->udc; | |
967 | if (!_ep || !ep->desc) { | |
968 | status = -EINVAL; | |
969 | goto out; | |
970 | } | |
971 | ||
972 | if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
973 | status = -EOPNOTSUPP; | |
974 | goto out; | |
975 | } | |
976 | ||
977 | /* Attempt to halt IN ep will fail if any transfer requests | |
978 | * are still queue */ | |
979 | if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { | |
980 | status = -EAGAIN; | |
981 | goto out; | |
982 | } | |
983 | ||
984 | status = 0; | |
985 | ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; | |
986 | ep_num = (unsigned char)(ep_index(ep)); | |
987 | spin_lock_irqsave(&ep->udc->lock, flags); | |
988 | dr_ep_change_stall(ep_num, ep_dir, value); | |
989 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
990 | ||
991 | if (ep_index(ep) == 0) { | |
992 | udc->ep0_state = WAIT_FOR_SETUP; | |
993 | udc->ep0_dir = 0; | |
994 | } | |
995 | out: | |
996 | VDBG(" %s %s halt stat %d", ep->ep.name, | |
997 | value ? "set" : "clear", status); | |
998 | ||
999 | return status; | |
1000 | } | |
1001 | ||
1002 | static void fsl_ep_fifo_flush(struct usb_ep *_ep) | |
1003 | { | |
1004 | struct fsl_ep *ep; | |
1005 | int ep_num, ep_dir; | |
1006 | u32 bits; | |
1007 | unsigned long timeout; | |
1008 | #define FSL_UDC_FLUSH_TIMEOUT 1000 | |
1009 | ||
1010 | if (!_ep) { | |
1011 | return; | |
1012 | } else { | |
1013 | ep = container_of(_ep, struct fsl_ep, ep); | |
1014 | if (!ep->desc) | |
1015 | return; | |
1016 | } | |
1017 | ep_num = ep_index(ep); | |
1018 | ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; | |
1019 | ||
1020 | if (ep_num == 0) | |
1021 | bits = (1 << 16) | 1; | |
1022 | else if (ep_dir == USB_SEND) | |
1023 | bits = 1 << (16 + ep_num); | |
1024 | else | |
1025 | bits = 1 << ep_num; | |
1026 | ||
1027 | timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; | |
1028 | do { | |
1029 | fsl_writel(bits, &dr_regs->endptflush); | |
1030 | ||
1031 | /* Wait until flush complete */ | |
1032 | while (fsl_readl(&dr_regs->endptflush)) { | |
1033 | if (time_after(jiffies, timeout)) { | |
1034 | ERR("ep flush timeout\n"); | |
1035 | return; | |
1036 | } | |
1037 | cpu_relax(); | |
1038 | } | |
1039 | /* See if we need to flush again */ | |
1040 | } while (fsl_readl(&dr_regs->endptstatus) & bits); | |
1041 | } | |
1042 | ||
1043 | static struct usb_ep_ops fsl_ep_ops = { | |
1044 | .enable = fsl_ep_enable, | |
1045 | .disable = fsl_ep_disable, | |
1046 | ||
1047 | .alloc_request = fsl_alloc_request, | |
1048 | .free_request = fsl_free_request, | |
1049 | ||
1050 | .alloc_buffer = fsl_alloc_buffer, | |
1051 | .free_buffer = fsl_free_buffer, | |
1052 | ||
1053 | .queue = fsl_ep_queue, | |
1054 | .dequeue = fsl_ep_dequeue, | |
1055 | ||
1056 | .set_halt = fsl_ep_set_halt, | |
1057 | .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ | |
1058 | }; | |
1059 | ||
1060 | /*------------------------------------------------------------------------- | |
1061 | Gadget Driver Layer Operations | |
1062 | -------------------------------------------------------------------------*/ | |
1063 | ||
1064 | /*---------------------------------------------------------------------- | |
1065 | * Get the current frame number (from DR frame_index Reg ) | |
1066 | *----------------------------------------------------------------------*/ | |
1067 | static int fsl_get_frame(struct usb_gadget *gadget) | |
1068 | { | |
1069 | return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); | |
1070 | } | |
1071 | ||
1072 | /*----------------------------------------------------------------------- | |
1073 | * Tries to wake up the host connected to this gadget | |
1074 | -----------------------------------------------------------------------*/ | |
1075 | static int fsl_wakeup(struct usb_gadget *gadget) | |
1076 | { | |
1077 | struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); | |
1078 | u32 portsc; | |
1079 | ||
1080 | /* Remote wakeup feature not enabled by host */ | |
1081 | if (!udc->remote_wakeup) | |
1082 | return -ENOTSUPP; | |
1083 | ||
1084 | portsc = fsl_readl(&dr_regs->portsc1); | |
1085 | /* not suspended? */ | |
1086 | if (!(portsc & PORTSCX_PORT_SUSPEND)) | |
1087 | return 0; | |
1088 | /* trigger force resume */ | |
1089 | portsc |= PORTSCX_PORT_FORCE_RESUME; | |
1090 | fsl_writel(portsc, &dr_regs->portsc1); | |
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | static int can_pullup(struct fsl_udc *udc) | |
1095 | { | |
1096 | return udc->driver && udc->softconnect && udc->vbus_active; | |
1097 | } | |
1098 | ||
1099 | /* Notify controller that VBUS is powered, Called by whatever | |
1100 | detects VBUS sessions */ | |
1101 | static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) | |
1102 | { | |
1103 | struct fsl_udc *udc; | |
1104 | unsigned long flags; | |
1105 | ||
1106 | udc = container_of(gadget, struct fsl_udc, gadget); | |
1107 | spin_lock_irqsave(&udc->lock, flags); | |
1108 | VDBG("VBUS %s\n", is_active ? "on" : "off"); | |
1109 | udc->vbus_active = (is_active != 0); | |
1110 | if (can_pullup(udc)) | |
1111 | fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), | |
1112 | &dr_regs->usbcmd); | |
1113 | else | |
1114 | fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), | |
1115 | &dr_regs->usbcmd); | |
1116 | spin_unlock_irqrestore(&udc->lock, flags); | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | /* constrain controller's VBUS power usage | |
1121 | * This call is used by gadget drivers during SET_CONFIGURATION calls, | |
1122 | * reporting how much power the device may consume. For example, this | |
1123 | * could affect how quickly batteries are recharged. | |
1124 | * | |
1125 | * Returns zero on success, else negative errno. | |
1126 | */ | |
1127 | static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1128 | { | |
1129 | #ifdef CONFIG_USB_OTG | |
1130 | struct fsl_udc *udc; | |
1131 | ||
1132 | udc = container_of(gadget, struct fsl_udc, gadget); | |
1133 | ||
1134 | if (udc->transceiver) | |
1135 | return otg_set_power(udc->transceiver, mA); | |
1136 | #endif | |
1137 | return -ENOTSUPP; | |
1138 | } | |
1139 | ||
1140 | /* Change Data+ pullup status | |
1141 | * this func is used by usb_gadget_connect/disconnet | |
1142 | */ | |
1143 | static int fsl_pullup(struct usb_gadget *gadget, int is_on) | |
1144 | { | |
1145 | struct fsl_udc *udc; | |
1146 | ||
1147 | udc = container_of(gadget, struct fsl_udc, gadget); | |
1148 | udc->softconnect = (is_on != 0); | |
1149 | if (can_pullup(udc)) | |
1150 | fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), | |
1151 | &dr_regs->usbcmd); | |
1152 | else | |
1153 | fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), | |
1154 | &dr_regs->usbcmd); | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | /* defined in usb_gadget.h */ | |
1160 | static struct usb_gadget_ops fsl_gadget_ops = { | |
1161 | .get_frame = fsl_get_frame, | |
1162 | .wakeup = fsl_wakeup, | |
1163 | /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ | |
1164 | .vbus_session = fsl_vbus_session, | |
1165 | .vbus_draw = fsl_vbus_draw, | |
1166 | .pullup = fsl_pullup, | |
1167 | }; | |
1168 | ||
1169 | /* Set protocol stall on ep0, protocol stall will automatically be cleared | |
1170 | on new transaction */ | |
1171 | static void ep0stall(struct fsl_udc *udc) | |
1172 | { | |
1173 | u32 tmp; | |
1174 | ||
1175 | /* must set tx and rx to stall at the same time */ | |
1176 | tmp = fsl_readl(&dr_regs->endptctrl[0]); | |
1177 | tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; | |
1178 | fsl_writel(tmp, &dr_regs->endptctrl[0]); | |
1179 | udc->ep0_state = WAIT_FOR_SETUP; | |
1180 | udc->ep0_dir = 0; | |
1181 | } | |
1182 | ||
1183 | /* Prime a status phase for ep0 */ | |
1184 | static int ep0_prime_status(struct fsl_udc *udc, int direction) | |
1185 | { | |
1186 | struct fsl_req *req = udc->status_req; | |
1187 | struct fsl_ep *ep; | |
1188 | int status = 0; | |
1189 | ||
1190 | if (direction == EP_DIR_IN) | |
1191 | udc->ep0_dir = USB_DIR_IN; | |
1192 | else | |
1193 | udc->ep0_dir = USB_DIR_OUT; | |
1194 | ||
1195 | ep = &udc->eps[0]; | |
1196 | udc->ep0_state = WAIT_FOR_OUT_STATUS; | |
1197 | ||
1198 | req->ep = ep; | |
1199 | req->req.length = 0; | |
1200 | req->req.status = -EINPROGRESS; | |
1201 | req->req.actual = 0; | |
1202 | req->req.complete = NULL; | |
1203 | req->dtd_count = 0; | |
1204 | ||
1205 | if (fsl_req_to_dtd(req) == 0) | |
1206 | status = fsl_queue_td(ep, req); | |
1207 | else | |
1208 | return -ENOMEM; | |
1209 | ||
1210 | if (status) | |
1211 | ERR("Can't queue ep0 status request \n"); | |
1212 | list_add_tail(&req->queue, &ep->queue); | |
1213 | ||
1214 | return status; | |
1215 | } | |
1216 | ||
1217 | static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) | |
1218 | { | |
1219 | struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); | |
1220 | ||
1221 | if (!ep->name) | |
1222 | return 0; | |
1223 | ||
1224 | nuke(ep, -ESHUTDOWN); | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * ch9 Set address | |
1231 | */ | |
1232 | static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) | |
1233 | { | |
1234 | /* Save the new address to device struct */ | |
1235 | udc->device_address = (u8) value; | |
1236 | /* Update usb state */ | |
1237 | udc->usb_state = USB_STATE_ADDRESS; | |
1238 | /* Status phase */ | |
1239 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1240 | ep0stall(udc); | |
1241 | } | |
1242 | ||
1243 | /* | |
1244 | * ch9 Get status | |
1245 | */ | |
1246 | static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, | |
1247 | u16 index, u16 length) | |
1248 | { | |
1249 | u16 tmp = 0; /* Status, cpu endian */ | |
1250 | ||
1251 | struct fsl_req *req; | |
1252 | struct fsl_ep *ep; | |
1253 | int status = 0; | |
1254 | ||
1255 | ep = &udc->eps[0]; | |
1256 | ||
1257 | if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { | |
1258 | /* Get device status */ | |
1259 | tmp = 1 << USB_DEVICE_SELF_POWERED; | |
1260 | tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; | |
1261 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { | |
1262 | /* Get interface status */ | |
1263 | /* We don't have interface information in udc driver */ | |
1264 | tmp = 0; | |
1265 | } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { | |
1266 | /* Get endpoint status */ | |
1267 | struct fsl_ep *target_ep; | |
1268 | ||
1269 | target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); | |
1270 | ||
1271 | /* stall if endpoint doesn't exist */ | |
1272 | if (!target_ep->desc) | |
1273 | goto stall; | |
1274 | tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) | |
1275 | << USB_ENDPOINT_HALT; | |
1276 | } | |
1277 | ||
1278 | udc->ep0_dir = USB_DIR_IN; | |
1279 | /* Borrow the per device status_req */ | |
1280 | req = udc->status_req; | |
1281 | /* Fill in the reqest structure */ | |
1282 | *((u16 *) req->req.buf) = cpu_to_le16(tmp); | |
1283 | req->ep = ep; | |
1284 | req->req.length = 2; | |
1285 | req->req.status = -EINPROGRESS; | |
1286 | req->req.actual = 0; | |
1287 | req->req.complete = NULL; | |
1288 | req->dtd_count = 0; | |
1289 | ||
1290 | /* prime the data phase */ | |
1291 | if ((fsl_req_to_dtd(req) == 0)) | |
1292 | status = fsl_queue_td(ep, req); | |
1293 | else /* no mem */ | |
1294 | goto stall; | |
1295 | ||
1296 | if (status) { | |
1297 | ERR("Can't respond to getstatus request \n"); | |
1298 | goto stall; | |
1299 | } | |
1300 | list_add_tail(&req->queue, &ep->queue); | |
1301 | udc->ep0_state = DATA_STATE_XMIT; | |
1302 | return; | |
1303 | stall: | |
1304 | ep0stall(udc); | |
1305 | } | |
1306 | ||
1307 | static void setup_received_irq(struct fsl_udc *udc, | |
1308 | struct usb_ctrlrequest *setup) | |
1309 | { | |
1310 | u16 wValue = le16_to_cpu(setup->wValue); | |
1311 | u16 wIndex = le16_to_cpu(setup->wIndex); | |
1312 | u16 wLength = le16_to_cpu(setup->wLength); | |
1313 | ||
1314 | udc_reset_ep_queue(udc, 0); | |
1315 | ||
1316 | switch (setup->bRequest) { | |
1317 | /* Request that need Data+Status phase from udc */ | |
1318 | case USB_REQ_GET_STATUS: | |
1319 | if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_STANDARD)) | |
1320 | != (USB_DIR_IN | USB_TYPE_STANDARD)) | |
1321 | break; | |
1322 | ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); | |
1323 | break; | |
1324 | ||
1325 | /* Requests that need Status phase from udc */ | |
1326 | case USB_REQ_SET_ADDRESS: | |
1327 | if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD | |
1328 | | USB_RECIP_DEVICE)) | |
1329 | break; | |
1330 | ch9setaddress(udc, wValue, wIndex, wLength); | |
1331 | break; | |
1332 | ||
1333 | /* Handled by udc, no data, status by udc */ | |
1334 | case USB_REQ_CLEAR_FEATURE: | |
1335 | case USB_REQ_SET_FEATURE: | |
1336 | { /* status transaction */ | |
1337 | int rc = -EOPNOTSUPP; | |
1338 | ||
1339 | if ((setup->bRequestType & USB_RECIP_MASK) | |
1340 | == USB_RECIP_ENDPOINT) { | |
1341 | int pipe = get_pipe_by_windex(wIndex); | |
1342 | struct fsl_ep *ep; | |
1343 | ||
1344 | if (wValue != 0 || wLength != 0 || pipe > udc->max_ep) | |
1345 | break; | |
1346 | ep = get_ep_by_pipe(udc, pipe); | |
1347 | ||
1348 | spin_unlock(&udc->lock); | |
1349 | rc = fsl_ep_set_halt(&ep->ep, | |
1350 | (setup->bRequest == USB_REQ_SET_FEATURE) | |
1351 | ? 1 : 0); | |
1352 | spin_lock(&udc->lock); | |
1353 | ||
1354 | } else if ((setup->bRequestType & USB_RECIP_MASK) | |
1355 | == USB_RECIP_DEVICE) { | |
1356 | /* Note: The driver has not include OTG support yet. | |
1357 | * This will be set when OTG support is added */ | |
1358 | if (!udc->gadget.is_otg) | |
1359 | break; | |
1360 | else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) | |
1361 | udc->gadget.b_hnp_enable = 1; | |
1362 | else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT) | |
1363 | udc->gadget.a_hnp_support = 1; | |
1364 | else if (setup->bRequest == | |
1365 | USB_DEVICE_A_ALT_HNP_SUPPORT) | |
1366 | udc->gadget.a_alt_hnp_support = 1; | |
1367 | rc = 0; | |
1368 | } | |
1369 | if (rc == 0) { | |
1370 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1371 | ep0stall(udc); | |
1372 | } | |
1373 | break; | |
1374 | } | |
1375 | /* Requests handled by gadget */ | |
1376 | default: | |
1377 | if (wLength) { | |
1378 | /* Data phase from gadget, status phase from udc */ | |
1379 | udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) | |
1380 | ? USB_DIR_IN : USB_DIR_OUT; | |
1381 | spin_unlock(&udc->lock); | |
1382 | if (udc->driver->setup(&udc->gadget, | |
1383 | &udc->local_setup_buff) < 0) | |
1384 | ep0stall(udc); | |
1385 | spin_lock(&udc->lock); | |
1386 | udc->ep0_state = (setup->bRequestType & USB_DIR_IN) | |
1387 | ? DATA_STATE_XMIT : DATA_STATE_RECV; | |
1388 | ||
1389 | } else { | |
1390 | /* No data phase, IN status from gadget */ | |
1391 | udc->ep0_dir = USB_DIR_IN; | |
1392 | spin_unlock(&udc->lock); | |
1393 | if (udc->driver->setup(&udc->gadget, | |
1394 | &udc->local_setup_buff) < 0) | |
1395 | ep0stall(udc); | |
1396 | spin_lock(&udc->lock); | |
1397 | udc->ep0_state = WAIT_FOR_OUT_STATUS; | |
1398 | } | |
1399 | break; | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /* Process request for Data or Status phase of ep0 | |
1404 | * prime status phase if needed */ | |
1405 | static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, | |
1406 | struct fsl_req *req) | |
1407 | { | |
1408 | if (udc->usb_state == USB_STATE_ADDRESS) { | |
1409 | /* Set the new address */ | |
1410 | u32 new_address = (u32) udc->device_address; | |
1411 | fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, | |
1412 | &dr_regs->deviceaddr); | |
1413 | } | |
1414 | ||
1415 | done(ep0, req, 0); | |
1416 | ||
1417 | switch (udc->ep0_state) { | |
1418 | case DATA_STATE_XMIT: | |
1419 | /* receive status phase */ | |
1420 | if (ep0_prime_status(udc, EP_DIR_OUT)) | |
1421 | ep0stall(udc); | |
1422 | break; | |
1423 | case DATA_STATE_RECV: | |
1424 | /* send status phase */ | |
1425 | if (ep0_prime_status(udc, EP_DIR_IN)) | |
1426 | ep0stall(udc); | |
1427 | break; | |
1428 | case WAIT_FOR_OUT_STATUS: | |
1429 | udc->ep0_state = WAIT_FOR_SETUP; | |
1430 | break; | |
1431 | case WAIT_FOR_SETUP: | |
1432 | ERR("Unexpect ep0 packets \n"); | |
1433 | break; | |
1434 | default: | |
1435 | ep0stall(udc); | |
1436 | break; | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | /* Tripwire mechanism to ensure a setup packet payload is extracted without | |
1441 | * being corrupted by another incoming setup packet */ | |
1442 | static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) | |
1443 | { | |
1444 | u32 temp; | |
1445 | struct ep_queue_head *qh; | |
1446 | ||
1447 | qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; | |
1448 | ||
1449 | /* Clear bit in ENDPTSETUPSTAT */ | |
1450 | temp = fsl_readl(&dr_regs->endptsetupstat); | |
1451 | fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); | |
1452 | ||
1453 | /* while a hazard exists when setup package arrives */ | |
1454 | do { | |
1455 | /* Set Setup Tripwire */ | |
1456 | temp = fsl_readl(&dr_regs->usbcmd); | |
1457 | fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); | |
1458 | ||
1459 | /* Copy the setup packet to local buffer */ | |
1460 | memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); | |
1461 | } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); | |
1462 | ||
1463 | /* Clear Setup Tripwire */ | |
1464 | temp = fsl_readl(&dr_regs->usbcmd); | |
1465 | fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); | |
1466 | } | |
1467 | ||
1468 | /* process-ep_req(): free the completed Tds for this req */ | |
1469 | static int process_ep_req(struct fsl_udc *udc, int pipe, | |
1470 | struct fsl_req *curr_req) | |
1471 | { | |
1472 | struct ep_td_struct *curr_td; | |
1473 | int td_complete, actual, remaining_length, j, tmp; | |
1474 | int status = 0; | |
1475 | int errors = 0; | |
1476 | struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; | |
1477 | int direction = pipe % 2; | |
1478 | ||
1479 | curr_td = curr_req->head; | |
1480 | td_complete = 0; | |
1481 | actual = curr_req->req.length; | |
1482 | ||
1483 | for (j = 0; j < curr_req->dtd_count; j++) { | |
1484 | remaining_length = (le32_to_cpu(curr_td->size_ioc_sts) | |
1485 | & DTD_PACKET_SIZE) | |
1486 | >> DTD_LENGTH_BIT_POS; | |
1487 | actual -= remaining_length; | |
1488 | ||
1489 | if ((errors = le32_to_cpu(curr_td->size_ioc_sts) & | |
1490 | DTD_ERROR_MASK)) { | |
1491 | if (errors & DTD_STATUS_HALTED) { | |
1492 | ERR("dTD error %08x QH=%d\n", errors, pipe); | |
1493 | /* Clear the errors and Halt condition */ | |
1494 | tmp = le32_to_cpu(curr_qh->size_ioc_int_sts); | |
1495 | tmp &= ~errors; | |
1496 | curr_qh->size_ioc_int_sts = cpu_to_le32(tmp); | |
1497 | status = -EPIPE; | |
1498 | /* FIXME: continue with next queued TD? */ | |
1499 | ||
1500 | break; | |
1501 | } | |
1502 | if (errors & DTD_STATUS_DATA_BUFF_ERR) { | |
1503 | VDBG("Transfer overflow"); | |
1504 | status = -EPROTO; | |
1505 | break; | |
1506 | } else if (errors & DTD_STATUS_TRANSACTION_ERR) { | |
1507 | VDBG("ISO error"); | |
1508 | status = -EILSEQ; | |
1509 | break; | |
1510 | } else | |
1511 | ERR("Unknown error has occured (0x%x)!\r\n", | |
1512 | errors); | |
1513 | ||
1514 | } else if (le32_to_cpu(curr_td->size_ioc_sts) | |
1515 | & DTD_STATUS_ACTIVE) { | |
1516 | VDBG("Request not complete"); | |
1517 | status = REQ_UNCOMPLETE; | |
1518 | return status; | |
1519 | } else if (remaining_length) { | |
1520 | if (direction) { | |
1521 | VDBG("Transmit dTD remaining length not zero"); | |
1522 | status = -EPROTO; | |
1523 | break; | |
1524 | } else { | |
1525 | td_complete++; | |
1526 | break; | |
1527 | } | |
1528 | } else { | |
1529 | td_complete++; | |
1530 | VDBG("dTD transmitted successful "); | |
1531 | } | |
1532 | ||
1533 | if (j != curr_req->dtd_count - 1) | |
1534 | curr_td = (struct ep_td_struct *)curr_td->next_td_virt; | |
1535 | } | |
1536 | ||
1537 | if (status) | |
1538 | return status; | |
1539 | ||
1540 | curr_req->req.actual = actual; | |
1541 | ||
1542 | return 0; | |
1543 | } | |
1544 | ||
1545 | /* Process a DTD completion interrupt */ | |
1546 | static void dtd_complete_irq(struct fsl_udc *udc) | |
1547 | { | |
1548 | u32 bit_pos; | |
1549 | int i, ep_num, direction, bit_mask, status; | |
1550 | struct fsl_ep *curr_ep; | |
1551 | struct fsl_req *curr_req, *temp_req; | |
1552 | ||
1553 | /* Clear the bits in the register */ | |
1554 | bit_pos = fsl_readl(&dr_regs->endptcomplete); | |
1555 | fsl_writel(bit_pos, &dr_regs->endptcomplete); | |
1556 | ||
1557 | if (!bit_pos) | |
1558 | return; | |
1559 | ||
1560 | for (i = 0; i < udc->max_ep * 2; i++) { | |
1561 | ep_num = i >> 1; | |
1562 | direction = i % 2; | |
1563 | ||
1564 | bit_mask = 1 << (ep_num + 16 * direction); | |
1565 | ||
1566 | if (!(bit_pos & bit_mask)) | |
1567 | continue; | |
1568 | ||
1569 | curr_ep = get_ep_by_pipe(udc, i); | |
1570 | ||
1571 | /* If the ep is configured */ | |
1572 | if (curr_ep->name == NULL) { | |
1573 | WARN("Invalid EP?"); | |
1574 | continue; | |
1575 | } | |
1576 | ||
1577 | /* process the req queue until an uncomplete request */ | |
1578 | list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, | |
1579 | queue) { | |
1580 | status = process_ep_req(udc, i, curr_req); | |
1581 | ||
1582 | VDBG("status of process_ep_req= %d, ep = %d", | |
1583 | status, ep_num); | |
1584 | if (status == REQ_UNCOMPLETE) | |
1585 | break; | |
1586 | /* write back status to req */ | |
1587 | curr_req->req.status = status; | |
1588 | ||
1589 | if (ep_num == 0) { | |
1590 | ep0_req_complete(udc, curr_ep, curr_req); | |
1591 | break; | |
1592 | } else | |
1593 | done(curr_ep, curr_req, status); | |
1594 | } | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | /* Process a port change interrupt */ | |
1599 | static void port_change_irq(struct fsl_udc *udc) | |
1600 | { | |
1601 | u32 speed; | |
1602 | ||
1603 | if (udc->bus_reset) | |
1604 | udc->bus_reset = 0; | |
1605 | ||
1606 | /* Bus resetting is finished */ | |
1607 | if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) { | |
1608 | /* Get the speed */ | |
1609 | speed = (fsl_readl(&dr_regs->portsc1) | |
1610 | & PORTSCX_PORT_SPEED_MASK); | |
1611 | switch (speed) { | |
1612 | case PORTSCX_PORT_SPEED_HIGH: | |
1613 | udc->gadget.speed = USB_SPEED_HIGH; | |
1614 | break; | |
1615 | case PORTSCX_PORT_SPEED_FULL: | |
1616 | udc->gadget.speed = USB_SPEED_FULL; | |
1617 | break; | |
1618 | case PORTSCX_PORT_SPEED_LOW: | |
1619 | udc->gadget.speed = USB_SPEED_LOW; | |
1620 | break; | |
1621 | default: | |
1622 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1623 | break; | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | /* Update USB state */ | |
1628 | if (!udc->resume_state) | |
1629 | udc->usb_state = USB_STATE_DEFAULT; | |
1630 | } | |
1631 | ||
1632 | /* Process suspend interrupt */ | |
1633 | static void suspend_irq(struct fsl_udc *udc) | |
1634 | { | |
1635 | udc->resume_state = udc->usb_state; | |
1636 | udc->usb_state = USB_STATE_SUSPENDED; | |
1637 | ||
1638 | /* report suspend to the driver, serial.c does not support this */ | |
1639 | if (udc->driver->suspend) | |
1640 | udc->driver->suspend(&udc->gadget); | |
1641 | } | |
1642 | ||
1643 | static void bus_resume(struct fsl_udc *udc) | |
1644 | { | |
1645 | udc->usb_state = udc->resume_state; | |
1646 | udc->resume_state = 0; | |
1647 | ||
1648 | /* report resume to the driver, serial.c does not support this */ | |
1649 | if (udc->driver->resume) | |
1650 | udc->driver->resume(&udc->gadget); | |
1651 | } | |
1652 | ||
1653 | /* Clear up all ep queues */ | |
1654 | static int reset_queues(struct fsl_udc *udc) | |
1655 | { | |
1656 | u8 pipe; | |
1657 | ||
1658 | for (pipe = 0; pipe < udc->max_pipes; pipe++) | |
1659 | udc_reset_ep_queue(udc, pipe); | |
1660 | ||
1661 | /* report disconnect; the driver is already quiesced */ | |
1662 | udc->driver->disconnect(&udc->gadget); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | /* Process reset interrupt */ | |
1668 | static void reset_irq(struct fsl_udc *udc) | |
1669 | { | |
1670 | u32 temp; | |
1671 | unsigned long timeout; | |
1672 | ||
1673 | /* Clear the device address */ | |
1674 | temp = fsl_readl(&dr_regs->deviceaddr); | |
1675 | fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); | |
1676 | ||
1677 | udc->device_address = 0; | |
1678 | ||
1679 | /* Clear usb state */ | |
1680 | udc->resume_state = 0; | |
1681 | udc->ep0_dir = 0; | |
1682 | udc->ep0_state = WAIT_FOR_SETUP; | |
1683 | udc->remote_wakeup = 0; /* default to 0 on reset */ | |
1684 | udc->gadget.b_hnp_enable = 0; | |
1685 | udc->gadget.a_hnp_support = 0; | |
1686 | udc->gadget.a_alt_hnp_support = 0; | |
1687 | ||
1688 | /* Clear all the setup token semaphores */ | |
1689 | temp = fsl_readl(&dr_regs->endptsetupstat); | |
1690 | fsl_writel(temp, &dr_regs->endptsetupstat); | |
1691 | ||
1692 | /* Clear all the endpoint complete status bits */ | |
1693 | temp = fsl_readl(&dr_regs->endptcomplete); | |
1694 | fsl_writel(temp, &dr_regs->endptcomplete); | |
1695 | ||
1696 | timeout = jiffies + 100; | |
1697 | while (fsl_readl(&dr_regs->endpointprime)) { | |
1698 | /* Wait until all endptprime bits cleared */ | |
1699 | if (time_after(jiffies, timeout)) { | |
1700 | ERR("Timeout for reset\n"); | |
1701 | break; | |
1702 | } | |
1703 | cpu_relax(); | |
1704 | } | |
1705 | ||
1706 | /* Write 1s to the flush register */ | |
1707 | fsl_writel(0xffffffff, &dr_regs->endptflush); | |
1708 | ||
1709 | if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { | |
1710 | VDBG("Bus reset"); | |
1711 | /* Bus is reseting */ | |
1712 | udc->bus_reset = 1; | |
1713 | /* Reset all the queues, include XD, dTD, EP queue | |
1714 | * head and TR Queue */ | |
1715 | reset_queues(udc); | |
1716 | udc->usb_state = USB_STATE_DEFAULT; | |
1717 | } else { | |
1718 | VDBG("Controller reset"); | |
1719 | /* initialize usb hw reg except for regs for EP, not | |
1720 | * touch usbintr reg */ | |
1721 | dr_controller_setup(udc); | |
1722 | ||
1723 | /* Reset all internal used Queues */ | |
1724 | reset_queues(udc); | |
1725 | ||
1726 | ep0_setup(udc); | |
1727 | ||
1728 | /* Enable DR IRQ reg, Set Run bit, change udc state */ | |
1729 | dr_controller_run(udc); | |
1730 | udc->usb_state = USB_STATE_ATTACHED; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | /* | |
1735 | * USB device controller interrupt handler | |
1736 | */ | |
1737 | static irqreturn_t fsl_udc_irq(int irq, void *_udc) | |
1738 | { | |
1739 | struct fsl_udc *udc = _udc; | |
1740 | u32 irq_src; | |
1741 | irqreturn_t status = IRQ_NONE; | |
1742 | unsigned long flags; | |
1743 | ||
1744 | /* Disable ISR for OTG host mode */ | |
1745 | if (udc->stopped) | |
1746 | return IRQ_NONE; | |
1747 | spin_lock_irqsave(&udc->lock, flags); | |
1748 | irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); | |
1749 | /* Clear notification bits */ | |
1750 | fsl_writel(irq_src, &dr_regs->usbsts); | |
1751 | ||
1752 | /* VDBG("irq_src [0x%8x]", irq_src); */ | |
1753 | ||
1754 | /* Need to resume? */ | |
1755 | if (udc->usb_state == USB_STATE_SUSPENDED) | |
1756 | if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) | |
1757 | bus_resume(udc); | |
1758 | ||
1759 | /* USB Interrupt */ | |
1760 | if (irq_src & USB_STS_INT) { | |
1761 | VDBG("Packet int"); | |
1762 | /* Setup package, we only support ep0 as control ep */ | |
1763 | if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { | |
1764 | tripwire_handler(udc, 0, | |
1765 | (u8 *) (&udc->local_setup_buff)); | |
1766 | setup_received_irq(udc, &udc->local_setup_buff); | |
1767 | status = IRQ_HANDLED; | |
1768 | } | |
1769 | ||
1770 | /* completion of dtd */ | |
1771 | if (fsl_readl(&dr_regs->endptcomplete)) { | |
1772 | dtd_complete_irq(udc); | |
1773 | status = IRQ_HANDLED; | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | /* SOF (for ISO transfer) */ | |
1778 | if (irq_src & USB_STS_SOF) { | |
1779 | status = IRQ_HANDLED; | |
1780 | } | |
1781 | ||
1782 | /* Port Change */ | |
1783 | if (irq_src & USB_STS_PORT_CHANGE) { | |
1784 | port_change_irq(udc); | |
1785 | status = IRQ_HANDLED; | |
1786 | } | |
1787 | ||
1788 | /* Reset Received */ | |
1789 | if (irq_src & USB_STS_RESET) { | |
1790 | reset_irq(udc); | |
1791 | status = IRQ_HANDLED; | |
1792 | } | |
1793 | ||
1794 | /* Sleep Enable (Suspend) */ | |
1795 | if (irq_src & USB_STS_SUSPEND) { | |
1796 | suspend_irq(udc); | |
1797 | status = IRQ_HANDLED; | |
1798 | } | |
1799 | ||
1800 | if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { | |
1801 | VDBG("Error IRQ %x ", irq_src); | |
1802 | } | |
1803 | ||
1804 | spin_unlock_irqrestore(&udc->lock, flags); | |
1805 | return status; | |
1806 | } | |
1807 | ||
1808 | /*----------------------------------------------------------------* | |
1809 | * Hook to gadget drivers | |
1810 | * Called by initialization code of gadget drivers | |
1811 | *----------------------------------------------------------------*/ | |
1812 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1813 | { | |
1814 | int retval = -ENODEV; | |
1815 | unsigned long flags = 0; | |
1816 | ||
1817 | if (!udc_controller) | |
1818 | return -ENODEV; | |
1819 | ||
1820 | if (!driver || (driver->speed != USB_SPEED_FULL | |
1821 | && driver->speed != USB_SPEED_HIGH) | |
1822 | || !driver->bind || !driver->disconnect | |
1823 | || !driver->setup) | |
1824 | return -EINVAL; | |
1825 | ||
1826 | if (udc_controller->driver) | |
1827 | return -EBUSY; | |
1828 | ||
1829 | /* lock is needed but whether should use this lock or another */ | |
1830 | spin_lock_irqsave(&udc_controller->lock, flags); | |
1831 | ||
1832 | driver->driver.bus = 0; | |
1833 | /* hook up the driver */ | |
1834 | udc_controller->driver = driver; | |
1835 | udc_controller->gadget.dev.driver = &driver->driver; | |
1836 | spin_unlock_irqrestore(&udc_controller->lock, flags); | |
1837 | ||
1838 | /* bind udc driver to gadget driver */ | |
1839 | retval = driver->bind(&udc_controller->gadget); | |
1840 | if (retval) { | |
1841 | VDBG("bind to %s --> %d", driver->driver.name, retval); | |
1842 | udc_controller->gadget.dev.driver = 0; | |
1843 | udc_controller->driver = 0; | |
1844 | goto out; | |
1845 | } | |
1846 | ||
1847 | /* Enable DR IRQ reg and Set usbcmd reg Run bit */ | |
1848 | dr_controller_run(udc_controller); | |
1849 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
1850 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
1851 | udc_controller->ep0_dir = 0; | |
1852 | printk(KERN_INFO "%s: bind to driver %s \n", | |
1853 | udc_controller->gadget.name, driver->driver.name); | |
1854 | ||
1855 | out: | |
1856 | if (retval) | |
1857 | printk("retval %d \n", retval); | |
1858 | return retval; | |
1859 | } | |
1860 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1861 | ||
1862 | /* Disconnect from gadget driver */ | |
1863 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1864 | { | |
1865 | struct fsl_ep *loop_ep; | |
1866 | unsigned long flags; | |
1867 | ||
1868 | if (!udc_controller) | |
1869 | return -ENODEV; | |
1870 | ||
1871 | if (!driver || driver != udc_controller->driver || !driver->unbind) | |
1872 | return -EINVAL; | |
1873 | ||
1874 | #ifdef CONFIG_USB_OTG | |
1875 | if (udc_controller->transceiver) | |
1876 | (void)otg_set_peripheral(udc_controller->transceiver, 0); | |
1877 | #endif | |
1878 | ||
1879 | /* stop DR, disable intr */ | |
1880 | dr_controller_stop(udc_controller); | |
1881 | ||
1882 | /* in fact, no needed */ | |
1883 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
1884 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
1885 | udc_controller->ep0_dir = 0; | |
1886 | ||
1887 | /* stand operation */ | |
1888 | spin_lock_irqsave(&udc_controller->lock, flags); | |
1889 | udc_controller->gadget.speed = USB_SPEED_UNKNOWN; | |
1890 | nuke(&udc_controller->eps[0], -ESHUTDOWN); | |
1891 | list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, | |
1892 | ep.ep_list) | |
1893 | nuke(loop_ep, -ESHUTDOWN); | |
1894 | spin_unlock_irqrestore(&udc_controller->lock, flags); | |
1895 | ||
1896 | /* unbind gadget and unhook driver. */ | |
1897 | driver->unbind(&udc_controller->gadget); | |
1898 | udc_controller->gadget.dev.driver = 0; | |
1899 | udc_controller->driver = 0; | |
1900 | ||
1901 | printk("unregistered gadget driver '%s'\r\n", driver->driver.name); | |
1902 | return 0; | |
1903 | } | |
1904 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1905 | ||
1906 | /*------------------------------------------------------------------------- | |
1907 | PROC File System Support | |
1908 | -------------------------------------------------------------------------*/ | |
1909 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
1910 | ||
1911 | #include <linux/seq_file.h> | |
1912 | ||
1913 | static const char proc_filename[] = "driver/fsl_usb2_udc"; | |
1914 | ||
1915 | static int fsl_proc_read(char *page, char **start, off_t off, int count, | |
1916 | int *eof, void *_dev) | |
1917 | { | |
1918 | char *buf = page; | |
1919 | char *next = buf; | |
1920 | unsigned size = count; | |
1921 | unsigned long flags; | |
1922 | int t, i; | |
1923 | u32 tmp_reg; | |
1924 | struct fsl_ep *ep = NULL; | |
1925 | struct fsl_req *req; | |
1926 | ||
1927 | struct fsl_udc *udc = udc_controller; | |
1928 | if (off != 0) | |
1929 | return 0; | |
1930 | ||
1931 | spin_lock_irqsave(&udc->lock, flags); | |
1932 | ||
1933 | /* ------basic driver infomation ---- */ | |
1934 | t = scnprintf(next, size, | |
1935 | DRIVER_DESC "\n" | |
1936 | "%s version: %s\n" | |
1937 | "Gadget driver: %s\n\n", | |
1938 | driver_name, DRIVER_VERSION, | |
1939 | udc->driver ? udc->driver->driver.name : "(none)"); | |
1940 | size -= t; | |
1941 | next += t; | |
1942 | ||
1943 | /* ------ DR Registers ----- */ | |
1944 | tmp_reg = fsl_readl(&dr_regs->usbcmd); | |
1945 | t = scnprintf(next, size, | |
1946 | "USBCMD reg:\n" | |
1947 | "SetupTW: %d\n" | |
1948 | "Run/Stop: %s\n\n", | |
1949 | (tmp_reg & USB_CMD_SUTW) ? 1 : 0, | |
1950 | (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); | |
1951 | size -= t; | |
1952 | next += t; | |
1953 | ||
1954 | tmp_reg = fsl_readl(&dr_regs->usbsts); | |
1955 | t = scnprintf(next, size, | |
1956 | "USB Status Reg:\n" | |
1957 | "Dr Suspend: %d" "Reset Received: %d" "System Error: %s" | |
1958 | "USB Error Interrupt: %s\n\n", | |
1959 | (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, | |
1960 | (tmp_reg & USB_STS_RESET) ? 1 : 0, | |
1961 | (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", | |
1962 | (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); | |
1963 | size -= t; | |
1964 | next += t; | |
1965 | ||
1966 | tmp_reg = fsl_readl(&dr_regs->usbintr); | |
1967 | t = scnprintf(next, size, | |
1968 | "USB Intrrupt Enable Reg:\n" | |
1969 | "Sleep Enable: %d" "SOF Received Enable: %d" | |
1970 | "Reset Enable: %d\n" | |
1971 | "System Error Enable: %d" | |
1972 | "Port Change Dectected Enable: %d\n" | |
1973 | "USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n", | |
1974 | (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, | |
1975 | (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, | |
1976 | (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, | |
1977 | (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, | |
1978 | (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, | |
1979 | (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, | |
1980 | (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); | |
1981 | size -= t; | |
1982 | next += t; | |
1983 | ||
1984 | tmp_reg = fsl_readl(&dr_regs->frindex); | |
1985 | t = scnprintf(next, size, | |
1986 | "USB Frame Index Reg:" "Frame Number is 0x%x\n\n", | |
1987 | (tmp_reg & USB_FRINDEX_MASKS)); | |
1988 | size -= t; | |
1989 | next += t; | |
1990 | ||
1991 | tmp_reg = fsl_readl(&dr_regs->deviceaddr); | |
1992 | t = scnprintf(next, size, | |
1993 | "USB Device Address Reg:" "Device Addr is 0x%x\n\n", | |
1994 | (tmp_reg & USB_DEVICE_ADDRESS_MASK)); | |
1995 | size -= t; | |
1996 | next += t; | |
1997 | ||
1998 | tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); | |
1999 | t = scnprintf(next, size, | |
2000 | "USB Endpoint List Address Reg:" | |
2001 | "Device Addr is 0x%x\n\n", | |
2002 | (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); | |
2003 | size -= t; | |
2004 | next += t; | |
2005 | ||
2006 | tmp_reg = fsl_readl(&dr_regs->portsc1); | |
2007 | t = scnprintf(next, size, | |
2008 | "USB Port Status&Control Reg:\n" | |
2009 | "Port Transceiver Type : %s" "Port Speed: %s \n" | |
2010 | "PHY Low Power Suspend: %s" "Port Reset: %s" | |
2011 | "Port Suspend Mode: %s \n" "Over-current Change: %s" | |
2012 | "Port Enable/Disable Change: %s\n" | |
2013 | "Port Enabled/Disabled: %s" | |
2014 | "Current Connect Status: %s\n\n", ( { | |
2015 | char *s; | |
2016 | switch (tmp_reg & PORTSCX_PTS_FSLS) { | |
2017 | case PORTSCX_PTS_UTMI: | |
2018 | s = "UTMI"; break; | |
2019 | case PORTSCX_PTS_ULPI: | |
2020 | s = "ULPI "; break; | |
2021 | case PORTSCX_PTS_FSLS: | |
2022 | s = "FS/LS Serial"; break; | |
2023 | default: | |
2024 | s = "None"; break; | |
2025 | } | |
2026 | s;} ), ( { | |
2027 | char *s; | |
2028 | switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) { | |
2029 | case PORTSCX_PORT_SPEED_FULL: | |
2030 | s = "Full Speed"; break; | |
2031 | case PORTSCX_PORT_SPEED_LOW: | |
2032 | s = "Low Speed"; break; | |
2033 | case PORTSCX_PORT_SPEED_HIGH: | |
2034 | s = "High Speed"; break; | |
2035 | default: | |
2036 | s = "Undefined"; break; | |
2037 | } | |
2038 | s; | |
2039 | } ), | |
2040 | (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? | |
2041 | "Normal PHY mode" : "Low power mode", | |
2042 | (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : | |
2043 | "Not in Reset", | |
2044 | (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", | |
2045 | (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : | |
2046 | "No", | |
2047 | (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : | |
2048 | "Not change", | |
2049 | (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : | |
2050 | "Not correct", | |
2051 | (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? | |
2052 | "Attached" : "Not-Att"); | |
2053 | size -= t; | |
2054 | next += t; | |
2055 | ||
2056 | tmp_reg = fsl_readl(&dr_regs->usbmode); | |
2057 | t = scnprintf(next, size, | |
2058 | "USB Mode Reg:" "Controller Mode is : %s\n\n", ( { | |
2059 | char *s; | |
2060 | switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { | |
2061 | case USB_MODE_CTRL_MODE_IDLE: | |
2062 | s = "Idle"; break; | |
2063 | case USB_MODE_CTRL_MODE_DEVICE: | |
2064 | s = "Device Controller"; break; | |
2065 | case USB_MODE_CTRL_MODE_HOST: | |
2066 | s = "Host Controller"; break; | |
2067 | default: | |
2068 | s = "None"; break; | |
2069 | } | |
2070 | s; | |
2071 | } )); | |
2072 | size -= t; | |
2073 | next += t; | |
2074 | ||
2075 | tmp_reg = fsl_readl(&dr_regs->endptsetupstat); | |
2076 | t = scnprintf(next, size, | |
2077 | "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n", | |
2078 | (tmp_reg & EP_SETUP_STATUS_MASK)); | |
2079 | size -= t; | |
2080 | next += t; | |
2081 | ||
2082 | for (i = 0; i < udc->max_ep / 2; i++) { | |
2083 | tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); | |
2084 | t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n", | |
2085 | i, tmp_reg); | |
2086 | size -= t; | |
2087 | next += t; | |
2088 | } | |
2089 | tmp_reg = fsl_readl(&dr_regs->endpointprime); | |
2090 | t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg); | |
2091 | size -= t; | |
2092 | next += t; | |
2093 | ||
2094 | tmp_reg = usb_sys_regs->snoop1; | |
2095 | t = scnprintf(next, size, "\nSnoop1 Reg : = [0x%x]\n\n", tmp_reg); | |
2096 | size -= t; | |
2097 | next += t; | |
2098 | ||
2099 | tmp_reg = usb_sys_regs->control; | |
2100 | t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n", | |
2101 | tmp_reg); | |
2102 | size -= t; | |
2103 | next += t; | |
2104 | ||
2105 | /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ | |
2106 | ep = &udc->eps[0]; | |
2107 | t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n", | |
2108 | ep->ep.name, ep_maxpacket(ep), ep_index(ep)); | |
2109 | size -= t; | |
2110 | next += t; | |
2111 | ||
2112 | if (list_empty(&ep->queue)) { | |
2113 | t = scnprintf(next, size, "its req queue is empty\n\n"); | |
2114 | size -= t; | |
2115 | next += t; | |
2116 | } else { | |
2117 | list_for_each_entry(req, &ep->queue, queue) { | |
2118 | t = scnprintf(next, size, | |
2119 | "req %p actual 0x%x length 0x%x buf %p\n", | |
2120 | &req->req, req->req.actual, | |
2121 | req->req.length, req->req.buf); | |
2122 | size -= t; | |
2123 | next += t; | |
2124 | } | |
2125 | } | |
2126 | /* other gadget->eplist ep */ | |
2127 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { | |
2128 | if (ep->desc) { | |
2129 | t = scnprintf(next, size, | |
2130 | "\nFor %s Maxpkt is 0x%x " | |
2131 | "index is 0x%x\n", | |
2132 | ep->ep.name, ep_maxpacket(ep), | |
2133 | ep_index(ep)); | |
2134 | size -= t; | |
2135 | next += t; | |
2136 | ||
2137 | if (list_empty(&ep->queue)) { | |
2138 | t = scnprintf(next, size, | |
2139 | "its req queue is empty\n\n"); | |
2140 | size -= t; | |
2141 | next += t; | |
2142 | } else { | |
2143 | list_for_each_entry(req, &ep->queue, queue) { | |
2144 | t = scnprintf(next, size, | |
2145 | "req %p actual 0x%x length" | |
2146 | "0x%x buf %p\n", | |
2147 | &req->req, req->req.actual, | |
2148 | req->req.length, req->req.buf); | |
2149 | size -= t; | |
2150 | next += t; | |
2151 | } /* end for each_entry of ep req */ | |
2152 | } /* end for else */ | |
2153 | } /* end for if(ep->queue) */ | |
2154 | } /* end (ep->desc) */ | |
2155 | ||
2156 | spin_unlock_irqrestore(&udc->lock, flags); | |
2157 | ||
2158 | *eof = 1; | |
2159 | return count - size; | |
2160 | } | |
2161 | ||
2162 | #define create_proc_file() create_proc_read_entry(proc_filename, \ | |
2163 | 0, NULL, fsl_proc_read, NULL) | |
2164 | ||
2165 | #define remove_proc_file() remove_proc_entry(proc_filename, NULL) | |
2166 | ||
2167 | #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ | |
2168 | ||
2169 | #define create_proc_file() do {} while (0) | |
2170 | #define remove_proc_file() do {} while (0) | |
2171 | ||
2172 | #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ | |
2173 | ||
2174 | /*-------------------------------------------------------------------------*/ | |
2175 | ||
2176 | /* Release udc structures */ | |
2177 | static void fsl_udc_release(struct device *dev) | |
2178 | { | |
2179 | complete(udc_controller->done); | |
2180 | dma_free_coherent(dev, udc_controller->ep_qh_size, | |
2181 | udc_controller->ep_qh, udc_controller->ep_qh_dma); | |
2182 | kfree(udc_controller); | |
2183 | } | |
2184 | ||
2185 | /****************************************************************** | |
2186 | Internal structure setup functions | |
2187 | *******************************************************************/ | |
2188 | /*------------------------------------------------------------------ | |
2189 | * init resource for globle controller | |
2190 | * Return the udc handle on success or NULL on failure | |
2191 | ------------------------------------------------------------------*/ | |
2192 | static struct fsl_udc *__init struct_udc_setup(struct platform_device *pdev) | |
2193 | { | |
2194 | struct fsl_udc *udc; | |
2195 | struct fsl_usb2_platform_data *pdata; | |
2196 | size_t size; | |
2197 | ||
2198 | udc = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); | |
2199 | if (udc == NULL) { | |
2200 | ERR("malloc udc failed\n"); | |
2201 | return NULL; | |
2202 | } | |
2203 | ||
2204 | pdata = pdev->dev.platform_data; | |
2205 | udc->phy_mode = pdata->phy_mode; | |
2206 | /* max_ep_nr is bidirectional ep number, max_ep doubles the number */ | |
2207 | udc->max_ep = pdata->max_ep_nr * 2; | |
2208 | ||
2209 | udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); | |
2210 | if (!udc->eps) { | |
2211 | ERR("malloc fsl_ep failed\n"); | |
2212 | goto cleanup; | |
2213 | } | |
2214 | ||
2215 | /* initialized QHs, take care of alignment */ | |
2216 | size = udc->max_ep * sizeof(struct ep_queue_head); | |
2217 | if (size < QH_ALIGNMENT) | |
2218 | size = QH_ALIGNMENT; | |
2219 | else if ((size % QH_ALIGNMENT) != 0) { | |
2220 | size += QH_ALIGNMENT + 1; | |
2221 | size &= ~(QH_ALIGNMENT - 1); | |
2222 | } | |
2223 | udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, | |
2224 | &udc->ep_qh_dma, GFP_KERNEL); | |
2225 | if (!udc->ep_qh) { | |
2226 | ERR("malloc QHs for udc failed\n"); | |
2227 | kfree(udc->eps); | |
2228 | goto cleanup; | |
2229 | } | |
2230 | ||
2231 | udc->ep_qh_size = size; | |
2232 | ||
2233 | /* Initialize ep0 status request structure */ | |
2234 | /* FIXME: fsl_alloc_request() ignores ep argument */ | |
2235 | udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), | |
2236 | struct fsl_req, req); | |
2237 | /* allocate a small amount of memory to get valid address */ | |
2238 | udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); | |
2239 | udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf); | |
2240 | ||
2241 | udc->resume_state = USB_STATE_NOTATTACHED; | |
2242 | udc->usb_state = USB_STATE_POWERED; | |
2243 | udc->ep0_dir = 0; | |
2244 | udc->remote_wakeup = 0; /* default to 0 on reset */ | |
2245 | spin_lock_init(&udc->lock); | |
2246 | ||
2247 | return udc; | |
2248 | ||
2249 | cleanup: | |
2250 | kfree(udc); | |
2251 | return NULL; | |
2252 | } | |
2253 | ||
2254 | /*---------------------------------------------------------------- | |
2255 | * Setup the fsl_ep struct for eps | |
2256 | * Link fsl_ep->ep to gadget->ep_list | |
2257 | * ep0out is not used so do nothing here | |
2258 | * ep0in should be taken care | |
2259 | *--------------------------------------------------------------*/ | |
2260 | static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, | |
2261 | char *name, int link) | |
2262 | { | |
2263 | struct fsl_ep *ep = &udc->eps[index]; | |
2264 | ||
2265 | ep->udc = udc; | |
2266 | strcpy(ep->name, name); | |
2267 | ep->ep.name = ep->name; | |
2268 | ||
2269 | ep->ep.ops = &fsl_ep_ops; | |
2270 | ep->stopped = 0; | |
2271 | ||
2272 | /* for ep0: maxP defined in desc | |
2273 | * for other eps, maxP is set by epautoconfig() called by gadget layer | |
2274 | */ | |
2275 | ep->ep.maxpacket = (unsigned short) ~0; | |
2276 | ||
2277 | /* the queue lists any req for this ep */ | |
2278 | INIT_LIST_HEAD(&ep->queue); | |
2279 | ||
2280 | /* gagdet.ep_list used for ep_autoconfig so no ep0 */ | |
2281 | if (link) | |
2282 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
2283 | ep->gadget = &udc->gadget; | |
2284 | ep->qh = &udc->ep_qh[index]; | |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
2289 | /* Driver probe function | |
2290 | * all intialize operations implemented here except enabling usb_intr reg | |
2291 | */ | |
2292 | static int __init fsl_udc_probe(struct platform_device *pdev) | |
2293 | { | |
2294 | struct resource *res; | |
2295 | int ret = -ENODEV; | |
2296 | unsigned int i; | |
2297 | ||
2298 | if (strcmp(pdev->name, driver_name)) { | |
2299 | VDBG("Wrong device\n"); | |
2300 | return -ENODEV; | |
2301 | } | |
2302 | ||
2303 | /* board setup should have been done in the platform code */ | |
2304 | ||
2305 | /* Initialize the udc structure including QH member and other member */ | |
2306 | udc_controller = struct_udc_setup(pdev); | |
2307 | if (!udc_controller) { | |
2308 | VDBG("udc_controller is NULL \n"); | |
2309 | return -ENOMEM; | |
2310 | } | |
2311 | ||
2312 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2313 | if (!res) | |
2314 | return -ENXIO; | |
2315 | ||
2316 | if (!request_mem_region(res->start, res->end - res->start + 1, | |
2317 | driver_name)) { | |
2318 | ERR("request mem region for %s failed \n", pdev->name); | |
2319 | return -EBUSY; | |
2320 | } | |
2321 | ||
2322 | dr_regs = ioremap(res->start, res->end - res->start + 1); | |
2323 | if (!dr_regs) { | |
2324 | ret = -ENOMEM; | |
2325 | goto err1; | |
2326 | } | |
2327 | ||
2328 | usb_sys_regs = (struct usb_sys_interface *) | |
2329 | ((u32)dr_regs + USB_DR_SYS_OFFSET); | |
2330 | ||
2331 | udc_controller->irq = platform_get_irq(pdev, 0); | |
2332 | if (!udc_controller->irq) { | |
2333 | ret = -ENODEV; | |
2334 | goto err2; | |
2335 | } | |
2336 | ||
2337 | ret = request_irq(udc_controller->irq, fsl_udc_irq, SA_SHIRQ, | |
2338 | driver_name, udc_controller); | |
2339 | if (ret != 0) { | |
2340 | ERR("cannot request irq %d err %d \n", | |
2341 | udc_controller->irq, ret); | |
2342 | goto err2; | |
2343 | } | |
2344 | ||
2345 | /* initialize usb hw reg except for regs for EP, | |
2346 | * leave usbintr reg untouched */ | |
2347 | dr_controller_setup(udc_controller); | |
2348 | ||
2349 | /* Setup gadget structure */ | |
2350 | udc_controller->gadget.ops = &fsl_gadget_ops; | |
2351 | udc_controller->gadget.is_dualspeed = 1; | |
2352 | udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; | |
2353 | INIT_LIST_HEAD(&udc_controller->gadget.ep_list); | |
2354 | udc_controller->gadget.speed = USB_SPEED_UNKNOWN; | |
2355 | udc_controller->gadget.name = driver_name; | |
2356 | ||
2357 | /* Setup gadget.dev and register with kernel */ | |
2358 | strcpy(udc_controller->gadget.dev.bus_id, "gadget"); | |
2359 | udc_controller->gadget.dev.release = fsl_udc_release; | |
2360 | udc_controller->gadget.dev.parent = &pdev->dev; | |
2361 | ret = device_register(&udc_controller->gadget.dev); | |
2362 | if (ret < 0) | |
2363 | goto err3; | |
2364 | ||
2365 | /* setup QH and epctrl for ep0 */ | |
2366 | ep0_setup(udc_controller); | |
2367 | ||
2368 | /* setup udc->eps[] for ep0 */ | |
2369 | struct_ep_setup(udc_controller, 0, "ep0", 0); | |
2370 | /* for ep0: the desc defined here; | |
2371 | * for other eps, gadget layer called ep_enable with defined desc | |
2372 | */ | |
2373 | udc_controller->eps[0].desc = &fsl_ep0_desc; | |
2374 | udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; | |
2375 | ||
2376 | /* setup the udc->eps[] for non-control endpoints and link | |
2377 | * to gadget.ep_list */ | |
2378 | for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { | |
2379 | char name[14]; | |
2380 | ||
2381 | sprintf(name, "ep%dout", i); | |
2382 | struct_ep_setup(udc_controller, i * 2, name, 1); | |
2383 | sprintf(name, "ep%din", i); | |
2384 | struct_ep_setup(udc_controller, i * 2 + 1, name, 1); | |
2385 | } | |
2386 | ||
2387 | /* use dma_pool for TD management */ | |
2388 | udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, | |
2389 | sizeof(struct ep_td_struct), | |
2390 | DTD_ALIGNMENT, UDC_DMA_BOUNDARY); | |
2391 | if (udc_controller->td_pool == NULL) { | |
2392 | ret = -ENOMEM; | |
2393 | goto err4; | |
2394 | } | |
2395 | create_proc_file(); | |
2396 | return 0; | |
2397 | ||
2398 | err4: | |
2399 | device_unregister(&udc_controller->gadget.dev); | |
2400 | err3: | |
2401 | free_irq(udc_controller->irq, udc_controller); | |
2402 | err2: | |
2403 | iounmap(dr_regs); | |
2404 | err1: | |
2405 | release_mem_region(res->start, res->end - res->start + 1); | |
2406 | return ret; | |
2407 | } | |
2408 | ||
2409 | /* Driver removal function | |
2410 | * Free resources and finish pending transactions | |
2411 | */ | |
2412 | static int __exit fsl_udc_remove(struct platform_device *pdev) | |
2413 | { | |
2414 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2415 | ||
2416 | DECLARE_COMPLETION(done); | |
2417 | ||
2418 | if (!udc_controller) | |
2419 | return -ENODEV; | |
2420 | udc_controller->done = &done; | |
2421 | ||
2422 | /* DR has been stopped in usb_gadget_unregister_driver() */ | |
2423 | remove_proc_file(); | |
2424 | ||
2425 | /* Free allocated memory */ | |
2426 | kfree(udc_controller->status_req->req.buf); | |
2427 | kfree(udc_controller->status_req); | |
2428 | kfree(udc_controller->eps); | |
2429 | ||
2430 | dma_pool_destroy(udc_controller->td_pool); | |
2431 | free_irq(udc_controller->irq, udc_controller); | |
2432 | iounmap(dr_regs); | |
2433 | release_mem_region(res->start, res->end - res->start + 1); | |
2434 | ||
2435 | device_unregister(&udc_controller->gadget.dev); | |
2436 | /* free udc --wait for the release() finished */ | |
2437 | wait_for_completion(&done); | |
2438 | ||
2439 | return 0; | |
2440 | } | |
2441 | ||
2442 | /*----------------------------------------------------------------- | |
2443 | * Modify Power management attributes | |
2444 | * Used by OTG statemachine to disable gadget temporarily | |
2445 | -----------------------------------------------------------------*/ | |
2446 | static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) | |
2447 | { | |
2448 | dr_controller_stop(udc_controller); | |
2449 | return 0; | |
2450 | } | |
2451 | ||
2452 | /*----------------------------------------------------------------- | |
2453 | * Invoked on USB resume. May be called in_interrupt. | |
2454 | * Here we start the DR controller and enable the irq | |
2455 | *-----------------------------------------------------------------*/ | |
2456 | static int fsl_udc_resume(struct platform_device *pdev) | |
2457 | { | |
2458 | /* Enable DR irq reg and set controller Run */ | |
2459 | if (udc_controller->stopped) { | |
2460 | dr_controller_setup(udc_controller); | |
2461 | dr_controller_run(udc_controller); | |
2462 | } | |
2463 | udc_controller->usb_state = USB_STATE_ATTACHED; | |
2464 | udc_controller->ep0_state = WAIT_FOR_SETUP; | |
2465 | udc_controller->ep0_dir = 0; | |
2466 | return 0; | |
2467 | } | |
2468 | ||
2469 | /*------------------------------------------------------------------------- | |
2470 | Register entry point for the peripheral controller driver | |
2471 | --------------------------------------------------------------------------*/ | |
2472 | ||
2473 | static struct platform_driver udc_driver = { | |
2474 | .remove = __exit_p(fsl_udc_remove), | |
2475 | /* these suspend and resume are not usb suspend and resume */ | |
2476 | .suspend = fsl_udc_suspend, | |
2477 | .resume = fsl_udc_resume, | |
2478 | .driver = { | |
2479 | .name = (char *)driver_name, | |
2480 | .owner = THIS_MODULE, | |
2481 | }, | |
2482 | }; | |
2483 | ||
2484 | static int __init udc_init(void) | |
2485 | { | |
2486 | printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION); | |
2487 | return platform_driver_probe(&udc_driver, fsl_udc_probe); | |
2488 | } | |
2489 | ||
2490 | module_init(udc_init); | |
2491 | ||
2492 | static void __exit udc_exit(void) | |
2493 | { | |
2494 | platform_driver_unregister(&udc_driver); | |
2495 | printk("%s unregistered \n", driver_desc); | |
2496 | } | |
2497 | ||
2498 | module_exit(udc_exit); | |
2499 | ||
2500 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2501 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2502 | MODULE_LICENSE("GPL"); |