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0fe6f1d1 YHC |
1 | /* |
2 | * Fusb300 UDC (USB gadget) | |
3 | * | |
4 | * Copyright (C) 2010 Faraday Technology Corp. | |
5 | * | |
6 | * Author : Yuan-hsin Chen <yhchen@faraday-tech.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
29 | ||
30 | #include "fusb300_udc.h" | |
31 | ||
32 | MODULE_DESCRIPTION("FUSB300 USB gadget driver"); | |
33 | MODULE_LICENSE("GPL"); | |
34 | MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>"); | |
35 | MODULE_ALIAS("platform:fusb300_udc"); | |
36 | ||
37 | #define DRIVER_VERSION "20 October 2010" | |
38 | ||
39 | static const char udc_name[] = "fusb300_udc"; | |
40 | static const char * const fusb300_ep_name[] = { | |
6b2e30c0 DC |
41 | "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9", |
42 | "ep10", "ep11", "ep12", "ep13", "ep14", "ep15" | |
0fe6f1d1 YHC |
43 | }; |
44 | ||
45 | static void done(struct fusb300_ep *ep, struct fusb300_request *req, | |
46 | int status); | |
47 | ||
48 | static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset, | |
49 | u32 value) | |
50 | { | |
51 | u32 reg = ioread32(fusb300->reg + offset); | |
52 | ||
53 | reg |= value; | |
54 | iowrite32(reg, fusb300->reg + offset); | |
55 | } | |
56 | ||
57 | static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset, | |
58 | u32 value) | |
59 | { | |
60 | u32 reg = ioread32(fusb300->reg + offset); | |
61 | ||
62 | reg &= ~value; | |
63 | iowrite32(reg, fusb300->reg + offset); | |
64 | } | |
65 | ||
66 | ||
67 | static void fusb300_ep_setting(struct fusb300_ep *ep, | |
68 | struct fusb300_ep_info info) | |
69 | { | |
70 | ep->epnum = info.epnum; | |
71 | ep->type = info.type; | |
72 | } | |
73 | ||
74 | static int fusb300_ep_release(struct fusb300_ep *ep) | |
75 | { | |
76 | if (!ep->epnum) | |
77 | return 0; | |
78 | ep->epnum = 0; | |
79 | ep->stall = 0; | |
80 | ep->wedged = 0; | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static void fusb300_set_fifo_entry(struct fusb300 *fusb300, | |
85 | u32 ep) | |
86 | { | |
87 | u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
88 | ||
89 | val &= ~FUSB300_EPSET1_FIFOENTRY_MSK; | |
90 | val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM); | |
91 | iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
92 | } | |
93 | ||
94 | static void fusb300_set_start_entry(struct fusb300 *fusb300, | |
95 | u8 ep) | |
96 | { | |
97 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
98 | u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM; | |
99 | ||
100 | reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ; | |
101 | reg |= FUSB300_EPSET1_START_ENTRY(start_entry); | |
102 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
103 | if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) { | |
104 | fusb300->fifo_entry_num = 0; | |
105 | fusb300->addrofs = 0; | |
106 | pr_err("fifo entry is over the maximum number!\n"); | |
107 | } else | |
108 | fusb300->fifo_entry_num++; | |
109 | } | |
110 | ||
111 | /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */ | |
112 | static void fusb300_set_epaddrofs(struct fusb300 *fusb300, | |
113 | struct fusb300_ep_info info) | |
114 | { | |
115 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); | |
116 | ||
117 | reg &= ~FUSB300_EPSET2_ADDROFS_MSK; | |
118 | reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs); | |
119 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); | |
120 | fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM; | |
121 | } | |
122 | ||
123 | static void ep_fifo_setting(struct fusb300 *fusb300, | |
124 | struct fusb300_ep_info info) | |
125 | { | |
126 | fusb300_set_fifo_entry(fusb300, info.epnum); | |
127 | fusb300_set_start_entry(fusb300, info.epnum); | |
128 | fusb300_set_epaddrofs(fusb300, info); | |
129 | } | |
130 | ||
131 | static void fusb300_set_eptype(struct fusb300 *fusb300, | |
132 | struct fusb300_ep_info info) | |
133 | { | |
134 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
135 | ||
136 | reg &= ~FUSB300_EPSET1_TYPE_MSK; | |
137 | reg |= FUSB300_EPSET1_TYPE(info.type); | |
138 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
139 | } | |
140 | ||
141 | static void fusb300_set_epdir(struct fusb300 *fusb300, | |
142 | struct fusb300_ep_info info) | |
143 | { | |
144 | u32 reg; | |
145 | ||
146 | if (!info.dir_in) | |
147 | return; | |
148 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
149 | reg &= ~FUSB300_EPSET1_DIR_MSK; | |
150 | reg |= FUSB300_EPSET1_DIRIN; | |
151 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
152 | } | |
153 | ||
154 | static void fusb300_set_ep_active(struct fusb300 *fusb300, | |
155 | u8 ep) | |
156 | { | |
157 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
158 | ||
159 | reg |= FUSB300_EPSET1_ACTEN; | |
160 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); | |
161 | } | |
162 | ||
163 | static void fusb300_set_epmps(struct fusb300 *fusb300, | |
164 | struct fusb300_ep_info info) | |
165 | { | |
166 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); | |
167 | ||
168 | reg &= ~FUSB300_EPSET2_MPS_MSK; | |
169 | reg |= FUSB300_EPSET2_MPS(info.maxpacket); | |
170 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); | |
171 | } | |
172 | ||
173 | static void fusb300_set_interval(struct fusb300 *fusb300, | |
174 | struct fusb300_ep_info info) | |
175 | { | |
176 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
177 | ||
178 | reg &= ~FUSB300_EPSET1_INTERVAL(0x7); | |
179 | reg |= FUSB300_EPSET1_INTERVAL(info.interval); | |
180 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
181 | } | |
182 | ||
183 | static void fusb300_set_bwnum(struct fusb300 *fusb300, | |
184 | struct fusb300_ep_info info) | |
185 | { | |
186 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
187 | ||
188 | reg &= ~FUSB300_EPSET1_BWNUM(0x3); | |
189 | reg |= FUSB300_EPSET1_BWNUM(info.bw_num); | |
190 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); | |
191 | } | |
192 | ||
193 | static void set_ep_reg(struct fusb300 *fusb300, | |
194 | struct fusb300_ep_info info) | |
195 | { | |
196 | fusb300_set_eptype(fusb300, info); | |
197 | fusb300_set_epdir(fusb300, info); | |
198 | fusb300_set_epmps(fusb300, info); | |
199 | ||
200 | if (info.interval) | |
201 | fusb300_set_interval(fusb300, info); | |
202 | ||
203 | if (info.bw_num) | |
204 | fusb300_set_bwnum(fusb300, info); | |
205 | ||
206 | fusb300_set_ep_active(fusb300, info.epnum); | |
207 | } | |
208 | ||
209 | static int config_ep(struct fusb300_ep *ep, | |
210 | const struct usb_endpoint_descriptor *desc) | |
211 | { | |
212 | struct fusb300 *fusb300 = ep->fusb300; | |
213 | struct fusb300_ep_info info; | |
214 | ||
215 | ep->desc = desc; | |
216 | ||
217 | info.interval = 0; | |
218 | info.addrofs = 0; | |
219 | info.bw_num = 0; | |
220 | ||
221 | info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; | |
222 | info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
223 | info.maxpacket = le16_to_cpu(desc->wMaxPacketSize); | |
224 | info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; | |
225 | ||
226 | if ((info.type == USB_ENDPOINT_XFER_INT) || | |
227 | (info.type == USB_ENDPOINT_XFER_ISOC)) { | |
228 | info.interval = desc->bInterval; | |
229 | if (info.type == USB_ENDPOINT_XFER_ISOC) | |
230 | info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11); | |
231 | } | |
232 | ||
233 | ep_fifo_setting(fusb300, info); | |
234 | ||
235 | set_ep_reg(fusb300, info); | |
236 | ||
237 | fusb300_ep_setting(ep, info); | |
238 | ||
239 | fusb300->ep[info.epnum] = ep; | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static int fusb300_enable(struct usb_ep *_ep, | |
245 | const struct usb_endpoint_descriptor *desc) | |
246 | { | |
247 | struct fusb300_ep *ep; | |
248 | ||
249 | ep = container_of(_ep, struct fusb300_ep, ep); | |
250 | ||
251 | if (ep->fusb300->reenum) { | |
252 | ep->fusb300->fifo_entry_num = 0; | |
253 | ep->fusb300->addrofs = 0; | |
254 | ep->fusb300->reenum = 0; | |
255 | } | |
256 | ||
257 | return config_ep(ep, desc); | |
258 | } | |
259 | ||
260 | static int fusb300_disable(struct usb_ep *_ep) | |
261 | { | |
262 | struct fusb300_ep *ep; | |
263 | struct fusb300_request *req; | |
264 | unsigned long flags; | |
265 | ||
266 | ep = container_of(_ep, struct fusb300_ep, ep); | |
267 | ||
268 | BUG_ON(!ep); | |
269 | ||
270 | while (!list_empty(&ep->queue)) { | |
271 | req = list_entry(ep->queue.next, struct fusb300_request, queue); | |
272 | spin_lock_irqsave(&ep->fusb300->lock, flags); | |
273 | done(ep, req, -ECONNRESET); | |
274 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); | |
275 | } | |
276 | ||
277 | return fusb300_ep_release(ep); | |
278 | } | |
279 | ||
280 | static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep, | |
281 | gfp_t gfp_flags) | |
282 | { | |
283 | struct fusb300_request *req; | |
284 | ||
285 | req = kzalloc(sizeof(struct fusb300_request), gfp_flags); | |
286 | if (!req) | |
287 | return NULL; | |
288 | INIT_LIST_HEAD(&req->queue); | |
289 | ||
290 | return &req->req; | |
291 | } | |
292 | ||
293 | static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
294 | { | |
295 | struct fusb300_request *req; | |
296 | ||
297 | req = container_of(_req, struct fusb300_request, req); | |
298 | kfree(req); | |
299 | } | |
300 | ||
301 | static int enable_fifo_int(struct fusb300_ep *ep) | |
302 | { | |
303 | struct fusb300 *fusb300 = ep->fusb300; | |
304 | ||
305 | if (ep->epnum) { | |
306 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0, | |
307 | FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum)); | |
308 | } else { | |
309 | pr_err("can't enable_fifo_int ep0\n"); | |
310 | return -EINVAL; | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int disable_fifo_int(struct fusb300_ep *ep) | |
317 | { | |
318 | struct fusb300 *fusb300 = ep->fusb300; | |
319 | ||
320 | if (ep->epnum) { | |
321 | fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0, | |
322 | FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum)); | |
323 | } else { | |
324 | pr_err("can't disable_fifo_int ep0\n"); | |
325 | return -EINVAL; | |
326 | } | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length) | |
332 | { | |
333 | u32 reg; | |
334 | ||
335 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); | |
336 | reg &= ~FUSB300_CSR_LEN_MSK; | |
337 | reg |= FUSB300_CSR_LEN(length); | |
338 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR); | |
339 | } | |
340 | ||
341 | /* write data to cx fifo */ | |
342 | static void fusb300_wrcxf(struct fusb300_ep *ep, | |
343 | struct fusb300_request *req) | |
344 | { | |
345 | int i = 0; | |
346 | u8 *tmp; | |
347 | u32 data; | |
348 | struct fusb300 *fusb300 = ep->fusb300; | |
349 | u32 length = req->req.length - req->req.actual; | |
350 | ||
351 | tmp = req->req.buf + req->req.actual; | |
352 | ||
353 | if (length > SS_CTL_MAX_PACKET_SIZE) { | |
354 | fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE); | |
355 | for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) { | |
356 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 | | |
357 | *(tmp + 3) << 24; | |
358 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); | |
359 | tmp += 4; | |
360 | } | |
361 | req->req.actual += SS_CTL_MAX_PACKET_SIZE; | |
362 | } else { /* length is less than max packet size */ | |
363 | fusb300_set_cxlen(fusb300, length); | |
364 | for (i = length >> 2; i > 0; i--) { | |
365 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 | | |
366 | *(tmp + 3) << 24; | |
367 | printk(KERN_DEBUG " 0x%x\n", data); | |
368 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); | |
369 | tmp = tmp + 4; | |
370 | } | |
371 | switch (length % 4) { | |
372 | case 1: | |
373 | data = *tmp; | |
374 | printk(KERN_DEBUG " 0x%x\n", data); | |
375 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); | |
376 | break; | |
377 | case 2: | |
378 | data = *tmp | *(tmp + 1) << 8; | |
379 | printk(KERN_DEBUG " 0x%x\n", data); | |
380 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); | |
381 | break; | |
382 | case 3: | |
383 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16; | |
384 | printk(KERN_DEBUG " 0x%x\n", data); | |
385 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); | |
386 | break; | |
387 | default: | |
388 | break; | |
389 | } | |
390 | req->req.actual += length; | |
391 | } | |
392 | } | |
393 | ||
394 | static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep) | |
395 | { | |
396 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep), | |
397 | FUSB300_EPSET0_STL); | |
398 | } | |
399 | ||
400 | static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep) | |
401 | { | |
402 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); | |
403 | ||
404 | if (reg & FUSB300_EPSET0_STL) { | |
405 | printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep); | |
406 | reg &= ~FUSB300_EPSET0_STL; | |
407 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); | |
408 | } | |
409 | } | |
410 | ||
411 | static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req) | |
412 | { | |
413 | if (ep->fusb300->ep0_dir) { /* if IN */ | |
414 | if (req->req.length) { | |
415 | fusb300_wrcxf(ep, req); | |
416 | } else | |
417 | printk(KERN_DEBUG "%s : req->req.length = 0x%x\n", | |
418 | __func__, req->req.length); | |
419 | if ((req->req.length == req->req.actual) || | |
420 | (req->req.actual < ep->ep.maxpacket)) | |
421 | done(ep, req, 0); | |
422 | } else { /* OUT */ | |
423 | if (!req->req.length) | |
424 | done(ep, req, 0); | |
425 | else | |
426 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1, | |
427 | FUSB300_IGER1_CX_OUT_INT); | |
428 | } | |
429 | } | |
430 | ||
431 | static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req, | |
432 | gfp_t gfp_flags) | |
433 | { | |
434 | struct fusb300_ep *ep; | |
435 | struct fusb300_request *req; | |
436 | unsigned long flags; | |
437 | int request = 0; | |
438 | ||
439 | ep = container_of(_ep, struct fusb300_ep, ep); | |
440 | req = container_of(_req, struct fusb300_request, req); | |
441 | ||
442 | if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN) | |
443 | return -ESHUTDOWN; | |
444 | ||
445 | spin_lock_irqsave(&ep->fusb300->lock, flags); | |
446 | ||
447 | if (list_empty(&ep->queue)) | |
448 | request = 1; | |
449 | ||
450 | list_add_tail(&req->queue, &ep->queue); | |
451 | ||
452 | req->req.actual = 0; | |
453 | req->req.status = -EINPROGRESS; | |
454 | ||
455 | if (ep->desc == NULL) /* ep0 */ | |
456 | ep0_queue(ep, req); | |
457 | else if (request && !ep->stall) | |
458 | enable_fifo_int(ep); | |
459 | ||
460 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
466 | { | |
467 | struct fusb300_ep *ep; | |
468 | struct fusb300_request *req; | |
469 | unsigned long flags; | |
470 | ||
471 | ep = container_of(_ep, struct fusb300_ep, ep); | |
472 | req = container_of(_req, struct fusb300_request, req); | |
473 | ||
474 | spin_lock_irqsave(&ep->fusb300->lock, flags); | |
475 | if (!list_empty(&ep->queue)) | |
476 | done(ep, req, -ECONNRESET); | |
477 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge) | |
483 | { | |
484 | struct fusb300_ep *ep; | |
485 | struct fusb300 *fusb300; | |
486 | unsigned long flags; | |
487 | int ret = 0; | |
488 | ||
489 | ep = container_of(_ep, struct fusb300_ep, ep); | |
490 | ||
491 | fusb300 = ep->fusb300; | |
492 | ||
493 | spin_lock_irqsave(&ep->fusb300->lock, flags); | |
494 | ||
495 | if (!list_empty(&ep->queue)) { | |
496 | ret = -EAGAIN; | |
497 | goto out; | |
498 | } | |
499 | ||
500 | if (value) { | |
501 | fusb300_set_epnstall(fusb300, ep->epnum); | |
502 | ep->stall = 1; | |
503 | if (wedge) | |
504 | ep->wedged = 1; | |
505 | } else { | |
506 | fusb300_clear_epnstall(fusb300, ep->epnum); | |
507 | ep->stall = 0; | |
508 | ep->wedged = 0; | |
509 | } | |
510 | ||
511 | out: | |
512 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); | |
513 | return ret; | |
514 | } | |
515 | ||
516 | static int fusb300_set_halt(struct usb_ep *_ep, int value) | |
517 | { | |
518 | return fusb300_set_halt_and_wedge(_ep, value, 0); | |
519 | } | |
520 | ||
521 | static int fusb300_set_wedge(struct usb_ep *_ep) | |
522 | { | |
523 | return fusb300_set_halt_and_wedge(_ep, 1, 1); | |
524 | } | |
525 | ||
526 | static void fusb300_fifo_flush(struct usb_ep *_ep) | |
527 | { | |
528 | } | |
529 | ||
530 | static struct usb_ep_ops fusb300_ep_ops = { | |
531 | .enable = fusb300_enable, | |
532 | .disable = fusb300_disable, | |
533 | ||
534 | .alloc_request = fusb300_alloc_request, | |
535 | .free_request = fusb300_free_request, | |
536 | ||
537 | .queue = fusb300_queue, | |
538 | .dequeue = fusb300_dequeue, | |
539 | ||
540 | .set_halt = fusb300_set_halt, | |
541 | .fifo_flush = fusb300_fifo_flush, | |
542 | .set_wedge = fusb300_set_wedge, | |
543 | }; | |
544 | ||
545 | /*****************************************************************************/ | |
546 | static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset, | |
547 | u32 value) | |
548 | { | |
549 | iowrite32(value, fusb300->reg + offset); | |
550 | } | |
551 | ||
552 | static void fusb300_reset(void) | |
553 | { | |
554 | } | |
555 | ||
556 | static void fusb300_set_cxstall(struct fusb300 *fusb300) | |
557 | { | |
558 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR, | |
559 | FUSB300_CSR_STL); | |
560 | } | |
561 | ||
562 | static void fusb300_set_cxdone(struct fusb300 *fusb300) | |
563 | { | |
564 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR, | |
565 | FUSB300_CSR_DONE); | |
566 | } | |
567 | ||
568 | /* read data from cx fifo */ | |
569 | void fusb300_rdcxf(struct fusb300 *fusb300, | |
570 | u8 *buffer, u32 length) | |
571 | { | |
572 | int i = 0; | |
573 | u8 *tmp; | |
574 | u32 data; | |
575 | ||
576 | tmp = buffer; | |
577 | ||
578 | for (i = (length >> 2); i > 0; i--) { | |
579 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); | |
580 | printk(KERN_DEBUG " 0x%x\n", data); | |
581 | *tmp = data & 0xFF; | |
582 | *(tmp + 1) = (data >> 8) & 0xFF; | |
583 | *(tmp + 2) = (data >> 16) & 0xFF; | |
584 | *(tmp + 3) = (data >> 24) & 0xFF; | |
585 | tmp = tmp + 4; | |
586 | } | |
587 | ||
588 | switch (length % 4) { | |
589 | case 1: | |
590 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); | |
591 | printk(KERN_DEBUG " 0x%x\n", data); | |
592 | *tmp = data & 0xFF; | |
593 | break; | |
594 | case 2: | |
595 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); | |
596 | printk(KERN_DEBUG " 0x%x\n", data); | |
597 | *tmp = data & 0xFF; | |
598 | *(tmp + 1) = (data >> 8) & 0xFF; | |
599 | break; | |
600 | case 3: | |
601 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); | |
602 | printk(KERN_DEBUG " 0x%x\n", data); | |
603 | *tmp = data & 0xFF; | |
604 | *(tmp + 1) = (data >> 8) & 0xFF; | |
605 | *(tmp + 2) = (data >> 16) & 0xFF; | |
606 | break; | |
607 | default: | |
608 | break; | |
609 | } | |
610 | } | |
611 | ||
0fe6f1d1 YHC |
612 | static void fusb300_rdfifo(struct fusb300_ep *ep, |
613 | struct fusb300_request *req, | |
614 | u32 length) | |
615 | { | |
616 | int i = 0; | |
617 | u8 *tmp; | |
618 | u32 data, reg; | |
619 | struct fusb300 *fusb300 = ep->fusb300; | |
620 | ||
621 | tmp = req->req.buf + req->req.actual; | |
622 | req->req.actual += length; | |
623 | ||
624 | if (req->req.actual > req->req.length) | |
625 | printk(KERN_DEBUG "req->req.actual > req->req.length\n"); | |
626 | ||
627 | for (i = (length >> 2); i > 0; i--) { | |
628 | data = ioread32(fusb300->reg + | |
629 | FUSB300_OFFSET_EPPORT(ep->epnum)); | |
630 | *tmp = data & 0xFF; | |
631 | *(tmp + 1) = (data >> 8) & 0xFF; | |
632 | *(tmp + 2) = (data >> 16) & 0xFF; | |
633 | *(tmp + 3) = (data >> 24) & 0xFF; | |
634 | tmp = tmp + 4; | |
635 | } | |
636 | ||
637 | switch (length % 4) { | |
638 | case 1: | |
639 | data = ioread32(fusb300->reg + | |
640 | FUSB300_OFFSET_EPPORT(ep->epnum)); | |
641 | *tmp = data & 0xFF; | |
642 | break; | |
643 | case 2: | |
644 | data = ioread32(fusb300->reg + | |
645 | FUSB300_OFFSET_EPPORT(ep->epnum)); | |
646 | *tmp = data & 0xFF; | |
647 | *(tmp + 1) = (data >> 8) & 0xFF; | |
648 | break; | |
649 | case 3: | |
650 | data = ioread32(fusb300->reg + | |
651 | FUSB300_OFFSET_EPPORT(ep->epnum)); | |
652 | *tmp = data & 0xFF; | |
653 | *(tmp + 1) = (data >> 8) & 0xFF; | |
654 | *(tmp + 2) = (data >> 16) & 0xFF; | |
655 | break; | |
656 | default: | |
657 | break; | |
658 | } | |
659 | ||
660 | do { | |
661 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); | |
662 | reg &= FUSB300_IGR1_SYNF0_EMPTY_INT; | |
663 | if (i) | |
664 | printk(KERN_INFO "sync fifo is not empty!\n"); | |
665 | i++; | |
666 | } while (!reg); | |
667 | } | |
668 | ||
0fe6f1d1 YHC |
669 | static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep) |
670 | { | |
671 | u8 value; | |
672 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); | |
673 | ||
674 | value = reg & FUSB300_EPSET0_STL; | |
675 | ||
676 | return value; | |
677 | } | |
678 | ||
679 | static u8 fusb300_get_cxstall(struct fusb300 *fusb300) | |
680 | { | |
681 | u8 value; | |
682 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); | |
683 | ||
684 | value = (reg & FUSB300_CSR_STL) >> 1; | |
685 | ||
686 | return value; | |
687 | } | |
688 | ||
689 | static void request_error(struct fusb300 *fusb300) | |
690 | { | |
691 | fusb300_set_cxstall(fusb300); | |
692 | printk(KERN_DEBUG "request error!!\n"); | |
693 | } | |
694 | ||
695 | static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) | |
696 | __releases(fusb300->lock) | |
697 | __acquires(fusb300->lock) | |
698 | { | |
699 | u8 ep; | |
700 | u16 status = 0; | |
701 | u16 w_index = ctrl->wIndex; | |
702 | ||
703 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
704 | case USB_RECIP_DEVICE: | |
705 | status = 1 << USB_DEVICE_SELF_POWERED; | |
706 | break; | |
707 | case USB_RECIP_INTERFACE: | |
708 | status = 0; | |
709 | break; | |
710 | case USB_RECIP_ENDPOINT: | |
711 | ep = w_index & USB_ENDPOINT_NUMBER_MASK; | |
712 | if (ep) { | |
713 | if (fusb300_get_epnstall(fusb300, ep)) | |
714 | status = 1 << USB_ENDPOINT_HALT; | |
715 | } else { | |
716 | if (fusb300_get_cxstall(fusb300)) | |
717 | status = 0; | |
718 | } | |
719 | break; | |
720 | ||
721 | default: | |
722 | request_error(fusb300); | |
723 | return; /* exit */ | |
724 | } | |
725 | ||
726 | fusb300->ep0_data = cpu_to_le16(status); | |
727 | fusb300->ep0_req->buf = &fusb300->ep0_data; | |
728 | fusb300->ep0_req->length = 2; | |
729 | ||
730 | spin_unlock(&fusb300->lock); | |
731 | fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL); | |
732 | spin_lock(&fusb300->lock); | |
733 | } | |
734 | ||
735 | static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) | |
736 | { | |
737 | u8 ep; | |
738 | ||
739 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
740 | case USB_RECIP_DEVICE: | |
741 | fusb300_set_cxdone(fusb300); | |
742 | break; | |
743 | case USB_RECIP_INTERFACE: | |
744 | fusb300_set_cxdone(fusb300); | |
745 | break; | |
746 | case USB_RECIP_ENDPOINT: { | |
747 | u16 w_index = le16_to_cpu(ctrl->wIndex); | |
748 | ||
749 | ep = w_index & USB_ENDPOINT_NUMBER_MASK; | |
750 | if (ep) | |
751 | fusb300_set_epnstall(fusb300, ep); | |
752 | else | |
753 | fusb300_set_cxstall(fusb300); | |
754 | fusb300_set_cxdone(fusb300); | |
755 | } | |
756 | break; | |
757 | default: | |
758 | request_error(fusb300); | |
759 | break; | |
760 | } | |
761 | } | |
762 | ||
763 | static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep) | |
764 | { | |
765 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep), | |
766 | FUSB300_EPSET0_CLRSEQNUM); | |
767 | } | |
768 | ||
769 | static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) | |
770 | { | |
771 | struct fusb300_ep *ep = | |
772 | fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK]; | |
773 | ||
774 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
775 | case USB_RECIP_DEVICE: | |
776 | fusb300_set_cxdone(fusb300); | |
777 | break; | |
778 | case USB_RECIP_INTERFACE: | |
779 | fusb300_set_cxdone(fusb300); | |
780 | break; | |
781 | case USB_RECIP_ENDPOINT: | |
782 | if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) { | |
783 | if (ep->wedged) { | |
784 | fusb300_set_cxdone(fusb300); | |
785 | break; | |
786 | } | |
787 | if (ep->stall) { | |
788 | ep->stall = 0; | |
789 | fusb300_clear_seqnum(fusb300, ep->epnum); | |
790 | fusb300_clear_epnstall(fusb300, ep->epnum); | |
791 | if (!list_empty(&ep->queue)) | |
792 | enable_fifo_int(ep); | |
793 | } | |
794 | } | |
795 | fusb300_set_cxdone(fusb300); | |
796 | break; | |
797 | default: | |
798 | request_error(fusb300); | |
799 | break; | |
800 | } | |
801 | } | |
802 | ||
803 | static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr) | |
804 | { | |
805 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR); | |
806 | ||
807 | reg &= ~FUSB300_DAR_DRVADDR_MSK; | |
808 | reg |= FUSB300_DAR_DRVADDR(addr); | |
809 | ||
810 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR); | |
811 | } | |
812 | ||
813 | static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) | |
814 | { | |
815 | if (ctrl->wValue >= 0x0100) | |
816 | request_error(fusb300); | |
817 | else { | |
818 | fusb300_set_dev_addr(fusb300, ctrl->wValue); | |
819 | fusb300_set_cxdone(fusb300); | |
820 | } | |
821 | } | |
822 | ||
823 | #define UVC_COPY_DESCRIPTORS(mem, src) \ | |
824 | do { \ | |
825 | const struct usb_descriptor_header * const *__src; \ | |
826 | for (__src = src; *__src; ++__src) { \ | |
827 | memcpy(mem, *__src, (*__src)->bLength); \ | |
828 | mem += (*__src)->bLength; \ | |
829 | } \ | |
830 | } while (0) | |
831 | ||
0fe6f1d1 YHC |
832 | static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
833 | { | |
834 | u8 *p = (u8 *)ctrl; | |
835 | u8 ret = 0; | |
836 | u8 i = 0; | |
837 | ||
838 | fusb300_rdcxf(fusb300, p, 8); | |
839 | fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN; | |
840 | fusb300->ep0_length = ctrl->wLength; | |
841 | ||
842 | /* check request */ | |
843 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
844 | switch (ctrl->bRequest) { | |
845 | case USB_REQ_GET_STATUS: | |
846 | get_status(fusb300, ctrl); | |
847 | break; | |
848 | case USB_REQ_CLEAR_FEATURE: | |
849 | clear_feature(fusb300, ctrl); | |
850 | break; | |
851 | case USB_REQ_SET_FEATURE: | |
852 | set_feature(fusb300, ctrl); | |
853 | break; | |
854 | case USB_REQ_SET_ADDRESS: | |
855 | set_address(fusb300, ctrl); | |
856 | break; | |
857 | case USB_REQ_SET_CONFIGURATION: | |
858 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR, | |
859 | FUSB300_DAR_SETCONFG); | |
860 | /* clear sequence number */ | |
861 | for (i = 1; i <= FUSB300_MAX_NUM_EP; i++) | |
862 | fusb300_clear_seqnum(fusb300, i); | |
863 | fusb300->reenum = 1; | |
864 | ret = 1; | |
865 | break; | |
866 | default: | |
867 | ret = 1; | |
868 | break; | |
869 | } | |
870 | } else | |
871 | ret = 1; | |
872 | ||
873 | return ret; | |
874 | } | |
875 | ||
0fe6f1d1 YHC |
876 | static void done(struct fusb300_ep *ep, struct fusb300_request *req, |
877 | int status) | |
878 | { | |
879 | list_del_init(&req->queue); | |
880 | ||
881 | /* don't modify queue heads during completion callback */ | |
882 | if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN) | |
883 | req->req.status = -ESHUTDOWN; | |
884 | else | |
885 | req->req.status = status; | |
886 | ||
887 | spin_unlock(&ep->fusb300->lock); | |
888 | req->req.complete(&ep->ep, &req->req); | |
889 | spin_lock(&ep->fusb300->lock); | |
890 | ||
891 | if (ep->epnum) { | |
892 | disable_fifo_int(ep); | |
893 | if (!list_empty(&ep->queue)) | |
894 | enable_fifo_int(ep); | |
895 | } else | |
896 | fusb300_set_cxdone(ep->fusb300); | |
897 | } | |
898 | ||
1425b80e SAS |
899 | static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d, |
900 | u32 len) | |
0fe6f1d1 YHC |
901 | { |
902 | u32 value; | |
903 | u32 reg; | |
904 | ||
905 | /* wait SW owner */ | |
906 | do { | |
907 | reg = ioread32(ep->fusb300->reg + | |
908 | FUSB300_OFFSET_EPPRD_W0(ep->epnum)); | |
909 | reg &= FUSB300_EPPRD0_H; | |
910 | } while (reg); | |
911 | ||
1425b80e | 912 | iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum)); |
0fe6f1d1 | 913 | |
1425b80e | 914 | value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H | |
0fe6f1d1 YHC |
915 | FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I; |
916 | iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum)); | |
917 | ||
918 | iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum)); | |
919 | ||
920 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY, | |
921 | FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum)); | |
922 | } | |
923 | ||
924 | static void fusb300_wait_idma_finished(struct fusb300_ep *ep) | |
925 | { | |
926 | u32 reg; | |
927 | ||
928 | do { | |
929 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1); | |
930 | if ((reg & FUSB300_IGR1_VBUS_CHG_INT) || | |
931 | (reg & FUSB300_IGR1_WARM_RST_INT) || | |
932 | (reg & FUSB300_IGR1_HOT_RST_INT) || | |
933 | (reg & FUSB300_IGR1_USBRST_INT) | |
934 | ) | |
935 | goto IDMA_RESET; | |
936 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0); | |
937 | reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum); | |
938 | } while (!reg); | |
939 | ||
940 | fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0, | |
941 | FUSB300_IGR0_EPn_PRD_INT(ep->epnum)); | |
942 | IDMA_RESET: | |
943 | fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0, | |
944 | FUSB300_IGER0_EEPn_PRD_INT(ep->epnum)); | |
945 | } | |
946 | ||
947 | static void fusb300_set_idma(struct fusb300_ep *ep, | |
948 | struct fusb300_request *req) | |
949 | { | |
950 | dma_addr_t d; | |
0fe6f1d1 YHC |
951 | |
952 | d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE); | |
953 | ||
954 | if (dma_mapping_error(NULL, d)) { | |
0fe6f1d1 | 955 | printk(KERN_DEBUG "dma_mapping_error\n"); |
1425b80e | 956 | return; |
0fe6f1d1 YHC |
957 | } |
958 | ||
959 | dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE); | |
960 | ||
961 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0, | |
962 | FUSB300_IGER0_EEPn_PRD_INT(ep->epnum)); | |
963 | ||
1425b80e | 964 | fusb300_fill_idma_prdtbl(ep, d, req->req.length); |
0fe6f1d1 YHC |
965 | /* check idma is done */ |
966 | fusb300_wait_idma_finished(ep); | |
967 | ||
1425b80e | 968 | dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE); |
0fe6f1d1 YHC |
969 | } |
970 | ||
971 | static void in_ep_fifo_handler(struct fusb300_ep *ep) | |
972 | { | |
973 | struct fusb300_request *req = list_entry(ep->queue.next, | |
974 | struct fusb300_request, queue); | |
975 | ||
4dbafd3d | 976 | if (req->req.length) |
0fe6f1d1 | 977 | fusb300_set_idma(ep, req); |
0fe6f1d1 YHC |
978 | done(ep, req, 0); |
979 | } | |
980 | ||
981 | static void out_ep_fifo_handler(struct fusb300_ep *ep) | |
982 | { | |
983 | struct fusb300 *fusb300 = ep->fusb300; | |
984 | struct fusb300_request *req = list_entry(ep->queue.next, | |
985 | struct fusb300_request, queue); | |
986 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); | |
987 | u32 length = reg & FUSB300_FFR_BYCNT; | |
988 | ||
989 | fusb300_rdfifo(ep, req, length); | |
990 | ||
991 | /* finish out transfer */ | |
992 | if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket)) | |
993 | done(ep, req, 0); | |
994 | } | |
995 | ||
996 | static void check_device_mode(struct fusb300 *fusb300) | |
997 | { | |
998 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR); | |
999 | ||
1000 | switch (reg & FUSB300_GCR_DEVEN_MSK) { | |
1001 | case FUSB300_GCR_DEVEN_SS: | |
1002 | fusb300->gadget.speed = USB_SPEED_SUPER; | |
1003 | break; | |
1004 | case FUSB300_GCR_DEVEN_HS: | |
1005 | fusb300->gadget.speed = USB_SPEED_HIGH; | |
1006 | break; | |
1007 | case FUSB300_GCR_DEVEN_FS: | |
1008 | fusb300->gadget.speed = USB_SPEED_FULL; | |
1009 | break; | |
1010 | default: | |
1011 | fusb300->gadget.speed = USB_SPEED_UNKNOWN; | |
1012 | break; | |
1013 | } | |
1014 | printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK)); | |
1015 | } | |
1016 | ||
1017 | ||
1018 | static void fusb300_ep0out(struct fusb300 *fusb300) | |
1019 | { | |
1020 | struct fusb300_ep *ep = fusb300->ep[0]; | |
1021 | u32 reg; | |
1022 | ||
1023 | if (!list_empty(&ep->queue)) { | |
1024 | struct fusb300_request *req; | |
1025 | ||
1026 | req = list_first_entry(&ep->queue, | |
1027 | struct fusb300_request, queue); | |
1028 | if (req->req.length) | |
1029 | fusb300_rdcxf(ep->fusb300, req->req.buf, | |
1030 | req->req.length); | |
1031 | done(ep, req, 0); | |
1032 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); | |
1033 | reg &= ~FUSB300_IGER1_CX_OUT_INT; | |
1034 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1); | |
1035 | } else | |
1036 | pr_err("%s : empty queue\n", __func__); | |
1037 | } | |
1038 | ||
1039 | static void fusb300_ep0in(struct fusb300 *fusb300) | |
1040 | { | |
1041 | struct fusb300_request *req; | |
1042 | struct fusb300_ep *ep = fusb300->ep[0]; | |
1043 | ||
1044 | if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) { | |
1045 | req = list_entry(ep->queue.next, | |
1046 | struct fusb300_request, queue); | |
1047 | if (req->req.length) | |
1048 | fusb300_wrcxf(ep, req); | |
1049 | if ((req->req.length - req->req.actual) < ep->ep.maxpacket) | |
1050 | done(ep, req, 0); | |
1051 | } else | |
1052 | fusb300_set_cxdone(fusb300); | |
1053 | } | |
1054 | ||
1055 | static void fusb300_grp2_handler(void) | |
1056 | { | |
1057 | } | |
1058 | ||
1059 | static void fusb300_grp3_handler(void) | |
1060 | { | |
1061 | } | |
1062 | ||
1063 | static void fusb300_grp4_handler(void) | |
1064 | { | |
1065 | } | |
1066 | ||
1067 | static void fusb300_grp5_handler(void) | |
1068 | { | |
1069 | } | |
1070 | ||
1071 | static irqreturn_t fusb300_irq(int irq, void *_fusb300) | |
1072 | { | |
1073 | struct fusb300 *fusb300 = _fusb300; | |
1074 | u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); | |
1075 | u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); | |
1076 | u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0); | |
1077 | u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0); | |
1078 | struct usb_ctrlrequest ctrl; | |
1079 | u8 in; | |
1080 | u32 reg; | |
1081 | int i; | |
1082 | ||
1083 | spin_lock(&fusb300->lock); | |
1084 | ||
1085 | int_grp1 &= int_grp1_en; | |
1086 | int_grp0 &= int_grp0_en; | |
1087 | ||
1088 | if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) { | |
1089 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1090 | FUSB300_IGR1_WARM_RST_INT); | |
1091 | printk(KERN_INFO"fusb300_warmreset\n"); | |
1092 | fusb300_reset(); | |
1093 | } | |
1094 | ||
1095 | if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) { | |
1096 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1097 | FUSB300_IGR1_HOT_RST_INT); | |
1098 | printk(KERN_INFO"fusb300_hotreset\n"); | |
1099 | fusb300_reset(); | |
1100 | } | |
1101 | ||
1102 | if (int_grp1 & FUSB300_IGR1_USBRST_INT) { | |
1103 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1104 | FUSB300_IGR1_USBRST_INT); | |
1105 | fusb300_reset(); | |
1106 | } | |
1107 | /* COMABT_INT has a highest priority */ | |
1108 | ||
1109 | if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) { | |
1110 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1111 | FUSB300_IGR1_CX_COMABT_INT); | |
1112 | printk(KERN_INFO"fusb300_ep0abt\n"); | |
1113 | } | |
1114 | ||
1115 | if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) { | |
1116 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1117 | FUSB300_IGR1_VBUS_CHG_INT); | |
1118 | printk(KERN_INFO"fusb300_vbus_change\n"); | |
1119 | } | |
1120 | ||
1121 | if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) { | |
1122 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1123 | FUSB300_IGR1_U3_EXIT_FAIL_INT); | |
1124 | } | |
1125 | ||
1126 | if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) { | |
1127 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1128 | FUSB300_IGR1_U2_EXIT_FAIL_INT); | |
1129 | } | |
1130 | ||
1131 | if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) { | |
1132 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1133 | FUSB300_IGR1_U1_EXIT_FAIL_INT); | |
1134 | } | |
1135 | ||
1136 | if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) { | |
1137 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1138 | FUSB300_IGR1_U2_ENTRY_FAIL_INT); | |
1139 | } | |
1140 | ||
1141 | if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) { | |
1142 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1143 | FUSB300_IGR1_U1_ENTRY_FAIL_INT); | |
1144 | } | |
1145 | ||
1146 | if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) { | |
1147 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1148 | FUSB300_IGR1_U3_EXIT_INT); | |
1149 | printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n"); | |
1150 | } | |
1151 | ||
1152 | if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) { | |
1153 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1154 | FUSB300_IGR1_U2_EXIT_INT); | |
1155 | printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n"); | |
1156 | } | |
1157 | ||
1158 | if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) { | |
1159 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1160 | FUSB300_IGR1_U1_EXIT_INT); | |
1161 | printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n"); | |
1162 | } | |
1163 | ||
1164 | if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) { | |
1165 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1166 | FUSB300_IGR1_U3_ENTRY_INT); | |
1167 | printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n"); | |
1168 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1, | |
1169 | FUSB300_SSCR1_GO_U3_DONE); | |
1170 | } | |
1171 | ||
1172 | if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) { | |
1173 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1174 | FUSB300_IGR1_U2_ENTRY_INT); | |
1175 | printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n"); | |
1176 | } | |
1177 | ||
1178 | if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) { | |
1179 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1180 | FUSB300_IGR1_U1_ENTRY_INT); | |
1181 | printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n"); | |
1182 | } | |
1183 | ||
1184 | if (int_grp1 & FUSB300_IGR1_RESM_INT) { | |
1185 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1186 | FUSB300_IGR1_RESM_INT); | |
1187 | printk(KERN_INFO "fusb300_resume\n"); | |
1188 | } | |
1189 | ||
1190 | if (int_grp1 & FUSB300_IGR1_SUSP_INT) { | |
1191 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1192 | FUSB300_IGR1_SUSP_INT); | |
1193 | printk(KERN_INFO "fusb300_suspend\n"); | |
1194 | } | |
1195 | ||
1196 | if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) { | |
1197 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1198 | FUSB300_IGR1_HS_LPM_INT); | |
1199 | printk(KERN_INFO "fusb300_HS_LPM_INT\n"); | |
1200 | } | |
1201 | ||
1202 | if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) { | |
1203 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, | |
1204 | FUSB300_IGR1_DEV_MODE_CHG_INT); | |
1205 | check_device_mode(fusb300); | |
1206 | } | |
1207 | ||
1208 | if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) { | |
1209 | fusb300_set_cxstall(fusb300); | |
1210 | printk(KERN_INFO "fusb300_ep0fail\n"); | |
1211 | } | |
1212 | ||
1213 | if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) { | |
1214 | printk(KERN_INFO "fusb300_ep0setup\n"); | |
1215 | if (setup_packet(fusb300, &ctrl)) { | |
1216 | spin_unlock(&fusb300->lock); | |
1217 | if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0) | |
1218 | fusb300_set_cxstall(fusb300); | |
1219 | spin_lock(&fusb300->lock); | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT) | |
1224 | printk(KERN_INFO "fusb300_cmdend\n"); | |
1225 | ||
1226 | ||
1227 | if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) { | |
1228 | printk(KERN_INFO "fusb300_cxout\n"); | |
1229 | fusb300_ep0out(fusb300); | |
1230 | } | |
1231 | ||
1232 | if (int_grp1 & FUSB300_IGR1_CX_IN_INT) { | |
1233 | printk(KERN_INFO "fusb300_cxin\n"); | |
1234 | fusb300_ep0in(fusb300); | |
1235 | } | |
1236 | ||
1237 | if (int_grp1 & FUSB300_IGR1_INTGRP5) | |
1238 | fusb300_grp5_handler(); | |
1239 | ||
1240 | if (int_grp1 & FUSB300_IGR1_INTGRP4) | |
1241 | fusb300_grp4_handler(); | |
1242 | ||
1243 | if (int_grp1 & FUSB300_IGR1_INTGRP3) | |
1244 | fusb300_grp3_handler(); | |
1245 | ||
1246 | if (int_grp1 & FUSB300_IGR1_INTGRP2) | |
1247 | fusb300_grp2_handler(); | |
1248 | ||
1249 | if (int_grp0) { | |
1250 | for (i = 1; i < FUSB300_MAX_NUM_EP; i++) { | |
1251 | if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) { | |
1252 | reg = ioread32(fusb300->reg + | |
1253 | FUSB300_OFFSET_EPSET1(i)); | |
1254 | in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0; | |
1255 | if (in) | |
1256 | in_ep_fifo_handler(fusb300->ep[i]); | |
1257 | else | |
1258 | out_ep_fifo_handler(fusb300->ep[i]); | |
1259 | } | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | spin_unlock(&fusb300->lock); | |
1264 | ||
1265 | return IRQ_HANDLED; | |
1266 | } | |
1267 | ||
1268 | static void fusb300_set_u2_timeout(struct fusb300 *fusb300, | |
1269 | u32 time) | |
1270 | { | |
1271 | u32 reg; | |
1272 | ||
1273 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); | |
1274 | reg &= ~0xff; | |
1275 | reg |= FUSB300_SSCR2_U2TIMEOUT(time); | |
1276 | ||
1277 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); | |
1278 | } | |
1279 | ||
1280 | static void fusb300_set_u1_timeout(struct fusb300 *fusb300, | |
1281 | u32 time) | |
1282 | { | |
1283 | u32 reg; | |
1284 | ||
1285 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); | |
1286 | reg &= ~(0xff << 8); | |
1287 | reg |= FUSB300_SSCR2_U1TIMEOUT(time); | |
1288 | ||
1289 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); | |
1290 | } | |
1291 | ||
1292 | static void init_controller(struct fusb300 *fusb300) | |
1293 | { | |
1294 | u32 reg; | |
1295 | u32 mask = 0; | |
1296 | u32 val = 0; | |
1297 | ||
1298 | /* split on */ | |
1299 | mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON; | |
1300 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR); | |
1301 | reg &= ~mask; | |
1302 | reg |= val; | |
1303 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR); | |
1304 | ||
1305 | /* enable high-speed LPM */ | |
1306 | mask = val = FUSB300_HSCR_HS_LPM_PERMIT; | |
1307 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR); | |
1308 | reg &= ~mask; | |
1309 | reg |= val; | |
1310 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR); | |
1311 | ||
1312 | /*set u1 u2 timmer*/ | |
1313 | fusb300_set_u2_timeout(fusb300, 0xff); | |
1314 | fusb300_set_u1_timeout(fusb300, 0xff); | |
1315 | ||
1316 | /* enable all grp1 interrupt */ | |
1317 | iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1); | |
1318 | } | |
1319 | /*------------------------------------------------------------------------*/ | |
1320 | static struct fusb300 *the_controller; | |
1321 | ||
0f91349b | 1322 | static int fusb300_udc_start(struct usb_gadget_driver *driver, |
0fe6f1d1 YHC |
1323 | int (*bind)(struct usb_gadget *)) |
1324 | { | |
1325 | struct fusb300 *fusb300 = the_controller; | |
1326 | int retval; | |
1327 | ||
1328 | if (!driver | |
1329 | || driver->speed < USB_SPEED_FULL | |
1330 | || !bind | |
1331 | || !driver->setup) | |
1332 | return -EINVAL; | |
1333 | ||
1334 | if (!fusb300) | |
1335 | return -ENODEV; | |
1336 | ||
1337 | if (fusb300->driver) | |
1338 | return -EBUSY; | |
1339 | ||
1340 | /* hook up the driver */ | |
1341 | driver->driver.bus = NULL; | |
1342 | fusb300->driver = driver; | |
1343 | fusb300->gadget.dev.driver = &driver->driver; | |
1344 | ||
1345 | retval = device_add(&fusb300->gadget.dev); | |
1346 | if (retval) { | |
1347 | pr_err("device_add error (%d)\n", retval); | |
1348 | goto error; | |
1349 | } | |
1350 | ||
1351 | retval = bind(&fusb300->gadget); | |
1352 | if (retval) { | |
1353 | pr_err("bind to driver error (%d)\n", retval); | |
1354 | device_del(&fusb300->gadget.dev); | |
1355 | goto error; | |
1356 | } | |
1357 | ||
1358 | return 0; | |
1359 | ||
1360 | error: | |
1361 | fusb300->driver = NULL; | |
1362 | fusb300->gadget.dev.driver = NULL; | |
1363 | ||
1364 | return retval; | |
1365 | } | |
0fe6f1d1 | 1366 | |
0f91349b | 1367 | static int fusb300_udc_stop(struct usb_gadget_driver *driver) |
0fe6f1d1 YHC |
1368 | { |
1369 | struct fusb300 *fusb300 = the_controller; | |
1370 | ||
1371 | if (driver != fusb300->driver || !driver->unbind) | |
1372 | return -EINVAL; | |
1373 | ||
1374 | driver->unbind(&fusb300->gadget); | |
1375 | fusb300->gadget.dev.driver = NULL; | |
1376 | ||
1377 | init_controller(fusb300); | |
1378 | device_del(&fusb300->gadget.dev); | |
1379 | fusb300->driver = NULL; | |
1380 | ||
1381 | return 0; | |
1382 | } | |
0fe6f1d1 YHC |
1383 | /*--------------------------------------------------------------------------*/ |
1384 | ||
1385 | static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active) | |
1386 | { | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static struct usb_gadget_ops fusb300_gadget_ops = { | |
1391 | .pullup = fusb300_udc_pullup, | |
0f91349b SAS |
1392 | .start = fusb300_udc_start, |
1393 | .stop = fusb300_udc_stop, | |
0fe6f1d1 YHC |
1394 | }; |
1395 | ||
1396 | static int __exit fusb300_remove(struct platform_device *pdev) | |
1397 | { | |
1398 | struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev); | |
1399 | ||
0f91349b | 1400 | usb_del_gadget_udc(&fusb300->gadget); |
0fe6f1d1 YHC |
1401 | iounmap(fusb300->reg); |
1402 | free_irq(platform_get_irq(pdev, 0), fusb300); | |
1403 | ||
1404 | fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req); | |
1405 | kfree(fusb300); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | static int __init fusb300_probe(struct platform_device *pdev) | |
1411 | { | |
1412 | struct resource *res, *ires, *ires1; | |
1413 | void __iomem *reg = NULL; | |
1414 | struct fusb300 *fusb300 = NULL; | |
1415 | struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP]; | |
1416 | int ret = 0; | |
1417 | int i; | |
1418 | ||
1419 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1420 | if (!res) { | |
1421 | ret = -ENODEV; | |
1422 | pr_err("platform_get_resource error.\n"); | |
1423 | goto clean_up; | |
1424 | } | |
1425 | ||
1426 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1427 | if (!ires) { | |
1428 | ret = -ENODEV; | |
1429 | dev_err(&pdev->dev, | |
1430 | "platform_get_resource IORESOURCE_IRQ error.\n"); | |
1431 | goto clean_up; | |
1432 | } | |
1433 | ||
1434 | ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
1435 | if (!ires1) { | |
1436 | ret = -ENODEV; | |
1437 | dev_err(&pdev->dev, | |
1438 | "platform_get_resource IORESOURCE_IRQ 1 error.\n"); | |
1439 | goto clean_up; | |
1440 | } | |
1441 | ||
1442 | reg = ioremap(res->start, resource_size(res)); | |
1443 | if (reg == NULL) { | |
1444 | ret = -ENOMEM; | |
1445 | pr_err("ioremap error.\n"); | |
1446 | goto clean_up; | |
1447 | } | |
1448 | ||
1449 | /* initialize udc */ | |
1450 | fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL); | |
1451 | if (fusb300 == NULL) { | |
1452 | pr_err("kzalloc error\n"); | |
1453 | goto clean_up; | |
1454 | } | |
1455 | ||
1456 | for (i = 0; i < FUSB300_MAX_NUM_EP; i++) { | |
1457 | _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL); | |
1458 | if (_ep[i] == NULL) { | |
1459 | pr_err("_ep kzalloc error\n"); | |
1460 | goto clean_up; | |
1461 | } | |
1462 | fusb300->ep[i] = _ep[i]; | |
1463 | } | |
1464 | ||
1465 | spin_lock_init(&fusb300->lock); | |
1466 | ||
1467 | dev_set_drvdata(&pdev->dev, fusb300); | |
1468 | ||
1469 | fusb300->gadget.ops = &fusb300_gadget_ops; | |
1470 | ||
1471 | device_initialize(&fusb300->gadget.dev); | |
1472 | ||
1473 | dev_set_name(&fusb300->gadget.dev, "gadget"); | |
1474 | ||
1475 | fusb300->gadget.is_dualspeed = 1; | |
1476 | fusb300->gadget.dev.parent = &pdev->dev; | |
1477 | fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
1478 | fusb300->gadget.dev.release = pdev->dev.release; | |
1479 | fusb300->gadget.name = udc_name; | |
1480 | fusb300->reg = reg; | |
1481 | ||
1482 | ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED, | |
1483 | udc_name, fusb300); | |
1484 | if (ret < 0) { | |
1485 | pr_err("request_irq error (%d)\n", ret); | |
1486 | goto clean_up; | |
1487 | } | |
1488 | ||
1489 | ret = request_irq(ires1->start, fusb300_irq, | |
1490 | IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300); | |
1491 | if (ret < 0) { | |
1492 | pr_err("request_irq1 error (%d)\n", ret); | |
1493 | goto clean_up; | |
1494 | } | |
1495 | ||
1496 | INIT_LIST_HEAD(&fusb300->gadget.ep_list); | |
1497 | ||
1498 | for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) { | |
1499 | struct fusb300_ep *ep = fusb300->ep[i]; | |
1500 | ||
1501 | if (i != 0) { | |
1502 | INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list); | |
1503 | list_add_tail(&fusb300->ep[i]->ep.ep_list, | |
1504 | &fusb300->gadget.ep_list); | |
1505 | } | |
1506 | ep->fusb300 = fusb300; | |
1507 | INIT_LIST_HEAD(&ep->queue); | |
1508 | ep->ep.name = fusb300_ep_name[i]; | |
1509 | ep->ep.ops = &fusb300_ep_ops; | |
1510 | ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE; | |
1511 | } | |
1512 | fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE; | |
1513 | fusb300->ep[0]->epnum = 0; | |
1514 | fusb300->gadget.ep0 = &fusb300->ep[0]->ep; | |
1515 | INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list); | |
1516 | ||
1517 | the_controller = fusb300; | |
1518 | ||
1519 | fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep, | |
1520 | GFP_KERNEL); | |
1521 | if (fusb300->ep0_req == NULL) | |
1522 | goto clean_up3; | |
1523 | ||
1524 | init_controller(fusb300); | |
0f91349b SAS |
1525 | ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget); |
1526 | if (ret) | |
1527 | goto err_add_udc; | |
1528 | ||
0fe6f1d1 YHC |
1529 | dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION); |
1530 | ||
1531 | return 0; | |
0f91349b SAS |
1532 | err_add_udc: |
1533 | fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req); | |
0fe6f1d1 YHC |
1534 | |
1535 | clean_up3: | |
1536 | free_irq(ires->start, fusb300); | |
1537 | ||
1538 | clean_up: | |
1539 | if (fusb300) { | |
1540 | if (fusb300->ep0_req) | |
1541 | fusb300_free_request(&fusb300->ep[0]->ep, | |
1542 | fusb300->ep0_req); | |
1543 | kfree(fusb300); | |
1544 | } | |
1545 | if (reg) | |
1546 | iounmap(reg); | |
1547 | ||
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | static struct platform_driver fusb300_driver = { | |
1552 | .remove = __exit_p(fusb300_remove), | |
1553 | .driver = { | |
1554 | .name = (char *) udc_name, | |
1555 | .owner = THIS_MODULE, | |
1556 | }, | |
1557 | }; | |
1558 | ||
1559 | static int __init fusb300_udc_init(void) | |
1560 | { | |
1561 | return platform_driver_probe(&fusb300_driver, fusb300_probe); | |
1562 | } | |
1563 | ||
1564 | module_init(fusb300_udc_init); | |
1565 | ||
1566 | static void __exit fusb300_udc_cleanup(void) | |
1567 | { | |
1568 | platform_driver_unregister(&fusb300_driver); | |
1569 | } | |
1570 | module_exit(fusb300_udc_cleanup); |