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USB: use usb_endpoint_maxp() instead of le16_to_cpu()
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / gadget / omap_udc.c
CommitLineData
1da177e4
LT		 1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
527ea73e
KP		 7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
1da177e4
LT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#undef DEBUG
25#undef VERBOSE
26
1da177e4
LT		 27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/ioport.h>
30#include <linux/types.h>
31#include <linux/errno.h>
32#include <linux/delay.h>
1da177e4
LT		 33#include <linux/slab.h>
34#include <linux/init.h>
35#include <linux/timer.h>
36#include <linux/list.h>
37#include <linux/interrupt.h>
38#include <linux/proc_fs.h>
39#include <linux/mm.h>
40#include <linux/moduleparam.h>
d052d1be 41#include <linux/platform_device.h>
5f848137 42#include <linux/usb/ch9.h>
9454a57a 43#include <linux/usb/gadget.h>
3a16f7b4 44#include <linux/usb/otg.h>
1da177e4 45#include <linux/dma-mapping.h>
e6a6e472 46#include <linux/clk.h>
268bb0ce 47#include <linux/prefetch.h>
1da177e4
LT		 48
49#include <asm/byteorder.h>
50#include <asm/io.h>
51#include <asm/irq.h>
52#include <asm/system.h>
53#include <asm/unaligned.h>
54#include <asm/mach-types.h>
55
ce491cf8
TL		 56#include <plat/dma.h>
57#include <plat/usb.h>
1da177e4
LT		 58
59#include "omap_udc.h"
60
61#undef USB_TRACE
62
63/* bulk DMA seems to be behaving for both IN and OUT */
64#define USE_DMA
65
66/* ISO too */
67#define USE_ISO
68
69#define DRIVER_DESC "OMAP UDC driver"
70#define DRIVER_VERSION "4 October 2004"
71
72#define DMA_ADDR_INVALID (~(dma_addr_t)0)
73
527ea73e
KP		 74#define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
75#define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
1da177e4
LT		 76
77/*
78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
79 * D+ pullup to allow enumeration. That's too early for the gadget
80 * framework to use from usb_endpoint_enable(), which happens after
81 * enumeration as part of activating an interface. (But if we add an
82 * optional new "UDC not yet running" state to the gadget driver model,
83 * even just during driver binding, the endpoint autoconfig logic is the
84 * natural spot to manufacture new endpoints.)
85 *
86 * So instead of using endpoint enable calls to control the hardware setup,
87 * this driver defines a "fifo mode" parameter. It's used during driver
88 * initialization to choose among a set of pre-defined endpoint configs.
89 * See omap_udc_setup() for available modes, or to add others. That code
90 * lives in an init section, so use this driver as a module if you need
91 * to change the fifo mode after the kernel boots.
92 *
93 * Gadget drivers normally ignore endpoints they don't care about, and
94 * won't include them in configuration descriptors. That means only
95 * misbehaving hosts would even notice they exist.
96 */
97#ifdef USE_ISO
98static unsigned fifo_mode = 3;
99#else
100static unsigned fifo_mode = 0;
101#endif
102
103/* "modprobe omap_udc fifo_mode=42", or else as a kernel
104 * boot parameter "omap_udc:fifo_mode=42"
105 */
106module_param (fifo_mode, uint, 0);
e6a6e472 107MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
1da177e4
LT		 108
109#ifdef USE_DMA
110static unsigned use_dma = 1;
111
112/* "modprobe omap_udc use_dma=y", or else as a kernel
113 * boot parameter "omap_udc:use_dma=y"
114 */
115module_param (use_dma, bool, 0);
116MODULE_PARM_DESC (use_dma, "enable/disable DMA");
117#else /* !USE_DMA */
118
119/* save a bit of code */
120#define use_dma 0
121#endif /* !USE_DMA */
122
123
124static const char driver_name [] = "omap_udc";
125static const char driver_desc [] = DRIVER_DESC;
126
127/*-------------------------------------------------------------------------*/
128
129/* there's a notion of "current endpoint" for modifying endpoint
e6a6e472 130 * state, and PIO access to its FIFO.
1da177e4
LT		 131 */
132
133static void use_ep(struct omap_ep *ep, u16 select)
134{
135 u16 num = ep->bEndpointAddress & 0x0f;
136
137 if (ep->bEndpointAddress & USB_DIR_IN)
138 num |= UDC_EP_DIR;
f35ae634 139 omap_writew(num | select, UDC_EP_NUM);
1da177e4
LT		 140 /* when select, MUST deselect later !! */
141}
142
143static inline void deselect_ep(void)
144{
f35ae634
TL		 145 u16 w;
146
147 w = omap_readw(UDC_EP_NUM);
148 w &= ~UDC_EP_SEL;
149 omap_writew(w, UDC_EP_NUM);
1da177e4
LT		 150 /* 6 wait states before TX will happen */
151}
152
153static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
154
155/*-------------------------------------------------------------------------*/
156
157static int omap_ep_enable(struct usb_ep *_ep,
158 const struct usb_endpoint_descriptor *desc)
159{
160 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
161 struct omap_udc *udc;
162 unsigned long flags;
163 u16 maxp;
164
165 /* catch various bogus parameters */
166 if (!_ep || !desc || ep->desc
167 || desc->bDescriptorType != USB_DT_ENDPOINT
168 || ep->bEndpointAddress != desc->bEndpointAddress
29cc8897 169 || ep->maxpacket < usb_endpoint_maxp(desc)) {
441b62c1 170 DBG("%s, bad ep or descriptor\n", __func__);
1da177e4
LT		 171 return -EINVAL;
172 }
29cc8897 173 maxp = usb_endpoint_maxp(desc);
1da177e4
LT		 174 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
175 && maxp != ep->maxpacket)
29cc8897 176 || usb_endpoint_maxp(desc) > ep->maxpacket
1da177e4 177 || !desc->wMaxPacketSize) {
441b62c1 178 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
1da177e4
LT		 179 return -ERANGE;
180 }
181
182#ifdef USE_ISO
183 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
184 && desc->bInterval != 1)) {
185 /* hardware wants period = 1; USB allows 2^(Interval-1) */
186 DBG("%s, unsupported ISO period %dms\n", _ep->name,
187 1 << (desc->bInterval - 1));
188 return -EDOM;
189 }
190#else
191 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
192 DBG("%s, ISO nyet\n", _ep->name);
193 return -EDOM;
194 }
195#endif
196
197 /* xfer types must match, except that interrupt ~= bulk */
198 if (ep->bmAttributes != desc->bmAttributes
199 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
200 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
441b62c1 201 DBG("%s, %s type mismatch\n", __func__, _ep->name);
1da177e4
LT		 202 return -EINVAL;
203 }
204
205 udc = ep->udc;
206 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
441b62c1 207 DBG("%s, bogus device state\n", __func__);
1da177e4
LT		 208 return -ESHUTDOWN;
209 }
210
211 spin_lock_irqsave(&udc->lock, flags);
212
213 ep->desc = desc;
214 ep->irqs = 0;
215 ep->stopped = 0;
216 ep->ep.maxpacket = maxp;
217
218 /* set endpoint to initial state */
219 ep->dma_channel = 0;
220 ep->has_dma = 0;
221 ep->lch = -1;
222 use_ep(ep, UDC_EP_SEL);
f35ae634 223 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 224 ep->ackwait = 0;
225 deselect_ep();
226
227 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
228 list_add(&ep->iso, &udc->iso);
229
230 /* maybe assign a DMA channel to this endpoint */
231 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
232 /* FIXME ISO can dma, but prefers first channel */
233 dma_channel_claim(ep, 0);
234
235 /* PIO OUT may RX packets */
236 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
237 && !ep->has_dma
238 && !(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 239 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 240 ep->ackwait = 1 + ep->double_buf;
241 }
242
243 spin_unlock_irqrestore(&udc->lock, flags);
244 VDBG("%s enabled\n", _ep->name);
245 return 0;
246}
247
248static void nuke(struct omap_ep *, int status);
249
250static int omap_ep_disable(struct usb_ep *_ep)
251{
252 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
253 unsigned long flags;
254
255 if (!_ep || !ep->desc) {
441b62c1 256 DBG("%s, %s not enabled\n", __func__,
1da177e4
LT		 257 _ep ? ep->ep.name : NULL);
258 return -EINVAL;
259 }
260
261 spin_lock_irqsave(&ep->udc->lock, flags);
313980c9 262 ep->desc = NULL;
1da177e4
LT		 263 nuke (ep, -ESHUTDOWN);
264 ep->ep.maxpacket = ep->maxpacket;
265 ep->has_dma = 0;
f35ae634 266 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 267 list_del_init(&ep->iso);
268 del_timer(&ep->timer);
269
270 spin_unlock_irqrestore(&ep->udc->lock, flags);
271
272 VDBG("%s disabled\n", _ep->name);
273 return 0;
274}
275
276/*-------------------------------------------------------------------------*/
277
278static struct usb_request *
55016f10 279omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1da177e4
LT		 280{
281 struct omap_req *req;
282
7039f422 283 req = kzalloc(sizeof(*req), gfp_flags);
1da177e4 284 if (req) {
1da177e4
LT		 285 req->req.dma = DMA_ADDR_INVALID;
286 INIT_LIST_HEAD (&req->queue);
287 }
288 return &req->req;
289}
290
291static void
292omap_free_request(struct usb_ep *ep, struct usb_request *_req)
293{
294 struct omap_req *req = container_of(_req, struct omap_req, req);
295
296 if (_req)
297 kfree (req);
298}
299
300/*-------------------------------------------------------------------------*/
301
1da177e4
LT		 302static void
303done(struct omap_ep *ep, struct omap_req *req, int status)
304{
305 unsigned stopped = ep->stopped;
306
307 list_del_init(&req->queue);
308
309 if (req->req.status == -EINPROGRESS)
310 req->req.status = status;
311 else
312 status = req->req.status;
313
314 if (use_dma && ep->has_dma) {
315 if (req->mapped) {
316 dma_unmap_single(ep->udc->gadget.dev.parent,
317 req->req.dma, req->req.length,
318 (ep->bEndpointAddress & USB_DIR_IN)
319 ? DMA_TO_DEVICE
320 : DMA_FROM_DEVICE);
321 req->req.dma = DMA_ADDR_INVALID;
322 req->mapped = 0;
323 } else
324 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
325 req->req.dma, req->req.length,
326 (ep->bEndpointAddress & USB_DIR_IN)
327 ? DMA_TO_DEVICE
328 : DMA_FROM_DEVICE);
329 }
330
331#ifndef USB_TRACE
332 if (status && status != -ESHUTDOWN)
333#endif
334 VDBG("complete %s req %p stat %d len %u/%u\n",
335 ep->ep.name, &req->req, status,
336 req->req.actual, req->req.length);
337
338 /* don't modify queue heads during completion callback */
339 ep->stopped = 1;
340 spin_unlock(&ep->udc->lock);
341 req->req.complete(&ep->ep, &req->req);
342 spin_lock(&ep->udc->lock);
343 ep->stopped = stopped;
344}
345
346/*-------------------------------------------------------------------------*/
347
313980c9
DB		 348#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
349#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
1da177e4
LT		 350
351#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
352#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
353
e6a6e472 354static inline int
1da177e4
LT		 355write_packet(u8 *buf, struct omap_req *req, unsigned max)
356{
357 unsigned len;
358 u16 *wp;
359
360 len = min(req->req.length - req->req.actual, max);
361 req->req.actual += len;
362
363 max = len;
364 if (likely((((int)buf) & 1) == 0)) {
365 wp = (u16 *)buf;
366 while (max >= 2) {
f35ae634 367 omap_writew(*wp++, UDC_DATA);
1da177e4
LT		 368 max -= 2;
369 }
370 buf = (u8 *)wp;
371 }
372 while (max--)
f35ae634 373 omap_writeb(*buf++, UDC_DATA);
1da177e4
LT		 374 return len;
375}
376
377// FIXME change r/w fifo calling convention
378
379
380// return: 0 = still running, 1 = completed, negative = errno
381static int write_fifo(struct omap_ep *ep, struct omap_req *req)
382{
383 u8 *buf;
384 unsigned count;
385 int is_last;
386 u16 ep_stat;
387
388 buf = req->req.buf + req->req.actual;
389 prefetch(buf);
390
391 /* PIO-IN isn't double buffered except for iso */
f35ae634 392 ep_stat = omap_readw(UDC_STAT_FLG);
313980c9 393 if (ep_stat & UDC_FIFO_UNWRITABLE)
1da177e4
LT		 394 return 0;
395
396 count = ep->ep.maxpacket;
397 count = write_packet(buf, req, count);
f35ae634 398 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 399 ep->ackwait = 1;
400
401 /* last packet is often short (sometimes a zlp) */
402 if (count != ep->ep.maxpacket)
403 is_last = 1;
404 else if (req->req.length == req->req.actual
405 && !req->req.zero)
406 is_last = 1;
407 else
408 is_last = 0;
409
410 /* NOTE: requests complete when all IN data is in a
411 * FIFO (or sometimes later, if a zlp was needed).
412 * Use usb_ep_fifo_status() where needed.
413 */
414 if (is_last)
415 done(ep, req, 0);
416 return is_last;
417}
418
e6a6e472 419static inline int
1da177e4
LT		 420read_packet(u8 *buf, struct omap_req *req, unsigned avail)
421{
422 unsigned len;
423 u16 *wp;
424
425 len = min(req->req.length - req->req.actual, avail);
426 req->req.actual += len;
427 avail = len;
428
429 if (likely((((int)buf) & 1) == 0)) {
430 wp = (u16 *)buf;
431 while (avail >= 2) {
f35ae634 432 *wp++ = omap_readw(UDC_DATA);
1da177e4
LT		 433 avail -= 2;
434 }
435 buf = (u8 *)wp;
436 }
437 while (avail--)
f35ae634 438 *buf++ = omap_readb(UDC_DATA);
1da177e4
LT		 439 return len;
440}
441
442// return: 0 = still running, 1 = queue empty, negative = errno
443static int read_fifo(struct omap_ep *ep, struct omap_req *req)
444{
445 u8 *buf;
446 unsigned count, avail;
447 int is_last;
448
449 buf = req->req.buf + req->req.actual;
450 prefetchw(buf);
451
452 for (;;) {
f35ae634 453 u16 ep_stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 454
455 is_last = 0;
456 if (ep_stat & FIFO_EMPTY) {
457 if (!ep->double_buf)
458 break;
459 ep->fnf = 1;
460 }
461 if (ep_stat & UDC_EP_HALTED)
462 break;
463
313980c9 464 if (ep_stat & UDC_FIFO_FULL)
1da177e4
LT		 465 avail = ep->ep.maxpacket;
466 else {
f35ae634 467 avail = omap_readw(UDC_RXFSTAT);
1da177e4
LT		 468 ep->fnf = ep->double_buf;
469 }
470 count = read_packet(buf, req, avail);
471
472 /* partial packet reads may not be errors */
473 if (count < ep->ep.maxpacket) {
474 is_last = 1;
475 /* overflowed this request? flush extra data */
476 if (count != avail) {
477 req->req.status = -EOVERFLOW;
478 avail -= count;
479 while (avail--)
f35ae634 480 omap_readw(UDC_DATA);
1da177e4
LT		 481 }
482 } else if (req->req.length == req->req.actual)
483 is_last = 1;
484 else
485 is_last = 0;
486
487 if (!ep->bEndpointAddress)
488 break;
489 if (is_last)
490 done(ep, req, 0);
491 break;
492 }
493 return is_last;
494}
495
496/*-------------------------------------------------------------------------*/
497
498static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
499{
500 dma_addr_t end;
501
502 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
503 * the last transfer's bytecount by more than a FIFO's worth.
504 */
505 if (cpu_is_omap15xx())
506 return 0;
507
0499bdeb 508 end = omap_get_dma_src_pos(ep->lch);
1da177e4
LT		 509 if (end == ep->dma_counter)
510 return 0;
511
512 end |= start & (0xffff << 16);
513 if (end < start)
514 end += 0x10000;
515 return end - start;
516}
517
1da177e4
LT		 518static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
519{
520 dma_addr_t end;
521
0499bdeb 522 end = omap_get_dma_dst_pos(ep->lch);
1da177e4
LT		 523 if (end == ep->dma_counter)
524 return 0;
525
526 end |= start & (0xffff << 16);
527 if (cpu_is_omap15xx())
528 end++;
529 if (end < start)
530 end += 0x10000;
531 return end - start;
532}
533
534
535/* Each USB transfer request using DMA maps to one or more DMA transfers.
536 * When DMA completion isn't request completion, the UDC continues with
537 * the next DMA transfer for that USB transfer.
538 */
539
540static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
541{
f35ae634 542 u16 txdma_ctrl, w;
1da177e4
LT		 543 unsigned length = req->req.length - req->req.actual;
544 const int sync_mode = cpu_is_omap15xx()
545 ? OMAP_DMA_SYNC_FRAME
546 : OMAP_DMA_SYNC_ELEMENT;
527ea73e
KP		 547 int dma_trigger = 0;
548
549 if (cpu_is_omap24xx())
550 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
1da177e4
LT		 551
552 /* measure length in either bytes or packets */
65111084 553 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
527ea73e 554 || (cpu_is_omap24xx() && length < ep->maxpacket)
1da177e4
LT		 555 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
556 txdma_ctrl = UDC_TXN_EOT | length;
557 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
527ea73e 558 length, 1, sync_mode, dma_trigger, 0);
1da177e4
LT		 559 } else {
560 length = min(length / ep->maxpacket,
561 (unsigned) UDC_TXN_TSC + 1);
e6a6e472 562 txdma_ctrl = length;
65111084 563 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
e6a6e472 564 ep->ep.maxpacket >> 1, length, sync_mode,
527ea73e 565 dma_trigger, 0);
1da177e4
LT		 566 length *= ep->maxpacket;
567 }
568 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 569 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
570 0, 0);
1da177e4
LT		 571
572 omap_start_dma(ep->lch);
0499bdeb 573 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
f35ae634
TL		 574 w = omap_readw(UDC_DMA_IRQ_EN);
575 w |= UDC_TX_DONE_IE(ep->dma_channel);
576 omap_writew(w, UDC_DMA_IRQ_EN);
577 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
1da177e4
LT		 578 req->dma_bytes = length;
579}
580
581static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
582{
f35ae634
TL		 583 u16 w;
584
1da177e4
LT		 585 if (status == 0) {
586 req->req.actual += req->dma_bytes;
587
588 /* return if this request needs to send data or zlp */
589 if (req->req.actual < req->req.length)
590 return;
591 if (req->req.zero
592 && req->dma_bytes != 0
593 && (req->req.actual % ep->maxpacket) == 0)
594 return;
595 } else
596 req->req.actual += dma_src_len(ep, req->req.dma
597 + req->req.actual);
598
599 /* tx completion */
600 omap_stop_dma(ep->lch);
f35ae634
TL		 601 w = omap_readw(UDC_DMA_IRQ_EN);
602 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
603 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 604 done(ep, req, status);
605}
606
607static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
608{
527ea73e
KP		 609 unsigned packets = req->req.length - req->req.actual;
610 int dma_trigger = 0;
f35ae634 611 u16 w;
527ea73e
KP		 612
613 if (cpu_is_omap24xx())
614 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
1da177e4
LT		 615
616 /* NOTE: we filtered out "short reads" before, so we know
617 * the buffer has only whole numbers of packets.
527ea73e 618 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
1da177e4 619 */
527ea73e
KP		 620 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
621 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
622 packets, 1, OMAP_DMA_SYNC_ELEMENT,
623 dma_trigger, 0);
624 req->dma_bytes = packets;
625 } else {
626 /* set up this DMA transfer, enable the fifo, start */
627 packets /= ep->ep.maxpacket;
628 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
629 req->dma_bytes = packets * ep->ep.maxpacket;
630 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
631 ep->ep.maxpacket >> 1, packets,
632 OMAP_DMA_SYNC_ELEMENT,
633 dma_trigger, 0);
634 }
1da177e4 635 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 636 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
637 0, 0);
0499bdeb 638 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
1da177e4 639
f35ae634
TL		 640 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
641 w = omap_readw(UDC_DMA_IRQ_EN);
642 w |= UDC_RX_EOT_IE(ep->dma_channel);
643 omap_writew(w, UDC_DMA_IRQ_EN);
644 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
645 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 646
647 omap_start_dma(ep->lch);
648}
649
650static void
cb97c5c9 651finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
1da177e4 652{
f35ae634 653 u16 count, w;
1da177e4
LT		 654
655 if (status == 0)
656 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
657 count = dma_dest_len(ep, req->req.dma + req->req.actual);
658 count += req->req.actual;
cb97c5c9
DB		 659 if (one)
660 count--;
1da177e4
LT		 661 if (count <= req->req.length)
662 req->req.actual = count;
663
664 if (count != req->dma_bytes || status)
665 omap_stop_dma(ep->lch);
666
667 /* if this wasn't short, request may need another transfer */
668 else if (req->req.actual < req->req.length)
669 return;
670
671 /* rx completion */
f35ae634
TL		 672 w = omap_readw(UDC_DMA_IRQ_EN);
673 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
674 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 675 done(ep, req, status);
676}
677
678static void dma_irq(struct omap_udc *udc, u16 irq_src)
679{
f35ae634 680 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
1da177e4
LT		 681 struct omap_ep *ep;
682 struct omap_req *req;
683
684 /* IN dma: tx to host */
685 if (irq_src & UDC_TXN_DONE) {
686 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
687 ep->irqs++;
688 /* can see TXN_DONE after dma abort */
689 if (!list_empty(&ep->queue)) {
690 req = container_of(ep->queue.next,
691 struct omap_req, queue);
692 finish_in_dma(ep, req, 0);
693 }
f35ae634 694 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
1da177e4
LT		 695
696 if (!list_empty (&ep->queue)) {
697 req = container_of(ep->queue.next,
698 struct omap_req, queue);
699 next_in_dma(ep, req);
700 }
701 }
702
703 /* OUT dma: rx from host */
704 if (irq_src & UDC_RXN_EOT) {
705 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
706 ep->irqs++;
707 /* can see RXN_EOT after dma abort */
708 if (!list_empty(&ep->queue)) {
709 req = container_of(ep->queue.next,
710 struct omap_req, queue);
cb97c5c9 711 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
1da177e4 712 }
f35ae634 713 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
1da177e4
LT		 714
715 if (!list_empty (&ep->queue)) {
716 req = container_of(ep->queue.next,
717 struct omap_req, queue);
718 next_out_dma(ep, req);
719 }
720 }
721
722 if (irq_src & UDC_RXN_CNT) {
723 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
724 ep->irqs++;
725 /* omap15xx does this unasked... */
726 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
f35ae634 727 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
1da177e4
LT		 728 }
729}
730
731static void dma_error(int lch, u16 ch_status, void *data)
732{
733 struct omap_ep *ep = data;
734
735 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
7ff879db 736 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
1da177e4
LT		 737 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
738
739 /* complete current transfer ... */
740}
741
742static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
743{
744 u16 reg;
745 int status, restart, is_in;
527ea73e 746 int dma_channel;
1da177e4
LT		 747
748 is_in = ep->bEndpointAddress & USB_DIR_IN;
749 if (is_in)
f35ae634 750 reg = omap_readw(UDC_TXDMA_CFG);
1da177e4 751 else
f35ae634 752 reg = omap_readw(UDC_RXDMA_CFG);
65111084 753 reg |= UDC_DMA_REQ; /* "pulse" activated */
1da177e4
LT		 754
755 ep->dma_channel = 0;
756 ep->lch = -1;
757 if (channel == 0 || channel > 3) {
758 if ((reg & 0x0f00) == 0)
759 channel = 3;
760 else if ((reg & 0x00f0) == 0)
761 channel = 2;
762 else if ((reg & 0x000f) == 0) /* preferred for ISO */
763 channel = 1;
764 else {
765 status = -EMLINK;
766 goto just_restart;
767 }
768 }
769 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
770 ep->dma_channel = channel;
771
772 if (is_in) {
527ea73e
KP		 773 if (cpu_is_omap24xx())
774 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
775 else
776 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
777 status = omap_request_dma(dma_channel,
1da177e4
LT		 778 ep->ep.name, dma_error, ep, &ep->lch);
779 if (status == 0) {
f35ae634 780 omap_writew(reg, UDC_TXDMA_CFG);
527ea73e 781 /* EMIFF or SDRC */
65111084
DB		 782 omap_set_dma_src_burst_mode(ep->lch,
783 OMAP_DMA_DATA_BURST_4);
784 omap_set_dma_src_data_pack(ep->lch, 1);
785 /* TIPB */
1da177e4
LT		 786 omap_set_dma_dest_params(ep->lch,
787 OMAP_DMA_PORT_TIPB,
788 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 789 UDC_DATA_DMA,
e6a6e472 790 0, 0);
1da177e4
LT		 791 }
792 } else {
527ea73e
KP		 793 if (cpu_is_omap24xx())
794 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
795 else
796 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
797
798 status = omap_request_dma(dma_channel,
1da177e4
LT		 799 ep->ep.name, dma_error, ep, &ep->lch);
800 if (status == 0) {
f35ae634 801 omap_writew(reg, UDC_RXDMA_CFG);
65111084 802 /* TIPB */
1da177e4
LT		 803 omap_set_dma_src_params(ep->lch,
804 OMAP_DMA_PORT_TIPB,
805 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 806 UDC_DATA_DMA,
e6a6e472 807 0, 0);
527ea73e 808 /* EMIFF or SDRC */
65111084
DB		 809 omap_set_dma_dest_burst_mode(ep->lch,
810 OMAP_DMA_DATA_BURST_4);
811 omap_set_dma_dest_data_pack(ep->lch, 1);
1da177e4
LT		 812 }
813 }
814 if (status)
815 ep->dma_channel = 0;
816 else {
817 ep->has_dma = 1;
818 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
819
820 /* channel type P: hw synch (fifo) */
527ea73e 821 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
0499bdeb 822 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
1da177e4
LT		 823 }
824
825just_restart:
826 /* restart any queue, even if the claim failed */
827 restart = !ep->stopped && !list_empty(&ep->queue);
828
829 if (status)
830 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
831 restart ? " (restart)" : "");
832 else
833 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
834 is_in ? 't' : 'r',
835 ep->dma_channel - 1, ep->lch,
836 restart ? " (restart)" : "");
837
838 if (restart) {
839 struct omap_req *req;
840 req = container_of(ep->queue.next, struct omap_req, queue);
841 if (ep->has_dma)
842 (is_in ? next_in_dma : next_out_dma)(ep, req);
843 else {
844 use_ep(ep, UDC_EP_SEL);
845 (is_in ? write_fifo : read_fifo)(ep, req);
846 deselect_ep();
847 if (!is_in) {
f35ae634 848 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 849 ep->ackwait = 1 + ep->double_buf;
850 }
851 /* IN: 6 wait states before it'll tx */
852 }
853 }
854}
855
856static void dma_channel_release(struct omap_ep *ep)
857{
858 int shift = 4 * (ep->dma_channel - 1);
859 u16 mask = 0x0f << shift;
860 struct omap_req *req;
861 int active;
862
863 /* abort any active usb transfer request */
864 if (!list_empty(&ep->queue))
865 req = container_of(ep->queue.next, struct omap_req, queue);
866 else
313980c9 867 req = NULL;
1da177e4 868
0499bdeb 869 active = omap_get_dma_active_status(ep->lch);
1da177e4
LT		 870
871 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
872 active ? "active" : "idle",
873 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
874 ep->dma_channel - 1, req);
875
65111084
DB		 876 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
877 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
878 */
879
1da177e4
LT		 880 /* wait till current packet DMA finishes, and fifo empties */
881 if (ep->bEndpointAddress & USB_DIR_IN) {
f35ae634
TL		 882 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
883 UDC_TXDMA_CFG);
1da177e4
LT		 884
885 if (req) {
886 finish_in_dma(ep, req, -ECONNRESET);
887
888 /* clear FIFO; hosts probably won't empty it */
889 use_ep(ep, UDC_EP_SEL);
f35ae634 890 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4
LT		 891 deselect_ep();
892 }
f35ae634 893 while (omap_readw(UDC_TXDMA_CFG) & mask)
1da177e4
LT		 894 udelay(10);
895 } else {
f35ae634
TL		 896 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
897 UDC_RXDMA_CFG);
1da177e4
LT		 898
899 /* dma empties the fifo */
f35ae634 900 while (omap_readw(UDC_RXDMA_CFG) & mask)
1da177e4
LT		 901 udelay(10);
902 if (req)
cb97c5c9 903 finish_out_dma(ep, req, -ECONNRESET, 0);
1da177e4
LT		 904 }
905 omap_free_dma(ep->lch);
906 ep->dma_channel = 0;
907 ep->lch = -1;
908 /* has_dma still set, till endpoint is fully quiesced */
909}
910
911
912/*-------------------------------------------------------------------------*/
913
914static int
55016f10 915omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1da177e4
LT		 916{
917 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
918 struct omap_req *req = container_of(_req, struct omap_req, req);
919 struct omap_udc *udc;
920 unsigned long flags;
921 int is_iso = 0;
922
923 /* catch various bogus parameters */
924 if (!_req || !req->req.complete || !req->req.buf
925 || !list_empty(&req->queue)) {
441b62c1 926 DBG("%s, bad params\n", __func__);
1da177e4
LT		 927 return -EINVAL;
928 }
929 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
441b62c1 930 DBG("%s, bad ep\n", __func__);
1da177e4
LT		 931 return -EINVAL;
932 }
933 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
934 if (req->req.length > ep->ep.maxpacket)
935 return -EMSGSIZE;
936 is_iso = 1;
937 }
938
939 /* this isn't bogus, but OMAP DMA isn't the only hardware to
940 * have a hard time with partial packet reads... reject it.
527ea73e 941 * Except OMAP2 can handle the small packets.
1da177e4
LT		 942 */
943 if (use_dma
944 && ep->has_dma
945 && ep->bEndpointAddress != 0
946 && (ep->bEndpointAddress & USB_DIR_IN) == 0
527ea73e 947 && !cpu_class_is_omap2()
1da177e4 948 && (req->req.length % ep->ep.maxpacket) != 0) {
441b62c1 949 DBG("%s, no partial packet OUT reads\n", __func__);
1da177e4
LT		 950 return -EMSGSIZE;
951 }
952
953 udc = ep->udc;
954 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
955 return -ESHUTDOWN;
956
957 if (use_dma && ep->has_dma) {
958 if (req->req.dma == DMA_ADDR_INVALID) {
959 req->req.dma = dma_map_single(
960 ep->udc->gadget.dev.parent,
961 req->req.buf,
962 req->req.length,
963 (ep->bEndpointAddress & USB_DIR_IN)
964 ? DMA_TO_DEVICE
965 : DMA_FROM_DEVICE);
966 req->mapped = 1;
967 } else {
968 dma_sync_single_for_device(
969 ep->udc->gadget.dev.parent,
970 req->req.dma, req->req.length,
971 (ep->bEndpointAddress & USB_DIR_IN)
972 ? DMA_TO_DEVICE
973 : DMA_FROM_DEVICE);
974 req->mapped = 0;
975 }
976 }
977
978 VDBG("%s queue req %p, len %d buf %p\n",
979 ep->ep.name, _req, _req->length, _req->buf);
980
981 spin_lock_irqsave(&udc->lock, flags);
982
983 req->req.status = -EINPROGRESS;
984 req->req.actual = 0;
985
986 /* maybe kickstart non-iso i/o queues */
f35ae634
TL		 987 if (is_iso) {
988 u16 w;
989
990 w = omap_readw(UDC_IRQ_EN);
991 w |= UDC_SOF_IE;
992 omap_writew(w, UDC_IRQ_EN);
993 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1da177e4
LT		 994 int is_in;
995
996 if (ep->bEndpointAddress == 0) {
997 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
998 spin_unlock_irqrestore(&udc->lock, flags);
999 return -EL2HLT;
1000 }
1001
1002 /* empty DATA stage? */
1003 is_in = udc->ep0_in;
1004 if (!req->req.length) {
1005
1006 /* chip became CONFIGURED or ADDRESSED
1007 * earlier; drivers may already have queued
1008 * requests to non-control endpoints
1009 */
1010 if (udc->ep0_set_config) {
f35ae634 1011 u16 irq_en = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 1012
1013 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1014 if (!udc->ep0_reset_config)
1015 irq_en |= UDC_EPN_RX_IE
1016 | UDC_EPN_TX_IE;
f35ae634 1017 omap_writew(irq_en, UDC_IRQ_EN);
1da177e4
LT		 1018 }
1019
313980c9
DB		 1020 /* STATUS for zero length DATA stages is
1021 * always an IN ... even for IN transfers,
dc0d5c1e 1022 * a weird case which seem to stall OMAP.
313980c9 1023 */
f35ae634
TL		 1024 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1025 omap_writew(UDC_CLR_EP, UDC_CTRL);
1026 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1027 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1028
1029 /* cleanup */
1030 udc->ep0_pending = 0;
1031 done(ep, req, 0);
313980c9 1032 req = NULL;
1da177e4
LT		 1033
1034 /* non-empty DATA stage */
1035 } else if (is_in) {
f35ae634 1036 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1037 } else {
1038 if (udc->ep0_setup)
1039 goto irq_wait;
f35ae634 1040 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1da177e4
LT		 1041 }
1042 } else {
1043 is_in = ep->bEndpointAddress & USB_DIR_IN;
1044 if (!ep->has_dma)
1045 use_ep(ep, UDC_EP_SEL);
1046 /* if ISO: SOF IRQs must be enabled/disabled! */
1047 }
1048
1049 if (ep->has_dma)
1050 (is_in ? next_in_dma : next_out_dma)(ep, req);
1051 else if (req) {
1052 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
313980c9 1053 req = NULL;
1da177e4
LT		 1054 deselect_ep();
1055 if (!is_in) {
f35ae634 1056 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1057 ep->ackwait = 1 + ep->double_buf;
1058 }
1059 /* IN: 6 wait states before it'll tx */
1060 }
1061 }
1062
1063irq_wait:
1064 /* irq handler advances the queue */
313980c9 1065 if (req != NULL)
1da177e4
LT		 1066 list_add_tail(&req->queue, &ep->queue);
1067 spin_unlock_irqrestore(&udc->lock, flags);
1068
1069 return 0;
1070}
1071
1072static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1073{
1074 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1075 struct omap_req *req;
1076 unsigned long flags;
1077
1078 if (!_ep || !_req)
1079 return -EINVAL;
1080
1081 spin_lock_irqsave(&ep->udc->lock, flags);
1082
1083 /* make sure it's actually queued on this endpoint */
1084 list_for_each_entry (req, &ep->queue, queue) {
1085 if (&req->req == _req)
1086 break;
1087 }
1088 if (&req->req != _req) {
1089 spin_unlock_irqrestore(&ep->udc->lock, flags);
1090 return -EINVAL;
1091 }
1092
1093 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1094 int channel = ep->dma_channel;
1095
1096 /* releasing the channel cancels the request,
1097 * reclaiming the channel restarts the queue
1098 */
1099 dma_channel_release(ep);
1100 dma_channel_claim(ep, channel);
e6a6e472 1101 } else
1da177e4
LT		 1102 done(ep, req, -ECONNRESET);
1103 spin_unlock_irqrestore(&ep->udc->lock, flags);
1104 return 0;
1105}
1106
1107/*-------------------------------------------------------------------------*/
1108
1109static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1110{
1111 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1112 unsigned long flags;
1113 int status = -EOPNOTSUPP;
1114
1115 spin_lock_irqsave(&ep->udc->lock, flags);
1116
1117 /* just use protocol stalls for ep0; real halts are annoying */
1118 if (ep->bEndpointAddress == 0) {
1119 if (!ep->udc->ep0_pending)
1120 status = -EINVAL;
1121 else if (value) {
1122 if (ep->udc->ep0_set_config) {
b6c63937 1123 WARNING("error changing config?\n");
f35ae634 1124 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1125 }
f35ae634 1126 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1127 ep->udc->ep0_pending = 0;
1128 status = 0;
1129 } else /* NOP */
1130 status = 0;
1131
1132 /* otherwise, all active non-ISO endpoints can halt */
1133 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1134
1135 /* IN endpoints must already be idle */
1136 if ((ep->bEndpointAddress & USB_DIR_IN)
e6a6e472 1137 && !list_empty(&ep->queue)) {
1da177e4
LT		 1138 status = -EAGAIN;
1139 goto done;
1140 }
1141
1142 if (value) {
1143 int channel;
1144
1145 if (use_dma && ep->dma_channel
1146 && !list_empty(&ep->queue)) {
1147 channel = ep->dma_channel;
1148 dma_channel_release(ep);
1149 } else
1150 channel = 0;
1151
1152 use_ep(ep, UDC_EP_SEL);
f35ae634
TL		 1153 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1154 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1155 status = 0;
1156 } else
1157 status = -EAGAIN;
1158 deselect_ep();
1159
1160 if (channel)
1161 dma_channel_claim(ep, channel);
1162 } else {
1163 use_ep(ep, 0);
f35ae634 1164 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1165 ep->ackwait = 0;
1166 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1167 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1168 ep->ackwait = 1 + ep->double_buf;
1169 }
1170 }
1171 }
1172done:
1173 VDBG("%s %s halt stat %d\n", ep->ep.name,
1174 value ? "set" : "clear", status);
1175
1176 spin_unlock_irqrestore(&ep->udc->lock, flags);
1177 return status;
1178}
1179
1180static struct usb_ep_ops omap_ep_ops = {
1181 .enable = omap_ep_enable,
1182 .disable = omap_ep_disable,
1183
1184 .alloc_request = omap_alloc_request,
1185 .free_request = omap_free_request,
1186
1da177e4
LT		 1187 .queue = omap_ep_queue,
1188 .dequeue = omap_ep_dequeue,
1189
1190 .set_halt = omap_ep_set_halt,
1191 // fifo_status ... report bytes in fifo
1192 // fifo_flush ... flush fifo
1193};
1194
1195/*-------------------------------------------------------------------------*/
1196
1197static int omap_get_frame(struct usb_gadget *gadget)
1198{
f35ae634 1199 u16 sof = omap_readw(UDC_SOF);
1da177e4
LT		 1200 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1201}
1202
1203static int omap_wakeup(struct usb_gadget *gadget)
1204{
1205 struct omap_udc *udc;
1206 unsigned long flags;
1207 int retval = -EHOSTUNREACH;
1208
1209 udc = container_of(gadget, struct omap_udc, gadget);
1210
1211 spin_lock_irqsave(&udc->lock, flags);
1212 if (udc->devstat & UDC_SUS) {
1213 /* NOTE: OTG spec erratum says that OTG devices may
1214 * issue wakeups without host enable.
1215 */
1216 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1217 DBG("remote wakeup...\n");
f35ae634 1218 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1da177e4
LT		 1219 retval = 0;
1220 }
1221
1222 /* NOTE: non-OTG systems may use SRP TOO... */
1223 } else if (!(udc->devstat & UDC_ATT)) {
1224 if (udc->transceiver)
1225 retval = otg_start_srp(udc->transceiver);
1226 }
1227 spin_unlock_irqrestore(&udc->lock, flags);
1228
1229 return retval;
1230}
1231
1232static int
1233omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1234{
1235 struct omap_udc *udc;
1236 unsigned long flags;
1237 u16 syscon1;
1238
1239 udc = container_of(gadget, struct omap_udc, gadget);
1240 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1241 syscon1 = omap_readw(UDC_SYSCON1);
1da177e4
LT		 1242 if (is_selfpowered)
1243 syscon1 |= UDC_SELF_PWR;
1244 else
1245 syscon1 &= ~UDC_SELF_PWR;
f35ae634 1246 omap_writew(syscon1, UDC_SYSCON1);
1da177e4
LT		 1247 spin_unlock_irqrestore(&udc->lock, flags);
1248
1249 return 0;
1250}
1251
1252static int can_pullup(struct omap_udc *udc)
1253{
1254 return udc->driver && udc->softconnect && udc->vbus_active;
1255}
1256
1257static void pullup_enable(struct omap_udc *udc)
1258{
f35ae634
TL		 1259 u16 w;
1260
1261 w = omap_readw(UDC_SYSCON1);
1262 w |= UDC_PULLUP_EN;
1263 omap_writew(w, UDC_SYSCON1);
1264 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1265 u32 l;
1266
1267 l = omap_readl(OTG_CTRL);
1268 l |= OTG_BSESSVLD;
1269 omap_writel(l, OTG_CTRL);
1270 }
1271 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1da177e4
LT		 1272}
1273
1274static void pullup_disable(struct omap_udc *udc)
1275{
f35ae634
TL		 1276 u16 w;
1277
1278 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1279 u32 l;
1280
1281 l = omap_readl(OTG_CTRL);
1282 l &= ~OTG_BSESSVLD;
1283 omap_writel(l, OTG_CTRL);
1284 }
1285 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1286 w = omap_readw(UDC_SYSCON1);
1287 w &= ~UDC_PULLUP_EN;
1288 omap_writew(w, UDC_SYSCON1);
1da177e4
LT		 1289}
1290
e6a6e472
DB		 1291static struct omap_udc *udc;
1292
1293static void omap_udc_enable_clock(int enable)
1294{
1295 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1296 return;
1297
1298 if (enable) {
1299 clk_enable(udc->dc_clk);
1300 clk_enable(udc->hhc_clk);
1301 udelay(100);
1302 } else {
1303 clk_disable(udc->hhc_clk);
1304 clk_disable(udc->dc_clk);
1305 }
1306}
1307
1da177e4
LT		 1308/*
1309 * Called by whatever detects VBUS sessions: external transceiver
1310 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1311 */
1312static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1313{
1314 struct omap_udc *udc;
1315 unsigned long flags;
f35ae634 1316 u32 l;
1da177e4
LT		 1317
1318 udc = container_of(gadget, struct omap_udc, gadget);
1319 spin_lock_irqsave(&udc->lock, flags);
1320 VDBG("VBUS %s\n", is_active ? "on" : "off");
1321 udc->vbus_active = (is_active != 0);
1322 if (cpu_is_omap15xx()) {
1323 /* "software" detect, ignored if !VBUS_MODE_1510 */
f35ae634 1324 l = omap_readl(FUNC_MUX_CTRL_0);
1da177e4 1325 if (is_active)
f35ae634 1326 l |= VBUS_CTRL_1510;
1da177e4 1327 else
f35ae634
TL		 1328 l &= ~VBUS_CTRL_1510;
1329 omap_writel(l, FUNC_MUX_CTRL_0);
1da177e4 1330 }
e6a6e472
DB		 1331 if (udc->dc_clk != NULL && is_active) {
1332 if (!udc->clk_requested) {
1333 omap_udc_enable_clock(1);
1334 udc->clk_requested = 1;
1335 }
1336 }
1da177e4
LT		 1337 if (can_pullup(udc))
1338 pullup_enable(udc);
1339 else
1340 pullup_disable(udc);
e6a6e472
DB		 1341 if (udc->dc_clk != NULL && !is_active) {
1342 if (udc->clk_requested) {
1343 omap_udc_enable_clock(0);
1344 udc->clk_requested = 0;
1345 }
1346 }
1da177e4
LT		 1347 spin_unlock_irqrestore(&udc->lock, flags);
1348 return 0;
1349}
1350
1351static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1352{
1353 struct omap_udc *udc;
1354
1355 udc = container_of(gadget, struct omap_udc, gadget);
1356 if (udc->transceiver)
1357 return otg_set_power(udc->transceiver, mA);
1358 return -EOPNOTSUPP;
1359}
1360
1361static int omap_pullup(struct usb_gadget *gadget, int is_on)
1362{
1363 struct omap_udc *udc;
1364 unsigned long flags;
1365
1366 udc = container_of(gadget, struct omap_udc, gadget);
1367 spin_lock_irqsave(&udc->lock, flags);
1368 udc->softconnect = (is_on != 0);
1369 if (can_pullup(udc))
1370 pullup_enable(udc);
1371 else
1372 pullup_disable(udc);
1373 spin_unlock_irqrestore(&udc->lock, flags);
1374 return 0;
1375}
1376
0f91349b
SAS		 1377static int omap_udc_start(struct usb_gadget_driver *driver,
1378 int (*bind)(struct usb_gadget *));
1379static int omap_udc_stop(struct usb_gadget_driver *driver);
1380
1da177e4
LT		 1381static struct usb_gadget_ops omap_gadget_ops = {
1382 .get_frame = omap_get_frame,
1383 .wakeup = omap_wakeup,
1384 .set_selfpowered = omap_set_selfpowered,
1385 .vbus_session = omap_vbus_session,
1386 .vbus_draw = omap_vbus_draw,
1387 .pullup = omap_pullup,
0f91349b
SAS		 1388 .start = omap_udc_start,
1389 .stop = omap_udc_stop,
1da177e4
LT		 1390};
1391
1392/*-------------------------------------------------------------------------*/
1393
1394/* dequeue ALL requests; caller holds udc->lock */
1395static void nuke(struct omap_ep *ep, int status)
1396{
1397 struct omap_req *req;
1398
1399 ep->stopped = 1;
1400
1401 if (use_dma && ep->dma_channel)
1402 dma_channel_release(ep);
1403
1404 use_ep(ep, 0);
f35ae634 1405 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4 1406 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
f35ae634 1407 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1408
1409 while (!list_empty(&ep->queue)) {
1410 req = list_entry(ep->queue.next, struct omap_req, queue);
1411 done(ep, req, status);
1412 }
1413}
1414
1415/* caller holds udc->lock */
1416static void udc_quiesce(struct omap_udc *udc)
1417{
1418 struct omap_ep *ep;
1419
1420 udc->gadget.speed = USB_SPEED_UNKNOWN;
1421 nuke(&udc->ep[0], -ESHUTDOWN);
1422 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1423 nuke(ep, -ESHUTDOWN);
1424}
1425
1426/*-------------------------------------------------------------------------*/
1427
1428static void update_otg(struct omap_udc *udc)
1429{
1430 u16 devstat;
1431
9cfbba73 1432 if (!gadget_is_otg(&udc->gadget))
1da177e4
LT		 1433 return;
1434
f35ae634
TL		 1435 if (omap_readl(OTG_CTRL) & OTG_ID)
1436 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1437 else
1438 devstat = 0;
1439
1440 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1441 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1442 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1443
1444 /* Enable HNP early, avoiding races on suspend irq path.
1445 * ASSUMES OTG state machine B_BUS_REQ input is true.
1446 */
f35ae634
TL		 1447 if (udc->gadget.b_hnp_enable) {
1448 u32 l;
1449
1450 l = omap_readl(OTG_CTRL);
1451 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1452 l &= ~OTG_PULLUP;
1453 omap_writel(l, OTG_CTRL);
1454 }
1da177e4
LT		 1455}
1456
1457static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1458{
1459 struct omap_ep *ep0 = &udc->ep[0];
313980c9 1460 struct omap_req *req = NULL;
1da177e4
LT		 1461
1462 ep0->irqs++;
1463
1464 /* Clear any pending requests and then scrub any rx/tx state
1465 * before starting to handle the SETUP request.
1466 */
1467 if (irq_src & UDC_SETUP) {
1468 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1469
1470 nuke(ep0, 0);
1471 if (ack) {
f35ae634 1472 omap_writew(ack, UDC_IRQ_SRC);
1da177e4
LT		 1473 irq_src = UDC_SETUP;
1474 }
1475 }
1476
e6a6e472 1477 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1da177e4
LT		 1478 * This driver uses only uses protocol stalls (ep0 never halts),
1479 * and if we got this far the gadget driver already had a
1480 * chance to stall. Tries to be forgiving of host oddities.
1481 *
1482 * NOTE: the last chance gadget drivers have to stall control
1483 * requests is during their request completion callback.
1484 */
1485 if (!list_empty(&ep0->queue))
1486 req = container_of(ep0->queue.next, struct omap_req, queue);
1487
1488 /* IN == TX to host */
1489 if (irq_src & UDC_EP0_TX) {
1490 int stat;
1491
f35ae634
TL		 1492 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1493 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1494 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1495 if (stat & UDC_ACK) {
1496 if (udc->ep0_in) {
1497 /* write next IN packet from response,
1498 * or set up the status stage.
1499 */
1500 if (req)
1501 stat = write_fifo(ep0, req);
f35ae634 1502 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1503 if (!req && udc->ep0_pending) {
f35ae634
TL		 1504 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1505 omap_writew(UDC_CLR_EP, UDC_CTRL);
1506 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1507 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1508 udc->ep0_pending = 0;
1509 } /* else: 6 wait states before it'll tx */
1510 } else {
1511 /* ack status stage of OUT transfer */
f35ae634 1512 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1513 if (req)
1514 done(ep0, req, 0);
1515 }
313980c9 1516 req = NULL;
1da177e4 1517 } else if (stat & UDC_STALL) {
f35ae634
TL		 1518 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1519 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1520 } else {
f35ae634 1521 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1522 }
1523 }
1524
1525 /* OUT == RX from host */
1526 if (irq_src & UDC_EP0_RX) {
1527 int stat;
1528
f35ae634
TL		 1529 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1530 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1531 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1532 if (stat & UDC_ACK) {
1533 if (!udc->ep0_in) {
1534 stat = 0;
1535 /* read next OUT packet of request, maybe
1536 * reactiviting the fifo; stall on errors.
1537 */
1538 if (!req || (stat = read_fifo(ep0, req)) < 0) {
f35ae634 1539 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1540 udc->ep0_pending = 0;
1541 stat = 0;
1542 } else if (stat == 0)
f35ae634
TL		 1543 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1544 omap_writew(0, UDC_EP_NUM);
e6a6e472 1545
1da177e4
LT		 1546 /* activate status stage */
1547 if (stat == 1) {
1548 done(ep0, req, 0);
1549 /* that may have STALLed ep0... */
f35ae634
TL		 1550 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1551 UDC_EP_NUM);
1552 omap_writew(UDC_CLR_EP, UDC_CTRL);
1553 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1554 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1555 udc->ep0_pending = 0;
1556 }
1557 } else {
1558 /* ack status stage of IN transfer */
f35ae634 1559 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1560 if (req)
1561 done(ep0, req, 0);
1562 }
1563 } else if (stat & UDC_STALL) {
f35ae634
TL		 1564 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1565 omap_writew(0, UDC_EP_NUM);
1da177e4 1566 } else {
f35ae634 1567 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1568 }
1569 }
1570
1571 /* SETUP starts all control transfers */
1572 if (irq_src & UDC_SETUP) {
1573 union u {
1574 u16 word[4];
1575 struct usb_ctrlrequest r;
1576 } u;
1577 int status = -EINVAL;
1578 struct omap_ep *ep;
1579
1580 /* read the (latest) SETUP message */
1581 do {
f35ae634 1582 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1da177e4 1583 /* two bytes at a time */
f35ae634
TL		 1584 u.word[0] = omap_readw(UDC_DATA);
1585 u.word[1] = omap_readw(UDC_DATA);
1586 u.word[2] = omap_readw(UDC_DATA);
1587 u.word[3] = omap_readw(UDC_DATA);
1588 omap_writew(0, UDC_EP_NUM);
1589 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1da177e4 1590
01ee7d70
DB		 1591#define w_value le16_to_cpu(u.r.wValue)
1592#define w_index le16_to_cpu(u.r.wIndex)
1593#define w_length le16_to_cpu(u.r.wLength)
65111084 1594
1da177e4
LT		 1595 /* Delegate almost all control requests to the gadget driver,
1596 * except for a handful of ch9 status/feature requests that
1597 * hardware doesn't autodecode _and_ the gadget API hides.
1598 */
1599 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1600 udc->ep0_set_config = 0;
1601 udc->ep0_pending = 1;
1602 ep0->stopped = 0;
1603 ep0->ackwait = 0;
1604 switch (u.r.bRequest) {
1605 case USB_REQ_SET_CONFIGURATION:
1606 /* udc needs to know when ep != 0 is valid */
1607 if (u.r.bRequestType != USB_RECIP_DEVICE)
1608 goto delegate;
65111084 1609 if (w_length != 0)
1da177e4
LT		 1610 goto do_stall;
1611 udc->ep0_set_config = 1;
65111084
DB		 1612 udc->ep0_reset_config = (w_value == 0);
1613 VDBG("set config %d\n", w_value);
1da177e4
LT		 1614
1615 /* update udc NOW since gadget driver may start
1616 * queueing requests immediately; clear config
1617 * later if it fails the request.
1618 */
1619 if (udc->ep0_reset_config)
f35ae634 1620 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1621 else
f35ae634 1622 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1da177e4
LT		 1623 update_otg(udc);
1624 goto delegate;
1625 case USB_REQ_CLEAR_FEATURE:
1626 /* clear endpoint halt */
1627 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1628 goto delegate;
65111084
DB		 1629 if (w_value != USB_ENDPOINT_HALT
1630 || w_length != 0)
1da177e4 1631 goto do_stall;
65111084 1632 ep = &udc->ep[w_index & 0xf];
1da177e4 1633 if (ep != ep0) {
65111084 1634 if (w_index & USB_DIR_IN)
1da177e4
LT		 1635 ep += 16;
1636 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1637 || !ep->desc)
1638 goto do_stall;
1639 use_ep(ep, 0);
f35ae634 1640 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1641 ep->ackwait = 0;
1642 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1643 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1644 ep->ackwait = 1 + ep->double_buf;
1645 }
313980c9
DB		 1646 /* NOTE: assumes the host behaves sanely,
1647 * only clearing real halts. Else we may
1648 * need to kill pending transfers and then
1649 * restart the queue... very messy for DMA!
1650 */
1da177e4
LT		 1651 }
1652 VDBG("%s halt cleared by host\n", ep->name);
1653 goto ep0out_status_stage;
1654 case USB_REQ_SET_FEATURE:
1655 /* set endpoint halt */
1656 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1657 goto delegate;
65111084
DB		 1658 if (w_value != USB_ENDPOINT_HALT
1659 || w_length != 0)
1da177e4 1660 goto do_stall;
65111084
DB		 1661 ep = &udc->ep[w_index & 0xf];
1662 if (w_index & USB_DIR_IN)
1da177e4
LT		 1663 ep += 16;
1664 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1665 || ep == ep0 || !ep->desc)
1666 goto do_stall;
1667 if (use_dma && ep->has_dma) {
1668 /* this has rude side-effects (aborts) and
1669 * can't really work if DMA-IN is active
1670 */
1671 DBG("%s host set_halt, NYET \n", ep->name);
1672 goto do_stall;
1673 }
1674 use_ep(ep, 0);
1675 /* can't halt if fifo isn't empty... */
f35ae634
TL		 1676 omap_writew(UDC_CLR_EP, UDC_CTRL);
1677 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1678 VDBG("%s halted by host\n", ep->name);
1679ep0out_status_stage:
1680 status = 0;
f35ae634
TL		 1681 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1682 omap_writew(UDC_CLR_EP, UDC_CTRL);
1683 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1684 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1685 udc->ep0_pending = 0;
1686 break;
1687 case USB_REQ_GET_STATUS:
8a3c1f57
DB		 1688 /* USB_ENDPOINT_HALT status? */
1689 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1690 goto intf_status;
1691
1692 /* ep0 never stalls */
1693 if (!(w_index & 0xf))
1694 goto zero_status;
1695
1696 /* only active endpoints count */
1697 ep = &udc->ep[w_index & 0xf];
1698 if (w_index & USB_DIR_IN)
1699 ep += 16;
1700 if (!ep->desc)
1701 goto do_stall;
1702
1703 /* iso never stalls */
1704 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1705 goto zero_status;
1706
1707 /* FIXME don't assume non-halted endpoints!! */
1708 ERR("%s status, can't report\n", ep->ep.name);
1709 goto do_stall;
1710
1711intf_status:
1da177e4
LT		 1712 /* return interface status. if we were pedantic,
1713 * we'd detect non-existent interfaces, and stall.
1714 */
1715 if (u.r.bRequestType
1716 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1717 goto delegate;
8a3c1f57
DB		 1718
1719zero_status:
1da177e4 1720 /* return two zero bytes */
f35ae634
TL		 1721 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1722 omap_writew(0, UDC_DATA);
1723 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1724 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1725 status = 0;
65111084 1726 VDBG("GET_STATUS, interface %d\n", w_index);
1da177e4
LT		 1727 /* next, status stage */
1728 break;
1729 default:
1730delegate:
1731 /* activate the ep0out fifo right away */
65111084 1732 if (!udc->ep0_in && w_length) {
f35ae634
TL		 1733 omap_writew(0, UDC_EP_NUM);
1734 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1735 }
1736
1737 /* gadget drivers see class/vendor specific requests,
1738 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1739 * and more
1740 */
1741 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1742 u.r.bRequestType, u.r.bRequest,
65111084
DB		 1743 w_value, w_index, w_length);
1744
1745#undef w_value
1746#undef w_index
1747#undef w_length
1da177e4
LT		 1748
1749 /* The gadget driver may return an error here,
1750 * causing an immediate protocol stall.
1751 *
1752 * Else it must issue a response, either queueing a
1753 * response buffer for the DATA stage, or halting ep0
1754 * (causing a protocol stall, not a real halt). A
1755 * zero length buffer means no DATA stage.
1756 *
1757 * It's fine to issue that response after the setup()
1758 * call returns, and this IRQ was handled.
1759 */
1760 udc->ep0_setup = 1;
1761 spin_unlock(&udc->lock);
1762 status = udc->driver->setup (&udc->gadget, &u.r);
1763 spin_lock(&udc->lock);
1764 udc->ep0_setup = 0;
1765 }
1766
1767 if (status < 0) {
1768do_stall:
1769 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1770 u.r.bRequestType, u.r.bRequest, status);
1771 if (udc->ep0_set_config) {
1772 if (udc->ep0_reset_config)
b6c63937 1773 WARNING("error resetting config?\n");
1da177e4 1774 else
f35ae634 1775 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1776 }
f35ae634 1777 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1778 udc->ep0_pending = 0;
1779 }
1780 }
1781}
1782
1783/*-------------------------------------------------------------------------*/
1784
1785#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1786
1787static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1788{
1789 u16 devstat, change;
1790
f35ae634 1791 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1792 change = devstat ^ udc->devstat;
1793 udc->devstat = devstat;
1794
1795 if (change & (UDC_USB_RESET|UDC_ATT)) {
1796 udc_quiesce(udc);
1797
1798 if (change & UDC_ATT) {
1799 /* driver for any external transceiver will
1800 * have called omap_vbus_session() already
1801 */
1802 if (devstat & UDC_ATT) {
1803 udc->gadget.speed = USB_SPEED_FULL;
1804 VDBG("connect\n");
1805 if (!udc->transceiver)
1806 pullup_enable(udc);
1807 // if (driver->connect) call it
1808 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1809 udc->gadget.speed = USB_SPEED_UNKNOWN;
1810 if (!udc->transceiver)
1811 pullup_disable(udc);
1812 DBG("disconnect, gadget %s\n",
1813 udc->driver->driver.name);
1814 if (udc->driver->disconnect) {
1815 spin_unlock(&udc->lock);
1816 udc->driver->disconnect(&udc->gadget);
1817 spin_lock(&udc->lock);
1818 }
1819 }
1820 change &= ~UDC_ATT;
1821 }
1822
1823 if (change & UDC_USB_RESET) {
1824 if (devstat & UDC_USB_RESET) {
1825 VDBG("RESET=1\n");
1826 } else {
1827 udc->gadget.speed = USB_SPEED_FULL;
1828 INFO("USB reset done, gadget %s\n",
1829 udc->driver->driver.name);
1830 /* ep0 traffic is legal from now on */
f35ae634
TL		 1831 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1832 UDC_IRQ_EN);
1da177e4
LT		 1833 }
1834 change &= ~UDC_USB_RESET;
1835 }
1836 }
1837 if (change & UDC_SUS) {
1838 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1839 // FIXME tell isp1301 to suspend/resume (?)
1840 if (devstat & UDC_SUS) {
1841 VDBG("suspend\n");
1842 update_otg(udc);
1843 /* HNP could be under way already */
1844 if (udc->gadget.speed == USB_SPEED_FULL
1845 && udc->driver->suspend) {
1846 spin_unlock(&udc->lock);
1847 udc->driver->suspend(&udc->gadget);
1848 spin_lock(&udc->lock);
1849 }
4e67185a
JY		 1850 if (udc->transceiver)
1851 otg_set_suspend(udc->transceiver, 1);
1da177e4
LT		 1852 } else {
1853 VDBG("resume\n");
4e67185a
JY		 1854 if (udc->transceiver)
1855 otg_set_suspend(udc->transceiver, 0);
1da177e4
LT		 1856 if (udc->gadget.speed == USB_SPEED_FULL
1857 && udc->driver->resume) {
1858 spin_unlock(&udc->lock);
1859 udc->driver->resume(&udc->gadget);
1860 spin_lock(&udc->lock);
1861 }
1862 }
1863 }
1864 change &= ~UDC_SUS;
1865 }
1866 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1867 update_otg(udc);
1868 change &= ~OTG_FLAGS;
1869 }
1870
1871 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1872 if (change)
1873 VDBG("devstat %03x, ignore change %03x\n",
1874 devstat, change);
1875
f35ae634 1876 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1da177e4
LT		 1877}
1878
7d12e780 1879static irqreturn_t omap_udc_irq(int irq, void *_udc)
1da177e4
LT		 1880{
1881 struct omap_udc *udc = _udc;
1882 u16 irq_src;
1883 irqreturn_t status = IRQ_NONE;
1884 unsigned long flags;
1885
1886 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1887 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1888
1889 /* Device state change (usb ch9 stuff) */
1890 if (irq_src & UDC_DS_CHG) {
1891 devstate_irq(_udc, irq_src);
1892 status = IRQ_HANDLED;
1893 irq_src &= ~UDC_DS_CHG;
1894 }
1895
1896 /* EP0 control transfers */
1897 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1898 ep0_irq(_udc, irq_src);
1899 status = IRQ_HANDLED;
1900 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1901 }
1902
1903 /* DMA transfer completion */
1904 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1905 dma_irq(_udc, irq_src);
1906 status = IRQ_HANDLED;
1907 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1908 }
1909
f35ae634 1910 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1da177e4
LT		 1911 if (irq_src)
1912 DBG("udc_irq, unhandled %03x\n", irq_src);
1913 spin_unlock_irqrestore(&udc->lock, flags);
1914
1915 return status;
1916}
1917
1918/* workaround for seemingly-lost IRQs for RX ACKs... */
1919#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1920#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1921
1922static void pio_out_timer(unsigned long _ep)
1923{
1924 struct omap_ep *ep = (void *) _ep;
1925 unsigned long flags;
1926 u16 stat_flg;
1927
1928 spin_lock_irqsave(&ep->udc->lock, flags);
1929 if (!list_empty(&ep->queue) && ep->ackwait) {
e6a6e472 1930 use_ep(ep, UDC_EP_SEL);
f35ae634 1931 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1932
1933 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1934 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1935 struct omap_req *req;
1936
1937 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1938 req = container_of(ep->queue.next,
1939 struct omap_req, queue);
1da177e4 1940 (void) read_fifo(ep, req);
f35ae634
TL		 1941 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1942 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4 1943 ep->ackwait = 1 + ep->double_buf;
e6a6e472
DB		 1944 } else
1945 deselect_ep();
1da177e4
LT		 1946 }
1947 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1948 spin_unlock_irqrestore(&ep->udc->lock, flags);
1949}
1950
7d12e780 1951static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1da177e4
LT		 1952{
1953 u16 epn_stat, irq_src;
1954 irqreturn_t status = IRQ_NONE;
1955 struct omap_ep *ep;
1956 int epnum;
1957 struct omap_udc *udc = _dev;
1958 struct omap_req *req;
1959 unsigned long flags;
1960
1961 spin_lock_irqsave(&udc->lock, flags);
f35ae634
TL		 1962 epn_stat = omap_readw(UDC_EPN_STAT);
1963 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1964
1965 /* handle OUT first, to avoid some wasteful NAKs */
1966 if (irq_src & UDC_EPN_RX) {
1967 epnum = (epn_stat >> 8) & 0x0f;
f35ae634 1968 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1da177e4
LT		 1969 status = IRQ_HANDLED;
1970 ep = &udc->ep[epnum];
1971 ep->irqs++;
1972
f35ae634 1973 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1da177e4 1974 ep->fnf = 0;
f35ae634 1975 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 1976 ep->ackwait--;
1977 if (!list_empty(&ep->queue)) {
1978 int stat;
1979 req = container_of(ep->queue.next,
1980 struct omap_req, queue);
1981 stat = read_fifo(ep, req);
1982 if (!ep->double_buf)
1983 ep->fnf = 1;
1984 }
1985 }
1986 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 1987 epn_stat = omap_readw(UDC_EPN_STAT);
1988 epn_stat = omap_readw(UDC_EPN_STAT);
1989 omap_writew(epnum, UDC_EP_NUM);
1da177e4
LT		 1990
1991 /* enabling fifo _after_ clearing ACK, contrary to docs,
1992 * reduces lossage; timer still needed though (sigh).
1993 */
1994 if (ep->fnf) {
f35ae634 1995 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1996 ep->ackwait = 1 + ep->double_buf;
1997 }
1998 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1999 }
2000
2001 /* then IN transfers */
2002 else if (irq_src & UDC_EPN_TX) {
2003 epnum = epn_stat & 0x0f;
f35ae634 2004 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1da177e4
LT		 2005 status = IRQ_HANDLED;
2006 ep = &udc->ep[16 + epnum];
2007 ep->irqs++;
2008
f35ae634
TL		 2009 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2010 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 2011 ep->ackwait = 0;
2012 if (!list_empty(&ep->queue)) {
2013 req = container_of(ep->queue.next,
2014 struct omap_req, queue);
2015 (void) write_fifo(ep, req);
2016 }
2017 }
2018 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 2019 epn_stat = omap_readw(UDC_EPN_STAT);
2020 epn_stat = omap_readw(UDC_EPN_STAT);
2021 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 2022 /* then 6 clocks before it'd tx */
2023 }
2024
2025 spin_unlock_irqrestore(&udc->lock, flags);
2026 return status;
2027}
2028
2029#ifdef USE_ISO
7d12e780 2030static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1da177e4
LT		 2031{
2032 struct omap_udc *udc = _dev;
2033 struct omap_ep *ep;
2034 int pending = 0;
2035 unsigned long flags;
2036
2037 spin_lock_irqsave(&udc->lock, flags);
2038
2039 /* handle all non-DMA ISO transfers */
2040 list_for_each_entry (ep, &udc->iso, iso) {
2041 u16 stat;
2042 struct omap_req *req;
2043
2044 if (ep->has_dma || list_empty(&ep->queue))
2045 continue;
2046 req = list_entry(ep->queue.next, struct omap_req, queue);
2047
2048 use_ep(ep, UDC_EP_SEL);
f35ae634 2049 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2050
2051 /* NOTE: like the other controller drivers, this isn't
2052 * currently reporting lost or damaged frames.
2053 */
2054 if (ep->bEndpointAddress & USB_DIR_IN) {
2055 if (stat & UDC_MISS_IN)
2056 /* done(ep, req, -EPROTO) */;
2057 else
2058 write_fifo(ep, req);
2059 } else {
2060 int status = 0;
2061
2062 if (stat & UDC_NO_RXPACKET)
2063 status = -EREMOTEIO;
2064 else if (stat & UDC_ISO_ERR)
2065 status = -EILSEQ;
2066 else if (stat & UDC_DATA_FLUSH)
2067 status = -ENOSR;
2068
2069 if (status)
2070 /* done(ep, req, status) */;
2071 else
2072 read_fifo(ep, req);
2073 }
2074 deselect_ep();
2075 /* 6 wait states before next EP */
2076
2077 ep->irqs++;
2078 if (!list_empty(&ep->queue))
2079 pending = 1;
2080 }
f35ae634
TL		 2081 if (!pending) {
2082 u16 w;
2083
2084 w = omap_readw(UDC_IRQ_EN);
2085 w &= ~UDC_SOF_IE;
2086 omap_writew(w, UDC_IRQ_EN);
2087 }
2088 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
1da177e4
LT		 2089
2090 spin_unlock_irqrestore(&udc->lock, flags);
2091 return IRQ_HANDLED;
2092}
2093#endif
2094
2095/*-------------------------------------------------------------------------*/
2096
8a3c1f57 2097static inline int machine_without_vbus_sense(void)
e6a6e472
DB		 2098{
2099 return (machine_is_omap_innovator()
2100 || machine_is_omap_osk()
2101 || machine_is_omap_apollon()
2102#ifndef CONFIG_MACH_OMAP_H4_OTG
2103 || machine_is_omap_h4()
2104#endif
2105 || machine_is_sx1()
45f780a0 2106 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
e6a6e472
DB		 2107 );
2108}
1da177e4 2109
0f91349b 2110static int omap_udc_start(struct usb_gadget_driver *driver,
b0fca50f 2111 int (*bind)(struct usb_gadget *))
1da177e4
LT		 2112{
2113 int status = -ENODEV;
2114 struct omap_ep *ep;
2115 unsigned long flags;
2116
2117 /* basic sanity tests */
2118 if (!udc)
2119 return -ENODEV;
2120 if (!driver
2121 // FIXME if otg, check: driver->is_otg
2122 || driver->speed < USB_SPEED_FULL
b0fca50f 2123 || !bind || !driver->setup)
1da177e4
LT		 2124 return -EINVAL;
2125
2126 spin_lock_irqsave(&udc->lock, flags);
2127 if (udc->driver) {
2128 spin_unlock_irqrestore(&udc->lock, flags);
2129 return -EBUSY;
2130 }
2131
2132 /* reset state */
2133 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2134 ep->irqs = 0;
2135 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2136 continue;
2137 use_ep(ep, 0);
f35ae634 2138 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 2139 }
2140 udc->ep0_pending = 0;
2141 udc->ep[0].irqs = 0;
2142 udc->softconnect = 1;
2143
2144 /* hook up the driver */
313980c9 2145 driver->driver.bus = NULL;
1da177e4
LT		 2146 udc->driver = driver;
2147 udc->gadget.dev.driver = &driver->driver;
2148 spin_unlock_irqrestore(&udc->lock, flags);
2149
e6a6e472
DB		 2150 if (udc->dc_clk != NULL)
2151 omap_udc_enable_clock(1);
2152
b0fca50f 2153 status = bind(&udc->gadget);
1da177e4
LT		 2154 if (status) {
2155 DBG("bind to %s --> %d\n", driver->driver.name, status);
313980c9
DB		 2156 udc->gadget.dev.driver = NULL;
2157 udc->driver = NULL;
1da177e4
LT		 2158 goto done;
2159 }
2160 DBG("bound to driver %s\n", driver->driver.name);
2161
f35ae634 2162 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
1da177e4
LT		 2163
2164 /* connect to bus through transceiver */
2165 if (udc->transceiver) {
2166 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2167 if (status < 0) {
2168 ERR("can't bind to transceiver\n");
6bea476c
DB		 2169 if (driver->unbind) {
2170 driver->unbind (&udc->gadget);
2171 udc->gadget.dev.driver = NULL;
2172 udc->driver = NULL;
2173 }
1da177e4
LT		 2174 goto done;
2175 }
2176 } else {
2177 if (can_pullup(udc))
2178 pullup_enable (udc);
2179 else
2180 pullup_disable (udc);
2181 }
2182
2183 /* boards that don't have VBUS sensing can't autogate 48MHz;
2184 * can't enter deep sleep while a gadget driver is active.
2185 */
8a3c1f57 2186 if (machine_without_vbus_sense())
1da177e4
LT		 2187 omap_vbus_session(&udc->gadget, 1);
2188
2189done:
e6a6e472
DB		 2190 if (udc->dc_clk != NULL)
2191 omap_udc_enable_clock(0);
1da177e4
LT		 2192 return status;
2193}
1da177e4 2194
0f91349b 2195static int omap_udc_stop(struct usb_gadget_driver *driver)
1da177e4
LT		 2196{
2197 unsigned long flags;
2198 int status = -ENODEV;
2199
2200 if (!udc)
2201 return -ENODEV;
6bea476c 2202 if (!driver || driver != udc->driver || !driver->unbind)
1da177e4
LT		 2203 return -EINVAL;
2204
e6a6e472
DB		 2205 if (udc->dc_clk != NULL)
2206 omap_udc_enable_clock(1);
2207
8a3c1f57 2208 if (machine_without_vbus_sense())
1da177e4
LT		 2209 omap_vbus_session(&udc->gadget, 0);
2210
2211 if (udc->transceiver)
313980c9 2212 (void) otg_set_peripheral(udc->transceiver, NULL);
1da177e4
LT		 2213 else
2214 pullup_disable(udc);
2215
2216 spin_lock_irqsave(&udc->lock, flags);
2217 udc_quiesce(udc);
2218 spin_unlock_irqrestore(&udc->lock, flags);
2219
2220 driver->unbind(&udc->gadget);
313980c9
DB		 2221 udc->gadget.dev.driver = NULL;
2222 udc->driver = NULL;
1da177e4 2223
e6a6e472
DB		 2224 if (udc->dc_clk != NULL)
2225 omap_udc_enable_clock(0);
1da177e4
LT		 2226 DBG("unregistered driver '%s'\n", driver->driver.name);
2227 return status;
2228}
1da177e4
LT		 2229
2230/*-------------------------------------------------------------------------*/
2231
2232#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2233
2234#include <linux/seq_file.h>
2235
2236static const char proc_filename[] = "driver/udc";
2237
2238#define FOURBITS "%s%s%s%s"
2239#define EIGHTBITS FOURBITS FOURBITS
2240
2241static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2242{
2243 u16 stat_flg;
2244 struct omap_req *req;
2245 char buf[20];
2246
2247 use_ep(ep, 0);
2248
2249 if (use_dma && ep->has_dma)
2250 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2251 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2252 ep->dma_channel - 1, ep->lch);
2253 else
2254 buf[0] = 0;
2255
f35ae634 2256 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2257 seq_printf(s,
2258 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2259 ep->name, buf,
2260 ep->double_buf ? "dbuf " : "",
2261 ({char *s; switch(ep->ackwait){
2262 case 0: s = ""; break;
2263 case 1: s = "(ackw) "; break;
2264 case 2: s = "(ackw2) "; break;
2265 default: s = "(?) "; break;
2266 } s;}),
2267 ep->irqs, stat_flg,
2268 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2269 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2270 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2271 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2272 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2273 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2274 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2275 (stat_flg & UDC_STALL) ? "STALL " : "",
2276 (stat_flg & UDC_NAK) ? "NAK " : "",
2277 (stat_flg & UDC_ACK) ? "ACK " : "",
2278 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2279 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2280 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2281
2282 if (list_empty (&ep->queue))
2283 seq_printf(s, "\t(queue empty)\n");
2284 else
2285 list_for_each_entry (req, &ep->queue, queue) {
2286 unsigned length = req->req.actual;
2287
2288 if (use_dma && buf[0]) {
2289 length += ((ep->bEndpointAddress & USB_DIR_IN)
2290 ? dma_src_len : dma_dest_len)
2291 (ep, req->req.dma + length);
2292 buf[0] = 0;
2293 }
2294 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2295 &req->req, length,
2296 req->req.length, req->req.buf);
2297 }
2298}
2299
2300static char *trx_mode(unsigned m, int enabled)
2301{
2302 switch (m) {
2303 case 0: return enabled ? "*6wire" : "unused";
2304 case 1: return "4wire";
2305 case 2: return "3wire";
e6a6e472 2306 case 3: return "6wire";
1da177e4
LT		 2307 default: return "unknown";
2308 }
2309}
2310
2311static int proc_otg_show(struct seq_file *s)
2312{
2313 u32 tmp;
4814ced5
PW		 2314 u32 trans = 0;
2315 char *ctrl_name = "(UNKNOWN)";
1da177e4 2316
4814ced5 2317 /* XXX This needs major revision for OMAP2+ */
e12cc345 2318 tmp = omap_readl(OTG_REV);
4814ced5 2319 if (cpu_class_is_omap1()) {
e6a6e472 2320 ctrl_name = "tranceiver_ctrl";
f35ae634 2321 trans = omap_readw(USB_TRANSCEIVER_CTRL);
e6a6e472
DB		 2322 }
2323 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2324 tmp >> 4, tmp & 0xf, ctrl_name, trans);
f35ae634 2325 tmp = omap_readw(OTG_SYSCON_1);
1da177e4
LT		 2326 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2327 FOURBITS "\n", tmp,
2328 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2329 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
65111084 2330 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
1da177e4
LT		 2331 ? "internal"
2332 : trx_mode(USB0_TRX_MODE(tmp), 1),
2333 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2334 (tmp & HST_IDLE_EN) ? " !host" : "",
2335 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2336 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
f35ae634 2337 tmp = omap_readl(OTG_SYSCON_2);
1da177e4
LT		 2338 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2339 " b_ase_brst=%d hmc=%d\n", tmp,
2340 (tmp & OTG_EN) ? " otg_en" : "",
2341 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2342 // much more SRP stuff
2343 (tmp & SRP_DATA) ? " srp_data" : "",
2344 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2345 (tmp & OTG_PADEN) ? " otg_paden" : "",
2346 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2347 (tmp & UHOST_EN) ? " uhost_en" : "",
2348 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2349 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2350 B_ASE_BRST(tmp),
2351 OTG_HMC(tmp));
f35ae634 2352 tmp = omap_readl(OTG_CTRL);
1da177e4
LT		 2353 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2354 (tmp & OTG_ASESSVLD) ? " asess" : "",
2355 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2356 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2357 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2358 (tmp & OTG_ID) ? " id" : "",
2359 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2360 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2361 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2362 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2363 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2364 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2365 (tmp & OTG_PULLDOWN) ? " down" : "",
2366 (tmp & OTG_PULLUP) ? " up" : "",
2367 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2368 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2369 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2370 (tmp & OTG_PU_ID) ? " pu_id" : ""
2371 );
f35ae634 2372 tmp = omap_readw(OTG_IRQ_EN);
1da177e4 2373 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
f35ae634 2374 tmp = omap_readw(OTG_IRQ_SRC);
1da177e4 2375 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
f35ae634 2376 tmp = omap_readw(OTG_OUTCTRL);
1da177e4 2377 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
f35ae634 2378 tmp = omap_readw(OTG_TEST);
1da177e4 2379 seq_printf(s, "otg_test %04x" "\n", tmp);
313980c9 2380 return 0;
1da177e4
LT		 2381}
2382
2383static int proc_udc_show(struct seq_file *s, void *_)
2384{
2385 u32 tmp;
2386 struct omap_ep *ep;
2387 unsigned long flags;
2388
2389 spin_lock_irqsave(&udc->lock, flags);
2390
2391 seq_printf(s, "%s, version: " DRIVER_VERSION
2392#ifdef USE_ISO
2393 " (iso)"
2394#endif
2395 "%s\n",
2396 driver_desc,
2397 use_dma ? " (dma)" : "");
2398
f35ae634 2399 tmp = omap_readw(UDC_REV) & 0xff;
1da177e4
LT		 2400 seq_printf(s,
2401 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2402 "hmc %d, transceiver %s\n",
2403 tmp >> 4, tmp & 0xf,
2404 fifo_mode,
2405 udc->driver ? udc->driver->driver.name : "(none)",
2406 HMC,
e6a6e472
DB		 2407 udc->transceiver
2408 ? udc->transceiver->label
2409 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2410 ? "external" : "(none)"));
2411 if (cpu_class_is_omap1()) {
2412 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
f35ae634
TL		 2413 omap_readw(ULPD_CLOCK_CTRL),
2414 omap_readw(ULPD_SOFT_REQ),
2415 omap_readw(ULPD_STATUS_REQ));
e6a6e472 2416 }
1da177e4
LT		 2417
2418 /* OTG controller registers */
2419 if (!cpu_is_omap15xx())
2420 proc_otg_show(s);
2421
f35ae634 2422 tmp = omap_readw(UDC_SYSCON1);
1da177e4
LT		 2423 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2424 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2425 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2426 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2427 (tmp & UDC_NAK_EN) ? " nak" : "",
2428 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2429 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2430 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2431 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2432 // syscon2 is write-only
2433
2434 /* UDC controller registers */
2435 if (!(tmp & UDC_PULLUP_EN)) {
2436 seq_printf(s, "(suspended)\n");
2437 spin_unlock_irqrestore(&udc->lock, flags);
2438 return 0;
2439 }
2440
f35ae634 2441 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2442 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2443 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2444 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2445 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2446 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2447 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2448 (tmp & UDC_SUS) ? " SUS" : "",
2449 (tmp & UDC_CFG) ? " CFG" : "",
2450 (tmp & UDC_ADD) ? " ADD" : "",
2451 (tmp & UDC_DEF) ? " DEF" : "",
2452 (tmp & UDC_ATT) ? " ATT" : "");
f35ae634
TL		 2453 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2454 tmp = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 2455 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2456 (tmp & UDC_SOF_IE) ? " sof" : "",
2457 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2458 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2459 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2460 (tmp & UDC_EP0_IE) ? " ep0" : "");
f35ae634 2461 tmp = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 2462 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2463 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2464 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2465 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
f35ae634 2466 (tmp & UDC_IRQ_SOF) ? " sof" : "",
1da177e4
LT		 2467 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2468 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2469 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2470 (tmp & UDC_SETUP) ? " setup" : "",
2471 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2472 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2473 if (use_dma) {
2474 unsigned i;
2475
f35ae634 2476 tmp = omap_readw(UDC_DMA_IRQ_EN);
1da177e4
LT		 2477 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2478 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2479 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2480 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2481
2482 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2483 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2484 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2485
2486 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2487 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2488 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2489
f35ae634 2490 tmp = omap_readw(UDC_RXDMA_CFG);
1da177e4
LT		 2491 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2492 if (tmp) {
2493 for (i = 0; i < 3; i++) {
2494 if ((tmp & (0x0f << (i * 4))) == 0)
2495 continue;
2496 seq_printf(s, "rxdma[%d] %04x\n", i,
f35ae634 2497 omap_readw(UDC_RXDMA(i + 1)));
1da177e4
LT		 2498 }
2499 }
f35ae634 2500 tmp = omap_readw(UDC_TXDMA_CFG);
1da177e4
LT		 2501 seq_printf(s, "txdma_cfg %04x\n", tmp);
2502 if (tmp) {
2503 for (i = 0; i < 3; i++) {
2504 if (!(tmp & (0x0f << (i * 4))))
2505 continue;
2506 seq_printf(s, "txdma[%d] %04x\n", i,
f35ae634 2507 omap_readw(UDC_TXDMA(i + 1)));
1da177e4
LT		 2508 }
2509 }
2510 }
2511
f35ae634 2512 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2513 if (tmp & UDC_ATT) {
2514 proc_ep_show(s, &udc->ep[0]);
2515 if (tmp & UDC_ADD) {
2516 list_for_each_entry (ep, &udc->gadget.ep_list,
2517 ep.ep_list) {
2518 if (ep->desc)
2519 proc_ep_show(s, ep);
2520 }
2521 }
2522 }
2523 spin_unlock_irqrestore(&udc->lock, flags);
2524 return 0;
2525}
2526
2527static int proc_udc_open(struct inode *inode, struct file *file)
2528{
313980c9 2529 return single_open(file, proc_udc_show, NULL);
1da177e4
LT		 2530}
2531
066202dd 2532static const struct file_operations proc_ops = {
cdefa185 2533 .owner = THIS_MODULE,
1da177e4
LT		 2534 .open = proc_udc_open,
2535 .read = seq_read,
2536 .llseek = seq_lseek,
2537 .release = single_release,
2538};
2539
2540static void create_proc_file(void)
2541{
cdefa185 2542 proc_create(proc_filename, 0, NULL, &proc_ops);
1da177e4
LT		 2543}
2544
2545static void remove_proc_file(void)
2546{
313980c9 2547 remove_proc_entry(proc_filename, NULL);
1da177e4
LT		 2548}
2549
2550#else
2551
2552static inline void create_proc_file(void) {}
2553static inline void remove_proc_file(void) {}
2554
2555#endif
2556
2557/*-------------------------------------------------------------------------*/
2558
2559/* Before this controller can enumerate, we need to pick an endpoint
2560 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2561 * buffer space among the endpoints we'll be operating.
65111084
DB		 2562 *
2563 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
f35ae634 2564 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
65111084 2565 * capability yet though.
1da177e4
LT		 2566 */
2567static unsigned __init
2568omap_ep_setup(char *name, u8 addr, u8 type,
2569 unsigned buf, unsigned maxp, int dbuf)
2570{
2571 struct omap_ep *ep;
2572 u16 epn_rxtx = 0;
2573
2574 /* OUT endpoints first, then IN */
2575 ep = &udc->ep[addr & 0xf];
2576 if (addr & USB_DIR_IN)
2577 ep += 16;
2578
2579 /* in case of ep init table bugs */
2580 BUG_ON(ep->name[0]);
2581
2582 /* chip setup ... bit values are same for IN, OUT */
2583 if (type == USB_ENDPOINT_XFER_ISOC) {
2584 switch (maxp) {
2585 case 8: epn_rxtx = 0 << 12; break;
2586 case 16: epn_rxtx = 1 << 12; break;
2587 case 32: epn_rxtx = 2 << 12; break;
2588 case 64: epn_rxtx = 3 << 12; break;
2589 case 128: epn_rxtx = 4 << 12; break;
2590 case 256: epn_rxtx = 5 << 12; break;
2591 case 512: epn_rxtx = 6 << 12; break;
2592 default: BUG();
2593 }
2594 epn_rxtx |= UDC_EPN_RX_ISO;
2595 dbuf = 1;
2596 } else {
2597 /* double-buffering "not supported" on 15xx,
e6a6e472
DB		 2598 * and ignored for PIO-IN on newer chips
2599 * (for more reliable behavior)
1da177e4 2600 */
e6a6e472 2601 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
1da177e4
LT		 2602 dbuf = 0;
2603
2604 switch (maxp) {
2605 case 8: epn_rxtx = 0 << 12; break;
2606 case 16: epn_rxtx = 1 << 12; break;
2607 case 32: epn_rxtx = 2 << 12; break;
2608 case 64: epn_rxtx = 3 << 12; break;
2609 default: BUG();
2610 }
2611 if (dbuf && addr)
2612 epn_rxtx |= UDC_EPN_RX_DB;
2613 init_timer(&ep->timer);
2614 ep->timer.function = pio_out_timer;
2615 ep->timer.data = (unsigned long) ep;
2616 }
2617 if (addr)
2618 epn_rxtx |= UDC_EPN_RX_VALID;
2619 BUG_ON(buf & 0x07);
2620 epn_rxtx |= buf >> 3;
2621
2622 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2623 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2624
2625 if (addr & USB_DIR_IN)
f35ae634 2626 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
1da177e4 2627 else
f35ae634 2628 omap_writew(epn_rxtx, UDC_EP_RX(addr));
1da177e4
LT		 2629
2630 /* next endpoint's buffer starts after this one's */
2631 buf += maxp;
2632 if (dbuf)
2633 buf += maxp;
2634 BUG_ON(buf > 2048);
2635
2636 /* set up driver data structures */
2637 BUG_ON(strlen(name) >= sizeof ep->name);
2638 strlcpy(ep->name, name, sizeof ep->name);
2639 INIT_LIST_HEAD(&ep->queue);
2640 INIT_LIST_HEAD(&ep->iso);
2641 ep->bEndpointAddress = addr;
2642 ep->bmAttributes = type;
2643 ep->double_buf = dbuf;
e6a6e472 2644 ep->udc = udc;
1da177e4
LT		 2645
2646 ep->ep.name = ep->name;
2647 ep->ep.ops = &omap_ep_ops;
2648 ep->ep.maxpacket = ep->maxpacket = maxp;
2649 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2650
2651 return buf;
2652}
2653
2654static void omap_udc_release(struct device *dev)
2655{
2656 complete(udc->done);
2657 kfree (udc);
313980c9 2658 udc = NULL;
1da177e4
LT		 2659}
2660
2661static int __init
2662omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2663{
2664 unsigned tmp, buf;
2665
2666 /* abolish any previous hardware state */
f35ae634
TL		 2667 omap_writew(0, UDC_SYSCON1);
2668 omap_writew(0, UDC_IRQ_EN);
2669 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2670 omap_writew(0, UDC_DMA_IRQ_EN);
2671 omap_writew(0, UDC_RXDMA_CFG);
2672 omap_writew(0, UDC_TXDMA_CFG);
1da177e4
LT		 2673
2674 /* UDC_PULLUP_EN gates the chip clock */
f35ae634 2675 // OTG_SYSCON_1 |= DEV_IDLE_EN;
1da177e4 2676
e94b1766 2677 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
1da177e4
LT		 2678 if (!udc)
2679 return -ENOMEM;
2680
1da177e4
LT		 2681 spin_lock_init (&udc->lock);
2682
2683 udc->gadget.ops = &omap_gadget_ops;
2684 udc->gadget.ep0 = &udc->ep[0].ep;
2685 INIT_LIST_HEAD(&udc->gadget.ep_list);
2686 INIT_LIST_HEAD(&udc->iso);
2687 udc->gadget.speed = USB_SPEED_UNKNOWN;
2688 udc->gadget.name = driver_name;
2689
2690 device_initialize(&udc->gadget.dev);
0031a06e 2691 dev_set_name(&udc->gadget.dev, "gadget");
1da177e4
LT		 2692 udc->gadget.dev.release = omap_udc_release;
2693 udc->gadget.dev.parent = &odev->dev;
2694 if (use_dma)
2695 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2696
2697 udc->transceiver = xceiv;
2698
2699 /* ep0 is special; put it right after the SETUP buffer */
2700 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2701 8 /* after SETUP */, 64 /* maxpacket */, 0);
2702 list_del_init(&udc->ep[0].ep.ep_list);
2703
2704 /* initially disable all non-ep0 endpoints */
2705 for (tmp = 1; tmp < 15; tmp++) {
f35ae634
TL		 2706 omap_writew(0, UDC_EP_RX(tmp));
2707 omap_writew(0, UDC_EP_TX(tmp));
1da177e4
LT		 2708 }
2709
2710#define OMAP_BULK_EP(name,addr) \
2711 buf = omap_ep_setup(name "-bulk", addr, \
2712 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2713#define OMAP_INT_EP(name,addr, maxp) \
2714 buf = omap_ep_setup(name "-int", addr, \
2715 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2716#define OMAP_ISO_EP(name,addr, maxp) \
2717 buf = omap_ep_setup(name "-iso", addr, \
2718 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2719
2720 switch (fifo_mode) {
2721 case 0:
2722 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2723 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2724 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2725 break;
2726 case 1:
2727 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2728 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
313980c9
DB		 2729 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2730
1da177e4
LT		 2731 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2732 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
313980c9 2733 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
1da177e4
LT		 2734
2735 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2736 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
313980c9
DB		 2737 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2738
1da177e4
LT		 2739 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2740 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
313980c9 2741 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
1da177e4
LT		 2742
2743 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2744 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
313980c9
DB		 2745 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2746 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2747
1da177e4
LT		 2748 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2749 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
313980c9
DB		 2750 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2751 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2752
2753 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2754 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
1da177e4 2755
1da177e4
LT		 2756 break;
2757
2758#ifdef USE_ISO
2759 case 2: /* mixed iso/bulk */
2760 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2761 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2762 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2763 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2764
2765 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2766
2767 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2768 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2769 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2770 break;
2771 case 3: /* mixed bulk/iso */
2772 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2773 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2774 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2775
2776 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2777 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2778 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2779
2780 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2781 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2782 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2783 break;
2784#endif
2785
2786 /* add more modes as needed */
2787
2788 default:
2789 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2790 return -ENODEV;
2791 }
f35ae634 2792 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
1da177e4
LT		 2793 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2794 return 0;
2795}
2796
3ae5eaec 2797static int __init omap_udc_probe(struct platform_device *pdev)
1da177e4 2798{
1da177e4
LT		 2799 int status = -ENODEV;
2800 int hmc;
313980c9
DB		 2801 struct otg_transceiver *xceiv = NULL;
2802 const char *type = NULL;
3ae5eaec 2803 struct omap_usb_config *config = pdev->dev.platform_data;
e6a6e472
DB		 2804 struct clk *dc_clk;
2805 struct clk *hhc_clk;
1da177e4
LT		 2806
2807 /* NOTE: "knows" the order of the resources! */
e6a6e472 2808 if (!request_mem_region(pdev->resource[0].start,
3ae5eaec 2809 pdev->resource[0].end - pdev->resource[0].start + 1,
1da177e4
LT		 2810 driver_name)) {
2811 DBG("request_mem_region failed\n");
2812 return -EBUSY;
2813 }
2814
e6a6e472
DB		 2815 if (cpu_is_omap16xx()) {
2816 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2817 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2818 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2819 /* can't use omap_udc_enable_clock yet */
2820 clk_enable(dc_clk);
2821 clk_enable(hhc_clk);
2822 udelay(100);
2823 }
2824
2825 if (cpu_is_omap24xx()) {
2826 dc_clk = clk_get(&pdev->dev, "usb_fck");
2827 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2828 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2829 /* can't use omap_udc_enable_clock yet */
2830 clk_enable(dc_clk);
2831 clk_enable(hhc_clk);
2832 udelay(100);
2833 }
2834
45f780a0
CM		 2835 if (cpu_is_omap7xx()) {
2836 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2837 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2838 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2839 /* can't use omap_udc_enable_clock yet */
2840 clk_enable(dc_clk);
2841 clk_enable(hhc_clk);
2842 udelay(100);
2843 }
2844
1da177e4 2845 INFO("OMAP UDC rev %d.%d%s\n",
f35ae634 2846 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
1da177e4
LT		 2847 config->otg ? ", Mini-AB" : "");
2848
2849 /* use the mode given to us by board init code */
2850 if (cpu_is_omap15xx()) {
2851 hmc = HMC_1510;
2852 type = "(unknown)";
2853
8a3c1f57 2854 if (machine_without_vbus_sense()) {
1da177e4
LT		 2855 /* just set up software VBUS detect, and then
2856 * later rig it so we always report VBUS.
2857 * FIXME without really sensing VBUS, we can't
2858 * know when to turn PULLUP_EN on/off; and that
2859 * means we always "need" the 48MHz clock.
2860 */
f35ae634
TL		 2861 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2862 tmp &= ~VBUS_CTRL_1510;
2863 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2864 tmp |= VBUS_MODE_1510;
2865 tmp &= ~VBUS_CTRL_1510;
f35ae634 2866 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2867 }
2868 } else {
65111084
DB		 2869 /* The transceiver may package some GPIO logic or handle
2870 * loopback and/or transceiverless setup; if we find one,
2871 * use it. Except for OTG, we don't _need_ to talk to one;
2872 * but not having one probably means no VBUS detection.
2873 */
2874 xceiv = otg_get_transceiver();
2875 if (xceiv)
2876 type = xceiv->label;
2877 else if (config->otg) {
2878 DBG("OTG requires external transceiver!\n");
2879 goto cleanup0;
2880 }
2881
1da177e4 2882 hmc = HMC_1610;
e6a6e472
DB		 2883
2884 if (cpu_is_omap24xx()) {
2885 /* this could be transceiverless in one of the
2886 * "we don't need to know" modes.
2887 */
2888 type = "external";
2889 goto known;
2890 }
2891
1da177e4 2892 switch (hmc) {
313980c9
DB		 2893 case 0: /* POWERUP DEFAULT == 0 */
2894 case 4:
2895 case 12:
2896 case 20:
2897 if (!cpu_is_omap1710()) {
2898 type = "integrated";
2899 break;
2900 }
2901 /* FALL THROUGH */
1da177e4
LT		 2902 case 3:
2903 case 11:
2904 case 16:
2905 case 19:
2906 case 25:
1da177e4
LT		 2907 if (!xceiv) {
2908 DBG("external transceiver not registered!\n");
313980c9 2909 type = "unknown";
65111084 2910 }
1da177e4 2911 break;
1da177e4 2912 case 21: /* internal loopback */
313980c9 2913 type = "loopback";
1da177e4
LT		 2914 break;
2915 case 14: /* transceiverless */
65111084
DB		 2916 if (cpu_is_omap1710())
2917 goto bad_on_1710;
2918 /* FALL THROUGH */
2919 case 13:
2920 case 15:
313980c9 2921 type = "no";
1da177e4
LT		 2922 break;
2923
2924 default:
65111084 2925bad_on_1710:
1da177e4 2926 ERR("unrecognized UDC HMC mode %d\n", hmc);
65111084 2927 goto cleanup0;
1da177e4
LT		 2928 }
2929 }
e6a6e472 2930known:
313980c9 2931 INFO("hmc mode %d, %s transceiver\n", hmc, type);
1da177e4
LT		 2932
2933 /* a "gadget" abstracts/virtualizes the controller */
3ae5eaec 2934 status = omap_udc_setup(pdev, xceiv);
1da177e4
LT		 2935 if (status) {
2936 goto cleanup0;
2937 }
313980c9 2938 xceiv = NULL;
1da177e4
LT		 2939 // "udc" is now valid
2940 pullup_disable(udc);
2941#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2942 udc->gadget.is_otg = (config->otg != 0);
2943#endif
2944
65111084 2945 /* starting with omap1710 es2.0, clear toggle is a separate bit */
f35ae634 2946 if (omap_readw(UDC_REV) >= 0x61)
65111084
DB		 2947 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2948 else
2949 udc->clr_halt = UDC_RESET_EP;
2950
1da177e4 2951 /* USB general purpose IRQ: ep0, state changes, dma, etc */
3ae5eaec 2952 status = request_irq(pdev->resource[1].start, omap_udc_irq,
d54b5caa 2953 IRQF_SAMPLE_RANDOM, driver_name, udc);
1da177e4 2954 if (status != 0) {
e6a6e472
DB		 2955 ERR("can't get irq %d, err %d\n",
2956 (int) pdev->resource[1].start, status);
1da177e4
LT		 2957 goto cleanup1;
2958 }
2959
2960 /* USB "non-iso" IRQ (PIO for all but ep0) */
3ae5eaec 2961 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
d54b5caa 2962 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
1da177e4 2963 if (status != 0) {
e6a6e472
DB		 2964 ERR("can't get irq %d, err %d\n",
2965 (int) pdev->resource[2].start, status);
1da177e4
LT		 2966 goto cleanup2;
2967 }
2968#ifdef USE_ISO
3ae5eaec 2969 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
d54b5caa 2970 IRQF_DISABLED, "omap_udc iso", udc);
1da177e4 2971 if (status != 0) {
e6a6e472
DB		 2972 ERR("can't get irq %d, err %d\n",
2973 (int) pdev->resource[3].start, status);
1da177e4
LT		 2974 goto cleanup3;
2975 }
2976#endif
45f780a0 2977 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 2978 udc->dc_clk = dc_clk;
2979 udc->hhc_clk = hhc_clk;
2980 clk_disable(hhc_clk);
2981 clk_disable(dc_clk);
2982 }
2983
2984 if (cpu_is_omap24xx()) {
2985 udc->dc_clk = dc_clk;
2986 udc->hhc_clk = hhc_clk;
2987 /* FIXME OMAP2 don't release hhc & dc clock */
2988#if 0
2989 clk_disable(hhc_clk);
2990 clk_disable(dc_clk);
2991#endif
2992 }
1da177e4
LT		 2993
2994 create_proc_file();
e6a6e472 2995 status = device_add(&udc->gadget.dev);
0f91349b
SAS		 2996 if (status)
2997 goto cleanup4;
2998
2999 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
e6a6e472
DB		 3000 if (!status)
3001 return status;
3002 /* If fail, fall through */
0f91349b
SAS		 3003cleanup4:
3004 remove_proc_file();
3005
1da177e4
LT		 3006#ifdef USE_ISO
3007cleanup3:
3ae5eaec 3008 free_irq(pdev->resource[2].start, udc);
1da177e4
LT		 3009#endif
3010
3011cleanup2:
3ae5eaec 3012 free_irq(pdev->resource[1].start, udc);
1da177e4
LT		 3013
3014cleanup1:
3015 kfree (udc);
313980c9 3016 udc = NULL;
1da177e4
LT		 3017
3018cleanup0:
3019 if (xceiv)
68144e0c 3020 otg_put_transceiver(xceiv);
e6a6e472 3021
45f780a0 3022 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 3023 clk_disable(hhc_clk);
3024 clk_disable(dc_clk);
3025 clk_put(hhc_clk);
3026 clk_put(dc_clk);
3027 }
3028
3ae5eaec
RK		 3029 release_mem_region(pdev->resource[0].start,
3030 pdev->resource[0].end - pdev->resource[0].start + 1);
e6a6e472 3031
1da177e4
LT		 3032 return status;
3033}
3034
3ae5eaec 3035static int __exit omap_udc_remove(struct platform_device *pdev)
1da177e4 3036{
6e9a4738 3037 DECLARE_COMPLETION_ONSTACK(done);
1da177e4
LT		 3038
3039 if (!udc)
3040 return -ENODEV;
0f91349b
SAS		 3041
3042 usb_del_gadget_udc(&udc->gadget);
6bea476c
DB		 3043 if (udc->driver)
3044 return -EBUSY;
1da177e4
LT		 3045
3046 udc->done = &done;
3047
3048 pullup_disable(udc);
3049 if (udc->transceiver) {
68144e0c 3050 otg_put_transceiver(udc->transceiver);
313980c9 3051 udc->transceiver = NULL;
1da177e4 3052 }
f35ae634 3053 omap_writew(0, UDC_SYSCON1);
1da177e4
LT		 3054
3055 remove_proc_file();
3056
3057#ifdef USE_ISO
3ae5eaec 3058 free_irq(pdev->resource[3].start, udc);
1da177e4 3059#endif
3ae5eaec
RK		 3060 free_irq(pdev->resource[2].start, udc);
3061 free_irq(pdev->resource[1].start, udc);
1da177e4 3062
e6a6e472
DB		 3063 if (udc->dc_clk) {
3064 if (udc->clk_requested)
3065 omap_udc_enable_clock(0);
3066 clk_put(udc->hhc_clk);
3067 clk_put(udc->dc_clk);
3068 }
3069
3ae5eaec
RK		 3070 release_mem_region(pdev->resource[0].start,
3071 pdev->resource[0].end - pdev->resource[0].start + 1);
1da177e4
LT		 3072
3073 device_unregister(&udc->gadget.dev);
3074 wait_for_completion(&done);
3075
3076 return 0;
3077}
3078
313980c9
DB		 3079/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3080 * system is forced into deep sleep
3081 *
3082 * REVISIT we should probably reject suspend requests when there's a host
3083 * session active, rather than disconnecting, at least on boards that can
f35ae634 3084 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
313980c9
DB		 3085 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3086 * may involve talking to an external transceiver (e.g. isp1301).
3087 */
1d7beee3 3088
3ae5eaec 3089static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
1da177e4 3090{
313980c9
DB		 3091 u32 devstat;
3092
f35ae634 3093 devstat = omap_readw(UDC_DEVSTAT);
313980c9
DB		 3094
3095 /* we're requesting 48 MHz clock if the pullup is enabled
3096 * (== we're attached to the host) and we're not suspended,
3097 * which would prevent entry to deep sleep...
3098 */
3099 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
b6c63937 3100 WARNING("session active; suspend requires disconnect\n");
313980c9
DB		 3101 omap_pullup(&udc->gadget, 0);
3102 }
1da177e4 3103
1da177e4
LT		 3104 return 0;
3105}
3106
3ae5eaec 3107static int omap_udc_resume(struct platform_device *dev)
1da177e4 3108{
1da177e4 3109 DBG("resume + wakeup/SRP\n");
1da177e4
LT		 3110 omap_pullup(&udc->gadget, 1);
3111
3112 /* maybe the host would enumerate us if we nudged it */
3113 msleep(100);
3114 return omap_wakeup(&udc->gadget);
3115}
3116
3117/*-------------------------------------------------------------------------*/
3118
3ae5eaec 3119static struct platform_driver udc_driver = {
1da177e4
LT		 3120 .remove = __exit_p(omap_udc_remove),
3121 .suspend = omap_udc_suspend,
3122 .resume = omap_udc_resume,
3ae5eaec
RK		 3123 .driver = {
3124 .owner = THIS_MODULE,
3125 .name = (char *) driver_name,
3126 },
1da177e4
LT		 3127};
3128
3129static int __init udc_init(void)
3130{
45f780a0
CM		 3131 /* Disable DMA for omap7xx -- it doesn't work right. */
3132 if (cpu_is_omap7xx())
3133 use_dma = 0;
3134
1da177e4
LT		 3135 INFO("%s, version: " DRIVER_VERSION
3136#ifdef USE_ISO
3137 " (iso)"
3138#endif
3139 "%s\n", driver_desc,
3140 use_dma ? " (dma)" : "");
864e28b4 3141 return platform_driver_probe(&udc_driver, omap_udc_probe);
1da177e4
LT		 3142}
3143module_init(udc_init);
3144
3145static void __exit udc_exit(void)
3146{
3ae5eaec 3147 platform_driver_unregister(&udc_driver);
1da177e4
LT		 3148}
3149module_exit(udc_exit);
3150
3151MODULE_DESCRIPTION(DRIVER_DESC);
3152MODULE_LICENSE("GPL");
f34c32f1 3153MODULE_ALIAS("platform:omap_udc");
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