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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * omap_udc.c -- for OMAP full speed udc; most chips support OTG. | |
3 | * | |
4 | * Copyright (C) 2004 Texas Instruments, Inc. | |
5 | * Copyright (C) 2004-2005 David Brownell | |
6 | * | |
527ea73e KP |
7 | * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com> |
8 | * | |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
1da177e4 LT |
13 | */ |
14 | ||
15 | #undef DEBUG | |
16 | #undef VERBOSE | |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/types.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/delay.h> | |
1da177e4 LT |
24 | #include <linux/slab.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/timer.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/moduleparam.h> | |
d052d1be | 32 | #include <linux/platform_device.h> |
5f848137 | 33 | #include <linux/usb/ch9.h> |
9454a57a | 34 | #include <linux/usb/gadget.h> |
3a16f7b4 | 35 | #include <linux/usb/otg.h> |
1da177e4 | 36 | #include <linux/dma-mapping.h> |
e6a6e472 | 37 | #include <linux/clk.h> |
ded017ee | 38 | #include <linux/err.h> |
268bb0ce | 39 | #include <linux/prefetch.h> |
80dd1358 | 40 | #include <linux/io.h> |
1da177e4 LT |
41 | |
42 | #include <asm/byteorder.h> | |
1da177e4 | 43 | #include <asm/irq.h> |
1da177e4 LT |
44 | #include <asm/unaligned.h> |
45 | #include <asm/mach-types.h> | |
46 | ||
45c3eb7d | 47 | #include <linux/omap-dma.h> |
b924b204 TL |
48 | |
49 | #include <mach/usb.h> | |
1da177e4 LT |
50 | |
51 | #include "omap_udc.h" | |
52 | ||
53 | #undef USB_TRACE | |
54 | ||
55 | /* bulk DMA seems to be behaving for both IN and OUT */ | |
56 | #define USE_DMA | |
57 | ||
58 | /* ISO too */ | |
59 | #define USE_ISO | |
60 | ||
61 | #define DRIVER_DESC "OMAP UDC driver" | |
62 | #define DRIVER_VERSION "4 October 2004" | |
63 | ||
8c4cc005 | 64 | #define OMAP_DMA_USB_W2FC_TX0 29 |
518868c8 | 65 | #define OMAP_DMA_USB_W2FC_RX0 26 |
8c4cc005 | 66 | |
1da177e4 LT |
67 | /* |
68 | * The OMAP UDC needs _very_ early endpoint setup: before enabling the | |
69 | * D+ pullup to allow enumeration. That's too early for the gadget | |
70 | * framework to use from usb_endpoint_enable(), which happens after | |
71 | * enumeration as part of activating an interface. (But if we add an | |
72 | * optional new "UDC not yet running" state to the gadget driver model, | |
73 | * even just during driver binding, the endpoint autoconfig logic is the | |
74 | * natural spot to manufacture new endpoints.) | |
75 | * | |
76 | * So instead of using endpoint enable calls to control the hardware setup, | |
77 | * this driver defines a "fifo mode" parameter. It's used during driver | |
78 | * initialization to choose among a set of pre-defined endpoint configs. | |
79 | * See omap_udc_setup() for available modes, or to add others. That code | |
80 | * lives in an init section, so use this driver as a module if you need | |
81 | * to change the fifo mode after the kernel boots. | |
82 | * | |
83 | * Gadget drivers normally ignore endpoints they don't care about, and | |
84 | * won't include them in configuration descriptors. That means only | |
85 | * misbehaving hosts would even notice they exist. | |
86 | */ | |
87 | #ifdef USE_ISO | |
88 | static unsigned fifo_mode = 3; | |
89 | #else | |
80dd1358 | 90 | static unsigned fifo_mode; |
1da177e4 LT |
91 | #endif |
92 | ||
93 | /* "modprobe omap_udc fifo_mode=42", or else as a kernel | |
94 | * boot parameter "omap_udc:fifo_mode=42" | |
95 | */ | |
80dd1358 FB |
96 | module_param(fifo_mode, uint, 0); |
97 | MODULE_PARM_DESC(fifo_mode, "endpoint configuration"); | |
1da177e4 LT |
98 | |
99 | #ifdef USE_DMA | |
90ab5ee9 | 100 | static bool use_dma = 1; |
1da177e4 LT |
101 | |
102 | /* "modprobe omap_udc use_dma=y", or else as a kernel | |
103 | * boot parameter "omap_udc:use_dma=y" | |
104 | */ | |
80dd1358 FB |
105 | module_param(use_dma, bool, 0); |
106 | MODULE_PARM_DESC(use_dma, "enable/disable DMA"); | |
1da177e4 LT |
107 | #else /* !USE_DMA */ |
108 | ||
109 | /* save a bit of code */ | |
110 | #define use_dma 0 | |
111 | #endif /* !USE_DMA */ | |
112 | ||
113 | ||
80dd1358 FB |
114 | static const char driver_name[] = "omap_udc"; |
115 | static const char driver_desc[] = DRIVER_DESC; | |
1da177e4 LT |
116 | |
117 | /*-------------------------------------------------------------------------*/ | |
118 | ||
119 | /* there's a notion of "current endpoint" for modifying endpoint | |
e6a6e472 | 120 | * state, and PIO access to its FIFO. |
1da177e4 LT |
121 | */ |
122 | ||
123 | static void use_ep(struct omap_ep *ep, u16 select) | |
124 | { | |
125 | u16 num = ep->bEndpointAddress & 0x0f; | |
126 | ||
127 | if (ep->bEndpointAddress & USB_DIR_IN) | |
128 | num |= UDC_EP_DIR; | |
f35ae634 | 129 | omap_writew(num | select, UDC_EP_NUM); |
1da177e4 LT |
130 | /* when select, MUST deselect later !! */ |
131 | } | |
132 | ||
133 | static inline void deselect_ep(void) | |
134 | { | |
f35ae634 TL |
135 | u16 w; |
136 | ||
137 | w = omap_readw(UDC_EP_NUM); | |
138 | w &= ~UDC_EP_SEL; | |
139 | omap_writew(w, UDC_EP_NUM); | |
1da177e4 LT |
140 | /* 6 wait states before TX will happen */ |
141 | } | |
142 | ||
143 | static void dma_channel_claim(struct omap_ep *ep, unsigned preferred); | |
144 | ||
145 | /*-------------------------------------------------------------------------*/ | |
146 | ||
147 | static int omap_ep_enable(struct usb_ep *_ep, | |
148 | const struct usb_endpoint_descriptor *desc) | |
149 | { | |
150 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
151 | struct omap_udc *udc; | |
152 | unsigned long flags; | |
153 | u16 maxp; | |
154 | ||
155 | /* catch various bogus parameters */ | |
77964b3c | 156 | if (!_ep || !desc |
1da177e4 LT |
157 | || desc->bDescriptorType != USB_DT_ENDPOINT |
158 | || ep->bEndpointAddress != desc->bEndpointAddress | |
29cc8897 | 159 | || ep->maxpacket < usb_endpoint_maxp(desc)) { |
441b62c1 | 160 | DBG("%s, bad ep or descriptor\n", __func__); |
1da177e4 LT |
161 | return -EINVAL; |
162 | } | |
29cc8897 | 163 | maxp = usb_endpoint_maxp(desc); |
1da177e4 LT |
164 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK |
165 | && maxp != ep->maxpacket) | |
29cc8897 | 166 | || usb_endpoint_maxp(desc) > ep->maxpacket |
1da177e4 | 167 | || !desc->wMaxPacketSize) { |
441b62c1 | 168 | DBG("%s, bad %s maxpacket\n", __func__, _ep->name); |
1da177e4 LT |
169 | return -ERANGE; |
170 | } | |
171 | ||
172 | #ifdef USE_ISO | |
173 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
174 | && desc->bInterval != 1)) { | |
175 | /* hardware wants period = 1; USB allows 2^(Interval-1) */ | |
176 | DBG("%s, unsupported ISO period %dms\n", _ep->name, | |
177 | 1 << (desc->bInterval - 1)); | |
178 | return -EDOM; | |
179 | } | |
180 | #else | |
181 | if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
182 | DBG("%s, ISO nyet\n", _ep->name); | |
183 | return -EDOM; | |
184 | } | |
185 | #endif | |
186 | ||
187 | /* xfer types must match, except that interrupt ~= bulk */ | |
188 | if (ep->bmAttributes != desc->bmAttributes | |
189 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK | |
190 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { | |
441b62c1 | 191 | DBG("%s, %s type mismatch\n", __func__, _ep->name); |
1da177e4 LT |
192 | return -EINVAL; |
193 | } | |
194 | ||
195 | udc = ep->udc; | |
196 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { | |
441b62c1 | 197 | DBG("%s, bogus device state\n", __func__); |
1da177e4 LT |
198 | return -ESHUTDOWN; |
199 | } | |
200 | ||
201 | spin_lock_irqsave(&udc->lock, flags); | |
202 | ||
f8bdae06 | 203 | ep->ep.desc = desc; |
1da177e4 LT |
204 | ep->irqs = 0; |
205 | ep->stopped = 0; | |
206 | ep->ep.maxpacket = maxp; | |
207 | ||
208 | /* set endpoint to initial state */ | |
209 | ep->dma_channel = 0; | |
210 | ep->has_dma = 0; | |
211 | ep->lch = -1; | |
212 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 213 | omap_writew(udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
214 | ep->ackwait = 0; |
215 | deselect_ep(); | |
216 | ||
217 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
218 | list_add(&ep->iso, &udc->iso); | |
219 | ||
220 | /* maybe assign a DMA channel to this endpoint */ | |
221 | if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK) | |
222 | /* FIXME ISO can dma, but prefers first channel */ | |
223 | dma_channel_claim(ep, 0); | |
224 | ||
225 | /* PIO OUT may RX packets */ | |
226 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC | |
227 | && !ep->has_dma | |
228 | && !(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 229 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
230 | ep->ackwait = 1 + ep->double_buf; |
231 | } | |
232 | ||
233 | spin_unlock_irqrestore(&udc->lock, flags); | |
234 | VDBG("%s enabled\n", _ep->name); | |
235 | return 0; | |
236 | } | |
237 | ||
238 | static void nuke(struct omap_ep *, int status); | |
239 | ||
240 | static int omap_ep_disable(struct usb_ep *_ep) | |
241 | { | |
242 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
243 | unsigned long flags; | |
244 | ||
f8bdae06 | 245 | if (!_ep || !ep->ep.desc) { |
441b62c1 | 246 | DBG("%s, %s not enabled\n", __func__, |
1da177e4 LT |
247 | _ep ? ep->ep.name : NULL); |
248 | return -EINVAL; | |
249 | } | |
250 | ||
251 | spin_lock_irqsave(&ep->udc->lock, flags); | |
f9c56cdd | 252 | ep->ep.desc = NULL; |
80dd1358 | 253 | nuke(ep, -ESHUTDOWN); |
1da177e4 LT |
254 | ep->ep.maxpacket = ep->maxpacket; |
255 | ep->has_dma = 0; | |
f35ae634 | 256 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
257 | list_del_init(&ep->iso); |
258 | del_timer(&ep->timer); | |
259 | ||
260 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
261 | ||
262 | VDBG("%s disabled\n", _ep->name); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | /*-------------------------------------------------------------------------*/ | |
267 | ||
268 | static struct usb_request * | |
55016f10 | 269 | omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1da177e4 LT |
270 | { |
271 | struct omap_req *req; | |
272 | ||
7039f422 | 273 | req = kzalloc(sizeof(*req), gfp_flags); |
70617db7 FB |
274 | if (!req) |
275 | return NULL; | |
276 | ||
70617db7 FB |
277 | INIT_LIST_HEAD(&req->queue); |
278 | ||
1da177e4 LT |
279 | return &req->req; |
280 | } | |
281 | ||
282 | static void | |
283 | omap_free_request(struct usb_ep *ep, struct usb_request *_req) | |
284 | { | |
285 | struct omap_req *req = container_of(_req, struct omap_req, req); | |
286 | ||
23673d7d | 287 | kfree(req); |
1da177e4 LT |
288 | } |
289 | ||
290 | /*-------------------------------------------------------------------------*/ | |
291 | ||
1da177e4 LT |
292 | static void |
293 | done(struct omap_ep *ep, struct omap_req *req, int status) | |
294 | { | |
dd8e9381 | 295 | struct omap_udc *udc = ep->udc; |
1da177e4 LT |
296 | unsigned stopped = ep->stopped; |
297 | ||
298 | list_del_init(&req->queue); | |
299 | ||
300 | if (req->req.status == -EINPROGRESS) | |
301 | req->req.status = status; | |
302 | else | |
303 | status = req->req.status; | |
304 | ||
dd8e9381 FB |
305 | if (use_dma && ep->has_dma) |
306 | usb_gadget_unmap_request(&udc->gadget, &req->req, | |
307 | (ep->bEndpointAddress & USB_DIR_IN)); | |
1da177e4 LT |
308 | |
309 | #ifndef USB_TRACE | |
310 | if (status && status != -ESHUTDOWN) | |
311 | #endif | |
312 | VDBG("complete %s req %p stat %d len %u/%u\n", | |
313 | ep->ep.name, &req->req, status, | |
314 | req->req.actual, req->req.length); | |
315 | ||
316 | /* don't modify queue heads during completion callback */ | |
317 | ep->stopped = 1; | |
318 | spin_unlock(&ep->udc->lock); | |
319 | req->req.complete(&ep->ep, &req->req); | |
320 | spin_lock(&ep->udc->lock); | |
321 | ep->stopped = stopped; | |
322 | } | |
323 | ||
324 | /*-------------------------------------------------------------------------*/ | |
325 | ||
313980c9 DB |
326 | #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) |
327 | #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL) | |
1da177e4 LT |
328 | |
329 | #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) | |
330 | #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) | |
331 | ||
e6a6e472 | 332 | static inline int |
1da177e4 LT |
333 | write_packet(u8 *buf, struct omap_req *req, unsigned max) |
334 | { | |
335 | unsigned len; | |
336 | u16 *wp; | |
337 | ||
338 | len = min(req->req.length - req->req.actual, max); | |
339 | req->req.actual += len; | |
340 | ||
341 | max = len; | |
342 | if (likely((((int)buf) & 1) == 0)) { | |
343 | wp = (u16 *)buf; | |
344 | while (max >= 2) { | |
f35ae634 | 345 | omap_writew(*wp++, UDC_DATA); |
1da177e4 LT |
346 | max -= 2; |
347 | } | |
348 | buf = (u8 *)wp; | |
349 | } | |
350 | while (max--) | |
f35ae634 | 351 | omap_writeb(*buf++, UDC_DATA); |
1da177e4 LT |
352 | return len; |
353 | } | |
354 | ||
80dd1358 | 355 | /* FIXME change r/w fifo calling convention */ |
1da177e4 LT |
356 | |
357 | ||
80dd1358 | 358 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1da177e4 LT |
359 | static int write_fifo(struct omap_ep *ep, struct omap_req *req) |
360 | { | |
361 | u8 *buf; | |
362 | unsigned count; | |
363 | int is_last; | |
364 | u16 ep_stat; | |
365 | ||
366 | buf = req->req.buf + req->req.actual; | |
367 | prefetch(buf); | |
368 | ||
369 | /* PIO-IN isn't double buffered except for iso */ | |
f35ae634 | 370 | ep_stat = omap_readw(UDC_STAT_FLG); |
313980c9 | 371 | if (ep_stat & UDC_FIFO_UNWRITABLE) |
1da177e4 LT |
372 | return 0; |
373 | ||
374 | count = ep->ep.maxpacket; | |
375 | count = write_packet(buf, req, count); | |
f35ae634 | 376 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
377 | ep->ackwait = 1; |
378 | ||
379 | /* last packet is often short (sometimes a zlp) */ | |
380 | if (count != ep->ep.maxpacket) | |
381 | is_last = 1; | |
382 | else if (req->req.length == req->req.actual | |
383 | && !req->req.zero) | |
384 | is_last = 1; | |
385 | else | |
386 | is_last = 0; | |
387 | ||
388 | /* NOTE: requests complete when all IN data is in a | |
389 | * FIFO (or sometimes later, if a zlp was needed). | |
390 | * Use usb_ep_fifo_status() where needed. | |
391 | */ | |
392 | if (is_last) | |
393 | done(ep, req, 0); | |
394 | return is_last; | |
395 | } | |
396 | ||
e6a6e472 | 397 | static inline int |
1da177e4 LT |
398 | read_packet(u8 *buf, struct omap_req *req, unsigned avail) |
399 | { | |
400 | unsigned len; | |
401 | u16 *wp; | |
402 | ||
403 | len = min(req->req.length - req->req.actual, avail); | |
404 | req->req.actual += len; | |
405 | avail = len; | |
406 | ||
407 | if (likely((((int)buf) & 1) == 0)) { | |
408 | wp = (u16 *)buf; | |
409 | while (avail >= 2) { | |
f35ae634 | 410 | *wp++ = omap_readw(UDC_DATA); |
1da177e4 LT |
411 | avail -= 2; |
412 | } | |
413 | buf = (u8 *)wp; | |
414 | } | |
415 | while (avail--) | |
f35ae634 | 416 | *buf++ = omap_readb(UDC_DATA); |
1da177e4 LT |
417 | return len; |
418 | } | |
419 | ||
80dd1358 | 420 | /* return: 0 = still running, 1 = queue empty, negative = errno */ |
1da177e4 LT |
421 | static int read_fifo(struct omap_ep *ep, struct omap_req *req) |
422 | { | |
423 | u8 *buf; | |
424 | unsigned count, avail; | |
425 | int is_last; | |
426 | ||
427 | buf = req->req.buf + req->req.actual; | |
428 | prefetchw(buf); | |
429 | ||
430 | for (;;) { | |
f35ae634 | 431 | u16 ep_stat = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
432 | |
433 | is_last = 0; | |
434 | if (ep_stat & FIFO_EMPTY) { | |
435 | if (!ep->double_buf) | |
436 | break; | |
437 | ep->fnf = 1; | |
438 | } | |
439 | if (ep_stat & UDC_EP_HALTED) | |
440 | break; | |
441 | ||
313980c9 | 442 | if (ep_stat & UDC_FIFO_FULL) |
1da177e4 LT |
443 | avail = ep->ep.maxpacket; |
444 | else { | |
f35ae634 | 445 | avail = omap_readw(UDC_RXFSTAT); |
1da177e4 LT |
446 | ep->fnf = ep->double_buf; |
447 | } | |
448 | count = read_packet(buf, req, avail); | |
449 | ||
450 | /* partial packet reads may not be errors */ | |
451 | if (count < ep->ep.maxpacket) { | |
452 | is_last = 1; | |
453 | /* overflowed this request? flush extra data */ | |
454 | if (count != avail) { | |
455 | req->req.status = -EOVERFLOW; | |
456 | avail -= count; | |
457 | while (avail--) | |
f35ae634 | 458 | omap_readw(UDC_DATA); |
1da177e4 LT |
459 | } |
460 | } else if (req->req.length == req->req.actual) | |
461 | is_last = 1; | |
462 | else | |
463 | is_last = 0; | |
464 | ||
465 | if (!ep->bEndpointAddress) | |
466 | break; | |
467 | if (is_last) | |
468 | done(ep, req, 0); | |
469 | break; | |
470 | } | |
471 | return is_last; | |
472 | } | |
473 | ||
474 | /*-------------------------------------------------------------------------*/ | |
475 | ||
476 | static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) | |
477 | { | |
478 | dma_addr_t end; | |
479 | ||
480 | /* IN-DMA needs this on fault/cancel paths, so 15xx misreports | |
481 | * the last transfer's bytecount by more than a FIFO's worth. | |
482 | */ | |
483 | if (cpu_is_omap15xx()) | |
484 | return 0; | |
485 | ||
0499bdeb | 486 | end = omap_get_dma_src_pos(ep->lch); |
1da177e4 LT |
487 | if (end == ep->dma_counter) |
488 | return 0; | |
489 | ||
490 | end |= start & (0xffff << 16); | |
491 | if (end < start) | |
492 | end += 0x10000; | |
493 | return end - start; | |
494 | } | |
495 | ||
1da177e4 LT |
496 | static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) |
497 | { | |
498 | dma_addr_t end; | |
499 | ||
0499bdeb | 500 | end = omap_get_dma_dst_pos(ep->lch); |
1da177e4 LT |
501 | if (end == ep->dma_counter) |
502 | return 0; | |
503 | ||
504 | end |= start & (0xffff << 16); | |
505 | if (cpu_is_omap15xx()) | |
506 | end++; | |
507 | if (end < start) | |
508 | end += 0x10000; | |
509 | return end - start; | |
510 | } | |
511 | ||
512 | ||
513 | /* Each USB transfer request using DMA maps to one or more DMA transfers. | |
514 | * When DMA completion isn't request completion, the UDC continues with | |
515 | * the next DMA transfer for that USB transfer. | |
516 | */ | |
517 | ||
518 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | |
519 | { | |
f35ae634 | 520 | u16 txdma_ctrl, w; |
1da177e4 LT |
521 | unsigned length = req->req.length - req->req.actual; |
522 | const int sync_mode = cpu_is_omap15xx() | |
523 | ? OMAP_DMA_SYNC_FRAME | |
524 | : OMAP_DMA_SYNC_ELEMENT; | |
527ea73e KP |
525 | int dma_trigger = 0; |
526 | ||
1da177e4 | 527 | /* measure length in either bytes or packets */ |
65111084 | 528 | if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC) |
1da177e4 LT |
529 | || (cpu_is_omap15xx() && length < ep->maxpacket)) { |
530 | txdma_ctrl = UDC_TXN_EOT | length; | |
531 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, | |
527ea73e | 532 | length, 1, sync_mode, dma_trigger, 0); |
1da177e4 LT |
533 | } else { |
534 | length = min(length / ep->maxpacket, | |
535 | (unsigned) UDC_TXN_TSC + 1); | |
e6a6e472 | 536 | txdma_ctrl = length; |
65111084 | 537 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, |
e6a6e472 | 538 | ep->ep.maxpacket >> 1, length, sync_mode, |
527ea73e | 539 | dma_trigger, 0); |
1da177e4 LT |
540 | length *= ep->maxpacket; |
541 | } | |
542 | omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, | |
e6a6e472 DB |
543 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, |
544 | 0, 0); | |
1da177e4 LT |
545 | |
546 | omap_start_dma(ep->lch); | |
0499bdeb | 547 | ep->dma_counter = omap_get_dma_src_pos(ep->lch); |
f35ae634 TL |
548 | w = omap_readw(UDC_DMA_IRQ_EN); |
549 | w |= UDC_TX_DONE_IE(ep->dma_channel); | |
550 | omap_writew(w, UDC_DMA_IRQ_EN); | |
551 | omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); | |
1da177e4 LT |
552 | req->dma_bytes = length; |
553 | } | |
554 | ||
555 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | |
556 | { | |
f35ae634 TL |
557 | u16 w; |
558 | ||
1da177e4 LT |
559 | if (status == 0) { |
560 | req->req.actual += req->dma_bytes; | |
561 | ||
562 | /* return if this request needs to send data or zlp */ | |
563 | if (req->req.actual < req->req.length) | |
564 | return; | |
565 | if (req->req.zero | |
566 | && req->dma_bytes != 0 | |
567 | && (req->req.actual % ep->maxpacket) == 0) | |
568 | return; | |
569 | } else | |
570 | req->req.actual += dma_src_len(ep, req->req.dma | |
571 | + req->req.actual); | |
572 | ||
573 | /* tx completion */ | |
574 | omap_stop_dma(ep->lch); | |
f35ae634 TL |
575 | w = omap_readw(UDC_DMA_IRQ_EN); |
576 | w &= ~UDC_TX_DONE_IE(ep->dma_channel); | |
577 | omap_writew(w, UDC_DMA_IRQ_EN); | |
1da177e4 LT |
578 | done(ep, req, status); |
579 | } | |
580 | ||
581 | static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |
582 | { | |
527ea73e KP |
583 | unsigned packets = req->req.length - req->req.actual; |
584 | int dma_trigger = 0; | |
f35ae634 | 585 | u16 w; |
527ea73e | 586 | |
ae372571 TL |
587 | /* set up this DMA transfer, enable the fifo, start */ |
588 | packets /= ep->ep.maxpacket; | |
589 | packets = min(packets, (unsigned)UDC_RXN_TC + 1); | |
590 | req->dma_bytes = packets * ep->ep.maxpacket; | |
591 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, | |
592 | ep->ep.maxpacket >> 1, packets, | |
593 | OMAP_DMA_SYNC_ELEMENT, | |
594 | dma_trigger, 0); | |
1da177e4 | 595 | omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, |
e6a6e472 DB |
596 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, |
597 | 0, 0); | |
0499bdeb | 598 | ep->dma_counter = omap_get_dma_dst_pos(ep->lch); |
1da177e4 | 599 | |
f35ae634 TL |
600 | omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); |
601 | w = omap_readw(UDC_DMA_IRQ_EN); | |
602 | w |= UDC_RX_EOT_IE(ep->dma_channel); | |
603 | omap_writew(w, UDC_DMA_IRQ_EN); | |
604 | omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); | |
605 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 LT |
606 | |
607 | omap_start_dma(ep->lch); | |
608 | } | |
609 | ||
610 | static void | |
cb97c5c9 | 611 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) |
1da177e4 | 612 | { |
f35ae634 | 613 | u16 count, w; |
1da177e4 LT |
614 | |
615 | if (status == 0) | |
616 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); | |
617 | count = dma_dest_len(ep, req->req.dma + req->req.actual); | |
618 | count += req->req.actual; | |
cb97c5c9 DB |
619 | if (one) |
620 | count--; | |
1da177e4 LT |
621 | if (count <= req->req.length) |
622 | req->req.actual = count; | |
623 | ||
624 | if (count != req->dma_bytes || status) | |
625 | omap_stop_dma(ep->lch); | |
626 | ||
627 | /* if this wasn't short, request may need another transfer */ | |
628 | else if (req->req.actual < req->req.length) | |
629 | return; | |
630 | ||
631 | /* rx completion */ | |
f35ae634 TL |
632 | w = omap_readw(UDC_DMA_IRQ_EN); |
633 | w &= ~UDC_RX_EOT_IE(ep->dma_channel); | |
634 | omap_writew(w, UDC_DMA_IRQ_EN); | |
1da177e4 LT |
635 | done(ep, req, status); |
636 | } | |
637 | ||
638 | static void dma_irq(struct omap_udc *udc, u16 irq_src) | |
639 | { | |
f35ae634 | 640 | u16 dman_stat = omap_readw(UDC_DMAN_STAT); |
1da177e4 LT |
641 | struct omap_ep *ep; |
642 | struct omap_req *req; | |
643 | ||
644 | /* IN dma: tx to host */ | |
645 | if (irq_src & UDC_TXN_DONE) { | |
646 | ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)]; | |
647 | ep->irqs++; | |
648 | /* can see TXN_DONE after dma abort */ | |
649 | if (!list_empty(&ep->queue)) { | |
650 | req = container_of(ep->queue.next, | |
651 | struct omap_req, queue); | |
652 | finish_in_dma(ep, req, 0); | |
653 | } | |
f35ae634 | 654 | omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); |
1da177e4 | 655 | |
80dd1358 | 656 | if (!list_empty(&ep->queue)) { |
1da177e4 LT |
657 | req = container_of(ep->queue.next, |
658 | struct omap_req, queue); | |
659 | next_in_dma(ep, req); | |
660 | } | |
661 | } | |
662 | ||
663 | /* OUT dma: rx from host */ | |
664 | if (irq_src & UDC_RXN_EOT) { | |
665 | ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; | |
666 | ep->irqs++; | |
667 | /* can see RXN_EOT after dma abort */ | |
668 | if (!list_empty(&ep->queue)) { | |
669 | req = container_of(ep->queue.next, | |
670 | struct omap_req, queue); | |
cb97c5c9 | 671 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); |
1da177e4 | 672 | } |
f35ae634 | 673 | omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); |
1da177e4 | 674 | |
80dd1358 | 675 | if (!list_empty(&ep->queue)) { |
1da177e4 LT |
676 | req = container_of(ep->queue.next, |
677 | struct omap_req, queue); | |
678 | next_out_dma(ep, req); | |
679 | } | |
680 | } | |
681 | ||
682 | if (irq_src & UDC_RXN_CNT) { | |
683 | ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; | |
684 | ep->irqs++; | |
685 | /* omap15xx does this unasked... */ | |
686 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); | |
f35ae634 | 687 | omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); |
1da177e4 LT |
688 | } |
689 | } | |
690 | ||
691 | static void dma_error(int lch, u16 ch_status, void *data) | |
692 | { | |
693 | struct omap_ep *ep = data; | |
694 | ||
695 | /* if ch_status & OMAP_DMA_DROP_IRQ ... */ | |
7ff879db | 696 | /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */ |
1da177e4 LT |
697 | ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); |
698 | ||
699 | /* complete current transfer ... */ | |
700 | } | |
701 | ||
702 | static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |
703 | { | |
704 | u16 reg; | |
705 | int status, restart, is_in; | |
527ea73e | 706 | int dma_channel; |
1da177e4 LT |
707 | |
708 | is_in = ep->bEndpointAddress & USB_DIR_IN; | |
709 | if (is_in) | |
f35ae634 | 710 | reg = omap_readw(UDC_TXDMA_CFG); |
1da177e4 | 711 | else |
f35ae634 | 712 | reg = omap_readw(UDC_RXDMA_CFG); |
65111084 | 713 | reg |= UDC_DMA_REQ; /* "pulse" activated */ |
1da177e4 LT |
714 | |
715 | ep->dma_channel = 0; | |
716 | ep->lch = -1; | |
717 | if (channel == 0 || channel > 3) { | |
718 | if ((reg & 0x0f00) == 0) | |
719 | channel = 3; | |
720 | else if ((reg & 0x00f0) == 0) | |
721 | channel = 2; | |
722 | else if ((reg & 0x000f) == 0) /* preferred for ISO */ | |
723 | channel = 1; | |
724 | else { | |
725 | status = -EMLINK; | |
726 | goto just_restart; | |
727 | } | |
728 | } | |
729 | reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); | |
730 | ep->dma_channel = channel; | |
731 | ||
732 | if (is_in) { | |
ae372571 | 733 | dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel; |
527ea73e | 734 | status = omap_request_dma(dma_channel, |
1da177e4 LT |
735 | ep->ep.name, dma_error, ep, &ep->lch); |
736 | if (status == 0) { | |
f35ae634 | 737 | omap_writew(reg, UDC_TXDMA_CFG); |
527ea73e | 738 | /* EMIFF or SDRC */ |
65111084 DB |
739 | omap_set_dma_src_burst_mode(ep->lch, |
740 | OMAP_DMA_DATA_BURST_4); | |
741 | omap_set_dma_src_data_pack(ep->lch, 1); | |
742 | /* TIPB */ | |
1da177e4 LT |
743 | omap_set_dma_dest_params(ep->lch, |
744 | OMAP_DMA_PORT_TIPB, | |
745 | OMAP_DMA_AMODE_CONSTANT, | |
c3e3208e | 746 | UDC_DATA_DMA, |
e6a6e472 | 747 | 0, 0); |
1da177e4 LT |
748 | } |
749 | } else { | |
ae372571 | 750 | dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel; |
527ea73e | 751 | status = omap_request_dma(dma_channel, |
1da177e4 LT |
752 | ep->ep.name, dma_error, ep, &ep->lch); |
753 | if (status == 0) { | |
f35ae634 | 754 | omap_writew(reg, UDC_RXDMA_CFG); |
65111084 | 755 | /* TIPB */ |
1da177e4 LT |
756 | omap_set_dma_src_params(ep->lch, |
757 | OMAP_DMA_PORT_TIPB, | |
758 | OMAP_DMA_AMODE_CONSTANT, | |
c3e3208e | 759 | UDC_DATA_DMA, |
e6a6e472 | 760 | 0, 0); |
527ea73e | 761 | /* EMIFF or SDRC */ |
65111084 DB |
762 | omap_set_dma_dest_burst_mode(ep->lch, |
763 | OMAP_DMA_DATA_BURST_4); | |
764 | omap_set_dma_dest_data_pack(ep->lch, 1); | |
1da177e4 LT |
765 | } |
766 | } | |
767 | if (status) | |
768 | ep->dma_channel = 0; | |
769 | else { | |
770 | ep->has_dma = 1; | |
771 | omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ); | |
772 | ||
773 | /* channel type P: hw synch (fifo) */ | |
ae372571 | 774 | if (!cpu_is_omap15xx()) |
0499bdeb | 775 | omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P); |
1da177e4 LT |
776 | } |
777 | ||
778 | just_restart: | |
779 | /* restart any queue, even if the claim failed */ | |
780 | restart = !ep->stopped && !list_empty(&ep->queue); | |
781 | ||
782 | if (status) | |
783 | DBG("%s no dma channel: %d%s\n", ep->ep.name, status, | |
784 | restart ? " (restart)" : ""); | |
785 | else | |
786 | DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name, | |
787 | is_in ? 't' : 'r', | |
788 | ep->dma_channel - 1, ep->lch, | |
789 | restart ? " (restart)" : ""); | |
790 | ||
791 | if (restart) { | |
792 | struct omap_req *req; | |
793 | req = container_of(ep->queue.next, struct omap_req, queue); | |
794 | if (ep->has_dma) | |
795 | (is_in ? next_in_dma : next_out_dma)(ep, req); | |
796 | else { | |
797 | use_ep(ep, UDC_EP_SEL); | |
798 | (is_in ? write_fifo : read_fifo)(ep, req); | |
799 | deselect_ep(); | |
800 | if (!is_in) { | |
f35ae634 | 801 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
802 | ep->ackwait = 1 + ep->double_buf; |
803 | } | |
804 | /* IN: 6 wait states before it'll tx */ | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
809 | static void dma_channel_release(struct omap_ep *ep) | |
810 | { | |
811 | int shift = 4 * (ep->dma_channel - 1); | |
812 | u16 mask = 0x0f << shift; | |
813 | struct omap_req *req; | |
814 | int active; | |
815 | ||
816 | /* abort any active usb transfer request */ | |
817 | if (!list_empty(&ep->queue)) | |
818 | req = container_of(ep->queue.next, struct omap_req, queue); | |
819 | else | |
313980c9 | 820 | req = NULL; |
1da177e4 | 821 | |
0499bdeb | 822 | active = omap_get_dma_active_status(ep->lch); |
1da177e4 LT |
823 | |
824 | DBG("%s release %s %cxdma%d %p\n", ep->ep.name, | |
825 | active ? "active" : "idle", | |
826 | (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', | |
827 | ep->dma_channel - 1, req); | |
828 | ||
65111084 DB |
829 | /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before |
830 | * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them. | |
831 | */ | |
832 | ||
1da177e4 LT |
833 | /* wait till current packet DMA finishes, and fifo empties */ |
834 | if (ep->bEndpointAddress & USB_DIR_IN) { | |
f35ae634 TL |
835 | omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
836 | UDC_TXDMA_CFG); | |
1da177e4 LT |
837 | |
838 | if (req) { | |
839 | finish_in_dma(ep, req, -ECONNRESET); | |
840 | ||
841 | /* clear FIFO; hosts probably won't empty it */ | |
842 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 843 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1da177e4 LT |
844 | deselect_ep(); |
845 | } | |
f35ae634 | 846 | while (omap_readw(UDC_TXDMA_CFG) & mask) |
1da177e4 LT |
847 | udelay(10); |
848 | } else { | |
f35ae634 TL |
849 | omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
850 | UDC_RXDMA_CFG); | |
1da177e4 LT |
851 | |
852 | /* dma empties the fifo */ | |
f35ae634 | 853 | while (omap_readw(UDC_RXDMA_CFG) & mask) |
1da177e4 LT |
854 | udelay(10); |
855 | if (req) | |
cb97c5c9 | 856 | finish_out_dma(ep, req, -ECONNRESET, 0); |
1da177e4 LT |
857 | } |
858 | omap_free_dma(ep->lch); | |
859 | ep->dma_channel = 0; | |
860 | ep->lch = -1; | |
861 | /* has_dma still set, till endpoint is fully quiesced */ | |
862 | } | |
863 | ||
864 | ||
865 | /*-------------------------------------------------------------------------*/ | |
866 | ||
867 | static int | |
55016f10 | 868 | omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
1da177e4 LT |
869 | { |
870 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
871 | struct omap_req *req = container_of(_req, struct omap_req, req); | |
872 | struct omap_udc *udc; | |
873 | unsigned long flags; | |
874 | int is_iso = 0; | |
875 | ||
876 | /* catch various bogus parameters */ | |
877 | if (!_req || !req->req.complete || !req->req.buf | |
878 | || !list_empty(&req->queue)) { | |
441b62c1 | 879 | DBG("%s, bad params\n", __func__); |
1da177e4 LT |
880 | return -EINVAL; |
881 | } | |
f8bdae06 | 882 | if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) { |
441b62c1 | 883 | DBG("%s, bad ep\n", __func__); |
1da177e4 LT |
884 | return -EINVAL; |
885 | } | |
886 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
887 | if (req->req.length > ep->ep.maxpacket) | |
888 | return -EMSGSIZE; | |
889 | is_iso = 1; | |
890 | } | |
891 | ||
892 | /* this isn't bogus, but OMAP DMA isn't the only hardware to | |
893 | * have a hard time with partial packet reads... reject it. | |
894 | */ | |
895 | if (use_dma | |
896 | && ep->has_dma | |
897 | && ep->bEndpointAddress != 0 | |
898 | && (ep->bEndpointAddress & USB_DIR_IN) == 0 | |
899 | && (req->req.length % ep->ep.maxpacket) != 0) { | |
441b62c1 | 900 | DBG("%s, no partial packet OUT reads\n", __func__); |
1da177e4 LT |
901 | return -EMSGSIZE; |
902 | } | |
903 | ||
904 | udc = ep->udc; | |
905 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) | |
906 | return -ESHUTDOWN; | |
907 | ||
dd8e9381 FB |
908 | if (use_dma && ep->has_dma) |
909 | usb_gadget_map_request(&udc->gadget, &req->req, | |
910 | (ep->bEndpointAddress & USB_DIR_IN)); | |
1da177e4 LT |
911 | |
912 | VDBG("%s queue req %p, len %d buf %p\n", | |
913 | ep->ep.name, _req, _req->length, _req->buf); | |
914 | ||
915 | spin_lock_irqsave(&udc->lock, flags); | |
916 | ||
917 | req->req.status = -EINPROGRESS; | |
918 | req->req.actual = 0; | |
919 | ||
920 | /* maybe kickstart non-iso i/o queues */ | |
f35ae634 TL |
921 | if (is_iso) { |
922 | u16 w; | |
923 | ||
924 | w = omap_readw(UDC_IRQ_EN); | |
925 | w |= UDC_SOF_IE; | |
926 | omap_writew(w, UDC_IRQ_EN); | |
927 | } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | |
1da177e4 LT |
928 | int is_in; |
929 | ||
930 | if (ep->bEndpointAddress == 0) { | |
80dd1358 | 931 | if (!udc->ep0_pending || !list_empty(&ep->queue)) { |
1da177e4 LT |
932 | spin_unlock_irqrestore(&udc->lock, flags); |
933 | return -EL2HLT; | |
934 | } | |
935 | ||
936 | /* empty DATA stage? */ | |
937 | is_in = udc->ep0_in; | |
938 | if (!req->req.length) { | |
939 | ||
940 | /* chip became CONFIGURED or ADDRESSED | |
941 | * earlier; drivers may already have queued | |
942 | * requests to non-control endpoints | |
943 | */ | |
944 | if (udc->ep0_set_config) { | |
f35ae634 | 945 | u16 irq_en = omap_readw(UDC_IRQ_EN); |
1da177e4 LT |
946 | |
947 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; | |
948 | if (!udc->ep0_reset_config) | |
949 | irq_en |= UDC_EPN_RX_IE | |
950 | | UDC_EPN_TX_IE; | |
f35ae634 | 951 | omap_writew(irq_en, UDC_IRQ_EN); |
1da177e4 LT |
952 | } |
953 | ||
313980c9 DB |
954 | /* STATUS for zero length DATA stages is |
955 | * always an IN ... even for IN transfers, | |
dc0d5c1e | 956 | * a weird case which seem to stall OMAP. |
313980c9 | 957 | */ |
80dd1358 FB |
958 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
959 | UDC_EP_NUM); | |
f35ae634 TL |
960 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
961 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
962 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
963 | |
964 | /* cleanup */ | |
965 | udc->ep0_pending = 0; | |
966 | done(ep, req, 0); | |
313980c9 | 967 | req = NULL; |
1da177e4 LT |
968 | |
969 | /* non-empty DATA stage */ | |
970 | } else if (is_in) { | |
80dd1358 FB |
971 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
972 | UDC_EP_NUM); | |
1da177e4 LT |
973 | } else { |
974 | if (udc->ep0_setup) | |
975 | goto irq_wait; | |
f35ae634 | 976 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1da177e4 LT |
977 | } |
978 | } else { | |
979 | is_in = ep->bEndpointAddress & USB_DIR_IN; | |
980 | if (!ep->has_dma) | |
981 | use_ep(ep, UDC_EP_SEL); | |
982 | /* if ISO: SOF IRQs must be enabled/disabled! */ | |
983 | } | |
984 | ||
985 | if (ep->has_dma) | |
986 | (is_in ? next_in_dma : next_out_dma)(ep, req); | |
987 | else if (req) { | |
988 | if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) | |
313980c9 | 989 | req = NULL; |
1da177e4 LT |
990 | deselect_ep(); |
991 | if (!is_in) { | |
f35ae634 | 992 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
993 | ep->ackwait = 1 + ep->double_buf; |
994 | } | |
995 | /* IN: 6 wait states before it'll tx */ | |
996 | } | |
997 | } | |
998 | ||
999 | irq_wait: | |
1000 | /* irq handler advances the queue */ | |
313980c9 | 1001 | if (req != NULL) |
1da177e4 LT |
1002 | list_add_tail(&req->queue, &ep->queue); |
1003 | spin_unlock_irqrestore(&udc->lock, flags); | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
1009 | { | |
1010 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
1011 | struct omap_req *req; | |
1012 | unsigned long flags; | |
1013 | ||
1014 | if (!_ep || !_req) | |
1015 | return -EINVAL; | |
1016 | ||
1017 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1018 | ||
1019 | /* make sure it's actually queued on this endpoint */ | |
80dd1358 | 1020 | list_for_each_entry(req, &ep->queue, queue) { |
1da177e4 LT |
1021 | if (&req->req == _req) |
1022 | break; | |
1023 | } | |
1024 | if (&req->req != _req) { | |
1025 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1026 | return -EINVAL; | |
1027 | } | |
1028 | ||
1029 | if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) { | |
1030 | int channel = ep->dma_channel; | |
1031 | ||
1032 | /* releasing the channel cancels the request, | |
1033 | * reclaiming the channel restarts the queue | |
1034 | */ | |
1035 | dma_channel_release(ep); | |
1036 | dma_channel_claim(ep, channel); | |
e6a6e472 | 1037 | } else |
1da177e4 LT |
1038 | done(ep, req, -ECONNRESET); |
1039 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | /*-------------------------------------------------------------------------*/ | |
1044 | ||
1045 | static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |
1046 | { | |
1047 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
1048 | unsigned long flags; | |
1049 | int status = -EOPNOTSUPP; | |
1050 | ||
1051 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1052 | ||
1053 | /* just use protocol stalls for ep0; real halts are annoying */ | |
1054 | if (ep->bEndpointAddress == 0) { | |
1055 | if (!ep->udc->ep0_pending) | |
1056 | status = -EINVAL; | |
1057 | else if (value) { | |
1058 | if (ep->udc->ep0_set_config) { | |
b6c63937 | 1059 | WARNING("error changing config?\n"); |
f35ae634 | 1060 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1061 | } |
f35ae634 | 1062 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1063 | ep->udc->ep0_pending = 0; |
1064 | status = 0; | |
1065 | } else /* NOP */ | |
1066 | status = 0; | |
1067 | ||
1068 | /* otherwise, all active non-ISO endpoints can halt */ | |
f8bdae06 | 1069 | } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) { |
1da177e4 LT |
1070 | |
1071 | /* IN endpoints must already be idle */ | |
1072 | if ((ep->bEndpointAddress & USB_DIR_IN) | |
e6a6e472 | 1073 | && !list_empty(&ep->queue)) { |
1da177e4 LT |
1074 | status = -EAGAIN; |
1075 | goto done; | |
1076 | } | |
1077 | ||
1078 | if (value) { | |
1079 | int channel; | |
1080 | ||
1081 | if (use_dma && ep->dma_channel | |
1082 | && !list_empty(&ep->queue)) { | |
1083 | channel = ep->dma_channel; | |
1084 | dma_channel_release(ep); | |
1085 | } else | |
1086 | channel = 0; | |
1087 | ||
1088 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 TL |
1089 | if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { |
1090 | omap_writew(UDC_SET_HALT, UDC_CTRL); | |
1da177e4 LT |
1091 | status = 0; |
1092 | } else | |
1093 | status = -EAGAIN; | |
1094 | deselect_ep(); | |
1095 | ||
1096 | if (channel) | |
1097 | dma_channel_claim(ep, channel); | |
1098 | } else { | |
1099 | use_ep(ep, 0); | |
f35ae634 | 1100 | omap_writew(ep->udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
1101 | ep->ackwait = 0; |
1102 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 1103 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1104 | ep->ackwait = 1 + ep->double_buf; |
1105 | } | |
1106 | } | |
1107 | } | |
1108 | done: | |
1109 | VDBG("%s %s halt stat %d\n", ep->ep.name, | |
1110 | value ? "set" : "clear", status); | |
1111 | ||
1112 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1113 | return status; | |
1114 | } | |
1115 | ||
1116 | static struct usb_ep_ops omap_ep_ops = { | |
1117 | .enable = omap_ep_enable, | |
1118 | .disable = omap_ep_disable, | |
1119 | ||
1120 | .alloc_request = omap_alloc_request, | |
1121 | .free_request = omap_free_request, | |
1122 | ||
1da177e4 LT |
1123 | .queue = omap_ep_queue, |
1124 | .dequeue = omap_ep_dequeue, | |
1125 | ||
1126 | .set_halt = omap_ep_set_halt, | |
80dd1358 FB |
1127 | /* fifo_status ... report bytes in fifo */ |
1128 | /* fifo_flush ... flush fifo */ | |
1da177e4 LT |
1129 | }; |
1130 | ||
1131 | /*-------------------------------------------------------------------------*/ | |
1132 | ||
1133 | static int omap_get_frame(struct usb_gadget *gadget) | |
1134 | { | |
f35ae634 | 1135 | u16 sof = omap_readw(UDC_SOF); |
1da177e4 LT |
1136 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; |
1137 | } | |
1138 | ||
1139 | static int omap_wakeup(struct usb_gadget *gadget) | |
1140 | { | |
1141 | struct omap_udc *udc; | |
1142 | unsigned long flags; | |
1143 | int retval = -EHOSTUNREACH; | |
1144 | ||
1145 | udc = container_of(gadget, struct omap_udc, gadget); | |
1146 | ||
1147 | spin_lock_irqsave(&udc->lock, flags); | |
1148 | if (udc->devstat & UDC_SUS) { | |
1149 | /* NOTE: OTG spec erratum says that OTG devices may | |
1150 | * issue wakeups without host enable. | |
1151 | */ | |
1152 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { | |
1153 | DBG("remote wakeup...\n"); | |
f35ae634 | 1154 | omap_writew(UDC_RMT_WKP, UDC_SYSCON2); |
1da177e4 LT |
1155 | retval = 0; |
1156 | } | |
1157 | ||
1158 | /* NOTE: non-OTG systems may use SRP TOO... */ | |
1159 | } else if (!(udc->devstat & UDC_ATT)) { | |
ded017ee | 1160 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
6e13c650 | 1161 | retval = otg_start_srp(udc->transceiver->otg); |
1da177e4 LT |
1162 | } |
1163 | spin_unlock_irqrestore(&udc->lock, flags); | |
1164 | ||
1165 | return retval; | |
1166 | } | |
1167 | ||
1168 | static int | |
1169 | omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) | |
1170 | { | |
1171 | struct omap_udc *udc; | |
1172 | unsigned long flags; | |
1173 | u16 syscon1; | |
1174 | ||
1175 | udc = container_of(gadget, struct omap_udc, gadget); | |
1176 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 | 1177 | syscon1 = omap_readw(UDC_SYSCON1); |
1da177e4 LT |
1178 | if (is_selfpowered) |
1179 | syscon1 |= UDC_SELF_PWR; | |
1180 | else | |
1181 | syscon1 &= ~UDC_SELF_PWR; | |
f35ae634 | 1182 | omap_writew(syscon1, UDC_SYSCON1); |
1da177e4 LT |
1183 | spin_unlock_irqrestore(&udc->lock, flags); |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | static int can_pullup(struct omap_udc *udc) | |
1189 | { | |
1190 | return udc->driver && udc->softconnect && udc->vbus_active; | |
1191 | } | |
1192 | ||
1193 | static void pullup_enable(struct omap_udc *udc) | |
1194 | { | |
f35ae634 TL |
1195 | u16 w; |
1196 | ||
1197 | w = omap_readw(UDC_SYSCON1); | |
1198 | w |= UDC_PULLUP_EN; | |
1199 | omap_writew(w, UDC_SYSCON1); | |
1200 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | |
1201 | u32 l; | |
1202 | ||
1203 | l = omap_readl(OTG_CTRL); | |
1204 | l |= OTG_BSESSVLD; | |
1205 | omap_writel(l, OTG_CTRL); | |
1206 | } | |
1207 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | |
1da177e4 LT |
1208 | } |
1209 | ||
1210 | static void pullup_disable(struct omap_udc *udc) | |
1211 | { | |
f35ae634 TL |
1212 | u16 w; |
1213 | ||
1214 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | |
1215 | u32 l; | |
1216 | ||
1217 | l = omap_readl(OTG_CTRL); | |
1218 | l &= ~OTG_BSESSVLD; | |
1219 | omap_writel(l, OTG_CTRL); | |
1220 | } | |
1221 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | |
1222 | w = omap_readw(UDC_SYSCON1); | |
1223 | w &= ~UDC_PULLUP_EN; | |
1224 | omap_writew(w, UDC_SYSCON1); | |
1da177e4 LT |
1225 | } |
1226 | ||
e6a6e472 DB |
1227 | static struct omap_udc *udc; |
1228 | ||
1229 | static void omap_udc_enable_clock(int enable) | |
1230 | { | |
1231 | if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL) | |
1232 | return; | |
1233 | ||
1234 | if (enable) { | |
1235 | clk_enable(udc->dc_clk); | |
1236 | clk_enable(udc->hhc_clk); | |
1237 | udelay(100); | |
1238 | } else { | |
1239 | clk_disable(udc->hhc_clk); | |
1240 | clk_disable(udc->dc_clk); | |
1241 | } | |
1242 | } | |
1243 | ||
1da177e4 LT |
1244 | /* |
1245 | * Called by whatever detects VBUS sessions: external transceiver | |
1246 | * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock. | |
1247 | */ | |
1248 | static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |
1249 | { | |
1250 | struct omap_udc *udc; | |
1251 | unsigned long flags; | |
f35ae634 | 1252 | u32 l; |
1da177e4 LT |
1253 | |
1254 | udc = container_of(gadget, struct omap_udc, gadget); | |
1255 | spin_lock_irqsave(&udc->lock, flags); | |
1256 | VDBG("VBUS %s\n", is_active ? "on" : "off"); | |
1257 | udc->vbus_active = (is_active != 0); | |
1258 | if (cpu_is_omap15xx()) { | |
1259 | /* "software" detect, ignored if !VBUS_MODE_1510 */ | |
f35ae634 | 1260 | l = omap_readl(FUNC_MUX_CTRL_0); |
1da177e4 | 1261 | if (is_active) |
f35ae634 | 1262 | l |= VBUS_CTRL_1510; |
1da177e4 | 1263 | else |
f35ae634 TL |
1264 | l &= ~VBUS_CTRL_1510; |
1265 | omap_writel(l, FUNC_MUX_CTRL_0); | |
1da177e4 | 1266 | } |
e6a6e472 DB |
1267 | if (udc->dc_clk != NULL && is_active) { |
1268 | if (!udc->clk_requested) { | |
1269 | omap_udc_enable_clock(1); | |
1270 | udc->clk_requested = 1; | |
1271 | } | |
1272 | } | |
1da177e4 LT |
1273 | if (can_pullup(udc)) |
1274 | pullup_enable(udc); | |
1275 | else | |
1276 | pullup_disable(udc); | |
e6a6e472 DB |
1277 | if (udc->dc_clk != NULL && !is_active) { |
1278 | if (udc->clk_requested) { | |
1279 | omap_udc_enable_clock(0); | |
1280 | udc->clk_requested = 0; | |
1281 | } | |
1282 | } | |
1da177e4 LT |
1283 | spin_unlock_irqrestore(&udc->lock, flags); |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1288 | { | |
1289 | struct omap_udc *udc; | |
1290 | ||
1291 | udc = container_of(gadget, struct omap_udc, gadget); | |
ded017ee | 1292 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 | 1293 | return usb_phy_set_power(udc->transceiver, mA); |
1da177e4 LT |
1294 | return -EOPNOTSUPP; |
1295 | } | |
1296 | ||
1297 | static int omap_pullup(struct usb_gadget *gadget, int is_on) | |
1298 | { | |
1299 | struct omap_udc *udc; | |
1300 | unsigned long flags; | |
1301 | ||
1302 | udc = container_of(gadget, struct omap_udc, gadget); | |
1303 | spin_lock_irqsave(&udc->lock, flags); | |
1304 | udc->softconnect = (is_on != 0); | |
1305 | if (can_pullup(udc)) | |
1306 | pullup_enable(udc); | |
1307 | else | |
1308 | pullup_disable(udc); | |
1309 | spin_unlock_irqrestore(&udc->lock, flags); | |
1310 | return 0; | |
1311 | } | |
1312 | ||
1bf0cf60 | 1313 | static int omap_udc_start(struct usb_gadget *g, |
518868c8 | 1314 | struct usb_gadget_driver *driver); |
1bf0cf60 FB |
1315 | static int omap_udc_stop(struct usb_gadget *g, |
1316 | struct usb_gadget_driver *driver); | |
0f91349b | 1317 | |
eeef4587 | 1318 | static const struct usb_gadget_ops omap_gadget_ops = { |
1da177e4 LT |
1319 | .get_frame = omap_get_frame, |
1320 | .wakeup = omap_wakeup, | |
1321 | .set_selfpowered = omap_set_selfpowered, | |
1322 | .vbus_session = omap_vbus_session, | |
1323 | .vbus_draw = omap_vbus_draw, | |
1324 | .pullup = omap_pullup, | |
1bf0cf60 FB |
1325 | .udc_start = omap_udc_start, |
1326 | .udc_stop = omap_udc_stop, | |
1da177e4 LT |
1327 | }; |
1328 | ||
1329 | /*-------------------------------------------------------------------------*/ | |
1330 | ||
1331 | /* dequeue ALL requests; caller holds udc->lock */ | |
1332 | static void nuke(struct omap_ep *ep, int status) | |
1333 | { | |
1334 | struct omap_req *req; | |
1335 | ||
1336 | ep->stopped = 1; | |
1337 | ||
1338 | if (use_dma && ep->dma_channel) | |
1339 | dma_channel_release(ep); | |
1340 | ||
1341 | use_ep(ep, 0); | |
f35ae634 | 1342 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1da177e4 | 1343 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) |
f35ae634 | 1344 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
1345 | |
1346 | while (!list_empty(&ep->queue)) { | |
1347 | req = list_entry(ep->queue.next, struct omap_req, queue); | |
1348 | done(ep, req, status); | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | /* caller holds udc->lock */ | |
1353 | static void udc_quiesce(struct omap_udc *udc) | |
1354 | { | |
1355 | struct omap_ep *ep; | |
1356 | ||
1357 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1358 | nuke(&udc->ep[0], -ESHUTDOWN); | |
80dd1358 | 1359 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) |
1da177e4 LT |
1360 | nuke(ep, -ESHUTDOWN); |
1361 | } | |
1362 | ||
1363 | /*-------------------------------------------------------------------------*/ | |
1364 | ||
1365 | static void update_otg(struct omap_udc *udc) | |
1366 | { | |
1367 | u16 devstat; | |
1368 | ||
9cfbba73 | 1369 | if (!gadget_is_otg(&udc->gadget)) |
1da177e4 LT |
1370 | return; |
1371 | ||
f35ae634 TL |
1372 | if (omap_readl(OTG_CTRL) & OTG_ID) |
1373 | devstat = omap_readw(UDC_DEVSTAT); | |
1da177e4 LT |
1374 | else |
1375 | devstat = 0; | |
1376 | ||
1377 | udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE); | |
1378 | udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT); | |
1379 | udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT); | |
1380 | ||
1381 | /* Enable HNP early, avoiding races on suspend irq path. | |
1382 | * ASSUMES OTG state machine B_BUS_REQ input is true. | |
1383 | */ | |
f35ae634 TL |
1384 | if (udc->gadget.b_hnp_enable) { |
1385 | u32 l; | |
1386 | ||
1387 | l = omap_readl(OTG_CTRL); | |
1388 | l |= OTG_B_HNPEN | OTG_B_BUSREQ; | |
1389 | l &= ~OTG_PULLUP; | |
1390 | omap_writel(l, OTG_CTRL); | |
1391 | } | |
1da177e4 LT |
1392 | } |
1393 | ||
1394 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |
1395 | { | |
1396 | struct omap_ep *ep0 = &udc->ep[0]; | |
313980c9 | 1397 | struct omap_req *req = NULL; |
1da177e4 LT |
1398 | |
1399 | ep0->irqs++; | |
1400 | ||
1401 | /* Clear any pending requests and then scrub any rx/tx state | |
1402 | * before starting to handle the SETUP request. | |
1403 | */ | |
1404 | if (irq_src & UDC_SETUP) { | |
1405 | u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX); | |
1406 | ||
1407 | nuke(ep0, 0); | |
1408 | if (ack) { | |
f35ae634 | 1409 | omap_writew(ack, UDC_IRQ_SRC); |
1da177e4 LT |
1410 | irq_src = UDC_SETUP; |
1411 | } | |
1412 | } | |
1413 | ||
e6a6e472 | 1414 | /* IN/OUT packets mean we're in the DATA or STATUS stage. |
1da177e4 LT |
1415 | * This driver uses only uses protocol stalls (ep0 never halts), |
1416 | * and if we got this far the gadget driver already had a | |
1417 | * chance to stall. Tries to be forgiving of host oddities. | |
1418 | * | |
1419 | * NOTE: the last chance gadget drivers have to stall control | |
1420 | * requests is during their request completion callback. | |
1421 | */ | |
1422 | if (!list_empty(&ep0->queue)) | |
1423 | req = container_of(ep0->queue.next, struct omap_req, queue); | |
1424 | ||
1425 | /* IN == TX to host */ | |
1426 | if (irq_src & UDC_EP0_TX) { | |
1427 | int stat; | |
1428 | ||
f35ae634 TL |
1429 | omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); |
1430 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); | |
1431 | stat = omap_readw(UDC_STAT_FLG); | |
1da177e4 LT |
1432 | if (stat & UDC_ACK) { |
1433 | if (udc->ep0_in) { | |
1434 | /* write next IN packet from response, | |
1435 | * or set up the status stage. | |
1436 | */ | |
1437 | if (req) | |
1438 | stat = write_fifo(ep0, req); | |
f35ae634 | 1439 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 | 1440 | if (!req && udc->ep0_pending) { |
f35ae634 TL |
1441 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1442 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1443 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1444 | omap_writew(0, UDC_EP_NUM); | |
1da177e4 LT |
1445 | udc->ep0_pending = 0; |
1446 | } /* else: 6 wait states before it'll tx */ | |
1447 | } else { | |
1448 | /* ack status stage of OUT transfer */ | |
f35ae634 | 1449 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 LT |
1450 | if (req) |
1451 | done(ep0, req, 0); | |
1452 | } | |
313980c9 | 1453 | req = NULL; |
1da177e4 | 1454 | } else if (stat & UDC_STALL) { |
f35ae634 TL |
1455 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1456 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 | 1457 | } else { |
f35ae634 | 1458 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 LT |
1459 | } |
1460 | } | |
1461 | ||
1462 | /* OUT == RX from host */ | |
1463 | if (irq_src & UDC_EP0_RX) { | |
1464 | int stat; | |
1465 | ||
f35ae634 TL |
1466 | omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); |
1467 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); | |
1468 | stat = omap_readw(UDC_STAT_FLG); | |
1da177e4 LT |
1469 | if (stat & UDC_ACK) { |
1470 | if (!udc->ep0_in) { | |
1471 | stat = 0; | |
1472 | /* read next OUT packet of request, maybe | |
1473 | * reactiviting the fifo; stall on errors. | |
1474 | */ | |
80dd1358 FB |
1475 | stat = read_fifo(ep0, req); |
1476 | if (!req || stat < 0) { | |
f35ae634 | 1477 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1478 | udc->ep0_pending = 0; |
1479 | stat = 0; | |
1480 | } else if (stat == 0) | |
f35ae634 TL |
1481 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1482 | omap_writew(0, UDC_EP_NUM); | |
e6a6e472 | 1483 | |
1da177e4 LT |
1484 | /* activate status stage */ |
1485 | if (stat == 1) { | |
1486 | done(ep0, req, 0); | |
1487 | /* that may have STALLed ep0... */ | |
f35ae634 TL |
1488 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
1489 | UDC_EP_NUM); | |
1490 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1491 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1492 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1493 | udc->ep0_pending = 0; |
1494 | } | |
1495 | } else { | |
1496 | /* ack status stage of IN transfer */ | |
f35ae634 | 1497 | omap_writew(0, UDC_EP_NUM); |
1da177e4 LT |
1498 | if (req) |
1499 | done(ep0, req, 0); | |
1500 | } | |
1501 | } else if (stat & UDC_STALL) { | |
f35ae634 TL |
1502 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1503 | omap_writew(0, UDC_EP_NUM); | |
1da177e4 | 1504 | } else { |
f35ae634 | 1505 | omap_writew(0, UDC_EP_NUM); |
1da177e4 LT |
1506 | } |
1507 | } | |
1508 | ||
1509 | /* SETUP starts all control transfers */ | |
1510 | if (irq_src & UDC_SETUP) { | |
1511 | union u { | |
1512 | u16 word[4]; | |
1513 | struct usb_ctrlrequest r; | |
1514 | } u; | |
1515 | int status = -EINVAL; | |
1516 | struct omap_ep *ep; | |
1517 | ||
1518 | /* read the (latest) SETUP message */ | |
1519 | do { | |
f35ae634 | 1520 | omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); |
1da177e4 | 1521 | /* two bytes at a time */ |
f35ae634 TL |
1522 | u.word[0] = omap_readw(UDC_DATA); |
1523 | u.word[1] = omap_readw(UDC_DATA); | |
1524 | u.word[2] = omap_readw(UDC_DATA); | |
1525 | u.word[3] = omap_readw(UDC_DATA); | |
1526 | omap_writew(0, UDC_EP_NUM); | |
1527 | } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); | |
1da177e4 | 1528 | |
01ee7d70 DB |
1529 | #define w_value le16_to_cpu(u.r.wValue) |
1530 | #define w_index le16_to_cpu(u.r.wIndex) | |
1531 | #define w_length le16_to_cpu(u.r.wLength) | |
65111084 | 1532 | |
1da177e4 LT |
1533 | /* Delegate almost all control requests to the gadget driver, |
1534 | * except for a handful of ch9 status/feature requests that | |
1535 | * hardware doesn't autodecode _and_ the gadget API hides. | |
1536 | */ | |
1537 | udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0; | |
1538 | udc->ep0_set_config = 0; | |
1539 | udc->ep0_pending = 1; | |
1540 | ep0->stopped = 0; | |
1541 | ep0->ackwait = 0; | |
1542 | switch (u.r.bRequest) { | |
1543 | case USB_REQ_SET_CONFIGURATION: | |
1544 | /* udc needs to know when ep != 0 is valid */ | |
1545 | if (u.r.bRequestType != USB_RECIP_DEVICE) | |
1546 | goto delegate; | |
65111084 | 1547 | if (w_length != 0) |
1da177e4 LT |
1548 | goto do_stall; |
1549 | udc->ep0_set_config = 1; | |
65111084 DB |
1550 | udc->ep0_reset_config = (w_value == 0); |
1551 | VDBG("set config %d\n", w_value); | |
1da177e4 LT |
1552 | |
1553 | /* update udc NOW since gadget driver may start | |
1554 | * queueing requests immediately; clear config | |
1555 | * later if it fails the request. | |
1556 | */ | |
1557 | if (udc->ep0_reset_config) | |
f35ae634 | 1558 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1559 | else |
f35ae634 | 1560 | omap_writew(UDC_DEV_CFG, UDC_SYSCON2); |
1da177e4 LT |
1561 | update_otg(udc); |
1562 | goto delegate; | |
1563 | case USB_REQ_CLEAR_FEATURE: | |
1564 | /* clear endpoint halt */ | |
1565 | if (u.r.bRequestType != USB_RECIP_ENDPOINT) | |
1566 | goto delegate; | |
65111084 DB |
1567 | if (w_value != USB_ENDPOINT_HALT |
1568 | || w_length != 0) | |
1da177e4 | 1569 | goto do_stall; |
65111084 | 1570 | ep = &udc->ep[w_index & 0xf]; |
1da177e4 | 1571 | if (ep != ep0) { |
65111084 | 1572 | if (w_index & USB_DIR_IN) |
1da177e4 LT |
1573 | ep += 16; |
1574 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
f8bdae06 | 1575 | || !ep->ep.desc) |
1da177e4 LT |
1576 | goto do_stall; |
1577 | use_ep(ep, 0); | |
f35ae634 | 1578 | omap_writew(udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
1579 | ep->ackwait = 0; |
1580 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 1581 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1582 | ep->ackwait = 1 + ep->double_buf; |
1583 | } | |
313980c9 DB |
1584 | /* NOTE: assumes the host behaves sanely, |
1585 | * only clearing real halts. Else we may | |
1586 | * need to kill pending transfers and then | |
1587 | * restart the queue... very messy for DMA! | |
1588 | */ | |
1da177e4 LT |
1589 | } |
1590 | VDBG("%s halt cleared by host\n", ep->name); | |
1591 | goto ep0out_status_stage; | |
1592 | case USB_REQ_SET_FEATURE: | |
1593 | /* set endpoint halt */ | |
1594 | if (u.r.bRequestType != USB_RECIP_ENDPOINT) | |
1595 | goto delegate; | |
65111084 DB |
1596 | if (w_value != USB_ENDPOINT_HALT |
1597 | || w_length != 0) | |
1da177e4 | 1598 | goto do_stall; |
65111084 DB |
1599 | ep = &udc->ep[w_index & 0xf]; |
1600 | if (w_index & USB_DIR_IN) | |
1da177e4 LT |
1601 | ep += 16; |
1602 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
f8bdae06 | 1603 | || ep == ep0 || !ep->ep.desc) |
1da177e4 LT |
1604 | goto do_stall; |
1605 | if (use_dma && ep->has_dma) { | |
1606 | /* this has rude side-effects (aborts) and | |
1607 | * can't really work if DMA-IN is active | |
1608 | */ | |
80dd1358 | 1609 | DBG("%s host set_halt, NYET\n", ep->name); |
1da177e4 LT |
1610 | goto do_stall; |
1611 | } | |
1612 | use_ep(ep, 0); | |
1613 | /* can't halt if fifo isn't empty... */ | |
f35ae634 TL |
1614 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1615 | omap_writew(UDC_SET_HALT, UDC_CTRL); | |
1da177e4 LT |
1616 | VDBG("%s halted by host\n", ep->name); |
1617 | ep0out_status_stage: | |
1618 | status = 0; | |
f35ae634 TL |
1619 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1620 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1621 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1622 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1623 | udc->ep0_pending = 0; |
1624 | break; | |
1625 | case USB_REQ_GET_STATUS: | |
8a3c1f57 DB |
1626 | /* USB_ENDPOINT_HALT status? */ |
1627 | if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT)) | |
1628 | goto intf_status; | |
1629 | ||
1630 | /* ep0 never stalls */ | |
1631 | if (!(w_index & 0xf)) | |
1632 | goto zero_status; | |
1633 | ||
1634 | /* only active endpoints count */ | |
1635 | ep = &udc->ep[w_index & 0xf]; | |
1636 | if (w_index & USB_DIR_IN) | |
1637 | ep += 16; | |
f8bdae06 | 1638 | if (!ep->ep.desc) |
8a3c1f57 DB |
1639 | goto do_stall; |
1640 | ||
1641 | /* iso never stalls */ | |
1642 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
1643 | goto zero_status; | |
1644 | ||
1645 | /* FIXME don't assume non-halted endpoints!! */ | |
1646 | ERR("%s status, can't report\n", ep->ep.name); | |
1647 | goto do_stall; | |
1648 | ||
1649 | intf_status: | |
1da177e4 LT |
1650 | /* return interface status. if we were pedantic, |
1651 | * we'd detect non-existent interfaces, and stall. | |
1652 | */ | |
1653 | if (u.r.bRequestType | |
1654 | != (USB_DIR_IN|USB_RECIP_INTERFACE)) | |
1655 | goto delegate; | |
8a3c1f57 DB |
1656 | |
1657 | zero_status: | |
1da177e4 | 1658 | /* return two zero bytes */ |
f35ae634 TL |
1659 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1660 | omap_writew(0, UDC_DATA); | |
1661 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1662 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 | 1663 | status = 0; |
65111084 | 1664 | VDBG("GET_STATUS, interface %d\n", w_index); |
1da177e4 LT |
1665 | /* next, status stage */ |
1666 | break; | |
1667 | default: | |
1668 | delegate: | |
1669 | /* activate the ep0out fifo right away */ | |
65111084 | 1670 | if (!udc->ep0_in && w_length) { |
f35ae634 TL |
1671 | omap_writew(0, UDC_EP_NUM); |
1672 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 LT |
1673 | } |
1674 | ||
1675 | /* gadget drivers see class/vendor specific requests, | |
1676 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, | |
1677 | * and more | |
1678 | */ | |
1679 | VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1680 | u.r.bRequestType, u.r.bRequest, | |
65111084 DB |
1681 | w_value, w_index, w_length); |
1682 | ||
1683 | #undef w_value | |
1684 | #undef w_index | |
1685 | #undef w_length | |
1da177e4 LT |
1686 | |
1687 | /* The gadget driver may return an error here, | |
1688 | * causing an immediate protocol stall. | |
1689 | * | |
1690 | * Else it must issue a response, either queueing a | |
1691 | * response buffer for the DATA stage, or halting ep0 | |
1692 | * (causing a protocol stall, not a real halt). A | |
1693 | * zero length buffer means no DATA stage. | |
1694 | * | |
1695 | * It's fine to issue that response after the setup() | |
1696 | * call returns, and this IRQ was handled. | |
1697 | */ | |
1698 | udc->ep0_setup = 1; | |
1699 | spin_unlock(&udc->lock); | |
80dd1358 | 1700 | status = udc->driver->setup(&udc->gadget, &u.r); |
1da177e4 LT |
1701 | spin_lock(&udc->lock); |
1702 | udc->ep0_setup = 0; | |
1703 | } | |
1704 | ||
1705 | if (status < 0) { | |
1706 | do_stall: | |
1707 | VDBG("req %02x.%02x protocol STALL; stat %d\n", | |
1708 | u.r.bRequestType, u.r.bRequest, status); | |
1709 | if (udc->ep0_set_config) { | |
1710 | if (udc->ep0_reset_config) | |
b6c63937 | 1711 | WARNING("error resetting config?\n"); |
1da177e4 | 1712 | else |
f35ae634 | 1713 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1714 | } |
f35ae634 | 1715 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1716 | udc->ep0_pending = 0; |
1717 | } | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | /*-------------------------------------------------------------------------*/ | |
1722 | ||
1723 | #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT) | |
1724 | ||
1725 | static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |
1726 | { | |
1727 | u16 devstat, change; | |
1728 | ||
f35ae634 | 1729 | devstat = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
1730 | change = devstat ^ udc->devstat; |
1731 | udc->devstat = devstat; | |
1732 | ||
1733 | if (change & (UDC_USB_RESET|UDC_ATT)) { | |
1734 | udc_quiesce(udc); | |
1735 | ||
1736 | if (change & UDC_ATT) { | |
1737 | /* driver for any external transceiver will | |
1738 | * have called omap_vbus_session() already | |
1739 | */ | |
1740 | if (devstat & UDC_ATT) { | |
1741 | udc->gadget.speed = USB_SPEED_FULL; | |
1742 | VDBG("connect\n"); | |
ded017ee | 1743 | if (IS_ERR_OR_NULL(udc->transceiver)) |
1da177e4 | 1744 | pullup_enable(udc); |
80dd1358 | 1745 | /* if (driver->connect) call it */ |
1da177e4 LT |
1746 | } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) { |
1747 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
ded017ee | 1748 | if (IS_ERR_OR_NULL(udc->transceiver)) |
1da177e4 LT |
1749 | pullup_disable(udc); |
1750 | DBG("disconnect, gadget %s\n", | |
1751 | udc->driver->driver.name); | |
1752 | if (udc->driver->disconnect) { | |
1753 | spin_unlock(&udc->lock); | |
1754 | udc->driver->disconnect(&udc->gadget); | |
1755 | spin_lock(&udc->lock); | |
1756 | } | |
1757 | } | |
1758 | change &= ~UDC_ATT; | |
1759 | } | |
1760 | ||
1761 | if (change & UDC_USB_RESET) { | |
1762 | if (devstat & UDC_USB_RESET) { | |
1763 | VDBG("RESET=1\n"); | |
1764 | } else { | |
1765 | udc->gadget.speed = USB_SPEED_FULL; | |
1766 | INFO("USB reset done, gadget %s\n", | |
1767 | udc->driver->driver.name); | |
1768 | /* ep0 traffic is legal from now on */ | |
f35ae634 TL |
1769 | omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, |
1770 | UDC_IRQ_EN); | |
1da177e4 LT |
1771 | } |
1772 | change &= ~UDC_USB_RESET; | |
1773 | } | |
1774 | } | |
1775 | if (change & UDC_SUS) { | |
1776 | if (udc->gadget.speed != USB_SPEED_UNKNOWN) { | |
80dd1358 | 1777 | /* FIXME tell isp1301 to suspend/resume (?) */ |
1da177e4 LT |
1778 | if (devstat & UDC_SUS) { |
1779 | VDBG("suspend\n"); | |
1780 | update_otg(udc); | |
1781 | /* HNP could be under way already */ | |
1782 | if (udc->gadget.speed == USB_SPEED_FULL | |
1783 | && udc->driver->suspend) { | |
1784 | spin_unlock(&udc->lock); | |
1785 | udc->driver->suspend(&udc->gadget); | |
1786 | spin_lock(&udc->lock); | |
1787 | } | |
ded017ee | 1788 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 HK |
1789 | usb_phy_set_suspend( |
1790 | udc->transceiver, 1); | |
1da177e4 LT |
1791 | } else { |
1792 | VDBG("resume\n"); | |
ded017ee | 1793 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 HK |
1794 | usb_phy_set_suspend( |
1795 | udc->transceiver, 0); | |
1da177e4 LT |
1796 | if (udc->gadget.speed == USB_SPEED_FULL |
1797 | && udc->driver->resume) { | |
1798 | spin_unlock(&udc->lock); | |
1799 | udc->driver->resume(&udc->gadget); | |
1800 | spin_lock(&udc->lock); | |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | change &= ~UDC_SUS; | |
1805 | } | |
1806 | if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) { | |
1807 | update_otg(udc); | |
1808 | change &= ~OTG_FLAGS; | |
1809 | } | |
1810 | ||
1811 | change &= ~(UDC_CFG|UDC_DEF|UDC_ADD); | |
1812 | if (change) | |
1813 | VDBG("devstat %03x, ignore change %03x\n", | |
1814 | devstat, change); | |
1815 | ||
f35ae634 | 1816 | omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); |
1da177e4 LT |
1817 | } |
1818 | ||
7d12e780 | 1819 | static irqreturn_t omap_udc_irq(int irq, void *_udc) |
1da177e4 LT |
1820 | { |
1821 | struct omap_udc *udc = _udc; | |
1822 | u16 irq_src; | |
1823 | irqreturn_t status = IRQ_NONE; | |
1824 | unsigned long flags; | |
1825 | ||
1826 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 | 1827 | irq_src = omap_readw(UDC_IRQ_SRC); |
1da177e4 LT |
1828 | |
1829 | /* Device state change (usb ch9 stuff) */ | |
1830 | if (irq_src & UDC_DS_CHG) { | |
1831 | devstate_irq(_udc, irq_src); | |
1832 | status = IRQ_HANDLED; | |
1833 | irq_src &= ~UDC_DS_CHG; | |
1834 | } | |
1835 | ||
1836 | /* EP0 control transfers */ | |
1837 | if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) { | |
1838 | ep0_irq(_udc, irq_src); | |
1839 | status = IRQ_HANDLED; | |
1840 | irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX); | |
1841 | } | |
1842 | ||
1843 | /* DMA transfer completion */ | |
1844 | if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) { | |
1845 | dma_irq(_udc, irq_src); | |
1846 | status = IRQ_HANDLED; | |
1847 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); | |
1848 | } | |
1849 | ||
f35ae634 | 1850 | irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); |
1da177e4 LT |
1851 | if (irq_src) |
1852 | DBG("udc_irq, unhandled %03x\n", irq_src); | |
1853 | spin_unlock_irqrestore(&udc->lock, flags); | |
1854 | ||
1855 | return status; | |
1856 | } | |
1857 | ||
1858 | /* workaround for seemingly-lost IRQs for RX ACKs... */ | |
1859 | #define PIO_OUT_TIMEOUT (jiffies + HZ/3) | |
1860 | #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY))) | |
1861 | ||
1862 | static void pio_out_timer(unsigned long _ep) | |
1863 | { | |
1864 | struct omap_ep *ep = (void *) _ep; | |
1865 | unsigned long flags; | |
1866 | u16 stat_flg; | |
1867 | ||
1868 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1869 | if (!list_empty(&ep->queue) && ep->ackwait) { | |
e6a6e472 | 1870 | use_ep(ep, UDC_EP_SEL); |
f35ae634 | 1871 | stat_flg = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
1872 | |
1873 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) | |
1874 | || (ep->double_buf && HALF_FULL(stat_flg)))) { | |
1875 | struct omap_req *req; | |
1876 | ||
1877 | VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg); | |
1878 | req = container_of(ep->queue.next, | |
1879 | struct omap_req, queue); | |
1da177e4 | 1880 | (void) read_fifo(ep, req); |
f35ae634 TL |
1881 | omap_writew(ep->bEndpointAddress, UDC_EP_NUM); |
1882 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 | 1883 | ep->ackwait = 1 + ep->double_buf; |
e6a6e472 DB |
1884 | } else |
1885 | deselect_ep(); | |
1da177e4 LT |
1886 | } |
1887 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | |
1888 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1889 | } | |
1890 | ||
7d12e780 | 1891 | static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) |
1da177e4 LT |
1892 | { |
1893 | u16 epn_stat, irq_src; | |
1894 | irqreturn_t status = IRQ_NONE; | |
1895 | struct omap_ep *ep; | |
1896 | int epnum; | |
1897 | struct omap_udc *udc = _dev; | |
1898 | struct omap_req *req; | |
1899 | unsigned long flags; | |
1900 | ||
1901 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 TL |
1902 | epn_stat = omap_readw(UDC_EPN_STAT); |
1903 | irq_src = omap_readw(UDC_IRQ_SRC); | |
1da177e4 LT |
1904 | |
1905 | /* handle OUT first, to avoid some wasteful NAKs */ | |
1906 | if (irq_src & UDC_EPN_RX) { | |
1907 | epnum = (epn_stat >> 8) & 0x0f; | |
f35ae634 | 1908 | omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); |
1da177e4 LT |
1909 | status = IRQ_HANDLED; |
1910 | ep = &udc->ep[epnum]; | |
1911 | ep->irqs++; | |
1912 | ||
f35ae634 | 1913 | omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); |
1da177e4 | 1914 | ep->fnf = 0; |
f35ae634 | 1915 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1da177e4 LT |
1916 | ep->ackwait--; |
1917 | if (!list_empty(&ep->queue)) { | |
1918 | int stat; | |
1919 | req = container_of(ep->queue.next, | |
1920 | struct omap_req, queue); | |
1921 | stat = read_fifo(ep, req); | |
1922 | if (!ep->double_buf) | |
1923 | ep->fnf = 1; | |
1924 | } | |
1925 | } | |
1926 | /* min 6 clock delay before clearing EP_SEL ... */ | |
f35ae634 TL |
1927 | epn_stat = omap_readw(UDC_EPN_STAT); |
1928 | epn_stat = omap_readw(UDC_EPN_STAT); | |
1929 | omap_writew(epnum, UDC_EP_NUM); | |
1da177e4 LT |
1930 | |
1931 | /* enabling fifo _after_ clearing ACK, contrary to docs, | |
1932 | * reduces lossage; timer still needed though (sigh). | |
1933 | */ | |
1934 | if (ep->fnf) { | |
f35ae634 | 1935 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1936 | ep->ackwait = 1 + ep->double_buf; |
1937 | } | |
1938 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | |
1939 | } | |
1940 | ||
1941 | /* then IN transfers */ | |
1942 | else if (irq_src & UDC_EPN_TX) { | |
1943 | epnum = epn_stat & 0x0f; | |
f35ae634 | 1944 | omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); |
1da177e4 LT |
1945 | status = IRQ_HANDLED; |
1946 | ep = &udc->ep[16 + epnum]; | |
1947 | ep->irqs++; | |
1948 | ||
f35ae634 TL |
1949 | omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); |
1950 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { | |
1da177e4 LT |
1951 | ep->ackwait = 0; |
1952 | if (!list_empty(&ep->queue)) { | |
1953 | req = container_of(ep->queue.next, | |
1954 | struct omap_req, queue); | |
1955 | (void) write_fifo(ep, req); | |
1956 | } | |
1957 | } | |
1958 | /* min 6 clock delay before clearing EP_SEL ... */ | |
f35ae634 TL |
1959 | epn_stat = omap_readw(UDC_EPN_STAT); |
1960 | epn_stat = omap_readw(UDC_EPN_STAT); | |
1961 | omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1962 | /* then 6 clocks before it'd tx */ |
1963 | } | |
1964 | ||
1965 | spin_unlock_irqrestore(&udc->lock, flags); | |
1966 | return status; | |
1967 | } | |
1968 | ||
1969 | #ifdef USE_ISO | |
7d12e780 | 1970 | static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) |
1da177e4 LT |
1971 | { |
1972 | struct omap_udc *udc = _dev; | |
1973 | struct omap_ep *ep; | |
1974 | int pending = 0; | |
1975 | unsigned long flags; | |
1976 | ||
1977 | spin_lock_irqsave(&udc->lock, flags); | |
1978 | ||
1979 | /* handle all non-DMA ISO transfers */ | |
80dd1358 | 1980 | list_for_each_entry(ep, &udc->iso, iso) { |
1da177e4 LT |
1981 | u16 stat; |
1982 | struct omap_req *req; | |
1983 | ||
1984 | if (ep->has_dma || list_empty(&ep->queue)) | |
1985 | continue; | |
1986 | req = list_entry(ep->queue.next, struct omap_req, queue); | |
1987 | ||
1988 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 1989 | stat = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
1990 | |
1991 | /* NOTE: like the other controller drivers, this isn't | |
1992 | * currently reporting lost or damaged frames. | |
1993 | */ | |
1994 | if (ep->bEndpointAddress & USB_DIR_IN) { | |
1995 | if (stat & UDC_MISS_IN) | |
1996 | /* done(ep, req, -EPROTO) */; | |
1997 | else | |
1998 | write_fifo(ep, req); | |
1999 | } else { | |
2000 | int status = 0; | |
2001 | ||
2002 | if (stat & UDC_NO_RXPACKET) | |
2003 | status = -EREMOTEIO; | |
2004 | else if (stat & UDC_ISO_ERR) | |
2005 | status = -EILSEQ; | |
2006 | else if (stat & UDC_DATA_FLUSH) | |
2007 | status = -ENOSR; | |
2008 | ||
2009 | if (status) | |
2010 | /* done(ep, req, status) */; | |
2011 | else | |
2012 | read_fifo(ep, req); | |
2013 | } | |
2014 | deselect_ep(); | |
2015 | /* 6 wait states before next EP */ | |
2016 | ||
2017 | ep->irqs++; | |
2018 | if (!list_empty(&ep->queue)) | |
2019 | pending = 1; | |
2020 | } | |
f35ae634 TL |
2021 | if (!pending) { |
2022 | u16 w; | |
2023 | ||
2024 | w = omap_readw(UDC_IRQ_EN); | |
2025 | w &= ~UDC_SOF_IE; | |
2026 | omap_writew(w, UDC_IRQ_EN); | |
2027 | } | |
2028 | omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); | |
1da177e4 LT |
2029 | |
2030 | spin_unlock_irqrestore(&udc->lock, flags); | |
2031 | return IRQ_HANDLED; | |
2032 | } | |
2033 | #endif | |
2034 | ||
2035 | /*-------------------------------------------------------------------------*/ | |
2036 | ||
8a3c1f57 | 2037 | static inline int machine_without_vbus_sense(void) |
e6a6e472 | 2038 | { |
80dd1358 | 2039 | return machine_is_omap_innovator() |
e6a6e472 | 2040 | || machine_is_omap_osk() |
e6a6e472 | 2041 | || machine_is_sx1() |
80dd1358 FB |
2042 | /* No known omap7xx boards with vbus sense */ |
2043 | || cpu_is_omap7xx(); | |
e6a6e472 | 2044 | } |
1da177e4 | 2045 | |
1bf0cf60 FB |
2046 | static int omap_udc_start(struct usb_gadget *g, |
2047 | struct usb_gadget_driver *driver) | |
1da177e4 LT |
2048 | { |
2049 | int status = -ENODEV; | |
2050 | struct omap_ep *ep; | |
2051 | unsigned long flags; | |
2052 | ||
1da177e4 LT |
2053 | |
2054 | spin_lock_irqsave(&udc->lock, flags); | |
1da177e4 | 2055 | /* reset state */ |
80dd1358 | 2056 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { |
1da177e4 LT |
2057 | ep->irqs = 0; |
2058 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
2059 | continue; | |
2060 | use_ep(ep, 0); | |
f35ae634 | 2061 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
2062 | } |
2063 | udc->ep0_pending = 0; | |
2064 | udc->ep[0].irqs = 0; | |
2065 | udc->softconnect = 1; | |
2066 | ||
2067 | /* hook up the driver */ | |
313980c9 | 2068 | driver->driver.bus = NULL; |
1da177e4 LT |
2069 | udc->driver = driver; |
2070 | udc->gadget.dev.driver = &driver->driver; | |
2071 | spin_unlock_irqrestore(&udc->lock, flags); | |
2072 | ||
e6a6e472 DB |
2073 | if (udc->dc_clk != NULL) |
2074 | omap_udc_enable_clock(1); | |
2075 | ||
f35ae634 | 2076 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
1da177e4 LT |
2077 | |
2078 | /* connect to bus through transceiver */ | |
ded017ee | 2079 | if (!IS_ERR_OR_NULL(udc->transceiver)) { |
6e13c650 HK |
2080 | status = otg_set_peripheral(udc->transceiver->otg, |
2081 | &udc->gadget); | |
1da177e4 LT |
2082 | if (status < 0) { |
2083 | ERR("can't bind to transceiver\n"); | |
6bea476c | 2084 | if (driver->unbind) { |
80dd1358 | 2085 | driver->unbind(&udc->gadget); |
6bea476c DB |
2086 | udc->gadget.dev.driver = NULL; |
2087 | udc->driver = NULL; | |
2088 | } | |
1da177e4 LT |
2089 | goto done; |
2090 | } | |
2091 | } else { | |
2092 | if (can_pullup(udc)) | |
80dd1358 | 2093 | pullup_enable(udc); |
1da177e4 | 2094 | else |
80dd1358 | 2095 | pullup_disable(udc); |
1da177e4 LT |
2096 | } |
2097 | ||
2098 | /* boards that don't have VBUS sensing can't autogate 48MHz; | |
2099 | * can't enter deep sleep while a gadget driver is active. | |
2100 | */ | |
8a3c1f57 | 2101 | if (machine_without_vbus_sense()) |
1da177e4 LT |
2102 | omap_vbus_session(&udc->gadget, 1); |
2103 | ||
2104 | done: | |
e6a6e472 DB |
2105 | if (udc->dc_clk != NULL) |
2106 | omap_udc_enable_clock(0); | |
1bf0cf60 | 2107 | |
1da177e4 LT |
2108 | return status; |
2109 | } | |
1da177e4 | 2110 | |
1bf0cf60 FB |
2111 | static int omap_udc_stop(struct usb_gadget *g, |
2112 | struct usb_gadget_driver *driver) | |
1da177e4 LT |
2113 | { |
2114 | unsigned long flags; | |
2115 | int status = -ENODEV; | |
2116 | ||
e6a6e472 DB |
2117 | if (udc->dc_clk != NULL) |
2118 | omap_udc_enable_clock(1); | |
2119 | ||
8a3c1f57 | 2120 | if (machine_without_vbus_sense()) |
1da177e4 LT |
2121 | omap_vbus_session(&udc->gadget, 0); |
2122 | ||
ded017ee | 2123 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
6e13c650 | 2124 | (void) otg_set_peripheral(udc->transceiver->otg, NULL); |
1da177e4 LT |
2125 | else |
2126 | pullup_disable(udc); | |
2127 | ||
2128 | spin_lock_irqsave(&udc->lock, flags); | |
2129 | udc_quiesce(udc); | |
2130 | spin_unlock_irqrestore(&udc->lock, flags); | |
2131 | ||
313980c9 DB |
2132 | udc->gadget.dev.driver = NULL; |
2133 | udc->driver = NULL; | |
1da177e4 | 2134 | |
e6a6e472 DB |
2135 | if (udc->dc_clk != NULL) |
2136 | omap_udc_enable_clock(0); | |
1bf0cf60 | 2137 | |
1da177e4 LT |
2138 | return status; |
2139 | } | |
1da177e4 LT |
2140 | |
2141 | /*-------------------------------------------------------------------------*/ | |
2142 | ||
2143 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2144 | ||
2145 | #include <linux/seq_file.h> | |
2146 | ||
2147 | static const char proc_filename[] = "driver/udc"; | |
2148 | ||
2149 | #define FOURBITS "%s%s%s%s" | |
80dd1358 | 2150 | #define EIGHTBITS "%s%s%s%s%s%s%s%s" |
1da177e4 LT |
2151 | |
2152 | static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) | |
2153 | { | |
2154 | u16 stat_flg; | |
2155 | struct omap_req *req; | |
2156 | char buf[20]; | |
2157 | ||
2158 | use_ep(ep, 0); | |
2159 | ||
2160 | if (use_dma && ep->has_dma) | |
2161 | snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ", | |
2162 | (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', | |
2163 | ep->dma_channel - 1, ep->lch); | |
2164 | else | |
2165 | buf[0] = 0; | |
2166 | ||
f35ae634 | 2167 | stat_flg = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
2168 | seq_printf(s, |
2169 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", | |
2170 | ep->name, buf, | |
2171 | ep->double_buf ? "dbuf " : "", | |
80dd1358 FB |
2172 | ({ char *s; |
2173 | switch (ep->ackwait) { | |
2174 | case 0: | |
2175 | s = ""; | |
2176 | break; | |
2177 | case 1: | |
2178 | s = "(ackw) "; | |
2179 | break; | |
2180 | case 2: | |
2181 | s = "(ackw2) "; | |
2182 | break; | |
2183 | default: | |
2184 | s = "(?) "; | |
2185 | break; | |
2186 | } s; }), | |
1da177e4 LT |
2187 | ep->irqs, stat_flg, |
2188 | (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "", | |
2189 | (stat_flg & UDC_MISS_IN) ? "miss_in " : "", | |
2190 | (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "", | |
2191 | (stat_flg & UDC_ISO_ERR) ? "iso_err " : "", | |
2192 | (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "", | |
2193 | (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "", | |
2194 | (stat_flg & UDC_EP_HALTED) ? "HALT " : "", | |
2195 | (stat_flg & UDC_STALL) ? "STALL " : "", | |
2196 | (stat_flg & UDC_NAK) ? "NAK " : "", | |
2197 | (stat_flg & UDC_ACK) ? "ACK " : "", | |
2198 | (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "", | |
2199 | (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "", | |
2200 | (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : ""); | |
2201 | ||
80dd1358 | 2202 | if (list_empty(&ep->queue)) |
1da177e4 LT |
2203 | seq_printf(s, "\t(queue empty)\n"); |
2204 | else | |
80dd1358 | 2205 | list_for_each_entry(req, &ep->queue, queue) { |
1da177e4 LT |
2206 | unsigned length = req->req.actual; |
2207 | ||
2208 | if (use_dma && buf[0]) { | |
2209 | length += ((ep->bEndpointAddress & USB_DIR_IN) | |
2210 | ? dma_src_len : dma_dest_len) | |
2211 | (ep, req->req.dma + length); | |
2212 | buf[0] = 0; | |
2213 | } | |
2214 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
2215 | &req->req, length, | |
2216 | req->req.length, req->req.buf); | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | static char *trx_mode(unsigned m, int enabled) | |
2221 | { | |
2222 | switch (m) { | |
80dd1358 FB |
2223 | case 0: |
2224 | return enabled ? "*6wire" : "unused"; | |
2225 | case 1: | |
2226 | return "4wire"; | |
2227 | case 2: | |
2228 | return "3wire"; | |
2229 | case 3: | |
2230 | return "6wire"; | |
2231 | default: | |
2232 | return "unknown"; | |
1da177e4 LT |
2233 | } |
2234 | } | |
2235 | ||
2236 | static int proc_otg_show(struct seq_file *s) | |
2237 | { | |
2238 | u32 tmp; | |
4814ced5 PW |
2239 | u32 trans = 0; |
2240 | char *ctrl_name = "(UNKNOWN)"; | |
1da177e4 | 2241 | |
e12cc345 | 2242 | tmp = omap_readl(OTG_REV); |
ae372571 TL |
2243 | ctrl_name = "tranceiver_ctrl"; |
2244 | trans = omap_readw(USB_TRANSCEIVER_CTRL); | |
e6a6e472 DB |
2245 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", |
2246 | tmp >> 4, tmp & 0xf, ctrl_name, trans); | |
f35ae634 | 2247 | tmp = omap_readw(OTG_SYSCON_1); |
1da177e4 LT |
2248 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," |
2249 | FOURBITS "\n", tmp, | |
2250 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), | |
2251 | trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), | |
65111084 | 2252 | (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710()) |
1da177e4 LT |
2253 | ? "internal" |
2254 | : trx_mode(USB0_TRX_MODE(tmp), 1), | |
2255 | (tmp & OTG_IDLE_EN) ? " !otg" : "", | |
2256 | (tmp & HST_IDLE_EN) ? " !host" : "", | |
2257 | (tmp & DEV_IDLE_EN) ? " !dev" : "", | |
2258 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); | |
f35ae634 | 2259 | tmp = omap_readl(OTG_SYSCON_2); |
1da177e4 LT |
2260 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS |
2261 | " b_ase_brst=%d hmc=%d\n", tmp, | |
2262 | (tmp & OTG_EN) ? " otg_en" : "", | |
2263 | (tmp & USBX_SYNCHRO) ? " synchro" : "", | |
80dd1358 | 2264 | /* much more SRP stuff */ |
1da177e4 LT |
2265 | (tmp & SRP_DATA) ? " srp_data" : "", |
2266 | (tmp & SRP_VBUS) ? " srp_vbus" : "", | |
2267 | (tmp & OTG_PADEN) ? " otg_paden" : "", | |
2268 | (tmp & HMC_PADEN) ? " hmc_paden" : "", | |
2269 | (tmp & UHOST_EN) ? " uhost_en" : "", | |
2270 | (tmp & HMC_TLLSPEED) ? " tllspeed" : "", | |
2271 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", | |
2272 | B_ASE_BRST(tmp), | |
2273 | OTG_HMC(tmp)); | |
f35ae634 | 2274 | tmp = omap_readl(OTG_CTRL); |
1da177e4 LT |
2275 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, |
2276 | (tmp & OTG_ASESSVLD) ? " asess" : "", | |
2277 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", | |
2278 | (tmp & OTG_BSESSVLD) ? " bsess" : "", | |
2279 | (tmp & OTG_VBUSVLD) ? " vbus" : "", | |
2280 | (tmp & OTG_ID) ? " id" : "", | |
2281 | (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST", | |
2282 | (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "", | |
2283 | (tmp & OTG_A_BUSREQ) ? " a_bus" : "", | |
2284 | (tmp & OTG_B_HNPEN) ? " b_hnpen" : "", | |
2285 | (tmp & OTG_B_BUSREQ) ? " b_bus" : "", | |
2286 | (tmp & OTG_BUSDROP) ? " busdrop" : "", | |
2287 | (tmp & OTG_PULLDOWN) ? " down" : "", | |
2288 | (tmp & OTG_PULLUP) ? " up" : "", | |
2289 | (tmp & OTG_DRV_VBUS) ? " drv" : "", | |
2290 | (tmp & OTG_PD_VBUS) ? " pd_vb" : "", | |
2291 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", | |
2292 | (tmp & OTG_PU_ID) ? " pu_id" : "" | |
2293 | ); | |
f35ae634 | 2294 | tmp = omap_readw(OTG_IRQ_EN); |
1da177e4 | 2295 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); |
f35ae634 | 2296 | tmp = omap_readw(OTG_IRQ_SRC); |
1da177e4 | 2297 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); |
f35ae634 | 2298 | tmp = omap_readw(OTG_OUTCTRL); |
1da177e4 | 2299 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); |
f35ae634 | 2300 | tmp = omap_readw(OTG_TEST); |
1da177e4 | 2301 | seq_printf(s, "otg_test %04x" "\n", tmp); |
313980c9 | 2302 | return 0; |
1da177e4 LT |
2303 | } |
2304 | ||
2305 | static int proc_udc_show(struct seq_file *s, void *_) | |
2306 | { | |
2307 | u32 tmp; | |
2308 | struct omap_ep *ep; | |
2309 | unsigned long flags; | |
2310 | ||
2311 | spin_lock_irqsave(&udc->lock, flags); | |
2312 | ||
2313 | seq_printf(s, "%s, version: " DRIVER_VERSION | |
2314 | #ifdef USE_ISO | |
2315 | " (iso)" | |
2316 | #endif | |
2317 | "%s\n", | |
2318 | driver_desc, | |
2319 | use_dma ? " (dma)" : ""); | |
2320 | ||
f35ae634 | 2321 | tmp = omap_readw(UDC_REV) & 0xff; |
1da177e4 LT |
2322 | seq_printf(s, |
2323 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" | |
2324 | "hmc %d, transceiver %s\n", | |
2325 | tmp >> 4, tmp & 0xf, | |
2326 | fifo_mode, | |
2327 | udc->driver ? udc->driver->driver.name : "(none)", | |
2328 | HMC, | |
e6a6e472 DB |
2329 | udc->transceiver |
2330 | ? udc->transceiver->label | |
ae372571 | 2331 | : (cpu_is_omap1710() |
e6a6e472 | 2332 | ? "external" : "(none)")); |
ae372571 TL |
2333 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", |
2334 | omap_readw(ULPD_CLOCK_CTRL), | |
2335 | omap_readw(ULPD_SOFT_REQ), | |
2336 | omap_readw(ULPD_STATUS_REQ)); | |
1da177e4 LT |
2337 | |
2338 | /* OTG controller registers */ | |
2339 | if (!cpu_is_omap15xx()) | |
2340 | proc_otg_show(s); | |
2341 | ||
f35ae634 | 2342 | tmp = omap_readw(UDC_SYSCON1); |
1da177e4 LT |
2343 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, |
2344 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", | |
2345 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", | |
2346 | (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "", | |
2347 | (tmp & UDC_NAK_EN) ? " nak" : "", | |
2348 | (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "", | |
2349 | (tmp & UDC_SELF_PWR) ? " self_pwr" : "", | |
2350 | (tmp & UDC_SOFF_DIS) ? " soff_dis" : "", | |
2351 | (tmp & UDC_PULLUP_EN) ? " PULLUP" : ""); | |
80dd1358 | 2352 | /* syscon2 is write-only */ |
1da177e4 LT |
2353 | |
2354 | /* UDC controller registers */ | |
2355 | if (!(tmp & UDC_PULLUP_EN)) { | |
2356 | seq_printf(s, "(suspended)\n"); | |
2357 | spin_unlock_irqrestore(&udc->lock, flags); | |
2358 | return 0; | |
2359 | } | |
2360 | ||
f35ae634 | 2361 | tmp = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
2362 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, |
2363 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", | |
2364 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", | |
2365 | (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "", | |
2366 | (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "", | |
2367 | (tmp & UDC_USB_RESET) ? " usb_reset" : "", | |
2368 | (tmp & UDC_SUS) ? " SUS" : "", | |
2369 | (tmp & UDC_CFG) ? " CFG" : "", | |
2370 | (tmp & UDC_ADD) ? " ADD" : "", | |
2371 | (tmp & UDC_DEF) ? " DEF" : "", | |
2372 | (tmp & UDC_ATT) ? " ATT" : ""); | |
f35ae634 TL |
2373 | seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); |
2374 | tmp = omap_readw(UDC_IRQ_EN); | |
1da177e4 LT |
2375 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, |
2376 | (tmp & UDC_SOF_IE) ? " sof" : "", | |
2377 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", | |
2378 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", | |
2379 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", | |
2380 | (tmp & UDC_EP0_IE) ? " ep0" : ""); | |
f35ae634 | 2381 | tmp = omap_readw(UDC_IRQ_SRC); |
1da177e4 LT |
2382 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, |
2383 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", | |
2384 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", | |
2385 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", | |
f35ae634 | 2386 | (tmp & UDC_IRQ_SOF) ? " sof" : "", |
1da177e4 LT |
2387 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", |
2388 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", | |
2389 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", | |
2390 | (tmp & UDC_SETUP) ? " setup" : "", | |
2391 | (tmp & UDC_EP0_RX) ? " ep0out" : "", | |
2392 | (tmp & UDC_EP0_TX) ? " ep0in" : ""); | |
2393 | if (use_dma) { | |
2394 | unsigned i; | |
2395 | ||
f35ae634 | 2396 | tmp = omap_readw(UDC_DMA_IRQ_EN); |
1da177e4 LT |
2397 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, |
2398 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", | |
2399 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", | |
2400 | (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "", | |
2401 | ||
2402 | (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "", | |
2403 | (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "", | |
2404 | (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "", | |
2405 | ||
2406 | (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "", | |
2407 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", | |
2408 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); | |
2409 | ||
f35ae634 | 2410 | tmp = omap_readw(UDC_RXDMA_CFG); |
1da177e4 LT |
2411 | seq_printf(s, "rxdma_cfg %04x\n", tmp); |
2412 | if (tmp) { | |
2413 | for (i = 0; i < 3; i++) { | |
2414 | if ((tmp & (0x0f << (i * 4))) == 0) | |
2415 | continue; | |
2416 | seq_printf(s, "rxdma[%d] %04x\n", i, | |
f35ae634 | 2417 | omap_readw(UDC_RXDMA(i + 1))); |
1da177e4 LT |
2418 | } |
2419 | } | |
f35ae634 | 2420 | tmp = omap_readw(UDC_TXDMA_CFG); |
1da177e4 LT |
2421 | seq_printf(s, "txdma_cfg %04x\n", tmp); |
2422 | if (tmp) { | |
2423 | for (i = 0; i < 3; i++) { | |
2424 | if (!(tmp & (0x0f << (i * 4)))) | |
2425 | continue; | |
2426 | seq_printf(s, "txdma[%d] %04x\n", i, | |
f35ae634 | 2427 | omap_readw(UDC_TXDMA(i + 1))); |
1da177e4 LT |
2428 | } |
2429 | } | |
2430 | } | |
2431 | ||
f35ae634 | 2432 | tmp = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
2433 | if (tmp & UDC_ATT) { |
2434 | proc_ep_show(s, &udc->ep[0]); | |
2435 | if (tmp & UDC_ADD) { | |
80dd1358 | 2436 | list_for_each_entry(ep, &udc->gadget.ep_list, |
1da177e4 | 2437 | ep.ep_list) { |
f8bdae06 | 2438 | if (ep->ep.desc) |
1da177e4 LT |
2439 | proc_ep_show(s, ep); |
2440 | } | |
2441 | } | |
2442 | } | |
2443 | spin_unlock_irqrestore(&udc->lock, flags); | |
2444 | return 0; | |
2445 | } | |
2446 | ||
2447 | static int proc_udc_open(struct inode *inode, struct file *file) | |
2448 | { | |
313980c9 | 2449 | return single_open(file, proc_udc_show, NULL); |
1da177e4 LT |
2450 | } |
2451 | ||
066202dd | 2452 | static const struct file_operations proc_ops = { |
cdefa185 | 2453 | .owner = THIS_MODULE, |
1da177e4 LT |
2454 | .open = proc_udc_open, |
2455 | .read = seq_read, | |
2456 | .llseek = seq_lseek, | |
2457 | .release = single_release, | |
2458 | }; | |
2459 | ||
2460 | static void create_proc_file(void) | |
2461 | { | |
cdefa185 | 2462 | proc_create(proc_filename, 0, NULL, &proc_ops); |
1da177e4 LT |
2463 | } |
2464 | ||
2465 | static void remove_proc_file(void) | |
2466 | { | |
313980c9 | 2467 | remove_proc_entry(proc_filename, NULL); |
1da177e4 LT |
2468 | } |
2469 | ||
2470 | #else | |
2471 | ||
2472 | static inline void create_proc_file(void) {} | |
2473 | static inline void remove_proc_file(void) {} | |
2474 | ||
2475 | #endif | |
2476 | ||
2477 | /*-------------------------------------------------------------------------*/ | |
2478 | ||
2479 | /* Before this controller can enumerate, we need to pick an endpoint | |
2480 | * configuration, or "fifo_mode" That involves allocating 2KB of packet | |
2481 | * buffer space among the endpoints we'll be operating. | |
65111084 DB |
2482 | * |
2483 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when | |
f35ae634 | 2484 | * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that |
65111084 | 2485 | * capability yet though. |
1da177e4 | 2486 | */ |
41ac7b3a | 2487 | static unsigned |
1da177e4 LT |
2488 | omap_ep_setup(char *name, u8 addr, u8 type, |
2489 | unsigned buf, unsigned maxp, int dbuf) | |
2490 | { | |
2491 | struct omap_ep *ep; | |
2492 | u16 epn_rxtx = 0; | |
2493 | ||
2494 | /* OUT endpoints first, then IN */ | |
2495 | ep = &udc->ep[addr & 0xf]; | |
2496 | if (addr & USB_DIR_IN) | |
2497 | ep += 16; | |
2498 | ||
2499 | /* in case of ep init table bugs */ | |
2500 | BUG_ON(ep->name[0]); | |
2501 | ||
2502 | /* chip setup ... bit values are same for IN, OUT */ | |
2503 | if (type == USB_ENDPOINT_XFER_ISOC) { | |
2504 | switch (maxp) { | |
80dd1358 FB |
2505 | case 8: |
2506 | epn_rxtx = 0 << 12; | |
2507 | break; | |
2508 | case 16: | |
2509 | epn_rxtx = 1 << 12; | |
2510 | break; | |
2511 | case 32: | |
2512 | epn_rxtx = 2 << 12; | |
2513 | break; | |
2514 | case 64: | |
2515 | epn_rxtx = 3 << 12; | |
2516 | break; | |
2517 | case 128: | |
2518 | epn_rxtx = 4 << 12; | |
2519 | break; | |
2520 | case 256: | |
2521 | epn_rxtx = 5 << 12; | |
2522 | break; | |
2523 | case 512: | |
2524 | epn_rxtx = 6 << 12; | |
2525 | break; | |
2526 | default: | |
2527 | BUG(); | |
1da177e4 LT |
2528 | } |
2529 | epn_rxtx |= UDC_EPN_RX_ISO; | |
2530 | dbuf = 1; | |
2531 | } else { | |
2532 | /* double-buffering "not supported" on 15xx, | |
e6a6e472 DB |
2533 | * and ignored for PIO-IN on newer chips |
2534 | * (for more reliable behavior) | |
1da177e4 | 2535 | */ |
ae372571 | 2536 | if (!use_dma || cpu_is_omap15xx()) |
1da177e4 LT |
2537 | dbuf = 0; |
2538 | ||
2539 | switch (maxp) { | |
80dd1358 FB |
2540 | case 8: |
2541 | epn_rxtx = 0 << 12; | |
2542 | break; | |
2543 | case 16: | |
2544 | epn_rxtx = 1 << 12; | |
2545 | break; | |
2546 | case 32: | |
2547 | epn_rxtx = 2 << 12; | |
2548 | break; | |
2549 | case 64: | |
2550 | epn_rxtx = 3 << 12; | |
2551 | break; | |
2552 | default: | |
2553 | BUG(); | |
1da177e4 LT |
2554 | } |
2555 | if (dbuf && addr) | |
2556 | epn_rxtx |= UDC_EPN_RX_DB; | |
2557 | init_timer(&ep->timer); | |
2558 | ep->timer.function = pio_out_timer; | |
2559 | ep->timer.data = (unsigned long) ep; | |
2560 | } | |
2561 | if (addr) | |
2562 | epn_rxtx |= UDC_EPN_RX_VALID; | |
2563 | BUG_ON(buf & 0x07); | |
2564 | epn_rxtx |= buf >> 3; | |
2565 | ||
2566 | DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n", | |
2567 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); | |
2568 | ||
2569 | if (addr & USB_DIR_IN) | |
f35ae634 | 2570 | omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); |
1da177e4 | 2571 | else |
f35ae634 | 2572 | omap_writew(epn_rxtx, UDC_EP_RX(addr)); |
1da177e4 LT |
2573 | |
2574 | /* next endpoint's buffer starts after this one's */ | |
2575 | buf += maxp; | |
2576 | if (dbuf) | |
2577 | buf += maxp; | |
2578 | BUG_ON(buf > 2048); | |
2579 | ||
2580 | /* set up driver data structures */ | |
2581 | BUG_ON(strlen(name) >= sizeof ep->name); | |
2582 | strlcpy(ep->name, name, sizeof ep->name); | |
2583 | INIT_LIST_HEAD(&ep->queue); | |
2584 | INIT_LIST_HEAD(&ep->iso); | |
2585 | ep->bEndpointAddress = addr; | |
2586 | ep->bmAttributes = type; | |
2587 | ep->double_buf = dbuf; | |
e6a6e472 | 2588 | ep->udc = udc; |
1da177e4 LT |
2589 | |
2590 | ep->ep.name = ep->name; | |
2591 | ep->ep.ops = &omap_ep_ops; | |
2592 | ep->ep.maxpacket = ep->maxpacket = maxp; | |
80dd1358 | 2593 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); |
1da177e4 LT |
2594 | |
2595 | return buf; | |
2596 | } | |
2597 | ||
2598 | static void omap_udc_release(struct device *dev) | |
2599 | { | |
2600 | complete(udc->done); | |
80dd1358 | 2601 | kfree(udc); |
313980c9 | 2602 | udc = NULL; |
1da177e4 LT |
2603 | } |
2604 | ||
41ac7b3a | 2605 | static int |
86753811 | 2606 | omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv) |
1da177e4 LT |
2607 | { |
2608 | unsigned tmp, buf; | |
2609 | ||
2610 | /* abolish any previous hardware state */ | |
f35ae634 TL |
2611 | omap_writew(0, UDC_SYSCON1); |
2612 | omap_writew(0, UDC_IRQ_EN); | |
2613 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); | |
2614 | omap_writew(0, UDC_DMA_IRQ_EN); | |
2615 | omap_writew(0, UDC_RXDMA_CFG); | |
2616 | omap_writew(0, UDC_TXDMA_CFG); | |
1da177e4 LT |
2617 | |
2618 | /* UDC_PULLUP_EN gates the chip clock */ | |
80dd1358 | 2619 | /* OTG_SYSCON_1 |= DEV_IDLE_EN; */ |
1da177e4 | 2620 | |
e94b1766 | 2621 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); |
1da177e4 LT |
2622 | if (!udc) |
2623 | return -ENOMEM; | |
2624 | ||
80dd1358 | 2625 | spin_lock_init(&udc->lock); |
1da177e4 LT |
2626 | |
2627 | udc->gadget.ops = &omap_gadget_ops; | |
2628 | udc->gadget.ep0 = &udc->ep[0].ep; | |
2629 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
2630 | INIT_LIST_HEAD(&udc->iso); | |
2631 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
d327ab5b | 2632 | udc->gadget.max_speed = USB_SPEED_FULL; |
1da177e4 LT |
2633 | udc->gadget.name = driver_name; |
2634 | ||
2635 | device_initialize(&udc->gadget.dev); | |
0031a06e | 2636 | dev_set_name(&udc->gadget.dev, "gadget"); |
1da177e4 LT |
2637 | udc->gadget.dev.release = omap_udc_release; |
2638 | udc->gadget.dev.parent = &odev->dev; | |
2639 | if (use_dma) | |
2640 | udc->gadget.dev.dma_mask = odev->dev.dma_mask; | |
2641 | ||
2642 | udc->transceiver = xceiv; | |
2643 | ||
2644 | /* ep0 is special; put it right after the SETUP buffer */ | |
2645 | buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL, | |
2646 | 8 /* after SETUP */, 64 /* maxpacket */, 0); | |
2647 | list_del_init(&udc->ep[0].ep.ep_list); | |
2648 | ||
2649 | /* initially disable all non-ep0 endpoints */ | |
2650 | for (tmp = 1; tmp < 15; tmp++) { | |
f35ae634 TL |
2651 | omap_writew(0, UDC_EP_RX(tmp)); |
2652 | omap_writew(0, UDC_EP_TX(tmp)); | |
1da177e4 LT |
2653 | } |
2654 | ||
80dd1358 | 2655 | #define OMAP_BULK_EP(name, addr) \ |
1da177e4 LT |
2656 | buf = omap_ep_setup(name "-bulk", addr, \ |
2657 | USB_ENDPOINT_XFER_BULK, buf, 64, 1); | |
80dd1358 | 2658 | #define OMAP_INT_EP(name, addr, maxp) \ |
1da177e4 LT |
2659 | buf = omap_ep_setup(name "-int", addr, \ |
2660 | USB_ENDPOINT_XFER_INT, buf, maxp, 0); | |
80dd1358 | 2661 | #define OMAP_ISO_EP(name, addr, maxp) \ |
1da177e4 LT |
2662 | buf = omap_ep_setup(name "-iso", addr, \ |
2663 | USB_ENDPOINT_XFER_ISOC, buf, maxp, 1); | |
2664 | ||
2665 | switch (fifo_mode) { | |
2666 | case 0: | |
2667 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2668 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
2669 | OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); | |
2670 | break; | |
2671 | case 1: | |
2672 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2673 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
313980c9 DB |
2674 | OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); |
2675 | ||
1da177e4 LT |
2676 | OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); |
2677 | OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); | |
313980c9 | 2678 | OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16); |
1da177e4 LT |
2679 | |
2680 | OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); | |
2681 | OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); | |
313980c9 DB |
2682 | OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16); |
2683 | ||
1da177e4 LT |
2684 | OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); |
2685 | OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); | |
313980c9 | 2686 | OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16); |
1da177e4 LT |
2687 | |
2688 | OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); | |
2689 | OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); | |
313980c9 DB |
2690 | OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16); |
2691 | OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16); | |
2692 | ||
1da177e4 LT |
2693 | OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); |
2694 | OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); | |
313980c9 DB |
2695 | OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16); |
2696 | OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16); | |
2697 | ||
2698 | OMAP_BULK_EP("ep15in", USB_DIR_IN | 15); | |
2699 | OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15); | |
1da177e4 | 2700 | |
1da177e4 LT |
2701 | break; |
2702 | ||
2703 | #ifdef USE_ISO | |
2704 | case 2: /* mixed iso/bulk */ | |
2705 | OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256); | |
2706 | OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256); | |
2707 | OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128); | |
2708 | OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128); | |
2709 | ||
2710 | OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16); | |
2711 | ||
2712 | OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); | |
2713 | OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); | |
2714 | OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16); | |
2715 | break; | |
2716 | case 3: /* mixed bulk/iso */ | |
2717 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2718 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
2719 | OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); | |
2720 | ||
2721 | OMAP_BULK_EP("ep4in", USB_DIR_IN | 4); | |
2722 | OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); | |
2723 | OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16); | |
2724 | ||
2725 | OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256); | |
2726 | OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256); | |
2727 | OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); | |
2728 | break; | |
2729 | #endif | |
2730 | ||
2731 | /* add more modes as needed */ | |
2732 | ||
2733 | default: | |
2734 | ERR("unsupported fifo_mode #%d\n", fifo_mode); | |
2735 | return -ENODEV; | |
2736 | } | |
f35ae634 | 2737 | omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); |
1da177e4 LT |
2738 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); |
2739 | return 0; | |
2740 | } | |
2741 | ||
41ac7b3a | 2742 | static int omap_udc_probe(struct platform_device *pdev) |
1da177e4 | 2743 | { |
1da177e4 LT |
2744 | int status = -ENODEV; |
2745 | int hmc; | |
86753811 | 2746 | struct usb_phy *xceiv = NULL; |
313980c9 | 2747 | const char *type = NULL; |
3ae5eaec | 2748 | struct omap_usb_config *config = pdev->dev.platform_data; |
ae372571 TL |
2749 | struct clk *dc_clk = NULL; |
2750 | struct clk *hhc_clk = NULL; | |
1da177e4 | 2751 | |
5b6d84b7 FB |
2752 | if (cpu_is_omap7xx()) |
2753 | use_dma = 0; | |
1da177e4 LT |
2754 | |
2755 | /* NOTE: "knows" the order of the resources! */ | |
e6a6e472 | 2756 | if (!request_mem_region(pdev->resource[0].start, |
3ae5eaec | 2757 | pdev->resource[0].end - pdev->resource[0].start + 1, |
1da177e4 LT |
2758 | driver_name)) { |
2759 | DBG("request_mem_region failed\n"); | |
2760 | return -EBUSY; | |
2761 | } | |
2762 | ||
e6a6e472 DB |
2763 | if (cpu_is_omap16xx()) { |
2764 | dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); | |
2765 | hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck"); | |
2766 | BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); | |
2767 | /* can't use omap_udc_enable_clock yet */ | |
2768 | clk_enable(dc_clk); | |
2769 | clk_enable(hhc_clk); | |
2770 | udelay(100); | |
2771 | } | |
2772 | ||
45f780a0 CM |
2773 | if (cpu_is_omap7xx()) { |
2774 | dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); | |
2775 | hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck"); | |
2776 | BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); | |
2777 | /* can't use omap_udc_enable_clock yet */ | |
2778 | clk_enable(dc_clk); | |
2779 | clk_enable(hhc_clk); | |
2780 | udelay(100); | |
2781 | } | |
2782 | ||
1da177e4 | 2783 | INFO("OMAP UDC rev %d.%d%s\n", |
f35ae634 | 2784 | omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, |
1da177e4 LT |
2785 | config->otg ? ", Mini-AB" : ""); |
2786 | ||
2787 | /* use the mode given to us by board init code */ | |
2788 | if (cpu_is_omap15xx()) { | |
2789 | hmc = HMC_1510; | |
2790 | type = "(unknown)"; | |
2791 | ||
8a3c1f57 | 2792 | if (machine_without_vbus_sense()) { |
1da177e4 LT |
2793 | /* just set up software VBUS detect, and then |
2794 | * later rig it so we always report VBUS. | |
2795 | * FIXME without really sensing VBUS, we can't | |
2796 | * know when to turn PULLUP_EN on/off; and that | |
2797 | * means we always "need" the 48MHz clock. | |
2798 | */ | |
f35ae634 TL |
2799 | u32 tmp = omap_readl(FUNC_MUX_CTRL_0); |
2800 | tmp &= ~VBUS_CTRL_1510; | |
2801 | omap_writel(tmp, FUNC_MUX_CTRL_0); | |
1da177e4 LT |
2802 | tmp |= VBUS_MODE_1510; |
2803 | tmp &= ~VBUS_CTRL_1510; | |
f35ae634 | 2804 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
1da177e4 LT |
2805 | } |
2806 | } else { | |
65111084 DB |
2807 | /* The transceiver may package some GPIO logic or handle |
2808 | * loopback and/or transceiverless setup; if we find one, | |
2809 | * use it. Except for OTG, we don't _need_ to talk to one; | |
2810 | * but not having one probably means no VBUS detection. | |
2811 | */ | |
662dca54 | 2812 | xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 2813 | if (!IS_ERR_OR_NULL(xceiv)) |
65111084 DB |
2814 | type = xceiv->label; |
2815 | else if (config->otg) { | |
2816 | DBG("OTG requires external transceiver!\n"); | |
2817 | goto cleanup0; | |
2818 | } | |
2819 | ||
1da177e4 | 2820 | hmc = HMC_1610; |
e6a6e472 | 2821 | |
1da177e4 | 2822 | switch (hmc) { |
313980c9 DB |
2823 | case 0: /* POWERUP DEFAULT == 0 */ |
2824 | case 4: | |
2825 | case 12: | |
2826 | case 20: | |
2827 | if (!cpu_is_omap1710()) { | |
2828 | type = "integrated"; | |
2829 | break; | |
2830 | } | |
2831 | /* FALL THROUGH */ | |
1da177e4 LT |
2832 | case 3: |
2833 | case 11: | |
2834 | case 16: | |
2835 | case 19: | |
2836 | case 25: | |
ded017ee | 2837 | if (IS_ERR_OR_NULL(xceiv)) { |
1da177e4 | 2838 | DBG("external transceiver not registered!\n"); |
313980c9 | 2839 | type = "unknown"; |
65111084 | 2840 | } |
1da177e4 | 2841 | break; |
1da177e4 | 2842 | case 21: /* internal loopback */ |
313980c9 | 2843 | type = "loopback"; |
1da177e4 LT |
2844 | break; |
2845 | case 14: /* transceiverless */ | |
65111084 DB |
2846 | if (cpu_is_omap1710()) |
2847 | goto bad_on_1710; | |
2848 | /* FALL THROUGH */ | |
2849 | case 13: | |
2850 | case 15: | |
313980c9 | 2851 | type = "no"; |
1da177e4 LT |
2852 | break; |
2853 | ||
2854 | default: | |
65111084 | 2855 | bad_on_1710: |
1da177e4 | 2856 | ERR("unrecognized UDC HMC mode %d\n", hmc); |
65111084 | 2857 | goto cleanup0; |
1da177e4 LT |
2858 | } |
2859 | } | |
ae372571 | 2860 | |
313980c9 | 2861 | INFO("hmc mode %d, %s transceiver\n", hmc, type); |
1da177e4 LT |
2862 | |
2863 | /* a "gadget" abstracts/virtualizes the controller */ | |
3ae5eaec | 2864 | status = omap_udc_setup(pdev, xceiv); |
80dd1358 | 2865 | if (status) |
1da177e4 | 2866 | goto cleanup0; |
80dd1358 | 2867 | |
313980c9 | 2868 | xceiv = NULL; |
80dd1358 | 2869 | /* "udc" is now valid */ |
1da177e4 LT |
2870 | pullup_disable(udc); |
2871 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
2872 | udc->gadget.is_otg = (config->otg != 0); | |
2873 | #endif | |
2874 | ||
65111084 | 2875 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ |
f35ae634 | 2876 | if (omap_readw(UDC_REV) >= 0x61) |
65111084 DB |
2877 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; |
2878 | else | |
2879 | udc->clr_halt = UDC_RESET_EP; | |
2880 | ||
1da177e4 | 2881 | /* USB general purpose IRQ: ep0, state changes, dma, etc */ |
3ae5eaec | 2882 | status = request_irq(pdev->resource[1].start, omap_udc_irq, |
80dd1358 | 2883 | 0, driver_name, udc); |
1da177e4 | 2884 | if (status != 0) { |
e6a6e472 DB |
2885 | ERR("can't get irq %d, err %d\n", |
2886 | (int) pdev->resource[1].start, status); | |
1da177e4 LT |
2887 | goto cleanup1; |
2888 | } | |
2889 | ||
2890 | /* USB "non-iso" IRQ (PIO for all but ep0) */ | |
3ae5eaec | 2891 | status = request_irq(pdev->resource[2].start, omap_udc_pio_irq, |
80dd1358 | 2892 | 0, "omap_udc pio", udc); |
1da177e4 | 2893 | if (status != 0) { |
e6a6e472 DB |
2894 | ERR("can't get irq %d, err %d\n", |
2895 | (int) pdev->resource[2].start, status); | |
1da177e4 LT |
2896 | goto cleanup2; |
2897 | } | |
2898 | #ifdef USE_ISO | |
3ae5eaec | 2899 | status = request_irq(pdev->resource[3].start, omap_udc_iso_irq, |
b5dd18d8 | 2900 | 0, "omap_udc iso", udc); |
1da177e4 | 2901 | if (status != 0) { |
e6a6e472 DB |
2902 | ERR("can't get irq %d, err %d\n", |
2903 | (int) pdev->resource[3].start, status); | |
1da177e4 LT |
2904 | goto cleanup3; |
2905 | } | |
2906 | #endif | |
45f780a0 | 2907 | if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
e6a6e472 DB |
2908 | udc->dc_clk = dc_clk; |
2909 | udc->hhc_clk = hhc_clk; | |
2910 | clk_disable(hhc_clk); | |
2911 | clk_disable(dc_clk); | |
2912 | } | |
2913 | ||
1da177e4 | 2914 | create_proc_file(); |
e6a6e472 | 2915 | status = device_add(&udc->gadget.dev); |
0f91349b SAS |
2916 | if (status) |
2917 | goto cleanup4; | |
2918 | ||
2919 | status = usb_add_gadget_udc(&pdev->dev, &udc->gadget); | |
e6a6e472 DB |
2920 | if (!status) |
2921 | return status; | |
2922 | /* If fail, fall through */ | |
0f91349b SAS |
2923 | cleanup4: |
2924 | remove_proc_file(); | |
2925 | ||
1da177e4 LT |
2926 | #ifdef USE_ISO |
2927 | cleanup3: | |
3ae5eaec | 2928 | free_irq(pdev->resource[2].start, udc); |
1da177e4 LT |
2929 | #endif |
2930 | ||
2931 | cleanup2: | |
3ae5eaec | 2932 | free_irq(pdev->resource[1].start, udc); |
1da177e4 LT |
2933 | |
2934 | cleanup1: | |
80dd1358 | 2935 | kfree(udc); |
313980c9 | 2936 | udc = NULL; |
1da177e4 LT |
2937 | |
2938 | cleanup0: | |
ded017ee | 2939 | if (!IS_ERR_OR_NULL(xceiv)) |
721002ec | 2940 | usb_put_phy(xceiv); |
e6a6e472 | 2941 | |
ae372571 | 2942 | if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
e6a6e472 DB |
2943 | clk_disable(hhc_clk); |
2944 | clk_disable(dc_clk); | |
2945 | clk_put(hhc_clk); | |
2946 | clk_put(dc_clk); | |
2947 | } | |
2948 | ||
3ae5eaec RK |
2949 | release_mem_region(pdev->resource[0].start, |
2950 | pdev->resource[0].end - pdev->resource[0].start + 1); | |
e6a6e472 | 2951 | |
1da177e4 LT |
2952 | return status; |
2953 | } | |
2954 | ||
fb4e98ab | 2955 | static int omap_udc_remove(struct platform_device *pdev) |
1da177e4 | 2956 | { |
6e9a4738 | 2957 | DECLARE_COMPLETION_ONSTACK(done); |
1da177e4 LT |
2958 | |
2959 | if (!udc) | |
2960 | return -ENODEV; | |
0f91349b SAS |
2961 | |
2962 | usb_del_gadget_udc(&udc->gadget); | |
6bea476c DB |
2963 | if (udc->driver) |
2964 | return -EBUSY; | |
1da177e4 LT |
2965 | |
2966 | udc->done = &done; | |
2967 | ||
2968 | pullup_disable(udc); | |
ded017ee | 2969 | if (!IS_ERR_OR_NULL(udc->transceiver)) { |
721002ec | 2970 | usb_put_phy(udc->transceiver); |
313980c9 | 2971 | udc->transceiver = NULL; |
1da177e4 | 2972 | } |
f35ae634 | 2973 | omap_writew(0, UDC_SYSCON1); |
1da177e4 LT |
2974 | |
2975 | remove_proc_file(); | |
2976 | ||
2977 | #ifdef USE_ISO | |
3ae5eaec | 2978 | free_irq(pdev->resource[3].start, udc); |
1da177e4 | 2979 | #endif |
3ae5eaec RK |
2980 | free_irq(pdev->resource[2].start, udc); |
2981 | free_irq(pdev->resource[1].start, udc); | |
1da177e4 | 2982 | |
e6a6e472 DB |
2983 | if (udc->dc_clk) { |
2984 | if (udc->clk_requested) | |
2985 | omap_udc_enable_clock(0); | |
2986 | clk_put(udc->hhc_clk); | |
2987 | clk_put(udc->dc_clk); | |
2988 | } | |
2989 | ||
3ae5eaec RK |
2990 | release_mem_region(pdev->resource[0].start, |
2991 | pdev->resource[0].end - pdev->resource[0].start + 1); | |
1da177e4 LT |
2992 | |
2993 | device_unregister(&udc->gadget.dev); | |
2994 | wait_for_completion(&done); | |
2995 | ||
2996 | return 0; | |
2997 | } | |
2998 | ||
313980c9 DB |
2999 | /* suspend/resume/wakeup from sysfs (echo > power/state) or when the |
3000 | * system is forced into deep sleep | |
3001 | * | |
3002 | * REVISIT we should probably reject suspend requests when there's a host | |
3003 | * session active, rather than disconnecting, at least on boards that can | |
f35ae634 | 3004 | * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to |
313980c9 DB |
3005 | * make host resumes and VBUS detection trigger OMAP wakeup events; that |
3006 | * may involve talking to an external transceiver (e.g. isp1301). | |
3007 | */ | |
1d7beee3 | 3008 | |
3ae5eaec | 3009 | static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) |
1da177e4 | 3010 | { |
313980c9 DB |
3011 | u32 devstat; |
3012 | ||
f35ae634 | 3013 | devstat = omap_readw(UDC_DEVSTAT); |
313980c9 DB |
3014 | |
3015 | /* we're requesting 48 MHz clock if the pullup is enabled | |
3016 | * (== we're attached to the host) and we're not suspended, | |
3017 | * which would prevent entry to deep sleep... | |
3018 | */ | |
3019 | if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) { | |
b6c63937 | 3020 | WARNING("session active; suspend requires disconnect\n"); |
313980c9 DB |
3021 | omap_pullup(&udc->gadget, 0); |
3022 | } | |
1da177e4 | 3023 | |
1da177e4 LT |
3024 | return 0; |
3025 | } | |
3026 | ||
3ae5eaec | 3027 | static int omap_udc_resume(struct platform_device *dev) |
1da177e4 | 3028 | { |
1da177e4 | 3029 | DBG("resume + wakeup/SRP\n"); |
1da177e4 LT |
3030 | omap_pullup(&udc->gadget, 1); |
3031 | ||
3032 | /* maybe the host would enumerate us if we nudged it */ | |
3033 | msleep(100); | |
3034 | return omap_wakeup(&udc->gadget); | |
3035 | } | |
3036 | ||
3037 | /*-------------------------------------------------------------------------*/ | |
3038 | ||
3ae5eaec | 3039 | static struct platform_driver udc_driver = { |
dc1737cd | 3040 | .probe = omap_udc_probe, |
7690417d | 3041 | .remove = omap_udc_remove, |
1da177e4 LT |
3042 | .suspend = omap_udc_suspend, |
3043 | .resume = omap_udc_resume, | |
3ae5eaec RK |
3044 | .driver = { |
3045 | .owner = THIS_MODULE, | |
3046 | .name = (char *) driver_name, | |
3047 | }, | |
1da177e4 LT |
3048 | }; |
3049 | ||
dc1737cd | 3050 | module_platform_driver(udc_driver); |
1da177e4 LT |
3051 | |
3052 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3053 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 3054 | MODULE_ALIAS("platform:omap_udc"); |