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d75379a5 RJ |
1 | /* |
2 | * Handles the Intel 27x USB Device Controller (UDC) | |
3 | * | |
4 | * Inspired by original driver by Frank Becker, David Brownell, and others. | |
5 | * Copyright (C) 2008 Robert Jarzmik | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/proc_fs.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/irq.h> | |
34 | ||
35 | #include <asm/byteorder.h> | |
36 | #include <asm/hardware.h> | |
37 | ||
38 | #include <linux/usb.h> | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
41 | ||
42 | #include <asm/arch/udc.h> | |
43 | ||
44 | #include "pxa27x_udc.h" | |
45 | ||
46 | /* | |
47 | * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x | |
48 | * series processors. | |
49 | * | |
50 | * Such controller drivers work with a gadget driver. The gadget driver | |
51 | * returns descriptors, implements configuration and data protocols used | |
52 | * by the host to interact with this device, and allocates endpoints to | |
53 | * the different protocol interfaces. The controller driver virtualizes | |
54 | * usb hardware so that the gadget drivers will be more portable. | |
55 | * | |
56 | * This UDC hardware wants to implement a bit too much USB protocol. The | |
57 | * biggest issues are: that the endpoints have to be set up before the | |
58 | * controller can be enabled (minor, and not uncommon); and each endpoint | |
59 | * can only have one configuration, interface and alternative interface | |
60 | * number (major, and very unusual). Once set up, these cannot be changed | |
61 | * without a controller reset. | |
62 | * | |
63 | * The workaround is to setup all combinations necessary for the gadgets which | |
64 | * will work with this driver. This is done in pxa_udc structure, statically. | |
65 | * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep. | |
66 | * (You could modify this if needed. Some drivers have a "fifo_mode" module | |
67 | * parameter to facilitate such changes.) | |
68 | * | |
69 | * The combinations have been tested with these gadgets : | |
70 | * - zero gadget | |
71 | * - file storage gadget | |
72 | * - ether gadget | |
73 | * | |
74 | * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is | |
75 | * made of UDC's double buffering either. USB "On-The-Go" is not implemented. | |
76 | * | |
77 | * All the requests are handled the same way : | |
78 | * - the drivers tries to handle the request directly to the IO | |
79 | * - if the IO fifo is not big enough, the remaining is send/received in | |
80 | * interrupt handling. | |
81 | */ | |
82 | ||
83 | #define DRIVER_VERSION "2008-04-18" | |
84 | #define DRIVER_DESC "PXA 27x USB Device Controller driver" | |
85 | ||
86 | static const char driver_name[] = "pxa27x_udc"; | |
87 | static struct pxa_udc *the_controller; | |
88 | ||
89 | static void handle_ep(struct pxa_ep *ep); | |
90 | ||
91 | /* | |
92 | * Debug filesystem | |
93 | */ | |
94 | #ifdef CONFIG_USB_GADGET_DEBUG_FS | |
95 | ||
96 | #include <linux/debugfs.h> | |
97 | #include <linux/uaccess.h> | |
98 | #include <linux/seq_file.h> | |
99 | ||
100 | static int state_dbg_show(struct seq_file *s, void *p) | |
101 | { | |
102 | struct pxa_udc *udc = s->private; | |
103 | int pos = 0, ret; | |
104 | u32 tmp; | |
105 | ||
106 | ret = -ENODEV; | |
107 | if (!udc->driver) | |
108 | goto out; | |
109 | ||
110 | /* basic device status */ | |
111 | pos += seq_printf(s, DRIVER_DESC "\n" | |
112 | "%s version: %s\nGadget driver: %s\n", | |
113 | driver_name, DRIVER_VERSION, | |
114 | udc->driver ? udc->driver->driver.name : "(none)"); | |
115 | ||
116 | tmp = udc_readl(udc, UDCCR); | |
117 | pos += seq_printf(s, | |
118 | "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), " | |
119 | "con=%d,inter=%d,altinter=%d\n", tmp, | |
120 | (tmp & UDCCR_OEN) ? " oen":"", | |
121 | (tmp & UDCCR_AALTHNP) ? " aalthnp":"", | |
122 | (tmp & UDCCR_AHNP) ? " rem" : "", | |
123 | (tmp & UDCCR_BHNP) ? " rstir" : "", | |
124 | (tmp & UDCCR_DWRE) ? " dwre" : "", | |
125 | (tmp & UDCCR_SMAC) ? " smac" : "", | |
126 | (tmp & UDCCR_EMCE) ? " emce" : "", | |
127 | (tmp & UDCCR_UDR) ? " udr" : "", | |
128 | (tmp & UDCCR_UDA) ? " uda" : "", | |
129 | (tmp & UDCCR_UDE) ? " ude" : "", | |
130 | (tmp & UDCCR_ACN) >> UDCCR_ACN_S, | |
131 | (tmp & UDCCR_AIN) >> UDCCR_AIN_S, | |
132 | (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S); | |
133 | /* registers for device and ep0 */ | |
134 | pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n", | |
135 | udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1)); | |
136 | pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n", | |
137 | udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1)); | |
138 | pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR)); | |
139 | pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, " | |
140 | "reconfig=%lu\n", | |
141 | udc->stats.irqs_reset, udc->stats.irqs_suspend, | |
142 | udc->stats.irqs_resume, udc->stats.irqs_reconfig); | |
143 | ||
144 | ret = 0; | |
145 | out: | |
146 | return ret; | |
147 | } | |
148 | ||
149 | static int queues_dbg_show(struct seq_file *s, void *p) | |
150 | { | |
151 | struct pxa_udc *udc = s->private; | |
152 | struct pxa_ep *ep; | |
153 | struct pxa27x_request *req; | |
154 | int pos = 0, i, maxpkt, ret; | |
155 | ||
156 | ret = -ENODEV; | |
157 | if (!udc->driver) | |
158 | goto out; | |
159 | ||
160 | /* dump endpoint queues */ | |
161 | for (i = 0; i < NR_PXA_ENDPOINTS; i++) { | |
162 | ep = &udc->pxa_ep[i]; | |
163 | maxpkt = ep->fifo_size; | |
164 | pos += seq_printf(s, "%-12s max_pkt=%d %s\n", | |
165 | EPNAME(ep), maxpkt, "pio"); | |
166 | ||
167 | if (list_empty(&ep->queue)) { | |
168 | pos += seq_printf(s, "\t(nothing queued)\n"); | |
169 | continue; | |
170 | } | |
171 | ||
172 | list_for_each_entry(req, &ep->queue, queue) { | |
173 | pos += seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
174 | &req->req, req->req.actual, | |
175 | req->req.length, req->req.buf); | |
176 | } | |
177 | } | |
178 | ||
179 | ret = 0; | |
180 | out: | |
181 | return ret; | |
182 | } | |
183 | ||
184 | static int eps_dbg_show(struct seq_file *s, void *p) | |
185 | { | |
186 | struct pxa_udc *udc = s->private; | |
187 | struct pxa_ep *ep; | |
188 | int pos = 0, i, ret; | |
189 | u32 tmp; | |
190 | ||
191 | ret = -ENODEV; | |
192 | if (!udc->driver) | |
193 | goto out; | |
194 | ||
195 | ep = &udc->pxa_ep[0]; | |
196 | tmp = udc_ep_readl(ep, UDCCSR); | |
197 | pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp, | |
198 | (tmp & UDCCSR0_SA) ? " sa" : "", | |
199 | (tmp & UDCCSR0_RNE) ? " rne" : "", | |
200 | (tmp & UDCCSR0_FST) ? " fst" : "", | |
201 | (tmp & UDCCSR0_SST) ? " sst" : "", | |
202 | (tmp & UDCCSR0_DME) ? " dme" : "", | |
203 | (tmp & UDCCSR0_IPR) ? " ipr" : "", | |
204 | (tmp & UDCCSR0_OPC) ? " opc" : ""); | |
205 | for (i = 0; i < NR_PXA_ENDPOINTS; i++) { | |
206 | ep = &udc->pxa_ep[i]; | |
207 | tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR); | |
208 | pos += seq_printf(s, "%-12s: " | |
209 | "IN %lu(%lu reqs), OUT %lu(%lu reqs), " | |
210 | "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, " | |
211 | "udcbcr=%d\n", | |
212 | EPNAME(ep), | |
213 | ep->stats.in_bytes, ep->stats.in_ops, | |
214 | ep->stats.out_bytes, ep->stats.out_ops, | |
215 | ep->stats.irqs, | |
216 | tmp, udc_ep_readl(ep, UDCCSR), | |
217 | udc_ep_readl(ep, UDCBCR)); | |
218 | } | |
219 | ||
220 | ret = 0; | |
221 | out: | |
222 | return ret; | |
223 | } | |
224 | ||
225 | static int eps_dbg_open(struct inode *inode, struct file *file) | |
226 | { | |
227 | return single_open(file, eps_dbg_show, inode->i_private); | |
228 | } | |
229 | ||
230 | static int queues_dbg_open(struct inode *inode, struct file *file) | |
231 | { | |
232 | return single_open(file, queues_dbg_show, inode->i_private); | |
233 | } | |
234 | ||
235 | static int state_dbg_open(struct inode *inode, struct file *file) | |
236 | { | |
237 | return single_open(file, state_dbg_show, inode->i_private); | |
238 | } | |
239 | ||
240 | static const struct file_operations state_dbg_fops = { | |
241 | .owner = THIS_MODULE, | |
242 | .open = state_dbg_open, | |
243 | .llseek = seq_lseek, | |
244 | .read = seq_read, | |
245 | .release = single_release, | |
246 | }; | |
247 | ||
248 | static const struct file_operations queues_dbg_fops = { | |
249 | .owner = THIS_MODULE, | |
250 | .open = queues_dbg_open, | |
251 | .llseek = seq_lseek, | |
252 | .read = seq_read, | |
253 | .release = single_release, | |
254 | }; | |
255 | ||
256 | static const struct file_operations eps_dbg_fops = { | |
257 | .owner = THIS_MODULE, | |
258 | .open = eps_dbg_open, | |
259 | .llseek = seq_lseek, | |
260 | .read = seq_read, | |
261 | .release = single_release, | |
262 | }; | |
263 | ||
264 | static void pxa_init_debugfs(struct pxa_udc *udc) | |
265 | { | |
266 | struct dentry *root, *state, *queues, *eps; | |
267 | ||
268 | root = debugfs_create_dir(udc->gadget.name, NULL); | |
269 | if (IS_ERR(root) || !root) | |
270 | goto err_root; | |
271 | ||
272 | state = debugfs_create_file("udcstate", 0400, root, udc, | |
273 | &state_dbg_fops); | |
274 | if (!state) | |
275 | goto err_state; | |
276 | queues = debugfs_create_file("queues", 0400, root, udc, | |
277 | &queues_dbg_fops); | |
278 | if (!queues) | |
279 | goto err_queues; | |
280 | eps = debugfs_create_file("epstate", 0400, root, udc, | |
281 | &eps_dbg_fops); | |
282 | if (!queues) | |
283 | goto err_eps; | |
284 | ||
285 | udc->debugfs_root = root; | |
286 | udc->debugfs_state = state; | |
287 | udc->debugfs_queues = queues; | |
288 | udc->debugfs_eps = eps; | |
289 | return; | |
290 | err_eps: | |
291 | debugfs_remove(eps); | |
292 | err_queues: | |
293 | debugfs_remove(queues); | |
294 | err_state: | |
295 | debugfs_remove(root); | |
296 | err_root: | |
297 | dev_err(udc->dev, "debugfs is not available\n"); | |
298 | } | |
299 | ||
300 | static void pxa_cleanup_debugfs(struct pxa_udc *udc) | |
301 | { | |
302 | debugfs_remove(udc->debugfs_eps); | |
303 | debugfs_remove(udc->debugfs_queues); | |
304 | debugfs_remove(udc->debugfs_state); | |
305 | debugfs_remove(udc->debugfs_root); | |
306 | udc->debugfs_eps = NULL; | |
307 | udc->debugfs_queues = NULL; | |
308 | udc->debugfs_state = NULL; | |
309 | udc->debugfs_root = NULL; | |
310 | } | |
311 | ||
312 | #else | |
313 | static inline void pxa_init_debugfs(struct pxa_udc *udc) | |
314 | { | |
315 | } | |
316 | ||
317 | static inline void pxa_cleanup_debugfs(struct pxa_udc *udc) | |
318 | { | |
319 | } | |
320 | #endif | |
321 | ||
322 | /** | |
323 | * is_match_usb_pxa - check if usb_ep and pxa_ep match | |
324 | * @udc_usb_ep: usb endpoint | |
325 | * @ep: pxa endpoint | |
326 | * @config: configuration required in pxa_ep | |
327 | * @interface: interface required in pxa_ep | |
328 | * @altsetting: altsetting required in pxa_ep | |
329 | * | |
330 | * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise | |
331 | */ | |
332 | static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep, | |
333 | int config, int interface, int altsetting) | |
334 | { | |
335 | if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr) | |
336 | return 0; | |
337 | if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in) | |
338 | return 0; | |
339 | if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type) | |
340 | return 0; | |
341 | if ((ep->config != config) || (ep->interface != interface) | |
342 | || (ep->alternate != altsetting)) | |
343 | return 0; | |
344 | return 1; | |
345 | } | |
346 | ||
347 | /** | |
348 | * find_pxa_ep - find pxa_ep structure matching udc_usb_ep | |
349 | * @udc: pxa udc | |
350 | * @udc_usb_ep: udc_usb_ep structure | |
351 | * | |
352 | * Match udc_usb_ep and all pxa_ep available, to see if one matches. | |
353 | * This is necessary because of the strong pxa hardware restriction requiring | |
354 | * that once pxa endpoints are initialized, their configuration is freezed, and | |
355 | * no change can be made to their address, direction, or in which configuration, | |
356 | * interface or altsetting they are active ... which differs from more usual | |
357 | * models which have endpoints be roughly just addressable fifos, and leave | |
358 | * configuration events up to gadget drivers (like all control messages). | |
359 | * | |
360 | * Note that there is still a blurred point here : | |
361 | * - we rely on UDCCR register "active interface" and "active altsetting". | |
362 | * This is a nonsense in regard of USB spec, where multiple interfaces are | |
363 | * active at the same time. | |
364 | * - if we knew for sure that the pxa can handle multiple interface at the | |
365 | * same time, assuming Intel's Developer Guide is wrong, this function | |
366 | * should be reviewed, and a cache of couples (iface, altsetting) should | |
367 | * be kept in the pxa_udc structure. In this case this function would match | |
368 | * against the cache of couples instead of the "last altsetting" set up. | |
369 | * | |
370 | * Returns the matched pxa_ep structure or NULL if none found | |
371 | */ | |
372 | static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc, | |
373 | struct udc_usb_ep *udc_usb_ep) | |
374 | { | |
375 | int i; | |
376 | struct pxa_ep *ep; | |
377 | int cfg = udc->config; | |
378 | int iface = udc->last_interface; | |
379 | int alt = udc->last_alternate; | |
380 | ||
381 | if (udc_usb_ep == &udc->udc_usb_ep[0]) | |
382 | return &udc->pxa_ep[0]; | |
383 | ||
384 | for (i = 1; i < NR_PXA_ENDPOINTS; i++) { | |
385 | ep = &udc->pxa_ep[i]; | |
386 | if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt)) | |
387 | return ep; | |
388 | } | |
389 | return NULL; | |
390 | } | |
391 | ||
392 | /** | |
393 | * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep | |
394 | * @udc: pxa udc | |
395 | * | |
396 | * Context: in_interrupt() | |
397 | * | |
398 | * Updates all pxa_ep fields in udc_usb_ep structures, if this field was | |
399 | * previously set up (and is not NULL). The update is necessary is a | |
400 | * configuration change or altsetting change was issued by the USB host. | |
401 | */ | |
402 | static void update_pxa_ep_matches(struct pxa_udc *udc) | |
403 | { | |
404 | int i; | |
405 | struct udc_usb_ep *udc_usb_ep; | |
406 | ||
407 | for (i = 1; i < NR_USB_ENDPOINTS; i++) { | |
408 | udc_usb_ep = &udc->udc_usb_ep[i]; | |
409 | if (udc_usb_ep->pxa_ep) | |
410 | udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep); | |
411 | } | |
412 | } | |
413 | ||
414 | /** | |
415 | * pio_irq_enable - Enables irq generation for one endpoint | |
416 | * @ep: udc endpoint | |
417 | */ | |
418 | static void pio_irq_enable(struct pxa_ep *ep) | |
419 | { | |
420 | struct pxa_udc *udc = ep->dev; | |
421 | int index = EPIDX(ep); | |
422 | u32 udcicr0 = udc_readl(udc, UDCICR0); | |
423 | u32 udcicr1 = udc_readl(udc, UDCICR1); | |
424 | ||
425 | if (index < 16) | |
426 | udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2))); | |
427 | else | |
428 | udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2))); | |
429 | } | |
430 | ||
431 | /** | |
432 | * pio_irq_disable - Disables irq generation for one endpoint | |
433 | * @ep: udc endpoint | |
434 | * @index: endpoint number | |
435 | */ | |
436 | static void pio_irq_disable(struct pxa_ep *ep) | |
437 | { | |
438 | struct pxa_udc *udc = ep->dev; | |
439 | int index = EPIDX(ep); | |
440 | u32 udcicr0 = udc_readl(udc, UDCICR0); | |
441 | u32 udcicr1 = udc_readl(udc, UDCICR1); | |
442 | ||
443 | if (index < 16) | |
444 | udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2))); | |
445 | else | |
446 | udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2))); | |
447 | } | |
448 | ||
449 | /** | |
450 | * udc_set_mask_UDCCR - set bits in UDCCR | |
451 | * @udc: udc device | |
452 | * @mask: bits to set in UDCCR | |
453 | * | |
454 | * Sets bits in UDCCR, leaving DME and FST bits as they were. | |
455 | */ | |
456 | static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask) | |
457 | { | |
458 | u32 udccr = udc_readl(udc, UDCCR); | |
459 | udc_writel(udc, UDCCR, | |
460 | (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS)); | |
461 | } | |
462 | ||
463 | /** | |
464 | * udc_clear_mask_UDCCR - clears bits in UDCCR | |
465 | * @udc: udc device | |
466 | * @mask: bit to clear in UDCCR | |
467 | * | |
468 | * Clears bits in UDCCR, leaving DME and FST bits as they were. | |
469 | */ | |
470 | static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask) | |
471 | { | |
472 | u32 udccr = udc_readl(udc, UDCCR); | |
473 | udc_writel(udc, UDCCR, | |
474 | (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS)); | |
475 | } | |
476 | ||
477 | /** | |
478 | * ep_count_bytes_remain - get how many bytes in udc endpoint | |
479 | * @ep: udc endpoint | |
480 | * | |
481 | * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP) | |
482 | */ | |
483 | static int ep_count_bytes_remain(struct pxa_ep *ep) | |
484 | { | |
485 | if (ep->dir_in) | |
486 | return -EOPNOTSUPP; | |
487 | return udc_ep_readl(ep, UDCBCR) & 0x3ff; | |
488 | } | |
489 | ||
490 | /** | |
491 | * ep_is_empty - checks if ep has byte ready for reading | |
492 | * @ep: udc endpoint | |
493 | * | |
494 | * If endpoint is the control endpoint, checks if there are bytes in the | |
495 | * control endpoint fifo. If endpoint is a data endpoint, checks if bytes | |
496 | * are ready for reading on OUT endpoint. | |
497 | * | |
498 | * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint | |
499 | */ | |
500 | static int ep_is_empty(struct pxa_ep *ep) | |
501 | { | |
502 | int ret; | |
503 | ||
504 | if (!is_ep0(ep) && ep->dir_in) | |
505 | return -EOPNOTSUPP; | |
506 | if (is_ep0(ep)) | |
507 | ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE); | |
508 | else | |
509 | ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE); | |
510 | return ret; | |
511 | } | |
512 | ||
513 | /** | |
514 | * ep_is_full - checks if ep has place to write bytes | |
515 | * @ep: udc endpoint | |
516 | * | |
517 | * If endpoint is not the control endpoint and is an IN endpoint, checks if | |
518 | * there is place to write bytes into the endpoint. | |
519 | * | |
520 | * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint | |
521 | */ | |
522 | static int ep_is_full(struct pxa_ep *ep) | |
523 | { | |
524 | if (is_ep0(ep)) | |
525 | return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR); | |
526 | if (!ep->dir_in) | |
527 | return -EOPNOTSUPP; | |
528 | return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF)); | |
529 | } | |
530 | ||
531 | /** | |
532 | * epout_has_pkt - checks if OUT endpoint fifo has a packet available | |
533 | * @ep: pxa endpoint | |
534 | * | |
535 | * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep. | |
536 | */ | |
537 | static int epout_has_pkt(struct pxa_ep *ep) | |
538 | { | |
539 | if (!is_ep0(ep) && ep->dir_in) | |
540 | return -EOPNOTSUPP; | |
541 | if (is_ep0(ep)) | |
542 | return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC); | |
543 | return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC); | |
544 | } | |
545 | ||
546 | /** | |
547 | * set_ep0state - Set ep0 automata state | |
548 | * @dev: udc device | |
549 | * @state: state | |
550 | */ | |
551 | static void set_ep0state(struct pxa_udc *udc, int state) | |
552 | { | |
553 | struct pxa_ep *ep = &udc->pxa_ep[0]; | |
554 | char *old_stname = EP0_STNAME(udc); | |
555 | ||
556 | udc->ep0state = state; | |
557 | ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname, | |
558 | EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR), | |
559 | udc_ep_readl(ep, UDCBCR)); | |
560 | } | |
561 | ||
562 | /** | |
563 | * ep0_idle - Put control endpoint into idle state | |
564 | * @dev: udc device | |
565 | */ | |
566 | static void ep0_idle(struct pxa_udc *dev) | |
567 | { | |
568 | set_ep0state(dev, WAIT_FOR_SETUP); | |
569 | } | |
570 | ||
571 | /** | |
572 | * inc_ep_stats_reqs - Update ep stats counts | |
573 | * @ep: physical endpoint | |
574 | * @req: usb request | |
575 | * @is_in: ep direction (USB_DIR_IN or 0) | |
576 | * | |
577 | */ | |
578 | static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in) | |
579 | { | |
580 | if (is_in) | |
581 | ep->stats.in_ops++; | |
582 | else | |
583 | ep->stats.out_ops++; | |
584 | } | |
585 | ||
586 | /** | |
587 | * inc_ep_stats_bytes - Update ep stats counts | |
588 | * @ep: physical endpoint | |
589 | * @count: bytes transfered on endpoint | |
590 | * @req: usb request | |
591 | * @is_in: ep direction (USB_DIR_IN or 0) | |
592 | */ | |
593 | static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in) | |
594 | { | |
595 | if (is_in) | |
596 | ep->stats.in_bytes += count; | |
597 | else | |
598 | ep->stats.out_bytes += count; | |
599 | } | |
600 | ||
601 | /** | |
602 | * pxa_ep_setup - Sets up an usb physical endpoint | |
603 | * @ep: pxa27x physical endpoint | |
604 | * | |
605 | * Find the physical pxa27x ep, and setup its UDCCR | |
606 | */ | |
607 | static __init void pxa_ep_setup(struct pxa_ep *ep) | |
608 | { | |
609 | u32 new_udccr; | |
610 | ||
611 | new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN) | |
612 | | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN) | |
613 | | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN) | |
614 | | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN) | |
615 | | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET) | |
616 | | ((ep->dir_in) ? UDCCONR_ED : 0) | |
617 | | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS) | |
618 | | UDCCONR_EE; | |
619 | ||
620 | udc_ep_writel(ep, UDCCR, new_udccr); | |
621 | } | |
622 | ||
623 | /** | |
624 | * pxa_eps_setup - Sets up all usb physical endpoints | |
625 | * @dev: udc device | |
626 | * | |
627 | * Setup all pxa physical endpoints, except ep0 | |
628 | */ | |
629 | static __init void pxa_eps_setup(struct pxa_udc *dev) | |
630 | { | |
631 | unsigned int i; | |
632 | ||
633 | dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev); | |
634 | ||
635 | for (i = 1; i < NR_PXA_ENDPOINTS; i++) | |
636 | pxa_ep_setup(&dev->pxa_ep[i]); | |
637 | } | |
638 | ||
639 | /** | |
640 | * pxa_ep_alloc_request - Allocate usb request | |
641 | * @_ep: usb endpoint | |
642 | * @gfp_flags: | |
643 | * | |
644 | * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers | |
645 | * must still pass correctly initialized endpoints, since other controller | |
646 | * drivers may care about how it's currently set up (dma issues etc). | |
647 | */ | |
648 | static struct usb_request * | |
649 | pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) | |
650 | { | |
651 | struct pxa27x_request *req; | |
652 | ||
653 | req = kzalloc(sizeof *req, gfp_flags); | |
654 | if (!req || !_ep) | |
655 | return NULL; | |
656 | ||
657 | INIT_LIST_HEAD(&req->queue); | |
658 | req->in_use = 0; | |
659 | req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
660 | ||
661 | return &req->req; | |
662 | } | |
663 | ||
664 | /** | |
665 | * pxa_ep_free_request - Free usb request | |
666 | * @_ep: usb endpoint | |
667 | * @_req: usb request | |
668 | * | |
669 | * Wrapper around kfree to free _req | |
670 | */ | |
671 | static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
672 | { | |
673 | struct pxa27x_request *req; | |
674 | ||
675 | req = container_of(_req, struct pxa27x_request, req); | |
676 | WARN_ON(!list_empty(&req->queue)); | |
677 | kfree(req); | |
678 | } | |
679 | ||
680 | /** | |
681 | * ep_add_request - add a request to the endpoint's queue | |
682 | * @ep: usb endpoint | |
683 | * @req: usb request | |
684 | * | |
685 | * Context: ep->lock held | |
686 | * | |
687 | * Queues the request in the endpoint's queue, and enables the interrupts | |
688 | * on the endpoint. | |
689 | */ | |
690 | static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req) | |
691 | { | |
692 | if (unlikely(!req)) | |
693 | return; | |
694 | ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, | |
695 | req->req.length, udc_ep_readl(ep, UDCCSR)); | |
696 | ||
697 | req->in_use = 1; | |
698 | list_add_tail(&req->queue, &ep->queue); | |
699 | pio_irq_enable(ep); | |
700 | } | |
701 | ||
702 | /** | |
703 | * ep_del_request - removes a request from the endpoint's queue | |
704 | * @ep: usb endpoint | |
705 | * @req: usb request | |
706 | * | |
707 | * Context: ep->lock held | |
708 | * | |
709 | * Unqueue the request from the endpoint's queue. If there are no more requests | |
710 | * on the endpoint, and if it's not the control endpoint, interrupts are | |
711 | * disabled on the endpoint. | |
712 | */ | |
713 | static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req) | |
714 | { | |
715 | if (unlikely(!req)) | |
716 | return; | |
717 | ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, | |
718 | req->req.length, udc_ep_readl(ep, UDCCSR)); | |
719 | ||
720 | list_del_init(&req->queue); | |
721 | req->in_use = 0; | |
722 | if (!is_ep0(ep) && list_empty(&ep->queue)) | |
723 | pio_irq_disable(ep); | |
724 | } | |
725 | ||
726 | /** | |
727 | * req_done - Complete an usb request | |
728 | * @ep: pxa physical endpoint | |
729 | * @req: pxa request | |
730 | * @status: usb request status sent to gadget API | |
731 | * | |
732 | * Context: ep->lock held | |
733 | * | |
734 | * Retire a pxa27x usb request. Endpoint must be locked. | |
735 | */ | |
736 | static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status) | |
737 | { | |
738 | ep_del_request(ep, req); | |
739 | if (likely(req->req.status == -EINPROGRESS)) | |
740 | req->req.status = status; | |
741 | else | |
742 | status = req->req.status; | |
743 | ||
744 | if (status && status != -ESHUTDOWN) | |
745 | ep_dbg(ep, "complete req %p stat %d len %u/%u\n", | |
746 | &req->req, status, | |
747 | req->req.actual, req->req.length); | |
748 | ||
749 | req->req.complete(&req->udc_usb_ep->usb_ep, &req->req); | |
750 | } | |
751 | ||
752 | /** | |
753 | * ep_end_out_req - Ends control endpoint in request | |
754 | * @ep: physical endpoint | |
755 | * @req: pxa request | |
756 | * | |
757 | * Context: ep->lock held | |
758 | * | |
759 | * Ends endpoint in request (completes usb request). | |
760 | */ | |
761 | static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req) | |
762 | { | |
763 | inc_ep_stats_reqs(ep, !USB_DIR_IN); | |
764 | req_done(ep, req, 0); | |
765 | } | |
766 | ||
767 | /** | |
768 | * ep0_end_out_req - Ends control endpoint in request (ends data stage) | |
769 | * @ep: physical endpoint | |
770 | * @req: pxa request | |
771 | * | |
772 | * Context: ep->lock held | |
773 | * | |
774 | * Ends control endpoint in request (completes usb request), and puts | |
775 | * control endpoint into idle state | |
776 | */ | |
777 | static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req) | |
778 | { | |
779 | set_ep0state(ep->dev, OUT_STATUS_STAGE); | |
780 | ep_end_out_req(ep, req); | |
781 | ep0_idle(ep->dev); | |
782 | } | |
783 | ||
784 | /** | |
785 | * ep_end_in_req - Ends endpoint out request | |
786 | * @ep: physical endpoint | |
787 | * @req: pxa request | |
788 | * | |
789 | * Context: ep->lock held | |
790 | * | |
791 | * Ends endpoint out request (completes usb request). | |
792 | */ | |
793 | static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req) | |
794 | { | |
795 | inc_ep_stats_reqs(ep, USB_DIR_IN); | |
796 | req_done(ep, req, 0); | |
797 | } | |
798 | ||
799 | /** | |
800 | * ep0_end_in_req - Ends control endpoint out request (ends data stage) | |
801 | * @ep: physical endpoint | |
802 | * @req: pxa request | |
803 | * | |
804 | * Context: ep->lock held | |
805 | * | |
806 | * Ends control endpoint out request (completes usb request), and puts | |
807 | * control endpoint into status state | |
808 | */ | |
809 | static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req) | |
810 | { | |
811 | struct pxa_udc *udc = ep->dev; | |
812 | ||
813 | set_ep0state(udc, IN_STATUS_STAGE); | |
814 | ep_end_in_req(ep, req); | |
815 | } | |
816 | ||
817 | /** | |
818 | * nuke - Dequeue all requests | |
819 | * @ep: pxa endpoint | |
820 | * @status: usb request status | |
821 | * | |
822 | * Context: ep->lock held | |
823 | * | |
824 | * Dequeues all requests on an endpoint. As a side effect, interrupts will be | |
825 | * disabled on that endpoint (because no more requests). | |
826 | */ | |
827 | static void nuke(struct pxa_ep *ep, int status) | |
828 | { | |
829 | struct pxa27x_request *req; | |
830 | ||
831 | while (!list_empty(&ep->queue)) { | |
832 | req = list_entry(ep->queue.next, struct pxa27x_request, queue); | |
833 | req_done(ep, req, status); | |
834 | } | |
835 | } | |
836 | ||
837 | /** | |
838 | * read_packet - transfer 1 packet from an OUT endpoint into request | |
839 | * @ep: pxa physical endpoint | |
840 | * @req: usb request | |
841 | * | |
842 | * Takes bytes from OUT endpoint and transfers them info the usb request. | |
843 | * If there is less space in request than bytes received in OUT endpoint, | |
844 | * bytes are left in the OUT endpoint. | |
845 | * | |
846 | * Returns how many bytes were actually transfered | |
847 | */ | |
848 | static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req) | |
849 | { | |
850 | u32 *buf; | |
851 | int bytes_ep, bufferspace, count, i; | |
852 | ||
853 | bytes_ep = ep_count_bytes_remain(ep); | |
854 | bufferspace = req->req.length - req->req.actual; | |
855 | ||
856 | buf = (u32 *)(req->req.buf + req->req.actual); | |
857 | prefetchw(buf); | |
858 | ||
859 | if (likely(!ep_is_empty(ep))) | |
860 | count = min(bytes_ep, bufferspace); | |
861 | else /* zlp */ | |
862 | count = 0; | |
863 | ||
864 | for (i = count; i > 0; i -= 4) | |
865 | *buf++ = udc_ep_readl(ep, UDCDR); | |
866 | req->req.actual += count; | |
867 | ||
868 | udc_ep_writel(ep, UDCCSR, UDCCSR_PC); | |
869 | ||
870 | return count; | |
871 | } | |
872 | ||
873 | /** | |
874 | * write_packet - transfer 1 packet from request into an IN endpoint | |
875 | * @ep: pxa physical endpoint | |
876 | * @req: usb request | |
877 | * @max: max bytes that fit into endpoint | |
878 | * | |
879 | * Takes bytes from usb request, and transfers them into the physical | |
880 | * endpoint. If there are no bytes to transfer, doesn't write anything | |
881 | * to physical endpoint. | |
882 | * | |
883 | * Returns how many bytes were actually transfered. | |
884 | */ | |
885 | static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req, | |
886 | unsigned int max) | |
887 | { | |
888 | int length, count, remain, i; | |
889 | u32 *buf; | |
890 | u8 *buf_8; | |
891 | ||
892 | buf = (u32 *)(req->req.buf + req->req.actual); | |
893 | prefetch(buf); | |
894 | ||
895 | length = min(req->req.length - req->req.actual, max); | |
896 | req->req.actual += length; | |
897 | ||
898 | remain = length & 0x3; | |
899 | count = length & ~(0x3); | |
900 | for (i = count; i > 0 ; i -= 4) | |
901 | udc_ep_writel(ep, UDCDR, *buf++); | |
902 | ||
903 | buf_8 = (u8 *)buf; | |
904 | for (i = remain; i > 0; i--) | |
905 | udc_ep_writeb(ep, UDCDR, *buf_8++); | |
906 | ||
907 | ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain, | |
908 | udc_ep_readl(ep, UDCCSR)); | |
909 | ||
910 | return length; | |
911 | } | |
912 | ||
913 | /** | |
914 | * read_fifo - Transfer packets from OUT endpoint into usb request | |
915 | * @ep: pxa physical endpoint | |
916 | * @req: usb request | |
917 | * | |
918 | * Context: callable when in_interrupt() | |
919 | * | |
920 | * Unload as many packets as possible from the fifo we use for usb OUT | |
921 | * transfers and put them into the request. Caller should have made sure | |
922 | * there's at least one packet ready. | |
923 | * Doesn't complete the request, that's the caller's job | |
924 | * | |
925 | * Returns 1 if the request completed, 0 otherwise | |
926 | */ | |
927 | static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req) | |
928 | { | |
929 | int count, is_short, completed = 0; | |
930 | ||
931 | while (epout_has_pkt(ep)) { | |
932 | count = read_packet(ep, req); | |
933 | inc_ep_stats_bytes(ep, count, !USB_DIR_IN); | |
934 | ||
935 | is_short = (count < ep->fifo_size); | |
936 | ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", | |
937 | udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", | |
938 | &req->req, req->req.actual, req->req.length); | |
939 | ||
940 | /* completion */ | |
941 | if (is_short || req->req.actual == req->req.length) { | |
942 | completed = 1; | |
943 | break; | |
944 | } | |
945 | /* finished that packet. the next one may be waiting... */ | |
946 | } | |
947 | return completed; | |
948 | } | |
949 | ||
950 | /** | |
951 | * write_fifo - transfer packets from usb request into an IN endpoint | |
952 | * @ep: pxa physical endpoint | |
953 | * @req: pxa usb request | |
954 | * | |
955 | * Write to an IN endpoint fifo, as many packets as possible. | |
956 | * irqs will use this to write the rest later. | |
957 | * caller guarantees at least one packet buffer is ready (or a zlp). | |
958 | * Doesn't complete the request, that's the caller's job | |
959 | * | |
960 | * Returns 1 if request fully transfered, 0 if partial transfer | |
961 | */ | |
962 | static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req) | |
963 | { | |
964 | unsigned max; | |
965 | int count, is_short, is_last = 0, completed = 0, totcount = 0; | |
966 | u32 udccsr; | |
967 | ||
968 | max = ep->fifo_size; | |
969 | do { | |
970 | is_short = 0; | |
971 | ||
972 | udccsr = udc_ep_readl(ep, UDCCSR); | |
973 | if (udccsr & UDCCSR_PC) { | |
974 | ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n", | |
975 | udccsr); | |
976 | udc_ep_writel(ep, UDCCSR, UDCCSR_PC); | |
977 | } | |
978 | if (udccsr & UDCCSR_TRN) { | |
979 | ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n", | |
980 | udccsr); | |
981 | udc_ep_writel(ep, UDCCSR, UDCCSR_TRN); | |
982 | } | |
983 | ||
984 | count = write_packet(ep, req, max); | |
985 | inc_ep_stats_bytes(ep, count, USB_DIR_IN); | |
986 | totcount += count; | |
987 | ||
988 | /* last packet is usually short (or a zlp) */ | |
989 | if (unlikely(count < max)) { | |
990 | is_last = 1; | |
991 | is_short = 1; | |
992 | } else { | |
993 | if (likely(req->req.length > req->req.actual) | |
994 | || req->req.zero) | |
995 | is_last = 0; | |
996 | else | |
997 | is_last = 1; | |
998 | /* interrupt/iso maxpacket may not fill the fifo */ | |
999 | is_short = unlikely(max < ep->fifo_size); | |
1000 | } | |
1001 | ||
1002 | if (is_short) | |
1003 | udc_ep_writel(ep, UDCCSR, UDCCSR_SP); | |
1004 | ||
1005 | /* requests complete when all IN data is in the FIFO */ | |
1006 | if (is_last) { | |
1007 | completed = 1; | |
1008 | break; | |
1009 | } | |
1010 | } while (!ep_is_full(ep)); | |
1011 | ||
1012 | ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n", | |
1013 | totcount, is_last ? "/L" : "", is_short ? "/S" : "", | |
1014 | req->req.length - req->req.actual, &req->req); | |
1015 | ||
1016 | return completed; | |
1017 | } | |
1018 | ||
1019 | /** | |
1020 | * read_ep0_fifo - Transfer packets from control endpoint into usb request | |
1021 | * @ep: control endpoint | |
1022 | * @req: pxa usb request | |
1023 | * | |
1024 | * Special ep0 version of the above read_fifo. Reads as many bytes from control | |
1025 | * endpoint as can be read, and stores them into usb request (limited by request | |
1026 | * maximum length). | |
1027 | * | |
1028 | * Returns 0 if usb request only partially filled, 1 if fully filled | |
1029 | */ | |
1030 | static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) | |
1031 | { | |
1032 | int count, is_short, completed = 0; | |
1033 | ||
1034 | while (epout_has_pkt(ep)) { | |
1035 | count = read_packet(ep, req); | |
1036 | udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); | |
1037 | inc_ep_stats_bytes(ep, count, !USB_DIR_IN); | |
1038 | ||
1039 | is_short = (count < ep->fifo_size); | |
1040 | ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", | |
1041 | udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", | |
1042 | &req->req, req->req.actual, req->req.length); | |
1043 | ||
1044 | if (is_short || req->req.actual >= req->req.length) { | |
1045 | completed = 1; | |
1046 | break; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | return completed; | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * write_ep0_fifo - Send a request to control endpoint (ep0 in) | |
1055 | * @ep: control endpoint | |
1056 | * @req: request | |
1057 | * | |
1058 | * Context: callable when in_interrupt() | |
1059 | * | |
1060 | * Sends a request (or a part of the request) to the control endpoint (ep0 in). | |
1061 | * If the request doesn't fit, the remaining part will be sent from irq. | |
1062 | * The request is considered fully written only if either : | |
1063 | * - last write transfered all remaining bytes, but fifo was not fully filled | |
1064 | * - last write was a 0 length write | |
1065 | * | |
1066 | * Returns 1 if request fully written, 0 if request only partially sent | |
1067 | */ | |
1068 | static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) | |
1069 | { | |
1070 | unsigned count; | |
1071 | int is_last, is_short; | |
1072 | ||
1073 | count = write_packet(ep, req, EP0_FIFO_SIZE); | |
1074 | inc_ep_stats_bytes(ep, count, USB_DIR_IN); | |
1075 | ||
1076 | is_short = (count < EP0_FIFO_SIZE); | |
1077 | is_last = ((count == 0) || (count < EP0_FIFO_SIZE)); | |
1078 | ||
1079 | /* Sends either a short packet or a 0 length packet */ | |
1080 | if (unlikely(is_short)) | |
1081 | udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR); | |
1082 | ||
1083 | ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n", | |
1084 | count, is_short ? "/S" : "", is_last ? "/L" : "", | |
1085 | req->req.length - req->req.actual, | |
1086 | &req->req, udc_ep_readl(ep, UDCCSR)); | |
1087 | ||
1088 | return is_last; | |
1089 | } | |
1090 | ||
1091 | /** | |
1092 | * pxa_ep_queue - Queue a request into an IN endpoint | |
1093 | * @_ep: usb endpoint | |
1094 | * @_req: usb request | |
1095 | * @gfp_flags: flags | |
1096 | * | |
1097 | * Context: normally called when !in_interrupt, but callable when in_interrupt() | |
1098 | * in the special case of ep0 setup : | |
1099 | * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue) | |
1100 | * | |
1101 | * Returns 0 if succedeed, error otherwise | |
1102 | */ | |
1103 | static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req, | |
1104 | gfp_t gfp_flags) | |
1105 | { | |
1106 | struct udc_usb_ep *udc_usb_ep; | |
1107 | struct pxa_ep *ep; | |
1108 | struct pxa27x_request *req; | |
1109 | struct pxa_udc *dev; | |
1110 | unsigned long flags; | |
1111 | int rc = 0; | |
1112 | int is_first_req; | |
1113 | unsigned length; | |
1114 | ||
1115 | req = container_of(_req, struct pxa27x_request, req); | |
1116 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1117 | ||
1118 | if (unlikely(!_req || !_req->complete || !_req->buf)) | |
1119 | return -EINVAL; | |
1120 | ||
1121 | if (unlikely(!_ep)) | |
1122 | return -EINVAL; | |
1123 | ||
1124 | dev = udc_usb_ep->dev; | |
1125 | ep = udc_usb_ep->pxa_ep; | |
1126 | if (unlikely(!ep)) | |
1127 | return -EINVAL; | |
1128 | ||
1129 | dev = ep->dev; | |
1130 | if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { | |
1131 | ep_dbg(ep, "bogus device state\n"); | |
1132 | return -ESHUTDOWN; | |
1133 | } | |
1134 | ||
1135 | /* iso is always one packet per request, that's the only way | |
1136 | * we can report per-packet status. that also helps with dma. | |
1137 | */ | |
1138 | if (unlikely(EPXFERTYPE_is_ISO(ep) | |
1139 | && req->req.length > ep->fifo_size)) | |
1140 | return -EMSGSIZE; | |
1141 | ||
1142 | spin_lock_irqsave(&ep->lock, flags); | |
1143 | ||
1144 | is_first_req = list_empty(&ep->queue); | |
1145 | ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n", | |
1146 | _req, is_first_req ? "yes" : "no", | |
1147 | _req->length, _req->buf); | |
1148 | ||
1149 | if (!ep->enabled) { | |
1150 | _req->status = -ESHUTDOWN; | |
1151 | rc = -ESHUTDOWN; | |
1152 | goto out; | |
1153 | } | |
1154 | ||
1155 | if (req->in_use) { | |
1156 | ep_err(ep, "refusing to queue req %p (already queued)\n", req); | |
1157 | goto out; | |
1158 | } | |
1159 | ||
1160 | length = _req->length; | |
1161 | _req->status = -EINPROGRESS; | |
1162 | _req->actual = 0; | |
1163 | ||
1164 | ep_add_request(ep, req); | |
1165 | ||
1166 | if (is_ep0(ep)) { | |
1167 | switch (dev->ep0state) { | |
1168 | case WAIT_ACK_SET_CONF_INTERF: | |
1169 | if (length == 0) { | |
1170 | ep_end_in_req(ep, req); | |
1171 | } else { | |
1172 | ep_err(ep, "got a request of %d bytes while" | |
1173 | "in state WATI_ACK_SET_CONF_INTERF\n", | |
1174 | length); | |
1175 | ep_del_request(ep, req); | |
1176 | rc = -EL2HLT; | |
1177 | } | |
1178 | ep0_idle(ep->dev); | |
1179 | break; | |
1180 | case IN_DATA_STAGE: | |
1181 | if (!ep_is_full(ep)) | |
1182 | if (write_ep0_fifo(ep, req)) | |
1183 | ep0_end_in_req(ep, req); | |
1184 | break; | |
1185 | case OUT_DATA_STAGE: | |
1186 | if ((length == 0) || !epout_has_pkt(ep)) | |
1187 | if (read_ep0_fifo(ep, req)) | |
1188 | ep0_end_out_req(ep, req); | |
1189 | break; | |
1190 | default: | |
1191 | ep_err(ep, "odd state %s to send me a request\n", | |
1192 | EP0_STNAME(ep->dev)); | |
1193 | ep_del_request(ep, req); | |
1194 | rc = -EL2HLT; | |
1195 | break; | |
1196 | } | |
1197 | } else { | |
1198 | handle_ep(ep); | |
1199 | } | |
1200 | ||
1201 | out: | |
1202 | spin_unlock_irqrestore(&ep->lock, flags); | |
1203 | return rc; | |
1204 | } | |
1205 | ||
1206 | /** | |
1207 | * pxa_ep_dequeue - Dequeue one request | |
1208 | * @_ep: usb endpoint | |
1209 | * @_req: usb request | |
1210 | * | |
1211 | * Return 0 if no error, -EINVAL or -ECONNRESET otherwise | |
1212 | */ | |
1213 | static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
1214 | { | |
1215 | struct pxa_ep *ep; | |
1216 | struct udc_usb_ep *udc_usb_ep; | |
1217 | struct pxa27x_request *req; | |
1218 | unsigned long flags; | |
1219 | int rc; | |
1220 | ||
1221 | if (!_ep) | |
1222 | return -EINVAL; | |
1223 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1224 | ep = udc_usb_ep->pxa_ep; | |
1225 | if (!ep || is_ep0(ep)) | |
1226 | return -EINVAL; | |
1227 | ||
1228 | spin_lock_irqsave(&ep->lock, flags); | |
1229 | ||
1230 | /* make sure it's actually queued on this endpoint */ | |
1231 | list_for_each_entry(req, &ep->queue, queue) { | |
1232 | if (&req->req == _req) | |
1233 | break; | |
1234 | } | |
1235 | ||
1236 | rc = -EINVAL; | |
1237 | if (&req->req != _req) | |
1238 | goto out; | |
1239 | ||
1240 | rc = 0; | |
1241 | req_done(ep, req, -ECONNRESET); | |
1242 | out: | |
1243 | spin_unlock_irqrestore(&ep->lock, flags); | |
1244 | return rc; | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * pxa_ep_set_halt - Halts operations on one endpoint | |
1249 | * @_ep: usb endpoint | |
1250 | * @value: | |
1251 | * | |
1252 | * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise | |
1253 | */ | |
1254 | static int pxa_ep_set_halt(struct usb_ep *_ep, int value) | |
1255 | { | |
1256 | struct pxa_ep *ep; | |
1257 | struct udc_usb_ep *udc_usb_ep; | |
1258 | unsigned long flags; | |
1259 | int rc; | |
1260 | ||
1261 | ||
1262 | if (!_ep) | |
1263 | return -EINVAL; | |
1264 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1265 | ep = udc_usb_ep->pxa_ep; | |
1266 | if (!ep || is_ep0(ep)) | |
1267 | return -EINVAL; | |
1268 | ||
1269 | if (value == 0) { | |
1270 | /* | |
1271 | * This path (reset toggle+halt) is needed to implement | |
1272 | * SET_INTERFACE on normal hardware. but it can't be | |
1273 | * done from software on the PXA UDC, and the hardware | |
1274 | * forgets to do it as part of SET_INTERFACE automagic. | |
1275 | */ | |
1276 | ep_dbg(ep, "only host can clear halt\n"); | |
1277 | return -EROFS; | |
1278 | } | |
1279 | ||
1280 | spin_lock_irqsave(&ep->lock, flags); | |
1281 | ||
1282 | rc = -EAGAIN; | |
1283 | if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue))) | |
1284 | goto out; | |
1285 | ||
1286 | /* FST, FEF bits are the same for control and non control endpoints */ | |
1287 | rc = 0; | |
1288 | udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF); | |
1289 | if (is_ep0(ep)) | |
1290 | set_ep0state(ep->dev, STALL); | |
1291 | ||
1292 | out: | |
1293 | spin_unlock_irqrestore(&ep->lock, flags); | |
1294 | return rc; | |
1295 | } | |
1296 | ||
1297 | /** | |
1298 | * pxa_ep_fifo_status - Get how many bytes in physical endpoint | |
1299 | * @_ep: usb endpoint | |
1300 | * | |
1301 | * Returns number of bytes in OUT fifos. Broken for IN fifos. | |
1302 | */ | |
1303 | static int pxa_ep_fifo_status(struct usb_ep *_ep) | |
1304 | { | |
1305 | struct pxa_ep *ep; | |
1306 | struct udc_usb_ep *udc_usb_ep; | |
1307 | ||
1308 | if (!_ep) | |
1309 | return -ENODEV; | |
1310 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1311 | ep = udc_usb_ep->pxa_ep; | |
1312 | if (!ep || is_ep0(ep)) | |
1313 | return -ENODEV; | |
1314 | ||
1315 | if (ep->dir_in) | |
1316 | return -EOPNOTSUPP; | |
1317 | if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep)) | |
1318 | return 0; | |
1319 | else | |
1320 | return ep_count_bytes_remain(ep) + 1; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * pxa_ep_fifo_flush - Flushes one endpoint | |
1325 | * @_ep: usb endpoint | |
1326 | * | |
1327 | * Discards all data in one endpoint(IN or OUT), except control endpoint. | |
1328 | */ | |
1329 | static void pxa_ep_fifo_flush(struct usb_ep *_ep) | |
1330 | { | |
1331 | struct pxa_ep *ep; | |
1332 | struct udc_usb_ep *udc_usb_ep; | |
1333 | unsigned long flags; | |
1334 | ||
1335 | if (!_ep) | |
1336 | return; | |
1337 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1338 | ep = udc_usb_ep->pxa_ep; | |
1339 | if (!ep || is_ep0(ep)) | |
1340 | return; | |
1341 | ||
1342 | spin_lock_irqsave(&ep->lock, flags); | |
1343 | ||
1344 | if (unlikely(!list_empty(&ep->queue))) | |
1345 | ep_dbg(ep, "called while queue list not empty\n"); | |
1346 | ep_dbg(ep, "called\n"); | |
1347 | ||
1348 | /* for OUT, just read and discard the FIFO contents. */ | |
1349 | if (!ep->dir_in) { | |
1350 | while (!ep_is_empty(ep)) | |
1351 | udc_ep_readl(ep, UDCDR); | |
1352 | } else { | |
1353 | /* most IN status is the same, but ISO can't stall */ | |
1354 | udc_ep_writel(ep, UDCCSR, | |
1355 | UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN | |
1356 | | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST)); | |
1357 | } | |
1358 | ||
1359 | spin_unlock_irqrestore(&ep->lock, flags); | |
1360 | ||
1361 | return; | |
1362 | } | |
1363 | ||
1364 | /** | |
1365 | * pxa_ep_enable - Enables usb endpoint | |
1366 | * @_ep: usb endpoint | |
1367 | * @desc: usb endpoint descriptor | |
1368 | * | |
1369 | * Nothing much to do here, as ep configuration is done once and for all | |
1370 | * before udc is enabled. After udc enable, no physical endpoint configuration | |
1371 | * can be changed. | |
1372 | * Function makes sanity checks and flushes the endpoint. | |
1373 | */ | |
1374 | static int pxa_ep_enable(struct usb_ep *_ep, | |
1375 | const struct usb_endpoint_descriptor *desc) | |
1376 | { | |
1377 | struct pxa_ep *ep; | |
1378 | struct udc_usb_ep *udc_usb_ep; | |
1379 | struct pxa_udc *udc; | |
1380 | ||
1381 | if (!_ep || !desc) | |
1382 | return -EINVAL; | |
1383 | ||
1384 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1385 | if (udc_usb_ep->pxa_ep) { | |
1386 | ep = udc_usb_ep->pxa_ep; | |
1387 | ep_warn(ep, "usb_ep %s already enabled, doing nothing\n", | |
1388 | _ep->name); | |
1389 | } else { | |
1390 | ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep); | |
1391 | } | |
1392 | ||
1393 | if (!ep || is_ep0(ep)) { | |
1394 | dev_err(udc_usb_ep->dev->dev, | |
1395 | "unable to match pxa_ep for ep %s\n", | |
1396 | _ep->name); | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | ||
1400 | if ((desc->bDescriptorType != USB_DT_ENDPOINT) | |
1401 | || (ep->type != usb_endpoint_type(desc))) { | |
1402 | ep_err(ep, "type mismatch\n"); | |
1403 | return -EINVAL; | |
1404 | } | |
1405 | ||
1406 | if (ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) { | |
1407 | ep_err(ep, "bad maxpacket\n"); | |
1408 | return -ERANGE; | |
1409 | } | |
1410 | ||
1411 | udc_usb_ep->pxa_ep = ep; | |
1412 | udc = ep->dev; | |
1413 | ||
1414 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { | |
1415 | ep_err(ep, "bogus device state\n"); | |
1416 | return -ESHUTDOWN; | |
1417 | } | |
1418 | ||
1419 | ep->enabled = 1; | |
1420 | ||
1421 | /* flush fifo (mostly for OUT buffers) */ | |
1422 | pxa_ep_fifo_flush(_ep); | |
1423 | ||
1424 | ep_dbg(ep, "enabled\n"); | |
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | /** | |
1429 | * pxa_ep_disable - Disable usb endpoint | |
1430 | * @_ep: usb endpoint | |
1431 | * | |
1432 | * Same as for pxa_ep_enable, no physical endpoint configuration can be | |
1433 | * changed. | |
1434 | * Function flushes the endpoint and related requests. | |
1435 | */ | |
1436 | static int pxa_ep_disable(struct usb_ep *_ep) | |
1437 | { | |
1438 | struct pxa_ep *ep; | |
1439 | struct udc_usb_ep *udc_usb_ep; | |
1440 | unsigned long flags; | |
1441 | ||
1442 | if (!_ep) | |
1443 | return -EINVAL; | |
1444 | ||
1445 | udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep); | |
1446 | ep = udc_usb_ep->pxa_ep; | |
1447 | if (!ep || is_ep0(ep) || !list_empty(&ep->queue)) | |
1448 | return -EINVAL; | |
1449 | ||
1450 | spin_lock_irqsave(&ep->lock, flags); | |
1451 | ep->enabled = 0; | |
1452 | nuke(ep, -ESHUTDOWN); | |
1453 | spin_unlock_irqrestore(&ep->lock, flags); | |
1454 | ||
1455 | pxa_ep_fifo_flush(_ep); | |
1456 | udc_usb_ep->pxa_ep = NULL; | |
1457 | ||
1458 | ep_dbg(ep, "disabled\n"); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static struct usb_ep_ops pxa_ep_ops = { | |
1463 | .enable = pxa_ep_enable, | |
1464 | .disable = pxa_ep_disable, | |
1465 | ||
1466 | .alloc_request = pxa_ep_alloc_request, | |
1467 | .free_request = pxa_ep_free_request, | |
1468 | ||
1469 | .queue = pxa_ep_queue, | |
1470 | .dequeue = pxa_ep_dequeue, | |
1471 | ||
1472 | .set_halt = pxa_ep_set_halt, | |
1473 | .fifo_status = pxa_ep_fifo_status, | |
1474 | .fifo_flush = pxa_ep_fifo_flush, | |
1475 | }; | |
1476 | ||
1477 | ||
1478 | /** | |
1479 | * pxa_udc_get_frame - Returns usb frame number | |
1480 | * @_gadget: usb gadget | |
1481 | */ | |
1482 | static int pxa_udc_get_frame(struct usb_gadget *_gadget) | |
1483 | { | |
1484 | struct pxa_udc *udc = to_gadget_udc(_gadget); | |
1485 | ||
1486 | return (udc_readl(udc, UDCFNR) & 0x7ff); | |
1487 | } | |
1488 | ||
1489 | /** | |
1490 | * pxa_udc_wakeup - Force udc device out of suspend | |
1491 | * @_gadget: usb gadget | |
1492 | * | |
1493 | * Returns 0 if succesfull, error code otherwise | |
1494 | */ | |
1495 | static int pxa_udc_wakeup(struct usb_gadget *_gadget) | |
1496 | { | |
1497 | struct pxa_udc *udc = to_gadget_udc(_gadget); | |
1498 | ||
1499 | /* host may not have enabled remote wakeup */ | |
1500 | if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0) | |
1501 | return -EHOSTUNREACH; | |
1502 | udc_set_mask_UDCCR(udc, UDCCR_UDR); | |
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | static const struct usb_gadget_ops pxa_udc_ops = { | |
1507 | .get_frame = pxa_udc_get_frame, | |
1508 | .wakeup = pxa_udc_wakeup, | |
1509 | /* current versions must always be self-powered */ | |
1510 | }; | |
1511 | ||
1512 | /** | |
1513 | * udc_disable - disable udc device controller | |
1514 | * @udc: udc device | |
1515 | * | |
1516 | * Disables the udc device : disables clocks, udc interrupts, control endpoint | |
1517 | * interrupts. | |
1518 | */ | |
1519 | static void udc_disable(struct pxa_udc *udc) | |
1520 | { | |
1521 | udc_writel(udc, UDCICR0, 0); | |
1522 | udc_writel(udc, UDCICR1, 0); | |
1523 | ||
1524 | udc_clear_mask_UDCCR(udc, UDCCR_UDE); | |
1525 | clk_disable(udc->clk); | |
1526 | ||
1527 | ep0_idle(udc); | |
1528 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1529 | udc->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); | |
1530 | } | |
1531 | ||
1532 | /** | |
1533 | * udc_init_data - Initialize udc device data structures | |
1534 | * @dev: udc device | |
1535 | * | |
1536 | * Initializes gadget endpoint list, endpoints locks. No action is taken | |
1537 | * on the hardware. | |
1538 | */ | |
1539 | static __init void udc_init_data(struct pxa_udc *dev) | |
1540 | { | |
1541 | int i; | |
1542 | struct pxa_ep *ep; | |
1543 | ||
1544 | /* device/ep0 records init */ | |
1545 | INIT_LIST_HEAD(&dev->gadget.ep_list); | |
1546 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); | |
1547 | dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0]; | |
1548 | ep0_idle(dev); | |
d75379a5 RJ |
1549 | |
1550 | /* PXA endpoints init */ | |
1551 | for (i = 0; i < NR_PXA_ENDPOINTS; i++) { | |
1552 | ep = &dev->pxa_ep[i]; | |
1553 | ||
1554 | ep->enabled = is_ep0(ep); | |
1555 | INIT_LIST_HEAD(&ep->queue); | |
1556 | spin_lock_init(&ep->lock); | |
1557 | } | |
1558 | ||
1559 | /* USB endpoints init */ | |
1560 | for (i = 0; i < NR_USB_ENDPOINTS; i++) | |
1561 | if (i != 0) | |
1562 | list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list, | |
1563 | &dev->gadget.ep_list); | |
1564 | } | |
1565 | ||
1566 | /** | |
1567 | * udc_enable - Enables the udc device | |
1568 | * @dev: udc device | |
1569 | * | |
1570 | * Enables the udc device : enables clocks, udc interrupts, control endpoint | |
1571 | * interrupts, sets usb as UDC client and setups endpoints. | |
1572 | */ | |
1573 | static void udc_enable(struct pxa_udc *udc) | |
1574 | { | |
1575 | udc_writel(udc, UDCICR0, 0); | |
1576 | udc_writel(udc, UDCICR1, 0); | |
1577 | udc_writel(udc, UP2OCR, UP2OCR_HXOE); | |
1578 | udc_clear_mask_UDCCR(udc, UDCCR_UDE); | |
1579 | ||
1580 | clk_enable(udc->clk); | |
1581 | ||
1582 | ep0_idle(udc); | |
1583 | udc->gadget.speed = USB_SPEED_FULL; | |
1584 | memset(&udc->stats, 0, sizeof(udc->stats)); | |
1585 | ||
1586 | udc_set_mask_UDCCR(udc, UDCCR_UDE); | |
1587 | udelay(2); | |
1588 | if (udc_readl(udc, UDCCR) & UDCCR_EMCE) | |
1589 | dev_err(udc->dev, "Configuration errors, udc disabled\n"); | |
1590 | ||
1591 | /* | |
1592 | * Caller must be able to sleep in order to cope with startup transients | |
1593 | */ | |
1594 | msleep(100); | |
1595 | ||
1596 | /* enable suspend/resume and reset irqs */ | |
1597 | udc_writel(udc, UDCICR1, | |
1598 | UDCICR1_IECC | UDCICR1_IERU | |
1599 | | UDCICR1_IESU | UDCICR1_IERS); | |
1600 | ||
1601 | /* enable ep0 irqs */ | |
1602 | pio_irq_enable(&udc->pxa_ep[0]); | |
1603 | ||
1604 | dev_info(udc->dev, "UDC connecting\n"); | |
1605 | if (udc->mach->udc_command) | |
1606 | udc->mach->udc_command(PXA2XX_UDC_CMD_CONNECT); | |
1607 | } | |
1608 | ||
1609 | /** | |
1610 | * usb_gadget_register_driver - Register gadget driver | |
1611 | * @driver: gadget driver | |
1612 | * | |
1613 | * When a driver is successfully registered, it will receive control requests | |
1614 | * including set_configuration(), which enables non-control requests. Then | |
1615 | * usb traffic follows until a disconnect is reported. Then a host may connect | |
1616 | * again, or the driver might get unbound. | |
1617 | * | |
1618 | * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise | |
1619 | */ | |
1620 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1621 | { | |
1622 | struct pxa_udc *udc = the_controller; | |
1623 | int retval; | |
1624 | ||
1625 | if (!driver || driver->speed != USB_SPEED_FULL || !driver->bind | |
1626 | || !driver->disconnect || !driver->setup) | |
1627 | return -EINVAL; | |
1628 | if (!udc) | |
1629 | return -ENODEV; | |
1630 | if (udc->driver) | |
1631 | return -EBUSY; | |
1632 | ||
1633 | /* first hook up the driver ... */ | |
1634 | udc->driver = driver; | |
1635 | udc->gadget.dev.driver = &driver->driver; | |
1636 | ||
1637 | retval = device_add(&udc->gadget.dev); | |
1638 | if (retval) { | |
1639 | dev_err(udc->dev, "device_add error %d\n", retval); | |
1640 | goto add_fail; | |
1641 | } | |
1642 | retval = driver->bind(&udc->gadget); | |
1643 | if (retval) { | |
1644 | dev_err(udc->dev, "bind to driver %s --> error %d\n", | |
1645 | driver->driver.name, retval); | |
1646 | goto bind_fail; | |
1647 | } | |
1648 | dev_dbg(udc->dev, "registered gadget driver '%s'\n", | |
1649 | driver->driver.name); | |
1650 | ||
1651 | udc_enable(udc); | |
1652 | return 0; | |
1653 | ||
1654 | bind_fail: | |
1655 | device_del(&udc->gadget.dev); | |
1656 | add_fail: | |
1657 | udc->driver = NULL; | |
1658 | udc->gadget.dev.driver = NULL; | |
1659 | return retval; | |
1660 | } | |
1661 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1662 | ||
1663 | ||
1664 | /** | |
1665 | * stop_activity - Stops udc endpoints | |
1666 | * @udc: udc device | |
1667 | * @driver: gadget driver | |
1668 | * | |
1669 | * Disables all udc endpoints (even control endpoint), report disconnect to | |
1670 | * the gadget user. | |
1671 | */ | |
1672 | static void stop_activity(struct pxa_udc *udc, struct usb_gadget_driver *driver) | |
1673 | { | |
1674 | int i; | |
1675 | ||
1676 | /* don't disconnect drivers more than once */ | |
1677 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
1678 | driver = NULL; | |
1679 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1680 | ||
1681 | for (i = 0; i < NR_USB_ENDPOINTS; i++) | |
1682 | pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep); | |
1683 | ||
1684 | if (driver) | |
1685 | driver->disconnect(&udc->gadget); | |
1686 | } | |
1687 | ||
1688 | /** | |
1689 | * usb_gadget_unregister_driver - Unregister the gadget driver | |
1690 | * @driver: gadget driver | |
1691 | * | |
1692 | * Returns 0 if no error, -ENODEV, -EINVAL otherwise | |
1693 | */ | |
1694 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1695 | { | |
1696 | struct pxa_udc *udc = the_controller; | |
1697 | ||
1698 | if (!udc) | |
1699 | return -ENODEV; | |
1700 | if (!driver || driver != udc->driver || !driver->unbind) | |
1701 | return -EINVAL; | |
1702 | ||
1703 | stop_activity(udc, driver); | |
1704 | udc_disable(udc); | |
1705 | ||
1706 | driver->unbind(&udc->gadget); | |
1707 | udc->driver = NULL; | |
1708 | ||
1709 | device_del(&udc->gadget.dev); | |
1710 | ||
1711 | dev_info(udc->dev, "unregistered gadget driver '%s'\n", | |
1712 | driver->driver.name); | |
1713 | return 0; | |
1714 | } | |
1715 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1716 | ||
1717 | /** | |
1718 | * handle_ep0_ctrl_req - handle control endpoint control request | |
1719 | * @udc: udc device | |
1720 | * @req: control request | |
1721 | */ | |
1722 | static void handle_ep0_ctrl_req(struct pxa_udc *udc, | |
1723 | struct pxa27x_request *req) | |
1724 | { | |
1725 | struct pxa_ep *ep = &udc->pxa_ep[0]; | |
1726 | union { | |
1727 | struct usb_ctrlrequest r; | |
1728 | u32 word[2]; | |
1729 | } u; | |
1730 | int i; | |
1731 | int have_extrabytes = 0; | |
1732 | ||
1733 | nuke(ep, -EPROTO); | |
1734 | ||
1735 | /* read SETUP packet */ | |
1736 | for (i = 0; i < 2; i++) { | |
1737 | if (unlikely(ep_is_empty(ep))) | |
1738 | goto stall; | |
1739 | u.word[i] = udc_ep_readl(ep, UDCDR); | |
1740 | } | |
1741 | ||
1742 | have_extrabytes = !ep_is_empty(ep); | |
1743 | while (!ep_is_empty(ep)) { | |
1744 | i = udc_ep_readl(ep, UDCDR); | |
1745 | ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i); | |
1746 | } | |
1747 | ||
d75379a5 RJ |
1748 | ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n", |
1749 | u.r.bRequestType, u.r.bRequest, | |
5a59bc54 RJ |
1750 | le16_to_cpu(u.r.wValue), le16_to_cpu(u.r.wIndex), |
1751 | le16_to_cpu(u.r.wLength)); | |
d75379a5 RJ |
1752 | if (unlikely(have_extrabytes)) |
1753 | goto stall; | |
1754 | ||
1755 | if (u.r.bRequestType & USB_DIR_IN) | |
1756 | set_ep0state(udc, IN_DATA_STAGE); | |
1757 | else | |
1758 | set_ep0state(udc, OUT_DATA_STAGE); | |
1759 | ||
1760 | /* Tell UDC to enter Data Stage */ | |
1761 | udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC); | |
1762 | ||
1763 | i = udc->driver->setup(&udc->gadget, &u.r); | |
1764 | if (i < 0) | |
1765 | goto stall; | |
1766 | out: | |
1767 | return; | |
1768 | stall: | |
1769 | ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n", | |
1770 | udc_ep_readl(ep, UDCCSR), i); | |
1771 | udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF); | |
1772 | set_ep0state(udc, STALL); | |
1773 | goto out; | |
1774 | } | |
1775 | ||
1776 | /** | |
1777 | * handle_ep0 - Handle control endpoint data transfers | |
1778 | * @udc: udc device | |
1779 | * @fifo_irq: 1 if triggered by fifo service type irq | |
1780 | * @opc_irq: 1 if triggered by output packet complete type irq | |
1781 | * | |
1782 | * Context : when in_interrupt() or with ep->lock held | |
1783 | * | |
1784 | * Tries to transfer all pending request data into the endpoint and/or | |
1785 | * transfer all pending data in the endpoint into usb requests. | |
1786 | * Handles states of ep0 automata. | |
1787 | * | |
1788 | * PXA27x hardware handles several standard usb control requests without | |
1789 | * driver notification. The requests fully handled by hardware are : | |
1790 | * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE, | |
1791 | * GET_STATUS | |
1792 | * The requests handled by hardware, but with irq notification are : | |
1793 | * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE | |
1794 | * The remaining standard requests really handled by handle_ep0 are : | |
1795 | * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests. | |
1796 | * Requests standardized outside of USB 2.0 chapter 9 are handled more | |
1797 | * uniformly, by gadget drivers. | |
1798 | * | |
1799 | * The control endpoint state machine is _not_ USB spec compliant, it's even | |
1800 | * hardly compliant with Intel PXA270 developers guide. | |
1801 | * The key points which inferred this state machine are : | |
1802 | * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by | |
1803 | * software. | |
1804 | * - on every OUT packet received, UDCCSR0_OPC is raised and held until | |
1805 | * cleared by software. | |
1806 | * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it | |
1807 | * before reading ep0. | |
1808 | * - irq can be called on a "packet complete" event (opc_irq=1), while | |
1809 | * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms | |
1810 | * from experimentation). | |
1811 | * - as UDCCSR0_SA can be activated while in irq handling, and clearing | |
1812 | * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC | |
1813 | * => we never actually read the "status stage" packet of an IN data stage | |
1814 | * => this is not documented in Intel documentation | |
1815 | * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA | |
1816 | * STAGE. The driver add STATUS STAGE to send last zero length packet in | |
1817 | * OUT_STATUS_STAGE. | |
1818 | * - special attention was needed for IN_STATUS_STAGE. If a packet complete | |
1819 | * event is detected, we terminate the status stage without ackowledging the | |
1820 | * packet (not to risk to loose a potential SETUP packet) | |
1821 | */ | |
1822 | static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) | |
1823 | { | |
1824 | u32 udccsr0; | |
1825 | struct pxa_ep *ep = &udc->pxa_ep[0]; | |
1826 | struct pxa27x_request *req = NULL; | |
1827 | int completed = 0; | |
1828 | ||
1829 | udccsr0 = udc_ep_readl(ep, UDCCSR); | |
1830 | ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n", | |
1831 | EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR), | |
1832 | (fifo_irq << 1 | opc_irq)); | |
1833 | ||
1834 | if (!list_empty(&ep->queue)) | |
1835 | req = list_entry(ep->queue.next, struct pxa27x_request, queue); | |
1836 | ||
1837 | if (udccsr0 & UDCCSR0_SST) { | |
1838 | ep_dbg(ep, "clearing stall status\n"); | |
1839 | nuke(ep, -EPIPE); | |
1840 | udc_ep_writel(ep, UDCCSR, UDCCSR0_SST); | |
1841 | ep0_idle(udc); | |
1842 | } | |
1843 | ||
1844 | if (udccsr0 & UDCCSR0_SA) { | |
1845 | nuke(ep, 0); | |
1846 | set_ep0state(udc, SETUP_STAGE); | |
1847 | } | |
1848 | ||
1849 | switch (udc->ep0state) { | |
1850 | case WAIT_FOR_SETUP: | |
1851 | /* | |
1852 | * Hardware bug : beware, we cannot clear OPC, since we would | |
1853 | * miss a potential OPC irq for a setup packet. | |
1854 | * So, we only do ... nothing, and hope for a next irq with | |
1855 | * UDCCSR0_SA set. | |
1856 | */ | |
1857 | break; | |
1858 | case SETUP_STAGE: | |
1859 | udccsr0 &= UDCCSR0_CTRL_REQ_MASK; | |
1860 | if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK)) | |
1861 | handle_ep0_ctrl_req(udc, req); | |
1862 | break; | |
1863 | case IN_DATA_STAGE: /* GET_DESCRIPTOR */ | |
1864 | if (epout_has_pkt(ep)) | |
1865 | udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); | |
1866 | if (req && !ep_is_full(ep)) | |
1867 | completed = write_ep0_fifo(ep, req); | |
1868 | if (completed) | |
1869 | ep0_end_in_req(ep, req); | |
1870 | break; | |
1871 | case OUT_DATA_STAGE: /* SET_DESCRIPTOR */ | |
1872 | if (epout_has_pkt(ep) && req) | |
1873 | completed = read_ep0_fifo(ep, req); | |
1874 | if (completed) | |
1875 | ep0_end_out_req(ep, req); | |
1876 | break; | |
1877 | case STALL: | |
1878 | udc_ep_writel(ep, UDCCSR, UDCCSR0_FST); | |
1879 | break; | |
1880 | case IN_STATUS_STAGE: | |
1881 | /* | |
1882 | * Hardware bug : beware, we cannot clear OPC, since we would | |
1883 | * miss a potential PC irq for a setup packet. | |
1884 | * So, we only put the ep0 into WAIT_FOR_SETUP state. | |
1885 | */ | |
1886 | if (opc_irq) | |
1887 | ep0_idle(udc); | |
1888 | break; | |
1889 | case OUT_STATUS_STAGE: | |
1890 | case WAIT_ACK_SET_CONF_INTERF: | |
1891 | ep_warn(ep, "should never get in %s state here!!!\n", | |
1892 | EP0_STNAME(ep->dev)); | |
1893 | ep0_idle(udc); | |
1894 | break; | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * handle_ep - Handle endpoint data tranfers | |
1900 | * @ep: pxa physical endpoint | |
1901 | * | |
1902 | * Tries to transfer all pending request data into the endpoint and/or | |
1903 | * transfer all pending data in the endpoint into usb requests. | |
1904 | * | |
1905 | * Is always called when in_interrupt() or with ep->lock held. | |
1906 | */ | |
1907 | static void handle_ep(struct pxa_ep *ep) | |
1908 | { | |
1909 | struct pxa27x_request *req; | |
1910 | int completed; | |
1911 | u32 udccsr; | |
1912 | int is_in = ep->dir_in; | |
1913 | int loop = 0; | |
1914 | ||
1915 | do { | |
1916 | completed = 0; | |
1917 | udccsr = udc_ep_readl(ep, UDCCSR); | |
1918 | if (likely(!list_empty(&ep->queue))) | |
1919 | req = list_entry(ep->queue.next, | |
1920 | struct pxa27x_request, queue); | |
1921 | else | |
1922 | req = NULL; | |
1923 | ||
1924 | ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n", | |
1925 | req, udccsr, loop++); | |
1926 | ||
1927 | if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN))) | |
1928 | udc_ep_writel(ep, UDCCSR, | |
1929 | udccsr & (UDCCSR_SST | UDCCSR_TRN)); | |
1930 | if (!req) | |
1931 | break; | |
1932 | ||
1933 | if (unlikely(is_in)) { | |
1934 | if (likely(!ep_is_full(ep))) | |
1935 | completed = write_fifo(ep, req); | |
1936 | if (completed) | |
1937 | ep_end_in_req(ep, req); | |
1938 | } else { | |
1939 | if (likely(epout_has_pkt(ep))) | |
1940 | completed = read_fifo(ep, req); | |
1941 | if (completed) | |
1942 | ep_end_out_req(ep, req); | |
1943 | } | |
1944 | } while (completed); | |
1945 | } | |
1946 | ||
1947 | /** | |
1948 | * pxa27x_change_configuration - Handle SET_CONF usb request notification | |
1949 | * @udc: udc device | |
1950 | * @config: usb configuration | |
1951 | * | |
1952 | * Post the request to upper level. | |
1953 | * Don't use any pxa specific harware configuration capabilities | |
1954 | */ | |
1955 | static void pxa27x_change_configuration(struct pxa_udc *udc, int config) | |
1956 | { | |
1957 | struct usb_ctrlrequest req ; | |
1958 | ||
1959 | dev_dbg(udc->dev, "config=%d\n", config); | |
1960 | ||
1961 | udc->config = config; | |
1962 | udc->last_interface = 0; | |
1963 | udc->last_alternate = 0; | |
1964 | ||
1965 | req.bRequestType = 0; | |
1966 | req.bRequest = USB_REQ_SET_CONFIGURATION; | |
1967 | req.wValue = config; | |
1968 | req.wIndex = 0; | |
1969 | req.wLength = 0; | |
1970 | ||
1971 | set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); | |
1972 | udc->driver->setup(&udc->gadget, &req); | |
1973 | } | |
1974 | ||
1975 | /** | |
1976 | * pxa27x_change_interface - Handle SET_INTERF usb request notification | |
1977 | * @udc: udc device | |
1978 | * @iface: interface number | |
1979 | * @alt: alternate setting number | |
1980 | * | |
1981 | * Post the request to upper level. | |
1982 | * Don't use any pxa specific harware configuration capabilities | |
1983 | */ | |
1984 | static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt) | |
1985 | { | |
1986 | struct usb_ctrlrequest req; | |
1987 | ||
1988 | dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt); | |
1989 | ||
1990 | udc->last_interface = iface; | |
1991 | udc->last_alternate = alt; | |
1992 | ||
1993 | req.bRequestType = USB_RECIP_INTERFACE; | |
1994 | req.bRequest = USB_REQ_SET_INTERFACE; | |
1995 | req.wValue = alt; | |
1996 | req.wIndex = iface; | |
1997 | req.wLength = 0; | |
1998 | ||
1999 | set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF); | |
2000 | udc->driver->setup(&udc->gadget, &req); | |
2001 | } | |
2002 | ||
2003 | /* | |
2004 | * irq_handle_data - Handle data transfer | |
2005 | * @irq: irq IRQ number | |
2006 | * @udc: dev pxa_udc device structure | |
2007 | * | |
2008 | * Called from irq handler, transferts data to or from endpoint to queue | |
2009 | */ | |
2010 | static void irq_handle_data(int irq, struct pxa_udc *udc) | |
2011 | { | |
2012 | int i; | |
2013 | struct pxa_ep *ep; | |
2014 | u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK; | |
2015 | u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK; | |
2016 | ||
2017 | if (udcisr0 & UDCISR_INT_MASK) { | |
2018 | udc->pxa_ep[0].stats.irqs++; | |
2019 | udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK)); | |
2020 | handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR), | |
2021 | !!(udcisr0 & UDCICR_PKTCOMPL)); | |
2022 | } | |
2023 | ||
2024 | udcisr0 >>= 2; | |
2025 | for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) { | |
2026 | if (!(udcisr0 & UDCISR_INT_MASK)) | |
2027 | continue; | |
2028 | ||
2029 | udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK)); | |
2030 | ep = &udc->pxa_ep[i]; | |
2031 | ep->stats.irqs++; | |
2032 | handle_ep(ep); | |
2033 | } | |
2034 | ||
2035 | for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) { | |
2036 | udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK)); | |
2037 | if (!(udcisr1 & UDCISR_INT_MASK)) | |
2038 | continue; | |
2039 | ||
2040 | ep = &udc->pxa_ep[i]; | |
2041 | ep->stats.irqs++; | |
2042 | handle_ep(ep); | |
2043 | } | |
2044 | ||
2045 | } | |
2046 | ||
2047 | /** | |
2048 | * irq_udc_suspend - Handle IRQ "UDC Suspend" | |
2049 | * @udc: udc device | |
2050 | */ | |
2051 | static void irq_udc_suspend(struct pxa_udc *udc) | |
2052 | { | |
2053 | udc_writel(udc, UDCISR1, UDCISR1_IRSU); | |
2054 | udc->stats.irqs_suspend++; | |
2055 | ||
2056 | if (udc->gadget.speed != USB_SPEED_UNKNOWN | |
2057 | && udc->driver && udc->driver->suspend) | |
2058 | udc->driver->suspend(&udc->gadget); | |
2059 | ep0_idle(udc); | |
2060 | } | |
2061 | ||
2062 | /** | |
2063 | * irq_udc_resume - Handle IRQ "UDC Resume" | |
2064 | * @udc: udc device | |
2065 | */ | |
2066 | static void irq_udc_resume(struct pxa_udc *udc) | |
2067 | { | |
2068 | udc_writel(udc, UDCISR1, UDCISR1_IRRU); | |
2069 | udc->stats.irqs_resume++; | |
2070 | ||
2071 | if (udc->gadget.speed != USB_SPEED_UNKNOWN | |
2072 | && udc->driver && udc->driver->resume) | |
2073 | udc->driver->resume(&udc->gadget); | |
2074 | } | |
2075 | ||
2076 | /** | |
2077 | * irq_udc_reconfig - Handle IRQ "UDC Change Configuration" | |
2078 | * @udc: udc device | |
2079 | */ | |
2080 | static void irq_udc_reconfig(struct pxa_udc *udc) | |
2081 | { | |
2082 | unsigned config, interface, alternate, config_change; | |
2083 | u32 udccr = udc_readl(udc, UDCCR); | |
2084 | ||
2085 | udc_writel(udc, UDCISR1, UDCISR1_IRCC); | |
2086 | udc->stats.irqs_reconfig++; | |
2087 | ||
2088 | config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S; | |
2089 | config_change = (config != udc->config); | |
2090 | pxa27x_change_configuration(udc, config); | |
2091 | ||
2092 | interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S; | |
2093 | alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S; | |
2094 | pxa27x_change_interface(udc, interface, alternate); | |
2095 | ||
2096 | if (config_change) | |
2097 | update_pxa_ep_matches(udc); | |
2098 | udc_set_mask_UDCCR(udc, UDCCR_SMAC); | |
2099 | } | |
2100 | ||
2101 | /** | |
2102 | * irq_udc_reset - Handle IRQ "UDC Reset" | |
2103 | * @udc: udc device | |
2104 | */ | |
2105 | static void irq_udc_reset(struct pxa_udc *udc) | |
2106 | { | |
2107 | u32 udccr = udc_readl(udc, UDCCR); | |
2108 | struct pxa_ep *ep = &udc->pxa_ep[0]; | |
2109 | ||
2110 | dev_info(udc->dev, "USB reset\n"); | |
2111 | udc_writel(udc, UDCISR1, UDCISR1_IRRS); | |
2112 | udc->stats.irqs_reset++; | |
2113 | ||
2114 | if ((udccr & UDCCR_UDA) == 0) { | |
2115 | dev_dbg(udc->dev, "USB reset start\n"); | |
2116 | stop_activity(udc, udc->driver); | |
2117 | } | |
2118 | udc->gadget.speed = USB_SPEED_FULL; | |
2119 | memset(&udc->stats, 0, sizeof udc->stats); | |
2120 | ||
2121 | nuke(ep, -EPROTO); | |
2122 | udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC); | |
2123 | ep0_idle(udc); | |
2124 | } | |
2125 | ||
2126 | /** | |
2127 | * pxa_udc_irq - Main irq handler | |
2128 | * @irq: irq number | |
2129 | * @_dev: udc device | |
2130 | * | |
2131 | * Handles all udc interrupts | |
2132 | */ | |
2133 | static irqreturn_t pxa_udc_irq(int irq, void *_dev) | |
2134 | { | |
2135 | struct pxa_udc *udc = _dev; | |
2136 | u32 udcisr0 = udc_readl(udc, UDCISR0); | |
2137 | u32 udcisr1 = udc_readl(udc, UDCISR1); | |
2138 | u32 udccr = udc_readl(udc, UDCCR); | |
2139 | u32 udcisr1_spec; | |
2140 | ||
2141 | dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, " | |
2142 | "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr); | |
2143 | ||
2144 | udcisr1_spec = udcisr1 & 0xf8000000; | |
2145 | if (unlikely(udcisr1_spec & UDCISR1_IRSU)) | |
2146 | irq_udc_suspend(udc); | |
2147 | if (unlikely(udcisr1_spec & UDCISR1_IRRU)) | |
2148 | irq_udc_resume(udc); | |
2149 | if (unlikely(udcisr1_spec & UDCISR1_IRCC)) | |
2150 | irq_udc_reconfig(udc); | |
2151 | if (unlikely(udcisr1_spec & UDCISR1_IRRS)) | |
2152 | irq_udc_reset(udc); | |
2153 | ||
2154 | if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK)) | |
2155 | irq_handle_data(irq, udc); | |
2156 | ||
2157 | return IRQ_HANDLED; | |
2158 | } | |
2159 | ||
2160 | static struct pxa_udc memory = { | |
2161 | .gadget = { | |
2162 | .ops = &pxa_udc_ops, | |
2163 | .ep0 = &memory.udc_usb_ep[0].usb_ep, | |
2164 | .name = driver_name, | |
2165 | .dev = { | |
2166 | .bus_id = "gadget", | |
2167 | }, | |
2168 | }, | |
2169 | ||
2170 | .udc_usb_ep = { | |
2171 | USB_EP_CTRL, | |
2172 | USB_EP_OUT_BULK(1), | |
2173 | USB_EP_IN_BULK(2), | |
2174 | USB_EP_IN_ISO(3), | |
2175 | USB_EP_OUT_ISO(4), | |
2176 | USB_EP_IN_INT(5), | |
2177 | }, | |
2178 | ||
2179 | .pxa_ep = { | |
2180 | PXA_EP_CTRL, | |
2181 | /* Endpoints for gadget zero */ | |
2182 | PXA_EP_OUT_BULK(1, 1, 3, 0, 0), | |
2183 | PXA_EP_IN_BULK(2, 2, 3, 0, 0), | |
2184 | /* Endpoints for ether gadget, file storage gadget */ | |
2185 | PXA_EP_OUT_BULK(3, 1, 1, 0, 0), | |
2186 | PXA_EP_IN_BULK(4, 2, 1, 0, 0), | |
2187 | PXA_EP_IN_ISO(5, 3, 1, 0, 0), | |
2188 | PXA_EP_OUT_ISO(6, 4, 1, 0, 0), | |
2189 | PXA_EP_IN_INT(7, 5, 1, 0, 0), | |
2190 | /* Endpoints for RNDIS, serial */ | |
2191 | PXA_EP_OUT_BULK(8, 1, 2, 0, 0), | |
2192 | PXA_EP_IN_BULK(9, 2, 2, 0, 0), | |
2193 | PXA_EP_IN_INT(10, 5, 2, 0, 0), | |
2194 | /* | |
2195 | * All the following endpoints are only for completion. They | |
2196 | * won't never work, as multiple interfaces are really broken on | |
2197 | * the pxa. | |
2198 | */ | |
2199 | PXA_EP_OUT_BULK(11, 1, 2, 1, 0), | |
2200 | PXA_EP_IN_BULK(12, 2, 2, 1, 0), | |
2201 | /* Endpoint for CDC Ether */ | |
2202 | PXA_EP_OUT_BULK(13, 1, 1, 1, 1), | |
2203 | PXA_EP_IN_BULK(14, 2, 1, 1, 1), | |
2204 | } | |
2205 | }; | |
2206 | ||
2207 | /** | |
2208 | * pxa_udc_probe - probes the udc device | |
2209 | * @_dev: platform device | |
2210 | * | |
2211 | * Perform basic init : allocates udc clock, creates sysfs files, requests | |
2212 | * irq. | |
2213 | */ | |
2214 | static int __init pxa_udc_probe(struct platform_device *pdev) | |
2215 | { | |
2216 | struct resource *regs; | |
2217 | struct pxa_udc *udc = &memory; | |
2218 | int retval; | |
2219 | ||
2220 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2221 | if (!regs) | |
2222 | return -ENXIO; | |
2223 | udc->irq = platform_get_irq(pdev, 0); | |
2224 | if (udc->irq < 0) | |
2225 | return udc->irq; | |
2226 | ||
2227 | udc->dev = &pdev->dev; | |
2228 | udc->mach = pdev->dev.platform_data; | |
2229 | ||
2230 | udc->clk = clk_get(&pdev->dev, "UDCCLK"); | |
2231 | if (IS_ERR(udc->clk)) { | |
2232 | retval = PTR_ERR(udc->clk); | |
2233 | goto err_clk; | |
2234 | } | |
2235 | ||
2236 | retval = -ENOMEM; | |
2237 | udc->regs = ioremap(regs->start, regs->end - regs->start + 1); | |
2238 | if (!udc->regs) { | |
2239 | dev_err(&pdev->dev, "Unable to map UDC I/O memory\n"); | |
2240 | goto err_map; | |
2241 | } | |
2242 | ||
2243 | device_initialize(&udc->gadget.dev); | |
2244 | udc->gadget.dev.parent = &pdev->dev; | |
2245 | udc->gadget.dev.dma_mask = NULL; | |
2246 | ||
2247 | the_controller = udc; | |
2248 | platform_set_drvdata(pdev, udc); | |
2249 | udc_init_data(udc); | |
2250 | pxa_eps_setup(udc); | |
2251 | ||
2252 | /* irq setup after old hardware state is cleaned up */ | |
2253 | retval = request_irq(udc->irq, pxa_udc_irq, | |
2254 | IRQF_SHARED, driver_name, udc); | |
2255 | if (retval != 0) { | |
2256 | dev_err(udc->dev, "%s: can't get irq %i, err %d\n", | |
2257 | driver_name, IRQ_USB, retval); | |
2258 | goto err_irq; | |
2259 | } | |
2260 | ||
2261 | pxa_init_debugfs(udc); | |
2262 | return 0; | |
2263 | err_irq: | |
2264 | iounmap(udc->regs); | |
2265 | err_map: | |
2266 | clk_put(udc->clk); | |
2267 | udc->clk = NULL; | |
2268 | err_clk: | |
2269 | return retval; | |
2270 | } | |
2271 | ||
2272 | /** | |
2273 | * pxa_udc_remove - removes the udc device driver | |
2274 | * @_dev: platform device | |
2275 | */ | |
2276 | static int __exit pxa_udc_remove(struct platform_device *_dev) | |
2277 | { | |
2278 | struct pxa_udc *udc = platform_get_drvdata(_dev); | |
2279 | ||
2280 | usb_gadget_unregister_driver(udc->driver); | |
2281 | free_irq(udc->irq, udc); | |
2282 | pxa_cleanup_debugfs(udc); | |
2283 | ||
2284 | platform_set_drvdata(_dev, NULL); | |
2285 | the_controller = NULL; | |
2286 | clk_put(udc->clk); | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
2291 | static void pxa_udc_shutdown(struct platform_device *_dev) | |
2292 | { | |
2293 | struct pxa_udc *udc = platform_get_drvdata(_dev); | |
2294 | ||
5a59bc54 RJ |
2295 | if (udc_readl(udc, UDCCR) & UDCCR_UDE) |
2296 | udc_disable(udc); | |
d75379a5 RJ |
2297 | } |
2298 | ||
2299 | #ifdef CONFIG_PM | |
2300 | /** | |
2301 | * pxa_udc_suspend - Suspend udc device | |
2302 | * @_dev: platform device | |
2303 | * @state: suspend state | |
2304 | * | |
2305 | * Suspends udc : saves configuration registers (UDCCR*), then disables the udc | |
2306 | * device. | |
2307 | */ | |
2308 | static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) | |
2309 | { | |
2310 | int i; | |
2311 | struct pxa_udc *udc = platform_get_drvdata(_dev); | |
2312 | struct pxa_ep *ep; | |
2313 | ||
2314 | ep = &udc->pxa_ep[0]; | |
2315 | udc->udccsr0 = udc_ep_readl(ep, UDCCSR); | |
2316 | for (i = 1; i < NR_PXA_ENDPOINTS; i++) { | |
2317 | ep = &udc->pxa_ep[i]; | |
2318 | ep->udccsr_value = udc_ep_readl(ep, UDCCSR); | |
2319 | ep->udccr_value = udc_ep_readl(ep, UDCCR); | |
2320 | ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", | |
2321 | ep->udccsr_value, ep->udccr_value); | |
2322 | } | |
2323 | ||
2324 | udc_disable(udc); | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
2329 | /** | |
2330 | * pxa_udc_resume - Resume udc device | |
2331 | * @_dev: platform device | |
2332 | * | |
2333 | * Resumes udc : restores configuration registers (UDCCR*), then enables the udc | |
2334 | * device. | |
2335 | */ | |
2336 | static int pxa_udc_resume(struct platform_device *_dev) | |
2337 | { | |
2338 | int i; | |
2339 | struct pxa_udc *udc = platform_get_drvdata(_dev); | |
2340 | struct pxa_ep *ep; | |
2341 | ||
2342 | ep = &udc->pxa_ep[0]; | |
2343 | udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME)); | |
2344 | for (i = 1; i < NR_PXA_ENDPOINTS; i++) { | |
2345 | ep = &udc->pxa_ep[i]; | |
2346 | udc_ep_writel(ep, UDCCSR, ep->udccsr_value); | |
2347 | udc_ep_writel(ep, UDCCR, ep->udccr_value); | |
2348 | ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", | |
2349 | ep->udccsr_value, ep->udccr_value); | |
2350 | } | |
2351 | ||
2352 | udc_enable(udc); | |
2353 | /* | |
2354 | * We do not handle OTG yet. | |
2355 | * | |
2356 | * OTGPH bit is set when sleep mode is entered. | |
2357 | * it indicates that OTG pad is retaining its state. | |
2358 | * Upon exit from sleep mode and before clearing OTGPH, | |
2359 | * Software must configure the USB OTG pad, UDC, and UHC | |
2360 | * to the state they were in before entering sleep mode. | |
d75379a5 | 2361 | */ |
5a59bc54 | 2362 | PSSR |= PSSR_OTGPH; |
d75379a5 RJ |
2363 | |
2364 | return 0; | |
2365 | } | |
2366 | #endif | |
2367 | ||
2368 | /* work with hotplug and coldplug */ | |
2369 | MODULE_ALIAS("platform:pxa2xx-udc"); | |
2370 | ||
2371 | static struct platform_driver udc_driver = { | |
2372 | .driver = { | |
2373 | .name = "pxa2xx-udc", | |
2374 | .owner = THIS_MODULE, | |
2375 | }, | |
2376 | .remove = __exit_p(pxa_udc_remove), | |
2377 | .shutdown = pxa_udc_shutdown, | |
2378 | #ifdef CONFIG_PM | |
2379 | .suspend = pxa_udc_suspend, | |
2380 | .resume = pxa_udc_resume | |
2381 | #endif | |
2382 | }; | |
2383 | ||
2384 | static int __init udc_init(void) | |
2385 | { | |
5a59bc54 RJ |
2386 | if (!cpu_is_pxa27x()) |
2387 | return -ENODEV; | |
2388 | ||
d75379a5 RJ |
2389 | printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); |
2390 | return platform_driver_probe(&udc_driver, pxa_udc_probe); | |
2391 | } | |
2392 | module_init(udc_init); | |
2393 | ||
2394 | ||
2395 | static void __exit udc_exit(void) | |
2396 | { | |
2397 | platform_driver_unregister(&udc_driver); | |
2398 | } | |
2399 | module_exit(udc_exit); | |
2400 | ||
2401 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2402 | MODULE_AUTHOR("Robert Jarzmik"); | |
2403 | MODULE_LICENSE("GPL"); |